diff --git a/Platform/AMD/AgesaModulePkg/AgesaCommonModulePkg.dec b/Platform/AMD/AgesaModulePkg/AgesaCommonModulePkg.dec index d35a1f27b4a54a6c079d7d1c68909b06e977bba1..d97aefa62aeb53f14d07071dd78468e741659a85 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaCommonModulePkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaCommonModulePkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) Common Module Package DEC -# file. -# This file provides the minimum AMD SoC/Mircoporcessor definitions for building -# AMD edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaEdk2Pkg.dec b/Platform/AMD/AgesaModulePkg/AgesaEdk2Pkg.dec index 16370684325a2801af93e9b5bcaf36b29dc97244..256940132a9957f23731e187c0368d22e1d7be74 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaEdk2Pkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaEdk2Pkg.dec @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,5 +14,3 @@ [Includes] Include/AmdEdk2 - - diff --git a/Platform/AMD/AgesaModulePkg/AgesaEdk2PlatformPkg.inc.dsc b/Platform/AMD/AgesaModulePkg/AgesaEdk2PlatformPkg.inc.dsc index 37b8d15cb17cc2e14bae89e8bff074639daef578..bf01a8e4709d045429c9ac55455325a30ca17651 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaEdk2PlatformPkg.inc.dsc +++ b/Platform/AMD/AgesaModulePkg/AgesaEdk2PlatformPkg.inc.dsc @@ -2,8 +2,8 @@ # # The DSC include file for edk2 package to pull in the necessary AGESA modules # into build process. -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaModuleCcxPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModuleCcxPkg.dec index b84fe5b7383b7a855690538f95bf535feaae8b9c..9c9fd3be643a84c57e71631a4b26e02d5c4d508a 100755 --- a/Platform/AMD/AgesaModulePkg/AgesaModuleCcxPkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaModuleCcxPkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) FCH Module Package DEC -# file. -# This file provides the minimum AMD Core Complex package definitions for building AMD -# edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaModuleDfPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModuleDfPkg.dec index 57db15e663ce6c1b95f92154d1a9a02e03896048..8f6d88e20120f288839dce944dd926d9c0b5b715 100755 --- a/Platform/AMD/AgesaModulePkg/AgesaModuleDfPkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaModuleDfPkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) FCH Module Package DEC -# file. -# This file provides the minimum AMD Data Fabric package definitions for building AMD -# edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaModuleFchPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModuleFchPkg.dec index 521957e809a392c1b7901fa88c7da8a2f7b8563f..71027fd9b4da631dfe27fb9edc5583264b49aa8d 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaModuleFchPkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaModuleFchPkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) FCH Module Package DEC -# file. -# This file provides the minimum AMD Fusion Control Hub package definitions for building AMD -# edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaModuleMemPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModuleMemPkg.dec index 721d3ea73b9e89263cef481e5ffefad1ac6626c3..40dbe76ab17981e97916ba00b2806235d4bfd99d 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaModuleMemPkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaModuleMemPkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) NBIO Module Package DEC -# file. -# This file provides the minimum AMD Memory package definitions for building AMD -# edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -21,6 +17,3 @@ [PcdsFixedAtBuild] gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemCfgMaxPostPackageRepairEntries|64|UINT32|0x00029001 - - - diff --git a/Platform/AMD/AgesaModulePkg/AgesaModuleNbioPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModuleNbioPkg.dec index 0501774c9b0c8a144ef2e0c4ca656eaba733c3d0..9536b0b41e0bec3df31300ac240df5357e08abc9 100755 --- a/Platform/AMD/AgesaModulePkg/AgesaModuleNbioPkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaModuleNbioPkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) NBIO Module Package DEC -# file. -# This file provides the minimum AMD North Bridge I/O package definitions for building AMD -# edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaModulePspPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModulePspPkg.dec index 41cf320c76797a746ed7349b1c997154519bf6b2..3efc87fb0eed180e0eab9c97406157f44f38f7b4 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaModulePspPkg.dec +++ b/Platform/AMD/AgesaModulePkg/AgesaModulePspPkg.dec @@ -1,10 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) NBIO Module Package DEC -# file. -# This file provides the minimum AMD Platform Security Processor package definitions -# for building AMD edk2 modules. # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaModuleRasPkg.dec b/Platform/AMD/AgesaModulePkg/AgesaModuleRasPkg.dec new file mode 100644 index 0000000000000000000000000000000000000000..8d79f533af83e1278a8b4d9e5716bbe35f99c874 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/AgesaModuleRasPkg.dec @@ -0,0 +1,20 @@ +## @file +# +# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = AgesaRasPkg + PACKAGE_GUID = B517CFC7-446E-A818-5FB9-C985575EA47B + PACKAGE_VERSION = 0.2 + +[Includes] + Include/ + Include/Library/ + +[Protocols] + gAmdRasInitDataProtocolGuid = {0x3C6ED57C, 0x4F6A, 0x8A58, {0x85, 0xDF, 0xDC, 0xA5, 0xAD, 0xF0, 0xF1, 0x6B}} diff --git a/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.dxe.inc.fdf b/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..7c94de85906ae8dfc61a94ca45a6e7d0db919216 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.dxe.inc.fdf @@ -0,0 +1,10 @@ +## @file +# +# Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + INF AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.inf + diff --git a/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.inc.dsc b/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..2e4910831622f85f825df5c48355e77ab2691101 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.inc.dsc @@ -0,0 +1,48 @@ +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses.common.SEC] + +[LibraryClasses.Common.PEIM] + ## APCB + ApcbLibV3Pei|AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.inf + +[LibraryClasses.Common.DXE_DRIVER] + AmdPspRomArmorLib|AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf + ApcbLibV3|AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.inf + +[LibraryClasses.Common.DXE_SMM_DRIVER] + AmdPspRomArmorLib|AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf + ApcbLibV3|AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.inf + +[LibraryClasses] + # + # Agesa specific common libraries + # + + ## PSP Libs + AmdPspBaseLibV2|AgesaModulePkg/Library/AmdPspBaseLibV2/AmdPspBaseLibV2.inf + AmdPspMboxLibV2|AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.inf + + ## DF Lib + BaseFabricTopologyLib|AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.inf + + ## Fch Lib + FchBaseLib|AgesaModulePkg/Library/FchBaseLib/FchBaseLib.inf + + NbioHandleLib|AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.inf + PcieConfigLib|AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf + SmnAccessLib|AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.inf + NbioCommonDxeLib|AgesaModulePkg/Nbio/Library/CommonDxe/NbioCommonDxeLib.inf + +[Components.IA32] + AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.inf + +[Components.X64] + AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.inf + diff --git a/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.pei.inc.fdf b/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..f68e8a27d885d0f4d4552c8a3834687fce2f3002 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/AgesaSp5BrhModulePkg.pei.inc.fdf @@ -0,0 +1,9 @@ +## @file +# +# Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + INF AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.inf diff --git a/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf b/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf index 9303d1fac4418333c46d2c627bc2275e35ee7e8a..476a21f662b3730ab7fedcc178174002b4bcf527 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf +++ b/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf @@ -1,7 +1,7 @@ ## @file # The AGESA DXE FDF file for building AMD SP5 Genoa boards. # -# Copyright (C) 2021-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc b/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc index e7e05fd2d80624586252ee6f728d708ebc937e38..a5cf26b03f9cbd57ca313f0467c67de4b3a1d9ed 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc +++ b/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc @@ -1,7 +1,7 @@ ## @file # The AGESA DSC file for building AMD SP5 Genoa boards. # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf b/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf index 0ef5a2a8062edcc94fe57193a674d4ab50599194..72aa5c5754cb7c943efec93bff94d8aa5669535a 100644 --- a/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf +++ b/Platform/AMD/AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf @@ -1,7 +1,7 @@ ## @file # The AGESA PEI FDF file for building AMD SP5 Genoa boards. # -# Copyright (C) 2021-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi b/Platform/AMD/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi new file mode 100644 index 0000000000000000000000000000000000000000..35ebc4322c8c789424fceb71086474a8d9777230 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi @@ -0,0 +1,1115 @@ +/** @file + + Fch Return I2C I3C Interrupt + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB) { + +Name (TSOS, 0x75) + +If(CondRefOf(\_OSI)) +{ + If(\_OSI("Windows 2009")) + { + Store(0x50, TSOS) + } + If(\_OSI("Windows 2015")) + { + Store(0x70, TSOS) + } +} + +OperationRegion(ECMC, SystemIo, 0x72, 0x02) +Field(ECMC, AnyAcc, NoLock, Preserve) +{ + ECMI, 8, + ECMD, 8, +} +IndexField(ECMI, ECMD, ByteAcc, NoLock, Preserve) { + Offset (0x08), + FRTB, 32, +} +OperationRegion(FRTP, SystemMemory, FRTB, 0x100) +Field(FRTP, AnyAcc, NoLock, Preserve) +{ + PEBA, 64, + Offset (0x08), + , 4, + LPCE, 1, //LPC , 4 + IC0E, 1, //I2C0, 5 + IC1E, 1, //I2C1, 6 + IC2E, 1, //I2C2, 7 + IC3E, 1, //I2C3, 8 + IC4E, 1, //I2C3, 9 + IC5E, 1, //I2C3, 10 + UT0E, 1, //UART0, 11 + UT1E, 1, //UART1, 12 + I31E, 1, //I3C1 13 + I32E, 1, //I3C2, 14 + I33E, 1, //I3C3, 15 + UT2E, 1, //UART2, 16 + , 1, + EMMD, 2, //18-19, EMMC Driver type, 0:AMD eMMC Driver (AMDI0040) 1:MS SD Driver (PNP0D40) 2:0:MS eMMC Driver (AMDI0040) + , 1, //UART4, 20 + I30E, 1, //I3C0, 21 + , 1, + XHCE, 1, //XCHI, 23 + , 1, //24 + , 1, + UT3E, 1, //UART3, 26 + ESPI, 1, //ESPI 27 + EMME, 1, //EMMC 28 + Offset (0x0C), + PCEF, 1, // Post Code Enable Flag + , 4, + IC0D, 1, //I2C0, 5 + IC1D, 1, + IC2D, 1, + IC3D, 1, //I2C3, 8 + IC4D, 1, //I2C3, 9 + IC5D, 1, //I2C3, 10 + UT0D, 1, //UART0, 11 + UT1D, 1, //UART1, 12 + , 1, //, 13 + , 1, //, 14 + ST_D, 1, //SATA, 15 + UT2D, 1, //UART2, 16 + , 1, + EHCD, 1, //EHCI, 18 + , 4, + XHCD, 1, //XCHI, 23 + SD_D, 1, //SD, 24 + , 1, + UT3D, 1, //UART1, 26 + , 1, + EMD3, 1, //EMMC D3 28 + , 2, + S03D, 1, //S0I3 flag, 31 + Offset (0x10), + FW00, 16, + FW01, 32, + FW02, 16, + FW03, 32, + SDS0, 8, //SataDevSlpPort0S5Pin + SDS1, 8, //SataDevSlpPort1S5Pin + Offset (0x2A), + I30M, 1, //I3C 0 Mode + I31M, 1, //I3C 1 Mode + I32M, 1, //I3C 2 Mode + I33M, 1, //I3C 3 Mode + Offset (0x2E), + UT0I, 1, // UART0 Invisible 0 + UT1I, 1, // UART1 Invisible 1 + UT2I, 1, // UART2 Invisible 2 + UT3I, 1, // UART3 Invisible 3 + UT4I, 1, // UART4 Invisible 4 + , 3, + UL0I, 1, // UART0 Legacy IO Invisible 8 + UL1I, 1, // UART1 Legacy IO Invisible 9 + UL2I, 1, // UART2 Legacy IO Invisible 10 + UL3I, 1, // UART3 Legacy IO Invisible 11 + Offset (0x30), + I20I, 1, // I2C0 Invisidble 0 + I21I, 1, // I2C1 Invisidble 1 + I22I, 1, // I2C2 Invisidble 2 + I23I, 1, // I2C3 Invisidble 3 + I24I, 1, // I2C4 Invisidble 4 + I25I, 1, // I2C5 Invisidble 5 + I30I, 1, // I3C0 Invisidble 6 + I31I, 1, // I3C1 Invisidble 7 + I32I, 1, // I3C2 Invisidble 8 + I33I, 1, // I3C3 Invisidble 9 + Offset (0x32), + IDPC, 8, // Identify Dimms per channel - Offset (0x32) +} +OperationRegion(FCFG, SystemMemory, PEBA, 0x01000000) +Field(FCFG, DwordAcc, NoLock, Preserve) +{ + Offset(0x000A3044), + IPDE, 32, //IO Port Decode Enable + Offset(0x000A3048), + IMPE, 32, //IO Memory Port decode Enable + Offset(0x000A3078), + , 2, + LDQ0, 1, // + Offset(0x000A30CB), + , 7, + AUSS, 1, //AutoSizeStart +} +OperationRegion(IOMX, SystemMemory, 0xFED80D00, 0x100) +Field(IOMX, AnyAcc, NoLock, Preserve) +{ + Offset (0x15), + IM15, 8, // + Offset (0x16), + IM16, 8, // + Offset (0x1F), + IM1F, 8, // + Offset (0x20), + IM20, 8, // + Offset (0x44), + IM44, 8, // + Offset (0x46), + IM46, 8, // + Offset (0x4A), + IM4A, 8, // + Offset (0x4B), + IM4B, 8, // + Offset (0x57), + IM57, 8, // + Offset (0x58), + IM58, 8, // + Offset (0x68), + IM68, 8, // + Offset (0x69), + IM69, 8, // + Offset (0x6A), + IM6A, 8, // + Offset (0x6B), + IM6B, 8, // + Offset (0x6D), + IM6D, 8, // +} +OperationRegion(FACR, SystemMemory, 0xFED81E00, 0x100) //Fch AoaC Register +Field(FACR, AnyAcc, NoLock, Preserve) +{ + Offset (0x80), + ,28, + RD28, 1, //Request of Device 28, MAP + , 1, + RQTY, 1, //ReQuestTYpe + Offset (0x84), + ,28, + SD28, 1, //Status of Device 28, MAP + , 1, + Offset (0xA0), //AOACx0000A0 [PwrGood Control] (PwrGoodCtl) + PG1A, 1, +} + + +OperationRegion(LUIE, SystemMemory, 0xFEDC0020, 0x4) //Legacy Uart Io Enable +Field(LUIE, AnyAcc, NoLock, Preserve) +{ + IER0, 1, //2E8 + IER1, 1, //2F8 + IER2, 1, //3E8 + IER3, 1, //3F8 + RESV, 4, //Reserved + WUR0, 2, // 0=Uart0, 1=Uart1, 2=Uart2, 3=Uart3 + WUR1, 2, // + WUR2, 2, // + WUR3, 2, // +} + +// Fch Return I2C/I3C Interrupt +Method (FRII, 1, Serialized) { + if (LEqual (Arg0, 0)) { + return (IIC0) + } elseif (LEqual (Arg0, 1)) { + return (IIC1) + } elseif (LEqual (Arg0, 2)) { + return (IIC2) + } elseif (LEqual (Arg0, 3)) { + return (IIC3) + } elseif (LEqual (Arg0, 4)) { + return (IIC4) + } elseif (LEqual (Arg0, 5)) { + return (IIC5) + } else { + // Return IRQ10 should never be run, it avoids ASL compiler warning. + return (10) + } +} // End of Method (FRII, 1, Serialized) + +// Fch Return Uart Interrupt +Method (FRUI, 1, Serialized) { + if (LEqual (Arg0, 0)) { + return (IUA0) + } elseif (LEqual (Arg0, 1)) { + return (IUA1) + } elseif (LEqual (Arg0, 2)) { + return (IUA2) + } elseif (LEqual (Arg0, 3)) { + return (IUA3) + } else { + // Return IRQ3 should never be run, it avoids ASL compiler warning. + return (3) + } +} // End of Method (FRUI + +Method(SRAD,2, Serialized) //SoftResetAoacDevice, Arg0:Device ID, Arg1:reset period in micro seconds +{ + ShiftLeft(Arg0, 1, Local0) + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + store (one, ADIS) // IsSwControl = 1 + store (zero, ADSR) // SwRstB = 0 + stall (Arg1) + store (one, ADSR) // SwRstB = 1 + store (zero, ADIS) // IsSwControl = 0 + stall (Arg1) +} +Method(DSAD,2, Serialized) //DxSequenceAoacDevice, Arg0:Device ID, Arg1:3=D3, 0=D0 +{ + ShiftLeft(Arg0, 1, Local0) + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + if (LNotEqual(Arg0, ADTD)) { + if (LEqual(Arg1, 0)) { + //D0 + store(0x00, ADTD) + store(one, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x7)) {store(ADDS, Local0)} + } + if (LEqual(Arg1, 3)) { + //D3 + store(zero, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x0)) {store(ADDS, Local0)} + store(0x03, ADTD) + } + } +} +Method(HSAD,2, Serialized) //Hardware dx Sequence Aoac Device, Arg0:Device ID, Arg1:3=D3, 0=D0 +{ + //ShiftLeft(1, Arg0, Local3) //caculate bit map location + ShiftLeft(Arg0, 1, Local0) //Caculate device register location + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + if (LNotEqual(Arg1, ADTD)) { + if (LEqual(Arg1, 0)) { + store (One, PG1A) //power up + //D0 + store(0x00, ADTD) + store(one, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x7)) {store(ADDS, Local0)} + //Do hareware restore now + // Set RequestType to restore + store (one, RQTY) + store (one, RD28) + // Wait for restore complete + store (SD28, Local0) + while (LNot(Local0)) {store (SD28, Local0)} + } + if (LEqual(Arg1, 3)) { + //Do hareware save first + store (zero, RQTY) + store (one, RD28) + store (SD28, Local0) + while (Local0) {store (SD28, Local0)} + //D3 + store(zero, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x0)) {store(ADDS, Local0)} + store(0x03, ADTD) + store (Zero, PG1A) //power down + } + } +} +OperationRegion(FPIC, SystemIo, 0xc00, 0x02)//Fch Pci Interrupt Connector +Field(FPIC, AnyAcc, NoLock, Preserve) +{ + FPII, 8, + FPID, 8, +} +IndexField(FPII, FPID, ByteAcc, NoLock, Preserve) { + Offset (0xF0), //Interrupt for I2C/I3C/UART + IIC0, 8, + IIC1, 8, + IIC2, 8, + IIC3, 8, + IUA0, 8, + IUA1, 8, + IIC4, 8, + IIC5, 8, + IUA2, 8, + IUA3, 8, +} + +Method(CKUL,1, Serialized) +{ + //Check if legacy UART is enabled. Return 1: enabled, 0:no legacy UART enabled. + if (LAnd (LEqual (IER0, 1), LEqual (WUR0, Arg0))) {Return (1)} + elseif (LAnd (LEqual (IER1, 1), LEqual (WUR1, Arg0))) {Return (1)} + elseif (LAnd (LEqual (IER2, 1), LEqual (WUR2, Arg0))) {Return (1)} + elseif (LAnd (LEqual (IER3, 1), LEqual (WUR3, Arg0))) {Return (1)} + else {Return (0)} +} + + Device(GPIO) { + Name (_HID, "AMDI0030") + Name (_CID, "AMDI0030") + Name(_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // + // Interrupt resource. In this example, banks 0 & 1 share the same + // interrupt to the parent controller and similarly banks 2 & 3. + // + // N.B. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform + // + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + + // + // Memory resource. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform. + // + Memory32Fixed(ReadWrite, 0xFED81500, 0x400) + //for 11 remote GPIO ( GPIO256~GPIO266) + Memory32Fixed(ReadWrite, 0xFED81200, 0x2C) + }) + + Return (RBUF) + } + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } // End Device GPIO + + + Device(FUR0) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID00") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {3} + Memory32Fixed(ReadWrite, 0xFEDC9000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDC7000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA0, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT0E, one)) { + if (LEqual(CKUL(0), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT0I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR0 + + Device(FUR1) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID01") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {14} + Memory32Fixed(ReadWrite, 0xFEDCA000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDC8000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA1, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT1E, one)) { + if (LEqual(CKUL(1), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT1I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR1 + + Device(FUR2) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID02") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {5} + Memory32Fixed(ReadWrite, 0xFEDCE000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDCC000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA2, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT2E, one)) { + if (LEqual(CKUL(2), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT2I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR2 + + Device(FUR3) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID03") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {15} + Memory32Fixed(ReadWrite, 0xFEDCF000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDCD000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA3, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT3E, one)) { + if (LEqual(CKUL(3), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT3I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR3 + + Device(I2CA) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x0) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC0, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC0E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I20I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (5, 200)} + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, one) || LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CA + + Device(I2CB) + { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x1) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC1, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC1E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I21I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (6, 200)} + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, one) || LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CB + + Device(I2CC) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x2) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC2, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC2E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I22I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (7, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CC + + Device(I2CD) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x3) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC3, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC3E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I23I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + Method(RSET,0) { SRAD (8, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CD + + Device(I2CE) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x4) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {22} + Memory32Fixed(ReadWrite, 0xFEDC6000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC4, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC4E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I24I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (9, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + Return(Buffer(One){0x00}) + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CE + + Device(I2CF) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x5) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {23} + Memory32Fixed(ReadWrite, 0xFEDCB000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC5, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC5E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I25I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (10, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + Return(Buffer(One){0x00}) + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CF + + + Device(I3CA) { + Name(_UID,0x0) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDD2000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC0, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I30E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I30I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (21, 200)} + +} // End Device I3C0 + + + Device(I3CB) { + Name(_UID,0x1) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDD3000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC1, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I31E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I31I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (13, 200)} + +} // End Device I3C1 + + + Device(I3CC) { + Name(_UID,0x2) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDD4000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC2, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I32E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I32I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (14, 200)} + +} // End Device I3C2 + + + Device(I3CD) { + Name(_UID,0x3) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDD6000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC3, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I33E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I33I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (15, 200)} + +} // End Device I3C3 + + + +Device(UAR4) { // UART COM Port 0x2E8 + Name(_HID, EISAID("PNP0501")) + Name(_DDN, "COM4") + Name(_UID, 0x4) + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER0) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x2E8, 0x2E8, 0x01, 0x08) + IRQNoFlags() {3} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + // CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + // CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + // CreateByteField (BUF0, 0x04, IORL) // IO Port Low + // CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the IRQ descriptor word (bitwise). + // + ShiftLeft (One, And (FRUI (WUR0), 0x0F), IRQL) + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART1 + +Device(UAR2) { // COM Port 0x2F8 + Name(_HID, EISAID("PNP0501")) + Name(_DDN, "COM2") + Name(_UID, 0x2) + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER1) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08) + IRQNoFlags() {4} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + // CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + // CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + // CreateByteField (BUF0, 0x04, IORL) // IO Port Low + // CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the IRQ descriptor word (bitwise). + // + ShiftLeft (One, And (FRUI (WUR1), 0x0F), IRQL) + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART2 + +Device(UAR3) { // COM Port 0x3E8 + Name(_HID, EISAID("PNP0501")) + Name(_DDN, "COM3") + Name(_UID, 0x3) + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER2) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x3E8, 0x3E8, 0x01, 0x08) + IRQNoFlags() {3} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + // CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + // CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + // CreateByteField (BUF0, 0x04, IORL) // IO Port Low + // CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the IRQ descriptor word (bitwise). + // + ShiftLeft (One, And (FRUI (WUR2), 0x0F), IRQL) + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART3 + +Device(UAR1) { // COM Port 0x3F8 + Name(_HID, EISAID("PNP0501")) + Name(_DDN, "COM1") + Name(_UID, 0x1) + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER3) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08) + IRQNoFlags() {4} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + // CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + // CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + // CreateByteField (BUF0, 0x04, IORL) // IO Port Low + // CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the IRQ descriptor word (bitwise). + // + ShiftLeft (One, And (FRUI (WUR3), 0x0F), IRQL) + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART4 + +} // End of Scope(\_SB) + diff --git a/Platform/AMD/AgesaModulePkg/Fch/Songshan/FchSongshanDxe/FchSongshanI2C_I3C.asl b/Platform/AMD/AgesaModulePkg/Fch/Songshan/FchSongshanDxe/FchSongshanI2C_I3C.asl index 72b9a876393e0fffa0d6b5566c211c463a89ade4..719e47d4a24a1013872d4dcfe13a5351bcacf6c9 100644 --- a/Platform/AMD/AgesaModulePkg/Fch/Songshan/FchSongshanDxe/FchSongshanI2C_I3C.asl +++ b/Platform/AMD/AgesaModulePkg/Fch/Songshan/FchSongshanDxe/FchSongshanI2C_I3C.asl @@ -1,9 +1,9 @@ -/** @file - - Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - +/** @file + + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + diff --git a/Platform/AMD/AgesaModulePkg/Include/AGESA.h b/Platform/AMD/AgesaModulePkg/Include/AGESA.h index 3ec03aafd39cbe0b8736f9f4c815ec7cc9ee2edf..3ed500ffc2a2863843b75cac6d7f1d72a52d6fb9 100644 --- a/Platform/AMD/AgesaModulePkg/Include/AGESA.h +++ b/Platform/AMD/AgesaModulePkg/Include/AGESA.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/AMD.h b/Platform/AMD/AgesaModulePkg/Include/AMD.h index 062d9e1e1aabed305ccd77a9ff666010306b5773..1caa4a6be4de69f97c2714c55aea623f213982a6 100755 --- a/Platform/AMD/AgesaModulePkg/Include/AMD.h +++ b/Platform/AMD/AgesaModulePkg/Include/AMD.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/AmdEdk2/CpuRegisters.h b/Platform/AMD/AgesaModulePkg/Include/AmdEdk2/CpuRegisters.h index 534b03d4a755a9f32776bb6ef83489a0cae09448..6c8f3eac514067a456a3101bb28796fcd5ead92b 100755 --- a/Platform/AMD/AgesaModulePkg/Include/AmdEdk2/CpuRegisters.h +++ b/Platform/AMD/AgesaModulePkg/Include/AmdEdk2/CpuRegisters.h @@ -1,7 +1,6 @@ /** @file - AMD CPU Register Table Related Functions. - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/AmdPspDirectory.h b/Platform/AMD/AgesaModulePkg/Include/AmdPspDirectory.h index e086a4c9b184a8707244ea5f1c3327132464da30..1328cf45ee9c98b2fea7d033960a5836d4dae83d 100644 --- a/Platform/AMD/AgesaModulePkg/Include/AmdPspDirectory.h +++ b/Platform/AMD/AgesaModulePkg/Include/AmdPspDirectory.h @@ -1,7 +1,7 @@ /** @file AMD Psp Directory header file - Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/CpuRegistersDef.h b/Platform/AMD/AgesaModulePkg/Include/CpuRegistersDef.h index faa8d35b1b1210fa993a1be046db992f83706e37..dd7052004a23f382edf98a76862018a6cc183569 100755 --- a/Platform/AMD/AgesaModulePkg/Include/CpuRegistersDef.h +++ b/Platform/AMD/AgesaModulePkg/Include/CpuRegistersDef.h @@ -1,7 +1,6 @@ /** @file - AMD CPU Register Table Related Definitions. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/FchRegistersCommon.h b/Platform/AMD/AgesaModulePkg/Include/FchRegistersCommon.h index 8ede1be83881453a4b866579ac0296a93806fa98..5b65f48a1edb6aaa297735e7810e2ab4604df9f2 100644 --- a/Platform/AMD/AgesaModulePkg/Include/FchRegistersCommon.h +++ b/Platform/AMD/AgesaModulePkg/Include/FchRegistersCommon.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -75,7 +75,7 @@ #define FCH_SPI_R2MSK25 0x00000008l // #define FCH_SPI_MMIO_REG45_CMDCODE 0x45 // #define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 // -#define FCH_SPI_MMIO_REG48_TXBYTECOUNT 0x48 // +#define FCH_SPI_MMIO_REG48_TX_BYTECOUNT 0x48 // #define FCH_SPI_MMIO_REG4B_RXBYTECOUNT 0x4B // #define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C // #define FCH_SPI_MMIO_REG5C_Addr32_Ctrl3 0x5C // diff --git a/Platform/AMD/AgesaModulePkg/Include/Filecode.h b/Platform/AMD/AgesaModulePkg/Include/Filecode.h index 726479d79f5104f8fa7f9604b82121f4c1c11178..74ee5f3d190f5d06ca6e2b77a03546b4c3d70387 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Filecode.h +++ b/Platform/AMD/AgesaModulePkg/Include/Filecode.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -23,9 +23,9 @@ * @e _$Revision: 312538 $ @e \$Date: 2015-02-09 16:53:54 +0800 (Mon, 09 Feb 2015) $ */ -#ifndef _FILECODE_H_ -#define _FILECODE_H_ +#ifndef FILECODE_H_ +#define FILECODE_H_ #define UNASSIGNED_FILE_FILECODE (0xFFFF) -#endif // _FILECODE_H_ +#endif // FILECODE_H_ diff --git a/Platform/AMD/AgesaModulePkg/Include/Gnb.h b/Platform/AMD/AgesaModulePkg/Include/Gnb.h index ddc9309d3d395153171c14615d3aa3338c3aa7d0..b330b3c359e4446d03c1bff8b98533d2316dc2ac 100755 --- a/Platform/AMD/AgesaModulePkg/Include/Gnb.h +++ b/Platform/AMD/AgesaModulePkg/Include/Gnb.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/GnbDxio.h b/Platform/AMD/AgesaModulePkg/Include/GnbDxio.h index 192e0d6a8bfc6d95d5d6df0129c96d009bb1197a..8928347ddad11cf2bb85b6e552b0bc5a5620398d 100644 --- a/Platform/AMD/AgesaModulePkg/Include/GnbDxio.h +++ b/Platform/AMD/AgesaModulePkg/Include/GnbDxio.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -34,6 +34,8 @@ #define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM) #define PcieLibGetNextDescriptor(Descriptor) ((Descriptor == NULL) ? NULL : ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor + 1)) +#define SILICON_CXL_CAPABLE 0x00008000ull + typedef UINT16 PCIE_ENGINE_INIT_STATUS; /// diff --git a/Platform/AMD/AgesaModulePkg/Include/GnbRegistersBRH.h b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersBRH.h new file mode 100644 index 0000000000000000000000000000000000000000..e34f24a7a8d879f888f659180d40b6180f91cf9d --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersBRH.h @@ -0,0 +1,18 @@ +/** @file + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef GNBREGISTERSBRH_H_ +#define GNBREGISTERSBRH_H_ + +#include "GnbRegistersBRH/IOHC.h" + +#ifndef NBIO_SPACE +#define NBIO_SPACE(HANDLE, ADDRESS) (ADDRESS + ((HANDLE->RBIndex & 0x3) << 20)) +#endif + +#endif /* GNBREGISTERSBRH_H_ */ diff --git a/Platform/AMD/AgesaModulePkg/Include/GnbRegistersBRH/IOHC.h b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersBRH/IOHC.h new file mode 100644 index 0000000000000000000000000000000000000000..d2368be9bda5d2911b2d2c59c219c82b9915670d --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersBRH/IOHC.h @@ -0,0 +1,22 @@ +/** @file + + Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef IOHC_H_ +#define IOHC_H_ + +#define DBG_BASE_ADDR_LO_DBG_MMIO_EN_OFFSET 0 + +#define DBG_BASE_ADDR_LO_DBG_MMIO_LOCK_OFFSET 1 + +#define SMN_IOHUB0NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS 0x13b102f0UL + +#define SMN_IOHUB0NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS 0x13b102f0UL +#define IOAPIC_BASE_ADDR_LO_IOAPIC_BASE_ADDR_LO_MASK 0xffffff00 +#define SMN_IOHUB1NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS 0x1d4102f0UL + +#endif /* IOHC_H_ */ diff --git a/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS.h b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS.h index 90f52cca7bc96317f47ebb603a0af7410f2fc02c..4c2a0bdc44d052eca212995bb2ea4315b2cb245f 100644 --- a/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS.h +++ b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS/IOHC.h b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS/IOHC.h index b1a95237decdf69dce68c7b7b05905d1d0831e3a..8dbed5769fc22a9779f31542756634baf47d5919 100644 --- a/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS/IOHC.h +++ b/Platform/AMD/AgesaModulePkg/Include/GnbRegistersRS/IOHC.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Guid/GnbPcieInfoHob.h b/Platform/AMD/AgesaModulePkg/Include/Guid/GnbPcieInfoHob.h index f5cc5e2228dcd4c3ebbdc166fff5bc37a10c8c18..6d8f6cb5a0eae9bff5c4bafb8ce08a689b61bd68 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Guid/GnbPcieInfoHob.h +++ b/Platform/AMD/AgesaModulePkg/Include/Guid/GnbPcieInfoHob.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/AmdBaseLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/AmdBaseLib.h index dc773737b9d306e9b85b29f1a0465d686e6ffc88..a25ac9c5bad0dc9762e67a594612ee65edc1df25 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/AmdBaseLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/AmdBaseLib.h @@ -1,7 +1,6 @@ /** @file - Contains interface to the AMD AGESA library. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/AmdPspMboxLibV2.h b/Platform/AMD/AgesaModulePkg/Include/Library/AmdPspMboxLibV2.h index 9d9892aa30425fb2ced7bf3763df091fa78c3519..0158108f1ab59ce0f006f82b37dfafefcc6c4ed5 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/AmdPspMboxLibV2.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/AmdPspMboxLibV2.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -19,8 +19,8 @@ * @e \$Revision: 312133 $ @e \$Date: 2015-02-03 02:47:45 +0800 (Tue, 03 Feb 2015) $ */ -#ifndef _PSP_MBOX_H_ -#define _PSP_MBOX_H_ +#ifndef PSP_MBOX_H_ +#define PSP_MBOX_H_ /** * @brief Bios send these commands to PSP to grant dTPM status and event log @@ -40,4 +40,4 @@ PspMboxGetDTPMData ( OUT VOID *LogData ); -#endif //_PSP_MBOX_H_ +#endif // PSP_MBOX_H_ diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/BaseFabricTopologyLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/BaseFabricTopologyLib.h index 51935f413aa25990e32d85636ef045fe49141167..ab321988b0b6a24145d9d81a2c8e1b1f3c11c97a 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/BaseFabricTopologyLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/BaseFabricTopologyLib.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -19,4 +19,18 @@ FabricTopologyGetNumberOfRootBridgesOnSocket ( IN UINTN Socket ); +UINTN +FabricTopologyGetHostBridgeBusBase ( + IN UINTN Socket, + IN UINTN Die, + IN UINTN Index + ); + +UINTN +FabricTopologyGetHostBridgeBusLimit ( + IN UINTN Socket, + IN UINTN Die, + IN UINTN Index + ); + #endif // BASE_FABRIC_TOPOLOGY_LIB_H_ diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/FchBaseLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/FchBaseLib.h index cae3aff9b39834e93c66537368d72297c529e12f..897c225df7f34f5f66419d0e00e21c6d6db9be62 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/FchBaseLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/FchBaseLib.h @@ -1,13 +1,13 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _FCH_BASE_LIB_H_ -#define _FCH_BASE_LIB_H_ +#ifndef FCH_BASE_LIB_H_ +#define FCH_BASE_LIB_H_ #include #include diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/FchEspiCmdLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/FchEspiCmdLib.h index 345e39adce3b97fd810be43d59c98726a901857b..cd0b85e90df78d296e12feed89cb1778ec14f764 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/FchEspiCmdLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/FchEspiCmdLib.h @@ -1,13 +1,13 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _FCH_ESPI_CMD_LIB_H_ -#define _FCH_ESPI_CMD_LIB_H_ +#ifndef FCH_ESPI_CMD_LIB_H_ +#define FCH_ESPI_CMD_LIB_H_ #include @@ -410,4 +410,4 @@ FchEspiCmd_SafsRpmcOp2 ( OUT UINT8 *Buffer ); -#endif +#endif // FCH_ESPI_CMD_LIB_H_ diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/GnbPcieConfigLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/GnbPcieConfigLib.h index 19688e25483ee3f8d8ad5a616ca26f42d6edeecd..3abe9f8a4f6479c14e4d0fef3c1e59fda8d6e0b1 100755 --- a/Platform/AMD/AgesaModulePkg/Include/Library/GnbPcieConfigLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/GnbPcieConfigLib.h @@ -1,7 +1,6 @@ /** @file - GNB PCIe Library definition. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/NbioCommonLibDxe.h b/Platform/AMD/AgesaModulePkg/Include/Library/NbioCommonLibDxe.h index df882745303e60be6be928129f2ac218d5d1a60a..14d3596cebfd8698da237e77c9bfd0150b483b8e 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/NbioCommonLibDxe.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/NbioCommonLibDxe.h @@ -1,7 +1,6 @@ /** @file - Header file of AMD NBIO Common DXE library. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/NbioHandleLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/NbioHandleLib.h index 4fec578a9f186b675b6cd5e70775f589c5a838f8..6b3aada1f3062b87141658d1e6324623ec246bcc 100755 --- a/Platform/AMD/AgesaModulePkg/Include/Library/NbioHandleLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/NbioHandleLib.h @@ -1,8 +1,6 @@ /** @file - GNB function to GetHostPciAddress and GetHandle. - Contain code that create/locate and rebase configuration data area. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/PcieConfigLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/PcieConfigLib.h index 9f5374681440840f4db3daa4737e054c34e78e6b..1ee27e7e949465a959a0a165cf734bdeff990cee 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/PcieConfigLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/PcieConfigLib.h @@ -1,7 +1,6 @@ /** @file - Helper functions to access PCIe configuration data area. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Library/SmnAccessLib.h b/Platform/AMD/AgesaModulePkg/Include/Library/SmnAccessLib.h index f0c6d1ccbb2c553e76f53ef7577a7f7787122b53..a58d0f663abb52bd353e6ea98574f9af9a09d461 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Library/SmnAccessLib.h +++ b/Platform/AMD/AgesaModulePkg/Include/Library/SmnAccessLib.h @@ -1,15 +1,16 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _SMNACCESSLIB_H_ -#define _SMNACCESSLIB_H_ +#ifndef SMNACCESSLIB_H_ +#define SMNACCESSLIB_H_ VOID +EFIAPI SmnRegisterReadS ( IN UINT32 SegmentNumber, IN UINT32 BusNumber, @@ -18,6 +19,7 @@ SmnRegisterReadS ( ); VOID +EFIAPI SmnRegisterRMWS ( IN UINT32 SegmentNumber, IN UINT32 BusNumber, @@ -27,4 +29,4 @@ SmnRegisterRMWS ( IN UINT32 Flags ); -#endif +#endif // SMNACCESSLIB_H_ diff --git a/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdNbioPcieServicesProtocol.h b/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdNbioPcieServicesProtocol.h index 0e08e64b248865e4f7cd62ed9258db6b52a34efb..57e98931eeb84e284fbea89a1506a2352e5467d4 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdNbioPcieServicesProtocol.h +++ b/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdNbioPcieServicesProtocol.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdOemOobPprProtocol.h b/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdOemOobPprProtocol.h index 10d3b730a6f13822ada658fe1353fb6ba8d0edd1..610f89b54608d63b49f05670879ab99d78ba0739 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdOemOobPprProtocol.h +++ b/Platform/AMD/AgesaModulePkg/Include/Protocol/AmdOemOobPprProtocol.h @@ -1,14 +1,14 @@ /** @file - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _AMD_OEM_OOB_PPR_PROTOCOL_H_ -#define _AMD_OEM_OOB_PPR_PROTOCOL_H_ +#ifndef AMD_OEM_OOB_PPR_PROTOCOL_H_ +#define AMD_OEM_OOB_PPR_PROTOCOL_H_ extern EFI_GUID gAmdOemOobPprDxeProtocolGuid; -#endif +#endif // AMD_OEM_OOB_PPR_PROTOCOL_H_ diff --git a/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricNumaServices2.h b/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricNumaServices2.h index a15995188b4698e98103ce22f0b29cebbe89a184..a16f4084e43405cada8e97fd8504e4cba4b62793 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricNumaServices2.h +++ b/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricNumaServices2.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricTopologyServices2.h b/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricTopologyServices2.h index 485240c0fb0330c3f6eff58e6a122108d50da89e..8c08cc60f4966b2f476d0bf9079022c4d84256b7 100644 --- a/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricTopologyServices2.h +++ b/Platform/AMD/AgesaModulePkg/Include/Protocol/FabricTopologyServices2.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Include/SocLogicalId.h b/Platform/AMD/AgesaModulePkg/Include/SocLogicalId.h index 44093e40970c5cebb933509f57d1104f5596061c..a81c3edb5389badd7fde9a7840d3bb3e6746522b 100755 --- a/Platform/AMD/AgesaModulePkg/Include/SocLogicalId.h +++ b/Platform/AMD/AgesaModulePkg/Include/SocLogicalId.h @@ -1,7 +1,6 @@ /** @file - SoC Logical ID Definitions. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf b/Platform/AMD/AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf index 8d3357bf56c3c1f92e1a7134849fe4eaa072f327..43606ad20bae91c7bbe398995bce09a711bca23a 100755 --- a/Platform/AMD/AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,7 +23,3 @@ [LibraryClasses] BaseLib PcdLib - - - - diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspBaseLibV2/AmdPspBaseLibV2.inf b/Platform/AMD/AgesaModulePkg/Library/AmdPspBaseLibV2/AmdPspBaseLibV2.inf new file mode 100644 index 0000000000000000000000000000000000000000..21da77402287768f9908f3071de9dee3e078c289 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspBaseLibV2/AmdPspBaseLibV2.inf @@ -0,0 +1,18 @@ +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = AmdPspBaseLibV2 + FILE_GUID = 3463D317-7619-4350-A7BB-64DA224D7DFD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = AmdPspBaseLibV2 + + + diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.c b/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.c index fa83888e95bee3d525b5a408a0911a33bd92c84f..ba53ff15da75ed5b1d6100a8c9abf6f5b09bbb21 100644 --- a/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.c +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.c @@ -1,7 +1,6 @@ /** @file - PSP Mailbox related functions - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.inf b/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.inf index 1594a99265a84bde4061c6cecf916b810a5b7678..ccb9fb2aacd3b7fda3befe659bbcc5130d9dd8cb 100644 --- a/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.inf +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.inf @@ -1,30 +1,27 @@ -## @file -# -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## -[Defines] - INF_VERSION = 0x00010006 - BASE_NAME = AmdPspMboxLibV2 - FILE_GUID = B9E57A31-CAB0-4CEE-9D50-9D43E2EEAA44 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = AmdPspMboxLibV2 - -[Sources.common] - AmdPspMboxLibV2.c - -[Packages] - MdePkg/MdePkg.dec - AgesaPkg/AgesaPkg.dec - AgesaModulePkg/AgesaCommonModulePkg.dec - AgesaModulePkg/AgesaModulePspPkg.dec - -[LibraryClasses] - PciLib - SmnAccessLib - - - +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = AmdPspMboxLibV2 + FILE_GUID = B9E57A31-CAB0-4CEE-9D50-9D43E2EEAA44 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = AmdPspMboxLibV2 + +[Sources.common] + AmdPspMboxLibV2.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModulePspPkg.dec + +[LibraryClasses] + PciLib + SmnAccessLib diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.c b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.c index 0e9baad955691b8f2f898044864593fa6b48ca40..65dde2e3d5865b392761f7b2db68310047f1eac9 100644 --- a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.inf b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.inf index c685a26604fc0be7679cf951d0c44cf0f14faf86..509c462459f0978200133722e4eed93ddafd0104 100644 --- a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLib/AmdPspRomArmorLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,3 @@ AgesaPkg/AgesaPkg.dec AgesaModulePkg/AgesaCommonModulePkg.dec AgesaModulePkg/AgesaModulePspPkg.dec - - - diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.c b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.c index a04bc1f9928ad8f73a4ade7307e9cd2ac0cda4ff..343e3794e89b1c1e4f535e38fb98f25873d049d0 100644 --- a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.c +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf index a3906dc13e8c98642d795ef4bbd1279fe5fbafca..e715c32c4d1c336b6eedcf1e95071dd127019863 100644 --- a/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf +++ b/Platform/AMD/AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,5 +22,3 @@ AgesaPkg/AgesaPkg.dec AgesaModulePkg/AgesaCommonModulePkg.dec AgesaModulePkg/AgesaModulePspPkg.dec - - diff --git a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.c b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.c index fce82d75b00f2c45c91c2ccba4aff1210ab3f0cc..81b47bd2523138bd9ff6f70f3abfb1ca0adb1911 100644 --- a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.c +++ b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.inf b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.inf index 09d5bd38ac1c17583d5a4b2d8c967175bd8c68eb..e7b78e76655eaa47ae7dfa8de858da37a39d5675 100644 --- a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.inf +++ b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3/ApcbLibV3.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -12,7 +12,7 @@ FILE_GUID = C7932467-DF16-4C7A-A32A-3E6F50213E68 MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 - LIBRARY_CLASS = ApcbLibV3 | DXE_DRIVER DXE_SMM_DRIVER DXE_RUNTIME_DRIVER DXE_CORE SMM_CORE UEFI_DRIVER + LIBRARY_CLASS = ApcbLibV3 | DXE_DRIVER DXE_SMM_DRIVER DXE_RUNTIME_DRIVER DXE_CORE SMM_CORE UEFI_DRIVER [Sources.common] ApcbLibV3.c @@ -31,7 +31,3 @@ [Pcd] gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemCfgMaxPostPackageRepairEntries - - - - diff --git a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.c b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.c index f8b9eb0bcfd3aa069b47413779ded6fb0767f777..235189aebfac80462b25d210f51ca1a1aa339daf 100644 --- a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.c +++ b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.inf b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.inf index c031d00d79227a907c42ad4876dbfd0c65d2347f..3a242a38eaa1ddcfbb5ddb34a01ad4c28d61f7ce 100644 --- a/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.inf +++ b/Platform/AMD/AgesaModulePkg/Library/ApcbLibV3Pei/ApcbLibV3Pei.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.c b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.c new file mode 100644 index 0000000000000000000000000000000000000000..1b15b82a93857bd63ba9c36e61fa8790ae631b36 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.c @@ -0,0 +1,47 @@ +/** @file + + Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +UINTN +FabricTopologyGetNumberOfProcessorsPresent ( + VOID + ) +{ + return 0; +} + +UINTN +FabricTopologyGetNumberOfRootBridgesOnSocket ( + IN UINTN Socket + ) +{ + return 0; +} + +UINTN +FabricTopologyGetHostBridgeBusBase ( + IN UINTN Socket, + IN UINTN Die, + IN UINTN Index + ) +{ + return (UINTN)-1; +} + +UINTN +FabricTopologyGetHostBridgeBusLimit ( + IN UINTN Socket, + IN UINTN Die, + IN UINTN Index + ) +{ + return 0; +} diff --git a/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.inf b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..92281562707e1670eb324e31116180945761c5f2 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyBrhLib/BaseFabricTopologyBrhLib.inf @@ -0,0 +1,31 @@ +## @file +# +# For EDKII use Only +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BaseFabricTopologyBrhLib + FILE_GUID = 92CA2E3D-A8C5-47E0-879D-9D56BDBD8B13 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BaseFabricTopologyLib + +[Sources] + BaseFabricTopologyBrhLib.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModuleDfPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + diff --git a/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.c b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.c index cff678d76b2d12387540663e58cd0ad2d8b3cfc7..6aaa72050eb9967777fd3be7f80d3b0be2397591 100644 --- a/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.c @@ -1,7 +1,7 @@ ** @file Fabric Topology Base Lib implementation - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.inf b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.inf index 38a72e26b76385d5b7e55f975becd33c66296046..718c22ca78dea8512181f4689eac1c575e8bb028 100644 --- a/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/BaseFabricTopologyRsLib/BaseFabricTopologyRsLib.inf @@ -2,7 +2,7 @@ # # For EDKII use Only # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.c b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.c index f72cbe7dffb656d838cb42831e97115e5180d540..970290c52b4eb229443ac808cdd74214f553cec4 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.c @@ -1,7 +1,6 @@ /** @file - A Base Timer Library implementation which uses the Time Stamp Counter in the processor. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf index d15d8169febbb2287eefc4b72570fb110628391e..d8a1e00dfe4c3b056d33d37c2ee3453c31e1226c 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf @@ -1,7 +1,6 @@ ## @file -# Base Timer Library which uses the Time Stamp Counter in the processor. # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.c b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.c index a155978a5d1595eba41299bfb6317389edbb2f2e..d08551a25d84aa3e89c557e7c4cb937e4fa6ba4c 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.c @@ -1,7 +1,6 @@ /** @file - A Dxe Timer Library implementation which uses the Time Stamp Counter in the processor. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf index 1e52768a01ec0b6fd495220e1edb3878391fbc09..c0b240bcfeb2de2725e1838b9d9f1666a9d11a22 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf @@ -1,7 +1,6 @@ ## @file -# Dxe Timer Library which uses the Time Stamp Counter in the processor. # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.c b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.c index f70aa3de0ece521df385c9090995fd8f664c2626..cf5932481f959185309fd43afeeef1ac4b052cf1 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.c @@ -1,7 +1,6 @@ /** @file - A Pei Timer Library implementation which uses the Time Stamp Counter in the processor. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf index b1eaefd2824c20b812c59a3c1bf839f74643eba8..23c5c67ed768fd32265f2ebc09b30f1564ba3378 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf @@ -1,7 +1,6 @@ ## @file -# Pei Timer Library which uses the Time Stamp Counter in the processor. # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/TscTimerLibShare.c b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/TscTimerLibShare.c index 7d14d62e60d75bcc58725170bec84edab07b8e54..054365347ccc5329d1dd4453b8073e39284c5075 100644 --- a/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/TscTimerLibShare.c +++ b/Platform/AMD/AgesaModulePkg/Library/CcxTscTimerLib/TscTimerLibShare.c @@ -1,7 +1,6 @@ /** @file - The Timer Library implementation which uses the Time Stamp Counter in the processor. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.c index 44e23df62f93b9cde6946d9f7562d3828b86080e..91d87216c2dc352b49d0ccf1f8202110f64b7d4e 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.c @@ -1,7 +1,6 @@ /** @file - AMD instance of the PCI Host Bridge Library. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf b/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf index f60f97905a7ca607a9c35e232e54e430ceb0faa3..6ff6aa68602d17114d8d81e323eede822faa3ba5 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf @@ -1,7 +1,6 @@ ## @file -# Library instance of PciHostBridgeLib library class for coreboot. # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlArgObjects.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlArgObjects.c index 318f8e5ad7ee5d900ce13589bd3f0d9956b26a11..edb8cd971c5d16e4bc5531257d62b8dd8ca65967 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlArgObjects.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlArgObjects.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2021-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c index 371537c9aac5435944317d2cb26a23aeb947235f..ddf7b859e5c5e385c08ea5f324854ba3cb3969fd 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlDataObjects.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlDataObjects.c index b7d4f4c9d74e673776f5b4885af6da2cccfd5921..b5cf796da16a1175f3813c25f6279e8fa6bbb7ce 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlDataObjects.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlDataObjects.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c index e8ea9d8e84d5f83bb8cab6f9600e2da1a3278a47..52b3ec13eb738a2430669412a3d1ec1f818cc3d3 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf index 2a72fa8117c03ee8a4b61ced452f20715b2e74b5..052d0a4d0336931f64f886a45a03e9f145c241c8 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf @@ -1,47 +1,47 @@ -## @file -# -# Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AmlGenerationLib - FILE_GUID = 8F62C8D1-B67F-4AFB-9179-54384F1A6163 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = AmlGenerationLib | DXE_DRIVER UEFI_DRIVER HOST_APPLICATION - -[Sources.common] - LocalAmlObjects.h - LocalAmlObjects.c - LocalAmlLib.h - AmlAssistFunctions.c - AmlObjectsDebug.c - AmlNameString.c - AmlDataObjects.c - AmlNamespaceModifierObjects.c - AmlPkgLength.c - AmlNamedObject.c - AmlTable.c - AmlStatementOpcodes.c - AmlResourceDescriptor.c - AmlExpressionOpcodes.c - AmlArgObjects.c - AmlLocalObjects.c - -[Packages] - MdePkg/MdePkg.dec - AgesaPkg/AgesaPkg.dec - AgesaModulePkg/AgesaCommonModulePkg.dec - -[LibraryClasses] - BaseLib - DebugLib - BaseMemoryLib - MemoryAllocationLib - -[Depex] - TRUE - +## @file +# +# Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmlGenerationLib + FILE_GUID = 8F62C8D1-B67F-4AFB-9179-54384F1A6163 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = AmlGenerationLib | DXE_DRIVER UEFI_DRIVER HOST_APPLICATION + +[Sources.common] + LocalAmlObjects.h + LocalAmlObjects.c + LocalAmlLib.h + AmlAssistFunctions.c + AmlObjectsDebug.c + AmlNameString.c + AmlDataObjects.c + AmlNamespaceModifierObjects.c + AmlPkgLength.c + AmlNamedObject.c + AmlTable.c + AmlStatementOpcodes.c + AmlResourceDescriptor.c + AmlExpressionOpcodes.c + AmlArgObjects.c + AmlLocalObjects.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + +[Depex] + TRUE + diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c index 21deb200e327732c4df25ddb0dc39f9e3c7cb298..0f639ba3f71937e9c4441c044e0a0d39faf61929 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNameString.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNameString.c index 0502547a013db3dffffa49e5a4666c2f3048c552..46d04534db0340b51e5d32aaf921de0bb80ce1e8 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNameString.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNameString.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamedObject.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamedObject.c index 37ae9319beadd78fb82d9b2366ecf2eb9c7393d1..eeeff6a8482370594db47f67d53076b65a156c86 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamedObject.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamedObject.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c index afe51cdcf24bf6086e4d65b55cf81bb88dfa7914..33bdd57df0219a38c36f2c9fad25af2b4b0415c6 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c index 279bfc782d76efc5797a2206269f3fba222409f3..1cda39236ff61390f4df5536b8d2f04540276feb 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlPkgLength.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlPkgLength.c index 85d184b759f920a682d344e3487e6233642df01e..d161fca586d95e34995338851de706688a1871a7 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlPkgLength.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlPkgLength.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c index 4ef746327bebaebffc9634d3489d825cc6ffface..7c34375ae124d900eff7e502b075c13d07c62f02 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c index 03201d01096658bae83788825baa9198f95ea318..86040fff3c49bc9a6d60b6c9a34feae526528bf2 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlTable.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlTable.c index c9a43997649d32cb2bf65a2c92f2209799519b21..cd7780cf6b2e563162d7a2720e84acabf6939156 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlTable.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/AmlTable.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlLib.h b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlLib.h index a60ae20d334ee7f2e210223663f88a0bbfadd388..a4759b5cc9d18343d5970393c64c285209add2c2 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlLib.h +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlLib.h @@ -1,13 +1,13 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _INTERNAL_AML_LIB_H_ -#define _INTERNAL_AML_LIB_H_ +#ifndef INTERNAL_AML_LIB_H_ +#define INTERNAL_AML_LIB_H_ #include #include @@ -97,4 +97,4 @@ InternalAmlNameSeg ( IN OUT LIST_ENTRY *ListHead ); -#endif +#endif // INTERNAL_AML_LIB_H_ diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c index b1ad9b70372c9e8718d987a4e93a0ad7c5d2a87c..6325cacec5984b9edbc94a093a503371fd41b5c6 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h index b19b6fe867609e6046880732fb4fb2922c176c33..4e8ca98a259cae4840301609e3f0046383c694e5 100644 --- a/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h +++ b/Platform/AMD/AgesaModulePkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h @@ -1,13 +1,13 @@ /** @file - Copyright (C) 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _INTERNAL_AML_OBJECTS_H_ -#define _INTERNAL_AML_OBJECTS_H_ +#ifndef INTERNAL_AML_OBJECTS_H_ +#define INTERNAL_AML_OBJECTS_H_ // #include "LocalAmlLib.h" @@ -147,4 +147,4 @@ InternalAmlCollapseAndReleaseChildren ( IN OUT LIST_ENTRY *ListHead ); -#endif // _INTERNAL_AML_OBJECTS_H_ +#endif // INTERNAL_AML_OBJECTS_H_ diff --git a/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchBaseLib.inf b/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchBaseLib.inf index e63a70e8490b3e40a8cd1fde310128d087852df0..eba5efd2fd587698a561b38546cb09c379ec1857 100644 --- a/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchBaseLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchBaseLib.inf @@ -1,26 +1,26 @@ -## @file -# -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x00010006 - BASE_NAME = FchBaseLib - FILE_GUID = 4108287a-c864-4427-b2c3-bd0e91a83abd - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = FchBaseLib - -[Sources.common] - FchStallLib.c - -[Packages] - AgesaModulePkg/AgesaModuleFchPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - PciSegmentLib - +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = FchBaseLib + FILE_GUID = 4108287a-c864-4427-b2c3-bd0e91a83abd + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FchBaseLib + +[Sources.common] + FchStallLib.c + +[Packages] + AgesaModulePkg/AgesaModuleFchPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + PciSegmentLib + diff --git a/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchStallLib.c b/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchStallLib.c index 2f4f676adb106ff8b179bbd66d6bbe2a26c3809c..0a030e056db7209b46ede0708c69ebc0b2985e9a 100644 --- a/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchStallLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/FchBaseLib/FchStallLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.c b/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.c index 60305ee4a6a7d4f14bcf7e7e3326176675fa852b..dc9d08389b51cd5453d5691f98c56d4590c726da 100644 --- a/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.c @@ -1,7 +1,6 @@ /** @file - Library to support reset library, inheritted from Agesa Cf9Reset module. - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf b/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf index e422cb69a47be58db4d58f361f1a4b1558b50967..a7f4a96fae53bcc713389f858c6fa6b425d263d3 100644 --- a/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.c b/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.c index d10e676668da50cb213ae6f7989325fa31e96b06..72681e16c97da73a0d94036dace69e07ba33c2b5 100644 --- a/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf b/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf index d7f49c40de3f00774eee6d7da5e9c6de03349f83..cd8d497539aa23ab4e5831331ee7008fc1160826 100644 --- a/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf @@ -1,33 +1,26 @@ -## @file -# -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x00010006 - BASE_NAME = FchEspiCmdLib - FILE_GUID = 89671327-a620-43e9-93b1-d1da79a50392 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = FchEspiCmdLib - -[Sources.common] - FchEspiCmdLib.c - -[Packages] - AgesaModulePkg/AgesaModuleFchPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - IoLib - FchBaseLib - - - - - - - +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = FchEspiCmdLib + FILE_GUID = 89671327-a620-43e9-93b1-d1da79a50392 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FchEspiCmdLib + +[Sources.common] + FchEspiCmdLib.c + +[Packages] + AgesaModulePkg/AgesaModuleFchPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + IoLib + FchBaseLib diff --git a/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.c b/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.c index 9044d3d497304c47d57014b548e5e2c01d66edc5..352ae3f3c0e3c6b23582640d1d9dd6bd2f2d038a 100755 --- a/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.c @@ -1,8 +1,6 @@ /** @file - GNB function to create/locate PCIe configuration data area, Contain code - that create/locate/manages GNB/PCIe configuration - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.inf b/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.inf index f32bbc9ff2173a8090b40838c86a3448ddaaea81..7b7355ea87b65ca9777c22a3a71407a35f756ae5 100755 --- a/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.c b/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.c index d5fbe98d2265502aba8d36e62483a0c66862b6ca..9d9b27ac43414dcfcd18c2577957ed7902ccb930 100755 --- a/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.c @@ -1,7 +1,6 @@ /** @file - GNB function to create/locate PCIe configuration data area - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf b/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf index 0d6ba605f5d2cc28b58c9f32645d100361989da7..efa6394a9a0dda4a2a6f0ffd87920c122d7f2dea 100755 --- a/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieInputParserLib.c b/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieInputParserLib.c index 5c6be22ee460fed8437907d9f956089a1a6fbd99..fa0249aca02de2be725c7b6a1a24de12f1f9072e 100755 --- a/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieInputParserLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/PcieConfigLib/PcieInputParserLib.c @@ -1,7 +1,6 @@ /** @file - Procedure to parse PCIe input configuration data - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.c b/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.c index e6be32b071c2226dab47c32f77b95bde4efe0c79..7f401b83b1125807404b5b732130cfa9478d14ea 100644 --- a/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.c +++ b/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.c @@ -1,10 +1,30 @@ /** @file - SMN Register Access Methods - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include + +/* + Routine to read all register spaces. + + @param[in] SegmentNumber Segment number of D0F0 of the target die + @param[in] BusNumber Bus number of D0F0 of the target die + @param[in] Address Register offset, but PortDevice + @param[out] Value Return value + @retval VOID + */ +VOID +EFIAPI +SmnRegisterReadS ( + IN UINT32 SegmentNumber, + IN UINT32 BusNumber, + IN UINT32 Address, + OUT VOID *Value + ) +{ + return; +} diff --git a/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.inf b/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.inf index ae1dd6cd8377f5a0fa8e17120bf7cf10bd53655a..d437916327e13227f2e42d16346d0045080a5ad7 100644 --- a/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.inf +++ b/Platform/AMD/AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/DxeLibFunctions.c b/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/DxeLibFunctions.c index 1dc13900c7d15a3974516a19569ccbafcf7e45a6..e924254bdd191f9a7e656e4c995ef876bf95a249 100644 --- a/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/DxeLibFunctions.c +++ b/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/DxeLibFunctions.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/NbioCommonDxeLib.inf b/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/NbioCommonDxeLib.inf index da7f5c185d54e68653fab3778dcd824035780957..da1bd461985abfbe21b8986560cd7cad57f3e445 100644 --- a/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/NbioCommonDxeLib.inf +++ b/Platform/AMD/AgesaModulePkg/Nbio/Library/CommonDxe/NbioCommonDxeLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.c b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.c index fbd3ddcf3742b1c7940abd8d212efd7c78fd69e0..a8db3ef5c75ac1dd489e17080c9756689abd7a6d 100644 --- a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.c +++ b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.c @@ -1,7 +1,6 @@ /** @file - APCB DXE Driver - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.inf b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.inf index 54c3514020dc283dedce3de134dfbc144bb3e632..4af1447848ca39027c821747ad745abe40ba3f59 100644 --- a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.inf +++ b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Dxe/ApcbV3Dxe.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.c b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.c index 23d1a8fee01d8b1458a348a5f707c6cdf7c44e23..5e81ab8dddcd023e57168ae246075759086a84ac 100644 --- a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.c +++ b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.inf b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.inf index 7f90aa6ea0a11e9442b93cdc354c0432b5eab14a..9bedce23f00b8b20621f0d41acf624fa1aae75ad 100644 --- a/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.inf +++ b/Platform/AMD/AgesaModulePkg/Psp/ApcbDrv/ApcbV3Pei/ApcbV3Pei.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.c b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.c new file mode 100644 index 0000000000000000000000000000000000000000..fe179889445c828728d529c6df4626e57070ef8a --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.c @@ -0,0 +1,44 @@ +/** @file + + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Entry point of Act Dynamic Command. + + Produce the DynamicCommand protocol to handle "act" command. + + @param ImageHandle The image handle of the process. + @param SystemTable The EFI System Table pointer. + + @retval EFI_SUCCESS Act command is executed sucessfully. + @retval EFI_ABORTED HII package was failed to initialize. + @retval others Other errors when executing act command. +**/ +EFI_STATUS +EFIAPI +ActCommandInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} + +/** + Destructor for the library. free any resources. + + @param ImageHandle The image handle of the process. + @param SystemTable The EFI System Table pointer. +**/ +EFI_STATUS +EFIAPI +ActLibraryUnregisterActCommand ( + IN EFI_HANDLE ImageHandle + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf new file mode 100644 index 0000000000000000000000000000000000000000..47000b346a7af31492f9240e8539726f04550172 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf @@ -0,0 +1,26 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = AmdAutoDynamicCommand + FILE_GUID = CCD8FEC8-1E30-45BD-8632-DB83A255FAC3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.1 + ENTRY_POINT = ActCommandInitialize + +[Sources.common] + AmdAutoDynamicCommand.c + AutoConfigOptions.c + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Depex] + TRUE \ No newline at end of file diff --git a/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf new file mode 100644 index 0000000000000000000000000000000000000000..7af256233a8d6ca840f600a929bfccc0b9c10544 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf @@ -0,0 +1,26 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = AmdAutoToolApp + FILE_GUID = 470E1741-2DFE-43EF-861E-505CB3226DC0 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + ENTRY_POINT = ActCommandInitialize + +[Sources.common] + AmdAutoDynamicCommand.c + AutoConfigOptions.c + +[LibraryClasses] + UefiBootServicesTableLib + UefiApplicationEntryPoint + +[Depex] + TRUE diff --git a/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AutoConfigOptions.c b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AutoConfigOptions.c new file mode 100644 index 0000000000000000000000000000000000000000..1e496a8a80dc20a7385bf276ddf85dcbcb4bf853 --- /dev/null +++ b/Platform/AMD/AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AutoConfigOptions.c @@ -0,0 +1,7 @@ +/** @file + + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ diff --git a/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.c b/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.c index 74b129931b0bdb47a643a7d570396900f90252ea..fd116812be70b5d266deafa6ce939eb4e1fa26bf 100644 --- a/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.c +++ b/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.c @@ -1,7 +1,6 @@ /** @file - Required OEM hooks for CCX initialization - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf b/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf index 0f115c362e71543c470eb85c12a56fd339fafec8..6438546e35d3a33ea45a78ed0478d29e90a78248 100755 --- a/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf +++ b/Platform/AMD/AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.c b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.c index 54ce202cb1a3a0ab241d0d0a5255b647e4408873..1915c1691da32ee508c81572fe661357206f9f0e 100644 --- a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.c +++ b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf index ba551e5c142ab7d78acfd4ab0939e822b4a21134..d1dfff95457611692cda1e6aad95c1ab6db66c9c 100644 --- a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf +++ b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf index e712a808862897c1700c5f52314e37b73b4b1297..b629ab8b248b79a67646c59b3104d99a63f1b13c 100644 --- a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf +++ b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciSegmentInfoLib.c b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciSegmentInfoLib.c index 643174d7b9e80df1cf7f996efce5ac4140a369b1..082ba89b0661dfd55f3d1f522858b8899cd054ed 100644 --- a/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciSegmentInfoLib.c +++ b/Platform/AMD/AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciSegmentInfoLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.c b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..eb188fa0b3926d78fe2ad885a9659271619ac505 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.c @@ -0,0 +1,16 @@ +/** @file + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +EFI_STATUS +EFIAPI +AmdPspDpeDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..07e257e4cf2f96dc2c7450a7398f5eec623144d7 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf @@ -0,0 +1,25 @@ +## @file +# +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmdPspDpeDxe + FILE_GUID = 3d86af84-10ca-4139-b253-f1b88e6fc279 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AmdPspDpeDxeEntry + +[Sources] + AmdPspDpeDxe.c + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Depex] + TRUE \ No newline at end of file diff --git a/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.c b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.c index d83bb6c2d88db06ecaccbd773baded591b041532..cfbe255bfce2c465ee5acb9d99426c95e5a1369d 100644 --- a/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.c +++ b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf index f4b9d0d7891370d658f62e0301a93d7daea0e88d..4e3cd9622cf2f7ce81bb477a2b147819e50cdc7d 100644 --- a/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf +++ b/Platform/AMD/AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.c b/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.c index a264eb929425bccf113fa7d090e9183ef360f673..74c0e90b2ba7a8df3be3d21abc4accafd4bcfc91 100644 --- a/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.c +++ b/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.c @@ -1,12 +1,29 @@ /** @file - Platform ROM Armor Whitelist table - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include +#include +#include #include #include -#include + +/* + Return allocated and filled AMD PSP ROM Armor White list Table + + @param[in] PlatformSpiWhitelist Pointer to white list table + + @return EFI_SUCCESS + @return EFI_OUT_OF_RESOURCES Buffer to return could not be allocated + */ +EFI_STATUS +EFIAPI +GetPspRomArmorWhitelist ( + IN SPI_WHITE_LIST **PlatformSpiWhitelist + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf b/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf index 57bb0d9e25745f14f1d99a86fe18c4efd1f0fc96..2e72f4e39c5c20c28ef020443399d171dcb4fd00 100644 --- a/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf +++ b/Platform/AMD/AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AgesaPkg/AgesaPkg.dec b/Platform/AMD/AgesaPkg/AgesaPkg.dec index 9377c64cc348f14d8b5c8a9104ab736c03e37c4d..c9f6070ad7efd8736c8913c56cc7290e1ab4d916 100644 --- a/Platform/AMD/AgesaPkg/AgesaPkg.dec +++ b/Platform/AMD/AgesaPkg/AgesaPkg.dec @@ -1,8 +1,6 @@ ## @file -# AMD Generic Encapsulated Software Architecture (AGESA) Package DEC -# file. # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -341,7 +339,6 @@ gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemPostPackageRepair|TRUE|BOOLEAN|0x00030004 gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemBootTimePostPackageRepair|TRUE|BOOLEAN|0x00030005 gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemRuntimePostPackageRepair|FALSE|BOOLEAN|0x00030006 -[PcdsDynamicEx] [PcdsFixedAtBuild, PcdsDynamic] #---------------------------------------------------------------------------- @@ -408,6 +405,14 @@ #---------------------------------------------------------------------------- ### PSP PCDs + ### @brief Switch to control if S3/Capsule start + ### @details Switch to control if S3/Capsule start from SMM or + ### the address provided by PspPlatfromProtocol->RsmHandOffInfo->RsmEntryPoint. + ### @li TRUE: S3/Capsule start from BspSmmResumeVector. + ### @li FALSE: S3/Capsule start from PspPlatfromProtocol->RsmHandOffInfo->RsmEntryPoint. + ### NOTE, Processor will be set to 32bits protect mode with pagging disabled. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspS3WakeFromSmm|TRUE|BOOLEAN|0x95940F00 + ### @brief Rom Armor selection ### @details Rom Armor selection ### @li 0: Rom Armor is disabled @@ -416,8 +421,6 @@ ### @li 3: Rom Armor 3 is enabled (CGL, RMB and later) gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspRomArmorSelection|0|UINT8|0x95940054 - - ### @brief System TPM config Value ### @details System TPM config Value, SBIOS needs to set the value in PEI phase. ### @li 0x0: dTPM diff --git a/Platform/AMD/AgesaPkg/Include/AmdPcieComplex.h b/Platform/AMD/AgesaPkg/Include/AmdPcieComplex.h index 3a628ed0b29ca3f70dd58af91fd6d41033006198..f546b245cc02512eff54e197cea919d2a2fa4fc0 100755 --- a/Platform/AMD/AgesaPkg/Include/AmdPcieComplex.h +++ b/Platform/AMD/AgesaPkg/Include/AmdPcieComplex.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -48,6 +48,17 @@ typedef struct { IN UINT32 Ovrd; ///< Ancillary data table address point to ANC_DATA_PARAM[] } ANC_DATA; +/** + * @brief Port parameter override enumerator. + * @details This enumerator provides a parmeter type for platform topology override values. + * If unused all ports will default to platform configurations. + */ +typedef enum { + PP_SLOT_NUM, /**< (__UINT16__) Specify a SLOT NUMBER value. + * @li Valid Values: __0-0xFFFF__ + */ +} DXIO_PORT_PARAM_TYPE; + typedef struct { UINT16 ParamType; ///< This identifies a specific PHY parameter UINT16 ParamValue; ///< This specifies the value to be assigned to indicated PHY parameter @@ -429,4 +440,14 @@ typedef enum { DxioGen5, ///< Gen5 MaxDxioGen ///< Max Gen for boundary check } DXIO_LINK_SPEEDS; + +/** + * @brief PCIe link initialization + * @details NOTE: UBM HFC hotplug types are identified during auto-discovery + */ +typedef enum { + DxioPortDisabled, ///< Disable + DxioPortEnabled ///< Enable +} DXIO_PORT_ENABLE; + #endif // AMD_PCIE_COMPLEX_H_ diff --git a/Platform/AMD/AgesaPkg/Include/AmdSoc.h b/Platform/AMD/AgesaPkg/Include/AmdSoc.h index d62f26023582722783ab4f5cc5dffe9cb487f11f..32978a16a81646f1c7f71a94a67e74c9301a1e24 100644 --- a/Platform/AMD/AgesaPkg/Include/AmdSoc.h +++ b/Platform/AMD/AgesaPkg/Include/AmdSoc.h @@ -1,13 +1,13 @@ /** @file - Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _AMD_SOC_H_ -#define _AMD_SOC_H_ +#ifndef AMD_SOC_H_ +#define AMD_SOC_H_ #define F1A_BRH_A0_RAW_ID 0x00B00F00ul #define F1A_BRH_B0_RAW_ID 0x00B00F10ul diff --git a/Platform/AMD/AgesaPkg/Include/AmdUefiStackNasm.inc b/Platform/AMD/AgesaPkg/Include/AmdUefiStackNasm.inc index 2dfb3190d4388e437b2ed0782a73bdead3b8b5b4..7508b7822fbd7a961d48269e9d56f4f105c0083a 100644 --- a/Platform/AMD/AgesaPkg/Include/AmdUefiStackNasm.inc +++ b/Platform/AMD/AgesaPkg/Include/AmdUefiStackNasm.inc @@ -1,10 +1,12 @@ ; @file ; ; AMD Generic Encapsulated Software Architecture -; Code to setup temporary memory access for stack usage. This code -; is to be used on memory present systems that do not need CAR. -; -; Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+; Workfile: AmdUefiStackNasm.inc +; $Revision$ $Date$ +; Description: Code to setup temporary memory access for stack usage. This code +; is to be used on memory present systems that do not need CAR +; +; Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
; ; SPDX-License-Identifier: BSD-2-Clause-Patent ; diff --git a/Platform/AMD/AgesaPkg/Include/FabricResourceManagerCmn.h b/Platform/AMD/AgesaPkg/Include/FabricResourceManagerCmn.h index 2291f7dc83c1455a27717989cdef6ac7ef25a132..d39153b2da40fbf9ca3fe9952ef71ffb16070ffa 100644 --- a/Platform/AMD/AgesaPkg/Include/FabricResourceManagerCmn.h +++ b/Platform/AMD/AgesaPkg/Include/FabricResourceManagerCmn.h @@ -1,7 +1,6 @@ /** @file - Fabric resource manager common definition - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -11,7 +10,7 @@ #define FABRIC_RESOURCE_MANAGER_CMN_H_ #pragma pack (push, 1) -#define MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system. +#define MAX_SOCKETS_SUPPORTED 4 ///< Max number of sockets in system. #define MAX_RBS_PER_SOCKET 20 ///< Max number of root bridges per socket. /** diff --git a/Platform/AMD/AgesaPkg/Include/Guid/AmdMemoryInfoHob.h b/Platform/AMD/AgesaPkg/Include/Guid/AmdMemoryInfoHob.h index 9e58f299b49a6baee96acdd55d2e524a04764f54..47d08de1e726d96765eea8fe2ce08ecfd603759a 100644 --- a/Platform/AMD/AgesaPkg/Include/Guid/AmdMemoryInfoHob.h +++ b/Platform/AMD/AgesaPkg/Include/Guid/AmdMemoryInfoHob.h @@ -1,7 +1,7 @@ /** @file - AMD Memory Info Hob Definition - Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AgesaPkg/Include/Library/AmdPspBaseLibV2.h b/Platform/AMD/AgesaPkg/Include/Library/AmdPspBaseLibV2.h index d144a4ad2052396792bc87839a1f60563426e09b..790ffdd6b337fe680a8e8416d777fc891e5b5113 100644 --- a/Platform/AMD/AgesaPkg/Include/Library/AmdPspBaseLibV2.h +++ b/Platform/AMD/AgesaPkg/Include/Library/AmdPspBaseLibV2.h @@ -1,6 +1,8 @@ /** @file AMD Psp Base Lib - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AgesaPkg/Include/Library/AmdPspFtpmLib.h b/Platform/AMD/AgesaPkg/Include/Library/AmdPspFtpmLib.h index 23c90b65c2b47780c480bab90587f09f23f2f50b..ba88f40836f25f894f246f4e1c80fccb0c2fe354 100644 --- a/Platform/AMD/AgesaPkg/Include/Library/AmdPspFtpmLib.h +++ b/Platform/AMD/AgesaPkg/Include/Library/AmdPspFtpmLib.h @@ -1,7 +1,8 @@ /** @file AMD Psp Ftpm Library header file - Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AgesaPkg/Include/Library/AmdPspRomArmorLib.h b/Platform/AMD/AgesaPkg/Include/Library/AmdPspRomArmorLib.h index 4ad4020f958904fe0feaee7c2c7ce1d6490bfcc9..5c1047f9a7dbca864e0566d5d7815ec72279a116 100644 --- a/Platform/AMD/AgesaPkg/Include/Library/AmdPspRomArmorLib.h +++ b/Platform/AMD/AgesaPkg/Include/Library/AmdPspRomArmorLib.h @@ -1,13 +1,13 @@ /** @file - Copyright (C) 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef _PSP_ROM_ARMOR_LIB_H_ -#define _PSP_ROM_ARMOR_LIB_H_ +#ifndef PSP_ROM_ARMOR_LIB_H_ +#define PSP_ROM_ARMOR_LIB_H_ #include "Uefi.h" @@ -228,4 +228,4 @@ PspSwitchChipSelect ( IN UINT8 ChipSelect ); -#endif //_PSP_ROM_ARMOR_LIB_H_ +#endif // PSP_ROM_ARMOR_LIB_H_ diff --git a/Platform/AMD/AgesaPkg/Include/Library/AmlGenerationLib.h b/Platform/AMD/AgesaPkg/Include/Library/AmlGenerationLib.h index 0189910bd12c424012522b3dc68ed887b67771d6..a28181cc12302d0f7043185acc61c6b69708c018 100644 --- a/Platform/AMD/AgesaPkg/Include/Library/AmlGenerationLib.h +++ b/Platform/AMD/AgesaPkg/Include/Library/AmlGenerationLib.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Include/Library/PlatformPspRomArmorWhitelistLib.h b/Platform/AMD/AgesaPkg/Include/Library/PlatformPspRomArmorWhitelistLib.h index d48ca1a90a3a4f3f45e56b5584e2937aca6297a8..fb1e75951866090c492c77d5ea91a94e96880259 100644 --- a/Platform/AMD/AgesaPkg/Include/Library/PlatformPspRomArmorWhitelistLib.h +++ b/Platform/AMD/AgesaPkg/Include/Library/PlatformPspRomArmorWhitelistLib.h @@ -1,12 +1,14 @@ /** @file - Platform ROM Armor Whitelist table - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ +#ifndef PLATFORM_PSP_ROM_ARMOR_WHILE_LIST_ +#define PLATFORM_PSP_ROM_ARMOR_WHILE_LIST_ + #include /* @@ -23,3 +25,5 @@ EFIAPI GetPspRomArmorWhitelist ( IN SPI_WHITE_LIST **PlatformSpiWhitelist ); + +#endif // PLATFORM_PSP_ROM_ARMOR_WHILE_LIST_ diff --git a/Platform/AMD/AgesaPkg/Include/Ppi/AmdPspFtpmPpi.h b/Platform/AMD/AgesaPkg/Include/Ppi/AmdPspFtpmPpi.h index 6c854651ccd9301de673c034e6a6dae13e0f7e87..80c0acfc83affcab790b343fd3914fb499341782 100644 --- a/Platform/AMD/AgesaPkg/Include/Ppi/AmdPspFtpmPpi.h +++ b/Platform/AMD/AgesaPkg/Include/Ppi/AmdPspFtpmPpi.h @@ -1,7 +1,8 @@ /** @file AMD Psp Ftpm Ppi Header - Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AgesaPkg/Include/Protocol/AmdCxlServicesProtocol.h b/Platform/AMD/AgesaPkg/Include/Protocol/AmdCxlServicesProtocol.h index 715cbbcf78179b111944c4c4f7d0af8ced017519..e3cf692d3bb003f5fa49d2a06421a279e7f95d5d 100644 --- a/Platform/AMD/AgesaPkg/Include/Protocol/AmdCxlServicesProtocol.h +++ b/Platform/AMD/AgesaPkg/Include/Protocol/AmdCxlServicesProtocol.h @@ -1,7 +1,6 @@ /** @file - CXL Configuration Services Protocol prototype definition - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Include/Protocol/AmdPciResourcesProtocol.h b/Platform/AMD/AgesaPkg/Include/Protocol/AmdPciResourcesProtocol.h index 7bcff65dc998f5645aae9655c46d18a004788eae..c5fd167fc775bea06494fb23bfbb961a0543752c 100644 --- a/Platform/AMD/AgesaPkg/Include/Protocol/AmdPciResourcesProtocol.h +++ b/Platform/AMD/AgesaPkg/Include/Protocol/AmdPciResourcesProtocol.h @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Include/Protocol/AmdPspFtpmProtocol.h b/Platform/AMD/AgesaPkg/Include/Protocol/AmdPspFtpmProtocol.h index ebc7812b18e510a5d9b68901fa17659f9a90c4fd..706250f5f16dde33a771fc198eef3127f9164fec 100644 --- a/Platform/AMD/AgesaPkg/Include/Protocol/AmdPspFtpmProtocol.h +++ b/Platform/AMD/AgesaPkg/Include/Protocol/AmdPspFtpmProtocol.h @@ -1,7 +1,8 @@ /** @file AMD Psp Ftpm Protocol Header - Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AgesaPkg/Include/Protocol/FabricResourceManagerServicesProtocol.h b/Platform/AMD/AgesaPkg/Include/Protocol/FabricResourceManagerServicesProtocol.h index 7f57facf8850816e1c19ec76b53210c5bf3a8f16..127ab819fa49b44082ea298e6fdf8ed463a94949 100644 --- a/Platform/AMD/AgesaPkg/Include/Protocol/FabricResourceManagerServicesProtocol.h +++ b/Platform/AMD/AgesaPkg/Include/Protocol/FabricResourceManagerServicesProtocol.h @@ -1,7 +1,6 @@ /** @file - Fabric MMIO map manager Protocol prototype definition - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlArgObjects.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlArgObjects.c new file mode 100644 index 0000000000000000000000000000000000000000..fe91cb4f4a7f46d138febd254812706e8658b51a --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlArgObjects.c @@ -0,0 +1,151 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/* + Fill the DataBuffer with correct Arg Opcode based on provided argument number + Valid Argument numbers are 0, 1, 2, 3, 4, 5 and 6. + AML supports max 7 argument, i.e., Arg1, Arg2 ... Arg6. + + @param[in] ArgN - Argument Number + @param[out] ReturnData - Allocated DataBuffer with encoded integer + @param[out] ReturnDataSize - Size of ReturnData + + @return EFI_SUCCESS - Successful completion + @return EFI_OUT_OF_RESOURCES - Failed to allocate ReturnDataBuffer + @return EFI_INVALID_PARAMETER - Invalid ArgN provided. +*/ +EFI_STATUS +EFIAPI +InternalAmlArgBuffer ( + IN OUT UINT8 ArgN, + OUT VOID **ReturnData, + OUT UINTN *ReturnDataSize + ) +{ + UINT8 *Data; + UINTN DataSize; + + Data = AllocateZeroPool (sizeof (UINT8)); + if (Data == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Failed to create Data Buffer.\n", + __FUNCTION__ + )); + return EFI_OUT_OF_RESOURCES; + } + + DataSize = 1; + switch (ArgN) { + case 0: + Data[0] = AML_ARG0; + break; + case 1: + Data[0] = AML_ARG1; + break; + case 2: + Data[0] = AML_ARG2; + break; + case 3: + Data[0] = AML_ARG3; + break; + case 4: + Data[0] = AML_ARG4; + break; + case 5: + Data[0] = AML_ARG5; + break; + case 6: + Data[0] = AML_ARG6; + break; + default: + FreePool (Data); + return EFI_INVALID_PARAMETER; + } + + *ReturnData = (VOID *)Data; + *ReturnDataSize = DataSize; + + return EFI_SUCCESS; +} + +/** + Creates an ArgN Opcode object + + Arg Objects Encoding + ArgObj := Arg0Op | Arg1Op | Arg2Op | Arg3Op | Arg4Op | Arg5Op | Arg6Op + Arg0Op := 0x68 + Arg1Op := 0x69 + Arg2Op := 0x6A + Arg3Op := 0x6B + Arg4Op := 0x6C + Arg5Op := 0x6D + Arg6Op := 0x6E + + @param[in] ArgN - Argument Number to be encoded + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOpArgN ( + IN UINT8 ArgN, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Start %a object\n", + __FUNCTION__, + "ARGN_OPCODE" + )); + goto Done; + } + + Status = InternalAmlArgBuffer ( + ArgN, + (VOID **)&(Object->Data), + &(Object->DataSize) + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: ACPI Argument 0x%X object\n", + __FUNCTION__, + ArgN + )); + goto Done; + } + + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c new file mode 100644 index 0000000000000000000000000000000000000000..6991e2b6ed5e8fe72f2b5cf0b2a79497ccd7a1a0 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlAssistFunctions.c @@ -0,0 +1,148 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + Free all the children AML_OBJECT_INSTANCE(s) of ListHead. + Will not free ListHead nor an Object containing ListHead. + + @param[in,out] ListHead - Head of linked list of Objects + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +AmlFreeObjectList ( + IN OUT LIST_ENTRY *ListHead + ) +{ + LIST_ENTRY *Node; + AML_OBJECT_INSTANCE *Object; + + Node = GetNextNode (ListHead, ListHead); + while (Node != ListHead) { + Object = AML_OBJECT_INSTANCE_FROM_LINK (Node); + // Get next node before freeing current Object + Node = GetNextNode (ListHead, Node); + // Free Object + InternalFreeAmlObject (&Object, ListHead); + } + + return EFI_SUCCESS; +} + +/** + Validate that ACPI table is completed and return Table and Size + + @param[in,out] ListHead - Head of linked list of Objects + @param[out] Table - Completed ACPI Table + @param[out] TableSize - Completed ACPI Table size + + @retval EFI_SUCCESS + EFI_INVALID_PARAMETER + EFI_DEVICE_ERROR +**/ +EFI_STATUS +EFIAPI +AmlGetCompletedTable ( + IN OUT LIST_ENTRY *ListHead, + OUT VOID **Table, + OUT UINTN *TableSize + ) +{ + LIST_ENTRY *Node; + AML_OBJECT_INSTANCE *Object; + + if (ListHead == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ListHead cannot be NULL\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + *Table = NULL; + *TableSize = 0; + Node = GetFirstNode (ListHead); + if (!IsNodeAtEnd (ListHead, Node)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Multiple nodes remain, Likely missed an 'AmlClose' call\n", __FUNCTION__)); + return EFI_DEVICE_ERROR; + } else { + Object = AML_OBJECT_INSTANCE_FROM_LINK (Node); + if (!Object->Completed) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Final node not completed: Likely missed an 'AmlCLose' call\n", __FUNCTION__)); + return EFI_DEVICE_ERROR; + } + + *Table = Object->Data; + *TableSize = Object->DataSize; + } + + return EFI_SUCCESS; +} + +/** + Initialize Table List to work with AmlGenerationLib + + Allocates a LIST_ENTRY linked list item and initializes it. Use + AmlReleaseTableList to free resulting table and LIST_ENTRY. + + @param[in,out] ListHead - Head of linked list of Objects + + @retval EFI_SUCCESS + EFI_INVALID_PARAMETER + EFI_OUT_OF_RESOURCES +**/ +EFI_STATUS +EFIAPI +AmlInitializeTableList ( + IN OUT LIST_ENTRY **ListHead + ) +{ + if (ListHead == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ListHead = NULL\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + *ListHead = AllocatePool (sizeof (LIST_ENTRY)); + if (*ListHead == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Unable to allocate Table List Head\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + InitializeListHead (*ListHead); + + return EFI_SUCCESS; +} + +/** + Release table List + + Releases all elements. Use to free built table and LIST_ENTRY allocated by + AmlInitializeTableList. + + @param[in,out] ListHead - Head of linked list of Objects + + @retval EFI_SUCCESS + EFI_INVALID_PARAMETER +**/ +EFI_STATUS +EFIAPI +AmlReleaseTableList ( + IN OUT LIST_ENTRY **ListHead + ) +{ + if (*ListHead == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: NULL ListHead passed in\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + AmlFreeObjectList (*ListHead); + FreePool (*ListHead); + *ListHead = NULL; + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlDataObjects.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlDataObjects.c new file mode 100644 index 0000000000000000000000000000000000000000..9fd1c0a430d63dc2d70791007550980ea135e7ae --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlDataObjects.c @@ -0,0 +1,637 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/* + Creates an allocated buffer with sized data and no Op Code + + ByteData := 0x00 - 0xFF + WordData := ByteData[0:7] ByteData[8:15] // 0x0000-0xFFFF + DWordData := WordData[0:15] WordData[16:31] // 0x00000000-0xFFFFFFFF + QWordData := DWordData[0:31] DWordData[32:63] // 0x0000000000000000- 0xFFFFFFFFFFFFFFFF + + Forces max integer size UINT64 + + Caller is responsible for freeing returned buffer. + + @param[in] Integer - Integer value to encode + @param[in] IntegerSize - Size of integer in bytes + @param[out] ReturnData - Allocated DataBuffer with encoded integer + @param[out] ReturnDataSize - Size of ReturnData + + @return EFI_SUCCESS - Successful completion + @return EFI_OUT_OF_RESOURCES - Failed to allocate ReturnDataBuffer +*/ +EFI_STATUS +EFIAPI +InternalAmlSizedDataBuffer ( + IN UINT64 Integer, + IN UINTN IntegerSize, + OUT VOID **ReturnData + ) +{ + UINT8 *Data; + + if ((IntegerSize != sizeof (UINT8)) && + (IntegerSize != sizeof (UINT16)) && + (IntegerSize != sizeof (UINT32)) && + (IntegerSize != sizeof (UINT64))) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Incorrect integer size=%d requested.\n", __FUNCTION__, IntegerSize)); + return EFI_INVALID_PARAMETER; + } + + if ((IntegerSize < sizeof (UINT64)) && (Integer >= LShiftU64 (1, IntegerSize * 8))) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Integer is larger than requestd size.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + // Max Data Size is 64 bit. Plus one Opcode byte + Data = AllocateZeroPool (sizeof (UINT64)); + if (Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Integer Space Alloc Failed\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + // Already established we only have supported sizes above + switch (IntegerSize) { + case sizeof (UINT8): + *(UINT8 *)Data = (UINT8)Integer; + break; + case sizeof (UINT16): + *(UINT16 *)Data = (UINT16)Integer; + break; + case sizeof (UINT32): + *(UINT32 *)Data = (UINT32)Integer; + break; + case sizeof (UINT64): + *(UINT64 *)Data = (UINT64)Integer; + break; + } + + *ReturnData = (VOID *)Data; + return EFI_SUCCESS; +} + +/* + Calculates the optimized integer value used by AmlOPDataInteger and others + + Forces max integer size UINT64 + + @param[in] Integer - Integer value to encode + @param[out] ReturnData - Allocated DataBuffer with encoded integer + @param[out] ReturnDataSize - Size of ReturnData + + @return EFI_SUCCESS - Successful completion + @return EFI_OUT_OF_RESOURCES - Failed to allocate ReturnDataBuffer +*/ +EFI_STATUS +EFIAPI +InternalAmlDataIntegerBuffer ( + IN UINT64 Integer, + OUT VOID **ReturnData, + OUT UINTN *ReturnDataSize + ) +{ + UINT8 *IntegerData; + UINTN IntegerDataSize; + UINT8 *Data = NULL; + UINTN DataSize; + + // Max Data Size is 64 bit. Plus one Opcode byte + IntegerData = AllocateZeroPool (sizeof (UINT64) + 1); + if (IntegerData == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Integer Space Alloc Failed\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + if (Integer == 0) { + // ZeroOp + IntegerDataSize = 1; + IntegerData[0] = AML_ZERO_OP; + } else if (Integer == 1) { + // OneOp + IntegerDataSize = 1; + IntegerData[0] = AML_ONE_OP; + } else if (Integer == (UINT64) ~0x0) { + // OnesOp + IntegerDataSize = 1; + IntegerData[0] = AML_ONES_OP; + } else { + if (Integer >= 0x100000000) { + // QWordConst + IntegerDataSize = sizeof (UINT64) + 1; + IntegerData[0] = AML_QWORD_PREFIX; + } else if (Integer >= 0x10000) { + // DWordConst + IntegerDataSize = sizeof (UINT32) + 1; + IntegerData[0] = AML_DWORD_PREFIX; + } else if (Integer >= 0x100) { + // WordConst + IntegerDataSize = sizeof (UINT16) + 1; + IntegerData[0] = AML_WORD_PREFIX; + } else { + // ByteConst + IntegerDataSize = sizeof (UINT8) + 1; + IntegerData[0] = AML_BYTE_PREFIX; + } + + DataSize = IntegerDataSize - 1; + InternalAmlSizedDataBuffer (Integer, DataSize, (VOID **)&Data); + if (Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Integer Data Space Alloc Failed\n", __FUNCTION__)); + FreePool (IntegerData); + return EFI_OUT_OF_RESOURCES; + } + + CopyMem (&IntegerData[1], Data, DataSize); + FreePool (Data); + } + + // Reallocate the pool so size is exact + *ReturnData = (VOID *)IntegerData; + *ReturnDataSize = IntegerDataSize; + + return EFI_SUCCESS; +} + +/** + Creates an optimized integer object + + Forces max integer size UINT64 + + ComputationalData := ByteConst | WordConst | DWordConst | QWordConst | String | + ConstObj | RevisionOp | DefBuffer + DataObject := ComputationalData | DefPackage | DefVarPackage + DataRefObject := DataObject | ObjectReference | DDBHandle + ByteConst := BytePrefix ByteData + BytePrefix := 0x0A + WordConst := WordPrefix WordData + WordPrefix := 0x0B + DWordConst := DWordPrefix DWordData + DWordPrefix := 0x0C + QWordConst := QWordPrefix QWordData + QWordPrefix := 0x0E + ConstObj := ZeroOp | OneOp | OnesOp + ByteData := 0x00 - 0xFF + WordData := ByteData[0:7] ByteData[8:15] + // 0x0000-0xFFFF + DWordData := WordData[0:15] WordData[16:31] + // 0x00000000-0xFFFFFFFF + QWordData := DWordData[0:31] DWordData[32:63] + // 0x0000000000000000-0xFFFFFFFFFFFFFFFF + ZeroOp := 0x00 + OneOp := 0x01 + OnesOp := 0xFF + + @param[in] Integer - Number to be optimized and encoded + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPDataInteger ( + IN UINT64 Integer, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "DATA_INTEGER")); + goto Done; + } + + Status = InternalAmlDataIntegerBuffer ( + Integer, + (VOID **)&(Object->Data), + &(Object->DataSize) + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ACPI Integer 0x%X object\n", __FUNCTION__, Integer)); + goto Done; + } + + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates an Sized Data integer object for use in Buffer objects. Does not + include opcode. + + ByteData := 0x00 - 0xFF + WordData := ByteData[0:7] ByteData[8:15] + // 0x0000-0xFFFF + DWordData := WordData[0:15] WordData[16:31] + // 0x00000000-0xFFFFFFFF + QWordData := DWordData[0:31] DWordData[32:63] + // 0x0000000000000000-0xFFFFFFFFFFFFFFFF + + @param[in] Integer - Number to be optimized and encoded + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +InternalAmlOPSizedData ( + IN UINT64 Integer, + IN UINTN IntegerSize, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "SIZED_DATA_INTEGER")); + goto Done; + } + + Object->DataSize = IntegerSize; + Status = InternalAmlSizedDataBuffer ( + Integer, + Object->DataSize, + (VOID **)&(Object->Data) + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ACPI Integer 0x%X object\n", __FUNCTION__, Integer)); + goto Done; + } + + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a ByteData integer object for use in Buffer objects. Does not + include opcode. + + ByteData := 0x00 - 0xFF + + @param[in] Integer - Number to be placed in object + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPByteData ( + IN UINT8 Integer, + IN OUT LIST_ENTRY *ListHead + ) +{ + return InternalAmlOPSizedData (Integer, sizeof (UINT8), ListHead); +} + +/** + Creates a WordData integer object for use in Buffer objects. Does not + include opcode. + + WordData := 0x0000 - 0xFFFF + + @param[in] Integer - Number to be placed in object + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPWordData ( + IN UINT16 Integer, + IN OUT LIST_ENTRY *ListHead + ) +{ + return InternalAmlOPSizedData (Integer, sizeof (UINT16), ListHead); +} + +/** + Creates a DWordData integer object for use in Buffer objects. Does not + include opcode. + + DWordData := 0x00000000 - 0xFFFFFFFF + + @param[in] Integer - Number to be placed in object + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPDWordData ( + IN UINT32 Integer, + IN OUT LIST_ENTRY *ListHead + ) +{ + return InternalAmlOPSizedData (Integer, sizeof (UINT32), ListHead); +} + +/** + Creates a QWordData integer object for use in Buffer objects. Does not + include opcode. + + QWordData := 0x00000000_00000000 - 0xFFFFFFFF_FFFFFFFF + + @param[in] Integer - Number to be placed in object + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPQWordData ( + IN UINT64 Integer, + IN OUT LIST_ENTRY *ListHead + ) +{ + return InternalAmlOPSizedData (Integer, sizeof (UINT64), ListHead); +} + +/** + Creates a data string object + + ComputationalData := String + + String := StringPrefix AsciiCharList NullChar + StringPrefix := 0x0D + AsciiCharList := Nothing | + AsciiChar := 0x01 - 0x7F + NullChar := 0x00 + + @param[in] String - String to be encoded + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPDataString ( + IN CHAR8 *String, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + UINT8 *Data; + UINTN DataSize; + UINTN Index; + + if ((String == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + // Validate all characters + DataSize = AsciiStrLen (String); + for (Index = 0; Index < DataSize; Index++) { + if (String[Index] < 0x01) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Invalid character String[%d] : %a\n", + __FUNCTION__, + Index, + String + )); + return Status; + } + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, String)); + goto Done; + } + + // AML_STRING_PREFIX + String + NULL Terminator + DataSize += 2; + Data = AllocatePool (DataSize); + if (Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: String Space Allocation %a\n", + __FUNCTION__, + String + )); + goto Done; + } + + Data[0] = AML_STRING_PREFIX; + CopyMem (&Data[1], String, DataSize - 1); + + // DataString Complete, Put into Object + Object->Data = Data; + Object->DataSize = DataSize; + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a data buffer AML object from an array + + This will take the passed in buffer and generate an AML Object from that + buffer + + @param[in] Buffer - Buffer to be placed in AML Object + @param[in] BufferSize - Size of Buffer to be copied into Object + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPDataBufferFromArray ( + IN VOID *Buffer, + IN UINTN BufferSize, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if ((Buffer == NULL) || (BufferSize == 0) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Object = NULL; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start Data Buffer object\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocatePool (BufferSize); + Object->DataSize = BufferSize; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: Data Buffer allocate failed\n", __FUNCTION__)); + goto Done; + } + + CopyMem (Object->Data, Buffer, BufferSize); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.36 EISAID (EISA ID String To Integer Conversion Macro) + + Syntax: + EISAID (EisaIdString) => DWordConst + + Arguments: + The EisaIdString must be a String object of the form "UUUNNNN", where "U" + is an uppercase letter and "N" is a hexadecimal digit. No asterisks or other + characters are allowed in the string. + + Description: + Converts EisaIdString, a 7-character text string argument, into its + corresponding 4-byte numeric EISA ID encoding. It can be used when declaring + IDs for devices that have EISA IDs. + + Encoded EISA ID Definition - 32-bits + bits[15:0] - three character compressed ASCII EISA ID. * + bits[31:16] - binary number + * Compressed ASCII is 5 bits per character 0b00001 = 'A' 0b11010 = 'Z' + + + Example: + EISAID ("PNP0C09") // This is a valid invocation of the macro. + + @param[in] String - EISA ID string. + @param[in,out] ListHead - Head of Linked List of all AML Objects +**/ +EFI_STATUS +EFIAPI +AmlOPEisaId ( + IN CHAR8 *String, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + UINT32 EncodedEisaId; + UINT8 i; + + EncodedEisaId = 0; + + if ((String == NULL) || (ListHead == NULL)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid parameter, inputs cannot == NULL.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if (AsciiStrLen (String) != 0x7) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid length for 'String' parameter.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + // + // Verify String is formatted as "UUUNNNN". + // + for (i = 0; i <= 0x6; i++) { + // + // If first 3 characters are not uppercase alpha or last 4 characters are not hexadecimal + // + if (((i <= 0x2) && (!IS_ASCII_UPPER_ALPHA (String[i]))) || + ((i >= 0x3) && (!IS_ASCII_HEX_DIGIT (String[i])))) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid EISA ID string format!\n", __FUNCTION__)); + DEBUG ((DEBUG_ERROR, " Input String must be formatted as 'UUUNNNN'.\n")); + return EFI_INVALID_PARAMETER; + } + } + + // + // Convert string to 4-byte EISA ID encoding. + // Ex: 'PNP0A03' encodes to '0x30AD041' + // + EncodedEisaId = ((((String[0] - AML_NAME_CHAR_A + 1) & 0x1f) << 10) + + (((String[1] - AML_NAME_CHAR_A + 1) & 0x1f) << 5) + + (((String[2] - AML_NAME_CHAR_A + 1) & 0x1f) << 0) + + (UINT32)(AsciiStrHexToUint64 (&String[3]) << 16)); + + // + // Swap bytes of upper and lower WORD to format EISA ID with proper endian-ness. + // + EncodedEisaId = Swap4Bytes (EncodedEisaId); + + // + // Insert DWordPrefix into list. + // Note: EncodedEisaId will always be 32-bits, resulting in DWordConst. + // + Status = AmlOPDataInteger (EncodedEisaId, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Unable to create ACPI DWordConst from Encoded EISA ID.\n", __FUNCTION__)); + return Status; + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c new file mode 100644 index 0000000000000000000000000000000000000000..d9ba614597f90fe307b0b09af10e59a32a341da3 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlExpressionOpcodes.c @@ -0,0 +1,1291 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +// ---------------------------------------------------------------------------- +// Expression Opcodes Encoding +// ---------------------------------------------------------------------------- +// ExpressionOpcode := DefAcquire | DefAdd | DefAnd | DefBuffer | DefConcat | +// DefConcatRes | DefCondRefOf | DefCopyObject | DefDecrement | +// DefDerefOf | DefDivide | DefFindSetLeftBit | DefFindSetRightBit | +// DefFromBCD | DefIncrement | DefIndex | DefLAnd | DefLEqual | +// DefLGreater | DefLGreaterEqual | DefLLess | DefLLessEqual | DefMid | +// DefLNot | DefLNotEqual | DefLoadTable | DefLOr | DefMatch | DefMod | +// DefMultiply | DefNAnd | DefNOr | DefNot | DefObjectType | DefOr | +// DefPackage | DefVarPackage | DefRefOf | DefShiftLeft | DefShiftRight | +// DefSizeOf | DefStore | DefSubtract | DefTimer | DefToBCD | DefToBuffer | +// DefToDecimalString | DefToHexString | DefToInteger | DefToString | +// DefWait | DefXOr | MethodInvocation +// ---------------------------------------------------------------------------- + +/** + Creates a Buffer (BufferSize) {Initializer} => Buffer Object + + Initializers must be created between AmlStart and AmlClose Phase + + DefBuffer := BufferOp PkgLength BufferSize ByteList + BufferOp := 0x11 + BufferSize := TermArg => Integer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] BufferSize - Requested BufferSize, Encoded value will be + MAX (BufferSize OR Child->DataSize) + @param[in,out] ListHead - Linked list has completed Buffer Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlBuffer ( + IN AML_FUNCTION_PHASE Phase, + IN UINTN BufferSize, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + UINTN InternalBufferSize; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // iASL compiler 20200110 only keeps lower 32 bits of size. We'll error if + // someone requests something >= 4GB size. Have a message with this to be + // very specific + if (BufferSize >= SIZE_4GB) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: BufferSize=0x%X >= 4GB\n", __FUNCTION__, BufferSize)); + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start the Buffer Object + Status = InternalAppendNewAmlObject (&Object, "BUFFER", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start BUFFER object\n", __FUNCTION__)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Buffer PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // Start BufferSize + Status = InternalAppendNewAmlObject (&Object, "BUFFERSIZE", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start BUFFERSIZE object\n", __FUNCTION__)); + goto Done; + } + + // ByteList is too complicated and must be added outside + break; + + case AmlClose: + // ByteList items should be closed already + + // Close BufferSize + Status = InternalAmlLocateObjectByIdentifier ( + &Object, + "BUFFERSIZE", + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Fail locate BufferSize object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collect BufferSize children\n", __FUNCTION__)); + goto Done; + } + + // Set BufferSize Object to correct value and size. + // BufferSize should be from zero (no Child Data) to MAX of requested + // BufferSize or size required for ChildObject->Data. + InternalBufferSize = MAX (BufferSize, ChildObject->DataSize); + // iASL compiler 20200110 only keeps lower 32 bits of size. We'll error if + // someone requests something >= 4GB size. + if (InternalBufferSize >= SIZE_4GB) { + Status = EFI_BAD_BUFFER_SIZE; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: BufferSize 0x%X >= 4GB\n", + __FUNCTION__, + InternalBufferSize + )); + goto Done; + } + + Status = InternalAmlDataIntegerBuffer ( + InternalBufferSize, + (VOID **)&Object->Data, + &Object->DataSize + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: calc BufferSize\n", __FUNCTION__)); + goto Done; + } + + if ((ChildObject->DataSize != 0) && (ChildObject->Data != NULL)) { + // Make room for ChildObject->Data + Object->Data = ReallocatePool ( + Object->DataSize, + Object->DataSize + + ChildObject->DataSize, + Object->Data + ); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: to reallocate BufferSize\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + CopyMem ( + &Object->Data[Object->DataSize], + ChildObject->Data, + ChildObject->DataSize + ); + Object->DataSize += ChildObject->DataSize; + } + + // Free Child Object since it has been consumed + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: close PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // Complete Buffer object with all data + Status = InternalAmlLocateObjectByIdentifier (&Object, "BUFFER", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locate Buffer object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + + // Buffer must have at least PkgLength BufferSize + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: No Buffer Data\n", __FUNCTION__)); + goto Done; + } + + // BufferOp is one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Buffer allocate failed\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Object->Data[0] = AML_BUFFER_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + // Free Child Object since it has been consumed + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a LEqual (Source1, Source2) => Boolean + + Source1 and Source2 operands must be created between AmlStart and AmlClose Phase + + DefLEqual := LequalOp Operand Operand + LequalOp := 0x93 + Operand := TermArg => Integer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed LEqual Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlLEqual ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start the LEqual Object + Status = InternalAppendNewAmlObject (&Object, "LEQUAL", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start LEQUAL object\n", __FUNCTION__)); + goto Done; + } + + // Operands are too complicated and must be added outside + break; + + case AmlClose: + + // Close LEqual + Status = InternalAmlLocateObjectByIdentifier ( + &Object, + "LEQUAL", + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Fail locate LEqual object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + + // LEqual must have at least two operands + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: No LEqual Args\n", __FUNCTION__)); + goto Done; + } + + // LequalOp is one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Buffer allocate failed\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Object->Data[0] = AML_LEQUAL_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + // Free Child Object since it has been consumed + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/* + Creates (NumElements) section of a Package: {PackageList} => Package + + Initializers must be created between AmlStart and AmlClose Phase + Internal only function no public reference or documentation needed. + + NumElements := ByteData + VarNumElements := TermArg => Integer + PackageElementList := Nothing | + PackageElement := DataRefObject | NameString + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] NumElements - Number of elements in the package. If 0, size + is calculated from the PackageList. + @param[in,out] ListHead - Linked list has completed Package Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +*/ +EFI_STATUS +EFIAPI +InternalAmlNumElements ( + IN AML_FUNCTION_PHASE Phase, + IN OUT UINTN *NumElements, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + ChildCount = 0; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start Number of Elements Object + Status = InternalAppendNewAmlObject (&Object, "NUM_ELEMENTS", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NUM_ELEMENTS object\n", __FUNCTION__)); + goto Done; + } + + // PackageList is too complicated and must be added outside + break; + + case AmlClose: + // PackageList items should be closed already + + // Close Number of Elements Object + Status = InternalAmlLocateObjectByIdentifier ( + &Object, + "NUM_ELEMENTS", + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Fail locate NUM_ELEMENTS object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collect NUM_ELEMENTS children\n", __FUNCTION__)); + goto Done; + } + + // We do not have to change anything for NumElements >= Child Count + if (*NumElements == 0) { + *NumElements = ChildCount; + } else if (*NumElements < ChildCount) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: NumElements < ChildCount.\n", __FUNCTION__)); + Status = EFI_INVALID_PARAMETER; + goto Done; + } + + if (*NumElements <= MAX_UINT8) { + Object->DataSize = 1; + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: NumElements allocate failed\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Object->Data[0] = (UINT8)*NumElements; + } else { + Status = InternalAmlDataIntegerBuffer ( + *NumElements, + (VOID **)&Object->Data, + &Object->DataSize + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: calc NumElements\n", __FUNCTION__)); + goto Done; + } + } + + if ((ChildObject->DataSize != 0) && (ChildObject->Data != NULL)) { + // Make room for ChildObject->Data + Object->Data = ReallocatePool ( + Object->DataSize, + Object->DataSize + + ChildObject->DataSize, + Object->Data + ); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: to reallocate NumElements\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + CopyMem ( + &Object->Data[Object->DataSize], + ChildObject->Data, + ChildObject->DataSize + ); + Object->DataSize += ChildObject->DataSize; + } + + // Free Child Object since it has been consumed + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a Package (NumElements) {PackageList} => Package + + Initializers must be created between AmlStart and AmlClose Phase + + DefPackage := PackageOp PkgLength NumElements PackageElementList + PackageOp := 0x12 + DefVarPackage := VarPackageOp PkgLength VarNumElements PackageElementList + VarPackageOp := 0x13 + NumElements := ByteData + VarNumElements := TermArg => Integer + PackageElementList := Nothing | + PackageElement := DataRefObject | NameString + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] NumElements - Number of elements in the package. If 0, size + is calculated from the PackageList. + @param[in,out] ListHead - Linked list has completed Package Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlPackage ( + IN AML_FUNCTION_PHASE Phase, + IN UINTN NumElements, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + UINT8 OpCode; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start the Package Object + Status = InternalAppendNewAmlObject (&Object, "PACKAGE", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PACKAGE object\n", __FUNCTION__)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Package PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // Start Number of Elements Object + Status = InternalAmlNumElements (AmlStart, &NumElements, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NUM_ELEMENTS object\n", __FUNCTION__)); + goto Done; + } + + // PackageList is too complicated and must be added outside + break; + + case AmlClose: + // PackageList items should be closed already + + // Close Number of Elements Object + Status = InternalAmlNumElements (AmlClose, &NumElements, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close NUM_ELEMENTS object\n", __FUNCTION__)); + goto Done; + } + + if (NumElements <= MAX_UINT8) { + OpCode = AML_PACKAGE_OP; + } else { + OpCode = AML_VAR_PACKAGE_OP; + } + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: close PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // Complete Package object with all data + Status = InternalAmlLocateObjectByIdentifier (&Object, "PACKAGE", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locate PACKAGE object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + // Package must have at least PkgLength NumElements + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: No Package Data\n", __FUNCTION__)); + goto Done; + } + + // PackageOp and VarPackageOp are both one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Package allocate failed\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Object->Data[0] = OpCode; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + // Free Child Object since it has been consumed + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a Store expression + + Syntax: + Store (Source, Destination) => DataRefObject Destination = Source => DataRefObject + + Store expression must be created between AmlStart and AmlClose Phase. + + DefStore := StoreOp TermArg SuperName + StoreOp := 0x70 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlStore ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + // Start Store expression + Status = InternalAppendNewAmlObject (&Object, "STORE", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot append STORE object\n", __FUNCTION__)); + goto Done; + } + + // TermArg and SuperName are outside the scope of this object. They must be + // defined as part of a multi-tier call - in between AmlStore(AmlStart,..) and + // AmlStore(AmlClose,...) - when creating the Store expression. + break; + + case AmlClose: + // TermArg and SuperName must have been created and closed by now. + Status = InternalAmlLocateObjectByIdentifier (&Object, "STORE", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating STORE Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Store() has no child data.\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (ChildObject->DataSize + 1); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for Store()\n", __FUNCTION__)); + goto Done; + } + + // Store Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + + // Fill out Store object + Object->Data[0] = AML_STORE_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a Shift Left or Right expression + + Syntax: + ShiftLeft (Source, ShiftCount, Reult) => Integer + Result = Source << ShiftCount => Integer + Result <<= ShiftCount => Integer + + ShiftRight (Source, ShiftCount, Reult) => Integer + Result = Source >> ShiftCount => Integer + Result >>= ShiftCount => Integer + + Shift expression must be created between AmlStart and AmlClose Phase. + + DefShiftLeft := ShiftOp Operand ShiftCount Target + ShiftOp := 0x79 or 0x7A + ShiftCount := TermArg => Integer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] ShiftOp - Specifies whether to shift left or shift + right. + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlShift ( + IN AML_FUNCTION_PHASE Phase, + IN UINT8 ShiftOp, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start Store expression + Status = InternalAppendNewAmlObject (&Object, "SHIFT", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot append SHIFT object\n", __FUNCTION__)); + goto Done; + } + + // Operand, ShiftCount, and Target are outside the scope of this object. They must be + // defined as part of a multi-tier call - in between AmlShift(AmlStart,..) and + // AmlShift(AmlClose,...) - when creating the Shift expression. + + break; + + case AmlClose: + // Operand, ShiftCount, and Target must have been created and closed by now. + Status = InternalAmlLocateObjectByIdentifier (&Object, "SHIFT", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating SHIFT Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Store() has no child data.\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (ChildObject->DataSize + 1); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for Store()\n", __FUNCTION__)); + goto Done; + } + + // Store Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + + // Fill out Store object + Object->Data[0] = ShiftOp; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a Shift Left expression + + Syntax: + ShiftLeft (Source, ShiftCount, Result) => Integer + Result = Source << ShiftCount => Integer + Result <<= ShiftCount => Integer + + Shift expression must be created between AmlStart and AmlClose Phase. + + DefShiftLeft := ShiftLeftOp Operand ShiftCount Target + ShiftLeftOp := 0x79 + ShiftCount := TermArg => Integer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlShiftLeft ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlShift (Phase, AML_SHIFT_LEFT_OP, ListHead); + return Status; +} + +/** + Creates a Shift Right expression + + Syntax: + ShiftRight (Source, ShiftCount, Reult) => Integer + Result = Source >> ShiftCount => Integer + Result >>= ShiftCount => Integer + + Shift expression must be created between AmlStart and AmlClose Phase. + + DefShiftRight := ShiftRightOp Operand ShiftCount Target + ShiftRightOp := 0x7A + ShiftCount := TermArg => Integer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlShiftRight ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlShift (Phase, AML_SHIFT_RIGHT_OP, ListHead); + return Status; +} + +/** + Creates a Find First Set Bit AML object for + both right and left searches. + + Syntax: + FindSetLeftBit (Source, Result) => Integer + + FindSetRightBit (Source, Result) => Integer + + Bit Fields must be created between AmlStart and AmlClose Phase. + + DefFindSetLeftBit := FindSetLeftBitOp Operand Target + FindSetLeftBitOp := 0x81 + + DefFindSetRightBit := FindSetRightBitOp Operand Target + FindSetRightBitOp := 0x82 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] FindSetOp - Specifies whether to search left or search + right. + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlFindSetBit ( + IN AML_FUNCTION_PHASE Phase, + IN UINT8 FindSetOp, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start Store expression + Status = InternalAppendNewAmlObject (&Object, "FINDSET", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot append FIND_SET object\n", __FUNCTION__)); + goto Done; + } + + // Source and Result are outside the scope of this object. They must be + // defined as part of a multi-tier call - in between AmlFindSet(AmlStart,..) and + // AmlFindSet(AmlClose,...) - when creating the FindSetBit expression. + + break; + + case AmlClose: + // Source and Result must have been created and closed by now. + Status = InternalAmlLocateObjectByIdentifier (&Object, "FINDSET", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating FIND_SET Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Store() has no child data.\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (ChildObject->DataSize + 1); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for Store()\n", __FUNCTION__)); + goto Done; + } + + // Store Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + + // Fill out Store object + Object->Data[0] = FindSetOp; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a FindSetLeftBit AML Object + + Syntax: + FindSetLeftBit (Source, Result) => Integer + + FindSetLeftBit expression must be created between + AmlStart and AmlClose Phase. + + DefFindSetLeftBit := FindSetLeftBitOp Operand Target + FindSetLeftBitOp := 0x81 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlFindSetLeftBit ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlFindSetBit (Phase, AML_FIND_SET_LEFT_BIT_OP, ListHead); + return Status; +} + +/** + Creates a FindSetRightBit AML Object + + Syntax: + FindSetRightBit (Source, Result) => Integer + + FindSetRightBit expression must be created between + AmlStart and AmlClose Phase. + + DefFindSetRightBit := FindSetRightBit Operand Target + FindSetRightBit := 0x82 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlFindSetRightBit ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlFindSetBit (Phase, AML_FIND_SET_RIGHT_BIT_OP, ListHead); + return Status; +} + +/** + Creates a Decrement expression + + Syntax: + Decrement (Minuend) => Integer + Minuend-- => Integer + + Creates object to decrement Minuend. + + DefDecrement := DecrementOp SuperName + DecrementOp := 0x76 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlDecrement ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + switch (Phase) { + case AmlStart: + // Start decrement expression + Status = InternalAppendNewAmlObject (&Object, "DECREMENT", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot append DECREMENT object\n", __FUNCTION__)); + goto Done; + } + + // Minuend is outside the scope of this object. It must be + // defined as part of a multi-tier call - in between AmlDecrement(AmlStart,..) and + // AmlDecrement(AmlClose,...) - when creating the Decrement expression. + + break; + + case AmlClose: + // Minuend must created and closed by now. + Status = InternalAmlLocateObjectByIdentifier (&Object, "DECREMENT", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating DECREMENT Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Store() has no child data.\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (ChildObject->DataSize + 1); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for Store()\n", __FUNCTION__)); + goto Done; + } + + // Decrement Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + + // Fill out Decrement object + Object->Data[0] = AML_DECREMENT_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..a0db35628ab436fc30c27404826ef66ac6d11072 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf @@ -0,0 +1,50 @@ +## @file +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmlGenerationLib + FILE_GUID = 8F62C8D1-B67F-4AFB-9179-54384F1A6163 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = DXE_DRIVER UEFI_DRIVER HOST_APPLICATION + +[Sources.common] + LocalAmlObjects.h + LocalAmlObjects.c + LocalAmlLib.h + AmlAssistFunctions.c + AmlObjectsDebug.c + AmlNameString.c + AmlDataObjects.c + AmlNamespaceModifierObjects.c + AmlPkgLength.c + AmlNamedObject.c + AmlTable.c + AmlStatementOpcodes.c + AmlResourceDescriptor.c + AmlExpressionOpcodes.c + AmlArgObjects.c + AmlLocalObjects.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + +[Protocols] + +[Pcd] + +[Depex] + TRUE diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c new file mode 100644 index 0000000000000000000000000000000000000000..0a0e2d2c64a71289d05e7e7703fdb0ae00dce54c --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlLocalObjects.c @@ -0,0 +1,155 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + Fill the DataBuffer with correct Local Opcode based on provided argument number + Valid Argument numbers are 0, 1, 2, 3, 4, 5 and 6. + AML supports max 7 Local variables, i.e., Local1, Local2 ... Local6. + + @param[in] LocalN - Local variable Number + @param[out] ReturnData - Allocated DataBuffer with encoded integer + @param[out] ReturnDataSize - Size of ReturnData + + @return EFI_SUCCESS - Successful completion + @return EFI_OUT_OF_RESOURCES - Failed to allocate ReturnDataBuffer + @return EFI_INVALID_PARAMETER - Invalid LocalN provided. +**/ +EFI_STATUS +EFIAPI +InternalAmlLocalBuffer ( + IN OUT UINT8 LocalN, + OUT VOID **ReturnData, + OUT UINTN *ReturnDataSize + ) +{ + UINT8 *Data; + UINTN DataSize; + + Data = AllocateZeroPool (sizeof (UINT8)); + if (Data == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Failed to create Data Buffer.\n", + __FUNCTION__ + )); + return EFI_OUT_OF_RESOURCES; + } + + DataSize = 1; + switch (LocalN) { + case 0: + Data[0] = AML_LOCAL0; + break; + case 1: + Data[0] = AML_LOCAL1; + break; + case 2: + Data[0] = AML_LOCAL2; + break; + case 3: + Data[0] = AML_LOCAL3; + break; + case 4: + Data[0] = AML_LOCAL4; + break; + case 5: + Data[0] = AML_LOCAL5; + break; + case 6: + Data[0] = AML_LOCAL6; + break; + case 7: + Data[0] = AML_LOCAL7; + break; + default: + FreePool (Data); + return EFI_INVALID_PARAMETER; + } + + *ReturnData = (VOID *)Data; + *ReturnDataSize = DataSize; + + return EFI_SUCCESS; +} + +/** + Creates an LocalN Opcode object + + Local Objects Encoding + LocalObj := Local0Op | Local1Op | Local2Op | Local3Op | Local4Op | Local5Op | Local6Op | Local7Op + Local0Op := 0x60 + Local1Op := 0x61 + Local2Op := 0x62 + Local3Op := 0x63 + Local4Op := 0x64 + Local5Op := 0x65 + Local6Op := 0x66 + Local7Op := 0x67 + + @param[in] LocalN - Argument Number to be encoded + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail +**/ +EFI_STATUS +EFIAPI +AmlOPLocalN ( + IN UINT8 LocalN, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Start %a object\n", + __FUNCTION__, + "LOCALN_OPCODE" + )); + goto Done; + } + + Status = InternalAmlLocalBuffer ( + LocalN, + (VOID **)&(Object->Data), + &(Object->DataSize) + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: ACPI Argument 0x%X object\n", + __FUNCTION__, + LocalN + )); + goto Done; + } + + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNameString.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNameString.c new file mode 100644 index 0000000000000000000000000000000000000000..620a2211598678b50c3de020001623e66d1e1bb9 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNameString.c @@ -0,0 +1,573 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +#define MAX_NAME_SEG_COUNT 255 + +/* + Is character a RootChar + + @param[in] TestChar - Character to check + + @return TRUE - Character is a RootChar + @return FALSE - Character is not a RootChar + */ +BOOLEAN +InternalIsRootChar ( + IN CHAR8 TestChar + ) +{ + if (TestChar == AML_ROOT_CHAR) { + return TRUE; + } + + return FALSE; +} + +/* + Is character a ParentPrefixChar + + @param[in] TestChar - Character to check + + @return TRUE - Character is a ParentPrefixChar + @return FALSE - Character is not a ParentPrefixChar + */ +BOOLEAN +InternalIsParentPrefixChar ( + IN CHAR8 TestChar + ) +{ + if (TestChar == AML_PARENT_PREFIX_CHAR) { + return TRUE; + } + + return FALSE; +} + +/* + Is character a LeadNameChar = '_', 'A' - 'Z' + + @param[in] TestChar - Character to check + + @return TRUE - Character is a LeadNameChar + @return FALSE - Character is not a LeadNameChar + */ +BOOLEAN +InternalIsLeadNameChar ( + IN CHAR8 TestChar + ) +{ + if ( // Allowed LeadNameChars '_', 'A'-'Z' + (TestChar == AML_NAME_CHAR__) || + ((TestChar >= AML_NAME_CHAR_A) && + (TestChar <= AML_NAME_CHAR_Z)) + ) + { + return TRUE; + } + + return FALSE; +} + +/* + Is character a DigitChar = '0' - '9' + + @param[in] TestChar - Character to check + + @return TRUE - Character is a DigitChar + @return FALSE - Character is not a DigitChar + */ +BOOLEAN +InternalIsDigitChar ( + IN CHAR8 TestChar + ) +{ + if ( // Allowed DigitChars '0'-'9' + (TestChar >= AML_DIGIT_CHAR_0) && + (TestChar <= AML_DIGIT_CHAR_9) + ) + { + return TRUE; + } + + return FALSE; +} + +/* + Is character a NameChar = LeadNameChar | DigitChar + + @param[in] TestChar - Character to check + + @return TRUE - Character is a NameChar + @return FALSE - Character is not a NameChar + */ +BOOLEAN +InternalIsNameChar ( + IN CHAR8 TestChar + ) +{ + if ( // Allowed LeadNameChar and DigitChars + InternalIsDigitChar (TestChar) || + InternalIsLeadNameChar (TestChar) + ) + { + return TRUE; + } + + return FALSE; +} + +/* + Is character a NameSeg separator + + @param[in] TestChar - Character to check + + @return TRUE - Character is a NameChar + @return FALSE - Character is not a NameChar + */ +BOOLEAN +InternalIsNameSegSeparator ( + IN CHAR8 TestChar + ) +{ + if (TestChar == '.') { + return TRUE; + } + + return FALSE; +} + +/** + Creates a NameSeg AML object and inserts it into the List + + NameSeg := + + NameSegs shorter than 4 characters are filled with trailing underscores + + @param[in] Name - NameSeg + @param[in,out] ListHead - Linked list has NameSeg after call + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlNameSeg ( + IN CHAR8 *Name, + IN OUT LIST_ENTRY *ListHead + ) +{ + AML_OBJECT_INSTANCE *Object; + UINT8 *NameSeg; + UINTN NameLen; + EFI_STATUS Status; + + if (Name == NULL) { + return EFI_INVALID_PARAMETER; + } + + NameLen = AsciiStrLen (Name); + Status = EFI_DEVICE_ERROR; + Object = NULL; + NameSeg = NULL; + // parameter validation + if ((NameLen == 0) || (NameLen > 4)) { + return EFI_INVALID_PARAMETER; + } + + if (!InternalIsLeadNameChar (Name[0])) { + return EFI_INVALID_PARAMETER; + } + + for (UINT8 i = 1; NameLen > 1 && i < NameLen; i++) { + if (!InternalIsNameChar (Name[i])) { + return EFI_INVALID_PARAMETER; + } + } + + NameSeg = AllocateZeroPool (4); + if (NameSeg == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + CopyMem (NameSeg, Name, NameLen); + + if (NameLen < 4) { + SetMem (&NameSeg[NameLen], 4 - NameLen, '_'); + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (Object != NULL) { + if (!EFI_ERROR (Status)) { + Object->Data = NameSeg; + Object->DataSize = 4; + Object->Completed = TRUE; + } else { + InternalFreeAmlObject (&Object, ListHead); + FreePool (NameSeg); + } + } + + return Status; +} + +/** + Creates a Namestring AML Object and inserts it into the linked list + + LeadNameChar := 'A'-'Z' | '_' + DigitChar := '0'-'9' + NameChar := DigitChar | LeadNameChar + RootChar := '\' + ParentPrefixChar := '^' + + 'A'-'Z' := 0x41 - 0x5A + '_' := 0x5F + '0'-'9' := 0x30 - 0x39 + '\' := 0x5C + '^' := 0x5E + + NameSeg := + // Notice that NameSegs shorter than 4 characters are filled with + // trailing underscores ('_'s). + NameString := | + PrefixPath := Nothing | <'^' PrefixPath> + NamePath := NameSeg | DualNamePath | MultiNamePath | NullName + + DualNamePath := DualNamePrefix NameSeg NameSeg + DualNamePrefix := 0x2E + MultiNamePath := MultiNamePrefix SegCount NameSeg(SegCount) + MultiNamePrefix := 0x2F + + SegCount := ByteData + + Note:SegCount can be from 1 to 255. For example: MultiNamePrefix(35) is + encoded as 0x2f 0x23 and followed by 35 NameSegs. So, the total encoding + length will be 1 + 1 + 35*4 = 142. Notice that: DualNamePrefix NameSeg + NameSeg has a smaller encoding than the encoding of: MultiNamePrefix(2) + NameSeg NameSeg + + SimpleName := NameString | ArgObj | LocalObj + SuperName := SimpleName | DebugObj | Type6Opcode + NullName := 0x00 + Target := SuperName | NullName + + @param[in] String - Null Terminated NameString Representation + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail + **/ +EFI_STATUS +EFIAPI +AmlOPNameString ( + IN CHAR8 *String, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + CHAR8 *NameString; + CHAR8 *NameStringPrefix; + UINTN NameStringBufferSize; + UINTN NameStringSize; + UINTN NameStringPrefixSize; + UINTN NameSegCount; + UINTN StringIndex; + UINTN StringLength; + UINTN NameSegIndex; + BOOLEAN FoundRootChar; + BOOLEAN FoundParentPrefixChar; + BOOLEAN FoundParenthesisOpenChar; + BOOLEAN FoundParenthesisCloseChar; + + if ((String == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + NameString = NULL; + FoundRootChar = FALSE; + FoundParentPrefixChar = FALSE; + NameStringBufferSize = 0; + FoundParenthesisOpenChar = FALSE; + FoundParenthesisCloseChar = FALSE; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Create a buffer to fit NameSeg [4] * max NameSegCount [255] + NameStringBufferSize = 4 * MAX_NAME_SEG_COUNT; + NameString = AllocateZeroPool (NameStringBufferSize); + // Create arbitrarily large RootChar\ParentPrefixChar buffer + NameStringPrefix = AllocateZeroPool (NameStringBufferSize); + + // Calculate length of required space + StringLength = AsciiStrLen (String); + NameStringSize = 0; + NameStringPrefixSize = 0; + NameSegIndex = 0; + NameSegCount = 0; + for (StringIndex = 0; StringIndex < StringLength; StringIndex++) { + if (NameStringPrefixSize >= NameStringBufferSize) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Exceeded ParentPrefixChar support at offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } + + if (InternalIsRootChar (String[StringIndex])) { + if (NameSegCount != 0) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: RootChar at offset=%d of String=%a\n", __FUNCTION__, StringIndex, String)); + goto Done; + } + + if (FoundRootChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: NameString=%a contains more than 1 RootChar.\n", __FUNCTION__, String)); + goto Done; + } + + if (FoundParentPrefixChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: NameString=%a contains RootChar and ParentPrefixChar.\n", __FUNCTION__, String)); + goto Done; + } + + // RootChar; increment NameStringSize + NameStringPrefix[NameStringPrefixSize] = String[StringIndex]; + NameStringPrefixSize++; + FoundRootChar = TRUE; + } else if (InternalIsParentPrefixChar (String[StringIndex])) { + if (NameSegCount != 0) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: ParentPrefixChar at offset=%d of String=%a\n", __FUNCTION__, StringIndex, String)); + goto Done; + } + + if (FoundRootChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: NameString=%a contains RootChar and ParentPrefixChar.\n", __FUNCTION__, String)); + goto Done; + } + + // ParentPrefixChar; increment NameStringSize + NameStringPrefix[NameStringPrefixSize] = String[StringIndex]; + NameStringPrefixSize++; + FoundParentPrefixChar = TRUE; + } else if (!InternalIsNameChar (String[StringIndex])) { + if (InternalIsNameSegSeparator (String[StringIndex])) { + if (NameSegIndex == 0) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Invalid NameSeg separator at offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } else { + NameSegIndex = 0; + } + } else if (String[StringIndex] == '(') { + if (FoundParenthesisOpenChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Invalid Parenthesis at offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } + + FoundParenthesisOpenChar = TRUE; + } else if (String[StringIndex] == ')') { + if (FoundParenthesisCloseChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Invalid Parenthesis at offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } else if (!FoundParenthesisOpenChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: No Open Parenthesis before offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } + + FoundParenthesisCloseChar = TRUE; + } else { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Unsupported character at offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } + } else { + // Must be NameChar + if (FoundParenthesisOpenChar || FoundParenthesisCloseChar) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: NameChar after Parenthesis at offset=%d of String=%a\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } else if ((NameSegIndex == 0) && InternalIsDigitChar (String[StringIndex])) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: must be LeadNameChar at offset=%d of String=%a'\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } + + if (NameSegIndex >= 4) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: NameSeg > 4 characters at offset=%d of String=%a'\n", + __FUNCTION__, + StringIndex, + String + )); + goto Done; + } else { + if (NameSegIndex == 0) { + NameSegCount++; + if (NameSegCount > MAX_NAME_SEG_COUNT) { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: Max NameSegCount=%d reached at offset=%d of String=%a'\n", + __FUNCTION__, + MAX_NAME_SEG_COUNT, + StringIndex, + String + )); + goto Done; + } + } + + NameString[NameStringSize] = String[StringIndex]; + NameStringSize++; + NameSegIndex++; + if ((StringIndex + 1 >= StringLength) || + !InternalIsNameChar (String[StringIndex + 1])) + { + // Extend in progress NameSeg with '_'s + if (NameSegIndex < 4) { + SetMem (&NameString[NameStringSize], 4 - NameSegIndex, '_'); + NameStringSize += 4 - NameSegIndex; + } + } + } + } + } + + // Create AML Record with NameString contents from above + // Copy in RootChar or ParentPrefixChar(s) + if (NameStringPrefixSize != 0) { + Object->Data = ReallocatePool ( + Object->DataSize, + NameStringPrefixSize, + Object->Data + ); + CopyMem ( + &Object->Data[Object->DataSize], + NameStringPrefix, + NameStringPrefixSize + ); + Object->DataSize += NameStringPrefixSize; + FreePool (NameStringPrefix); + } + + // Set up for Dual/MultiName Prefix + if (NameSegCount > MAX_NAME_SEG_COUNT) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: Exceeded MaxNameSegCount in NameString=%a\n", __FUNCTION__, String)); + goto Done; + } else if (NameSegCount == 0) { + Status = EFI_INVALID_PARAMETER; + DEBUG ((DEBUG_ERROR, "%a: ERROR: Must be at least one NameSeg in NameString=%a\n", __FUNCTION__, String)); + goto Done; + } else if (NameSegCount == 1) { + // Single NameSeg + Object->Data = ReallocatePool ( + Object->DataSize, + Object->DataSize + NameStringSize, + Object->Data + ); + } else if (NameSegCount == 2) { + Object->Data = ReallocatePool ( + Object->DataSize, + Object->DataSize + NameStringSize + 1, + Object->Data + ); + Object->Data[Object->DataSize] = AML_DUAL_NAME_PREFIX; + Object->DataSize += 1; + } else { + Object->Data = ReallocatePool ( + Object->DataSize, + Object->DataSize + NameStringSize + 2, + Object->Data + ); + Object->Data[Object->DataSize] = AML_MULTI_NAME_PREFIX; + Object->Data[Object->DataSize + 1] = NameSegCount & 0xFF; + Object->DataSize += 2; + } + + // Copy NameString data over. From above must be at least one NameSeg + CopyMem (&Object->Data[Object->DataSize], NameString, NameStringSize); + Object->DataSize += NameStringSize; + FreePool (NameString); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + if (NameString != NULL) { + FreePool (NameString); + } + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNamedObject.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNamedObject.c new file mode 100644 index 0000000000000000000000000000000000000000..2880adb117cc4c9ec974e7a218869afcfd023d9b --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNamedObject.c @@ -0,0 +1,2135 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +#define METHOD_ARGS_MAX 7 +#define MAX_SYNC_LEVEL 0x0F +#define GENERIC_FIELD_IDENTIFIER "FIELD" + +/** + Creates a Device (ObjectName, Object) + + Object must be created between AmlStart and AmlClose Phase + + DefName := DeviceOp PkgLength NameString TermList + NameOp := ExtOpPrefix 0x82 + ExtOpPrefix := 0x5B + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] String - Object name + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlDevice ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *String, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (String == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start Device for %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PkgLength for %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Insert required NameString + Status = AmlOPNameString (String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Insert NameString for %a object\n", __FUNCTION__, String)); + goto Done; + } + + // TermList is too complicated and must be added outside + break; + + case AmlClose: + // TermList should be closed already + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close PkgLength for %a object\n", __FUNCTION__, String)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, String)); + goto Done; + } + + // Device Op is two bytes + Object->DataSize = ChildObject->DataSize + 2; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, String)); + goto Done; + } + + Object->Data[0] = AML_EXT_OP; + Object->Data[1] = AML_EXT_DEVICE_OP; + CopyMem ( + &Object->Data[2], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates an AccessField + + AccessField := 0x01 AccessType AccessAttrib + + @param[in] AccessType - Access type for field member + @param[in] AccessAttribute - Access attribute for field member + @param[in,out] ListHead - Linked list containing AML objects + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlAccessField ( + IN EFI_ACPI_FIELD_ACCESS_TYPE_KEYWORDS AccessType, + IN EFI_ACPI_FIELD_ACCESS_ATTRIBUTE_KEYWORDS AccessAttribute, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + // Start new AML object + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start ACCESSFIELD object\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (3); + // AML_ACCESSFIELD_OP + AccessType + AccessAttrib + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for ACCESSFIELD\n", __FUNCTION__)); + goto Done; + } + + Object->Data[0] = AML_FIELD_ACCESS_OP; + Object->Data[1] = (UINT8)AccessType; + Object->Data[2] = (UINT8)AccessAttribute; + Object->DataSize = 3; + + Object->Completed = TRUE; + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates an ExtendedAccessField + + ExtendedAccessField := 0x03 AccessType ExtendedAccessAttrib AccessLength + + @param[in] AccessType - Access type for field member + @param[in] AccessAttribute - Access attribute for field member + @param[in] AccessLength - Specifies the access length for the field member + @param[in,out] ListHead - Linked list containing AML objects + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlExtendedAccessField ( + IN EFI_ACPI_FIELD_ACCESS_TYPE_KEYWORDS AccessType, + IN EFI_ACPI_FIELD_ACCESS_ATTRIBUTE_KEYWORDS AccessAttribute, + IN UINT8 AccessLength, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + + // Start new AML object + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start EXTENDEDACCESSFIELD object\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (4); + // AML_EXTACCESSFIELD_OP + AccessType + AccessAttrib + AccessLength + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for EXTENDEDACCESSFIELD\n", __FUNCTION__)); + goto Done; + } + + Object->Data[0] = AML_FIELD_EXT_ACCESS_OP; + Object->Data[1] = (UINT8)AccessType; + Object->Data[2] = (UINT8)AccessAttribute; + Object->Data[3] = AccessLength; + Object->DataSize = 4; + + Object->Completed = TRUE; + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates an AccessAs Field Unit + + AccessAs (AccessType, AccessAttribute) + AccessAs (AccessType, AccessAttribute (AccessLength)) + + AccessField := 0x01 AccessType AccessAttrib + AccessType := ByteData // Bits 0:3 - Same as AccessType bits of FieldFlags. + // Bits 4:5 - Reserved + // Bits 7:6 - 0 = AccessAttrib = Normal Access Attributes + // 1 = AccessAttrib = AttribBytes (x) + // 2 = AccessAttrib = AttribRawBytes (x) + // 3 = AccessAttrib = AttribRawProcessBytes (x) + + // x' is encoded as bits 0:7 of the AccessAttrib byte. + The description of bits 7:6 is incorrect and if AttribBytes, + AttribRawBytes, or AttribRawProcessBytes are used here, an + ExtendedAccessField is used with the following definitions + ExtendedAccessField := 0x03 AccessType ExtendedAccessAttrib AccessLength + ExtendedAccessAttrib := ByteData // 0x0B AttribBytes + // 0x0E AttribRawBytes + // 0x0F AttribRawProcess + + AccessAttrib := ByteData // If AccessType is BufferAcc for the SMB or + // GPIO OpRegions, AccessAttrib can be one of + // the following values: + // 0x02 AttribQuick + // 0x04 AttribSendReceive + // 0x06 AttribByte + // 0x08 AttribWord + // 0x0A AttribBlock + // 0x0C AttribProcessCall + // 0x0D AttribBlockProcessCall + + @param[in] AccessType - Access type for field member + @param[in] AccessAttribute - Access attribute for field member + @param[in] AccessLength - Only used if AccessAttribute is AttribBytes, + AttribRawBytes, or AttribRawProcessBytes. + Specifies the access length for the field member + Otherwise, ignored. + @param[in,out] ListHead - Linked list containing AML objects + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPAccessAs ( + IN EFI_ACPI_FIELD_ACCESS_TYPE_KEYWORDS AccessType, + IN EFI_ACPI_FIELD_ACCESS_ATTRIBUTE_KEYWORDS AccessAttribute, + IN UINT8 AccessLength, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + // AcessType parameter check + if (AccessType > BufferAcc) { + return EFI_INVALID_PARAMETER; + } + + // AccessAttrib parameter checking + if ((AccessAttribute >= AttribNormal) && (AccessAttribute <= AttribBlock)) { + if ((AccessAttribute & 1) == 1) { + return EFI_INVALID_PARAMETER; + } + } else if (AccessAttribute > AttribRawProcessBytes) { + return EFI_INVALID_PARAMETER; + } + + // if AccessAttrib requires a length parameter, then an ExtendedAccessField is used + switch (AccessAttribute) { + case AttribBytes: + case AttribRawBytes: + case AttribRawProcessBytes: + Status = InternalAmlExtendedAccessField (AccessType, AccessAttribute, AccessLength, ListHead); + break; + default: + Status = InternalAmlAccessField (AccessType, AccessAttribute, ListHead); + break; + } + + return Status; +} + +/** + Creates an External Object + + External (ObjectName, ObjectType, ReturnType, ParameterTypes) + + Note: ReturnType is not used for AML encoding and is therefore not passed in + to this function. + ParameterTypes is only used if the ObjectType is a MethodObj. It + specifies MethodObj's argument types in a list. For the purposes of + this library, we are passing in the the number of input parameters for + that MethodObj. + + DefExternal := ExternalOp NameString ObjectType ArgumentCount + ExternalOp := 0x15 + ObjectType := ByteData + ArgumentCount := ByteData (0 - 7) + + @param[in] Name - Object name + @param[in] ObjectType - Type of object declared + @param[in] NumArgs - Only used if ObjectType is MethodObj. + Specifies the number of input parameters for + that MethodObj. + Otherwise, ignored. + @param[in,out] ListHead - Linked list that has completed External Object + after AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPExternal ( + IN CHAR8 *Name, + IN UINT8 ObjectType, + IN UINT8 NumArgs, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Name == NULL) || + (NumArgs > METHOD_ARGS_MAX) || + (ObjectType >= InvalidObj) || + (ListHead == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + // Start EXTERNAL object + Status = InternalAppendNewAmlObject (&Object, "EXTERNAL", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Insert required NameString + Status = AmlOPNameString (Name, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a NameString object\n", __FUNCTION__, Name)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, "EXTERNAL", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a has no child data.\n", __FUNCTION__, Name)); + goto Done; + } + + Object->Data = AllocateZeroPool (ChildObject->DataSize + 3); + // AML_EXTERNAL_OP + Name + ObjectType + ArgumentCount + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, Name)); + goto Done; + } + + Object->DataSize = 0; + Object->Data[0] = AML_EXTERNAL_OP; + Object->DataSize++; + CopyMem ( + &Object->Data[Object->DataSize], + ChildObject->Data, + ChildObject->DataSize + ); + Object->DataSize += ChildObject->DataSize; + Object->Data[Object->DataSize] = ObjectType; + Object->DataSize++; + Object->Data[Object->DataSize] = NumArgs; + Object->DataSize++; + + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Locates the AML object that holds the cumulative offset term. + This is the node directly after the node designated by + GENERIC_FIELD_IDENTIFIER in Object->Data. + + @param[out] ReturnObject - Object that contains the offset term + @param[in,out] ListHead - Linked list that contains the GENERIC_FIELD_IDENTIFIER + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlLocateOffsetTerm ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN OUT LIST_ENTRY *ListHead + ) +{ + LIST_ENTRY *Node; + AML_OBJECT_INSTANCE *Object; + UINTN IdentifierSize; + CHAR8 *Identifier; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + Object = NULL; + *ReturnObject = NULL; + Identifier = GENERIC_FIELD_IDENTIFIER; + IdentifierSize = AsciiStrLen (Identifier) + 1; + // Look Backwards and find Node for this Object + Node = ListHead; + do { + Node = GetPreviousNode (ListHead, Node); + Object = AML_OBJECT_INSTANCE_FROM_LINK (Node); + if ((Object->DataSize != 0) && + (Object->DataSize == IdentifierSize) && + (CompareMem ( + Object->Data, + Identifier, + MAX (Object->DataSize, IdentifierSize) + ) == 0)) + { + break; + } + } while (Node != ListHead); + + // Check to make sure FIELD is found, otherwise error + if ((Object->DataSize == 0) || + (Object->DataSize != IdentifierSize) || + CompareMem ( + Object->Data, + Identifier, + (MAX (Object->DataSize, IdentifierSize) != 0) + )) + { + return EFI_DEVICE_ERROR; + } + + // Have found FIELD + Node = GetNextNode (ListHead, Node); + Object = AML_OBJECT_INSTANCE_FROM_LINK (Node); + *ReturnObject = Object; + return EFI_SUCCESS; +} + +/** + Offset (ByteOffset) + + Creates a ReservedField if the passed ByteOffset is larger than + the previous bit length value optionally specified by an AmlOPFieldListItem, + or another Offset call. All offsets are defined starting from zero, based at + the starting address of the parent Operation Region. + + ReservedField := 0x00 PkgLength + + @param[in] ByteLength -Byte offset of the next defined field within + the parent Operation Region + @param[in,out] ListHead - Linked list has completed Offset object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPOffset ( + IN UINT32 ByteOffset, + IN OUT LIST_ENTRY *ListHead + ) +{ + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *OffsetObject; + UINT8 *PkgLength; + UINTN DataLength; + EFI_STATUS Status; + UINT64 InternalOffsetData; + UINT64 BitCount; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + InternalOffsetData = 0; + BitCount = LShiftU64 (ByteOffset, 3); + Object = NULL; + OffsetObject = NULL; + PkgLength = NULL; + + // Find and read internal offset data + Status = InternalAmlLocateOffsetTerm (&OffsetObject, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locating internal offset term\n", __FUNCTION__)); + goto Done; + } + + InternalOffsetData = *(UINT64 *)OffsetObject->Data; + + if (InternalOffsetData > BitCount) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid backwards offset\n", __FUNCTION__)); + Status = EFI_INVALID_PARAMETER; + goto Done; + } else if (InternalOffsetData == BitCount) { + // Do not need to append any reserved fields + Status = EFI_SUCCESS; + goto Done; + } + + // update internal offset value to new offset + *(UINT64 *)OffsetObject->Data = BitCount; + + // take difference to find how many bits to reserve + BitCount = BitCount - InternalOffsetData; + + // Create new object for the offset data, add pkglength encoding + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: appending new AML object\n", __FUNCTION__)); + goto Done; + } + + Status = InternalAmlBitPkgLength ((UINT32)BitCount, &PkgLength, &DataLength); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: internal AML PkgLength\n", __FUNCTION__)); + goto Done; + } + + Object->DataSize = DataLength + 1; // add one for Reserved Field Indicator + Object->Data = AllocateZeroPool (Object->DataSize); + + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for Offset\n", __FUNCTION__)); + goto Done; + } + + Object->Data[0] = 0; + CopyMem (&Object->Data[1], PkgLength, DataLength); // read internal offset data + Object->Completed = TRUE; + FreePool (PkgLength); + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&OffsetObject, ListHead); + } + + return Status; +} + +/** + Creates a NamedField or a ReservedField, depending on the + parameters. + + To create a NamedField item pass in the NameSeg and Bitlength + as in ASL. To create a ReservedField pass "" as the Name. + Must be used inside a Field or IndexField TermList. + + NamedField := NameSeg PkgLength + ReservedField := 0x00 PkgLength + + @param[in] Name - Field NameSeg + @param[in] BitLength - Length of field item in bits + @param[in,out] ListHead - Linked list has completed FieldUnitItem + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPFieldUnit ( + IN CHAR8 *Name, + IN UINT32 BitLength, + IN OUT LIST_ENTRY *ListHead + ) +{ + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *OffsetObject; + EFI_STATUS Status; + + if ((ListHead == NULL) || (Name == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + OffsetObject = NULL; + + if (AsciiStrLen (Name) == 0) { + if (BitLength > 0) { + // Prepend a 0 to the list + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Unable to append AML object.\n", __FUNCTION__)); + goto Done; + } + + Object->Data = AllocateZeroPool (1); + Object->DataSize = 1; + Object->Completed = TRUE; + } else { + Status = EFI_SUCCESS; + goto Done; + } + } else { + // add NameSeg to List + Status = InternalAmlNameSeg (Name, ListHead); + } + + if (EFI_ERROR (Status)) { + goto Done; + } + + // Locate and update internal Offset term + Status = InternalAmlLocateOffsetTerm (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locating offset term for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + *(UINT64 *)Object->Data += BitLength; // write + + // Add BitLength as a PkgLength term + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Appending BitLength for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + Status = InternalAmlBitPkgLength (BitLength, &Object->Data, &Object->DataSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Appending BitLength for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&OffsetObject, ListHead); + } + + return Status; +} + +/** + Creates a Field + + Field (RegionName, AccessType, LockRule, UpdateRule) {FieldUnitList} + + FieldUnitList must be added between AmlStart and AmlClose phase + + DefField := FieldOp PkgLength NameString FieldFlags FieldList + FieldOp := ExtOpPrefix 0x81 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] Name - Field NameString + @param[in] AccessType - Access Type for field + @param[in] LockRule - Lock rule for field + @param[in] UpdateRule - Update rule for field + @param[in,out] ListHead - Linked list has completed Field Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlField ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *Name, + IN EFI_ACPI_FIELD_ACCESS_TYPE_KEYWORDS AccessType, + IN EFI_ACPI_FIELD_LOCK_RULE_KEYWORDS LockRule, + IN EFI_ACPI_FIELD_UPDATE_RULE_KEYWORDS UpdateRule, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINT8 FieldFlags; + UINTN ChildCount; + + if ((ListHead == NULL) || (Name == NULL) || (AsciiStrLen (Name) == 0)) { + return EFI_INVALID_PARAMETER; + } + + // parameter validation + if ((Phase > AmlClose) || (AccessType > BufferAcc) || (LockRule > Lock) || (UpdateRule > WriteAsZeros)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, GENERIC_FIELD_IDENTIFIER, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start Field for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Insert internal offset counter + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Unable to append AML object.\n", __FUNCTION__)); + goto Done; + } + + Object->DataSize = sizeof (UINT64); + Object->Data = AllocateZeroPool (Object->DataSize); + Object->Completed = TRUE; + if (EFI_ERROR (Status) || (Object->Data == NULL)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start Field internal offset %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PkgLength for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Insert required NameString + Status = AmlOPNameString (Name, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Add Field Flags + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start FIELD_FLAGS for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Field Flags is one byte + Object->DataSize = 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, Name)); + goto Done; + } + + FieldFlags = (UINT8)((UpdateRule << 5) | (LockRule << 4) | AccessType); + + Object->Data[0] = FieldFlags; + Object->Completed = TRUE; + + // TermList is too complicated and must be added outside + break; + + case AmlClose: + + // Required NameString completed in one phase call + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close PkgLength for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Remove internal offset counter + Status = InternalAmlLocateOffsetTerm (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locating internal offset term%a\n", __FUNCTION__, Name)); + goto Done; + } + + Status = InternalFreeAmlObject (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: removing offset term%a\n", __FUNCTION__, Name)); + goto Done; + } + + // remove original field identifier data + Status = InternalAmlLocateObjectByIdentifier (&Object, GENERIC_FIELD_IDENTIFIER, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, Name)); + goto Done; + } + + // Field Op is two bytes + Object->DataSize = ChildObject->DataSize + 2; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, Name)); + goto Done; + } + + Object->Data[0] = AML_EXT_OP; + Object->Data[1] = AML_EXT_FIELD_OP; + CopyMem ( + &Object->Data[2], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a BankField + + BankField (RegionName, BankName, BankValue, AccessType, LockRule, UpdateRule) {FieldUnitList} + FieldUnitList must be added between AmlStart and AmlClose phase + + DefBankField := BankFieldOp PkgLength NameString NameString BankValue FieldFlags FieldList + BankFieldOp := ExtOpPrefix 0x87 + BankValue := TermArg => Integer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] RegionName - Name of host Operation Region + @param[in] BankName - Name of bank selection register + @param[in] BankValue - Bank Selection ID + @param[in] AccessType - Access Type as in Field + @param[in] LockRule - Lock rule as in Field + @param[in] UpdateRule - Update rule as in Field + @param[in,out] ListHead - Linked list has completed BankField Object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlBankField ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *RegionName, + IN CHAR8 *BankName, + IN UINT64 BankValue, + IN EFI_ACPI_FIELD_ACCESS_TYPE_KEYWORDS AccessType, + IN EFI_ACPI_FIELD_LOCK_RULE_KEYWORDS LockRule, + IN EFI_ACPI_FIELD_UPDATE_RULE_KEYWORDS UpdateRule, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINT8 FieldFlags; + UINTN ChildCount; + + if ((ListHead == NULL) || (RegionName == NULL) || (AsciiStrLen (RegionName) == 0) || + (BankName == NULL) || (AsciiStrLen (BankName) == 0)) + { + return EFI_INVALID_PARAMETER; + } + + // parameter validation + if ((Phase > AmlClose) || (AccessType > BufferAcc) || (LockRule > Lock) || (UpdateRule > WriteAsZeros)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, GENERIC_FIELD_IDENTIFIER, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start BankField for %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Insert internal offset counter + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + Object->DataSize = sizeof (UINT64); + Object->Data = AllocateZeroPool (Object->DataSize); + Object->Completed = TRUE; + if (EFI_ERROR (Status) || (Object->Data == NULL)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start BankField internal offset %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PkgLength for %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Insert required Region NameString + Status = AmlOPNameString (RegionName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + // Insert required Bank NameString + Status = AmlOPNameString (BankName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Insert required BankValue integer + Status = AmlOPDataInteger (BankValue, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Adding BankValue Integer for %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Add Field Flags + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start FIELD_FLAGS for %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Field Flags is one byte + Object->DataSize = 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, BankName)); + goto Done; + } + + FieldFlags = (UINT8)((UpdateRule << 5) | (LockRule << 4) | AccessType); + + Object->Data[0] = FieldFlags; + Object->Completed = TRUE; + + // TermList is too complicated and must be added outside + break; + + case AmlClose: + + // Required NameStrings completed in one phase call + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close PkgLength for %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Remove internal offset counter + Status = InternalAmlLocateOffsetTerm (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locating internal offset term%a\n", __FUNCTION__, BankName)); + goto Done; + } + + Status = InternalFreeAmlObject (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: removing offset term%a\n", __FUNCTION__, BankName)); + goto Done; + } + + // remove original field identifier data + Status = InternalAmlLocateObjectByIdentifier (&Object, GENERIC_FIELD_IDENTIFIER, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, BankName)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, BankName)); + goto Done; + } + + // Field Op is two bytes + Object->DataSize = ChildObject->DataSize + 2; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, BankName)); + goto Done; + } + + Object->Data[0] = AML_EXT_OP; + Object->Data[1] = AML_EXT_BANK_FIELD_OP; + CopyMem ( + &Object->Data[2], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates an IndexField + + IndexField (IndexName, DataName, AccessType, LockRule, UpdateRule) {FieldUnitList} + + FieldUnitList must be added between AmlStart and AmlClose phase + + DefIndexField := IndexFieldOp PkgLength NameString NameString FieldFlags FieldList + IndexFieldOp := ExtOpPrefix 0x86 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] IndexName - Name of Index FieldUnit + @param[in] DataName - Name of Data FieldUnit + @param[in] AccessType - Access Type for the FieldUnit + @param[in] LockRule - Lock rule for the FieldUnit + @param[in] UpdateRule - Update rule for the FieldUnit + @param[in,out] ListHead - Linked list has completed IndexField Object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlIndexField ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *IndexName, + IN CHAR8 *DataName, + IN EFI_ACPI_FIELD_ACCESS_TYPE_KEYWORDS AccessType, + IN EFI_ACPI_FIELD_LOCK_RULE_KEYWORDS LockRule, + IN EFI_ACPI_FIELD_UPDATE_RULE_KEYWORDS UpdateRule, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINT8 FieldFlags; + UINTN ChildCount; + + if ((ListHead == NULL) || (IndexName == NULL) || (AsciiStrLen (IndexName) == 0) || + (DataName == NULL) || (AsciiStrLen (DataName) == 0)) + { + return EFI_INVALID_PARAMETER; + } + + // parameter validation + if ((Phase > AmlClose) || (AccessType > BufferAcc) || (LockRule > Lock) || (UpdateRule > WriteAsZeros)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, GENERIC_FIELD_IDENTIFIER, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start IndexField for %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Insert internal offset counter + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + Object->DataSize = sizeof (UINT64); + Object->Data = AllocateZeroPool (Object->DataSize); + Object->Completed = TRUE; + if (EFI_ERROR (Status) || (Object->Data == NULL)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start IndexField internal offset %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PkgLength for %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Insert required Index NameString + Status = AmlOPNameString (IndexName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Insert required Data NameString + Status = AmlOPNameString (DataName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, DataName)); + goto Done; + } + + // Add Field Flags + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start FIELD_FLAGS for %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Field Flags is one byte + Object->DataSize = 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, IndexName)); + goto Done; + } + + FieldFlags = (UINT8)((UpdateRule << 5) | (LockRule << 4) | AccessType); + + Object->Data[0] = FieldFlags; + Object->Completed = TRUE; + + // TermList is too complicated and must be added outside + break; + + case AmlClose: + + // Required NameString completed in one phase call + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close PkgLength for %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Remove internal offset counter + Status = InternalAmlLocateOffsetTerm (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locating internal offset term%a\n", __FUNCTION__, IndexName)); + goto Done; + } + + Status = InternalFreeAmlObject (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: removing offset term%a\n", __FUNCTION__, IndexName)); + goto Done; + } + + // remove original field identifier data + Status = InternalAmlLocateObjectByIdentifier (&Object, GENERIC_FIELD_IDENTIFIER, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, IndexName)); + goto Done; + } + + // Field Op is two bytes + Object->DataSize = ChildObject->DataSize + 2; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, IndexName)); + goto Done; + } + + Object->Data[0] = AML_EXT_OP; + Object->Data[1] = AML_EXT_INDEX_FIELD_OP; + CopyMem ( + &Object->Data[2], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + OperationRegion (RegionName, RegionSpace, Offset, Length) + + DefOpRegion := OpRegionOp NameString RegionSpace RegionOffset RegionLen + OpRegionOp := ExtOpPrefix 0x80 + RegionSpace := + ByteData // 0x00 SystemMemory + // 0x01 SystemIO + // 0x02 PCI_Config + // 0x03 EmbeddedControl + // 0x04 SMBus + // 0x05 System CMOS + // 0x06 PciBarTarget + // 0x07 IPMI + // 0x08 GeneralPurposeIO + // 0x09 GenericSerialBus + // 0x0A PCC + // 0x80-0xFF: OEM Defined + RegionOffset := TermArg => Integer + RegionLen := TermArg => Integer + + @param[in] RegionName - Name for the Operation Region + @param[in] RegionSpace - Region Space type + @param[in] Offset - Offset within the selected RegionSpace at which the + region starts (byte-granular) + @param[in] Length - Length of the region in bytes. + @param[in,out] ListHead - Linked list head + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPOperationRegion ( + IN CHAR8 *RegionName, + IN GENERIC_ADDRESS_SPACE_ID RegionSpace, + IN UINT64 Offset, + IN UINT64 Length, + IN OUT LIST_ENTRY *ListHead + ) +{ + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + EFI_STATUS Status; + + // Input parameter validation + if ((RegionName == NULL) || (AsciiStrLen (RegionName) == 0) || (ListHead == NULL) || + ((RegionSpace > PCC) && (RegionSpace < 0x80)) || (RegionSpace > 0xFF)) + { + return EFI_INVALID_PARAMETER; + } + + Object = NULL; + ChildObject = NULL; + Status = EFI_DEVICE_ERROR; + + Status = InternalAppendNewAmlObject (&Object, "OPREGION", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start OpRegion for %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + Status = AmlOPNameString (RegionName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Name String for %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + Status = AmlOPByteData ((UINT8)RegionSpace, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Region space byte data for %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + Status = AmlOPDataInteger (Offset, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Offset data integer for %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + Status = AmlOPDataInteger (Length, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Length data integer for %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, "OPREGION", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, RegionName)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, RegionName)); + goto Done; + } + + // OpRegion Opcode is two bytes + Object->DataSize = ChildObject->DataSize + 2; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, RegionName)); + goto Done; + } + + Object->Data[0] = AML_EXT_OP; + Object->Data[1] = AML_EXT_REGION_OP; + CopyMem ( + &Object->Data[2], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a CreateField AML Object and inserts it into the linked list + + Syntax: + CreateField ( SourceBuffer, BitIndex, NumBits, FieldName ) + + DefCreateField := CreateFieldOp SourceBuff BitIndex NumBits NameString + CreateFieldOp := ExtOpPrefix 0x13 + ExtOpPrefix := 0x5B + SourceBuff := TermArg => Buffer + BitIndex := TermArg => Integer + NumBits := TermArg -> Integer + + @param[in] SourceBuffer, - Buffer to house the new buffer field object + @param[in] BitIndex, - Starting bit index place the new buffer + @param[in] NumBits, - Number of bits to reserve + @param[in] FieldName, - The new buffer field object to be created in SourceBuffer + @param[in,out] ListHead - Linked list has completed CreateField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPCreateField ( + IN CHAR8 *SourceBuffer, + IN UINT64 BitIndex, + IN UINT64 NumBits, + IN CHAR8 *FieldName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + ChildObject = NULL; + Object = NULL; + + if ((SourceBuffer == NULL) || (FieldName == NULL) || (ListHead == NULL) || + (AsciiStrLen (SourceBuffer) == 0) || (AsciiStrLen (FieldName) == 0)) + { + return EFI_INVALID_PARAMETER; + } + + ChildObject = NULL; + Status = InternalAppendNewAmlObject (&Object, "CreateField", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: CreateField for %a object\n", __FUNCTION__, FieldName)); + goto Done; + } + + Status = AmlOPNameString (SourceBuffer, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: NameString for %a object\n", __FUNCTION__, FieldName)); + goto Done; + } + + Status = AmlOPDataInteger (BitIndex, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: BitIndex for %a object\n", __FUNCTION__, FieldName)); + goto Done; + } + + Status = AmlOPDataInteger (NumBits, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: NumBits for %a object\n", __FUNCTION__, FieldName)); + goto Done; + } + + Status = AmlOPNameString (FieldName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: FieldName for %a object\n", __FUNCTION__, FieldName)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, "CreateField", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, FieldName)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, FieldName)); + goto Done; + } + + // CreateFieldOp is two bytes + Object->DataSize = ChildObject->DataSize + 2; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, FieldName)); + goto Done; + } + + Object->Data[0] = AML_EXT_OP; + Object->Data[1] = AML_EXT_CREATE_FIELD_OP; + CopyMem ( + &Object->Data[2], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Internal function used to create a CreateBit|Byte|Word|DWord|QWordField objects + and insert them into the linked list + + @param[in] SourceBuffer, - Buffer to insert the new buffer fixed field object + @param[in] Index, - Starting index to place the new buffer + @param[in] FixedFieldName, - Name of the FixedField + @param[in] OpCode, - AML opcode for the Create_Field encoding + @param[in,out] ListHead - Linked list has completed CreateFixedField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlCreateFixedField ( + IN CHAR8 *SourceBuffer, + IN UINT64 Index, + IN CHAR8 *FixedFieldName, + IN UINT8 OpCode, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + ChildObject = NULL; + + if ((SourceBuffer == NULL) || (FixedFieldName == NULL) || (ListHead == NULL) || + (AsciiStrLen (SourceBuffer) == 0) || (AsciiStrLen (FixedFieldName) == 0)) + { + return EFI_INVALID_PARAMETER; + } + + Status = InternalAppendNewAmlObject (&Object, "CreateFixedField", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: CreateField for %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + + // Check if Localx Buffer + if (AsciiStrnCmp (SourceBuffer, "Local", 5) == 0) { + if ((SourceBuffer[5] >= '0') && (SourceBuffer[5] <= '9')) { + Status = AmlOPLocalN ((UINT8)AsciiStrDecimalToUintn (&SourceBuffer[5]), ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: LocalN for %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + } + + // Check if Argx Buffer + } else if (AsciiStrnCmp (SourceBuffer, "Arg", 3) == 0) { + if ((SourceBuffer[3] >= '0') && (SourceBuffer[3] <= '9')) { + Status = AmlOpArgN ((UINT8)AsciiStrDecimalToUintn (&SourceBuffer[3]), ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ArgN for %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + } + } else { + Status = AmlOPNameString (SourceBuffer, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: NameString for %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + } + + Status = AmlOPDataInteger (Index, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Index for %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + + Status = AmlOPNameString (FixedFieldName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: FieldName for %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, "CreateFixedField", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + + // CreateWordFieldOp is one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, FixedFieldName)); + goto Done; + } + + Object->Data[0] = OpCode; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + Creates a CreateBitField AML Object and inserts it into the linked list + + Syntax: + CreateBitField (SourceBuffer, BitIndex, BitFieldName) + + DefCreateBitField := CreateBitFieldOp SourceBuff BitIndex NameString + CreateBitFieldOp := 0x8D + SourceBuff := TermArg => Buffer + BitIndex := TermArg => Integer + + @param[in] SourceBuffer, - Buffer to insert the new buffer bit field object + @param[in] BitIndex, - Starting bit index to place the new buffer + @param[in] BitFieldName, - Name of the BitField + @param[in,out] ListHead - Linked list has completed CreateBitField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPCreateBitField ( + IN CHAR8 *SourceBuffer, + IN UINT64 BitIndex, + IN CHAR8 *BitFieldName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlCreateFixedField (SourceBuffer, BitIndex, BitFieldName, AML_CREATE_BIT_FIELD_OP, ListHead); + return Status; +} + +/** + Creates a CreateByteField AML Object and inserts it into the linked list + + Syntax: + CreateByteField ( SourceBuffer, ByteIndex, ByteFieldName ) + + DefCreateByteField := CreateByteFieldOp SourceBuff ByteIndex NameString + CreateByteFieldOp := 0x8C + SourceBuff := TermArg => Buffer + ByteIndex := TermArg => Integer + + @param[in] SourceBuffer, - Buffer to insert the new buffer byte field object + @param[in] ByteIndex, - Starting byte index to place the new buffer + @param[in] ByteFieldName, - Name of the ByteField + @param[in,out] ListHead - Linked list has completed CreateByteField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPCreateByteField ( + IN CHAR8 *SourceBuffer, + IN UINT64 ByteIndex, + IN CHAR8 *ByteFieldName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlCreateFixedField (SourceBuffer, ByteIndex, ByteFieldName, AML_CREATE_BYTE_FIELD_OP, ListHead); + return Status; +} + +/** + Creates a CreateDWordField AML Object and inserts it into the linked list + + Syntax: + CreateDWordField ( SourceBuffer, ByteIndex, DWordFieldName ) + + DefCreateDWordField := CreateDWordFieldOp SourceBuff ByteIndex NameString + CreateDWordFieldOp := 0x8A + SourceBuff := TermArg => Buffer + ByteIndex := TermArg => Integer + + @param[in] SourceBuffer, - Buffer to insert the new buffer DWord field object + @param[in] ByteIndex, - Starting byte index to place the new buffer + @param[in] DWordFieldName, - Name of the DWordField + @param[in,out] ListHead - Linked list has completed CreateDWordField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPCreateDWordField ( + IN CHAR8 *SourceBuffer, + IN UINT64 ByteIndex, + IN CHAR8 *DWordFieldName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlCreateFixedField (SourceBuffer, ByteIndex, DWordFieldName, AML_CREATE_DWORD_FIELD_OP, ListHead); + return Status; +} + +/** + Creates a CreateQWordField AML Object and inserts it into the linked list + + Syntax: + CreateQWordField ( SourceBuffer, ByteIndex, QWordFieldName ) + + DefCreateQWordField := CreateQWordFieldOp SourceBuff ByteIndex NameString + CreateQWordFieldOp := 0x8F + SourceBuff := TermArg => Buffer + ByteIndex := TermArg => Integer + + @param[in] SourceBuffer, - Buffer to insert the new buffer QWord field object + @param[in] ByteIndex, - Starting byte index to place the new buffer + @param[in] QWordFieldName, - Name of the QWordField + @param[in,out] ListHead - Linked list has completed CreateQWordField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPCreateQWordField ( + IN CHAR8 *SourceBuffer, + IN UINT64 ByteIndex, + IN CHAR8 *QWordFieldName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlCreateFixedField (SourceBuffer, ByteIndex, QWordFieldName, AML_CREATE_QWORD_FIELD_OP, ListHead); + return Status; +} + +/** + Creates a CreateWordField AML Object and inserts it into the linked list + + Syntax: + CreateWordField ( SourceBuffer, ByteIndex, WordFieldName ) + + DefCreateWordField := CreateWordFieldOp SourceBuff ByteIndex NameString + CreateWordFieldOp := 0x8B + SourceBuff := TermArg => Buffer + ByteIndex := TermArg => Integer + + @param[in] SourceBuffer, - Buffer to house the new buffer word field object + @param[in] ByteIndex, - Starting byte index to place the new buffer + @param[in] WordFieldName, - Name of the WordField + @param[in,out] ListHead - Linked list has completed CreateWordField object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPCreateWordField ( + IN CHAR8 *SourceBuffer, + IN UINT64 ByteIndex, + IN CHAR8 *WordFieldName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlCreateFixedField (SourceBuffer, ByteIndex, WordFieldName, AML_CREATE_WORD_FIELD_OP, ListHead); + return Status; +} + +/** + Creates a Method + + Method (MethodName, NumArgs, SerializeRule, SyncLevel, ReturnType, + ParameterTypes) {TermList} + + TermList must be created between AmlStart and AmlClose Phase + + Note: ReturnType and ParameterTypes are not used for AML encoding + and are therefore not passed in to this function. + + DefMethod := MethodOp PkgLength NameString MethodFlags TermList + MethodOp := 0x14 + MethodFlags := ByteData // bit 0-2: ArgCount (0-7) + // bit 3: SerializeFlag + // 0 NotSerialized + // 1 Serialized + // bit 4-7: SyncLevel (0x00-0x0f) + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] Name - Method name + @param[in] NumArgs - Number of arguments passed in to method + @param[in] SerializeRule - Flag indicating whether method is serialized + or not + @param[in] SyncLevel - synchronization level for the method (0 - 15), + use zero for default sync level. + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlMethod ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *Name, + IN UINT8 NumArgs, + IN METHOD_SERIALIZE_FLAG SerializeRule, + IN UINT8 SyncLevel, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINT8 MethodFlags; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || + (Name == NULL) || + (NumArgs > METHOD_ARGS_MAX) || + (SyncLevel > MAX_SYNC_LEVEL) || + (SerializeRule >= FlagInvalid) || + (ListHead == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, "Method", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start Method for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PkgLength for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Insert required NameString + Status = AmlOPNameString (Name, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Add Method Flags + Status = InternalAppendNewAmlObject (&Object, "METHOD_FLAGS", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start METHOD_FLAGS for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // TermList is too complicated and must be added outside + break; + + case AmlClose: + // TermList should be closed already + // Add Method Flags + Status = InternalAmlLocateObjectByIdentifier (&Object, "METHOD_FLAGS", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locate METHOD_FLAGS for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a METHOD_FLAGS child data collection.\n", __FUNCTION__, Name)); + goto Done; + } + + // Method Flags is one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, Name)); + goto Done; + } + + MethodFlags = NumArgs & 0x07; + if (SerializeRule) { + MethodFlags |= BIT3; + } + + MethodFlags |= (SyncLevel & 0x0F) << 4; + Object->Data[0] = MethodFlags; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + // Required NameString completed in one phase call + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close PkgLength for %a object\n", __FUNCTION__, Name)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, "Method", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, Name)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a child data collection.\n", __FUNCTION__, Name)); + goto Done; + } + + // Method Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, Name)); + goto Done; + } + + Object->Data[0] = AML_METHOD_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&ChildObject, ListHead); + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c new file mode 100644 index 0000000000000000000000000000000000000000..c1b66f4f84421f61d15e7371bdcbca68d6d7b75c --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlNamespaceModifierObjects.c @@ -0,0 +1,357 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + Creates a Scope (ObjectName, Object) + + Object must be created between AmlStart and AmlClose Phase + + DefScope := ScopeOp PkgLength NameString TermList + ScopeOp := 0x10 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] String - Location + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlScope ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *String, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (String == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start PkgLength for %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Insert required NameString + Status = AmlOPNameString (String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Insert NameString for %a object\n", __FUNCTION__, String)); + goto Done; + } + + // TermList is too complicated and must be added outside + break; + + case AmlClose: + // TermList should be closed already + + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close PkgLength for %a object\n", __FUNCTION__, String)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a has no child data.\n", __FUNCTION__, String)); + goto Done; + } + + // Scope Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, String)); + goto Done; + } + + Object->Data[0] = AML_SCOPE_OP; + CopyMem (&Object->Data[1], ChildObject->Data, ChildObject->DataSize); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a Name (ObjectName, Object) + + Object must be created between AmlStart and AmlClose Phase + + DefName := NameOp NameString ChildObjectData + NameOp := 0x08 + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] String - Object name + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlName ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *String, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (String == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Insert required NameString + Status = AmlOPNameString (String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start NameString for %a object\n", __FUNCTION__, String)); + goto Done; + } + + break; + case AmlClose: + // DataRefObject should be closed already + + Status = InternalAmlLocateObjectByIdentifier (&Object, String, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, String)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a has no child data.\n", __FUNCTION__, String)); + goto Done; + } + + Object->Data = AllocatePool (ChildObject->DataSize + 1); + // Name Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, String)); + goto Done; + } + + Object->Data[0] = AML_NAME_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates an Alias (SourceObject, AliasObject) + + DefAlias := AliasOp NameString NameString + AliasOp := 0x06 + + @param[in] SourceName - Any named Source Object NameString + @param[in] AliasName - Alias Object NameString + @param[in,out] ListHead - Linked list has completed the Alias Object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPAlias ( + IN CHAR8 *SourceName, + IN CHAR8 *AliasName, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((SourceName == NULL) || (AliasName == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + // Start ALIAS object + Status = InternalAppendNewAmlObject (&Object, "ALIAS", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot append ALIAS object\n", __FUNCTION__)); + goto Done; + } + + // Insert required Object (to be aliased) NameString + Status = AmlOPNameString (SourceName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot create NameString: %a \n", __FUNCTION__, SourceName)); + goto Done; + } + + // Insert required Alias NameString + Status = AmlOPNameString (AliasName, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot create NameString: %a \n", __FUNCTION__, AliasName)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, "ALIAS", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot locate ALIAS object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a has no child data.\n", __FUNCTION__, SourceName)); + goto Done; + } + + Object->Data = AllocateZeroPool (ChildObject->DataSize + 1); + // Alias Op is one byte + Object->DataSize = ChildObject->DataSize + 1; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, SourceName)); + goto Done; + } + + Object->Data[0] = AML_ALIAS_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c new file mode 100644 index 0000000000000000000000000000000000000000..f97f1741cf1ea914111001913da0ade4bd034b76 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlObjectsDebug.c @@ -0,0 +1,141 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + DEBUG print a (VOID *)buffer in an array of HEX bytes + + 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F + 0000 54 48 49 53 20 49 53 20 41 20 53 41 4D 50 4C 45 THIS IS A SAMPLE + 0010 5F 42 55 46 46 45 52 01 02 5E 5C 30 31 _BUFFER..^\01 + + @param[in] Buffer - Buffer containing buffer + @param[in] BufferSize - Number of bytes to print + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +AmlDebugPrintBuffer ( + IN VOID *Buffer, + IN UINTN BufferSize + ) +{ + UINTN Column; + UINTN Index; + UINTN NumberOfColumns; + UINT8 *Data; + + Data = Buffer; + NumberOfColumns = 16; + // Header + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\n")); + for (Index = 0; Index < BufferSize;) { + // Row Counter + DEBUG ((DEBUG_VERBOSE, "%4X ", Index)); + + // Hex ouput + for (Column = 0; Column < NumberOfColumns; Column++) { + if (Index + Column < BufferSize) { + DEBUG ((DEBUG_VERBOSE, " %02X", Data[Index + Column])); + } else { + DEBUG ((DEBUG_VERBOSE, " ")); + } + } + + DEBUG ((DEBUG_VERBOSE, " ")); + // Ascii ouput + for (Column = 0; Column < NumberOfColumns; Column++) { + if (Index + Column < BufferSize) { + // Only print ACPI acceptable characters + if (((Data[Index + Column] >= 0x30) && // '0' - '9' + (Data[Index + Column] <= 0x39)) || + ((Data[Index + Column] >= 0x41) && // 'A' - 'Z' + (Data[Index + Column] <= 0x5A)) || + (Data[Index + Column] == 0x5C) || // '\' + (Data[Index + Column] == 0x5F) || // '_' + (Data[Index + Column] == 0x5E) // '^' + ) + { + DEBUG ((DEBUG_VERBOSE, "%c", Data[Index + Column])); + } else { + DEBUG ((DEBUG_VERBOSE, ".")); + } + } + } + + Index += NumberOfColumns; + DEBUG ((DEBUG_VERBOSE, "\n")); + } + + return EFI_SUCCESS; +} + +/** + DEBUG print an AML Object including an array of HEX bytes for the data + + 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F + 0000 54 48 49 53 20 49 53 20 41 20 53 41 4D 50 4C 45 THIS IS A SAMPLE + 0010 5F 42 55 46 46 45 52 01 02 5E 5C 30 31 _BUFFER..^\01 + Completed=(TRUE|FALSE) + + @param[in] Object - AML_OBJECT_INSTANCE + + @retval EFI_SUCCESS, EFI_INVALID_PARAMETER +**/ +EFI_STATUS +EFIAPI +AmlDebugPrintObject ( + IN AML_OBJECT_INSTANCE *Object + ) +{ + if ((Object == NULL) || (Object->Signature != AML_OBJECT_INSTANCE_SIGNATURE)) { + return EFI_INVALID_PARAMETER; + } + + DEBUG (( + DEBUG_VERBOSE, + "Object=0x%X, Size=0x%d\n", + (UINTN)Object, + Object->DataSize + )); + AmlDebugPrintBuffer (Object->Data, Object->DataSize); + DEBUG ((DEBUG_VERBOSE, "Completed=%a\n", Object->Completed ? "TRUE" : "FALSE")); + DEBUG ((DEBUG_VERBOSE, "\n")); + return EFI_SUCCESS; +} + +/** + DEBUG print a linked list of AML buffer Objects in an array of HEX bytes + + @param[in] ListHead - Head of AML_OBJECT_INSTANCE Linked List +**/ +EFI_STATUS +EFIAPI +AmlDebugPrintLinkedObjects ( + IN LIST_ENTRY *ListHead + ) +{ + LIST_ENTRY *Node; + AML_OBJECT_INSTANCE *Object; + + if (ListHead == NULL) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_VERBOSE, "Printing AML_OBJECT_INSTANCE Linked List\n")); + Node = GetNextNode (ListHead, ListHead); + while (Node != ListHead) { + Object = AML_OBJECT_INSTANCE_FROM_LINK (Node); + AmlDebugPrintObject (Object); + Node = GetNextNode (ListHead, Node); + } + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlPkgLength.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlPkgLength.c new file mode 100644 index 0000000000000000000000000000000000000000..85efd9a835d1d3bd6e8654812d3b4cc6e9622623 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlPkgLength.c @@ -0,0 +1,264 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +#define MAX_ONE_BYTE_PKG_LENGTH 63 +#define ONE_BYTE_PKG_LENGTH_ENCODING 0x00 +#define ONE_BYTE_NIBBLE_MASK 0x3F + +#define MAX_TWO_BYTE_PKG_LENGTH 4095 +#define TWO_BYTE_PKG_LENGTH_ENCODING 0x40 +#define PKG_LENGTH_NIBBLE_MASK 0x0F + +#define MAX_THREE_BYTE_PKG_LENGTH 1048575 +#define THREE_BYTE_PKG_LENGTH_ENCODING 0x80 + +#define MAX_FOUR_BYTE_PKG_LENGTH 268435455 +#define FOUR_BYTE_PKG_LENGTH_ENCODING 0xC0 + +/** + Creates a Package Length encoding and places it in the return buffer, + PkgLengthEncoding. Similar to AmlPkgLength but the PkgLength does not + include the length of its own encoding. + + @param[in] DataSize - The size of data to be encoded as a pkglength + @param[out] PkgLengthEncoding - Return buffer containing the AML encoding + @param[out] ReturnDataLength - Size of the return buffer + + @return EFI_SUCCESS - Success + @return all others - Fail + **/ +EFI_STATUS +EFIAPI +InternalAmlBitPkgLength ( + IN UINT32 DataSize, + OUT UINT8 **PkgLengthEncoding, + OUT UINTN *ReturnDataLength + ) +{ + UINTN DataLength; + UINT8 PkgLeadByte; + UINTN PkgLengthRemainder; + EFI_STATUS Status; + + Status = EFI_INVALID_PARAMETER; + DataLength = 0; + // Calculate Length of PkgLength Data and fill out least + // significant nibble + if ((DataSize + 1) <= MAX_ONE_BYTE_PKG_LENGTH) { + DataLength = 1; + PkgLeadByte = ONE_BYTE_PKG_LENGTH_ENCODING; + PkgLeadByte |= ((DataSize) & ONE_BYTE_NIBBLE_MASK); + } else { + if ((DataSize + 2) <= MAX_TWO_BYTE_PKG_LENGTH) { + DataLength = 2; + PkgLeadByte = TWO_BYTE_PKG_LENGTH_ENCODING; + } else if ((DataSize + 3) <= MAX_THREE_BYTE_PKG_LENGTH) { + DataLength = 3; + PkgLeadByte = THREE_BYTE_PKG_LENGTH_ENCODING; + } else if ((DataSize + 4) <= MAX_FOUR_BYTE_PKG_LENGTH) { + DataLength = 4; + PkgLeadByte = FOUR_BYTE_PKG_LENGTH_ENCODING; + } else { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: PkgLength data size > 0x%X\n", + __FUNCTION__, + MAX_FOUR_BYTE_PKG_LENGTH - 4 + )); + goto Done; + } + + PkgLeadByte |= ((DataSize) & PKG_LENGTH_NIBBLE_MASK); + } + + // Allocate new data buffer + // DataSize = DataLength + DataSize; + *PkgLengthEncoding = AllocatePool (DataLength); + if (*PkgLengthEncoding == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocation failed Object=PkgLength\n", __FUNCTION__)); + goto Done; + } + + // Populate PkgLeadByte + *PkgLengthEncoding[0] = PkgLeadByte; + + // Populate remainder of PkgLength bytes + PkgLengthRemainder = (DataSize) >> 4; + if (PkgLengthRemainder != 0) { + CopyMem (&PkgLengthEncoding[0][1], &PkgLengthRemainder, DataLength - 1); + } + + *ReturnDataLength = DataLength; + +Done: + return Status; +} + +/** + Creates a Package Length AML Object and inserts it into the linked list + + PkgLength := PkgLeadByte | + | + | + + + PkgLeadByte := + + + + Note: The high 2 bits of the first byte reveal how many follow bytes are in + the PkgLength. If the PkgLength has only one byte, bit 0 through 5 are used + to encode the package length (in other words, values 0-63). If the package + length value is more than 63, more than one byte must be used for the encoding + in which case bit 4 and 5 of the PkgLeadByte are reserved and must be zero. + + If the multiple bytes encoding is used, bits 0-3 of the PkgLeadByte become + the least significant 4 bits of the resulting package length value. The next + ByteData will become the next least significant 8 bits of the resulting value + and so on, up to 3 ByteData bytes. Thus, the maximum package length is 2**28. + + @param[in] Phase - Example: AmlStart, AmlClose + @param[in,out] ListHead - Head of Linked List of all AML Objects + + @return EFI_SUCCESS - Success + @return all others - Fail + **/ +EFI_STATUS +EFIAPI +AmlPkgLength ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + UINTN DataLength; + UINT8 PkgLeadByte; + UINTN PkgLengthRemainder; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, "LENGTH", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start Length object\n", __FUNCTION__)); + goto Done; + } + + break; + case AmlClose: + Status = InternalAmlLocateObjectByIdentifier (&Object, "LENGTH", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locate Length object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a has no child data.\n", __FUNCTION__, "Length")); + goto Done; + } + + DataLength = 0; + // Calculate Length of PkgLength Data and fill out least + // significant nibble + if ((ChildObject->DataSize + 1) <= MAX_ONE_BYTE_PKG_LENGTH) { + DataLength = 1; + PkgLeadByte = ONE_BYTE_PKG_LENGTH_ENCODING; + PkgLeadByte |= ((ChildObject->DataSize + DataLength) & ONE_BYTE_NIBBLE_MASK); + } else { + if ((ChildObject->DataSize + 2) <= MAX_TWO_BYTE_PKG_LENGTH) { + DataLength = 2; + PkgLeadByte = TWO_BYTE_PKG_LENGTH_ENCODING; + } else if ((ChildObject->DataSize + 3) <= MAX_THREE_BYTE_PKG_LENGTH) { + DataLength = 3; + PkgLeadByte = THREE_BYTE_PKG_LENGTH_ENCODING; + } else if ((ChildObject->DataSize + 4) <= MAX_FOUR_BYTE_PKG_LENGTH) { + DataLength = 4; + PkgLeadByte = FOUR_BYTE_PKG_LENGTH_ENCODING; + } else { + Status = EFI_DEVICE_ERROR; + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: PkgLength data size > 0x%X\n", + __FUNCTION__, + MAX_FOUR_BYTE_PKG_LENGTH - 4 + )); + goto Done; + } + + PkgLeadByte |= ((ChildObject->DataSize + DataLength) & PKG_LENGTH_NIBBLE_MASK); + } + + // Allocate new data buffer + Object->DataSize = DataLength + ChildObject->DataSize; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocation failed Object=PkgLength\n", __FUNCTION__)); + goto Done; + } + + // Populate PkgLeadByte + Object->Data[0] = PkgLeadByte; + + // Populate remainder of PkgLength bytes + PkgLengthRemainder = (ChildObject->DataSize + DataLength) >> 4; + if (PkgLengthRemainder != 0) { + CopyMem (&Object->Data[1], &PkgLengthRemainder, DataLength - 1); + } + + CopyMem ( + &Object->Data[DataLength], + ChildObject->Data, + ChildObject->DataSize + ); + + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c new file mode 100644 index 0000000000000000000000000000000000000000..d2b326e846908d2533a9da759bc5faf6da1c36ab --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlResourceDescriptor.c @@ -0,0 +1,1986 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + ResourceTemplate (Resource To Buffer Conversion Macro) + + Syntax: + ResourceTemplate () {ResourceMacroList} => Buffer + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed ResourceTemplate Object + after AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlResourceTemplate ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + EFI_ACPI_END_TAG_DESCRIPTOR *EndTag; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = AmlBuffer (AmlStart, 0, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "ResourceTemplate")); + goto Done; + } + + // Start EndTag object to be completed in Close + // ACPI 6.3: 6.4.2.9 End Tag: ...The End Tag is automatically generated by + // the ASL compiler at the end of the ResourceTemplate statement. + Status = InternalAppendNewAmlObject (&Object, "END_TAG", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "END_TAG")); + goto Done; + } + + // ResourceMacroList is too complicated and must be added outside + break; + case AmlClose: + // ResourceMacroList should be closed already + + // Locate and complete End Tag + Status = InternalAmlLocateObjectByIdentifier (&Object, "END_TAG", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Locate %a object\n", __FUNCTION__, "END_TAG")); + goto Done; + } + + // Release Object->Data Identifier + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collecting Child data\n", __FUNCTION__)); + goto Done; + } + + Object->DataSize = ChildObject->DataSize + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: EndTag Alloc Failed\n", __FUNCTION__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + // ChildObject Data goes before End Tag + if ((ChildObject->Data != NULL) && (ChildObject->DataSize > 0)) { + CopyMem (Object->Data, ChildObject->Data, ChildObject->DataSize); + } + + EndTag = (EFI_ACPI_END_TAG_DESCRIPTOR *)&Object->Data[ChildObject->DataSize]; + EndTag->Desc = ACPI_END_TAG_DESCRIPTOR; + // Spec says the byte is a checksum, but I have never seen a value other + // than zero in the field compiled from ASL. + // EndTag->Checksum already = 0; + + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + + Status = AmlBuffer (AmlClose, 0, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Close %a object\n", __FUNCTION__, "ResourceTemplate")); + goto Done; + } + + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + InternalAmlAddressSpaceCheck + + Checks Address space parameters for Word, DWord, or QWord size Address space + Descriptor. Size will be constrained by the Resource Descriptor input + parameters being of the correct size. + + @param[in] IsMinFixed + @param[in] IsMaxFixed + @param[in] AddressGranularity + @param[in] AddressMinimum + @param[in] AddressMaximum + @param[in] RangeLength + +**/ +EFI_STATUS +EFIAPI +InternalAmlAddressSpaceCheck ( + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 RangeLength + ) +{ + // Max must be greater than Min + if (AddressMaximum < AddressMinimum) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: AddressMinimum greater than AddressMaximum\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + // Address Granularity must be (2^n)-1 + if (((AddressGranularity + 1) & AddressGranularity) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: AddressGranularity must be (a power of 2)-1\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if (RangeLength == 0) { + // LEN _MIF _MAF Definition + // 0 0 0 + // 0 0 1 + // 0 1 0 + // Variable size, variable location resource descriptor for _PRS. + // If _MIF is set, _MIN must be a multiple of (_GRA+1). If _MAF + // is set, _MAX must be (a multiple of (_GRA+1))-1. + // OS can pick the resource range that satisfies following conditions: + // If _MIF is not set, start address is a multiple of (_GRA+1) + // and greater or equal to _MIN. Otherwise, start address is _MIN. + // If _MAF is not set, end address is (a multiple of (_GRA+1))-1 + // and less or equal to _MAX. Otherwise, end address is _MAX. + // 0 1 1 (Invalid combination) + if ((IsMinFixed == EFI_ACPI_GENERAL_FLAG_MIN_IS_FIXED) && + (IsMaxFixed == EFI_ACPI_GENERAL_FLAG_MAX_IS_FIXED)) + { + // 0 1 1 (Invalid combination) + DEBUG ((DEBUG_ERROR, "%a: ERROR: IsMinFixed and IsMaxFixed cannot both be set\n", __FUNCTION__)); + DEBUG ((DEBUG_ERROR, "%a: When RangeLength=0x%lX\n", __FUNCTION__, RangeLength)); + return EFI_INVALID_PARAMETER; + } else if (IsMaxFixed == EFI_ACPI_GENERAL_FLAG_MAX_IS_FIXED) { + // 0 0 1 + if ((AddressMaximum & AddressGranularity) != AddressGranularity) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: (AddressMaximum=0x%lX + 1) is not a multiple of\n", __FUNCTION__, AddressMaximum)); + DEBUG ((DEBUG_ERROR, "%a: (AddressGranularity=0x%lX + 1)\n", __FUNCTION__, AddressGranularity)); + DEBUG ((DEBUG_ERROR, "%a: When IsMaxFixed = 1\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if (AddressMaximum == 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: AddressMaximum can not be 0\n", __FUNCTION__)); + DEBUG ((DEBUG_ERROR, "%a: When IsMaxFixed = 1\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + } else if (IsMinFixed == EFI_ACPI_GENERAL_FLAG_MIN_IS_FIXED) { + // 0 1 0 + if ((AddressMinimum & AddressGranularity) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: AddressMinimum=0x%lX is not a multiple of\n", __FUNCTION__, AddressMinimum)); + DEBUG ((DEBUG_ERROR, "%a: (AddressGranularity=0x%lX + 1)\n", __FUNCTION__, AddressGranularity)); + DEBUG ((DEBUG_ERROR, "%a: When IsMinFixed = 1\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + } else if ((IsMinFixed == EFI_ACPI_GENERAL_FLAG_MIN_IS_NOT_FIXED) && + (IsMaxFixed == EFI_ACPI_GENERAL_FLAG_MAX_IS_NOT_FIXED) && + (AddressMinimum == 0) && + (AddressMaximum == 0) && + (AddressGranularity == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Maximum, Minimum, Granularity all 0\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + } else { + // LEN _MIF _MAF Definition + // >0 0 0 Fixed size, variable location resource descriptor for _PRS. + // _LEN must be a multiple of (_GRA+1). + // OS can pick the resource range that satisfies following conditions: + // Start address is a multiple of (_GRA+1) and greater or equal to _MIN. + // End address is (start address+_LEN-1) and less or equal to _MAX. + // >0 0 1 (Invalid combination) + // >0 1 0 (Invalid combination) + // >0 1 1 Fixed size, fixed location resource descriptor. + // _GRA must be 0 and _LEN must be (_MAX - _MIN +1). + if ((IsMinFixed == EFI_ACPI_GENERAL_FLAG_MIN_IS_NOT_FIXED) && + (IsMaxFixed == EFI_ACPI_GENERAL_FLAG_MAX_IS_NOT_FIXED)) + { + // >0 0 0 + if ((RangeLength & AddressGranularity) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: RangeLength=0x%lX is not a multiple of\n", __FUNCTION__, RangeLength)); + DEBUG ((DEBUG_ERROR, "%a: (AddressGranularity=0x%lX + 1)\n", __FUNCTION__, AddressGranularity)); + DEBUG ((DEBUG_ERROR, "%a: When IsMinFixed = 0, IsMaxFixed = 0\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } else if (RangeLength > (AddressMaximum - AddressMinimum + 1)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: RangeLength=0x%lX > (AddrRangeMax=0x%lX - AddrRangeMin=0x%lX + 1)\n", __FUNCTION__, RangeLength, AddressMaximum, AddressMinimum)); + DEBUG ((DEBUG_ERROR, "%a: IsMinFixed = 0, IsMaxFixed = 0\n", __FUNCTION__, RangeLength)); + return EFI_INVALID_PARAMETER; + } + } else if ((IsMinFixed == EFI_ACPI_GENERAL_FLAG_MIN_IS_FIXED) && + (IsMaxFixed == EFI_ACPI_GENERAL_FLAG_MAX_IS_FIXED)) + { + // >0 1 1 + if (AddressGranularity != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: AddressGranularity=0x%lX != 0\n", __FUNCTION__, AddressGranularity)); + DEBUG ((DEBUG_ERROR, "%a: When RangeLength=0x%lX > 0, IsMinFixed = 1, and IsMaxFixed = 1\n", __FUNCTION__, RangeLength)); + return EFI_INVALID_PARAMETER; + } else if (RangeLength != (AddressMaximum - AddressMinimum + 1)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: RangeLength=0x%lX != (AddrRangeMax=0x%lX - AddrRangeMin=0x%lX + 1)\n", __FUNCTION__, RangeLength, AddressMaximum, AddressMinimum)); + DEBUG ((DEBUG_ERROR, "%a: IsMinFixed = 1, IsMaxFixed = 1\n", __FUNCTION__, RangeLength)); + return EFI_INVALID_PARAMETER; + } + } else { + // >0 0 1 (Invalid combination) + // >0 1 0 (Invalid combination) + DEBUG ((DEBUG_ERROR, "%a: ERROR: When RangeLength=0x%lX > 0,\n", __FUNCTION__, RangeLength)); + DEBUG ((DEBUG_ERROR, "%a: IsMinFixed and IsMaxFixed must both be either 1 or 0\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + +/* + Internal function to create DWord Address Space Descriptors + + This function only requires a single call and therefore no Phases + Generates: + 6.4.3.5.2 DWord Address Space Descriptor + Type 1, Large Item Value 0x7 + The DWORD address space descriptor is used to report resource usage in a + 32-bit address space (like memory and I/O). + + @param[in] ResourceType + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] TypeSpecificFlags, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed DWordSpace buffer + + @retval EFI_SUCCESS + @retval Error status +*/ +EFI_STATUS +EFIAPI +InternalAmlOPDWordAddressSpace ( + IN UINT8 ResourceType, + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 TypeSpecificFlags, + IN UINT32 AddressGranularity, + IN UINT32 AddressMinimum, + IN UINT32 AddressMaximum, + IN UINT32 AddressTranslation, + IN UINT32 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + + // Vaidate General Flags Input + if ((ResourceUsage & ~EFI_ACPI_GENERAL_FLAG_MASK_USAGE) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Dword Invalid ResourceUsage Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((Decode & ~EFI_ACPI_GENERAL_FLAG_MASK_DEC) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Dword Invalid Decode Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((IsMinFixed & ~EFI_ACPI_GENERAL_FLAG_MASK_MIF) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Dword Invalid IsMinFixed Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((IsMaxFixed & ~EFI_ACPI_GENERAL_FLAG_MASK_MAF) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Dword Invalid IsMaxFixed Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlAddressSpaceCheck ( + IsMinFixed, + IsMaxFixed, + AddressGranularity, + AddressMinimum, + AddressMaximum, + RangeLength + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: DWord Address Space Check FAILED\n", __FUNCTION__)); + return Status; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "DWORD_ADDRESS")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "DWORD_ADDRESS")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR *)Object->Data; + Descriptor->Header.Header.Byte = ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR; + Descriptor->Header.Length = sizeof (EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR) - + sizeof (ACPI_LARGE_RESOURCE_HEADER); + Descriptor->ResType = ResourceType; + Descriptor->GenFlag = IsMinFixed | IsMaxFixed | Decode; + Descriptor->SpecificFlag = TypeSpecificFlags; + Descriptor->AddrSpaceGranularity = AddressGranularity; + Descriptor->AddrRangeMin = AddressMinimum; + Descriptor->AddrRangeMax = AddressMaximum; + Descriptor->AddrTranslationOffset = AddressTranslation; + Descriptor->AddrLen = RangeLength; + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.32 DMA (DMA Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + DMA (DmaType, IsBusMaster, DmaTransferSize, DescriptorName) {DmaChannelList} => Buffer (BitMask) + + Generates: 6.4.2.2 DMA Descriptor + + @param[in] DmaType - DMA channel speed supported + @param[in] IsBusMaster - Logical device bus master status + @param[in] DmaTransferSize - DMA transfer type preference (8-bit, 16-bit, both) + @param[in] DmaChannelList - DMA channel mask bits [7:0] (channels 0 - 7), _DMA + Bit [0] is channel 0, etc. + // DescriptorName - Optional - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed DWordIO buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPDma ( + IN EFI_ACPI_DMA_SPEED_TYPE_KEYWORDS DmaType, + IN EFI_ACPI_DMA_BUS_MASTER_KEYWORDS IsBusMaster, + IN EFI_ACPI_DMA_TRANSFER_TYPE_KEYWORDS DmaTransferSize, + IN UINT8 DmaChannelList, + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_DMA_DESCRIPTOR *Descriptor; + + if ((DmaType & (UINT8) ~EFI_ACPI_DMA_SPEED_TYPE_MASK) != 0) { + // Invalid DmaType value + DEBUG ((DEBUG_ERROR, "%a: ERROR: DmaType '%x' is not valid.\n", __FUNCTION__, DmaType)); + return EFI_INVALID_PARAMETER; + } + + if ((IsBusMaster & ~EFI_ACPI_DMA_BUS_MASTER_MASK) != 0) { + // Invalid IsBusMaster value + DEBUG ((DEBUG_ERROR, "%a: ERROR: IsBusMaster '%x' is not valid.\n", __FUNCTION__, DmaType)); + return EFI_INVALID_PARAMETER; + } + + if (((DmaTransferSize & ~EFI_ACPI_DMA_TRANSFER_TYPE_MASK) != 0) || + (DmaTransferSize == 0x3)) + { + // Invalid DmaTransferSize value + DEBUG ((DEBUG_ERROR, "%a: ERROR: DmaTransferSize '%x' is not valid.\n", __FUNCTION__, DmaType)); + return EFI_INVALID_PARAMETER; + } + + if (ListHead == NULL) { + // Invalid + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid parameter, ListHead cannot == NULL.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a cannot create %a object.", __FUNCTION__, "DMA_RESOURCE")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_DMA_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "DMA_RESOURCE")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_DMA_DESCRIPTOR *)Object->Data; + Descriptor->Header.Byte = ACPI_DMA_DESCRIPTOR; + Descriptor->ChannelMask = DmaChannelList; + // + // Descriptor->Information bit mask: + // Bit [7] Reserved (must be 0) + // Bits [6:5] DMA channel speed supported, _TYP + // 00 Indicates compatibility mode + // 01 Indicates Type A DMA as described in the EISA + // 10 Indicates Type B DMA + // 11 Indicates Type F + // Bits [4:3] Ignored + // Bit [2] Logical device bus master status, _BM + // 0 Logical device is not a bus master + // 1 Logical device is a bus master + // Bits [1:0] DMA transfer type preference, _SIZ + // 00 8-bit only + // 01 8- and 16-bit + // 10 16-bit only + Descriptor->Information = (UINT8)(DmaType + + IsBusMaster + + DmaTransferSize); + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.35 DWordSpace (DWord Space Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + DWordSpace (ResourceType, ResourceUsage, Decode, IsMinFixed, IsMaxFixed, + TypeSpecificFlags, AddressGranularity, AddressMinimum, + AddressMaximum, AddressTranslation, RangeLength, + ResourceSourceIndex, ResourceSource, DescriptorName) + + Generates: + 6.4.3.5.2 DWord Address Space Descriptor + Type 1, Large Item Value 0x7 + + @param[in] ResourceType + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] TypeSpecificFlags, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed DWordSpace buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPDWordSpace ( + IN UINT8 ResourceType, + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 TypeSpecificFlags, + IN UINT32 AddressGranularity, + IN UINT32 AddressMinimum, + IN UINT32 AddressMaximum, + IN UINT32 AddressTranslation, + IN UINT32 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + // UINT8 ResourceType cannot be > 0xFF, so no need to check top end. + if (ResourceType < EFI_ACPI_SPACE_RESOURCE_TYPE_MIN) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid ResourceType\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPDWordAddressSpace ( + ResourceType, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + TypeSpecificFlags, + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/** + 19.6.33 DWordIO (DWord IO Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + DWordIO (ResourceUsage, IsMinFixed, IsMaxFixed, Decode, ISARanges, + AddressGranularity, AddressMinimum, AddressMaximum, + AddressTranslation, RangeLength, ResourceSourceIndex, + ResourceSource, DescriptorName, TranslationType, + TranslationDensity) + + defines for pass in parameters can be found in: + MdePkg/Include/IndustryStandard/Acpi10.h + + @param[in] ResourceUsage, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] Decode, + @param[in] ISARanges, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + TranslationType - NOT IMPLEMENTED + TranslationDensity - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed DWordIO buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPDWordIO ( + IN UINT8 ResourceUsage, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 Decode, + IN UINT8 ISARanges, + IN UINT32 AddressGranularity, + IN UINT32 AddressMinimum, + IN UINT32 AddressMaximum, + IN UINT32 AddressTranslation, + IN UINT32 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + // TranslationType - NOT IMPLEMENTED + // TranslationDensity - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + if (ISARanges == 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ISARanges = 0 = Reserved\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } else if (ISARanges > 3) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ISARanges > 3 are Invalid\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPDWordAddressSpace ( + ACPI_ADDRESS_SPACE_TYPE_IO, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + (ISARanges), + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/** + 19.6.34 DWordMemory (DWord Memory Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + DWordMemory (ResourceUsage, Decode, IsMinFixed, IsMaxFixed, Cacheable, + ReadAndWrite, AddressGranularity, AddressMinimum, AddressMaximum, + AddressTranslation, RangeLength, ResourceSourceIndex, + ResourceSource, DescriptorName, MemoryRangeType, TranslationType) + + defines for pass in parameters can be found in: + MdePkg/Include/IndustryStandard/Acpi10.h + + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] Cacheable, + @param[in] ReadAndWrite, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + MemoryRangeType - NOT IMPLEMENTED + TranslationType - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed DWordMemory buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPDWordMemory ( + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 Cacheable, + IN UINT8 ReadAndWrite, + IN UINT32 AddressGranularity, + IN UINT32 AddressMinimum, + IN UINT32 AddressMaximum, + IN UINT32 AddressTranslation, + IN UINT32 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + // MemoryRangeType - NOT IMPLEMENTED + // TranslationType - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + // Validate Type Specific Parameters + if ((Cacheable & ~EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_MASK_MEM) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid Cacheable Parameter 0x%X\n", __FUNCTION__, (Cacheable & ~EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_MASK_MEM))); + return EFI_INVALID_PARAMETER; + } + + if ((ReadAndWrite & ~EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_MASK_RW) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid ReadAndWrite Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPDWordAddressSpace ( + ACPI_ADDRESS_SPACE_TYPE_MEM, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + (Cacheable | ReadAndWrite), + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/* + Internal function to create QWord Address Space Descriptors + + This function only requires a single call and therefore no Phases + Generates: + 6.4.3.5.1 QWord Address Space Descriptor + Type 1, Large Item Value 0xA + The QWORD address space descriptor is used to report resource usage in a + 64-bit address space (like memory and I/O). + + @param[in] ResourceType + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] TypeSpecificFlags, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed QWordSpace buffer + + @retval EFI_SUCCESS + @retval Error status +*/ +EFI_STATUS +EFIAPI +InternalAmlOPQWordAddressSpace ( + IN UINT8 ResourceType, + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 TypeSpecificFlags, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 AddressTranslation, + IN UINT64 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + + // Vaidate General Flags Input + if ((ResourceUsage & ~EFI_ACPI_GENERAL_FLAG_MASK_USAGE) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Qword Invalid ResourceUsage Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((Decode & ~EFI_ACPI_GENERAL_FLAG_MASK_DEC) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Qword Invalid Decode Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((IsMinFixed & ~EFI_ACPI_GENERAL_FLAG_MASK_MIF) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Qword Invalid IsMinFixed Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((IsMaxFixed & ~EFI_ACPI_GENERAL_FLAG_MASK_MAF) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Qword Invalid IsMaxFixed Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlAddressSpaceCheck ( + IsMinFixed, + IsMaxFixed, + AddressGranularity, + AddressMinimum, + AddressMaximum, + RangeLength + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: QWord Address Space Check FAILED\n", __FUNCTION__)); + return Status; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "QWORD_ADDRESS")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "QWORD_ADDRESS")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR *)Object->Data; + Descriptor->Header.Header.Byte = ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR; + Descriptor->Header.Length = sizeof (EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR) - + sizeof (ACPI_LARGE_RESOURCE_HEADER); + Descriptor->ResType = ResourceType; + Descriptor->GenFlag = IsMinFixed | IsMaxFixed | Decode; + Descriptor->SpecificFlag = TypeSpecificFlags; + Descriptor->AddrSpaceGranularity = AddressGranularity; + Descriptor->AddrRangeMin = AddressMinimum; + Descriptor->AddrRangeMax = AddressMaximum; + Descriptor->AddrTranslationOffset = AddressTranslation; + Descriptor->AddrLen = RangeLength; + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.65 IRQ (Interrupt Resource Descriptor Macro) + + Syntax: + IRQ (EdgeLevel, ActiveLevel, Shared, DescriptorName) {InterruptList} => Buffer + + Arguments: + EdgeLevel: + Describes whether the interrupt is edge triggered (Edge) or level triggered + (Level). The field DescriptorName. _HE is automatically created to refer to + this portion of the resource descriptor, where '1' is Edge and ActiveHigh + and '0' is Level and ActiveLow. + + ActiveLevel: + Describes whether the interrupt is active-high (ActiveHigh) or active-low + (ActiveLow). The field DescriptorName. _LL is automatically created to refer + to this portion of the resource descriptor, where '1' is Edge and ActiveHigh + and '0' is Level and ActiveLow. + + Shared: + Describes whether the interrupt can be shared with other devices (Shared) or + not (Exclusive), and whether it is capable of waking the system from a + low-power idle or system sleep state (SharedAndWake or ExclusiveAndWake). + The field DescriptorName. _SHR is automatically created to refer to this portion + of the resource descriptor, where '1' is Shared and '0' is Exclusive. If nothing + is specified, then Exclusive is assumed. + + InterruptList: + IRQ mask bits [15:0] + Bit[0] represents IRQ0, bit[1] is IRQ1, etc. + + DescriptorName: + Is an optional argument that specifies a name for an integer constant that + will be created in the current scope that contains the offset of this resource + descriptor within the current resource template buffer. The predefined + descriptor field names may be appended to this name to access individual + fields within the descriptor via the Buffer Field operators. + + Description: + The IRQ macro evaluates to a buffer that contains an IRQ resource descriptor. + The format of the IRQ descriptor can be found in "IRQ Descriptor". The macro + produces the three-byte form of the descriptor. The macro is designed to be + used inside of a ResourceTemplate. + + Generates: 6.4.2.1 IRQ Descriptor + + @param[in] EdgeLevel - trigger level supported + @param[in] ActiveLevel - interrupt polarity + @param[in] Shared - interrupt exclusivity + @param[in] InterruptList - IRQ mask bits[7:0], _INT + Bit [0] represents IRQ0, + bit[1] is IRQ1, and so on. + IRQ mask bits[15:8], _INT + Bit [0] represents IRQ8, + bit[1] is IRQ9, and so on. + // DescriptorName - Optional - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed IRQ buffer + + @retval EFI_SUCCESS + @retval Error status + +**/ +EFI_STATUS +EFIAPI +AmlOPIRQ ( + IN EFI_ACPI_IRQ_INTERRUPT_MODE_KEYWORDS EdgeLevel, + IN EFI_ACPI_IRQ_INTERRUPT_POLARITY_KEYWORDS ActiveLevel, + IN EFI_ACPI_IRQ_INTERRUPT_SHARING_KEYWORDS Shared, + IN UINT16 InterruptList, + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_IRQ_DESCRIPTOR *Descriptor; + + if ((EdgeLevel & (UINT8) ~EFI_ACPI_IRQ_MODE_MASK) != 0) { + // Invalid Decode value + DEBUG ((DEBUG_ERROR, "%a: ERROR: EdgeLevel '%x' is not valid.\n", __FUNCTION__, EdgeLevel)); + return EFI_INVALID_PARAMETER; + } + + if ((ActiveLevel & (UINT8) ~EFI_ACPI_IRQ_POLARITY_MASK) != 0) { + // Invalid Decode value + DEBUG ((DEBUG_ERROR, "%a: ERROR: ActiveLevel '%x' is not valid.\n", __FUNCTION__, ActiveLevel)); + return EFI_INVALID_PARAMETER; + } + + if ((Shared & (UINT8) ~(EFI_ACPI_IRQ_WAKE_CAPABLE_MASK | EFI_ACPI_IRQ_SHARABLE_MASK)) != 0) { + // Invalid Decode value + DEBUG ((DEBUG_ERROR, "%a: ERROR: Shared '%x' is not valid.\n", __FUNCTION__, Shared)); + return EFI_INVALID_PARAMETER; + } + + if (ListHead == NULL) { + // Invalid + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid parameter, ListHead cannot == NULL.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Cannot create %a object.", __FUNCTION__, "IRQ_RESOURCE")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_IRQ_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Alloc for %a failed\n", __FUNCTION__, "IRQ_RESOURCE")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_IRQ_DESCRIPTOR *)Object->Data; + Descriptor->Header.Byte = ACPI_IRQ_DESCRIPTOR; + Descriptor->Mask = InterruptList; + // + // Ref 6.4.2.1 IRQ Descriptor - IRQ Information + // Descriptor->Information bit mask: + // IRQ Information. Each bit, when set, indicates this device is capable of + // driving a certain type of interrupt. (Optional-if not included then assume + // edge sensitive, high true interrupts.) These bits can be used both for + // reporting and setting IRQ resources. + // Note: This descriptor is meant for describing interrupts that are connected + // to PIC-compatible interrupt controllers, which can only be programmed + // for Active-High-Edge-Triggered or Active-Low-LevelTriggered interrupts. + // Any other combination is invalid. The Extended Interrupt Descriptor can + // be used to describe other combinations. + // + // Bit [7:6] Reserved (must be 0) + // Bit [5] Wake Capability, _WKC + // 0x0 = Not Wake Capable: This interrupt is not capable of waking the system. + // 0x1 = Wake Capable: This interrupt is capable of waking the system from a + // low-power idle state or a system sleep state. + // Bit [4] Interrupt Sharing, _SHR + // 0x0 = Exclusive: This interrupt is not shared with other devices. + // 0x1 = Shared: This interrupt is shared with other devices. + // Bit [3] Interrupt Polarity, _LL + // 0 Active-High - This interrupt is sampled when the signal is high, or true + // 1 Active-Low - This interrupt is sampled when the signal is low, or false. + // Bit [2:1] Ignored + // Bit [0] Interrupt Mode, _HE + // 0 Level-Triggered - Interrupt is triggered in response to signal in a low state. + // 1 Edge-Triggered - Interrupt is triggered in response to a change in signal state from + // low to high. + // + Descriptor->Information = (UINT8)((EFI_ACPI_IRQ_WAKE_CAPABLE_MASK | + EFI_ACPI_IRQ_SHARABLE_MASK | + EFI_ACPI_IRQ_POLARITY_MASK | + EFI_ACPI_IRQ_MODE_MASK) & + (Shared | + ActiveLevel | + EdgeLevel)); + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.64 IO (IO Resource Descriptor Macro) + + Syntax: + IO (Decode, AddressMin, AddressMax, AddressAlignment, RangeLength, DescriptorName) => Buffer + + Arguments: + Decode: + Describes whether the I/O range uses 10-bit decode (Decode10) or 16-bit + decode (Decode16). The field DescriptorName. _DEC is automatically created + to refer to this portion of the resource descriptor, where '1' is Decode16 + and '0' is Decode10. + + AddressMin: + Evaluates to a 16-bit integer that specifies the minimum acceptable starting + address for the I/O range. It must be an even multiple of AddressAlignment. + The field DescriptorName._MIN is automatically created to refer to this + portion of the resource descriptor. + + AddressMax: + Evaluates to a 16-bit integer that specifies the maximum acceptable starting + address for the I/O range. It must be an even multiple of AddressAlignment. + The field DescriptorName._MAX is automatically created to refer to this + portion of the resource descriptor. + + AddressAlignment: + Evaluates to an 8-bit integer that specifies the alignment granularity + for the I/O address assigned. The field DescriptorName. _ALN is automatically + created to refer to this portion of the resource descriptor. + + RangeLength: + Evaluates to an 8-bit integer that specifies the number of bytes in the + I/O range. The field DescriptorName. _LEN is automatically created to refer + to this portion of the resource descriptor. + + DescriptorName: + An optional argument that specifies a name for an integer constant that + will be created in the current scope that contains the offset of this + resource descriptor within the current resource template buffer. The + predefined descriptor field names may be appended to this name to access + individual fields within the descriptor via the Buffer Field operators. + + Description: + The IO macro evaluates to a buffer which contains an IO resource descriptor. + The format of the IO descriptor can be found in the ACPI Specification section + "I/O Port Descriptor". The macro is designed to be used inside of a ResourceTemplate. + + Generates: + 6.4.2.5 I/O Port Descriptor + Type 0, Small Item Name 0x8, Length = 7 + + @param[in] Decode, + @param[in] AddressMin, + @param[in] AddressMax, + @param[in] AddressAlignment, + @param[in] RangeLength, + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed IO buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPIO ( + IN EFI_ACPI_IO_PORT_DESCRIPTOR_INFORMATION Decode, + IN UINT16 AddressMin, + IN UINT16 AddressMax, + IN UINT8 AddressAlignment, + IN UINT8 RangeLength, + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_IO_PORT_DESCRIPTOR *Descriptor; + UINT64 Remainder; + + if ((Decode & (UINT8) ~EFI_ACPI_IO_DECODE_MASK) != 0) { + // Invalid Decode value + DEBUG ((DEBUG_ERROR, "%a: ERROR: Decode '%x' is not valid.\n", __FUNCTION__, Decode)); + return EFI_INVALID_PARAMETER; + } + + if (ListHead == NULL) { + // Invalid + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid parameter, ListHead cannot == NULL.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if (AddressAlignment != 0) { + DivU64x64Remainder (AddressMin, AddressAlignment, &Remainder); + if (Remainder != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: (AddressMin=0x%X) is not a multiple of\n", __FUNCTION__, AddressMin)); + DEBUG ((DEBUG_ERROR, "%a: (AddressAlignment)=0x%X\n", __FUNCTION__, AddressAlignment)); + return EFI_INVALID_PARAMETER; + } + + DivU64x64Remainder (AddressMax, AddressAlignment, &Remainder); + if (Remainder != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: (AddressMax=0x%X) is not a multiple of\n", __FUNCTION__, AddressMax)); + DEBUG ((DEBUG_ERROR, "%a: (AddressAlignment)=0x%X\n", __FUNCTION__, AddressAlignment)); + return EFI_INVALID_PARAMETER; + } + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a cannot create %a object.", __FUNCTION__, "IO_RESOURCE")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_IO_PORT_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "IO_RESOURCE")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_IO_PORT_DESCRIPTOR *)Object->Data; + + /* + * According to ACPI spec for + * ACPI_IO_PORT_DESCRIPTOR = 0x47 contains the informaion about + * Name, Type and Length, hence no need to calculate the length. + * Below is description from ACPI spec + * Byte 0 I/O Port Descriptor Value = 0x47 (01000111B) - Type = 0, Small item name = + * 0x8, Length = 7 + */ + Descriptor->Header.Byte = ACPI_IO_PORT_DESCRIPTOR; + // + // Descriptor->Information bit mask: + // Bit [7:1] Reserved, must be 0 + // Bit [0] (_DEC) + // 1 The logical device decodes 16-bit addresses + // 0 The logical device decodes 10-bit addresses + Descriptor->Information = (UINT8)(EFI_ACPI_IO_DECODE_MASK & Decode); + Descriptor->BaseAddressMin = AddressMin; + Descriptor->BaseAddressMax = AddressMax; + Descriptor->Alignment = AddressAlignment; + Descriptor->Length = RangeLength; + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/* + 19.6.114 Register (Generic Register Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, + RegisterAddress, AccessSize, DescriptorName) + + Generates: + 6.4.3.7 Generic Register Descriptor + Type 1, Large Item Value 0x2 + The generic register descriptor describes the location of a fixed width + register within any of the ACPI-defined address spaces. See Generic Register + Descriptor for details. + + + @param[in] AddressSpaceKeyword, + @param[in] RegisterBitWidth, + @param[in] RegisterBitOffset, + @param[in] RegisterAddress, + @param[in] AccessSize, + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed QWordSpace buffer + + @retval EFI_SUCCESS + @retval Error status +*/ +EFI_STATUS +EFIAPI +AmlOPRegister ( + IN GENERIC_ADDRESS_SPACE_ID AddressSpaceKeyword, + IN UINT8 RegisterBitWidth, + IN UINT8 RegisterBitOffset, + IN UINT64 RegisterAddress, + IN UINT8 AccessSize, + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR *Descriptor; + + if ((AddressSpaceKeyword < EFI_ACPI_6_4_SYSTEM_MEMORY) || + (AddressSpaceKeyword > EFI_ACPI_6_4_FUNCTIONAL_FIXED_HARDWARE)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid AddressSpaceKeyword=0x%02X\n", __FUNCTION__, AddressSpaceKeyword)); + return EFI_INVALID_PARAMETER; + } + + if ((AddressSpaceKeyword > EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL) && + (AddressSpaceKeyword < EFI_ACPI_6_4_FUNCTIONAL_FIXED_HARDWARE)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid AddressSpaceKeyword=0x%02X\n", __FUNCTION__, AddressSpaceKeyword)); + return EFI_INVALID_PARAMETER; + } + + if (AccessSize > EFI_ACPI_6_4_QWORD) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid AccessSize=0x%02X\n", __FUNCTION__, AccessSize)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a cannot create %a object.", __FUNCTION__, "IO_RESOURCE")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "IO_RESOURCE")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR *)Object->Data; + + Descriptor->Header.Header.Byte = ACPI_GENERIC_REGISTER_DESCRIPTOR; + Descriptor->Header.Length = sizeof (EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR) - + sizeof (ACPI_LARGE_RESOURCE_HEADER); + Descriptor->AddressSpaceId = AddressSpaceKeyword; + Descriptor->RegisterBitWidth = RegisterBitWidth; + Descriptor->RegisterBitOffset = RegisterBitOffset; + Descriptor->AddressSize = AccessSize; + Descriptor->RegisterAddress = RegisterAddress; + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/* + 19.6.111 QWordSpace (QWord Space Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + QWordSpace (ResourceType, ResourceUsage, Decode, IsMinFixed, IsMaxFixed, + TypeSpecificFlags, AddressGranularity, AddressMinimum, + AddressMaximum, AddressTranslation, RangeLength, + ResourceSourceIndex, ResourceSource, DescriptorName) + + Generates: + 6.4.3.5.1 QWord Address Space Descriptor + Type 1, Large Item Value 0xA + The QWORD address space descriptor is used to report resource usage in a + 64-bit address space (like memory and I/O). + + + @param[in] ResourceType + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] TypeSpecificFlags, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed QWordSpace buffer + + @retval EFI_SUCCESS + @retval Error status +*/ +EFI_STATUS +EFIAPI +AmlOPQWordSpace ( + IN UINT8 ResourceType, + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 TypeSpecificFlags, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 AddressTranslation, + IN UINT64 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + // UINT8 ResourceType cannot be > 0xFF, so no need to check top end. + if (ResourceType < EFI_ACPI_SPACE_RESOURCE_TYPE_MIN) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid ResourceType\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPQWordAddressSpace ( + ResourceType, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + TypeSpecificFlags, + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/** + 19.6.82 Memory32Fixed (Memory Resource Descriptor Macro) + + Syntax: + Memory32Fixed (ReadAndWrite, AddressBase, RangeLength, DescriptorName) + + Arguments: + ReadAndWrite: Specifies whether or not the memory region is read-only (ReadOnly) + or read/write (ReadWrite). If nothing is specified, then ReadWrite is assumed. + The 1-bit field DescriptorName._RW is automatically created to refer to this + portion of the resource descriptor, where '1' is ReadWrite and '0' is ReadOnly. + + AddressBase: Evaluates to a 32-bit integer that specifies the base address + of the memory range. The 32-bit field DescriptorName. _BAS is automatically + created to refer to this portion of the resource descriptor. + + RangeLength: Evaluates to a 32-bit integer that specifies the total number of + bytes decoded in the memory range. The 32-bit field DescriptorName. _LEN is + automatically created to refer to this portion of the resource descriptor. + + DescriptorName: Is an optional argument that specifies a name for an integer + constant that will be created in the current scope that contains the offset + of this resource descriptor within the current resource template buffer. The + predefined descriptor field names may be appended to this name to access + individual fields within the descriptor via the Buffer Field operators. + + Description: + The Memory32Fixed macro evaluates to a buffer which contains a 32-bit memory + descriptor, which describes a fixed range of memory addresses. The format of + the fixed 32-bit memory descriptor can be found in 32-Bit Fixed Memory Range + Descriptor. The macro is designed to be used inside of a ResourceTemplate. + + Generates: + 6.4.3.4 32-Bit Fixed Memory Range Descriptor + Type 1, Large Item Value 0x6 + This memory range descriptor describes a device's memory resources within a + 32-bit address space. + + @param[in] ReadAndWrite, + @param[in] AddressBase, + @param[in] RangeLength, + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed memory resource descriptor + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPMemory32Fixed ( + IN READ_WRITE_FLAG ReadAndWrite, + IN UINT32 AddressBase, + IN UINT32 RangeLength, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR *Descriptor; + + if ((ReadAndWrite & (UINT8) ~EFI_ACPI_MEMORY_WRITE_STATUS_MASK) != 0) { + // Invalid ReadAndWrite value + DEBUG ((DEBUG_ERROR, "%a: ERROR: ReadAndWrite '%x' is not valid.\n", __FUNCTION__, ReadAndWrite)); + return EFI_INVALID_PARAMETER; + } + + if (ListHead == NULL) { + // Invalid + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid parameter, ListHead cannot == NULL.\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a cannot create %a object.", __FUNCTION__, "MEMORY_32_FIXED_RESOURCE")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "MEMORY_32_FIXED_RESOURCE")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR *)Object->Data; + Descriptor->Header.Header.Byte = ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR; + Descriptor->Header.Length = sizeof (EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR) - + sizeof (ACPI_LARGE_RESOURCE_HEADER); + Descriptor->Information = ReadAndWrite; + Descriptor->BaseAddress = AddressBase; + Descriptor->Length = RangeLength; + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.109 QWordIO (QWord IO Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + QWordIO (ResourceUsage, IsMinFixed, IsMaxFixed, Decode, ISARanges, + AddressGranularity, AddressMinimum, AddressMaximum, + AddressTranslation, RangeLength, ResourceSourceIndex, + ResourceSource, DescriptorName, TranslationType, + TranslationDensity) + + defines for pass in parameters can be found in: + MdePkg/Include/IndustryStandard/Acpi10.h + + @param[in] ResourceUsage, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] Decode, + @param[in] ISARanges, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + TranslationType - NOT IMPLEMENTED + TranslationDensity - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed QWordIO buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPQWordIO ( + IN UINT8 ResourceUsage, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 Decode, + IN UINT8 ISARanges, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 AddressTranslation, + IN UINT64 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + // TranslationType - NOT IMPLEMENTED + // TranslationDensity - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + if (ISARanges == 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ISARanges = 0 = Reserved\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } else if (ISARanges > 3) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ISARanges > 3 is Invalid\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPQWordAddressSpace ( + ACPI_ADDRESS_SPACE_TYPE_IO, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + (ISARanges), + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/** + 19.6.110 QWordMemory (QWord Memory Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + QWordMemory (ResourceUsage, Decode, IsMinFixed, IsMaxFixed, Cacheable, + ReadAndWrite, AddressGranularity, AddressMinimum, AddressMaximum, + AddressTranslation, RangeLength, ResourceSourceIndex, + ResourceSource, DescriptorName, MemoryRangeType, TranslationType) + + defines for pass in parameters can be found in: + MdePkg/Include/IndustryStandard/Acpi10.h + + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] Cacheable, + @param[in] ReadAndWrite, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + MemoryRangeType - NOT IMPLEMENTED + TranslationType - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed QWordMemory buffer + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPQWordMemory ( + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 Cacheable, + IN UINT8 ReadAndWrite, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 AddressTranslation, + IN UINT64 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + // MemoryRangeType - NOT IMPLEMENTED + // TranslationType - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + // Validate Type Specific Parameters + if ((Cacheable & ~EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_MASK_MEM) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid Cacheable Parameter 0x%X\n", __FUNCTION__, (Cacheable & ~EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_MASK_MEM))); + return EFI_INVALID_PARAMETER; + } + + if ((ReadAndWrite & ~EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_MASK_RW) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid ReadAndWrite Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPQWordAddressSpace ( + ACPI_ADDRESS_SPACE_TYPE_MEM, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + (Cacheable | ReadAndWrite), + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/* + Internal function to create DWord Address Space Descriptors + + This function only requires a single call and therefore no Phases + Generates: + 6.4.3.5.3 Word Address Space Descriptor + Type 1, Large Item Value 0x8 + The WORD address space descriptor is used to report resource usage in a + 16-bit address space (like memory and I/O, Bus Number). + + @param[in] ResourceType + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] TypeSpecificFlags, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed WordSpace Descriptor + + @retval EFI_SUCCESS + @retval Error status +*/ +EFI_STATUS +EFIAPI +InternalAmlOPWordAddressSpace ( + IN UINT8 ResourceType, + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 TypeSpecificFlags, + IN UINT16 AddressGranularity, + IN UINT16 AddressMinimum, + IN UINT16 AddressMaximum, + IN UINT16 AddressTranslation, + IN UINT16 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + + // Vaidate General Flags Input + if ((ResourceUsage & ~EFI_ACPI_GENERAL_FLAG_MASK_USAGE) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Word Invalid ResourceUsage Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((Decode & ~EFI_ACPI_GENERAL_FLAG_MASK_DEC) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Word Invalid Decode Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((IsMinFixed & ~EFI_ACPI_GENERAL_FLAG_MASK_MIF) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Word Invalid IsMinFixed Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + if ((IsMaxFixed & ~EFI_ACPI_GENERAL_FLAG_MASK_MAF) != 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Word Invalid IsMaxFixed Parameter\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlAddressSpaceCheck ( + IsMinFixed, + IsMaxFixed, + AddressGranularity, + AddressMinimum, + AddressMaximum, + RangeLength + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Word Address Space Check FAILED\n", __FUNCTION__)); + return Status; + } + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Start %a object\n", __FUNCTION__, "WORD_ADDRESS")); + goto Done; + } + + Object->DataSize = sizeof (EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a Alloc Failed\n", __FUNCTION__, "DWORD_ADDRESS")); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Descriptor = (EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR *)Object->Data; + Descriptor->Header.Header.Byte = ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR; + Descriptor->Header.Length = sizeof (EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR) - + sizeof (ACPI_LARGE_RESOURCE_HEADER); + Descriptor->ResType = ResourceType; + Descriptor->GenFlag = IsMinFixed | IsMaxFixed | Decode; + Descriptor->SpecificFlag = TypeSpecificFlags; + Descriptor->AddrSpaceGranularity = AddressGranularity; + Descriptor->AddrRangeMin = AddressMinimum; + Descriptor->AddrRangeMax = AddressMaximum; + Descriptor->AddrTranslationOffset = AddressTranslation; + Descriptor->AddrLen = RangeLength; + Object->Completed = TRUE; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + } + + return Status; +} + +/** + 19.6.152 WordSpace (Word Space Resource Descriptor Macro) ) + + This function only requires a single call and therefore no Phases + Syntax + WordSpace (ResourceType, ResourceUsage, Decode, IsMinFixed, IsMaxFixed, + TypeSpecificFlags, AddressGranularity, AddressMinimum, + AddressMaximum, AddressTranslation, RangeLength, + ResourceSourceIndex, ResourceSource, DescriptorName) + + Generates: + 6.4.3.5.3 Word Address Space Descriptor + Type 1, Large Item Value 0x8 + + @param[in] ResourceType + @param[in] ResourceUsage, + @param[in] Decode, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] TypeSpecificFlags, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed WordSpace Descriptor + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPWordSpace ( + IN UINT8 ResourceType, + IN UINT8 ResourceUsage, + IN UINT8 Decode, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 TypeSpecificFlags, + IN UINT16 AddressGranularity, + IN UINT16 AddressMinimum, + IN UINT16 AddressMaximum, + IN UINT16 AddressTranslation, + IN UINT16 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + // UINT8 ResourceType cannot be > 0xFF, so no need to check top end. + if (ResourceType < EFI_ACPI_SPACE_RESOURCE_TYPE_MIN) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid ResourceType\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPWordAddressSpace ( + ResourceType, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + TypeSpecificFlags, + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/** + 19.6.150 WordBusNumber (Word Bus Number Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + WordBusNumber (ResourceUsage, IsMinFixed, IsMaxFixed, Decode, + AddressGranularity, AddressMinimum, AddressMaximum, + AddressTranslation, RangeLength, ResourceSourceIndex, + ResourceSource, DescriptorName) + + defines for pass in parameters can be found in: + MdePkg/Include/IndustryStandard/Acpi10.h + + @param[in] ResourceUsage, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] Decode, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed WordBusNumber + Descriptor + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPWordBusNumber ( + IN UINT8 ResourceUsage, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 Decode, + IN UINT16 AddressGranularity, + IN UINT16 AddressMinimum, + IN UINT16 AddressMaximum, + IN UINT16 AddressTranslation, + IN UINT16 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + Status = InternalAmlOPWordAddressSpace ( + ACPI_ADDRESS_SPACE_TYPE_BUS, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + 0, + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} + +/** + 19.6.151 WordIO (Word IO Resource Descriptor Macro) + + This function only requires a single call and therefore no Phases + Syntax + WordIO (ResourceUsage, IsMinFixed, IsMaxFixed, Decode, ISARanges, + AddressGranularity, AddressMinimum, AddressMaximum, + AddressTranslation, RangeLength, ResourceSourceIndex, + ResourceSource, DescriptorName, TranslationType, TranslationDensity) + + defines for pass in parameters can be found in: + MdePkg/Include/IndustryStandard/Acpi10.h + + @param[in] ResourceUsage, + @param[in] IsMinFixed, + @param[in] IsMaxFixed, + @param[in] Decode, + @param[in] ISARanges, + @param[in] AddressGranularity, + @param[in] AddressMinimum, + @param[in] AddressMaximum, + @param[in] AddressTranslation, + @param[in] RangeLength, + ResourceSourceIndex - NOT IMPLEMENTED + ResourceSource - NOT IMPLEMENTED + DescriptorName - NOT IMPLEMENTED + TranslationType - NOT IMPLEMENTED + TranslationDensity - NOT IMPLEMENTED + @param[in,out] ListHead - Linked list has completed WordIO Descriptor + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPWordIO ( + IN UINT8 ResourceUsage, + IN UINT8 IsMinFixed, + IN UINT8 IsMaxFixed, + IN UINT8 Decode, + IN UINT8 ISARanges, + IN UINT16 AddressGranularity, + IN UINT16 AddressMinimum, + IN UINT16 AddressMaximum, + IN UINT16 AddressTranslation, + IN UINT16 RangeLength, + // ResourceSourceIndex - NOT IMPLEMENTED + // ResourceSource - NOT IMPLEMENTED + // DescriptorName - NOT IMPLEMENTED + // TranslationType - NOT IMPLEMENTED + // TranslationDensity - NOT IMPLEMENTED + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + + if (ISARanges == 0) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ISARanges = 0 = Reserved\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } else if (ISARanges > 3) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: ISARanges > 3 is Invalid\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + Status = InternalAmlOPWordAddressSpace ( + ACPI_ADDRESS_SPACE_TYPE_IO, + ResourceUsage, + Decode, + IsMinFixed, + IsMaxFixed, + (ISARanges), + AddressGranularity, + AddressMinimum, + AddressMaximum, + AddressTranslation, + RangeLength, + ListHead + ); + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c new file mode 100644 index 0000000000000000000000000000000000000000..64066e13317969b2d78f0f158d20a2b49f032d95 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlStatementOpcodes.c @@ -0,0 +1,512 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + Creates an Else object + + TermList must be created between AmlStart and AmlClose Phase + + Since ElseIf (...) is created with Else {( If (){})}. ElseIf will not be + supported and must be created with Else and If. + + DefElse := Nothing | + ElseOp := 0xA1 + + EXAMPLE: + AmlIf (AmlStart, ListHead); + { + { // Predicate + AmlOpDataInteger (1, ListHead); + } // Predicate + { // TermList + ... + } // TermList + } + AmlIf (AmlClose, ListHead); + AmlElse (AmlStart, ListHead); + { + AmlIf (AmlStart, ListHead); + { + {} // Predicate + {} // Termlist + } + AmlIf (AmlClose, ListHead); + AmlElse (AmlStart, ListHead); + {} // TermList + AmlElse (AmlClose, ListHead); + } + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed AmlElse Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlElse ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, "Else", ListHead); + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: If PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // DataRefObject is outside the scope of this object + break; + case AmlClose: + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: close PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // DataRefObject should be closed already + Status = InternalAmlLocateObjectByIdentifier (&Object, "Else", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating Return Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collecting Child data\n", __FUNCTION__)); + goto Done; + } + + // Handle Return with no arguments + if ((ChildObject->Data == NULL) || (ChildObject->DataSize == 0)) { + Status = EFI_DEVICE_ERROR; + DEBUG ((DEBUG_ERROR, "%a: ERROR: If must have at least a Predicate\n", __FUNCTION__)); + goto Done; + } + + // Allocate buffer for Return object + Object->Data = AllocatePool (ChildObject->DataSize + 1); + Object->DataSize = ChildObject->DataSize + 1; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object=Return\n", __FUNCTION__)); + goto Done; + } + + // Fill out Return object + Object->Data[0] = AML_ELSE_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a If object + + Predicate and TermList must be created between AmlStart and AmlClose Phase + + Since ElseIf (...) is created with Else {( If (){})}. ElseIf will not be + supported and must be created with Else and If. + + DefIfElse := IfOp PkgLength Predicate TermList DefElse + IfOp := 0xA0 + Predicate := TermArg => Integer + + EXAMPLE: + AmlIf (AmlStart, ListHead); + { + { // Predicate + AmlOpDataInteger (1, ListHead); + } // Predicate + { // TermList + ... + } // TermList + } + AmlIf (AmlClose, ListHead); + AmlElse (AmlStart, ListHead); + { + AmlIf (AmlStart, ListHead); + { + {} // Predicate + {} // Termlist + } + AmlIf (AmlClose, ListHead); + AmlElse (AmlStart, ListHead); + {} // TermList + AmlElse (AmlClose, ListHead); + } + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed AmlIf Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlIf ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, "If", ListHead); + + // Start required PkgLength + Status = AmlPkgLength (AmlStart, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: If PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // DataRefObject is outside the scope of this object + break; + case AmlClose: + // Close required PkgLength before finishing Object + Status = AmlPkgLength (AmlClose, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: close PkgLength object\n", __FUNCTION__)); + goto Done; + } + + // DataRefObject should be closed already + Status = InternalAmlLocateObjectByIdentifier (&Object, "If", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating Return Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collecting Child data\n", __FUNCTION__)); + goto Done; + } + + // Handle Return with no arguments + if ((ChildObject->Data == NULL) || (ChildObject->DataSize == 0)) { + Status = EFI_DEVICE_ERROR; + DEBUG ((DEBUG_ERROR, "%a: ERROR: If must have at least a Predicate\n", __FUNCTION__)); + goto Done; + } + + // Allocate buffer for Return object + Object->Data = AllocatePool (ChildObject->DataSize + 1); + Object->DataSize = ChildObject->DataSize + 1; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object=Return\n", __FUNCTION__)); + goto Done; + } + + // Fill out Return object + Object->Data[0] = AML_IF_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a Notify object + + DefNotify := NotifyOp NotifyObject NotifyValue + NotifyOp := 0x86 + NotifyObject := SuperName => ThermalZone | Processor | Device + NotifyValue := TermArg => Integer + + @param[in] NotifyObject - String of Namestring to a device + @param[in] NotifyValue - Integer Notify value + @param[in,out] ListHead - Linked list updated with Notify object + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlOPNotify ( + IN CHAR8 *NotifyObject, + IN UINT64 NotifyValue, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + Status = InternalAppendNewAmlObject (&Object, NotifyObject, ListHead); + Status = AmlOPNameString (NotifyObject, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Failed creating NotifyObject NameString\n", __FUNCTION__)); + goto Done; + } + + Status = AmlOPDataInteger (NotifyValue, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Failed creating NotifyValue Integer\n", __FUNCTION__)); + goto Done; + } + + Status = InternalAmlLocateObjectByIdentifier (&Object, NotifyObject, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating Return Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collecting Child data\n", __FUNCTION__)); + goto Done; + } + + // Allocate buffer for Return object + Object->Data = AllocatePool (ChildObject->DataSize + 1); + Object->DataSize = ChildObject->DataSize + 1; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object=Return\n", __FUNCTION__)); + goto Done; + } + + // Fill out Return object + Object->Data[0] = AML_NOTIFY_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} + +/** + Creates a Return object + + Object must be created between AmlStart and AmlClose Phase + + DefReturn := ReturnOp ArgObject + ReturnOp := 0xA4 + ArgObject := TermArg => DataRefObject + + @param[in] Phase - Either AmlStart or AmlClose + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlReturn ( + IN AML_FUNCTION_PHASE Phase, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, "Return", ListHead); + // DataRefObject is outside the scope of this object + break; + case AmlClose: + // DataRefObject should be closed already + Status = InternalAmlLocateObjectByIdentifier (&Object, "Return", ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locating Return Object\n", __FUNCTION__)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: collecting Child data\n", __FUNCTION__)); + goto Done; + } + + // Handle Return with no arguments + if ((ChildObject->Data == NULL) || (ChildObject->DataSize == 0)) { + // Return without arguments is treated like Return(0) + // Zeroed byte = ZeroOp + ChildObject->Data = AllocateZeroPool (sizeof (UINT8)); + if (ChildObject->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Zero Child for Return\n", __FUNCTION__)); + goto Done; + } + + ChildObject->DataSize = 1; + } + + // Allocate buffer for Return object + Object->Data = AllocatePool (ChildObject->DataSize + 1); + Object->DataSize = ChildObject->DataSize + 1; + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object=Return\n", __FUNCTION__)); + goto Done; + } + + // Fill out Return object + Object->Data[0] = AML_RETURN_OP; + CopyMem ( + &Object->Data[1], + ChildObject->Data, + ChildObject->DataSize + ); + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlTable.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlTable.c new file mode 100644 index 0000000000000000000000000000000000000000..1d965572cf14946f78b06d102bf2b3f11eec2189 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/AmlTable.c @@ -0,0 +1,210 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +// String Length Constants +#define OEM_ID_LENGTH 6 +#define OEM_TABLE_ID_LENGTH 8 +#define SIGNATURE_LENGTH 4 +#define CREATOR_ID_LENGTH 4 + +/** + Creates an AML Encoded Table + Object must be created between AmlStart and AmlClose Phase + + DefBlockHeader := TableSignature TableLength SpecCompliance CheckSum OemID + OemTableID OemRevision CreatorID CreatorRevision + + TableSignature := DWordData // As defined in section 5.2.3. + TableLength := DWordData // Length of the table in bytes including the + // block header + SpecCompliance := ByteData // The revision of the structure. + CheckSum := ByteData // Byte checksum of the entire table. + OemID := ByteData(6) // OEM ID of up to 6 characters. + // If the OEM ID is shorter than 6 + // characters, it can be terminated with a + // NULL character. + OemTableID := ByteData(8) // OEM Table ID of up to 8 characters. + // If the OEM Table ID is shorter than + // 8 characters, it can be terminated with + // a NULL character. + OemRevision := DWordData // OEM Table Revision. + CreatorID := DWordData // Vendor ID of the ASL compiler. + CreatorRevision := DWordData // Revision of the ASL compiler. + + @param[in] Phase - Either AmlStart or AmlClose + @param[in] TableNameString - Table Name + @param[in] ComplianceRev - Compliance Revision + @param[in] OemId - OEM ID + @param[in] OemTableId - OEM ID of table + @param[in] OemRevision - OEM Revision number + @param[in] CreatorId - Vendor ID of the ASL compiler + @param[in] CreatorRevision - Vendor Revision of the ASL compiler + @param[in,out] ListHead - Linked list has completed String Object after + AmlClose. + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +AmlDefinitionBlock ( + IN AML_FUNCTION_PHASE Phase, + IN CHAR8 *TableNameString, + IN UINT8 ComplianceRev, + IN CHAR8 *OemId, + IN CHAR8 *OemTableId, + IN UINT32 OemRevision, + IN CHAR8 *CreatorId, + IN UINT32 CreatorRevision, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + UINTN ChildCount; + + if ((Phase >= AmlInvalid) || + (ListHead == NULL) || + (TableNameString == NULL) || + (OemId == NULL) || + (OemTableId == NULL) || + (CreatorId == NULL) || + (AsciiStrLen (TableNameString) != SIGNATURE_LENGTH) || + (AsciiStrLen (OemId) > OEM_ID_LENGTH) || + (AsciiStrLen (OemTableId) > OEM_TABLE_ID_LENGTH) || + (AsciiStrLen (CreatorId) != CREATOR_ID_LENGTH)) + { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_DEVICE_ERROR; + Object = NULL; + ChildObject = NULL; + + switch (Phase) { + case AmlStart: + Status = InternalAppendNewAmlObject (&Object, TableNameString, ListHead); + // TermList is too complicated and must be added outside + break; + + case AmlClose: + // TermList should be closed already + Status = InternalAmlLocateObjectByIdentifier (&Object, TableNameString, ListHead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: locate %a object\n", __FUNCTION__, TableNameString)); + goto Done; + } + + // Get rid of original Identifier data + InternalFreeAmlObjectData (Object); + + // Collect child data and delete children + Status = InternalAmlCollapseAndReleaseChildren ( + &ChildObject, + &ChildCount, + &Object->Link, + ListHead + ); + if (EFI_ERROR (Status) || + (ChildObject->Data == NULL) || + (ChildObject->DataSize == 0)) + { + DEBUG ((DEBUG_ERROR, "%a: ERROR: %a has no child data.\n", __FUNCTION__, TableNameString)); + goto Done; + } + + Object->DataSize = ChildObject->DataSize + sizeof (EFI_ACPI_DESCRIPTION_HEADER); + Object->Data = AllocateZeroPool (Object->DataSize); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocate Object->Data for %a\n", __FUNCTION__, TableNameString)); + goto Done; + } + + // Fill table header with data + // Signature + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Signature)], + TableNameString, + AsciiStrLen (TableNameString) + ); + + // Table Length + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Length)], + (UINT32 *)&Object->DataSize, + sizeof (UINT32) + ); + + // ACPI Table Version + Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Revision)] = ComplianceRev; + + // OEM ID + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, OemId)], + OemId, + AsciiStrLen (OemId) + ); + + // OEM Table ID + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, OemTableId)], + OemTableId, + AsciiStrLen (OemTableId) + ); + + // OEM Table Version + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, OemRevision)], + (UINT8 *)&OemRevision, + sizeof (UINT32) + ); + + // Creator ID + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, CreatorId)], + CreatorId, + AsciiStrLen (CreatorId) + ); + + // Creator Version + CopyMem ( + &Object->Data[OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, CreatorRevision)], + (UINT8 *)&CreatorRevision, + sizeof (UINT32) + ); + + // Copy rest of data into Object + CopyMem ( + &Object->Data[sizeof (EFI_ACPI_DESCRIPTION_HEADER)], + ChildObject->Data, + ChildObject->DataSize + ); + + // Checksum Set on Table Install + InternalFreeAmlObject (&ChildObject, ListHead); + Object->Completed = TRUE; + Status = EFI_SUCCESS; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + InternalFreeAmlObject (&ChildObject, ListHead); + } + + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlLib.h b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlLib.h new file mode 100644 index 0000000000000000000000000000000000000000..37cc81ec7c945f78c833f9e29cbe0f0e87892afb --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlLib.h @@ -0,0 +1,100 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef INTERNAL_AML_LIB_H_ +#define INTERNAL_AML_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include "LocalAmlObjects.h" + +// EDK2 open source MdePkg/Include/IndustryStandard/AcpiAml.h does not have +// these and should. +#define AML_DIGIT_CHAR_0 0x30 +#define AML_DIGIT_CHAR_9 0x39 + +// The max string size for a QWord is 8 bytes = 16 characters plus NULL Terminator +#define MAX_AML_DATA_INTEGER_SIZE 17 + +// Defines similar to ctype.h functions isalpha() and isdigit() +#define IS_ASCII_UPPER_ALPHA(c) ( ((c) >= AML_NAME_CHAR_A) && ((c) <= AML_NAME_CHAR_Z) ) +#define IS_ASCII_HEX_DIGIT(c) ( (((c) >= AML_DIGIT_CHAR_0) && ((c) <= AML_DIGIT_CHAR_9)) ||\ + (((c) >= AML_NAME_CHAR_A) && ((c) <= AML_NAME_CHAR_F)) ) + +// Swap bytes of upper and lower WORDs within a DWORD +#define Swap4Bytes(val) \ + ( (((val) >> 8) & 0x000000FF) | (((val) << 8) & 0x0000FF00) | \ + (((val) >> 8) & 0x00FF0000) | (((val) << 8) & 0xFF000000) ) + +/* + Calculates the optimized integer value used by AmlDataInteger and others + + Not a public function so no doxygen comment identifiers. + + @param[in] Integer - Integer value to encode + @param[out] ReturnData - Allocated DataBuffer with encoded integer + @param[out] ReturnDataSize - Size of ReturnData + + @return EFI_SUCCESS - Successful completion + @return EFI_OUT_OF_RESOURCES - Failed to allocate ReturnDataBuffer +*/ +EFI_STATUS +EFIAPI +InternalAmlDataIntegerBuffer ( + IN UINT64 Integer, + OUT VOID **ReturnData, + OUT UINTN *ReturnDataSize + ); + +/** + Creates a Package Length encoding and places it in the return buffer, + PkgLengthEncoding. Similar to AmlPkgLength but the PkgLength does not + include the length of its own encoding. + + @param[in] DataSize - The size of data to be encoded as a pkglength + @param[out] PkgLengthEncoding - Return buffer containing the AML encoding + @param[out] ReturnDataLength - Size of the return buffer + + @return EFI_SUCCESS - Success + @return all others - Fail + **/ +EFI_STATUS +EFIAPI +InternalAmlBitPkgLength ( + IN UINT32 DataSize, + OUT UINT8 **PkgLengthEncoding, + OUT UINTN *ReturnDataLength + ); + +/** + Creates a NameSeg AML object and inserts it into the List + + NameSeg := + + NameSegs shorter than 4 characters are filled with trailing underscores + + @param[in] Name - Field NameSeg + @param[in,out] ListHead - Linked list has NameSeg after call + + @retval EFI_SUCCESS + @retval Error status +**/ +EFI_STATUS +EFIAPI +InternalAmlNameSeg ( + IN CHAR8 *Name, + IN OUT LIST_ENTRY *ListHead + ); + +#endif // INTERNAL_AML_LIB_H_ diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c new file mode 100644 index 0000000000000000000000000000000000000000..b9d9bc5485ede69149ea347a5c7251b7e80f26b9 --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlObjects.c @@ -0,0 +1,357 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "LocalAmlLib.h" + +/** + Free Object->Data + + Frees Object->Data, Nulls pointer, zeros size and marks + Object->Completed = FALSE + + @param [in] Object - Pointer to Object to have Data freed + + @return EFI_SUCCESS - Object Freed + @return - Object free failed +**/ +EFI_STATUS +EFIAPI +InternalFreeAmlObjectData ( + IN AML_OBJECT_INSTANCE *Object + ) +{ + if (Object == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Object->Data != NULL) { + FreePool (Object->Data); + Object->Data = NULL; + Object->DataSize = 0; + Object->Completed = FALSE; + } + + return EFI_SUCCESS; +} + +/** + Free an Object + + Removes Object from it's linked list. + Frees Object->Data + Frees Object + + @param [in] Object - Pointer to Object to be freed + @param [in,out] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object Freed + @return - Object free failed +**/ +EFI_STATUS +EFIAPI +InternalFreeAmlObject ( + IN AML_OBJECT_INSTANCE **FreeObject, + IN OUT LIST_ENTRY *ListHead + ) +{ + AML_OBJECT_INSTANCE *Object; + + if ((FreeObject == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Object = *FreeObject; + if (Object != NULL) { + InternalFreeAmlObjectData (Object); + if (IsNodeInList (ListHead, &Object->Link)) { + RemoveEntryList (&Object->Link); + } + + FreePool (Object); + } + + *FreeObject = NULL; + return EFI_SUCCESS; +} + +/** + Creates a new AML_OBJECT_INSTANCE. Object->Data will be NULL and + Object->DataSize will be 0 + + Allocates AML_OBJECT_INSTANCE which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object + + @return EFI_SUCCESS - Object created and appended to linked list + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalNewAmlObjectNoData ( + OUT AML_OBJECT_INSTANCE **ReturnObject + ) +{ + AML_OBJECT_INSTANCE *Object; + + if (ReturnObject == NULL) { + return EFI_INVALID_PARAMETER; + } + + *ReturnObject = NULL; + + // Allocate AML Object + Object = AllocateZeroPool (sizeof (AML_OBJECT_INSTANCE)); + if (Object == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Allocate Object Failed\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + Object->DataSize = 0; + Object->Data = NULL; + Object->Signature = AML_OBJECT_INSTANCE_SIGNATURE; + + *ReturnObject = Object; + return EFI_SUCCESS; +} + +/** + Inserts a new AML_OBJECT_INSTANCE at the end of the linked list. Object->Data + will be NULL and Object->DataSize will be 0 + + Allocates AML_OBJECT_INSTANCE which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object + @param [in,out] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object created and appended to linked list + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAppendNewAmlObjectNoData ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if ((ListHead == NULL) || (ReturnObject == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = InternalNewAmlObjectNoData (&Object); + if (!EFI_ERROR (Status)) { + InsertTailList (ListHead, &Object->Link); + *ReturnObject = Object; + } + + return Status; +} + +/** + Inserts a new AML_OBJECT_INSTANCE at the end of the linked list. Using a + string Identifier for comparison purposes + + Allocates AML_OBJECT_INSTANCE which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object + @param [in] Identifier - String Identifier to create object with + @param [in,out] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object created and appended to linked list + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAppendNewAmlObject ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN CHAR8 *Identifier, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + AML_OBJECT_INSTANCE *Object; + + if ((Identifier == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Object = NULL; + + Status = InternalAppendNewAmlObjectNoData (&Object, ListHead); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + // Allocate Identifier Data + NULL termination + Object->DataSize = AsciiStrLen (Identifier) + 1; + Object->Data = AllocatePool (Object->DataSize); + if (Object->Data == NULL) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: Allocate Data Identifier=%a\n", __FUNCTION__, Identifier)); + InternalFreeAmlObject (&Object, ListHead); + return EFI_OUT_OF_RESOURCES; + } + + CopyMem (Object->Data, Identifier, Object->DataSize); + + *ReturnObject = Object; + return EFI_SUCCESS; +} + +/** + Finds AML_OBJECT_INSTANCE given a string Identifier looking backwards in the + AML_OBJECT_INSTANCE linked list + + @param [out] ReturnObject - Pointer to an Object + @param [in] Identifier - String Identifier to create object with + @param [in] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object located and returned + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAmlLocateObjectByIdentifier ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN CHAR8 *Identifier, + IN LIST_ENTRY *ListHead + ) +{ + LIST_ENTRY *Node; + AML_OBJECT_INSTANCE *Object; + UINTN IdentifierSize; + + if ((Identifier == NULL) || (ListHead == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Object = NULL; + *ReturnObject = NULL; + + IdentifierSize = AsciiStrLen (Identifier) + 1; + // Look Backwards and find Node for this Object + Node = ListHead; + do { + Node = GetPreviousNode (ListHead, Node); + Object = AML_OBJECT_INSTANCE_FROM_LINK (Node); + + if (Object->Completed) { + // Object to be found cannot be completed yet + continue; + } else { + if ((Object->DataSize != 0) && + (Object->DataSize == IdentifierSize) && + (CompareMem ( + Object->Data, + Identifier, + MAX (Object->DataSize, IdentifierSize) + ) == 0)) + { + *ReturnObject = Object; + return EFI_SUCCESS; + } else { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: First incomplete Object is not %a.\n", + __FUNCTION__, + Identifier + )); + // Object looking for should be the first uncompleted Object. + return EFI_NOT_FOUND; + } + } + } while (Node != ListHead); + + *ReturnObject = NULL; + return EFI_NOT_FOUND; +} + +/** + Finds all children of the Link and appends them into a single ObjectData + buffer of ObjectDataSize + + Allocates AML_OBJECT_INSTANCE and Data which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object pointer + @param [out] ChildCount - Count of Child Objects collapsed + @param [in] Link - Linked List Object entry to collect children + @param [in,out] ListHead - Head of Object Linked List + + @return EFI_SUCCESS - ChildObject created and returned + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAmlCollapseAndReleaseChildren ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + OUT UINTN *ChildCount, + IN LIST_ENTRY *Link, + IN OUT LIST_ENTRY *ListHead + ) +{ + EFI_STATUS Status; + LIST_ENTRY *Node; + AML_OBJECT_INSTANCE *Object; + AML_OBJECT_INSTANCE *ChildObject; + + Status = EFI_SUCCESS; + if ((ReturnObject == NULL) || + (ChildCount == NULL) || + (Link == NULL) || + (ListHead == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + *ChildCount = 0; + + Status = InternalNewAmlObjectNoData (&Object); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: allocating Object Data\n", __FUNCTION__)); + goto Done; + } + + // Get first Child Node + Node = GetNextNode (ListHead, Link); + while (Node != ListHead) { + ChildObject = AML_OBJECT_INSTANCE_FROM_LINK (Node); + // Expand data buffer to fit existing data + new data + Object->Data = ReallocatePool ( + Object->DataSize, + Object->DataSize + ChildObject->DataSize, + Object->Data + ); + if (Object->Data == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: ERROR: reallocating Object Data\n", __FUNCTION__)); + goto Done; + } + + // Copy new data at end of buffer + CopyMem ( + &Object->Data[Object->DataSize], + ChildObject->Data, + ChildObject->DataSize + ); + Object->DataSize += ChildObject->DataSize; + // Get Next ChildObject Node, then free ChildObject from list + Node = GetNextNode (ListHead, Node); + InternalFreeAmlObject (&ChildObject, ListHead); + *ChildCount = *ChildCount + 1; + } + +Done: + if (EFI_ERROR (Status)) { + InternalFreeAmlObject (&Object, ListHead); + Object = NULL; + } + + *ReturnObject = Object; + return Status; +} diff --git a/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h new file mode 100644 index 0000000000000000000000000000000000000000..453420307fee84cfa2a2f924bf687448071cb0ba --- /dev/null +++ b/Platform/AMD/AgesaPkg/Library/DxeAmlGenerationLib/LocalAmlObjects.h @@ -0,0 +1,150 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef INTERNAL_AML_OBJECTS_H_ +#define INTERNAL_AML_OBJECTS_H_ + +// #include "LocalAmlLib.h" + +/** + Free Object->Data + + Frees Object->Data, Nulls pointer, zeros size and marks + Object->Completed = FALSE + + @param [in] Object - Pointer to Object to have Data freed + + @return EFI_SUCCESS - Object Freed + @return - Object free failed +**/ +EFI_STATUS +EFIAPI +InternalFreeAmlObjectData ( + IN AML_OBJECT_INSTANCE *Object + ); + +/** + Free an Object + + Removes Object from it's linked list. + Frees Object->Data + Frees Object + + @param [in] Object - Pointer to Object to be freed + @param [in,out] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object Freed + @return - Object free failed +**/ +EFI_STATUS +EFIAPI +InternalFreeAmlObject ( + IN AML_OBJECT_INSTANCE **Object, + IN OUT LIST_ENTRY *ListHead + ); + +/** + Creates a new AML_OBJECT_INSTANCE. Object->Data will be NULL and + Object->DataSize will be 0 + + Allocates AML_OBJECT_INSTANCE which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object + + @return EFI_SUCCESS - Object created and appended to linked list + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalNewAmlObjectNoData ( + OUT AML_OBJECT_INSTANCE **ReturnObject + ); + +/** + Inserts a new AML_OBJECT_INSTANCE at the end of the linked list. Object->Data + will be NULL and Object->DataSize will be 0 + + Allocates AML_OBJECT_INSTANCE which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object + @param [in,out] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object created and appended to linked list + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAppendNewAmlObjectNoData ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN OUT LIST_ENTRY *ListHead + ); + +/** + Inserts a new AML_OBJECT_INSTANCE at the end of the linked list. Using a + string Identifier for comparison purposes + + Allocates AML_OBJECT_INSTANCE which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object + @param [in] Identifier - String Identifier to create object with + @param [in,out] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object created and appended to linked list + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAppendNewAmlObject ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN CHAR8 *Identifier, + IN OUT LIST_ENTRY *ListHead + ); + +/** + Finds AML_OBJECT_INSTANCE given a string Identifier looking backwards in the + AML_OBJECT_INSTANCE linked list + + @param [out] ReturnObject - Pointer to an Object + @param [in] Identifier - String Identifier to create object with + @param [in] ListHead - Head of AML Object linked list + + @return EFI_SUCCESS - Object located and returned + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAmlLocateObjectByIdentifier ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + IN CHAR8 *Identifier, + IN LIST_ENTRY *ListHead + ); + +/** + Finds all children of the Link and appends them into a single ObjectData + buffer of ObjectDataSize + + Allocates AML_OBJECT_INSTANCE and Data which must be freed by caller + + @param [out] ReturnObject - Pointer to an Object pointer + @param [out] ChildCount - Count of Child Objects collapsed + @param [in] Link - Linked List Object entry to collect children + @param [in,out] ListHead - Head of Object Linked List + + @return EFI_SUCCESS - ChildObject created and returned + @return - Object creation failed, Object = NULL +**/ +EFI_STATUS +EFIAPI +InternalAmlCollapseAndReleaseChildren ( + OUT AML_OBJECT_INSTANCE **ReturnObject, + OUT UINTN *ChildCount, + IN LIST_ENTRY *Link, + IN OUT LIST_ENTRY *ListHead + ); + +#endif // INTERNAL_AML_OBJECTS_H_ diff --git a/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.dxe.inc.fdf b/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.dxe.inc.fdf index 4766ad0447357c5e83d0763b16c95a976c528772..3f61cbbdc754a05a094be9f021a478e62d7e693f 100644 --- a/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.dxe.inc.fdf +++ b/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.dxe.inc.fdf @@ -1,7 +1,8 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## +## diff --git a/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.inc.dsc b/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.inc.dsc index 1f1e04c414b6517b91e5c599a2933b1984f8f2a1..5c05759883c6a4ee4247b696caeb6f2e02cd9a77 100644 --- a/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.inc.dsc +++ b/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.inc.dsc @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2012-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2012-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.pei.inc.fdf b/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.pei.inc.fdf index 4766ad0447357c5e83d0763b16c95a976c528772..3f61cbbdc754a05a094be9f021a478e62d7e693f 100644 --- a/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.pei.inc.fdf +++ b/Platform/AMD/AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.pei.inc.fdf @@ -1,7 +1,8 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## +## diff --git a/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf b/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf index da3afe6e59c1889f3bd2caed293199101c09b1d4..6a1494c2dbdea5f12c401f261dae471bd2c8bcd1 100644 --- a/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf +++ b/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf b/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf index da3afe6e59c1889f3bd2caed293199101c09b1d4..6a1494c2dbdea5f12c401f261dae471bd2c8bcd1 100644 --- a/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf +++ b/Platform/AMD/AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCbsPkg/Library/Family/0x1A/BRH/External/CbsBreithorn.dxe.inc.fdf b/Platform/AMD/AmdCbsPkg/Library/Family/0x1A/BRH/External/CbsBreithorn.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..3f61cbbdc754a05a094be9f021a478e62d7e693f --- /dev/null +++ b/Platform/AMD/AmdCbsPkg/Library/Family/0x1A/BRH/External/CbsBreithorn.dxe.inc.fdf @@ -0,0 +1,8 @@ +## @file +# +# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +## diff --git a/Platform/AMD/AmdCbsPkg/Library/Family/0x1A/BRH/External/CbsBreithorn.pei.inc.fdf b/Platform/AMD/AmdCbsPkg/Library/Family/0x1A/BRH/External/CbsBreithorn.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..3f61cbbdc754a05a094be9f021a478e62d7e693f --- /dev/null +++ b/Platform/AMD/AmdCbsPkg/Library/Family/0x1A/BRH/External/CbsBreithorn.pei.inc.fdf @@ -0,0 +1,8 @@ +## @file +# +# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +## diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/PspPlatformDriver/PspPlatform.inf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/PspPlatformDriver/PspPlatform.inf new file mode 100644 index 0000000000000000000000000000000000000000..87b4ec1aea7627b84f4054a8f97bde3f5293215a --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/PspPlatformDriver/PspPlatform.inf @@ -0,0 +1,33 @@ +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PspPlatform + FILE_GUID = 28374747-76FF-41B3-9740-381EFAEF13BC + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PspPlatformEntryPoint + +[Sources] + PspPlatformDriver.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModulePspPkg.dec + +[LibraryClasses] + DebugLib + BaseLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Depex] + TRUE diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/PspPlatformDriver/PspPlatformDriver.c b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/PspPlatformDriver/PspPlatformDriver.c new file mode 100644 index 0000000000000000000000000000000000000000..5ba586059b066a0a7bdc4ce66d45762a9de41fa2 --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/PspPlatformDriver/PspPlatformDriver.c @@ -0,0 +1,21 @@ +/** @file + + Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include + +#include + +EFI_STATUS +EFIAPI +PspPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/ServerHotplugDxe/ServerHotplugDxe.c b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/ServerHotplugDxe/ServerHotplugDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..d38258f0479ea14cf3abf5562d62801906682d2f --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/ServerHotplugDxe/ServerHotplugDxe.c @@ -0,0 +1,22 @@ +/** @file + + Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +HotplugDescEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..672e5168587b596ac6a61eeab89504f0c2dbc073 --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf @@ -0,0 +1,28 @@ +## @file +# +# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ServerHotplugDxe + FILE_GUID = FAFF8CA9-E515-44ed-B5F9-E2F6E5D902E3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HotplugDescEntry + +[Sources] + ServerHotplugDxe.c + +[Packages] + AgesaPkg/AgesaPkg.dec + MdePkg/MdePkg.dec + AmdCpmPkg/AmdCpmPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + +[Depex] + TRUE diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.dxe.inc.fdf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..3f61cbbdc754a05a094be9f021a478e62d7e693f --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.dxe.inc.fdf @@ -0,0 +1,8 @@ +## @file +# +# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +## diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.fdf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.fdf new file mode 100644 index 0000000000000000000000000000000000000000..980934c3ac3450c645784764a385510777dff4e5 --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.fdf @@ -0,0 +1,10 @@ +## @file +# +# Platform Package Flash Description File +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.inc.dsc b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..e6b5d185f18f68abc2ffd0134cf6279515d4cdc6 --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.inc.dsc @@ -0,0 +1,12 @@ +## @file +# +# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEFINE AGESA_PKG_PATH = AgesaModulePkg + DEFINE AGESA_PKG_DEC = AgesaCommonModulePkg + diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.pei.inc.fdf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..6a1494c2dbdea5f12c401f261dae471bd2c8bcd1 --- /dev/null +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Chalupa/Processor/Turin/AmdCpmTurinChalupaPkg.pei.inc.fdf @@ -0,0 +1,8 @@ +## @file +# +# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.c b/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.c index e379538e3ab61117e684bb837dbac38fcf9f79ae..3898790a2b6592ad085125a83cd0c6ad4c838a2f 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.c +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.c @@ -1,7 +1,6 @@ /** @file - OEM OOB PPR DXE Driver. - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf index 64fd2913ad80b54a726cc94dd5aa8e661f3a5332..4c0cee4bbe567c040e7f58f40baa27dc19359e0b 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf @@ -1,42 +1,39 @@ -## @file -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = OobPprDxe - FILE_GUID = F91DCAB4-3639-11EE-BE56-0242AC120002 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = OobPprEntry - -[Sources] - OobPprDxe.c - -[Packages] - AgesaPkg/AgesaPkg.dec - AgesaModulePkg/AgesaCommonModulePkg.dec - MdePkg/MdePkg.dec - AmdCpmPkg/AmdCpmPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - DebugLib - PcdLib - BaseMemoryLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - MemoryAllocationLib - TimerLib - -[Protocols] - gEfiPciIoProtocolGuid #CONSUMES - -[Depex] - TRUE - - - +## @file +# +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OobPprDxe + FILE_GUID = F91DCAB4-3639-11EE-BE56-0242AC120002 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = OobPprEntry + +[Sources] + OobPprDxe.c + +[Packages] + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + MdePkg/MdePkg.dec + AmdCpmPkg/AmdCpmPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + DebugLib + PcdLib + BaseMemoryLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + MemoryAllocationLib + TimerLib + +[Protocols] + gEfiPciIoProtocolGuid #CONSUMES + +[Depex] + TRUE \ No newline at end of file diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatform.inf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatform.inf index f4d7638c1a6bed2f5ae3ec6d96ae385d152e1bde..5c9857f921d6891032de4b71384de14602192cff 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatform.inf +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatform.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatformDriver.c b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatformDriver.c index 5242e6261a91cc359d8bb3e494f6c51ee7241a8f..6b532d7185ec3a58543752e57b77401f29908945 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatformDriver.c +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/PspPlatformDriver/PspPlatformDriver.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.c b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.c index 530bd9d4b699204acf43285a88672c83fbc8141a..d38258f0479ea14cf3abf5562d62801906682d2f 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.c +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf index 973ace863236fe481edfcac2181e9396620d89b2..c97f8dbc7c44155998141fdd9132bdb90945ade9 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2008-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.dxe.inc.fdf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.dxe.inc.fdf index 4766ad0447357c5e83d0763b16c95a976c528772..421a0cba662fc7be9bd99fe68b6b84edeb01b405 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.dxe.inc.fdf +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.dxe.inc.fdf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.fdf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.fdf index b790e4ead57d5d60b05fba25f571fb70ba45b351..1dfdb6800276b2ca88bf97f34501093a0a28bdc7 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.fdf +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.fdf @@ -2,7 +2,7 @@ # # Platform Package Flash Description File # -# Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.inc.dsc b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.inc.dsc index 2916fecb2625e80e0b3e16866f9fb3d0184558f2..1bc71dab3b584c7c33569aca1785af79184574a0 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.inc.dsc +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.inc.dsc @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.pei.inc.fdf b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.pei.inc.fdf index 4766ad0447357c5e83d0763b16c95a976c528772..421a0cba662fc7be9bd99fe68b6b84edeb01b405 100644 --- a/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.pei.inc.fdf +++ b/Platform/AMD/AmdCpmPkg/Addendum/Oem/Quartz/Processor/Genoa/AmdCpmGenoaQuartzPkg.pei.inc.fdf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2015-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2015-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/AmdCpmPkg.dec b/Platform/AMD/AmdCpmPkg/AmdCpmPkg.dec index c8c474637f8ac3e5d1a8b3553f9422e19726e792..0b7422c420fa7bcc1bcd68f074ac2dfdc1719607 100755 --- a/Platform/AMD/AmdCpmPkg/AmdCpmPkg.dec +++ b/Platform/AMD/AmdCpmPkg/AmdCpmPkg.dec @@ -1,7 +1,6 @@ ## @file -# AMD Common Platform Module (CPM) Module Package DEC. # -# Copyright (C) 2012-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2012-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Include/AmdCpmBase.h b/Platform/AMD/AmdCpmPkg/Include/AmdCpmBase.h index a7fef5a35c26d0f84cbc01b990437af21322f35e..059e32588847e4c0cf52a5848240914485cdbefa 100644 --- a/Platform/AMD/AmdCpmPkg/Include/AmdCpmBase.h +++ b/Platform/AMD/AmdCpmPkg/Include/AmdCpmBase.h @@ -1,7 +1,6 @@ /** @file - AMD CPM Base Definitions. - Copyright (C) 2014-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2014-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Include/AmdCpmCommon.h b/Platform/AMD/AmdCpmPkg/Include/AmdCpmCommon.h index af192fcf035c30b77ea1f0f541f4ca04efe22fa6..54e64cc8430f84a737dffb743e3a41f6510d3f82 100644 --- a/Platform/AMD/AmdCpmPkg/Include/AmdCpmCommon.h +++ b/Platform/AMD/AmdCpmPkg/Include/AmdCpmCommon.h @@ -1,7 +1,6 @@ /** @file - AMD CPM Common Definitions. - Copyright (C) 2012-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2012-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Include/AmdCpmDefine.h b/Platform/AMD/AmdCpmPkg/Include/AmdCpmDefine.h index 4fc3f97a80facc118e177c90f2f3ecd6d00802a4..b5b250702a16876cb8bd224ebb0ff81ba78155ce 100644 --- a/Platform/AMD/AmdCpmPkg/Include/AmdCpmDefine.h +++ b/Platform/AMD/AmdCpmPkg/Include/AmdCpmDefine.h @@ -1,7 +1,6 @@ /** @file - AMD CPM Common Definitions. - Copyright (C) 2012-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2012-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Include/AmdCpmFunction.h b/Platform/AMD/AmdCpmPkg/Include/AmdCpmFunction.h index 7dce2381356ac19015dea20f5ecd3350d5d4aad2..cede8ad198b50587a1cfb2d50e5f5734cdbeca98 100644 --- a/Platform/AMD/AmdCpmPkg/Include/AmdCpmFunction.h +++ b/Platform/AMD/AmdCpmPkg/Include/AmdCpmFunction.h @@ -1,7 +1,6 @@ /** @file - AMD CPM Common Functions. - Copyright (C) 2012-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2012-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.c b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.c index fbc372586b5d6793c54da12ce6a5735452de8da7..fe179889445c828728d529c6df4626e57070ef8a 100644 --- a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.c +++ b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.inf b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.inf index 2d9dbeb715f0eb82242c129bf1969e590bf34337..a38229af65e678757d3e00aaf09f3c22bdf2d75a 100644 --- a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.inf +++ b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.c b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.c index 0a5f4a7e817a60df9d718e844cbf7bc75d5fcd3b..f157218d2f77c88068fc654537591e3ce40cb092 100644 --- a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.c +++ b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.c @@ -1,13 +1,6 @@ /** @file - String token ID of help message text. - Shell supports to find help message in the resource section of an - application image if * .MAN file is not found. - This global variable is added to make build tool recognizes - that the help string is consumed by user and then build tool will - add the string into the resource section. - Thus the application can use '-?' option to show help message in Shell. - Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.inf b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.inf index 98c8755ab8d24ee7edde6c7879d72d1cd3ccff26..d56603a9378ae9448d5bbb0ba1a79a16e582d5e6 100644 --- a/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.inf +++ b/Platform/AMD/AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.c b/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.c index 47eb700f8fc25d0bf1b441225df3a70c122f9e1a..0ac33a2bc1404161b98b35440cb683f9bb88819e 100644 --- a/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.c +++ b/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.c @@ -1,6 +1,6 @@ /** @file - Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf b/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf index 9c3c0dd0a9b492f6efae7eae6628666581f627a0..f690274a35ee58215591367e65c9339765163b54 100644 --- a/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf +++ b/Platform/AMD/AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -30,4 +30,3 @@ PlatformHookLib - diff --git a/Platform/AMD/AmdCpmPkg/Library/Protocol/AmdCpmTableProtocol/AmdCpmTableProtocol.h b/Platform/AMD/AmdCpmPkg/Library/Protocol/AmdCpmTableProtocol/AmdCpmTableProtocol.h index 4a90aa3d8bcf53fcc8cbf1f82ff656d9a8c7bada..735a55668f289353db75f0cfd448d4dff869cce5 100644 --- a/Platform/AMD/AmdCpmPkg/Library/Protocol/AmdCpmTableProtocol/AmdCpmTableProtocol.h +++ b/Platform/AMD/AmdCpmPkg/Library/Protocol/AmdCpmTableProtocol/AmdCpmTableProtocol.h @@ -1,7 +1,6 @@ /** @file - AMD CPM Table Protocol. - Copyright (C) 2012-2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2012-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec index 58700988c845001bf02786e0dfc87c3b18a83a96..8e488f1aea1eb6e2cb38f81289a4c4c123a7ac12 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec @@ -4,7 +4,7 @@ # This package supports AMD processor family based board as per the MinPlatform # Arch specification. # -# Copyright (c) 2023 - 2024, Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2023 - 2025, Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # # @par Specification Reference: @@ -26,11 +26,9 @@ [Ppis] gAmdMemoryInfoHobPpiGuid = { 0xba16e587, 0x1d66, 0x41b7, { 0x9b, 0x52, 0xca, 0x4f, 0x2c, 0xad, 0x0d, 0xc8}} - gAmdTopOfTemporaryRamPpiGuid = { 0x1e1ad6ed, 0xa13d, 0x4fdc, { 0xa5, 0xb8, 0x58, 0x23, 0xef, 0x17, 0xd9, 0x08}} -[LibraryClasses] - ## @libraryclass Provide services to platform BDS hook. - BoardBdsHookLib|Include/Library/AmdBoardBdsHookLib.h +[Ppis] + gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b}} [Protocols] gAmdBoardBdsBootOptionPriorityProtocolGuid = { 0x5806db97, 0x5303, 0x409f, { 0x8f, 0x09, 0xab, 0x29, 0xd8, 0x07, 0xa3, 0xf1}} @@ -56,14 +54,21 @@ gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize |0x00000000|UINT32|0x10000008 gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset |0x00000000|UINT32|0x10000009 - # SMRAM size - # Holds the SMRAM area size, which is reserved for SMRAM operation - # default value 128MB - gAmdMinBoardPkgTokenSpaceGuid.PcdAmdSmramAreaSize |0x08000000|UINT64|0x20000100 - # PCDs of temp memory address gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamBase |0x00030000|UINT32|0x1000000A gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamSize |0x00020000|UINT32|0x1000000B # PCD of boot FV base address gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase |0x09B00000|UINT32|0x1000000C + + # + # PCIe Config Space + # + gAmdMinBoardPkgTokenSpaceGuid.PcdMmioCfgBusRange |0x00000008|UINT32|0x1000000D # 8 = 256MB, 7 = 128MB, and 6 = 64MB + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow |0xE0000000|UINT32|0x1000000E # Lower 32 bit address of PCIe config base. + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi |0x00000000|UINT32|0x1000000F # Upper 32 bit address of PCIe config base. + + # SMRAM size + # Holds the SMRAM area size, which is reserved for SMRAM operation + # default value 128MB + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdSmramAreaSize |0x08000000|UINT64|0x20000100 diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc index 1dbefbb7ec61a2cf50d97d48f80996e7e3abb91b..f9fb49ac8b6cc5dc17e02a988d95b583e33fa264 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc @@ -22,12 +22,10 @@ MinPlatformPkg/MinPlatformPkg.dec UefiCpuPkg/UefiCpuPkg.dec -[PcdsDynamicDefault] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000 - [LibraryClasses] - ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf + ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf + PlatformSecLib|AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf [LibraryClasses.common] BaseLib|MdePkg/Library/BaseLib/BaseLib.inf @@ -36,31 +34,45 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf - StackCheckLib|MdePkg/Library/StackCheckLibNull/StackCheckLibNull.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + BoardAcpiTableLib|MinPlatformPkg/Acpi/Library/BoardAcpiTableLibNull/BoardAcpiTableLibNull.inf -[LibraryClasses.common.SEC] - PlatformSecLib|AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf - [LibraryClasses.common.PEIM] - BoardInitLib|AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + BoardInitLib|AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf [LibraryClasses.common.DXE_DRIVER] - BoardBdsHookLib|AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf BoardInitLib|AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf [Components] AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf -[Components.IA32] - AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf - AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf +[Components.IA32, Components.X64] AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf + +[Components.IA32] AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf + AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf [Components.X64] - AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf - AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf + AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf + +# to make PcdSet64S working +[PcdsDynamicDefault] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000 + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + MSFT:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + + GCC:*_*_*_CC_FLAGS = -D USE_EDKII_HEADER_FILE + + # Turn off DEBUG messages for Release Builds + GCC:RELEASE_*_*_CC_FLAGS = -D MDEPKG_NDEBUG + INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + diff --git a/Platform/AMD/AmdMinBoardPkg/Include/Library/AmdBoardBdsHookLib.h b/Platform/AMD/AmdMinBoardPkg/Include/Library/AmdBoardBdsHookLib.h index 6bfa4747e061951106e3b466fac6366260311bfc..70683c2641aa32d82a1081ef190ac4e7277983bd 100644 --- a/Platform/AMD/AmdMinBoardPkg/Include/Library/AmdBoardBdsHookLib.h +++ b/Platform/AMD/AmdMinBoardPkg/Include/Library/AmdBoardBdsHookLib.h @@ -2,7 +2,7 @@ Header file for BDS Hook Library Copyright (c) 2020, Intel Corporation. All rights reserved.
- Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdMinBoardPkg/Include/Ppi/TopOfTemporaryRam.h b/Platform/AMD/AmdMinBoardPkg/Include/Ppi/TopOfTemporaryRam.h new file mode 100644 index 0000000000000000000000000000000000000000..5805bc184f62664481c71f978677c155a900259b --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Include/Ppi/TopOfTemporaryRam.h @@ -0,0 +1,15 @@ +/** @file + Provides the pointer to top of temporary ram. + + Copyright (c) 2014, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TOP_OF_TEMPORARY_RAM_H_ +#define TOP_OF_TEMPORARY_RAM_H_ + +extern EFI_GUID gTopOfTemporaryRamPpiGuid; + +#endif diff --git a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHook.h b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHook.h index 5c950c4866d64d51b85920c0627cb7f79467d135..bddf1426b2c70bed671078432f58f409c6d28ed5 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHook.h +++ b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHook.h @@ -2,7 +2,7 @@ Header file for BDS Hook Library Copyright (c) 2020, Intel Corporation. All rights reserved.
- Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent @@ -68,14 +68,29 @@ #define STD_ERROR 0x00000002 #define CONSOLE_IN 0x00000004 #define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) -#define END_ENTIRE_DEVICE_PATH \ - { \ - END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \ - } extern EFI_GUID gUefiShellFileGuid; extern EFI_BOOT_MODE gBootMode; +#define gPciRootBridge \ + { \ + { \ + ACPI_DEVICE_PATH, \ + ACPI_DP, \ + { \ + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ + }, \ + }, \ + EISA_PNP_ID (0x0A03), \ + 0 \ + } + +#define gEndEntire \ + { \ + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \ + } + typedef struct { EFI_DEVICE_PATH_PROTOCOL *DevicePath; UINTN ConnectType; diff --git a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.c b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.c index 3d7c0c2bf790f2cf37e2e34a786d5ce8d00d35a2..9739a40391582c2e6fcbf9388eb90bd46de20e90 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.c @@ -3,7 +3,7 @@ implementation instance of the BDS hook library Copyright (c) 2019, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -26,7 +26,6 @@ #include #endif -CHAR16 *mConsoleVar[] = { L"ConIn", L"ConOut" }; GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE gBootMode; BOOLEAN gPPRequireUIConfirm; extern UINTN mBootMenuOptionNumber; @@ -47,7 +46,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDev SUBCLASS_BOOT, // DeviceSubClass PROTOCOL_KEYBOARD // DeviceProtocol }, - END_ENTIRE_DEVICE_PATH + gEndEntire }; #ifdef INTERNAL_IDS @@ -638,6 +637,7 @@ ConnectTrustedConsole ( UINTN Index; EFI_HANDLE Handle; EFI_STATUS Status; + CHAR16 *ConsoleVar[] = { L"ConIn", L"ConOut" }; VOID *TrustedConsoleDevicepath; TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleInputDevicePath); @@ -645,8 +645,8 @@ ConnectTrustedConsole ( TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleOutputDevicePath); DumpDevicePath (L"TrustedConsoleOut", TrustedConsoleDevicepath); - for (Index = 0; Index < sizeof (mConsoleVar) / sizeof (mConsoleVar[0]); Index++) { - GetEfiGlobalVariable2 (mConsoleVar[Index], (VOID **)&Consoles, NULL); + for (Index = 0; Index < sizeof (ConsoleVar) / sizeof (ConsoleVar[0]); Index++) { + GetEfiGlobalVariable2 (ConsoleVar[Index], (VOID **)&Consoles, NULL); TempDevicePath = Consoles; do { diff --git a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf index 23e834e332bee5bb06d86f6b97a4b96856e41a17..6f573b41bf8490afc0d19d34bf7ffef90ea804c1 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf @@ -18,85 +18,83 @@ [LibraryClasses] BaseLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib BaseMemoryLib DebugLib + PcdLib + PrintLib DevicePathLib + UefiLib + HobLib DxeServicesLib DxeServicesTableLib HiiLib - HobLib - IpmiCommandLib - IpmiLib - MemoryAllocationLib - PcdLib + UefiBootManagerLib PerformanceLib - PrintLib - SortLib - Tcg2PhysicalPresenceLib TimerLib - UefiBootManagerLib - UefiBootServicesTableLib - UefiLib - UefiRuntimeServicesTableLib + Tcg2PhysicalPresenceLib + IpmiLib + IpmiCommandLib + SortLib [Packages] - AmdMinBoardPkg/AmdMinBoardPkg.dec - BoardModulePkg/BoardModulePkg.dec - IpmiFeaturePkg/IpmiFeaturePkg.dec - ManageabilityPkg/ManageabilityPkg.dec - MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - MinPlatformPkg/MinPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec SecurityPkg/SecurityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + BoardModulePkg/BoardModulePkg.dec + ManageabilityPkg/ManageabilityPkg.dec + AmdMinBoardPkg/AmdMinBoardPkg.dec [Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand ## PRODUCES - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn ## PRODUCES + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution ## CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution ## PRODUCES - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution ## PRODUCES - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## PRODUCES - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand ## PRODUCES gMinPlatformPkgTokenSpaceGuid.PcdPlatformMemoryCheckLevel ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdShellFile ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdTrustedStorageDevicePath ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdShellFile ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc ## CONSUMES [Sources] BoardBdsHook.h BoardBdsHookLib.c - BoardBootOption.c BoardMemoryTest.c + BoardBootOption.c [Protocols] - gAmdBoardBdsBootOptionPriorityProtocolGuid ## CONSUMES + gEfiPciRootBridgeIoProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES gEfiCpuIo2ProtocolGuid ## CONSUMES - gEfiDevicePathToTextProtocolGuid ## CONSUMES - gEfiDiskInfoProtocolGuid ## CONSUMES - gEfiDxeSmmReadyToLockProtocolGuid gEfiDxeSmmReadyToLockProtocolGuid ## PRODUCES + gEfiGenericMemTestProtocolGuid ## CONSUMES + gEfiDiskInfoProtocolGuid ## CONSUMES + gEfiDevicePathToTextProtocolGuid ## CONSUMES + gEfiSimpleTextInputExProtocolGuid ## CONSUMES gEfiFirmwareVolume2ProtocolGuid ## CONSUMES gEfiFormBrowser2ProtocolGuid ## CONSUMES gEfiGenericMemTestProtocolGuid ## CONSUMES - gEfiGenericMemTestProtocolGuid ## CONSUMES - gEfiPciIoProtocolGuid ## CONSUMES - gEfiPciRootBridgeIoProtocolGuid ## CONSUMES - gEfiSimpleTextInputExProtocolGuid ## CONSUMES - + gAmdBoardBdsBootOptionPriorityProtocolGuid ## CONSUMES + gEfiDxeSmmReadyToLockProtocolGuid [Guids] - gBdsEventAfterConsoleReadyBeforeBootOptionGuid - gBdsEventBeforeConsoleAfterTrustedConsoleGuid - gBdsEventBeforeConsoleBeforeEndOfDxeGuid - gEfiEndOfDxeEventGroupGuid ## CONSUMES gEfiGlobalVariableGuid ## PRODUCES gEfiMemoryOverwriteControlDataGuid ## PRODUCES + gEfiEndOfDxeEventGroupGuid ## CONSUMES + gBdsEventBeforeConsoleAfterTrustedConsoleGuid + gBdsEventBeforeConsoleBeforeEndOfDxeGuid + gBdsEventAfterConsoleReadyBeforeBootOptionGuid [Depex.common.DXE_DRIVER] gEfiVariableArchProtocolGuid diff --git a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBootOption.c index 16a47c2f8239bda6e43d81b86a1f7f2adfdfaf6d..837c2775ac28beea659034cb2f955e94b0373961 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBootOption.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBootOption.c @@ -2,7 +2,7 @@ Driver for Platform Boot Options support. Copyright (c) 2019, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardMemoryTest.c b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardMemoryTest.c index fff0ef299348e9b606314928b01bf988d79dc695..1969940c7be54d57c5919169921d9183c7580161 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardMemoryTest.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/BoardBdsHookLib/BoardMemoryTest.c @@ -1,7 +1,7 @@ /** @file Perform the platform memory test - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.c b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.c index 7f3bf1b9fca0f93c6bc053cd0974b889a3d8d72d..69f2f58c9d82a8536fe8078cb1cf84dc9409ba51 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.c @@ -1,7 +1,7 @@ /** @file BoardInitLib library implementation for DXE phase. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved + Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -187,6 +187,30 @@ BoardInitReadyToBoot ( VOID ) { + EFI_STATUS Status; + + Status = UpdateReinstallAcpiTable ( + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + (PATCH_ACPITABLE)FadtAcpiTablePatch + ); + DEBUG ((DEBUG_INFO, "Patching FADT ACPI Table ... Status = %r.\n", Status)); + + Status = UpdateReinstallAcpiTable ( + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + (PATCH_ACPITABLE)MadtAcpiTablePatch + ); + DEBUG ((DEBUG_INFO, "Patching MADT ACPI Table ... Status = %r.\n", Status)); + + UpdateReinstallAcpiTable ( + EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + (PATCH_ACPITABLE)AcpiTableAmlUpdate + ); + + UpdateReinstallAcpiTable ( + EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + (PATCH_ACPITABLE)AcpiTableAmlUpdate + ); + return EFI_SUCCESS; } diff --git a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf index 919777d0164e25ccfcfcf415ab5f1c786539520a..c526d09a9a2f4a62e559fa5fbaf2cf8fb3fb94b1 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf @@ -1,7 +1,7 @@ ## @file # Implements BoardInitLib Library Class in DXE phase. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent ## @@ -29,14 +29,13 @@ MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec MinPlatformPkg/MinPlatformPkg.dec - PcAtChipsetPkg/PcAtChipsetPkg.dec UefiCpuPkg/UefiCpuPkg.dec [Sources] DxeBoardInitLib.c DxeBoardInitLibInternal.c - DxeBoardInitLibInternal.h MadtAcpiTablePatch.c + DxeBoardInitLibInternal.h [Protocols] gEfiAcpiSdtProtocolGuid diff --git a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.c b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.c index 17bb46254585a3ad96276aeab43399ed97605234..a4c39125575b232b651d7fefd78c25d59b3f91a2 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.c @@ -1,14 +1,181 @@ /** @file BoardInitLib library internal implementation for DXE phase. -Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include "DxeBoardInitLibInternal.h" /** - Reserve Legacy VGA IO space. + A helper function to uninstall or update the ACPI table. + It searches for ACPI table for provided table signature, + if found then creates a copy of the table and calls the callbackfunction. + + @param[in] Signature ACPI table signature + @param[in] CallbackFunction The function to call to patch the searching ACPI table. + If NULL then uninstalls the table. + + @return EFI_SUCCESS Successfully Re-install the ACPI Table + @return EFI_NOT_FOUND Table not found + @return EFI_STATUS returns non-EFI_SUCCESS value in case of failure + +**/ +EFI_STATUS +EFIAPI +UpdateReinstallAcpiTable ( + IN UINT32 Signature, + IN PATCH_ACPITABLE CallbackFunction + ) +{ + EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol; + EFI_STATUS Status; + UINTN Index; + EFI_ACPI_SDT_HEADER *Table; + EFI_ACPI_TABLE_VERSION Version; + UINTN OriginalTableKey; + EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; + EFI_ACPI_SDT_HEADER *NewTable; + UINTN NewTableKey; + BOOLEAN Found; + + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTableProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error(%r): Unable to locate ACPI Table protocol.\n", Status)); + return Status; + } + + Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&AcpiSdtProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error(%r): Unable to locate ACPI SDT protocol.\n", Status)); + return Status; + } + + Found = FALSE; + Index = 0; + do { + Status = AcpiSdtProtocol->GetAcpiTable (Index, &Table, &Version, &OriginalTableKey); + if (EFI_ERROR (Status)) { + goto END_OF_SEARCH; + } + + // Look for given table + if (Table->Signature == Signature) { + if (CallbackFunction == NULL) { + Status = AcpiTableProtocol->UninstallAcpiTable (AcpiTableProtocol, OriginalTableKey); + return Status; + } + + NewTable = AllocateCopyPool (Table->Length, Table); + if (NULL == NewTable) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "Error(%r): Not enough resource to allocate table.\n", Status)); + return Status; + } + + Status = CallbackFunction (NewTable); + if (!EFI_ERROR (Status)) { + // Uninstall the old table + Status = AcpiTableProtocol->UninstallAcpiTable (AcpiTableProtocol, OriginalTableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error(%r): Uninstall old table error.\n", Status)); + FreePool (NewTable); + return Status; + } + + // Install the new table + Status = AcpiTableProtocol->InstallAcpiTable (AcpiTableProtocol, NewTable, NewTable->Length, &NewTableKey); + FreePool (NewTable); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error(%r): Failed to install new table.\n", Status)); + return Status; + } + + // If non SSDT table, then return status + if (Table->Signature != EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { + return Status; + } + + // Atleast one SSDT table update is success + Found = TRUE; + } + + // continue to search next SSDT table. + Status = EFI_SUCCESS; + } + + Index++; + } while (!EFI_ERROR (Status)); + +END_OF_SEARCH: + if (!Found) { + DEBUG ((DEBUG_ERROR, "Error(%r): Unable to locate ACPI Table.\n", Status)); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + A Callback function to patch the ACPI FADT table. + Updates FADT table with AMD specific values, which + are different than MinPlatformPkg. + + @param[in, out] NewTable Pointer to ACPI FADT table + + @return EFI_SUCCESS Always return EFI_SUCCESSe + +**/ +EFI_STATUS +EFIAPI +FadtAcpiTablePatch ( + IN OUT EFI_ACPI_SDT_HEADER *NewTable + ) +{ + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE *NewFadt; + + NewFadt = (EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE *)NewTable; + // Patch the Table + NewFadt->PLvl2Lat = 0x64; + NewFadt->Pm2CntLen = 0; + NewFadt->XGpe0Blk.RegisterBitWidth = 0x40; + NewFadt->FlushSize = 0x400; + NewFadt->FlushStride = 0x10; + NewFadt->XGpe1Blk.AccessSize = 0x01; + + return EFI_SUCCESS; +} + +/** + A Callback function to patch the ACPI DSDT/SSDT table. + Which has ASL code that needs to be updated. + + @param[in, out] NewTable Pointer to ACPI FADT table + + @return EFI_SUCCESS If table is modified. + EFI_NOT_FOUND If table is not modified. + +**/ +EFI_STATUS +EFIAPI +AcpiTableAmlUpdate ( + IN OUT EFI_ACPI_SDT_HEADER *NewTable + ) +{ + UINT64 OemTableId; + + if ((AsciiStrnCmp (NewTable->OemTableId, "AmdTable", 8) == 0)) { + DEBUG ((DEBUG_INFO, "Found (D/S)SDT table for patching OemTableId.\n")); + OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId); + CopyMem (NewTable->OemTableId, &OemTableId, 8); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** + Reserve Legay VGA IO space. @retval EFI_SUCCESS MMIO at Legacy VGA region has been allocated. @retval !EFI_SUCCESS Error allocating the legacy VGA region. diff --git a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.h b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.h index f61619677a6930c878ad5b46fe7e9e5359851b09..fa6aca513f867348e5788b2add661b9f9f86f3e7 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.h +++ b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLibInternal.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -20,7 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include +#include #include #include @@ -86,7 +86,64 @@ EFI_STATUS ); /** - Reserve Legacy VGA IO space. + A helper function to update and re-install ACPI table. + It searh for ACPI table for provided table signature, + if found then creates a copy of the table and calls the callbackfunction. + + @param[in] Signature ACPI table signature + @param[in] CallbackFunction The function to call to patch the searching ACPI table. + + @return EFI_SUCCESS Successfully Re-install the ACPI Table + @return EFI_NOT_FOUND Table not found + @return EFI_STATUS returns non-EFI_SUCCESS value in case of failure + +**/ +EFI_STATUS +EFIAPI +UpdateReinstallAcpiTable ( + IN UINT32 Signature, + IN PATCH_ACPITABLE CallbackFunction + ); + +/** + A Callback function to patch the ACPI FADT table. + Updates FADT table with AMD specific values, which + are different than MinPlatformPkg. + + @param[in, out] NewTable Pointer to ACPI FADT table + + @return EFI_SUCCESS Always return EFI_SUCCESSe + +**/ +EFI_STATUS +EFIAPI +FadtAcpiTablePatch ( + IN OUT EFI_ACPI_SDT_HEADER *NewTable + ); + +EFI_STATUS +EFIAPI +MadtAcpiTablePatch ( + IN OUT EFI_ACPI_SDT_HEADER *NewTable + ); + +/** + A Callback function to patch the ACPI DSDT/SSDT table. + Which has ASL code that needs to be updated. + + @param[in, out] NewTable Pointer to ACPI FADT table + + @return EFI_SUCCESS Always return EFI_SUCCESSe + +**/ +EFI_STATUS +EFIAPI +AcpiTableAmlUpdate ( + IN OUT EFI_ACPI_SDT_HEADER *NewTable + ); + +/** + Reserve Legay VGA IO space. @retval EFI_SUCCESS MMIO at Legacy VGA region has been allocated. @retval !EFI_SUCCESS Error allocating the legacy VGA region. diff --git a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/MadtAcpiTablePatch.c b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/MadtAcpiTablePatch.c index 555aab39889371b6b81c3573a634855e061d29be..dc4aaa79306a348b4f3de3af765bcc409ac80c7e 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/MadtAcpiTablePatch.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/DxeBoardInitLib/MadtAcpiTablePatch.c @@ -1,7 +1,7 @@ /** @file This file patches the ACPI MADT table for AMD specific values. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved + Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -94,6 +94,23 @@ SortByCcd ( return 0; } +/** + Function that determines whether SMT is enabled or disabled + based on CPU register values + + @retval TRUE SMT Enabled + @retval FALSE SMT Disabled + +**/ +BOOLEAN +IsSmtEnabled (VOID) { + UINT32 RegEbx = 0; + + // Get SMT enable/disable info from CPUIDx8000001E_EBX[15:8]: 0 SMT off, 1 SMT on + AsmCpuid (0x8000001E, NULL, &RegEbx, NULL, NULL); + return ((BOOLEAN) (((RegEbx >> 8) & 0xFF) != 0)); +} + /** A Callback function to patch the ACPI MADT table. Updates MADT table with AMD specific values, which @@ -232,10 +249,11 @@ MadtAcpiTablePatch ( } else { Src++; } + + CopyMem (LocalX2ApicPtr, SortedItem, sizeof (EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE) * LapicCount); + FreePool (SortedItem); } - CopyMem (LocalX2ApicPtr, SortedItem, sizeof (EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE) * LapicCount); - FreePool (SortedItem); } } diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/AmdMemoryInfoHob.h b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/AmdMemoryInfoHob.h index b596b3bdf3feb4137b115b2d187d70950d907c4e..3aa1fe7d08b39b23c9f79636428280a0fdb7c7ff 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/AmdMemoryInfoHob.h +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/AmdMemoryInfoHob.h @@ -1,7 +1,7 @@ /** @file Defines AMD memory info hob. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.c b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.c index af96969471ed42956a59534af8dcd2802b8c451e..f2f95b00da61c3a5f4fde39269b56e351ee7ccb7 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.c @@ -1,7 +1,7 @@ /** @file BoardInitLib library implementation for pre-mem PEI phase. -Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf index 9f3cfd47c4fef480636955bafc00a5b1985b5377..737cdd55be1b7684dfc78f8bed2ff97a90afcb48 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf @@ -1,7 +1,7 @@ ## @file # Board Init Library for AMD Platforms. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +# Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.c b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.c index 74da0f3c8705accf7535487ae39d2bbbcf8fa34d..bdd135ac638691aa22995040e369bb2f06983c82 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.c @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -112,7 +112,7 @@ EndofAmdMemoryInfoHobPpiGuidCallBack ( break; } - if (AmdMemoryInfoRange->Size > 0) { + if (AmdMemoryInfoRange->Size) { BuildResourceDescriptorHob ( EFI_RESOURCE_SYSTEM_MEMORY, SYSTEM_MEMORY_ATTRIBUTES, diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.h b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.h index 726db2554314f75e218eeccf392be5ba0a066839..375c6adb13598e3ca3e75b90a1421802f19bc445 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.h +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryInit.h @@ -1,7 +1,7 @@ /** @file This file contains definitions required for memory initialization in PEI phase. - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c index b19f33663d3012cc799a2bd0a5fb8c6d1f14bc9b..3abd7582bbb691ac171e7f8bfd60b2cb81e2c182 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c @@ -1,13 +1,17 @@ +/** + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved +**/ + /** @file Source code file for Report Firmware Volume (FV) library for AMD platforms. @par Note: This source has the reference of MinPlatformPkgs's PeriReportFvLib.c module. +**/ +/** Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved SPDX-License-Identifier: BSD-2-Clause-Patent - **/ #include diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf index 23ee503c42bed0e6dbe2810bd6e991a8ea92a63a..7c6875386f46bc08669598c3b73407edbd8e66a3 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf @@ -1,8 +1,11 @@ +### +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +### + ### @file # Component information file for the Report Firmware Volume (FV) library. # # Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.
-# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/AmdWrapperPlatformSecLib.c b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/AmdWrapperPlatformSecLib.c index 32455fb0c51516d96d91d5d400cdc46b3f082fea..b18c945e86c98fe15944497c94a49b38d094b7f8 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/AmdWrapperPlatformSecLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/AmdWrapperPlatformSecLib.c @@ -2,7 +2,7 @@ Sample to provide FSP wrapper platform sec related function. Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -44,7 +44,7 @@ PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = { EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = { { EFI_PEI_PPI_DESCRIPTOR_PPI, - &gAmdTopOfTemporaryRamPpiGuid, + &gTopOfTemporaryRamPpiGuid, NULL // To be patched later. }, { diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/AmdUefiStackNasm.inc b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/AmdUefiStackNasm.inc deleted file mode 100644 index 71e653f3ceeb2585ab730a386eab1b26a562bbe9..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/AmdUefiStackNasm.inc +++ /dev/null @@ -1,549 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Copyright (C) 2008 - 2024 Advanced Micro Devices, Inc. All rights reserved. -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -; Workfile: AmdUefiStackNasm.inc -; $Revision$ $Date$ -; -; Description: Code to setup temporary memory access for stack usage. This code -; is to be used on memory present systems that do not need CAR -; - -;============================================================================ -; -; Define a macro that allow the OEM to specify supported solutions in the -; cache-as-ram code. This will reduce the size of the assembled file. -; The macro will convert solutions into supported families. -; -;============================================================================ - -%include "CpStackNasm.inc" - -;====================================================================== -; Reference: UEFI PI v1.2 definition: -; -; typedef struct _UEFI_SEC_PEI_HAND_OFF { -; UINT16 DataSize; -; VOID *BootFirmwareVolumeBase; -; UINTN BootFirmwareVolumeSize; -; VOID *TemporaryRamBase; -; UINTN TemporaryRamSize; -; VOID *PeiTemporaryRamBase; -; UINTN PeiTemporaryRamSize; -; VOID *StackBase; -; UINTN StackSize; -; } UEFI_SEC_PEI_HAND_OFF; -; -struc UEFI_SEC_PEI_HAND_OFF - .DATA_SIZE resw 1 - .ALIGNMENT_PAD resw 1 - .BOOT_FIRMWARE_VOLUME_BASE resd 1 - .BOOT_FIRMWARE_VOLUME_SIZE resd 1 - .TEMPORARY_RAM_BASE resd 1 - .TEMPORARY_RAM_SIZE resd 1 - .PEI_TEMPORARY_RAM_BASE resd 1 - .PEI_TEMPORARY_RAM_SIZE resd 1 - .STACK_BASE resd 1 - .STACK_SIZE resd 1 -endstruc - -; Assure build option is defined, default is BIST only storage -%ifndef AMD_STACK_FRAME_PAD -%define AMD_STACK_FRAME_PAD 0 -%endif - - -;====================================================================== -;====================================================================== -; AMD_ENABLE_UEFI_STACK2: Setup a stack, heap & UEFI stack frame -; -; Input condition requirements: -; 32bit protected 'flat addressing' mode -; SS, DS, ES = segment descriptor defining 0x00000000 as the base. -; -; Build time options: -; AMD_STACK_FRAME_PAD EQU 00h -; used to create a Host Env stack frame for pseudo -; global variables - a build time option. Incremented -; by 4 to cover the BIST storage. -; -; Input Parameter: -; StackLocation -; STACK_AT_TOP -; Indicate stack is on the top of cache as RAM. -; STACK_AT_BOTTOM (default) -; Indicate stack is at the bottom of cache as RAM. -; BspStackSize = Stack size for BSP -; BspStackAddr = Stack base address for BSP -; -; In: -; EAX = BIST value collected after reset by host env -; EBX = Return address (preserved) -; ECX = size, in bytes, of the region to cache for execution. -; EDX = base address of region to cache, or zero for (4GB - size). -; -; Out: -; SS:ESP - Our new private stack location -; -; EAX = AGESA_STATUS -; EDX = Return status code if EAX contains a return code of higher -; severity than AGESA_SUCCESS -; ECX = Stack size in bytes -; EDI = pointer to stack frame location. Points to the -; beginning of the UEFI structure defined by the -; PI v1.2 spec. The Host Env stack frame follows -; this structure. -; [EDI]UEFI_SEC_PEI_HAND_OFF.BOOT_FIRMWARE_VOLUME_BASE = OEM_BFV_BASE -; [EDI]UEFI_SEC_PEI_HAND_OFF.BOOT_FIRMWARE_VOLUME_SIZE = OEM_BFV_SIZE -; [EDI+sizeof(UEFI_SEC_PEI_HAND_OFF)].OEM_DATA_DWORD[0] = BIST -; -; Preserved: -; EBX, EBP, DS, ES, SS -; -; Destroyed: -; EAX, ECX, EDX, EDI, ESI, ESP -; MMX0, MMX1, MMX2, MMX3, MMX4, MMX5 ... MMX[0..7] are used as save/restore storage -; -; Known Limitations: -; *!* This routine presently is limited to a max of 64 processor cores -; -; Description: -; This procedure will do the following: -; - allocate pre-defined address space for use as a stack for C code -; - allocate pre-defined address space for use as a UEFI heap -; - enable execution cache for a specified region -; - create an instance of the UEFI structure UEFI_SEC_PEI_HAND_OFF on the -; stack and populate it with values. -; -; Stack Allocation: -; Note: At present, the stack allocation is the same as described above in AMD_ENABLE_STACK_PRIVATE. -; In fact, this macro uses that macro to perform the allocation. -; The same 64 core limit applies to this implementation. -; Future versions of this macro will expand support to 80+ cores. -; Stack allocation will be 64k for the BSP, 16K for all APs. -; ESP is set to point below the HostEnv stack frame. -; -; Heap Allocation: -; Note: At present, only the BSP will be allocated space for a UEFI heap. -; Future versions of this macro will allcate 48K for each AP and the -; allocation for the BSP will vary for the size of the L2 present and -; the number of cores sharing the L2; maximizing the BSP allocation. -; -; Execution cache: -; The code will use Variable MTRRs 6 and 7 to define an area of memory -; enabled for execution cache. This is presumed to include the PEI core -; code area. The allocation is presummed to be at top-of-4G address range -; so the smaller block, if one exists, will be allocated at the base -; parameter (edx) and the larger block just after (edx+sizeof(smaller block)) -; -; HostEnv UEFI stack frame: -; The code will create a stack data frame containing: -; * a Host Env specific area for pseudo global variables. -; o This area is at 'bottom (defalult)' so as to be retained if the PEI core decides -; to reset the stack. -; o The first entry in this area is the BIST value. -; * an SEC-PEI hand-off structure (PI v1.2) -; o populated with the stack and Temporary RAM entries. -; o A processor's stack and heap are contiguous, with stack on 'top'. -; -;====================================================================== -%macro AMD_ENABLE_UEFI_STACK2 2-3 - - movd mm1, ebp ; Save user requested register - movd mm0, ebx ; Logically 'push' the input parameters ( return address ) - movd mm2, eax ; ( BIST ) - movd mm3, ecx ; ( cache zone size ) - movd mm4, edx ; ( cache zone base ) - - ; Short term method - need to accommodate existance of UEFI heap AND the AGESA heap. - ; So, use the old stack allocation process for stack, then mimick current UEFI (~v0.9) - ; operation to fill in the data stack frame. - %if (%0 = 3) - AMD_ENABLE_STACK_PRIVATE %1, %2, %3 - %else - AMD_ENABLE_STACK_PRIVATE STACK_AT_BOTTOM, %1, %2 - %endif - cmp eax, AGESA_SUCCESS ; Abort if not first entry; future versions will not allow multi-entry - jne %%AmdEnableUefiStackAbort - - ; review: - ; EAX = AGESA_STATUS - ; EDX = Return status code if EAX contains a return code of higher - ; severity than AGESA_SUCCESS - ; ECX = Stack size in bytes - ; ebx - return address parameter - ; ebp - user preserved register - ; ss:esp - stack pointer - ; - ; esi - address of start of stack block - ; [esp] - stack base address - ; [esp+4] - size of stack - ; [esp+8] - Marker for top-of-stack - ; mm0 - user return address - ; mm1 - user saved EBP register content - ; mm2 - BIST value - ; mm3 - cache zone size - ; mm5 - 32b pointer to family info struc. Set by GET_NODE_ID_CORE_ID_Fxx macros - - ; calculate stack frame pointer - - mov ebp, [esp] - mov edx, ebp ; save stack base to edx - - ; for BSC, we divide the memory allocation zone in half and allocate 1/2 to each of stack & UEFI heap - ; for APs, we allocate whole allocation to stack - IS_BSC - _if carry - %if (%0 = 3) - %if (%1 = STACK_AT_BOTTOM) - shr ecx, 1 - add ebp, ecx - shl ecx, 1 - %else - add ebp, ecx - %endif - %else - shr ecx, 1 - add ebp, ecx - shl ecx, 1 - %endif - _else - add ebp, ecx - _endif - sub ebp, (4 + AMD_STACK_FRAME_PAD) ; space for BIST and additional OEM data - movd eax, mm2 ; retrieve BIST data OEM acquired after reset - mov [ebp], eax ; place BIST data into first OEM data DWORD - sub ebp, UEFI_SEC_PEI_HAND_OFF_size ; space for UEFI structure storage - mov eax, edx ; retrieve memory base address for passing on - mov esp, ebp ; now can update the esp - ; fill the UEFI stack frame - mov [ebp + UEFI_SEC_PEI_HAND_OFF.TEMPORARY_RAM_BASE], eax - mov [ebp + UEFI_SEC_PEI_HAND_OFF.TEMPORARY_RAM_SIZE], ecx - mov word [ebp + UEFI_SEC_PEI_HAND_OFF.DATA_SIZE], UEFI_SEC_PEI_HAND_OFF_size - - ; for BSC, we divide the memory zone in half and allocate 1/2 to each of stack & UEFI heap - IS_BSC - _if carry - push ecx - shr ecx, 1 ; divide the memory zone in half and allocate 1/2 to each of stack & UEFI heap - mov [ebp + UEFI_SEC_PEI_HAND_OFF.PEI_TEMPORARY_RAM_SIZE], ecx - mov [ebp + UEFI_SEC_PEI_HAND_OFF.STACK_SIZE], ecx - - %if (%0 = 3) - %if (%1 = STACK_AT_BOTTOM) - mov [ebp + UEFI_SEC_PEI_HAND_OFF.STACK_BASE], eax - add eax, ecx ; put PEI temporary RAM base in upper half - mov [ebp + UEFI_SEC_PEI_HAND_OFF.PEI_TEMPORARY_RAM_BASE], eax - %else - mov [ebp + UEFI_SEC_PEI_HAND_OFF.PEI_TEMPORARY_RAM_BASE], eax - add eax, ecx ; put stack base in upper half - mov [ebp + UEFI_SEC_PEI_HAND_OFF.STACK_BASE], eax - %endif - %else - mov [ebp + UEFI_SEC_PEI_HAND_OFF.STACK_BASE], eax - add eax, ecx ; put PEI temporary RAM base in upper half - mov [ebp + UEFI_SEC_PEI_HAND_OFF.PEI_TEMPORARY_RAM_BASE], eax - %endif - pop ecx - _else - ; for APs, we allocate whole memory to stack - mov dword [ebp + UEFI_SEC_PEI_HAND_OFF.PEI_TEMPORARY_RAM_BASE], 0 - mov dword [ebp + UEFI_SEC_PEI_HAND_OFF.PEI_TEMPORARY_RAM_SIZE], 0 - mov [ebp + UEFI_SEC_PEI_HAND_OFF.STACK_SIZE], ecx - mov [ebp + UEFI_SEC_PEI_HAND_OFF.STACK_BASE], eax - _endif - - ; we will use the cache zone as implied BFV, - ; The OEM is free to override this from their code that follows - movd eax, mm3 ; cache zone size - mov [ebp + UEFI_SEC_PEI_HAND_OFF.BOOT_FIRMWARE_VOLUME_SIZE], eax - - ; calculate the base from size - movd ebx, mm4 - _if ebx, e, 0 - sub ebx, eax - movd mm4, ebx - _endif - mov [ebp + UEFI_SEC_PEI_HAND_OFF.BOOT_FIRMWARE_VOLUME_BASE], ebx - - ; Round up the size if there are more than 2 bits set in the given cache zone size - push edx - push ecx - push eax - - bsr ecx, eax - _if nzero - btr eax, ecx ; there is one bit set in the given cache zone size - bsr ecx, eax - _if nzero - push ecx - btr eax, ecx ; there are two bits set in the given cache zone size - bsr ecx, eax - _if nzero - pop ecx ; ecx is the index of second bit set from most-significant - pop eax ; eax is the given cache zone size - - xor edx, edx - bts edx, ecx - add eax, edx ; round up the size - dec edx - bts edx, ecx ; former 2nd bit spot should now be =0, clear it also - not edx - and eax, edx ; now, eax has two bits set at most, could have only one - - push eax - _else - pop ecx ; balance the stack - _endif - _endif - _endif - - pop eax - pop ecx - pop edx - movd mm3, eax ; update cache zone size - - ; Check for and apply any family size limits. - movd edi, mm5 - mov bx, [edi + CPU_FAMILY_INFO.L2_ALLOC_EXE] - - _if bx, a, 0 ; if there is a family limit - ; CPUID will destroyed EAX, EBX, ECX, EDX - ; but we only want to preserve EAX, ECX, EDX - push eax - push ecx - push edx - - ; get L2 allocate execution cache = CPU_FAMILY_INFO.L2_ALLOC_EXE + (L2 cache size - CPU_FAMILY_INFO.L2_MIN_SIZE) - AMD_CPUID AMD_CPUID_L2Cache - shr ecx, 16 ; CX = L2 cache size - sub cx, [edi + CPU_FAMILY_INFO.L2_MIN_SIZE] ; CX = additional L2 size to the family limit - mov bx, [edi + CPU_FAMILY_INFO.L2_ALLOC_EXE] ; use the additional L2 for exe cache - add bx, cx - - ; restore EAX, ECX, EDX - pop edx - pop ecx - pop eax - - movzx ebx, bx ; convert the limit from K to Bytes - shl ebx, 10 - _if eax, a, ebx ; enforce the family limit - ; note: SEC-PEI data is NOT updated on purpose, to allow the PEI - ; to see the full intended zone as the BFV - - - mov eax, ebx ; set size to family limit - movd mm3, eax ; update cache zone size - _endif - _endif - - ; base = 4G - size -; push edx -; xor edx, edx -; sub edx, eax -; movd mm4, edx -; pop edx - ; review: - ; eax - Cache zone size - ; ebx - - ; ecx - Stack size in bytes - ; edx - Return status code if EAX contains a return code of higher - ; severity than AGESA_SUCCESS - ; ebp - Stack Frame pointer - ; - ; esi - address of start of stack block - ; mm0 - user return address - ; mm1 - user saved EBP register content - ; mm3 - cache zone size - ; mm4 - cache zone base - ; mm5 - 32b pointer to family info struc. Set by GET_NODE_ID_CORE_ID_Fxx macros - - ; Cross check the cache zone for proper base/length values, - push edx - push ecx - - and eax, 0FFFF8000h ; size must be >= 32K - - ; Size a Power of Two? We can pull the two largest blocks from the size - ; then set first avaible vMTRR to cover those blocks of the zone. The zone is presumed - ; to be at the top of 4G memory space, so the blocks are allocated in a - ; 'top down' manner, smaller first at base address then the larger. - bsr ecx, eax - _if nzero ; Is parameter non-zero? - push ecx ; save size of larger block - btr eax, ecx ; reduce zone size by 1st 2**N - push eax - - ; skip vMTRR setting if it's not a primary thread - pushad - AMD_CPUID CPUID_MODEL - shr ebx, LOCAL_APIC_ID - and ebx, 0FFh ; ebx - initial local APIC physical ID - push ebx - - AMD_CPUID AMD_CPUID_EXT_APIC - - pop eax ; eax - initial local APIC physical ID - shr ebx, 8 - and ebx, 0FFh - inc bl ; bl - ThreadsPerCore - div bl - cmp ah, 0 - popad - jnz %%AmdSkipvMtrrSetting - - ; calculate upper mask value - needs to match the CPU address bus size - movzx ax, [edi + CPU_FAMILY_INFO.SIZE_ADDRESS_BUS] - movzx eax, ax - xor edx, edx - - ; find out the first vMTRR which is available - push eax - push ecx - push edx - mov ecx, AMD_MTRR_VARIABLE_MASK0 - _while ecx, be, AMD_MTRR_VARIABLE_MASK7 - rdmsr - _if eax, e, 0 - mov edi, ecx - dec edi ; now edi points to AMD_MTRR_VARIABLE_BASEx - jmp %%AmdvMtrrFound - _endif - add ecx, 2 - _endw -%%AmdvMtrrFound: - pop edx - pop ecx - pop eax - _if edi, a, AMD_MTRR_VARIABLE_BASE7 - jmp %%AmdSkipvMtrrSetting ; There's no enough vMTRR register pairs for ROM cache - _endif - - - _if al, be, 64 - bts edx, eax - _endif - dec edx ; edx = upper mask (e.g. 0x000FFFFF) - pop eax ; retrieve zone size (minus large block) - bsr ecx, eax - _if nzero - push edx ; save upper mask, make room to calc new base - ; set vMTRR[x] for Smaller block, if it exists - xor ebx, ebx - dec ebx ; ebx = all ones - btr ebx, ecx - inc ebx ; ebx = MTRR mask ( e.g 0xFFF80000) - movd eax, mm4 ; cache zone base - and eax, ebx ; use mask to align base - xor edx, edx - bts edx, ecx ; edx = block size - add edx, eax ; add block size to base - for next block's base - movd mm4, edx ; update stored base value - mov al, MTRR_TYPE_WP - mov ecx, edi ; use vMTRR pair # which is found above - add edi, 2 ; point to the next vMTRR - xor edx, edx ; clear upper base - wrmsr ; set the vMTRR[6] Base - mov eax, ebx ; now build the mask - pop edx ; retrieve upper mask value - bts eax, VMTRR_VALID - inc ecx - wrmsr ; set the vMTRR[6] Mask + Valid - _endif ; Any remaining size is abandoned. We can only use 2 vMTRRs - pop ecx ; retrieve size of larger block - push edx ; save upper mask value - ; set vMTRR[x + 1] for Larger block, if it exists - _if edi, a, AMD_MTRR_VARIABLE_BASE7 - jmp %%AmdSkipvMtrrSetting ; There's no enough vMTRR register pairs for ROM cache - _endif - - xor ebx, ebx - dec ebx ; ebx=all ones - btr ebx, ecx - inc ebx ; ebx = MTRR mask ( e.g 0xFFF00000) - movd eax, mm4 ; cache zone base - and eax, ebx ; use mask to align base - xor edx, edx ; clear upper base - mov al, MTRR_TYPE_WP - mov ecx, edi - wrmsr ; set the vMTRR[7] Base - mov eax, ebx ; now build the mask - bts eax, VMTRR_VALID - pop edx ; retrieve upper mask value - inc ecx - wrmsr ; set the vMTRR[7] Mask + Valid - _endif - - ; prepare to exit -%%AmdSkipvMtrrSetting: - mov edi, ebp ; place stack frame pointer for return - movd ebp, mm1 ; Restore saved user requested register - movd ebx, mm0 ; and the return address - - pop ecx - pop edx - mov eax, AGESA_SUCCESS -%%AmdEnableUefiStackAbort: -%endmacro - - -;====================================================================== -; AMD_DISABLE_UEFI_STACK2: Dismantle the pre-memory cache-as-RAM mode. -; -; In: -; EBX = Return address (preserved) -; -; Out: -; EAX = AGESA_SUCCESS -; -; Description: -; It is expected that the UEFI PEI core has relocated the stack to main -; RAM by this time and the MTRR map has been sync'd. Therefore, this -; routine will not modify the MTRR settings; but rather, just disable -; the CAR mode. Cache tags will be invalidated. -; -; Preserved: -; ebx, esp -; Destroyed: -; eax, ebx, ecx, edx, esi, ebp -;====================================================================== -%macro AMD_DISABLE_UEFI_STACK2 0 - - mov ebp, ebx ; Save return address - - ; get node/core/flags of current executing core - GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node); flags - - AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations - - mov ebx, ebp ; restore return address (ebx) - xor eax, AGESA_SUCCESS - -%endmacro - -;====================================================================== -; IS_BSC: Determine if this is Boot Strap Core -; -; In: -; NULL -; -; Out: -; CF = 1, it's BSC -; CF = 0, it's AP -; -; Destroyed: -; CF -;====================================================================== -%macro IS_BSC 0 - pushad - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - rdmsr - bt eax, APIC_BSC ; Is this the BSC? - popad - -%endmacro - - diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/CpStackHooksNasm.inc b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/CpStackHooksNasm.inc deleted file mode 100644 index 024939189c5c7f9eb0ae1fb83ea41a0324d0c44f..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/CpStackHooksNasm.inc +++ /dev/null @@ -1,452 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Copyright (C) 2008 - 2024 Advanced Micro Devices, Inc. All rights reserved. -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -; $Workfile:: CpStackHooksNasm.inc -; $Revision$ $Date$ -; -; Description: CpStackHooksNasm.inc - AGESA stack setup family hooks -; - -%include "NasmBase.inc" - -%define STACK_SIZE_4M 400000h ; 4MB -%define STACK_SIZE_2M 200000h ; 2MB -%define STACK_SIZE_1M 100000h ; 1MB -%define STACK_SIZE_256K 40000h ; 256KB -%define STACK_SIZE_192K 30000h ; 192KB -%define STACK_SIZE_128K 20000h ; 128KB -%define STACK_SIZE_64K 10000h ; 64KB -%define STACK_SIZE_32K 8000h ; 32KB -%define STACK_SIZE_16K 4000h ; 16KB -%define STACK_SIZE_4K 1000h ; 4KB - -%define CORE0_STACK_SIZE STACK_SIZE_16K ; 16KB for primary cores -%define CORE1_STACK_SIZE STACK_SIZE_4K ; 4KB for each AP cores - -%define BSP_STACK_BASE_ADDR 30000h ; Base address for core 0 stack -%define BSP_STACK_BASE_ADDR_4M 400000h ; Base address at 4MB -%define CORE0_STACK_BASE_ADDR 80000h ; Base address for primary cores stack -; -;CORE1_STACK_BASE_ADDR = BSP_STACK_BASE_ADDR + BSP_STACK_SIZE -; -%define BSP_CACHE_TYPE_POSITION 3 - -;============================================================================ -; -; Define a macro that allow the exclusion of processor families from -; the cache-as-ram code. This will reduce the size of the assembled file. -; -;============================================================================ - -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;--------------------------------------------------- -%macro AMD_ENABLE_STACK_FAMILY_HOOK 0 - - AMD_ENABLE_STACK_FAMILY_HOOK_F19 - AMD_ENABLE_STACK_FAMILY_HOOK_F1A - -%endmacro - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;---------------------------------------------- -%macro AMD_DISABLE_STACK_FAMILY_HOOK 0 - - AMD_DISABLE_STACK_FAMILY_HOOK_F19 - AMD_DISABLE_STACK_FAMILY_HOOK_F1A - -%endmacro - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI[7:0] = Core# (0..N, relative to node) -; SI[15:8]= Node# (0..N) -; SI[23:16]= reserved -; SI[24]= flag: 1=Family Unrecognized -; SI[25]= flag: 1=Interface re-entry call -; SI[26]= flag: 1=Core is primary of compute unit -; SI[31:27]= reserved, =0 -; -; Destroyed: -; eax, ebx, ecx, edx, esi -;--------------------------------------------------- -%macro GET_NODE_ID_CORE_ID 0 - - mov si, -1 - GET_NODE_ID_CORE_ID_F19 - GET_NODE_ID_CORE_ID_F1A - - ; - ; Check for unrecognized Family - ; - _if si, e, -1 ; Has family (node/core) been discovered? - mov esi, ( (1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY) ) ; No, Set error code, Only let BSP continue - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - rdmsr - bt eax, APIC_BSC ; Is this the BSC? - _if ncarry - ; - ; No, this is an AP - ; - hlt ; Kill APs - _endif - _endif -%endmacro - -;;*************************************************************************** -;; Family 19h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F19 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;--------------------------------------------------- -%macro AMD_ENABLE_STACK_FAMILY_HOOK_F19 0 - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 0Ah ; Is this family 19h? - jnz %%fam19_enable_stack_hook_exit ; Br if no - - ; - ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init. - ; - not strictly needed since the FixedMTRRs take presedence. - ; - mov ecx, TOP_MEM ; MSR:C001_001A - rdmsr - test eax, eax - _if zero - dec eax - wrmsr - _endif - -%%fam19_enable_stack_hook_exit: -%endmacro - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F19 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;--------------------------------------------------- -%macro AMD_DISABLE_STACK_FAMILY_HOOK_F19 0 - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 0Ah ; Is this family 19h? - jnz %%fam19_disable_stack_hook_exit ; Br if no - -%%fam19_disable_stack_hook_exit: -%endmacro - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F19 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -%macro GET_NODE_ID_CORE_ID_F19 0 - - jmp %%end_of_f19h_data - ; Family 19h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - %%FAM19H_INFO_STRUCT istruc CPU_FAMILY_INFO - at CPU_FAMILY_INFO.L2_MIN_SIZE, dw 2048 - at CPU_FAMILY_INFO.NUM_SHARED_CORES, db 2 - at CPU_FAMILY_INFO.L2_ALLOC_MEM, db 0 - at CPU_FAMILY_INFO.L2_ALLOC_EXE, dw 0 - at CPU_FAMILY_INFO.SIZE_ADDRESS_BUS, db 48 - at CPU_FAMILY_INFO.FAMILY_RESERVED, db 0 - iend -%%end_of_f19h_data: - jmp %%end_of_f19h_zen4_data - ; Family 19h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - %%FAM19H_ZEN4_INFO_STRUCT istruc CPU_FAMILY_INFO - at CPU_FAMILY_INFO.L2_MIN_SIZE, dw 2048 - at CPU_FAMILY_INFO.NUM_SHARED_CORES, db 2 - at CPU_FAMILY_INFO.L2_ALLOC_MEM, db 0 - at CPU_FAMILY_INFO.L2_ALLOC_EXE, dw 0 - at CPU_FAMILY_INFO.SIZE_ADDRESS_BUS, db 52 - at CPU_FAMILY_INFO.FAMILY_RESERVED, db 0 - iend -%%end_of_f19h_zen4_data: - - cmp si, -1 ; Has node/core already been discovered? - jnz %%node_core_f19_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr ebx, 16 ; BH = LocalApicId - mov bl, al - shr bl, 4 ; BL = cpu basic model - shr eax, 12 ; AH = cpu extended family - cmp ah, 0Ah ; Is this family 19h? - jnz %%node_core_f19_exit ; Br if no - or bl, al ; BL = cpu model - - cmp bl, 010h ; Is this RS - jz %%load_family_19_zen4_info ; Br if yes - cmp bl, 011h ; Is this RS B0 - jz %%load_family_19_zen4_info ; Br if yes - cmp bl, 018h ; Is this STP - jz %%load_family_19_zen4_info ; Br if yes - cmp bl, 0A0h ; Is this Bergamo - jz %%load_family_19_zen4_info ; Br if yes - jmp %%load_family_19_info - -%%load_family_19_zen4_info: - ; TODO, Need to check whether 52 bus is enabled or not - ; Assuming its enabled - LoadTableAddress %%FAM19H_ZEN4_INFO_STRUCT - jmp %%load_family_19_end -%%load_family_19_info: - LoadTableAddress %%FAM19H_INFO_STRUCT -%%load_family_19_end: - movd mm5, eax ; load pointer to Family Info Struc - - xor esi, esi ; Assume BSC, clear local flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - rdmsr - bt eax, APIC_BSC ; Is this the BSC? - _if ncarry - shr bx, 4 - shr bl, 4 - mov si, bx ; SI = [15:8]= Node# = 0; [7:0]= core# - _endif ; end - - ; - ; determine if this core shares MTRRs - ; - - AMD_CPUID AMD_CPUID_EXT_APIC - _if bh, ne, 0 - bt si, 0 - _if ncarry - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - _endif - _else - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - _endif - - bts esi, FLAG_DRAM_AVAILABLE -%%node_core_f19_exit: -%endmacro - -;;*************************************************************************** -;; Family 1Ah MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F1A Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -;--------------------------------------------------- -%macro AMD_ENABLE_STACK_FAMILY_HOOK_F1A 0 - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, EXT_FAMILY ; AL = cpu extended family - cmp al, 0bh ; Is this family 1Ah? - jnz %%fam1A_enable_stack_hook_exit ; Br if no - - ; - ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init. - ; - not strictly needed since the FixedMTRRs take presedence. - ; - mov ecx, TOP_MEM ; MSR:C001_001A - rdmsr - test eax, eax - - _if zero - dec eax - wrmsr - _endif - -%%fam1A_enable_stack_hook_exit: -%endmacro - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F1A Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -;--------------------------------------------------- -%macro AMD_DISABLE_STACK_FAMILY_HOOK_F1A 0 - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, EXT_FAMILY ; AL = cpu extended family - cmp al, 0bh ; Is this family 1ah? - jnz %%fam1A_disable_stack_hook_exit ; Br if no - -%%fam1A_disable_stack_hook_exit: -%endmacro - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F1A Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -%macro GET_NODE_ID_CORE_ID_F1A 0 - - jmp %%end_of_f1ah_48bit_data - - ; Family 1Ah Info Structure for 48 bits bus: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - %%FAM1AH_48BIT_INFO_STRUCT istruc CPU_FAMILY_INFO - at CPU_FAMILY_INFO.L2_MIN_SIZE, dw 2048 - at CPU_FAMILY_INFO.NUM_SHARED_CORES, db 2 - at CPU_FAMILY_INFO.L2_ALLOC_MEM, db 0 - at CPU_FAMILY_INFO.L2_ALLOC_EXE, dw 0 - at CPU_FAMILY_INFO.SIZE_ADDRESS_BUS, db 48 - at CPU_FAMILY_INFO.FAMILY_RESERVED, db 0 -%%end_of_f1ah_48bit_data: - jmp %%end_of_f1ah_52bit_data - - ; Family 1Ah Info Structure for 52 bits bus: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - %%FAM1AH_52BIT_INFO_STRUCT istruc CPU_FAMILY_INFO - at CPU_FAMILY_INFO.L2_MIN_SIZE, dw 2048 - at CPU_FAMILY_INFO.NUM_SHARED_CORES, db 2 - at CPU_FAMILY_INFO.L2_ALLOC_MEM, db 0 - at CPU_FAMILY_INFO.L2_ALLOC_EXE, dw 0 - at CPU_FAMILY_INFO.SIZE_ADDRESS_BUS, db 52 - at CPU_FAMILY_INFO.FAMILY_RESERVED, db 0 -%%end_of_f1ah_52bit_data: - - cmp si, -1 ; Has node/core already been discovered? - jnz %%node_core_f1A_exit ; Br if yes - - AMD_CPUID AMD_CPUID_CAP_EXT ; CPUID function 8000_0008h - and eax, PHYSICAL_ADDR_MASK ; - cmp al, 52 ; If the maximum physical address is 52 bits. - je %%load_family_1a_52bit_info ; Load 52-bit table if PAE is set - - ; Load 48-bit table. - LoadTableAddress %%FAM1AH_48BIT_INFO_STRUCT - jmp %%load_family_1a_info_end - -%%load_family_1a_52bit_info: - ; Load 52-bit table. - LoadTableAddress %%FAM1AH_52BIT_INFO_STRUCT - -%%load_family_1a_info_end: - movd mm5, eax ; load pointer to Family Info Struc - - AMD_CPUID CPUID_MODEL - shr eax, EXT_FAMILY ; AL = cpu extended family - cmp al, 0bh ; Is this family 1ah? - jnz %%node_core_f1A_exit ; Br if no - shr ebx, PROCESSOR_COUNT ; BH = LocalApicId (Node #), BL = Logical processor count (Core #) - xor esi, esi ; Assume BSC, clear local flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - rdmsr - bt eax, APIC_BSC ; Is this the BSC? - _if ncarry - mov si, bx ; SI = [15:8]= Node# = 0; [7:0]= core# - _endif ; end - - ; - ; determine if this core shares MTRRs - ; - AMD_CPUID AMD_CPUID_EXT_APIC - _if bh, ne, 0 - bt si, 0 - _if ncarry - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - _endif - _else - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - _endif - - bts esi, FLAG_DRAM_AVAILABLE -%%node_core_f1A_exit: -%endmacro - diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/CpStackNasm.inc b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/CpStackNasm.inc deleted file mode 100644 index 5fb79afaed03646e890af8a04712206595a4b616..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/CpStackNasm.inc +++ /dev/null @@ -1,855 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Copyright (C) 2008 - 2024 Advanced Micro Devices, Inc. All rights reserved. -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -; Workfile: CpStackNasm.inc $Revision$ $Date$ -; -; Description: Code to setup and break down stack -; - -;============================================================================ -; -; Define a macro that allow the OEM to specify supported solutions in the -; cache-as-ram code. This will reduce the size of the assembled file. -; The macro will convert solutions into supported families. -; -;============================================================================ - - %include "EarlyCpuSupportNasm.inc" - %include "CpStackHooksNasm.inc" - -;====================================================================== -; AMD_ENABLE_STACK_PRIVATE: Setup a stack -; -; In: -; EBX = Return address (preserved) -; -; Out: -; SS:ESP - Our new private stack location -; -; EAX = AGESA_STATUS -; EDX = Return status code if EAX contains a return code of higher -; severity than AGESA_SUCCESS -; ECX = Stack size in bytes -; -; Requirements: -; * This routine presently is limited to a max of 64 processor cores -; Preserved: -; ebx ebp -; Destroyed: -; eax, ecx, edx, edi, esi, ds, es, ss, esp -; mmx0, mmx1, mmx5 -; Input Parameter: -; STACK_AT_TOP -; Indicate stack is on the top of cache as RAM. -; STACK_AT_BOTTOM (default) -; Indicate stack is at the bottom of cache as RAM. -; -; BspStackSize (default: STACK_SIZE_64K) -; could be STACK_SIZE_64K, STACK_SIZE_128K, STACK_SIZE_192K, STACK_SIZE_256K -; N O T E: BspStackSize must be the same as the one in PspPlatformDriver.c (RESUME_BSP_STACK_SIZE) -; -; Description: -; Fixed MTRR address allocation to cores: -; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K. -; There is a max of 1 BSP, 7 core0s and 56 other cores. -; Although each core has it's own cache storage, they share the address space. Each core must -; be assigned a private and unique address space for its stack. To support legacy systems, -; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved -; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.) -; -; 80000h 40000h 00000h -; +----------+----------+----------+----------+----------+----------+----------+----------+ -; 64K | | | | | | | | | 64K ea -; ea +----------+----------+----------+----------+----------+----------+----------+----------+ -; | MTRR 0000_0250 MTRRfix64K_00000 | -; +----------+----------+----------+----------+----------+----------+----------+----------+ -; | 3 | 2 | 1 | 0 | 0 | | | | <-node -; | 15..1 | 15..1 | 15..1 | 15..1 | 0 | | | | <-core -; +----------+----------+----------+----------+----------+----------+----------+----------+ -; -; C0000h B0000h A0000h 90000h 80000h -; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -;16K | | | | | | | | | | | | | | | | | -; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -; | MTRR 0259 MTRRFIX16K_A0000 | MTRR 0258 MTRRFIX16K_80000 | -; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -; | > Dis|play B|uffer | < | | | | | | | | | | 3 | 2 | 1 | <-node -; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| | | | | | 0 | 0 | 0 | <-core -; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -; -; E0000h D0000h C0000h -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | 026B MTRRFIX4K_D8000 | 026A MTRRFIX4K_D0000 | 0269 MTRRFIX4K_C8000 | 0268 MTRRFIX4K_C0000 | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<| -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; -; 100000h F0000h E0000h -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | 026F MTRRFIX4K_F8000 | 026E MTRRFIX4K_F0000 | 026D MTRRFIX4K_E8000 | 026C MTRRFIX4K_E0000 | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -;====================================================================== -%macro AMD_ENABLE_STACK_PRIVATE 3 - - %if (%2 < STACK_SIZE_1M) - %if ((%2 != STACK_SIZE_64K) && (%2 != STACK_SIZE_128K) && (%2 != STACK_SIZE_192K) && (%2 != STACK_SIZE_256K)) - jmp $ ; We only support 64K, 128K, 192K, 256K, please check input parameter - %endif - %else - %if ((%2 % 100000h) != 0) - jmp $ ; For BspStackSize >= 1MB, BspStackSize needs to be aligned with 1MB - %endif - %endif - - ; Note that SS:ESP will be default stack. Note that this stack - ; routine will not be used after memory has been initialized. Because - ; of its limited lifetime, it will not conflict with typical PCI devices. - movd mm0, ebx ; Put return address in a safe place - movd mm1, ebp ; Save some other user registers - - ; get node id and core id of current executing core - GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) - ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established - - ; If Stack Base is located under 1M, limit it to the first 640K - mov ebp, %3 - _if ebp, b, 0100000h - _if ebp, ae, 0A0000h - mov edx, CPU_EVENT_STACK_BASE_OUT_OF_BOUNDS - mov eax, AGESA_FATAL - jmp %%AmdEnableStackExit - _endif - _endif - - ; If BspStackSize is >= 1MB, then BspStackAddr should also >= 1MB - %if (%2 >= STACK_SIZE_1M) - %if (%3 < 0100000h) - mov edx, CPU_EVENT_STACK_BASE_OUT_OF_BOUNDS - mov eax, AGESA_FATAL - jmp %%AmdEnableStackExit - %endif - %endif - - ; STACK_SIZE_1M or greater is not valid for systems where DRAM is not yet available at this timepoint. - bt esi, FLAG_DRAM_AVAILABLE - _if ncarry - %if (%2 >= STACK_SIZE_1M) - mov edx, CPU_EVENT_STACK_SIZE_INVALID - mov eax, AGESA_FATAL - jmp %%AmdEnableStackExit - %endif - _endif - - ; If we detected an unknown processor family or core combination, return AGESA_FATAL. - test esi, (1 << FLAG_UNKNOWN_FAMILY) - _if ne - mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY - mov eax, AGESA_FATAL - jmp %%AmdEnableStackExit - _else - test esi, (1 << FLAG_CORE_NOT_IDENTIFIED) - _if ne - mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED - mov eax, AGESA_FATAL - jmp %%AmdEnableStackExit - _endif - _endif - - ; determine if stack is already enabled. We are using the DefType MSR for this determination. - ; It is =0 after reset; CAR setup sets it to enable the MTRRs - mov eax, cr0 ; Is cache enabled? (CD or NW bit set) - %define CR0_MASK ((1 << CR0_CD) | (1 << CR0_NW)) - test eax, CR0_MASK - _if e - mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF - rdmsr ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN) - %define MSR_MASK ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) - test eax, MSR_MASK - _if ne - bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized - _endif - _endif - - AMD_ENABLE_STACK_FAMILY_HOOK - - ; Init CPU MSRs for our init routines - mov ecx, MTRR_SYS_CFG ; SYS_CFG - rdmsr - bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit - wrmsr - - mov eax, esi - bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry? - _if ncarry ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP - bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit? - _if carry ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset - ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores - ; Clear all variable and Fixed MTRRs for non-shared cores - mov ecx, AMD_MTRR_VARIABLE_BASE0 - xor eax, eax - xor edx, edx - _while cl, ne, 10h ; Variable MTRRphysBase[n] and MTRRphysMask[n] - wrmsr - inc cl - _endw - mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250 - wrmsr - mov cx, AMD_MTRR_FIX16K_80000 ; MSR:0000_0258 - wrmsr - mov cx, AMD_MTRR_FIX16K_A0000 ; MSR:0000_0259 - wrmsr - mov cx, AMD_MTRR_FIX4K_C0000 ; Fixed 4Ks: MTRRFIX4K_C0000 to MTRRFIX4K_F8000 - _while cl, ne, 70h - wrmsr - inc cl - _endw - - _endif ; End Is_Primary - _endif ; End Stack_ReEntry - - ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores - xor eax, eax - xor edx, edx - mov ecx, IORR_BASE ; MSR:C001_0016 - 0019 - _while cl, ne, 1Ah - wrmsr - inc cl - _endw - - ; setup MTTRs for stacks - ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone - ; or due to a data zone being interpreted as code. When a speculative read occurs outside a - ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. - ; To prevent speculative reads from causing an eviction, the unused cache ranges are set - ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs. - ; Note: some core stack regions will share an MTRR since the control granularity is much - ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra' - ; space covered by the MTRR when parseling out cache space for the various uses. In some cases - ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c - ; - ; Outcome of this block is that: (Note the MTRR map at the top of the file) - ; ebp - start address of stack block - ; ebx - [31:16] - MTRR MSR address - ; - [15:8] - slot# in MTRR register - ; - [7:0] - block size in #4K blocks - ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node) - ; - mov eax, esi ; Load Flags, node, core - _if al, e, 0 ; Is a core 0? - _if ah, e, 0 ; Is Node 0? (BSP) - bt esi, FLAG_DRAM_AVAILABLE - _if carry - ; a) For stack located under 1M, use Fixed MTRRs - _if ebp, b, 0100000h - ; a.i) Use Fixed 0250h and possibly 0258h - _if ebp, b, 080000h - ; Calculate starting block # - mov ecx, ebp - and ecx, 0F0000h - shr ecx, 16 - - ; Calculate # of 64K blocks to fill - mov bl, (%2 / 10000h) - mov ch, bl - - ; Calculate end block # - add ch, cl - - ; bl = Number of 64K blocks - ; cl = Start block # - ; ch = End block # - _if cl, b, 4 - _if ch, be, 4 - ; - ; a.i.i) if Start Block and End Block are within the lower 32 bits of MTRR - ; - mov edi, WB_DRAM_TYPE - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - shl cl, 3 - shl edi, cl - - mov ecx, AMD_MTRR_FIX64k_00000 - rdmsr - or eax, edi - wrmsr - _else - ; - ; a.i.ii) if Start Block and End Block spans upper and lower bits of MTRR - ; - ; bh = number of blocks that needs to be set in the lower 32 bits - mov bh, 4 - sub bh, cl - - ; Store number of remaining blocks to be set in upper 32 bits in ecx [24:16] - ror ecx, 16 - mov cl, bl - sub cl, bh - rol ecx, 16 - - mov edi, WB_DRAM_TYPE - _while bh, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bh - _endw - - ; transfer number of blocks to bs set in the upper 32 bits to ebx - mov ebx, ecx - - ; move to the correct Start block position - shl cl, 3 - shl edi, cl - - mov ecx, AMD_MTRR_FIX64k_00000 - rdmsr - or eax, edi - - mov edi, WB_DRAM_TYPE - ; Retrieve number of remaining blocks to be set in the upper 32 bits of MTRR - ror ebx, 16 - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - or edx, edi - wrmsr - _endif - _else - _if ch, be, 8 - ; - ; a.i.iii) if Start Block and End Block are within the upper 32 bits of MTRR - ; - sub cl, 4 - - mov edi, WB_DRAM_TYPE - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - - shl cl, 3 - shl edi, cl - - mov ecx, AMD_MTRR_FIX64k_00000 - rdmsr - or edx, edi - wrmsr - _else - ; - ; a.i.iv) if Start Block and End Block spans multiple MTRRs - ; - ; bh = Number of blocks that need to be set in MSR0000_0250 - mov bh, 8 - sub bh, cl - - ; Store number of remaining blocks to be set in MSR0000_0258 in ebx[24:16] - mov al, bl - sub al, bh - ror ebx, 16 - mov bx, ax - rol ebx, 16 - - mov edi, WB_DRAM_TYPE - _while bh, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bh - _endw - - shl cl, 3 - shl edi, cl - - ; Since the max size for stack under 1M is 256K, if the start block and end block - ; spans multiple MTRRs, then only upper bits of MSR250 needs to be set - mov ecx, AMD_MTRR_FIX64k_00000 - rdmsr - or edx, edi - wrmsr - - ; Retrieve number of blocks to be set in MSR0000_0258 - ror ebx, 16 - ; bl = Number of 16K blocks to be set in the lower 32 bits of MSR0000_0258 - shl bl, 2 - mov bh, bl - ; bh = Number of 16K blocks to be set in the upper 32 bits of MSR0000_0258 - sub bh, 4 - - mov edi, WB_DRAM_TYPE - _if bl, a, 4 - mov bl, 4 - _endif - - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - - mov ecx, AMD_MTRR_FIX16K_80000 - rdmsr - or eax, edi - - _if bh, e, 0 - xor edi, edi - _else - mov edi, WB_DRAM_TYPE - ; If number of slots exceeds 4, ignore the remaining since we are limiting stack within 640K - _if bh, a, 4 - mov bh, 4 - _endif - _endif - _while bh, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bh - _endw - - or edx, edi - wrmsr - - _endif - _endif - _else - ; a.ii) Use Fixed 258h - - ; Calculate start block # - mov ecx, ebp - and ecx, 01F000h - shr ecx, 14 - - ; Calculate # of 16K blocks to fill - mov bl, (%2 / 4000h) - mov ch, bl - - ; Calculate end block # - add ch, cl - - ; bl = Number of 16K blocks - ; cl = Start block # - ; ch = End block # - _if cl, b, 4 - _if ch, be, 4 - ; - ; a.ii.i) if Start Block and End Block are within the lower 32 bits of MTRR - ; - mov edi, WB_DRAM_TYPE - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - - mov ecx, AMD_MTRR_FIX16K_80000 - rdmsr - or eax, edi - wrmsr - _else - ; - ; a.ii.ii) if Start Block and End Block spans both the upper and lower 32 bits of the MTRR - ; - ; bh = number of blocks to be set in the lower 32 bits - mov bh, 4 - sub bh, cl - - ; store number of remaining blocks to be set in the upper 32 bits in ecx[26:16] - ror ecx, 16 - mov cl, bl - sub cl, bh - rol ecx, 16 - - mov edi, WB_DRAM_TYPE - _while bh, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bh - _endw - - shl cl, 3 - shl edi, cl - - ; transfer number of blocks to bs set in the upper 32 bits to ebx - mov ebx, ecx - - mov ecx, AMD_MTRR_FIX16K_80000 - rdmsr - or eax, edi - - mov edi, WB_DRAM_TYPE - ; Retrieve number of remaning blocks to be set in the upper 32 bits - ror ebx, 16 - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - - or edx, edi - wrmsr - - _endif - _else - ; - ; a.ii.iii) if Start Block and End Block are within the upper 32 bits of the MTRR - ; - mov edi, WB_DRAM_TYPE - _while bl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec bl - _endw - - mov ecx, AMD_MTRR_FIX16K_80000 - rdmsr - or edx, edi - wrmsr - _endif - _endif - - ; Set ebx with the correct value for later use - mov ebx, (%2 / 1000h) - jmp %%GoToVarMtrr - _else - ; b. If stack is located above 1M, use variable MTRRs - mov ebx, (%2 / 1000h) - jmp %%GoToVarMtrr - _endif - _else - ; Is BSP, assigning stack as specified by %2 - mov ebx, ((AMD_MTRR_FIX64k_00000 << 16) + (BSP_CACHE_TYPE_POSITION << 8) + (%2 / 1000h)) - mov ebp, BSP_STACK_BASE_ADDR - _endif - _else ; node 1 to 7, core0 - ; Is a Core0 of secondary node, assign 16K stacks - mov bx, AMD_MTRR_FIX16K_80000 - shl ebx, 16 ; - dec ah ; index from 0 - mov bh, ah ; Node# is used as slot# - mov bl, (CORE0_STACK_SIZE / 1000h) - mov al, ah ; Base = (Node# * Size); - mul bl ; - movzx eax, ax ; - shl eax, 12 ; Expand back to full byte count (* 4K) - add eax, CORE0_STACK_BASE_ADDR - mov ebp, eax - _endif - _else ;core 1 thru core 15 - ; Is core 1-15 of any node, assign 4K stacks - mov al, 16 ; CoreIndex = ( (Node# * 16) ... - mul ah ; - mov bx, si ; - dec bl ; account for core 0 on P1, etc - add al, bl ; ... + Core#); - - mov bx, AMD_MTRR_FIX64k_00000 - shl ebx, 16 ; - mov bh, al ; Slot# = (CoreIndex / 16) + 4; - shr bh, 4 ; - add bh, (%2 / 10000h + BSP_CACHE_TYPE_POSITION) - mov bl, (CORE1_STACK_SIZE / 1000h) - - mul bl ; Base = ( (CoreIndex * Size) ... - movzx eax, ax ; - shl eax, 12 ; Expand back to full byte count (* 4K) - add eax, (BSP_STACK_BASE_ADDR + %2) ; ... + Base_Addr); - mov ebp, eax - _endif - - ; Now set the MTRR. Add this to already existing settings (do not clear any MTRR) - ; Set lower 32 bits of MTRR - mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot - mov cl, bl ; block size in #64K blocks - shr cl, 4 - _if cl, a, 4 - jmp $ ; We do NOT support size larger than 256K - _endif - _while cl, a, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec cl - _endw - mov cl, bh ; ShiftCount = ((slot# ... - _if cl, a, 3 - mov edi, 0 - _else - shl cl, 3 ; ... * 8); - shl edi, cl ; Cache type is now in correct position - _endif - ror ebx, 16 ; Get the MTRR address - movzx ecx, bx ; - rol ebx, 16 ; Put slot# & size back in BX - rdmsr ; Read-modify-write the MSR - or eax, edi ; - - ; Set upper 32 bits of MTRR - mov cl, bl - add cl, 0Fh - shr cl, 4 - dec cl - add cl, bh - mov ch, cl - _if cl, ae, 4 - _if bh, ae, 4 - mov cl, bh - _else - mov cl, 4 - _endif - sub ch, cl - sub cl, 4 - mov edi, WB_DRAM_TYPE - _while ch, ae, 1 - shl edi, 8 - or edi, WB_DRAM_TYPE - dec ch - _endw - shl cl, 3 - shl edi, cl - _else - mov edi, 0 - _endif - ror ebx, 16 ; Get the MTRR address - movzx ecx, bx ; - rol ebx, 16 ; Put slot# & size back in BX - or edx, edi ; - wrmsr ; - -%%GoToVarMtrr: - bt esi, FLAG_IS_PRIMARY ; Is this a primary core? - _if carry - bt esi, FLAG_DRAM_AVAILABLE ; Is system DRAM initialized? - _if carry - mov ecx, TOP_MEM ; Read the top of memory below 4GB - rdmsr - mov edi, eax ; EDI = top of memory below 4GB - xor esp, esp ; Initialize DRAM base address to 0 - mov ecx, AMD_MTRR_VARIABLE_BASE0 ; Start with VarMtrr0 - jmp %%WhileCheck - %%WhileStart: ; Loop until all set bits are accounted for or we run out of mtrrs - mov eax, esp ; EAX = region base - mov al, MTRR_TYPE_WB ; WB type - xor edx, edx ; Only describing below 4GB - wrmsr ; Apply var mtrr base - inc cx ; Set ECX to var mtrr limit register - bsr edx, edi ; Find MSb - btr edi, edx ; Mark it as accounted for - xor eax, eax ; EAX = 0 - bts eax, edx ; EAX = region size - mov edx, esp ; EDX = current region base - add edx, eax ; EDX = next region base - mov esp, edx ; ESP = next region base - neg eax ; EAX = lower 32 bits of the mask required for this region's size - bts eax, VMTRR_VALID ; Set the valid bit - mov edx, edi ; Save EDI to EDX - movd edi, mm5 ; Load pointer to Family Info Struc - bswap ecx ; Save MTRR address to ECX[31:16] - mov cl, [edi + CPU_FAMILY_INFO.SIZE_ADDRESS_BUS] ; CL = number of address bits for this family - mov edi, edx ; Restore EDI - xor edx, edx ; EDX = 0 - _if cl, b, 64 - sub cl, 32 ; CL = number of valid address bits between [63:32] - inc dx ; EDX = 1 - shl edx, cl ; - _endif - dec edx ; EDX = Upper half of the address mask for this family - xor cl, cl ; Restore CL - bswap ecx ; Restore ECX - wrmsr ; Enable the var mtrr - inc cx ; Point to next var mtrr base - %%WhileCheck: - cmp edi, 0 - je %%WhileEnd - cmp ecx, AMD_MTRR_VARIABLE_BASE6 - jb %%WhileStart - %%WhileEnd: - _endif - _endif - - ; Enable MTRR defaults as UC type - mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF - rdmsr ; Read-modify-write the MSR - bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn - bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn - wrmsr - - ; Close the modification window on the Fixed MTRRs - mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010 - rdmsr - bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn - bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit - btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit - wrmsr - - ; Enable caching in CR0 - mov eax, CR0 ; Enable WT/WB cache - btr eax, CR0_PG ; Make sure paging is disabled - btr eax, CR0_CD ; Clear CR0 NW and CD - btr eax, CR0_NW - mov CR0, eax - - ; Use the Stack Base & size to calculate SS and ESP values - ; review: - ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - ; ebp - start address of stack block - ; ebx - [31:16] - MTRR MSR address - ; - [15:8] - slot# in MTRR register - ; - [7:0] - block size in #4K blocks - ; - mov esp, ebp ; Initialize the stack pointer - mov edi, esp ; Copy the stack start to edi - bt esi, FLAG_DRAM_AVAILABLE - - _if ncarry - movzx bx, bl - movzx ebx, bx ; Clear upper ebx, do not need MSR addr anymore - _endif - shl ebx, 12 ; Make size full byte count (* 4K) - %if (%1 = STACK_AT_BOTTOM) - mov ax, si - _if al, e, 0 ; Only BSC needs to cut its CAR in half for PEI RAM - shr ebx, 1 ; If stack is at the bottom of CAR, divide size by 2 - _endif - %endif - add esp, ebx ; Set the Stack Pointer as full linear address - sub esp, 4 - ; - ; review: - ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - ; edi - 32b start address of stack block - ; ebx - size of stack block - ; esp - 32b linear stack pointer - ; - - ; Determine mode for SS base; - mov ecx, CR0 ; Check for 32-bit protect mode - bt ecx, CR0_PE ; - _if ncarry ; PE=0 means real mode - mov cx, cs ; - _if cx, ae, 0D000h ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000 - ; alter SS:ESP for 16b Real Mode: - mov eax, edi ; - shr eax, 4 ; Create a Real Mode segment for ss, ds, es - mov ss, ax ; - mov ds, ax ; - mov es, ax ; - shl eax, 4 ; - sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode - mov esp, ebx ; Make SP an offset from SS - sub esp, 4 ; - _endif ; endif - ; else - ; Default is to use Protected 32b Mode - _endif - %if (%1 = STACK_AT_BOTTOM) - mov ax, si - _if al, e, 0 - shl ebx, 1 ; restore the size of CAR - _endif - %endif - ; - ; Clear The Stack - ; Now that we have set the location and the MTRRs, initialize the cache by - ; reading then writing to zero all of the stack area. - ; review: - ; ss - Stack base - ; esp - stack pointer - ; ebx - size of stack block - ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - ; edi - address of start of stack block - ; - shr ebx, 2 ; - mov ecx, ebx ; set cx for size count of DWORDS - - ; Check our flags - Do not clear an existing stack - test esi, (1 << FLAG_STACK_REENTRY) - _if zero - cld - mov esi, edi - rep lodsd ; Pre-load the range - xor eax, eax - mov ecx, ebx - mov esi, edi ; Preserve base for push on stack - rep stosd ; Clear the range - mov dword [esp], 0ABCDDCBAh ; Put marker in top stack dword - shl ebx, 2 ; Put stack size and base - push ebx ; in top of stack - push esi - - mov ecx, ebx ; Return size of stack in bytes - mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code - _else - movzx ecx, cx - shl ecx, 2 ; Return size of stack, in bytes - mov edx, CPU_EVENT_STACK_REENTRY - mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up) - _endif - -%%AmdEnableStackExit: - movd ebx, mm0 ; Restore return address - movd ebp, mm1 -%endmacro - -;====================================================================== -; AMD_DISABLE_STACK_PRIVATE: Destroy the stack inside the cache. This routine -; should only be executed on the BSP -; -; In: -; none -; -; Out: -; EAX = AGESA_SUCCESS -; -; Preserved: -; ebx -; Destroyed: -; eax, ecx, edx, esp, mmx5 -;====================================================================== -%macro AMD_DISABLE_STACK_PRIVATE 0 - - mov esp, ebx ; Save return address - - ; get node/core/flags of current executing core - GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) - - ; Turn on modification enable bit - mov ecx, MTRR_SYS_CFG ; MSR:C001_0010 - rdmsr - bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications - wrmsr - - ; Set lower 640K MTRRs for Write-Back memory caching - mov ecx, AMD_MTRR_FIX64k_00000 - mov eax, 1E1E1E1Eh - mov edx, eax - wrmsr ; 0 - 512K = WB Mem - mov ecx, AMD_MTRR_FIX16K_80000 - wrmsr ; 512K - 640K = WB Mem - - ; Turn off modification enable bit - mov ecx, MTRR_SYS_CFG ; MSR:C001_0010 - rdmsr - btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification - wrmsr - - AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations - - mov ebx, esp ; restore return address (ebx) - xor eax, eax - -%endmacro - - - diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/EarlyCpuSupportNasm.inc b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/EarlyCpuSupportNasm.inc deleted file mode 100644 index 78a3b63ec45ce1ec336b12a1da1ff6940369a3c7..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/EarlyCpuSupportNasm.inc +++ /dev/null @@ -1,208 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Copyright (C) 2008 - 2024 Advanced Micro Devices, Inc. All rights reserved. -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -; $Workfile:: EarlyCpuSupportNasm.inc -; -; $Revision$ $Date$ -; -; Description: -; - -%define STACK_AT_TOP 0 ; Stack is at the top of CAR -%define STACK_AT_BOTTOM 1 ; Stack is at the bottom of CAR - -%define APIC_BASE_ADDRESS 0000001Bh -%define APIC_BSC 8 ; Boot Strap Core - -%define APIC_MSG_REG 380h ; Location of BSC message -%define APIC_MSG 00DE00ADh ; Message data -%define APIC_INVD_ALL_DONE_MSG 00AD00DEh ; Indicate all cores have invalidated -%define APIC_CMD_LO_REG 300h ; APIC command low -%define APIC_CMD_HI_REG 310h ; APIC command high -%define CMD_REG_TO_READ_DATA 00000338h ; APIC command for remote read of APIC_MSG_REG -%define REMOTE_READ_STS 00030000h ; Remote read status mask -%define REMOTE_DELIVERY_PEND 00010000h ; Remote read is pending -%define REMOTE_DELIVERY_DONE 00020000h ; Remote read is complete -%define DELIVERY_STS_BIT 12 ; Delivery status valid bit -%define APIC_ID_REG 0020h ; Local APIC ID offset -%define APIC20_APICID 24 -%define APIC_REMOTE_READ_REG 00C0h ; Remote read offset - -%define AMD_MTRR_VARIABLE_BASE0 0200h -%define AMD_MTRR_VARIABLE_BASE6 020Ch -%define AMD_MTRR_VARIABLE_BASE7 020Eh -%define VMTRR_VALID 11 -%define MTRR_TYPE_WB 06h -%define MTRR_TYPE_WP 05h -%define MTRR_TYPE_WT 04h -%define MTRR_TYPE_UC 00h -%define AMD_MTRR_VARIABLE_MASK0 0201h -%define AMD_MTRR_VARIABLE_MASK7 020Fh -%define AMD_MTRR_FIX64k_00000 0250h -%define AMD_MTRR_FIX16K_80000 0258h -%define AMD_MTRR_FIX16K_A0000 0259h -%define AMD_MTRR_FIX4K_C0000 0268h -%define AMD_MTRR_FIX4K_C8000 0269h -%define AMD_MTRR_FIX4K_D0000 026Ah -%define AMD_MTRR_FIX4K_D8000 026Bh -%define AMD_MTRR_FIX4K_E0000 026Ch -%define AMD_MTRR_FIX4K_E8000 026Dh -%define AMD_MTRR_FIX4K_F0000 026Eh -%define AMD_MTRR_FIX4K_F8000 026Fh -%define CPU_LIST_TERMINAL 0FFFFFFFFh - -%define AMD_MTRR_DEFTYPE 02FFh -%define WB_DRAM_TYPE 1Eh ; MemType - memory type -%define MTRR_DEF_TYPE_EN 11 ; MtrrDefTypeEn - variable and fixed MTRRs default enabled -%define MTRR_DEF_TYPE_FIX_EN 10 ; MtrrDefTypeEn - fixed MTRRs default enabled - -%define INVD_WBINVD 4 ; INVD to WBINVD conversion - -%define IORR_BASE 0C0010016h ; IO Range Regusters Base/Mask, 2 pairs - ; uses 16h - 19h -%define TOP_MEM 0C001001Ah ; Top of Memory -%define TOP_MEM2 0C001001Dh ; Top of Memory2 - -%define CR0_PE 0 ; Protection Enable -%define CR0_NW 29 ; Not Write-through -%define CR0_CD 30 ; Cache Disable -%define CR0_PG 31 ; Paging Enable - -; CPUID Functions - -%define CPUID_MODEL 1 - ; In EAX -%define EXT_MODEL 16 ; Extended model -%define EXT_FAMILY 20 ; Extended family - ; In EBX -%define PROCESSOR_COUNT 16 ; Logical processor count -%define LOCAL_APIC_ID 24 ; LocalApicId - initial local APIC physical ID - ; In EDX -%define PYSYCAL_ADDRESS_EXT 6 ; Physical addresss extensions. - - -%define AMD_CPUID_L2Cache 80000006h ; L2/L3 cache info -%define AMD_CPUID_APIC 80000008h ; Long Mode and APIC info., core count -%define APIC_ID_CORE_ID_SIZE 12 ; ApicIdCoreIdSize bit position -%define AMD_CPUID_EXT_APIC 8000001Eh ; Extended APICID information - -%define AMD_CPUID_CAP_EXT 80000008h ; Processor capability parameter and - ; Extended feature identification. -%define PHYSICAL_ADDR_MASK 0FFh ; - -%define MTRR_SYS_CFG 0C0010010h ; System Configuration Register -%define SYS_UC_LOCK_EN 17 ; SysUcLockEn System lock command enable -%define MTRR_FIX_DRAM_EN 18 ; MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable -%define MTRR_FIX_DRAM_MOD_EN 19 ; MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable -%define MTRR_VAR_DRAM_EN 20 ; MtrrVarDramEn MTRR variable DRAM enable - -; Local use flags, in upper most byte of ESI -%define FLAG_UNKNOWN_FAMILY 24 ; Signals that the family# of the installed processor is not recognized -%define FLAG_STACK_REENTRY 25 ; Signals that the environment has made a re-entry (2nd) call to set up the stack -%define FLAG_IS_PRIMARY 26 ; Signals that this core is the primary within the compute unit -%define FLAG_CORE_NOT_IDENTIFIED 27 ; Signals that the cores/compute units of the installed processor is not recognized -%define FLAG_FORCE_32K_STACK 28 ; Signals to force 32KB stack size for BSP core -%define FLAG_DRAM_AVAILABLE 29 ; Signals that DRAM is present - -; Error code returned in EDX by AMD_ENABLE_STACK_PRIVATE -%ifndef CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY -%define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 008010500h -%endif -%ifndef CPU_EVENT_STACK_REENTRY -%define CPU_EVENT_STACK_REENTRY 008020500h -%endif -%ifndef CPU_EVENT_CORE_NOT_IDENTIFIED -%define CPU_EVENT_CORE_NOT_IDENTIFIED 008030500h -%endif -%ifndef CPU_EVENT_STACK_BASE_OUT_OF_BOUNDS -%define CPU_EVENT_STACK_BASE_OUT_OF_BOUNDS 008040500h -%endif -%ifndef CPU_EVENT_STACK_SIZE_INVALID -%define CPU_EVENT_STACK_SIZE_INVALID 008050500h -%endif - -; AGESA_STATUS values -%ifndef AGESA_SUCCESS -%define AGESA_SUCCESS 0 -%endif -%ifndef AGESA_WARNING -%define AGESA_WARNING 4 -%endif -%ifndef AGESA_FATAL -%define AGESA_FATAL 7 -%endif -;;*************************************************************************** -;; -;; CPU MACROS - PUBLIC -;; -;;*************************************************************************** - -%macro AMD_CPUID 0-1 - %if (%0 = 0) - mov eax, 1 - db 0Fh, 0A2h ; Execute instruction - bswap eax - xchg al, ah ; Ext model in al now - rol eax, 8 ; Ext model in ah, model in al - and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0 - %else - mov eax, %1 - db 0Fh, 0A2h - %endif -%endmacro - -%macro MAKE_SBDFO 5 - mov eax, ((%1 << 28) | (%2 << 20) | (%3 << 15) | (%4 << 12) | (%5)) -%endmacro - -%macro MAKE_EXT_PCI_ADDR 5 - mov eax, ((1 << 31) | (%1 << 28) | (((%5 & 0F00h) >> 8) << 24) | (%2 << 16) | (%3 << 11) | (%4 << 8) | (%5 & 0FCh)) -%endmacro - -;--------------------------------------------------- -; LoadTableAddress -; Due to the various assembly methodologies used by BIOS vendors, this macro is needed to abstract the -; loading of the address of a table. The default is the standard LEA instruction with table address. -; The IBV that needs to use an alternative method can define their version of the macro prior to including -; this file into their source. -; An alternative example: -; LoadTableAddress MACRO MyTable -; LEA eax, -(LAST_ADDRESS - MyTable) -;--------------------------------------------------- -%ifnmacro LoadTableAddress 1 -%macro LoadTableAddress 1 - lea eax, [%1] -%endmacro -%endif - - -;;*************************************************************************** -;; -;; CPU STRUCTURES - PUBLIC -;; -;;*************************************************************************** -struc CPU_FAMILY_INFO - .L2_MIN_SIZE resw 1 ; Minimum size of the L2 cache for this family, in K - .NUM_SHARED_CORES resb 1 ; Number of cores sharing an L2 cache - .L2_ALLOC_MEM resb 1 ; L2 space reserved for memory training, in K - .L2_ALLOC_EXE resw 1 ; L2 space reserved for EXE CACHE, in K. 0 means unlimited. - .SIZE_ADDRESS_BUS resb 1 ; Number of address bits supported by this family - .FAMILY_RESERVED resb 1 ; reserved, pad to DWORD size -endstruc - - -%macro CPU_DEADLOOP 0 - -%%DeadLoop: - out 84h, al - jmp %%DeadLoop - -%endmacro - - - - - diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm index dbf18413daa89b62283e19a3db71a704dccbeb28..cdccb423e0456dc5e81320aa6b9219f9b5047542 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Flat32.nasm @@ -9,7 +9,7 @@ ; It consumes the reset vector, and configures the stack. ; ; Copyright (c) 2013-2015 Intel Corporation -; Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +; Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. ; ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -51,6 +51,11 @@ extern ASM_PFX(BoardBeforeTempRamInit) extern ASM_PFX(BoardAfterTempRamInitWrapper) +; Following are fixed PCDs + +extern ASM_PFX(PcdGet32 (PcdPciExpressBaseAddressHi)) +extern ASM_PFX(PcdGet32 (PcdPciExpressBaseAddressLow)) + %define BSP_HEAP_STACK_BASE FixedPcdGet32 (PcdTempRamBase) %define BSP_HEAP_STACK_SIZE FixedPcdGet32 (PcdTempRamSize) %define FLASH_IMAGE_SIZE FixedPcdGet32 (PcdFlashAreaSize) @@ -177,6 +182,19 @@ ProtectedModeEntryPoint: ; Early board hooks ; JMP32 ASM_PFX(BoardBeforeTempRamInit) + ; + ; Configure MMIO Base Address + ; + mov ecx, 0x0C0010058 + rdmsr + mov ebx, eax + mov eax, DWORD [ASM_PFX(PcdGet32 (PcdPciExpressBaseAddressLow))] + or eax, ebx + or eax, MMIO_CFG_ENABLE + mov edx, DWORD [ASM_PFX(PcdGet32 (PcdPciExpressBaseAddressHi))] + mov ecx, 0x0C0010058 + wrmsr + ; ; Set UEFI stack ; diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/NasmBase.inc b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/NasmBase.inc deleted file mode 100644 index 8b56a38ae8f7c75c29f3a9c5b31010abfbcfa6ac..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/NasmBase.inc +++ /dev/null @@ -1,141 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Copyright (C) 2008 - 2024 Advanced Micro Devices, Inc. All rights reserved. -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -; $Workfile:: NasmBase.inc -; -; $Revision$ $Date$ -; -; Description: -; - -%ifnmacro _if 1-3 -%macro _if 1-3 - - nop ;WA for nasm to avoid label incorrect issue - - %push _if - - %if %0 = 1 - - %ifidn %1, carry - jae %$ifnot - %elifidn %1, ncarry - jb %$ifnot - %elifidn %1, zero - jne %$ifnot - %elifidn %1, nzero - je %$ifnot - %else - j%-1 %$ifnot - %endif - - %endif - - %if %0 = 2 - %error "2 parameters is not allowed" - %endif - - %if %0 = 3 - cmp %1, %3 - j%-2 %$ifnot - %endif - -%endmacro -%endif - - -%ifnmacro _else 0 -%macro _else 0 - - %ifctx _if - %repl _else - jmp %$ifend - %$ifnot: - %else - %error "expected '_if' before '_else'" - %endif - -%endmacro -%endif - - -%ifnmacro _endif 0 -%macro _endif 0 - - %ifctx _if - %$ifnot: - %elifctx _else - %$ifend: - %else - %error "expected '_if' or '_else' before '_endif'" - %endif - - %pop - -%endmacro -%endif - - -%ifnmacro _while 1-3 -%macro _while 1-3 - - nop ;WA for nasm to avoid label incorrect issue - - %push _while - - - %if %0 = 1 - %define %$arg1 %1 - %define %$arg2 one_parameter - %define %$arg3 one_parameter - %endif - - %if %0 = 2 - %error "2 parameters is not allowed" - %endif - - %if %0 = 3 - %define %$arg1 %1 - %define %$arg2 %2 - %define %$arg3 %3 - %endif - - jmp %$whilecheck - %$whilestart: -%endmacro -%endif - - -%ifnmacro _endw 0 -%macro _endw 0 - - %ifctx _while - %$whilecheck: - %ifidn %$arg2, one_parameter - %ifidn %$arg1, carry - jb %$whilestart - %elifidn %$arg1, ncarry - jae %$whilestart - %elifidn %$arg1, zero - je %$whilestart - %elifidn %$arg1, nzero - jne %$whilestart - %else - j%1 %$whilestart - %endif - %else - cmp %$arg1, %$arg3 - j%$arg2 %$whilestart - %endif - %else - %error "expected '_while' before '_endw'" - %endif - - %pop - -%endmacro -%endif - diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc index e2fd7e254a1c594b7f69414b35592368d5810905..60710c1af32065a345c5a1d49f7bc5d129eb9231 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/Ia32/Platform.inc @@ -7,7 +7,7 @@ ; Platform Specific Definitions ; ; Copyright (c) 2013-2015 Intel Corporation -; Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +; Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. ; ; SPDX-License-Identifier: BSD-2-Clause-Patent ; diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.c b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.c index 5fee7f8d42403b26f39da66d795c8f034d6ee826..8d820d3ee2419e1ebfa55be6e2af380569d53a80 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.c @@ -2,7 +2,7 @@ Platform SEC Library. Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -19,24 +19,7 @@ Platform SEC Library. #include #include -#define SYS_CFG 0xC0010010ul -#define TOP_MEM 0xC001001Aul -#define TOP_MEM2 0xC001001Dul - -// CPU Build Configuration structures and definitions - -#define AMD_AP_MTRR_FIX64K_00000 0x00000250ul -#define AMD_AP_MTRR_FIX16K_80000 0x00000258ul -#define AMD_AP_MTRR_FIX16K_A0000 0x00000259ul -#define AMD_AP_MTRR_FIX4K_C0000 0x00000268ul -#define AMD_AP_MTRR_FIX4K_C8000 0x00000269ul -#define AMD_AP_MTRR_FIX4K_D0000 0x0000026Aul -#define AMD_AP_MTRR_FIX4K_D8000 0x0000026Bul -#define AMD_AP_MTRR_FIX4K_E0000 0x0000026Cul -#define AMD_AP_MTRR_FIX4K_E8000 0x0000026Dul -#define AMD_AP_MTRR_FIX4K_F0000 0x0000026Eul -#define AMD_AP_MTRR_FIX4K_F8000 0x0000026Ful -#define CPU_LIST_TERMINAL 0xFFFFFFFFul +#include // // Bitfield Description : Not shared between threads. @@ -113,17 +96,17 @@ PlatformSecLibStartup ( SYS_CFG_MTRR_FIX_DRAM_MOD_EN_OFFSET, 0x1 ); - AsmWriteMsr64 (AMD_AP_MTRR_FIX64K_00000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX16K_80000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX16K_A0000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_C0000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_C8000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_D0000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_D8000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_E0000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_E8000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_F0000, 0x1E1E1E1E1E1E1E1E); - AsmWriteMsr64 (AMD_AP_MTRR_FIX4K_F8000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX16k_A0000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E); + AsmWriteMsr64 (AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E); AsmMsrBitFieldAnd64 ( SYS_CFG, SYS_CFG_MTRR_FIX_DRAM_MOD_EN_OFFSET, diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf index 3b6e4b33f299a5305440e52bf9610f41deff7523..35c9a0dbf859c3e77bc01af028084f41d9e1f710 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf @@ -2,7 +2,7 @@ # Platform SEC Library. # # Copyright (c) 2013-2015 Intel Corporation. -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -31,6 +31,8 @@ Ia32/Flat32.nasm [Packages] + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec AmdMinBoardPkg/AmdMinBoardPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -53,7 +55,9 @@ gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase ## CONSUMES gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamBase ## CONSUMES gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamSize ## CONSUMES + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow ## CONSUMES + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi ## CONSUMES [Ppis] gEfiSecPlatformInformationPpiGuid ## UNDEFINED # it is used as GUIDED HOB - gAmdTopOfTemporaryRamPpiGuid + gTopOfTemporaryRamPpiGuid diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni index 6c68ed4f8b76fe8a42e761965646ce4450450b74..f18f6384ead45ea16d666a2d1ca0c2a65475a340 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni @@ -3,7 +3,7 @@ // PlatformSecLib Localized Abstract and Description Content // // Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.
-// Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +// Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. // SPDX-License-Identifier: BSD-2-Clause-Patent // // **/ diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/SecGetPerformance.c b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/SecGetPerformance.c index 09e9b5002b72117c565a311df62e2bc31e96b7ce..594653b3c065fa8696f20bfc323adb52544016b5 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/SecGetPerformance.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/PlatformSecLib/SecGetPerformance.c @@ -2,13 +2,14 @@ Sample to provide SecGetPerformance function. Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include #include +#include #include #include #include @@ -49,7 +50,7 @@ SecGetPerformance ( Status = (*PeiServices)->LocatePpi ( PeiServices, - &gAmdTopOfTemporaryRamPpiGuid, + &gTopOfTemporaryRamPpiGuid, 0, NULL, (VOID **)&TopOfTemporaryRamPpi diff --git a/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c index e7a503f6cff0ba059cfd870a5a23ca76d83df0d3..d1e3e5410e77aeb6247402f4a6fcbd23bbee89a2 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c @@ -3,7 +3,7 @@ SetCacheMtrr library functions. This library implementation is for AMD processor based platforms. -Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf index b4c4b3e7de1406e3ece95093fd5a5d4cb661a887..79895865460aa10a5e7c37533bd5bdeada0324e3 100644 --- a/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf @@ -2,7 +2,7 @@ # Component information file for Platform SetCacheMtrr Library. # This library implementation is for AMD processor based platforms. # -# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.c b/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.c index 0762f16fb360f3202936c1a32247574d41d570f3..20074612f646569caa1c1828fdf721db8782b781 100755 --- a/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.c +++ b/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.c @@ -3,7 +3,7 @@ Implements SpcrDeviceLib library functions. This library implementation is for AMD processor based platforms. -Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf index d9b77e586aa8af5e81f9a97a483d1f00f16d0e80..302bb8f219ce5b3b046b2aad8461cf2c494bd1d1 100755 --- a/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf +++ b/Platform/AMD/AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf @@ -2,7 +2,7 @@ # Implementation for SpcrDeviceLib Library. # SpcrDeviceLib is usd for Serial Port Console Redirection Table (SPCR) device. # -# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c b/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c index 9a7b509b5518c48e76f2ca5f15e24a17c0d8e2d4..f4a5ec957d4b2127cbec27698ddecade1ae24446 100755 --- a/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c +++ b/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c @@ -44,7 +44,7 @@ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
Copyright (C) 2016, Red Hat, Inc.
- Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf b/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf index 861fc120d9737821dd16ebc95463919d792b90d6..4cfafceb085f4175b0a06ef8ed57855bf3032d2f 100755 --- a/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf +++ b/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf @@ -2,7 +2,7 @@ # This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL. # Adds resource padding information, for PCIe hotplug purposes. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +# Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved # SPDX-License-Identifier: BSD-2-Clause-Patent ## diff --git a/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.ci.yaml b/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.ci.yaml deleted file mode 100644 index b6b25dc18500f40e48d4e6846f8f54835f8f37b2..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.ci.yaml +++ /dev/null @@ -1,139 +0,0 @@ -## @file -# CI configuration for AmdPlatformPkg -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. -# SPDX-License-Identifier: BSD-2-Clause-Patent -## -{ - "PrEval": { - "DscPath": "AmdPlatformPkg.dsc", - }, - ## options defined .pytool/Plugin/LicenseCheck - "LicenseCheck": { - "IgnoreFiles": [] - }, - "EccCheck": { - ## Exception sample looks like below: - ## "ExceptionList": [ - ## "", "" - ## ] - "ExceptionList": [ - ], - ## Both file path and directory path are accepted. - "IgnoreFiles": [ - ] - }, - ## options defined ci/Plugin/CompilerPlugin - "CompilerPlugin": { - "DscPath": "AmdPlatformPkg.dsc" - }, - ## options defined ci/Plugin/HostUnitTestCompilerPlugin - "HostUnitTestCompilerPlugin": { - "DscPath": "" - }, - - ## options defined ci/Plugin/CharEncodingCheck - "CharEncodingCheck": { - "IgnoreFiles": [] - }, - - ## options defined ci/Plugin/DependencyCheck - "DependencyCheck": { - "AcceptableDependencies": [ - "AgesaModulePkg/AgesaCommonModulePkg.dec", - "AgesaModulePkg/AgesaEdk2Pkg.dec", - "AgesaModulePkg/AgesaModuleFchPkg.dec", - "AgesaModulePkg/AgesaModuleNbioPkg.dec", - "AgesaModulePkg/AgesaModulePspPkg.dec", - "AgesaPkg/AgesaPkg.dec", - "AmdCpmPkg/AmdCpmPkg.dec", - "AmdMinBoardPkg/AmdMinBoardPkg.dec", - "AmdPlatformPkg/AmdPlatformPkg.dec", - "BoardModulePkg/BoardModulePkg.dec", - "DynamicTablesPkg/DynamicTablesPkg.dec", - "IpmiFeaturePkg/IpmiFeaturePkg.dec", - "MdeModulePkg/MdeModulePkg.dec", - "MdePkg/MdePkg.dec", - "MinPlatformPkg/MinPlatformPkg.dec", - "PcAtChipsetPkg/PcAtChipsetPkg.dec", - "SignedCapsulePkg/SignedCapsulePkg.dec", - "SecurityPkg/SecurityPkg.dec", - "UefiCpuPkg/UefiCpuPkg.dec", - "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec" - ], - # For host based unit tests - "AcceptableDependencies-HOST_APPLICATION":[ - "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec" - ], - # For UEFI shell based apps - "AcceptableDependencies-UEFI_APPLICATION":[], - "IgnoreInf": [] - }, - - ## options defined ci/Plugin/DscCompleteCheck - "DscCompleteCheck": { - "IgnoreInf": [ - ], - "DscPath": "AmdPlatformPkg.dsc" - }, - ## options defined ci/Plugin/HostUnitTestDscCompleteCheck - "HostUnitTestDscCompleteCheck": { - "IgnoreInf": [""], - ## "DscPath": "Test/AmdPlatformPkgHostTest.dsc" - }, - - ## options defined ci/Plugin/GuidCheck - "GuidCheck": { - "IgnoreGuidName": [], - "IgnoreGuidValue": [], - "IgnoreFoldersAndFiles": [], - "IgnoreDuplicates": [] - }, - - ## options defined ci/Plugin/LibraryClassCheck - "LibraryClassCheck": { - "IgnoreHeaderFile": [] - }, - - ## options defined ci/Plugin/SpellCheck - "SpellCheck": { - "AuditOnly": False, # If True, only audit the files, do not fail the build - "IgnoreStandardPaths": [ # Standard Plugin defined paths that should be ignore - ## "*.c", "*.asm", "*.h", "*.nasm", "*.s", "*.asl", "*.inf" - ], - "IgnoreFiles": [ # use gitignore syntax to ignore errors in matching files - ], - "ExtendWords": [ # words to extend to the dictionary for this package - "agesa", - "defaultdb", - "defaultdbx", - "deviceid", - "eisaid", - "flashid", - "iomux", - "jedec", - "oemid", - "pmioa", - "ppread", - "rdsfdp", - "smdbg", - "ssdtproc", - "eeprom", - "gpiox", - "agpio", - "sgpio", - "acpimmio", - "glink", - "ehci's", - "uhci's" - ], - "AdditionalIncludePaths": [] # Additional paths to spell check relative to package root (wildcards supported) - }, - "DebugMacroCheck": { - "StringSubstitutions": { - # Reason: Expansion of macro that contains a print specifier. - # AMD can write its own print specifier. - # "AMD_PRINT": "0x%lx" - } - } -} diff --git a/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dec b/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dec index 6be301fd77d3801e481ab5e992ff5132f5c7cdb7..9355e009280d15028f49a96ba4a0da251f0e559f 100644 --- a/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dec +++ b/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dec @@ -3,7 +3,7 @@ # This is the package provides the AMD edk2 common platform drivers # and libraries for AMD Server, Client and Gaming console platforms. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -31,9 +31,9 @@ [Protocols] gAmdSpiHcStateProtocolGuid = { 0x189566ab, 0x245, 0x43ae, {0x9d, 0x1, 0xd2, 0x21, 0x1c, 0xb9, 0x1a, 0xda }} - gFakeDeviceIoProtocolGuid = { 0x7fecf70, 0xd7ae, 0x4274, {0x9f, 0x70, 0x78, 0xc8, 0x36, 0x91, 0xd4, 0xfb }} - gEdk2EspiSmmDriverProtocolGuid = { 0x0ecc91df, 0xe165, 0x42ee, {0x82, 0xa7, 0x8d, 0x63, 0x98, 0x53, 0x6a, 0x31 }} - gAmdEspiSmmNorFlashProtocolGuid = { 0x6ef7b652, 0x84b7, 0x4d43, {0x9d, 0x88, 0x04, 0xb3, 0x0c, 0x49, 0xde, 0xd5 }} + gFakeDeviceIoProtocolGuid = {0x7fecf70, 0xd7ae, 0x4274, {0x9f, 0x70, 0x78, 0xc8, 0x36, 0x91, 0xd4, 0xfb}} + gEdk2EspiSmmDriverProtocolGuid = {0x0ecc91df, 0xe165, 0x42ee, {0x82, 0xa7, 0x8d, 0x63, 0x98, 0x53, 0x6a, 0x31}} + gAmdEspiSmmNorFlashProtocolGuid = {0x6ef7b652, 0x84b7, 0x4d43, {0x9d, 0x88, 0x04, 0xb3, 0x0c, 0x49, 0xde, 0xd5}} [PcdsDynamic] ## Event GUID to trigger logo displaying @@ -80,6 +80,22 @@ MdeModulePkg/MdeModulePkg.dec } + # + # SPI PCDs + # + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount|0xFFFFFFFF|UINT32|0x00020006 + + # + # eSPI PCDs + # + gAmdPlatformPkgTokenSpaceGuid.PcdAmdEspiOffset|0x10000|UINT32|0x00040003 + + # + # ROM selection PCDs + # + gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaBase|0x00000000|UINT64|0x00020007 + gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaSize|0x00000000|UINT64|0x00020008 + # # These PCDs are mapped to AMD SMBIOS type 9 record structure # @@ -95,6 +111,7 @@ gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.CardBusSupported|0 gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.ZoomVideoSupported|0 gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.ModemRingResumeSupported|0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2|{0x0}|MISC_SLOT_CHARACTERISTICS2|0x0002000A { IndustryStandard/SmBios.h @@ -106,18 +123,23 @@ gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.AsyncSurpriseRemoval|0 gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.FlexbusSlotCxl10Capable|0 gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.FlexbusSlotCxl20Capable|0 - gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.FlexbusSlotCxl30Capable|0 - - # - # SPI PCDs - # - gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount|0xFFFFFFFF|UINT32|0x00020006 - gAmdPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x0002000B - gAmdPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF000000|UINT32|0x10000001 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.Reserved|0 [PcdsDynamic, PcdsDynamicEx] + # SMBIOS gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|0|UINT8|0x00030001 gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|NULL|VOID*|0x00030002 gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|0|UINT8|0x00030003 gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|NULL|VOID*|0x00030004 + +[PcdsFeatureFlag] + ## ROM Armor PCDs + # Used to specify if the Rom Armor is enabled or not + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable|FALSE|BOOLEAN|0x00040000 + # pecify whether to enable ROM Armor white list for the SPI device. + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorWhitelistEnable|FALSE|BOOLEAN|0x00040001 + + # Used to specify if the driver should disable SPI Write Enable command + # outside of SMM. + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiWriteDisable|TRUE|BOOLEAN|0x00040002 diff --git a/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dsc b/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dsc index 60d77ec22ee0bb340b3b048918acbc965096c473..90b5d636cebe146cbbfebbf46ed78a433b6bc80f 100644 --- a/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dsc +++ b/Platform/AMD/AmdPlatformPkg/AmdPlatformPkg.dsc @@ -3,7 +3,7 @@ # This is the package provides the AMD edk2 common platform drivers # and libraries for AMD Server, Client and Gaming console platforms. # -# Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -23,10 +23,11 @@ !include MdePkg/MdeLibs.dsc.inc +# Include AGESA module for edk2-platforms +!include AgesaModulePkg/AgesaEdk2PlatformPkg.inc.dsc + [LibraryClasses.Common] - AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf AlwaysFalseDepexLib|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf - AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf @@ -35,21 +36,15 @@ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf - PciSegmentInfoLib|MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf + PlatformSocLib|AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf - StackCheckLib|MdePkg/Library/StackCheckLibNull/StackCheckLibNull.inf SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf @@ -62,42 +57,113 @@ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf !endif -[LibraryClasses.common.DXE_DRIVER] + AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf + AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf + AmdPspMboxLibV2|AgesaModulePkg/Library/AmdPspMboxLibV2/AmdPspMboxLibV2.inf + AmdPspBaseLibV2|AgesaModulePkg/Library/AmdPspBaseLibV2/AmdPspBaseLibV2.inf + AmdPspMmioLib|AgesaModulePkg/Library/AmdPspMmioLib/AmdPspMmioLib.inf + AmdPspRegBaseLib|AgesaModulePkg/Library/AmdPspRegBaseLib/AmdPspRegBaseLib.inf + AmdSocBaseLib|AgesaModulePkg/Library/AmdSocBaseLib/AmdSocBaseLib.inf + AmdHeapLib|AgesaModulePkg/Library/AmdHeapLibNull/AmdHeapLibNull.inf + AmdPspRegMuxLibV2|AgesaModulePkg/Library/AmdPspRegMuxLibV2Null/AmdPspRegMuxLibV2.inf + AmdDirectoryBaseLib|AgesaModulePkg/Library/AmdDirectoryBaseLib/AmdDirectoryBaseLib.inf + FchBaseLib|AgesaModulePkg/Library/FchBaseLib/FchBaseLib.inf + FchSpiAccessLib|AgesaModulePkg/Library/FchSpiAccessLib/FchSpiAccessRom2Lib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + AmlGenerationLib|AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf + SmnAccessLib|AgesaModulePkg/Library/SmnAccessLib/SmnAccessLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + + # Simulator serial port 80 + SerialPortLib|AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf + + # Boot logo + + NbioHandleLib|AgesaModulePkg/Library/NbioHandleLib/NbioHandleLib.inf + PcieConfigLib|AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf + +[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER] + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + AmdPspRomArmorLib|AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf + PlatformPspRomArmorWhitelistLib|AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf + +[LibraryClasses.Common.DXE_DRIVER] BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - PlatformSocLib|AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf - SpiHcPlatformLib|AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.inf - TableHelperLib|DynamicTablesPkg/Library/Common/TableHelperLib/TableHelperLib.inf -[LibraryClasses.common.SMM_CORE] - SmmCoreAmdSpiHcHookLib|AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf + AmdPspRomArmorLib|AgesaModulePkg/Library/AmdPspRomArmorLibNull/AmdPspRomArmorLibNull.inf + +[LibraryClasses.Common.SMM_CORE] SmmCorePlatformHookLib|AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf + SmmCoreAmdSpiHcHookHookLib|AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf -[LibraryClasses.common.DXE_SMM_DRIVER] - MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf - SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf - SpiHcPlatformLib|AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf +[Components.common.DXE_DRIVER] + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf # AMD SMBIOS common DXE driver [Components] - AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManagerDxe.inf - AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.inf - AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.inf - AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.inf - AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SamplecmPlatOverrideLib.inf AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf - AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf - AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf - AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf - AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf + AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf AmdPlatformPkg/Universal/LogoDxe/JpegLogoDxe.inf # Server platform JPEG logo driver AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf # Server platfrom Bitmap logo driver AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf - AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf - AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf + + AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf + AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf + AgesaModulePkg/Nbio/Library/CommonDxe/NbioCommonDxeLib.inf + AgesaModulePkg/Library/PcieConfigLib/PcieConfigLib.inf + +[Components.X64] + AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.inf + AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.inf + AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.inf + AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.inf AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf - AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.inf - AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.inf + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + MSFT:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + + GCC:*_*_*_CC_FLAGS = -D USE_EDKII_HEADER_FILE + + # Turn off DEBUG messages for Release Builds + GCC:RELEASE_*_*_CC_FLAGS = -D MDEPKG_NDEBUG + INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + + !ifdef $(INTERNAL_IDS) + GCC:*_*_*_CC_FLAGS = -DINTERNAL_IDS + INTEL:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_VFRPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLCC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_PP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_APP_FLAGS = /D INTERNAL_IDS + !endif diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Hpet.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Hpet.c deleted file mode 100644 index f583094d4899b808f0ae83a90c8f12972b04d796..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Hpet.c +++ /dev/null @@ -1,64 +0,0 @@ -/** @file - This file implements the ACPI table updates for the Configuration Manager DXE driver. - - It includes functions to update the HPET table information in the Platform Repository. - - Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ -#include "../ConfigurationManager.h" -#include -#include - -/** - Update HPET table information in Platform Repository. - - @param[in] PlatformRepo The pointer to the Platform Repository. - - @retval EFI_SUCCESS The HPET table information is updated successfully. - @retval EFI_INVALID_PARAMETER The input parameter is NULL. -**/ -EFI_STATUS -EFIAPI -UpdateHpetTableInfo ( - IN EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo - ) -{ - UINT64 HpetCapabilities; - UINTN Index; - UINTN TableIndex; - - if (PlatformRepo == NULL) { - return EFI_INVALID_PARAMETER; - } - - HpetCapabilities = MmioRead64 (PlatformRepo->HpetInfo.BaseAddressLower32Bit); - if ((HpetCapabilities == 0) || (HpetCapabilities == MAX_UINT64)) { - for (Index = 0; Index < PlatformRepo->CurrentAcpiTableCount; Index++) { - if (PlatformRepo->CmAcpiTableList[Index].TableGeneratorId == CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdHpet)) { - for (TableIndex = Index; TableIndex < PlatformRepo->CurrentAcpiTableCount - 1; TableIndex++) { - CopyMem (&PlatformRepo->CmAcpiTableList[TableIndex], &PlatformRepo->CmAcpiTableList[TableIndex + 1], sizeof (CM_STD_OBJ_ACPI_TABLE_INFO)); - } - - ZeroMem (&PlatformRepo->CmAcpiTableList[PlatformRepo->CurrentAcpiTableCount - 1], sizeof (CM_STD_OBJ_ACPI_TABLE_INFO)); - PlatformRepo->CurrentAcpiTableCount--; - break; - } - } - - for (Index = 0; Index < PlatformRepo->CurrentAcpiTableCount; Index++) { - if (PlatformRepo->CmAcpiTableList[Index].TableGeneratorId == CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtHpet)) { - for (TableIndex = Index; TableIndex < PlatformRepo->CurrentAcpiTableCount - 1; TableIndex++) { - CopyMem (&PlatformRepo->CmAcpiTableList[TableIndex], &PlatformRepo->CmAcpiTableList[TableIndex + 1], sizeof (CM_STD_OBJ_ACPI_TABLE_INFO)); - } - - ZeroMem (&PlatformRepo->CmAcpiTableList[PlatformRepo->CurrentAcpiTableCount - 1], sizeof (CM_STD_OBJ_ACPI_TABLE_INFO)); - PlatformRepo->CurrentAcpiTableCount--; - break; - } - } - } - - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Madt.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Madt.c deleted file mode 100755 index 7ffc2c8330c925ac4f45ce26aaa82df15e164da9..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Madt.c +++ /dev/null @@ -1,372 +0,0 @@ -/** @file - Collects the information required to update the MADT table. - - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ConfigurationManager.h" - -UINT32 mMadtCcdOrder[16] = { 0, 4, 8, 12, 2, 6, 10, 14, 3, 7, 11, 15, 1, 5, 9, 13 }; - -/** - Callback compare function. - Compares CCD number of provided arguments. - - @param[in] ProcessorInfoLeft Pointer to Left Buffer. - @param[in] ProcessorInfoRight Pointer to Right Buffer. - @return 0 If both are same - -1 If left value is less than righ value. - 1 If left value is greater than righ value. - -**/ -INTN -EFIAPI -MadtSortByCcd ( - CONST VOID *ProcessorInfoLeft, - CONST VOID *ProcessorInfoRight - ) -{ - CONST EFI_PROCESSOR_INFORMATION *Left; - CONST EFI_PROCESSOR_INFORMATION *Right; - UINT32 Index; - UINT32 LeftCcdIndex; - UINT32 RightCcdIndex; - - Left = (EFI_PROCESSOR_INFORMATION *)ProcessorInfoLeft; - Right = (EFI_PROCESSOR_INFORMATION *)ProcessorInfoRight; - - // Get the CCD Index number - LeftCcdIndex = MAX_UINT32; - for (Index = 0; Index < ARRAY_SIZE (mMadtCcdOrder); Index++) { - if (Left->ExtendedInformation.Location2.Die == mMadtCcdOrder[Index]) { - LeftCcdIndex = Index; - break; - } - } - - RightCcdIndex = MAX_UINT32; - for (Index = 0; Index < ARRAY_SIZE (mMadtCcdOrder); Index++) { - if (Right->ExtendedInformation.Location2.Die == mMadtCcdOrder[Index]) { - RightCcdIndex = Index; - break; - } - } - - // Now compare for quick sort - if (LeftCcdIndex < RightCcdIndex) { - return -1; - } - - if (LeftCcdIndex > RightCcdIndex) { - return 1; - } - - return 0; -} - -/** The UpdateMadtTable function updates the MADT table. - - @param [in, out] PlatformRepo Pointer to the platform repository information. - - @retval EFI_SUCCESS The MADT table is updated successfully. - @retval EFI_INVALID_PARAMETER The input parameter is invalid. -**/ -EFI_STATUS -EFIAPI -UpdateMadtTable ( - IN OUT EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo - ) -{ - EFI_STATUS Status; - EFI_MP_SERVICES_PROTOCOL *MpService; - UINTN NumberOfProcessors; - UINTN NumberOfEnabledProcessors; - UINT32 Index; - EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer; - UINTN NumSocket; - UINTN ThreadsPerCore; - UINTN Socket; - CM_X64_LOCAL_APIC_X2APIC_INFO *LocalApicInfo; - CM_X64_LOCAL_APIC_X2APIC_INFO *TempLocalApicInfo; - CM_X64_LOCAL_APIC_X2APIC_INFO *SrcLocalApicInfo; - CM_X64_LOCAL_APIC_X2APIC_INFO *DstLocalApicInfo; - UINT8 ApicMode; - CM_X64_IO_APIC_INFO *CmIoApicInfo; - EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApicInfo; - UINTN IoApicCount; - CM_X64_INTR_SOURCE_OVERRIDE_INFO *IntrSourceOverrideInfo; - UINTN IntrSourceOverrideCount; - CM_X64_LOCAL_APIC_X2APIC_NMI_INFO *LocalApicNmiInfo; - UINTN LocalApicNmiCount; - - if (PlatformRepo == NULL) { - return EFI_INVALID_PARAMETER; - } - - ApicMode = (UINT8)GetApicMode (); - PlatformRepo->MadtInfo.LocalApicAddress = PcdGet32 (PcdCpuLocalApicBaseAddress); - PlatformRepo->MadtInfo.Flags = EFI_ACPI_6_5_PCAT_COMPAT; - PlatformRepo->MadtInfo.ApicMode = ApicMode; - - Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpService); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a:%d Failed to locate MP Services Protocol. Status(%r)\n", - __func__, - __LINE__, - Status - )); - ASSERT_EFI_ERROR (Status); - return Status; - } - - Status = MpService->GetNumberOfProcessors ( - MpService, - &NumberOfProcessors, - &NumberOfEnabledProcessors - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a:%d Failed to get number of processors. Status(%r)\n", - __func__, - __LINE__, - Status - )); - ASSERT_EFI_ERROR (Status); - return Status; - } - - ProcessorInfoBuffer = AllocateZeroPool (NumberOfProcessors * sizeof (EFI_PROCESSOR_INFORMATION)); - if (ProcessorInfoBuffer == NULL) { - DEBUG (( - DEBUG_ERROR, - "%a:%d Failed to allocate memory for Processor Information Buffer. Status(%r)\n", - __func__, - __LINE__, - Status - )); - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - return EFI_OUT_OF_RESOURCES; - } - - /// Get ProcessorInfoBuffer - NumSocket = 0; - ThreadsPerCore = 0; - for (Index = 0; Index < NumberOfProcessors; Index++) { - Status = MpService->GetProcessorInfo ( - MpService, - Index|CPU_V2_EXTENDED_TOPOLOGY, - &ProcessorInfoBuffer[Index] - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a:%d Failed to get Processor Information. Status(%r)\n", - __func__, - __LINE__, - Status - )); - ASSERT_EFI_ERROR (Status); - FreePool (ProcessorInfoBuffer); - return Status; - } - - if (ProcessorInfoBuffer[Index].ExtendedInformation.Location2.Package > NumSocket) { - NumSocket = ProcessorInfoBuffer[Index].ExtendedInformation.Location2.Package; - } - - if (ProcessorInfoBuffer[Index].ExtendedInformation.Location2.Thread > ThreadsPerCore) { - ThreadsPerCore = ProcessorInfoBuffer[Index].ExtendedInformation.Location2.Thread; - } - } - - /// Increment the NumSocket and ThreadsPerCore by 1, as it is 0 based - NumSocket++; - ThreadsPerCore++; - - /// Sort by CCD location - if (NumSocket > 1) { - PerformQuickSort ( - ProcessorInfoBuffer, - NumberOfProcessors/2, - sizeof (EFI_PROCESSOR_INFORMATION), - MadtSortByCcd - ); - PerformQuickSort ( - ProcessorInfoBuffer+(NumberOfProcessors/2), - NumberOfProcessors/2, - sizeof (EFI_PROCESSOR_INFORMATION), - MadtSortByCcd - ); - } else { - PerformQuickSort ( - ProcessorInfoBuffer, - NumberOfProcessors, - sizeof (EFI_PROCESSOR_INFORMATION), - MadtSortByCcd - ); - } - - LocalApicInfo = AllocateZeroPool (sizeof (CM_X64_LOCAL_APIC_X2APIC_INFO) * NumberOfProcessors); - if (LocalApicInfo == NULL) { - FreePool (ProcessorInfoBuffer); - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - return EFI_OUT_OF_RESOURCES; - } - - for (Socket = 0; Socket < NumSocket; Socket++) { - for (Index = 0; Index < NumberOfProcessors; Index++) { - if (ProcessorInfoBuffer[Index].ProcessorId > MAX_UINT32) { - DEBUG ((DEBUG_ERROR, "%a:%d ProcessorId is greater than MAX_UINT32\n", __func__, __LINE__)); - FreePool (ProcessorInfoBuffer); - ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); - return EFI_INVALID_PARAMETER; - } - - LocalApicInfo[Index].ApicId = (UINT32)ProcessorInfoBuffer[Index].ProcessorId; - if ((ProcessorInfoBuffer[Index].StatusFlag & PROCESSOR_ENABLED_BIT) != 0) { - LocalApicInfo[Index].Flags = 1; - } - - LocalApicInfo[Index].AcpiProcessorUid = Index; - } - } - - FreePool (ProcessorInfoBuffer); - - /// Now separate the first thread list - TempLocalApicInfo = NULL; - if (ThreadsPerCore > 1) { - TempLocalApicInfo = AllocateCopyPool ((sizeof (CM_X64_LOCAL_APIC_X2APIC_INFO) * NumberOfProcessors), (const void *)LocalApicInfo); - if (TempLocalApicInfo == NULL) { - FreePool (LocalApicInfo); - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - return EFI_OUT_OF_RESOURCES; - } - - SrcLocalApicInfo = TempLocalApicInfo; - DstLocalApicInfo = LocalApicInfo; - for (Index = 0; Index < NumberOfProcessors; Index++) { - if ((SrcLocalApicInfo->ApicId & 0x1) == 0) { - CopyMem (DstLocalApicInfo, SrcLocalApicInfo, sizeof (CM_X64_LOCAL_APIC_X2APIC_INFO)); - SrcLocalApicInfo++; - DstLocalApicInfo++; - } else { - SrcLocalApicInfo++; - } - } - - SrcLocalApicInfo = TempLocalApicInfo; - for (Index = 0; Index < NumberOfProcessors; Index++) { - if ((SrcLocalApicInfo->ApicId & 0x1) == 1) { - CopyMem (DstLocalApicInfo, SrcLocalApicInfo, sizeof (CM_X64_LOCAL_APIC_X2APIC_INFO)); - SrcLocalApicInfo++; - DstLocalApicInfo++; - } else { - SrcLocalApicInfo++; - } - } - } - - if (TempLocalApicInfo != NULL) { - FreePool (TempLocalApicInfo); - } - - /// Now copy the LocalApicInfo to PlatformRepo - PlatformRepo->LocalApicX2ApicInfoCount = NumberOfProcessors; - PlatformRepo->LocalApicX2ApicInfo = LocalApicInfo; - - /// Get the IO APIC Information - - IoApicInfo = NULL; - IoApicCount = 0; - Status = GetIoApicInfo (&IoApicInfo, (UINT8 *)&IoApicCount); - if ((EFI_ERROR (Status) || (IoApicInfo == NULL) || (IoApicCount == 0))) { - DEBUG (( - DEBUG_ERROR, - "%a:%d GetIoApicInfo() failed. Status (%r).\n", - __func__, - __LINE__, - Status - )); - return Status; - } - - CmIoApicInfo = NULL; - CmIoApicInfo = AllocateZeroPool (sizeof (CM_X64_IO_APIC_INFO) * IoApicCount); - if (CmIoApicInfo == NULL) { - FreePool (IoApicInfo); - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - return EFI_OUT_OF_RESOURCES; - } - - /// Copy the IO APIC Information - for (Index = 0; Index < IoApicCount; Index++) { - CmIoApicInfo[Index].IoApicId = IoApicInfo[Index].IoApicId; - CmIoApicInfo[Index].IoApicAddress = IoApicInfo[Index].IoApicAddress; - CmIoApicInfo[Index].GlobalSystemInterruptBase = IoApicInfo[Index].GlobalSystemInterruptBase; - } - - FreePool (IoApicInfo); - - PlatformRepo->IoApicInfoCount = IoApicCount; - PlatformRepo->IoApicInfo = CmIoApicInfo; - - /// Get the Interrupt Source Override Information - IntrSourceOverrideCount = 2; - IntrSourceOverrideInfo = AllocateZeroPool (sizeof (CM_X64_INTR_SOURCE_OVERRIDE_INFO) * IntrSourceOverrideCount); - if (IntrSourceOverrideInfo == NULL) { - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - return EFI_OUT_OF_RESOURCES; - } - - IntrSourceOverrideInfo[0].Bus = 0x0; - IntrSourceOverrideInfo[0].Source = 0x0; - IntrSourceOverrideInfo[0].GlobalSystemInterrupt = 0x2; - IntrSourceOverrideInfo[0].Flags = 0xF; - - IntrSourceOverrideInfo[1].Bus = 0x0; - IntrSourceOverrideInfo[1].Source = 0x9; - IntrSourceOverrideInfo[1].GlobalSystemInterrupt = 0x9; - IntrSourceOverrideInfo[1].Flags = 0xF; - - PlatformRepo->IntrSourceOverrideInfoCount = IntrSourceOverrideCount; - PlatformRepo->IntrSourceOverrideInfo = IntrSourceOverrideInfo; - - /// Get the Local APIC NMI Information - LocalApicNmiCount = 1; - LocalApicNmiInfo = AllocateZeroPool (sizeof (CM_X64_LOCAL_APIC_X2APIC_NMI_INFO) * LocalApicNmiCount); - if (LocalApicNmiInfo == NULL) { - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - return EFI_OUT_OF_RESOURCES; - } - - LocalApicNmiInfo[0].Flags = 0x5; - if (ApicMode == LOCAL_APIC_MODE_X2APIC) { - LocalApicNmiInfo[0].AcpiProcessorUid = MAX_UINT32; - } else { - LocalApicNmiInfo[0].AcpiProcessorUid = MAX_UINT8; - } - - LocalApicNmiInfo[0].LocalApicLint = 0x1; - - /// update the PlatformRepo - PlatformRepo->LocalApicX2ApicNmiInfoCount = LocalApicNmiCount; - PlatformRepo->LocalApicX2ApicNmiInfo = LocalApicNmiInfo; - - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Mcfg.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Mcfg.c deleted file mode 100644 index 572dc7b12347247b39b51cf5c988d55669b0c1bd..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/Acpi/Mcfg.c +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - This file contains the implementation of the MCFG table initialization for the - Configuration Manager DXE driver. - - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include -#include -#include "../ConfigurationManager.h" - -/** Updates ACPI MCFG table information in the platform repository. - - @param [in] PlatformRepo Pointer to the platform repository. - - @retval EFI_SUCCESS The ACPI MCFG table information is updated. - @retval EFI_INVALID_PARAMETER The input parameter is invalid. - @retval EFI_NOT_FOUND The PCI segment information is not found. -**/ -EFI_STATUS -EFIAPI -UpdateMcfgTableInfo ( - IN EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo - ) -{ - PCI_SEGMENT_INFO *PciSegmentInfo; - CM_ARCH_COMMON_PCI_CONFIG_SPACE_INFO *PciConfigSpaceInfo; - UINTN PciSegmentCount; - UINTN Index; - - if (PlatformRepo == NULL) { - return EFI_INVALID_PARAMETER; - } - - PciSegmentInfo = NULL; - PciSegmentCount = 0; - PciSegmentInfo = GetPciSegmentInfo (&PciSegmentCount); - if ((PciSegmentInfo == NULL) || (PciSegmentCount == 0)) { - return EFI_NOT_FOUND; - } - - PciConfigSpaceInfo = AllocateZeroPool (sizeof (CM_ARCH_COMMON_PCI_CONFIG_SPACE_INFO) * PciSegmentCount); - if (PciConfigSpaceInfo == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - for (Index = 0; Index < PciSegmentCount; Index++) { - PciConfigSpaceInfo[Index].BaseAddress = PciSegmentInfo[Index].BaseAddress; - PciConfigSpaceInfo[Index].PciSegmentGroupNumber = PciSegmentInfo[Index].SegmentNumber; - PciConfigSpaceInfo[Index].StartBusNumber = PciSegmentInfo[Index].StartBusNumber; - PciConfigSpaceInfo[Index].EndBusNumber = PciSegmentInfo[Index].EndBusNumber; - } - - PlatformRepo->PciConfigSpaceInfoCount = PciSegmentCount; - PlatformRepo->PciConfigSpaceInfo = PciConfigSpaceInfo; - - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManager.c deleted file mode 100755 index 724645bb0af6f3699c1cffad0e1f35a387db2386..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManager.c +++ /dev/null @@ -1,277 +0,0 @@ -/** @file - Configuration Manager Protocol implementation for AMD platform. - This file implements the Configuration Manager Protocol for the AMD platform. - The Configuration Manager Protocol is used to provide the Configuration - Objects to the Configuration Manager. - - Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include -#include -#include -#include -#include "ConfigurationManager.h" - -/** The platform configuration repository information. -*/ -STATIC -EDKII_PLATFORM_REPOSITORY_INFO mAmdPlatformRepositoryInfo = { - /// Configuration Manager Information - { - CONFIGURATION_MANAGER_REVISION, - CFG_MGR_OEM_ID - }, - /// ACPI Table List - { - /// FACS Table - { - EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, - EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFacs), - NULL - }, - /// FADT Table - { - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), - NULL - }, - /// HPET Table - { - EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, - EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdHpet), - NULL - }, - /// HPET Ssdt Table - { - EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, - 0, // Unused - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtHpet), - NULL - }, - /// WSMT Table - { - EFI_ACPI_6_3_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE, - EFI_WSMT_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdWsmt), - NULL - }, - /// SPMI Table - { - EFI_ACPI_6_5_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE, - EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_5_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpmi), - NULL - }, - /// MCFG Table - { - EFI_ACPI_6_5_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg), - NULL - }, - /// MADT Table - { - EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), - NULL - }, - /// SRAT Table - { - EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, - EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, - CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSrat), - NULL - } - }, - /// Current ACPI Table Count - PLAT_ACPI_TABLE_COUNT, - /// FACS info - { - 0, - 0, - 0, - 0 - }, - /// PmProfile - { - EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER - }, - /// HypervisorVendorId - { - 0x00000000 - }, - /// FixedFeatureFlags - { - EFI_ACPI_6_5_WBINVD | \ - EFI_ACPI_6_5_PROC_C1 | \ - EFI_ACPI_6_5_P_LVL2_UP | \ - EFI_ACPI_6_5_SLP_BUTTON | \ - EFI_ACPI_6_5_TMR_VAL_EXT | \ - EFI_ACPI_6_5_RESET_REG_SUP | \ - EFI_ACPI_6_5_REMOTE_POWER_ON_CAPABLE - }, - /// SciInterrupt - { - 0x0009 - }, - /// SciCmdinfo - { - 0x000000B2, - 0xA0, - 0xA1, - 0x00, - 0x00, - 0x00 - }, - /// PmBlockInfo - { - 0x00000800, - 0x00000000, - 0x00000804, - 0x00000000, - 0x00000000, - 0x00000808, - 0x04, - 0x02, - 0x00, - 0x04 - }, - /// GPE block - { - 0x00000820, - 0x00000000, - 0x08, - 0x00, - 0x00 - }, - /// X PM Event - { - { EFI_ACPI_6_5_SYSTEM_IO, 0x20, 0x0, EFI_ACPI_6_5_WORD, 0x0000000000000800 }, - { 0x0, 0x0, 0x0, 0x0, 0x0000000000000000 }, - { EFI_ACPI_6_5_SYSTEM_IO, 0x10, 0x0, EFI_ACPI_6_5_WORD, 0x0000000000000804 }, - { 0x0, 0x0, 0x0, 0x0, 0x0000000000000000 }, - { 0x0, 0x0, 0x0, 0x0, 0x0000000000000000 }, - { EFI_ACPI_6_5_SYSTEM_IO, 0x20, 0x0, EFI_ACPI_6_5_DWORD, 0x0000000000000808 } - }, - /// X GPE Event - { - { EFI_ACPI_6_5_SYSTEM_IO, 0x40, 0x0, EFI_ACPI_6_5_BYTE, 0x0000000000000820 }, - { 0x0, 0x0, 0x0, 0x0, 0x0000000000000000 } - }, - /// Sleep Event - { - { 0x0, 0x0, 0x0, 0x0, 0x0 }, - { 0x0, 0x0, 0x0, 0x0, 0x0 } - }, - /// Reset Event - { - { EFI_ACPI_6_5_SYSTEM_IO, 0x8, 0x0, EFI_ACPI_6_5_UNDEFINED, 0x0000000000000CF9 }, - 0x06 - }, - /// FadtMiscInfo - { - 0x0064, - 0x03E9, - 0x0400, - 0x0010, - 0x01, - 0x03, - 0x0D, - 0x00, - 0x32 - }, - /// HpetInfo - { - FixedPcdGet64 (PcdHpetBaseAddress), - 0x37EE, - 0x0 - }, - /// Wsmt flags info - { - EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS | \ - EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION | \ - EFI_WSMT_PROTECTION_FLAGS_SYSTEM_RESOURCE_PROTECTION - }, - /// SpmiInterruptInfo - { - 0x01, - { EFI_ACPI_6_5_SYSTEM_IO, 0x8, 0, 0, 0x0000000000000CA2 } - } -}; - -/** A structure describing the configuration manager protocol interface. -*/ -STATIC -EDKII_CONFIGURATION_MANAGER_PROTOCOL mAmdPlatformConfigManagerProtocol = { - CREATE_REVISION (1, 0), - AmdPlatformGetObject, - AmdPlatformSetObject, - &mAmdPlatformRepositoryInfo -}; - -/** - Entrypoint of Configuration Manager Dxe. - - @param [in] ImageHandle - @param [in] SystemTable - - @return EFI_SUCCESS - @return EFI_LOAD_ERROR - @return EFI_OUT_OF_RESOURCES -**/ -EFI_STATUS -EFIAPI -ConfigurationManagerDxeInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - UINTN Index; - - Status = UpdateMcfgTableInfo (&mAmdPlatformRepositoryInfo); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "ERROR: Failed to update MCFG table info. Status = %r\n", Status)); - return Status; - } - - /// set the OemTableId and OemRevision for the CmACpiTableList - for (Index = 0; Index < mAmdPlatformRepositoryInfo.CurrentAcpiTableCount; Index++) { - mAmdPlatformRepositoryInfo.CmAcpiTableList[Index].OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId); - mAmdPlatformRepositoryInfo.CmAcpiTableList[Index].OemRevision = PcdGet32 (PcdAcpiDefaultOemRevision); - } - - UpdateMadtTable (&mAmdPlatformRepositoryInfo); - Status = UpdateHpetTableInfo (&mAmdPlatformRepositoryInfo); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "ERROR: Failed to update HPET table info. Status = %r\n", Status)); - return Status; - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gEdkiiConfigurationManagerProtocolGuid, - EFI_NATIVE_INTERFACE, - (VOID *)&mAmdPlatformConfigManagerProtocol - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "ERROR: Failed to get Install Configuration Manager Protocol." \ - " Status = %r\n", - Status - )); - } - - return Status; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManager.h deleted file mode 100755 index cb86efa5b900235fa33bcfc11b3e0abba7376c89..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManager.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file - - Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent - - @par Glossary: - - Cm or CM - Configuration Manager - - Obj or OBJ - Object -**/ - -#ifndef CONFIGURATION_MANAGER_H_ -#define CONFIGURATION_MANAGER_H_ - -#include -#include -#include -#include -#include -#include - -/** The SetObject function defines the interface implemented by the - Configuration Manager Protocol for updating the Configuration - Manager Objects. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in] CmObject Pointer to the Configuration Manager Object - descriptor describing the Object. - - @retval EFI_UNSUPPORTED This operation is not supported. -**/ -EFI_STATUS -EFIAPI -AmdPlatformSetObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN CM_OBJ_DESCRIPTOR *CONST CmObject - ); - -/** The GetObject function defines the interface implemented by the - Configuration Manager Protocol for returning the Configuration - Manager Objects. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in, out] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -AmdPlatformGetObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject - ); - -/** Updates ACPI MCFG table information in the platform repository. - - @param [in] PlatformRepo Pointer to the platform repository. - - @retval EFI_SUCCESS The ACPI MCFG table information is updated. - @retval EFI_INVALID_PARAMETER The input parameter is invalid. - @retval EFI_UNSUPPORTED The operation is not supported. -**/ -EFI_STATUS -EFIAPI -UpdateMcfgTableInfo ( - IN EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo - ); - -/** The UpdateMadtTable function updates the MADT table. - - @param [in, out] PlatformRepo Pointer to the platform repository information. - - @retval EFI_SUCCESS The MADT table is updated successfully. - @retval EFI_INVALID_PARAMETER The input parameter is invalid. -**/ -EFI_STATUS -EFIAPI -UpdateMadtTable ( - IN OUT EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo - ); - -/** - Update HPET table information in Platform Repository. - - @param[in] PlatformRepo The pointer to the Platform Repository. - - @retval EFI_SUCCESS The HPET table information is updated successfully. - @retval EFI_INVALID_PARAMETER The input parameter is NULL. -**/ -EFI_STATUS -EFIAPI -UpdateHpetTableInfo ( - IN EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo - ); - -#endif // CONFIGURATION_MANAGER_H_ diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManagerDxe.inf deleted file mode 100755 index 341c460ef6cf396877efd2ae3f7cf150fcc74209..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +++ /dev/null @@ -1,65 +0,0 @@ -## @file -# AMD platform configuration manager Dxe driver. -# -# Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 1.30 - BASE_NAME = ConfigurationManagerDxe - FILE_GUID = C0400631-702B-4E7D-9CC1-38F0BD021F5D - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = ConfigurationManagerDxeInitialize - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = X64 -# - -[Sources] - Acpi/Hpet.c - Acpi/Madt.c - Acpi/Mcfg.c - ConfigurationManager.c - ConfigurationManager.h - NameSpaceObject.c - -[Packages] - AmdPlatformPkg/AmdPlatformPkg.dec - DynamicTablesPkg/DynamicTablesPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec - PcAtChipsetPkg/PcAtChipsetPkg.dec - -[LibraryClasses] - BaseMemoryLib - DebugLib - LocalApicLib - MemoryAllocationLib - IoLib - PciSegmentInfoLib - PlatformSocLib - PrintLib - SortLib - UefiBootServicesTableLib - UefiDriverEntryPoint - UefiRuntimeServicesTableLib - -[Protocols] - gEdkiiConfigurationManagerProtocolGuid - gEfiMpServiceProtocolGuid - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId - gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress - gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress - -[Depex] - TRUE diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/NameSpaceObject.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/NameSpaceObject.c deleted file mode 100644 index 2efdc24f4e113872ca73ee8d7e274044e9986ad0..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/ConfigurationManagerDxe/NameSpaceObject.c +++ /dev/null @@ -1,1028 +0,0 @@ -/** @file - This file implements the Get/Set function for the Configuration Manager. - - Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ -#include -#include -#include -#include -#include -#include "ConfigurationManager.h" - -/** A helper function for returning the Configuration Manager Objects. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Object Pointer to the Object(s). - @param [in] ObjectSize Total size of the Object(s). - @param [in] ObjectCount Number of Objects. - @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object - descriptor describing the requested Object. - @retval EFI_SUCCESS Success. -**/ -STATIC -EFI_STATUS -EFIAPI -HandleCmObject ( - IN CONST CM_OBJECT_ID CmObjectId, - IN VOID *Object, - IN CONST UINTN ObjectSize, - IN CONST UINTN ObjectCount, - IN OUT CM_OBJ_DESCRIPTOR *CONST CmObjectDesc - ) -{ - if ((ObjectSize > MAX_UINT32) || (ObjectCount > MAX_UINT32)) { - return EFI_INVALID_PARAMETER; - } - - if (Object == NULL) { - return EFI_INVALID_PARAMETER; - } - - CmObjectDesc->ObjectId = CmObjectId; - CmObjectDesc->Size = (UINT32)ObjectSize; - CmObjectDesc->Data = (VOID *)Object; - CmObjectDesc->Count = (UINT32)ObjectCount; - DEBUG (( - DEBUG_INFO, - "INFO: CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n", - CmObjectId, - CmObjectDesc->Data, - CmObjectDesc->Size, - CmObjectDesc->Count - )); - return EFI_SUCCESS; -} - -/** A helper function for setting the Configuration Manager Objects. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [out] Object Pointer to the Object(s). - @param [in] ObjectSize Total size of the Object(s). - @param [in] ObjectCount Number of Objects. - @param [in] CmObjectDesc Pointer to the Configuration Manager Object - descriptor describing the requested Object. - @retval EFI_SUCCESS Success. -**/ -STATIC -EFI_STATUS -EFIAPI -SetHandleCmObject ( - IN CONST CM_OBJECT_ID CmObjectId, - OUT VOID *Object, - IN CONST UINTN ObjectSize, - IN CONST UINTN ObjectCount, - IN CM_OBJ_DESCRIPTOR *CONST CmObjectDesc - ) -{ - DEBUG (( - DEBUG_INFO, - "INFO: Received CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n", - CmObjectId, - CmObjectDesc->Data, - CmObjectDesc->Size, - CmObjectDesc->Count - )); - if ((CmObjectDesc->Size != ObjectSize) || (CmObjectDesc->Count != ObjectCount)) { - return EFI_BAD_BUFFER_SIZE; - } - - CopyMem (Object, CmObjectDesc->Data, (ObjectSize * ObjectCount)); - - return EFI_SUCCESS; -} - -/** A helper function for setting the Configuration Manager Objects. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [out] Object Pointer to the Object(s). - @param [in] ObjectSize Total size of the Object(s). - @param [in] ObjectCount Number of Objects. - @param [in] CmObjectDesc Pointer to the Configuration Manager Object - descriptor describing the requested Object. - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_BAD_BUFFER_SIZE The buffer size is invalid. - @retval EFI_OUT_OF_RESOURCES The buffer allocation failed. - @retval EFI_BUFFER_TOO_SMALL The buffer is too small. -**/ -STATIC -EFI_STATUS -EFIAPI -SetHandleCmObjectBuffer ( - IN CM_OBJECT_ID CmObjectId, - OUT VOID **Object, - IN CONST UINTN ObjectSize, - IN UINTN *ObjectCount, - IN CM_OBJ_DESCRIPTOR *CONST CmObjectDesc - ) -{ - EFI_STATUS Status; - VOID *Buffer; - - if ((Object == NULL) || - (*Object == NULL) || - (ObjectCount == NULL) || - (CmObjectDesc == NULL) - ) - { - return EFI_INVALID_PARAMETER; - } - - if (*ObjectCount == 0) { - return EFI_BUFFER_TOO_SMALL; - } - - if (CmObjectDesc->Count != *ObjectCount) { - Buffer = AllocateZeroPool (CmObjectDesc->Size * CmObjectDesc->Count); - if (Buffer == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - *ObjectCount = CmObjectDesc->Count; - } else { - Buffer = *Object; - } - - Status = SetHandleCmObject (CmObjectId, Buffer, CmObjectDesc->Size, *ObjectCount, CmObjectDesc); - if ((!EFI_ERROR (Status)) && (Buffer != *Object)) { - FreePool (*Object); - *Object = Buffer; - } - - return Status; -} - -/** Return a standard namespace object. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in, out] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -GetStandardNameSpaceObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - - switch (GET_CM_OBJECT_ID (CmObjectId)) { - case EStdObjCfgMgrInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->CmInfo, - sizeof (PlatformRepo->CmInfo), - 1, - CmObject - ); - break; - case EStdObjAcpiTableList: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->CmAcpiTableList, - sizeof (CM_STD_OBJ_ACPI_TABLE_INFO) * PlatformRepo->CurrentAcpiTableCount, - PlatformRepo->CurrentAcpiTableCount, - CmObject - ); - break; - default: - { - Status = EFI_NOT_FOUND; - DEBUG (( - DEBUG_ERROR, - "ERROR: Object 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} - -/** Return an architecture namespace object. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in, out] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -GetArchNameSpaceObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - - switch (GET_CM_OBJECT_ID (CmObjectId)) { - case EArchCommonObjPowerManagementProfileInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->PowerManagementProfile, - sizeof (PlatformRepo->PowerManagementProfile), - 1, - CmObject - ); - break; - - case EArchCommonObjHypervisorVendorIdentity: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->HypervisorVendorId, - sizeof (PlatformRepo->HypervisorVendorId), - 1, - CmObject - ); - break; - - case EArchCommonObjFixedFeatureFlags: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->FixedFeatureFlags, - sizeof (PlatformRepo->FixedFeatureFlags), - 1, - CmObject - ); - break; - - case EArchCommonObjSpmiInterfaceInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->SpmiInterfaceInfo, - sizeof (PlatformRepo->SpmiInterfaceInfo), - 1, - CmObject - ); - break; - case EArchCommonObjPciConfigSpaceInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->PciConfigSpaceInfo, - sizeof (*(PlatformRepo->PciConfigSpaceInfo)) * PlatformRepo->PciConfigSpaceInfoCount, - PlatformRepo->PciConfigSpaceInfoCount, - CmObject - ); - break; - case EArchCommonObjMemoryAffinityInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->MemoryAffinityInfo, - sizeof (*(PlatformRepo->MemoryAffinityInfo)) * PlatformRepo->MemoryAffinityInfoCount, - PlatformRepo->MemoryAffinityInfoCount, - CmObject - ); - break; - default: - { - Status = EFI_NOT_FOUND; - DEBUG (( - DEBUG_ERROR, - "ERROR: Object 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} - -/** Set the data for standard namespace object. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -SetStandardNameSpaceObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - - switch (GET_CM_OBJECT_ID (CmObjectId)) { - case EStdObjAcpiTableList: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->CmAcpiTableList, - sizeof (CM_STD_OBJ_ACPI_TABLE_INFO) * PlatformRepo->CurrentAcpiTableCount, - PlatformRepo->CurrentAcpiTableCount, - CmObject - ); - break; - default: - { - Status = EFI_NOT_FOUND; - DEBUG (( - DEBUG_ERROR, - "ERROR: Object 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} - -/** Set the data for an architecture namespace object. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -SetArchNameSpaceObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - - switch (GET_CM_OBJECT_ID (CmObjectId)) { - case EArchCommonObjPowerManagementProfileInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->PowerManagementProfile, - sizeof (PlatformRepo->PowerManagementProfile), - 1, - CmObject - ); - break; - - case EArchCommonObjHypervisorVendorIdentity: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->HypervisorVendorId, - sizeof (PlatformRepo->HypervisorVendorId), - 1, - CmObject - ); - break; - - case EArchCommonObjFixedFeatureFlags: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->FixedFeatureFlags, - sizeof (PlatformRepo->FixedFeatureFlags), - 1, - CmObject - ); - break; - case EArchCommonObjPciConfigSpaceInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->PciConfigSpaceInfo, - sizeof (*(PlatformRepo->PciConfigSpaceInfo)) * PlatformRepo->PciConfigSpaceInfoCount, - (VOID *)&PlatformRepo->PciConfigSpaceInfoCount, - CmObject - ); - break; - case EArchCommonObjMemoryAffinityInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->MemoryAffinityInfo, - sizeof (*(PlatformRepo->MemoryAffinityInfo)) * PlatformRepo->MemoryAffinityInfoCount, - (VOID *)&PlatformRepo->MemoryAffinityInfoCount, - CmObject - ); - break; - default: - { - Status = EFI_NOT_FOUND; - DEBUG (( - DEBUG_ERROR, - "ERROR: Object 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} - -/** Return an architecture namespace object. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in, out] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -GetX64NameSpaceObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - - switch (GET_CM_OBJECT_ID (CmObjectId)) { - case EX64ObjFadtSciInterrupt: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->SciInterrupt, - sizeof (PlatformRepo->SciInterrupt), - 1, - CmObject - ); - break; - case EX64ObjFadtSciCmdInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->SciCmdinfo, - sizeof (PlatformRepo->SciCmdinfo), - 1, - CmObject - ); - break; - case EX64ObjFadtPmBlockInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->PmBlockInfo, - sizeof (PlatformRepo->PmBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtGpeBlockInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->GpeBlockInfo, - sizeof (PlatformRepo->GpeBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtXpmBlockInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->XpmBlockInfo, - sizeof (PlatformRepo->XpmBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtXgpeBlockInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->XgpeBlockInfo, - sizeof (PlatformRepo->XgpeBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtSleepBlockInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->SleepBlockInfo, - sizeof (PlatformRepo->SleepBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtResetBlockInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->ResetBlockInfo, - sizeof (PlatformRepo->ResetBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtMiscInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->FadtMiscInfo, - sizeof (PlatformRepo->FadtMiscInfo), - 1, - CmObject - ); - break; - case EX64ObjHpetInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->HpetInfo, - sizeof (PlatformRepo->HpetInfo), - 1, - CmObject - ); - break; - case EX64ObjWsmtFlagsInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->WsmtFlagsInfo, - sizeof (PlatformRepo->WsmtFlagsInfo), - 1, - CmObject - ); - break; - case EX64ObjMadtInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->MadtInfo, - sizeof (PlatformRepo->MadtInfo), - 1, - CmObject - ); - break; - case EX64ObjLocalApicX2ApicInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->LocalApicX2ApicInfo, - sizeof (*(PlatformRepo->LocalApicX2ApicInfo)) * PlatformRepo->LocalApicX2ApicInfoCount, - PlatformRepo->LocalApicX2ApicInfoCount, - CmObject - ); - break; - case EX64ObjIoApicInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->IoApicInfo, - sizeof (*(PlatformRepo->IoApicInfo)) * PlatformRepo->IoApicInfoCount, - PlatformRepo->IoApicInfoCount, - CmObject - ); - break; - case EX64ObjIntrSourceOverrideInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->IntrSourceOverrideInfo, - sizeof (*(PlatformRepo->IntrSourceOverrideInfo)) * PlatformRepo->IntrSourceOverrideInfoCount, - PlatformRepo->IntrSourceOverrideInfoCount, - CmObject - ); - break; - case EX64ObjLocalApicX2ApicNmiInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->LocalApicX2ApicNmiInfo, - sizeof (*(PlatformRepo->LocalApicX2ApicNmiInfo)) * PlatformRepo->LocalApicX2ApicNmiInfoCount, - PlatformRepo->LocalApicX2ApicNmiInfoCount, - CmObject - ); - break; - case EX64ObjFacsInfo: - Status = HandleCmObject ( - CmObjectId, - &PlatformRepo->FacsInfo, - sizeof (PlatformRepo->FacsInfo), - 1, - CmObject - ); - break; - case EX64ObjLocalApicX2ApicAffinityInfo: - Status = HandleCmObject ( - CmObjectId, - PlatformRepo->LocalApicX2ApicAffinityInfo, - sizeof (*PlatformRepo->LocalApicX2ApicAffinityInfo) * PlatformRepo->LocalApicX2ApicAffinityInfoCount, - PlatformRepo->LocalApicX2ApicAffinityInfoCount, - CmObject - ); - break; - default: - { - Status = EFI_NOT_FOUND; - DEBUG (( - DEBUG_ERROR, - "ERROR: Object 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} - -/** - Set the data for X64 namespace object. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. - If unused this must be CM_NULL_TOKEN. - @param [in] CmObject Pointer to the Configuration Manager Object. -**/ -EFI_STATUS -EFIAPI -SetX64NameSpaceObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO *PlatformRepo; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - - switch (GET_CM_OBJECT_ID (CmObjectId)) { - case EX64ObjFacsInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->FacsInfo, - sizeof (PlatformRepo->FacsInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtSciInterrupt: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->SciInterrupt, - sizeof (PlatformRepo->SciInterrupt), - 1, - CmObject - ); - break; - case EX64ObjFadtSciCmdInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->SciCmdinfo, - sizeof (PlatformRepo->SciCmdinfo), - 1, - CmObject - ); - break; - case EX64ObjFadtPmBlockInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->PmBlockInfo, - sizeof (PlatformRepo->PmBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtGpeBlockInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->GpeBlockInfo, - sizeof (PlatformRepo->GpeBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtXpmBlockInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->XpmBlockInfo, - sizeof (PlatformRepo->XpmBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtXgpeBlockInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->XgpeBlockInfo, - sizeof (PlatformRepo->XgpeBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtSleepBlockInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->SleepBlockInfo, - sizeof (PlatformRepo->SleepBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtResetBlockInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->ResetBlockInfo, - sizeof (PlatformRepo->ResetBlockInfo), - 1, - CmObject - ); - break; - case EX64ObjFadtMiscInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->FadtMiscInfo, - sizeof (PlatformRepo->FadtMiscInfo), - 1, - CmObject - ); - break; - case EX64ObjHpetInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->HpetInfo, - sizeof (PlatformRepo->HpetInfo), - 1, - CmObject - ); - break; - case EX64ObjWsmtFlagsInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->WsmtFlagsInfo, - sizeof (PlatformRepo->WsmtFlagsInfo), - 1, - CmObject - ); - break; - case EX64ObjMadtInfo: - Status = SetHandleCmObject ( - CmObjectId, - &PlatformRepo->MadtInfo, - sizeof (PlatformRepo->MadtInfo), - 1, - CmObject - ); - break; - case EX64ObjLocalApicX2ApicInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->LocalApicX2ApicInfo, - sizeof (*(PlatformRepo->LocalApicX2ApicInfo)) * PlatformRepo->LocalApicX2ApicInfoCount, - (VOID *)&PlatformRepo->LocalApicX2ApicInfoCount, - CmObject - ); - break; - case EX64ObjIoApicInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->IoApicInfo, - sizeof (*(PlatformRepo->IoApicInfo)) * PlatformRepo->IoApicInfoCount, - (VOID *)&PlatformRepo->IoApicInfoCount, - CmObject - ); - break; - case EX64ObjIntrSourceOverrideInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->IntrSourceOverrideInfo, - sizeof (*(PlatformRepo->IntrSourceOverrideInfo)) * PlatformRepo->IntrSourceOverrideInfoCount, - (VOID *)&PlatformRepo->IntrSourceOverrideInfoCount, - CmObject - ); - break; - case EX64ObjLocalApicX2ApicNmiInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->LocalApicX2ApicNmiInfo, - sizeof (*(PlatformRepo->LocalApicX2ApicNmiInfo)) * PlatformRepo->LocalApicX2ApicNmiInfoCount, - (VOID *)&PlatformRepo->LocalApicX2ApicNmiInfoCount, - CmObject - ); - break; - case EX64ObjLocalApicX2ApicAffinityInfo: - Status = SetHandleCmObjectBuffer ( - CmObjectId, - (VOID **)&PlatformRepo->LocalApicX2ApicAffinityInfo, - sizeof (*PlatformRepo->LocalApicX2ApicAffinityInfo) * PlatformRepo->LocalApicX2ApicAffinityInfoCount, - (VOID *)&PlatformRepo->LocalApicX2ApicAffinityInfoCount, - CmObject - ); - break; - default: - Status = EFI_NOT_FOUND; - DEBUG (( - DEBUG_ERROR, - "ERROR: Object 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - - return Status; -} - -/** The GetObject function defines the interface implemented by the - Configuration Manager Protocol for returning the Configuration - Manager Objects. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in, out] CmObject Pointer to the Configuration Manager Object - descriptor describing the requested Object. - - @retval EFI_SUCCESS Success. - @retval EFI_INVALID_PARAMETER A parameter is invalid. - @retval EFI_NOT_FOUND The required object information is not found. -**/ -EFI_STATUS -EFIAPI -AmdPlatformGetObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - switch (GET_CM_NAMESPACE_ID (CmObjectId)) { - case EObjNameSpaceStandard: - Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject); - break; - - case EObjNameSpaceArchCommon: - Status = GetArchNameSpaceObject (This, CmObjectId, Token, CmObject); - break; - - case EObjNameSpaceX64: - Status = GetX64NameSpaceObject (This, CmObjectId, Token, CmObject); - break; - - default: - { - Status = EFI_INVALID_PARAMETER; - DEBUG (( - DEBUG_ERROR, - "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} - -/** The SetObject function defines the interface implemented by the - Configuration Manager Protocol for updating the Configuration - Manager Objects. - - @param [in] This Pointer to the Configuration Manager Protocol. - @param [in] CmObjectId The Configuration Manager Object ID. - @param [in] Token An optional token identifying the object. If - unused this must be CM_NULL_TOKEN. - @param [in] CmObject Pointer to the Configuration Manager Object - descriptor describing the Object. - - @retval EFI_UNSUPPORTED This operation is not supported. -**/ -EFI_STATUS -EFIAPI -AmdPlatformSetObject ( - IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This, - IN CONST CM_OBJECT_ID CmObjectId, - IN CONST CM_OBJECT_TOKEN Token OPTIONAL, - IN CM_OBJ_DESCRIPTOR *CONST CmObject - ) -{ - EFI_STATUS Status; - - if ((This == NULL) || (CmObject == NULL)) { - ASSERT (This != NULL); - ASSERT (CmObject != NULL); - return EFI_INVALID_PARAMETER; - } - - switch (GET_CM_NAMESPACE_ID (CmObjectId)) { - case EObjNameSpaceStandard: - Status = SetStandardNameSpaceObject (This, CmObjectId, Token, CmObject); - break; - - case EObjNameSpaceArchCommon: - Status = SetArchNameSpaceObject (This, CmObjectId, Token, CmObject); - break; - - case EObjNameSpaceX64: - Status = SetX64NameSpaceObject (This, CmObjectId, Token, CmObject); - break; - - default: - { - Status = EFI_INVALID_PARAMETER; - DEBUG (( - DEBUG_ERROR, - "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n", - CmObjectId, - Status - )); - break; - } - } - - return Status; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.c deleted file mode 100644 index 700dec37631ebff8613c7f249ffd84ccaa0b1e3f..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.c +++ /dev/null @@ -1,222 +0,0 @@ -/** @file - - Generate ACPI FACS table for AMD platforms. - - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - -STATIC -EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE mAcpiFacs = { - EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, - sizeof (EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE), - /// Hardware Signature - 0x00000000, - /// Firmware Waking Vector - 0x00000000, - /// Global Lock - 0x00000000, - /// Flags - 0x00000000, - /// XFirmware Waking Vector - 0x0000000000000000, - /// Version - EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, - /// Reserved0 - { 0, 0, 0 }, - /// OspmFlags - 0x00000000, - /// Reserved1 - { 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0} -}; - -/** - Update the hardware signature in the FACS table. -**/ -VOID -AcpiFacsTableUpdate ( - VOID - ) -{ - EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs; - EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp; - EFI_ACPI_DESCRIPTION_HEADER *Rsdt; - EFI_ACPI_DESCRIPTION_HEADER *Table; - EFI_ACPI_DESCRIPTION_HEADER *Xsdt; - EFI_STATUS Status; - UINT32 *RsdtPtr32; - UINT32 CollectedCrc[2]; - UINT32 ComputedCrc; - UINT32 TableCount; - UINT64 XsdtTablePtr; - UINTN Index; - UINTN XsdtPtr; - - DEBUG ((DEBUG_INFO, "Updating hardware signature in FACS Table.\n")); - - Status = EfiGetSystemConfigurationTable (&gEfiAcpiTableGuid, (VOID **)&Rsdp); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to get RSDP. Status(%r)\n", Status)); - ASSERT_EFI_ERROR (Status); - return; - } - - CollectedCrc[0] = Rsdp->Checksum; - CollectedCrc[1] = Rsdp->ExtendedChecksum; - gBS->CalculateCrc32 ((UINT8 *)CollectedCrc, ARRAY_SIZE (CollectedCrc), &ComputedCrc); - CollectedCrc[0] = ComputedCrc; - - Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)Rsdp->XsdtAddress; - Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)Rsdp->RsdtAddress; - if (Xsdt != NULL) { - CollectedCrc[1] = Xsdt->Checksum; - gBS->CalculateCrc32 ((UINT8 *)CollectedCrc, ARRAY_SIZE (CollectedCrc), &ComputedCrc); - CollectedCrc[0] = ComputedCrc; - - TableCount = (Xsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) / sizeof (UINT64); - XsdtPtr = (UINTN)(Xsdt + 1); - for (Index = 0; Index < TableCount; Index++) { - CopyMem (&XsdtTablePtr, (VOID *)(XsdtPtr + Index * sizeof (UINT64)), sizeof (UINT64)); - Table = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)(XsdtTablePtr)); - CollectedCrc[1] = Table->Checksum; - gBS->CalculateCrc32 ((UINT8 *)CollectedCrc, ARRAY_SIZE (CollectedCrc), &ComputedCrc); - CollectedCrc[0] = ComputedCrc; - } - } else if (Rsdt != NULL) { - /// compute the CRC - CollectedCrc[1] = Rsdt->Checksum; - gBS->CalculateCrc32 ((UINT8 *)Rsdt, Rsdt->Length, &ComputedCrc); - CollectedCrc[0] = ComputedCrc; - - TableCount = (Rsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) / sizeof (UINT32); - RsdtPtr32 = (UINT32 *)(Rsdt + 1); - for (Index = 0; Index < TableCount; Index++, RsdtPtr32++) { - Table = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)(*RsdtPtr32)); - CollectedCrc[1] = Table->Checksum; - gBS->CalculateCrc32 ((UINT8 *)CollectedCrc, ARRAY_SIZE (CollectedCrc), &ComputedCrc); - CollectedCrc[0] = ComputedCrc; - } - } - - Facs = (EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE *)EfiLocateFirstAcpiTable (EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE); - if (Facs != NULL) { - /// Update FACS signature - Facs->HardwareSignature = ComputedCrc; - } - - return; -} - -/** - Event notification function for AcpiFacsLib. - - @param[in] Event Event whose notification function is being invoked. - @param[in] Context Pointer to the notification function's context, which is - implementation-dependent. -**/ -STATIC -VOID -EFIAPI -AcpiFacsLibEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - /// Close the Event - gBS->CloseEvent (Event); - - /// Update the FACS Table - AcpiFacsTableUpdate (); -} - -/** - Implementation of AcpiFacsLibConstructor for AMD platforms. - This is library constructor for AcpiFacsLib. - - @param[in] ImageHandle Image handle of the loaded driver. - @param[in] SystemTable Pointer to the EFI System Table. - - @retval EFI_SUCCESS Successfully generated ACPI FACS Table. - @retval Others Failed to generate ACPI FACS Table. -**/ -EFI_STATUS -EFIAPI -AcpiFacsLibConstructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol; - EFI_EVENT Event; - EFI_STATUS Status; - UINTN NewTableKey; - - // FACS Table Generation code goes here - DEBUG ((DEBUG_INFO, "Generating ACPI FACS Table.\n")); - - /// Locate ACPI Table Protocol - Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiProtocol); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol. Status(%r)\n", Status)); - ASSERT_EFI_ERROR (Status); - return Status; - } - - /// Install FACS Table - Status = AcpiProtocol->InstallAcpiTable ( - AcpiProtocol, - &mAcpiFacs, - sizeof (EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE), - &NewTableKey - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to install FACS Table. Status(%r)\n", Status)); - ASSERT_EFI_ERROR (Status); - return Status; - } - - // - // Register notify function - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - AcpiFacsLibEvent, - NULL, - &gEfiEventReadyToBootGuid, - &Event - ); - ASSERT_EFI_ERROR (Status); - return Status; -} - -/** - Implementation of AcpiFacsLibDestructor for AMD platforms. - This is library destructor for AcpiFacsLib. - - @param[in] ImageHandle Image handle of the loaded driver. - @param[in] SystemTable Pointer to the EFI System Table. - - @retval EFI_SUCCESS The destructor always returns EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -AcpiFacsLibDestructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.inf b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.inf deleted file mode 100644 index bb4745af79f815b2bed757a3ef272c8bc40d04a3..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiFacsLib/AcpiFacsLib.inf +++ /dev/null @@ -1,35 +0,0 @@ -## @file -# Creates ACPI FACS tables for AMD platforms. -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 1.30 - BASE_NAME = AcpiFacsLib - FILE_GUID = 9EB7C0C6-61B4-4C7A-8481-76E935C7957A - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = NULL|DXE_DRIVER - CONSTRUCTOR = AcpiFacsLibConstructor - DESTRUCTOR = AcpiFacsLibDestructor - -[Sources] - AcpiFacsLib.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - BaseLib - DebugLib - UefiBootServicesTableLib - UefiLib - -[Guids] - gEfiEventReadyToBootGuid - gEfiAcpiTableGuid diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.c deleted file mode 100644 index b5ccb99eb57d9ac2bab0af874f0496bc8bc75139..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.c +++ /dev/null @@ -1,613 +0,0 @@ -/** @file - - Generate ACPI SSDT CPU table for AMD platforms. - - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include // for CPUID_EXTENDED_TOPOLOGY -#include - -#define DEVICE_ENABLED_BIT 0x0002 -#define DEVICE_HEALTH_BIT 0x0008 -#define DEVICE_IN_UI_BIT 0x0004 -#define DEVICE_PRESENT_BIT 0x0001 -#define MAX_TEST_CPU_STRING_SIZE 20 - -EFI_PROCESSOR_INFORMATION *mApicIdtoUidMap = NULL; -UINT32 mCcdOrder[16] = { 0, 4, 8, 12, 2, 6, 10, 14, 3, 7, 11, 15, 1, 5, 9, 13 }; - -/** - Callback compare function. - Compares CCD number of provided arguments. - - @param[in] LocalX2ApicLeft Pointer to Left Buffer. - @param[in] LocalX2ApicRight Pointer to Right Buffer. - @return 0 If both are same - -1 If left value is less than righ value. - 1 If left value is greater than righ value. - -**/ -INTN -EFIAPI -SortByCcd ( - IN CONST VOID *LocalX2ApicLeft, - IN CONST VOID *LocalX2ApicRight - ) -{ - EFI_PROCESSOR_INFORMATION *Left; - EFI_PROCESSOR_INFORMATION *Right; - UINT32 Index; - UINT32 LeftCcdIndex; - UINT32 RightCcdIndex; - - Left = (EFI_PROCESSOR_INFORMATION *)LocalX2ApicLeft; - Right = (EFI_PROCESSOR_INFORMATION *)LocalX2ApicRight; - - // Get the CCD Index number - LeftCcdIndex = MAX_UINT32; - for (Index = 0; Index < ARRAY_SIZE (mCcdOrder); Index++) { - if (Left->ExtendedInformation.Location2.Die == mCcdOrder[Index]) { - LeftCcdIndex = Index; - break; - } - } - - RightCcdIndex = MAX_UINT32; - for (Index = 0; Index < ARRAY_SIZE (mCcdOrder); Index++) { - if (Right->ExtendedInformation.Location2.Die == mCcdOrder[Index]) { - RightCcdIndex = Index; - break; - } - } - - // Now compare for quick sort - if (LeftCcdIndex < RightCcdIndex) { - return -1; - } - - if (LeftCcdIndex > RightCcdIndex) { - return 1; - } - - return 0; -} - -/** - Generate ApicId to Processor UID map. - - @retval EFI_SUCCESS - ApicId to Processor UID map generated successfully. - @retval EFI_NOT_FOUND - MP Service Protocol not found. - @retval EFI_OUT_OF_RESOURCES - Memory allocation failed. -**/ -EFI_STATUS -GenerateApicIdToUidMap ( - VOID - ) -{ - EFI_MP_SERVICES_PROTOCOL *MpService; - EFI_STATUS Status; - UINTN Index; - UINTN NumberOfCpus; - UINTN NumberOfEnabledCPUs; - UINTN SocketCount; - - // Get MP service - Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpService); - if (EFI_ERROR (Status) || (MpService == NULL)) { - return EFI_NOT_FOUND; - } - - // Load MpServices - Status = MpService->GetNumberOfProcessors (MpService, &NumberOfCpus, &NumberOfEnabledCPUs); - if (EFI_ERROR (Status)) { - return Status; - } - - DEBUG ((DEBUG_ERROR, "%a: NumberOfCpus = %d NumberOfEnabledCPUs = %d\n", __func__, NumberOfCpus, NumberOfEnabledCPUs)); - - mApicIdtoUidMap = AllocateZeroPool (NumberOfCpus * sizeof (EFI_PROCESSOR_INFORMATION)); - if (mApicIdtoUidMap == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - SocketCount = 0; - for (Index = 0; Index < NumberOfCpus; Index++) { - Status = MpService->GetProcessorInfo ( - MpService, - Index | CPU_V2_EXTENDED_TOPOLOGY, - &mApicIdtoUidMap[Index] - ); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - FreePool (mApicIdtoUidMap); - mApicIdtoUidMap = NULL; - return Status; - } - - if (mApicIdtoUidMap[Index].ExtendedInformation.Location2.Package > SocketCount) { - SocketCount = mApicIdtoUidMap[Index].ExtendedInformation.Location2.Package; - } - } - - // increment the SocketCount by 1 because socket numbering starts from 0 - SocketCount++; - - if (SocketCount > 1) { - /// Sort by CCD location - PerformQuickSort ( - mApicIdtoUidMap, - NumberOfCpus/2, - sizeof (EFI_PROCESSOR_INFORMATION), - SortByCcd - ); - PerformQuickSort ( - mApicIdtoUidMap+(NumberOfCpus/2), - NumberOfCpus/2, - sizeof (EFI_PROCESSOR_INFORMATION), - SortByCcd - ); - } else { - /// Sort by CCD location - PerformQuickSort ( - mApicIdtoUidMap, - NumberOfCpus, - sizeof (EFI_PROCESSOR_INFORMATION), - SortByCcd - ); - } - - // Now allocate the Uid - for (Index = 0; Index < NumberOfCpus; Index++) { - // Now make Processor as Uid - mApicIdtoUidMap[Index].ProcessorId = Index; - } - - return EFI_SUCCESS; -} - -/** - Install CPU devices scoped under \_SB into DSDT - - Determine all the CPU threads and create ACPI Device nodes for each thread. - - @retval EFI_SUCCESS, various EFI FAILUREs. -**/ -EFI_STATUS -GenerateAcpiSsdtCpuTable ( - VOID - ) -{ - AML_OBJECT_NODE_HANDLE CpuInstanceNode; - AML_OBJECT_NODE_HANDLE CpuNode; - AML_OBJECT_NODE_HANDLE ScopeNode; - AML_ROOT_NODE_HANDLE RootNode; - CHAR8 *String; - CHAR8 Identifier[MAX_TEST_CPU_STRING_SIZE]; - EFI_ACPI_DESCRIPTION_HEADER *Table; - EFI_ACPI_SDT_HEADER *DsdtTable; - EFI_ACPI_SDT_HEADER *ReplacementAcpiTable; - EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol; - EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; - EFI_ACPI_TABLE_VERSION DsdtVersion; - EFI_MP_SERVICES_PROTOCOL *MpServices; - EFI_STATUS Status; - EFI_STATUS Status1; - UINT32 ReplacementAcpiTableLength; - UINTN DeviceStatus; - UINTN DsdtTableKey; - UINTN Index; - UINTN NumberOfEnabledProcessors; - UINTN NumberOfLogicProcessors; - UINTN TableHandle; - - DEBUG ((DEBUG_INFO, "Generating ACPI CPU SSDT Table. \n")); - - // Get Acpi Table Protocol - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID **)&AcpiTableProtocol - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - /// Locate ACPI SDT protocol - Status = gBS->LocateProtocol ( - &gEfiAcpiSdtProtocolGuid, - NULL, - (VOID **)&AcpiSdtProtocol - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "ERROR: Failed to locate ACPI SDT Protocol. Status = %r\n", - Status - )); - return Status; - } - - // Find the DSDT table and append to it - for (Index = 0; ; Index++) { - Status = AcpiSdtProtocol->GetAcpiTable ( - Index, - &DsdtTable, - &DsdtVersion, - &DsdtTableKey - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "ERROR: ACPI DSDT table not found. Status(%r)\n", - Status - )); - return Status; - } - - if (DsdtTable->Signature == EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { - break; - } - } - - String = &Identifier[0]; - - // Get MP service - MpServices = NULL; - Status = gBS->LocateProtocol ( - &gEfiMpServiceProtocolGuid, - NULL, - (VOID **)&MpServices - ); - if (EFI_ERROR (Status) || (MpServices == NULL)) { - return EFI_NOT_FOUND; - } - - // Load MpServices - Status = MpServices->GetNumberOfProcessors ( - MpServices, - &NumberOfLogicProcessors, - &NumberOfEnabledProcessors - ); - if (EFI_ERROR (Status)) { - return Status; - } - - // Generate ACPI UID Map - Status = GenerateApicIdToUidMap (); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a: Could not generate ApicId to ProcessorUid map.\n", - __func__ - )); - return EFI_NOT_FOUND; - } - - Status = AmlCodeGenDefinitionBlock ( - "SSDT", - "AMD ", - "CPU TOPO", - 0x00, - &RootNode - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - FreePool (mApicIdtoUidMap); - return Status; - } - - Status = AmlCodeGenScope ("\\_SB_", RootNode, &ScopeNode); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - CpuNode = ScopeNode; - - for (Index = 0; Index < NumberOfLogicProcessors; Index++) { - // Check for valid Processor under the current socket - if (!mApicIdtoUidMap[Index].StatusFlag) { - continue; - } - - AsciiSPrint (String, MAX_TEST_CPU_STRING_SIZE, "C%03X", Index); - Status = AmlCodeGenDevice (String, CpuNode, &CpuInstanceNode); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // _HID - Status = AmlCodeGenNameString ("_HID", "ACPI0007", CpuInstanceNode, NULL); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - DeviceStatus = DEVICE_PRESENT_BIT | DEVICE_IN_UI_BIT; - if (mApicIdtoUidMap[Index].StatusFlag & PROCESSOR_ENABLED_BIT) { - DeviceStatus |= DEVICE_ENABLED_BIT; - } - - if (mApicIdtoUidMap[Index].StatusFlag & PROCESSOR_HEALTH_STATUS_BIT) { - DeviceStatus |= DEVICE_HEALTH_BIT; - } - - // _UID - Must match ACPI Processor UID in MADT - Status = AmlCodeGenNameInteger ( - "_UID", - mApicIdtoUidMap[Index].ProcessorId, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // _STA - As defined by 6.3.7 - Status = AmlCodeGenMethodRetInteger ( - "_STA", - DeviceStatus, - 0, - FALSE, - 0, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // PACK -> Package - Status = AmlCodeGenNameInteger ( - "PACK", - mApicIdtoUidMap[Index].ExtendedInformation.Location2.Package, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // CCD_ -> Ccd - Status = AmlCodeGenNameInteger ( - "CCD_", - mApicIdtoUidMap[Index].ExtendedInformation.Location2.Die, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // CCX_ -> Ccx - Status = AmlCodeGenNameInteger ( - "CCX_", - mApicIdtoUidMap[Index].ExtendedInformation.Location2.Module, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // CORE -> Core Number - Status = AmlCodeGenNameInteger ( - "CORE", - mApicIdtoUidMap[Index].ExtendedInformation.Location2.Core, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - - // THRD -> Thread - Status = AmlCodeGenNameInteger ( - "THRD", - mApicIdtoUidMap[Index].ExtendedInformation.Location2.Thread, - CpuInstanceNode, - NULL - ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } - } - - Table = NULL; - // Serialize the tree. - Status = AmlSerializeDefinitionBlock ( - RootNode, - &Table - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "ERROR: SSDT-PCI: Failed to Serialize SSDT Table Data." - " Status = %r\n", - Status - )); - goto exit_handler; - } - - // Cleanup - Status1 = AmlDeleteTree (RootNode); - if (EFI_ERROR (Status1)) { - DEBUG (( - DEBUG_ERROR, - "ERROR: SSDT-PCI: Failed to cleanup AML tree." - " Status = %r\n", - Status1 - )); - // If Status was success but we failed to delete the AML Tree - // return Status1 else return the original error code, i.e. Status. - if (!EFI_ERROR (Status)) { - FreePool (mApicIdtoUidMap); - return Status1; - } - } - - // Update the Table header - Table->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId); - Table->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision); - CopyMem (&Table->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (Table->OemId)); - - // Calculate new DSDT Length and allocate space - ReplacementAcpiTableLength = DsdtTable->Length + (UINT32)(Table->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)); - ReplacementAcpiTable = AllocatePool (ReplacementAcpiTableLength); - if (ReplacementAcpiTable == NULL) { - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - DEBUG ((DEBUG_ERROR, "ERROR: Unable to allocate Replacement Table space.\n")); - FreePool (mApicIdtoUidMap); - return EFI_OUT_OF_RESOURCES; - } - - // Copy the old DSDT to the new buffer - CopyMem (ReplacementAcpiTable, DsdtTable, DsdtTable->Length); - - // Append new data to DSDT - CopyMem ( - (UINT8 *)ReplacementAcpiTable + DsdtTable->Length, - (UINT8 *)Table + sizeof (EFI_ACPI_DESCRIPTION_HEADER), - Table->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - ); - - ReplacementAcpiTable->Length = ReplacementAcpiTableLength; - - // Uninstall the original DSDT - Status = AcpiTableProtocol->UninstallAcpiTable ( - AcpiTableProtocol, - DsdtTableKey - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - DEBUG (( - DEBUG_ERROR, - "ERROR: Unable to uninstall original DSDT table. Status(%r)\n", - Status - )); - } else { - // Install ACPI table - Status = AcpiTableProtocol->InstallAcpiTable ( - AcpiTableProtocol, - ReplacementAcpiTable, - ReplacementAcpiTableLength, - &TableHandle - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - DEBUG (( - DEBUG_ERROR, - "ERROR: Unable to re-install ACPI DSDT Table. Status(%r)\n", - Status - )); - } - } - - FreePool (ReplacementAcpiTable); - FreePool (mApicIdtoUidMap); - return Status; - -exit_handler: - ASSERT_EFI_ERROR (Status); - AmlDeleteTree (RootNode); - FreePool (mApicIdtoUidMap); - return Status; -} - -/** - Event notification function for AcpiSsdtCpuTopologyLib. - - @param[in] Event Event whose notification function is being invoked. - @param[in] Context Pointer to the notification function's context, which is - implementation-dependent. -**/ -STATIC -VOID -EFIAPI -AcpiSsdtCpuLibEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - /// Close the Event - gBS->CloseEvent (Event); - - /// Update the CPU SSDT Table - GenerateAcpiSsdtCpuTable (); -} - -/** - Implementation of AcpiSsdtCpuTopologyLibConstructor for AMD platforms. - This is library constructor for AcpiSsdtCpuTopologyLib. - - @param[in] ImageHandle Image handle of the loaded driver. - @param[in] SystemTable Pointer to the EFI System Table. - - @retval EFI_SUCCESS Successfully generated ACPI SSDT CPU Table. - @retval Others Failed to generate ACPI SSDT CPU Table. -**/ -EFI_STATUS -EFIAPI -AcpiSsdtCpuTopologyLibConstructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_EVENT Event; - - // - // Register notify function - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - AcpiSsdtCpuLibEvent, - NULL, - &gEfiEventReadyToBootGuid, - &Event - ); - ASSERT_EFI_ERROR (Status); - - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a: Failed to create gEfiEventReadyToBootGuid event. Status(%r)\n", - __func__, - Status - )); - } - - return Status; -} - -/** - Implementation of AcpiSsdtCpuTopologyLibDestructor for AMD platforms. - This is library destructor for AcpiSsdtCpuTopologyLib. - - @param[in] ImageHandle Image handle of the loaded driver. - @param[in] SystemTable Pointer to the EFI System Table. - - @retval EFI_SUCCESS Successfully destroyed ACPI SSDT CPU Table. - @retval Others Failed to destroy ACPI SSDT CPU Table. -**/ -EFI_STATUS -EFIAPI -AcpiSsdtCpuTopologyLibDestructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.inf b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.inf deleted file mode 100644 index 089f9ce5f59204b5e54a199706df812dc65462b6..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtCpuTopologyLib/AcpiSsdtCpuTopologyLib.inf +++ /dev/null @@ -1,48 +0,0 @@ -## @file -# Creates ACPI SSDT CPU tables for AMD platforms. -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 1.30 - BASE_NAME = AcpiSsdtCpuTopologyLib - FILE_GUID = FA22591D-D6FE-4373-93B7-1749B58F6AC9 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = NULL|DXE_DRIVER - CONSTRUCTOR = AcpiSsdtCpuTopologyLibConstructor - DESTRUCTOR = AcpiSsdtCpuTopologyLibDestructor - -[Sources] - AcpiSsdtCpuTopologyLib.c - -[Packages] - DynamicTablesPkg/DynamicTablesPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec - -[LibraryClasses] - AmlLib - BaseLib - DebugLib - SortLib - UefiBootServicesTableLib - UefiLib - -[Protocols] - gEfiMpServiceProtocolGuid ## CONSUMES - gEfiAcpiSdtProtocolGuid ## CONSUMES - -[Guids] - gEfiAcpiTableGuid - gEfiEventReadyToBootGuid - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId ## CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision ## CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## CONSUMES diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.inf b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.inf deleted file mode 100644 index ca6e55f6045dfb2a1c150896a31482c43c6a73cf..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.inf +++ /dev/null @@ -1,57 +0,0 @@ -## @file -# Creates ACPI SSDT PCI tables for AMD platforms. -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 1.30 - BASE_NAME = AcpiSsdtPciLib - FILE_GUID = CF551DAA-C1BD-46FE-A68E-17CA216CF7B9 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = NULL|DXE_DRIVER - CONSTRUCTOR = AcpiSsdtPciLibConstructor - DESTRUCTOR = AcpiSsdtPciLibDestructor - -[Sources] - AcpiSsdtPciLib.c - -[Packages] - AmdPlatformPkg/AmdPlatformPkg.dec - DynamicTablesPkg/DynamicTablesPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - PcAtChipsetPkg/PcAtChipsetPkg.dec - -[LibraryClasses] - AmlLib - BaseLib - DebugLib - PlatformSocLib - UefiBootServicesTableLib - UefiLib - -[Protocols] - gEfiAcpiSdtProtocolGuid - gEfiPciRootBridgeIoProtocolGuid - -[Guids] - gEfiAcpiTableGuid - gEfiEventReadyToBootGuid - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId ## CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision ## CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## CONSUMES - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES - gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress ## CONSUMES - -[Depex] - gEfiAcpiTableProtocolGuid AND - gEfiPciRootBridgeIoProtocolGuid AND - gEfiPciEnumerationCompleteProtocolGuid diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SampleCmPlatOverrideLib.c b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SampleCmPlatOverrideLib.c deleted file mode 100644 index 0c1b8914392c8367e618ad3f198fef2a9680c041..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SampleCmPlatOverrideLib.c +++ /dev/null @@ -1,204 +0,0 @@ -/** @file - - Sample Code for CmPlatOverrideLib library. This library demonstrate the - functionality to override the default configuration of the Configuration Manager - Protocol. - - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include -#include -#include - -static EFI_EVENT mConfigurationManagerProtocolInstalledEvent = NULL; -static VOID *mConfigurationManagerProtocolRegistration = NULL; - -/** - This function is used to override the default configuration of the Configuration Manager. - - @param[in] ConfigurationManager A pointer to the Configuration Manager Protocol. - - @retval EFI_SUCCESS The default configuration is successfully overridden. - @retval EFI_INVALID_PARAMETER ConfigurationManager is NULL. - @retval Others The default configuration is not overridden. -**/ -EFI_STATUS -EFIAPI -PlatformOverrideConfigurationManager ( - IN EDKII_CONFIGURATION_MANAGER_PROTOCOL *ConfigurationManager - ) -{ - CM_ARCH_COMMON_POWER_MANAGEMENT_PROFILE_INFO PmProfile; - CM_OBJ_DESCRIPTOR PmProfileObjDesc; - EFI_STATUS Status; - - if (ConfigurationManager == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (ConfigurationManager->PlatRepoInfo == NULL) { - return EFI_INVALID_PARAMETER; - } - - /// - /// Example 1: Override the default PmProfile configuration using SetConfigurationData API. - /// - DEBUG ((DEBUG_INFO, "Override the default PmProfile configuration\n")); - PmProfile.PowerManagementProfile = 0x02; - PmProfileObjDesc.ObjectId = CREATE_CM_OBJECT_ID (EObjNameSpaceArchCommon, EArchCommonObjPowerManagementProfileInfo); - PmProfileObjDesc.Size = sizeof (CM_ARCH_COMMON_POWER_MANAGEMENT_PROFILE_INFO); - PmProfileObjDesc.Data = (VOID *)&PmProfile; - PmProfileObjDesc.Count = 1; - Status = ConfigurationManager->SetObject ( - ConfigurationManager, - PmProfileObjDesc.ObjectId, - CM_NULL_TOKEN, - &PmProfileObjDesc - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to set PowerManagementProfile configuration with Status: %r\n", Status)); - return Status; - } - - return EFI_SUCCESS; -} - -/** - This function is called when the Configuration Manager Protocol is installed. - It is used to override the default configuration of the Configuration Manager. - - @param[in] Event The Event that is being processed. - @param[in] Context Event Context. -**/ -VOID -EFIAPI -SampleCmPlatOverrideLibOnConfigurationManagerProtocolInstalled ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EDKII_CONFIGURATION_MANAGER_PROTOCOL *ConfigurationManager; - EFI_STATUS Status; - - gBS->CloseEvent (Event); - mConfigurationManagerProtocolInstalledEvent = NULL; - - /// - /// Locate gEdkiiConfigurationManagerProtocolGuid - /// - Status = gBS->LocateProtocol ( - &gEdkiiConfigurationManagerProtocolGuid, - NULL, - (VOID **)&ConfigurationManager - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to locate Configuration Manager Protocol\n")); - return; - } - - Status = PlatformOverrideConfigurationManager (ConfigurationManager); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "PlatformOverrideConfigurationManager failed with Status: %r\n", Status)); - } - - return; -} - -/** - The constructor function initializes the library. - - The constructor function locates the Configuration Manager Protocol and - overrides the default configuration of the Configuration Manager. - - @param[in] ImageHandle The firmware allocated handle for the EFI image. - @param[in] SystemTable A pointer to the EFI System Table. - - @retval EFI_SUCCESS The constructor executed successfully. - @retval Others The constructor did not complete successfully. -**/ -EFI_STATUS -EFIAPI -SampleCmPlatOverrideLibConstructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EDKII_CONFIGURATION_MANAGER_PROTOCOL *ConfigurationManager; - EFI_STATUS Status; - - Status = gBS->LocateProtocol ( - &gEdkiiConfigurationManagerProtocolGuid, - NULL, - (VOID **)&ConfigurationManager - ); - if (EFI_ERROR (Status)) { - Status = gBS->CreateEvent ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - SampleCmPlatOverrideLibOnConfigurationManagerProtocolInstalled, - NULL, - &mConfigurationManagerProtocolInstalledEvent - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to create event for Configuration Manager Protocol installation\n")); - return Status; - } - - Status = gBS->RegisterProtocolNotify ( - &gEdkiiConfigurationManagerProtocolGuid, - mConfigurationManagerProtocolInstalledEvent, - &mConfigurationManagerProtocolRegistration - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to register for Configuration Manager Protocol installation\n")); - return Status; - } - - return EFI_SUCCESS; - } - - Status = PlatformOverrideConfigurationManager (ConfigurationManager); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "PlatformOverrideConfigurationManager failed with Status: %r\n", Status)); - } - - return Status; -} - -/** - The destructor function frees resources allocated during initialization. - - The destructor function frees any resources allocated during the initialization - of the library. - - @param[in] ImageHandle The firmware allocated handle for the EFI image. - @param[in] SystemTable A pointer to the EFI System Table. - - @retval EFI_SUCCESS The destructor executed successfully. - @retval Others The destructor did not complete successfully. -**/ -EFI_STATUS -EFIAPI -SampleCmPlatOverrideLibDestructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - if (mConfigurationManagerProtocolInstalledEvent != NULL) { - Status = gBS->CloseEvent (mConfigurationManagerProtocolInstalledEvent); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to close event for Configuration Manager Protocol installation\n")); - return Status; - } - } - - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SamplecmPlatOverrideLib.inf b/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SamplecmPlatOverrideLib.inf deleted file mode 100644 index 1b6da6456e9a1a25d9f1e85a16e164ac958cd21b..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/SampleCmPlatOverrideLib/SamplecmPlatOverrideLib.inf +++ /dev/null @@ -1,39 +0,0 @@ -## @file -# This is Sample library to demonstrate how to override the CM table in the platform. -# Using similar mechanism, platform engineer, IBV or OEM can override the CM table. -# -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 1.30 - BASE_NAME = SampleCmPlatOverrideLib - FILE_GUID = 51FAD7D4-8C5B-4FE6-B531-AA0923A159ED - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = NULL|DXE_DRIVER - CONSTRUCTOR = SampleCmPlatOverrideLibConstructor - DESTRUCTOR = SampleCmPlatOverrideLibDestructor - -[Sources] - SampleCmPlatOverrideLib.c - -[Packages] - AmdPlatformPkg/AmdPlatformPkg.dec - DynamicTablesPkg/DynamicTablesPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - BaseLib - DebugLib - UefiBootServicesTableLib - -[Protocols] - gEdkiiConfigurationManagerProtocolGuid # PROTOCOL ALWAYS_CONSUMED - -[Depex] - TRUE diff --git a/Platform/AMD/AmdPlatformPkg/Include/AmdConfigurationManager.h b/Platform/AMD/AmdPlatformPkg/Include/AmdConfigurationManager.h deleted file mode 100755 index abd1a88102b903dcd635a694e842b35ad51999b8..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/Include/AmdConfigurationManager.h +++ /dev/null @@ -1,82 +0,0 @@ -/** @file - - Copyright (C) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent - - @par Glossary: - - Cm or CM - Configuration Manager - - Obj or OBJ - Object -**/ - -#ifndef AMD_CONFIGURATION_MANAGER_H_ -#define AMD_CONFIGURATION_MANAGER_H_ - -#include -#include -#include -#include - -/** The number of ACPI tables to install -*/ -#define PLAT_ACPI_TABLE_COUNT 9 - -/** The maximum number of ACPI tables to install -*/ -#define MAX_PLAT_ACPI_TABLE_COUNT 16 - -/** The configuration manager version. -*/ -#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0) - -/** The OEM ID -*/ -#define CFG_MGR_OEM_ID { 'A', 'M', 'D', 'I', 'N', 'C' } - -#pragma pack(1) - -/** A structure describing the platform configuration - manager repository information -*/ -typedef struct PlatformRepositoryInfo { - /// Configuration Manager Information - CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo; - - /// List of ACPI tables - CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[MAX_PLAT_ACPI_TABLE_COUNT]; - UINTN CurrentAcpiTableCount; - CM_X64_FACS_INFO FacsInfo; - CM_ARCH_COMMON_POWER_MANAGEMENT_PROFILE_INFO PowerManagementProfile; - CM_ARCH_COMMON_HYPERVISOR_VENDOR_ID HypervisorVendorId; - CM_ARCH_COMMON_FIXED_FEATURE_FLAGS FixedFeatureFlags; - CM_X64_FADT_SCI_INTERRUPT SciInterrupt; - CM_X64_FADT_SCI_CMD_INFO SciCmdinfo; - CM_X64_FADT_PM_BLOCK_INFO PmBlockInfo; - CM_X64_FADT_GPE_BLOCK_INFO GpeBlockInfo; - CM_X64_FADT_X_PM_BLOCK_INFO XpmBlockInfo; - CM_X64_FADT_X_GPE_BLOCK_INFO XgpeBlockInfo; - CM_X64_FADT_SLEEP_BLOCK_INFO SleepBlockInfo; - CM_X64_FADT_RESET_BLOCK_INFO ResetBlockInfo; - CM_X64_FADT_MISC_INFO FadtMiscInfo; - CM_X64_HPET_INFO HpetInfo; - CM_X64_WSMT_FLAGS_INFO WsmtFlagsInfo; - CM_ARCH_COMMON_SPMI_INTERFACE_INFO SpmiInterfaceInfo; - CM_ARCH_COMMON_PCI_CONFIG_SPACE_INFO *PciConfigSpaceInfo; - UINTN PciConfigSpaceInfoCount; - CM_X64_MADT_INFO MadtInfo; - CM_X64_LOCAL_APIC_X2APIC_INFO *LocalApicX2ApicInfo; - UINTN LocalApicX2ApicInfoCount; - CM_X64_IO_APIC_INFO *IoApicInfo; - UINTN IoApicInfoCount; - CM_X64_INTR_SOURCE_OVERRIDE_INFO *IntrSourceOverrideInfo; - UINTN IntrSourceOverrideInfoCount; - CM_X64_LOCAL_APIC_X2APIC_NMI_INFO *LocalApicX2ApicNmiInfo; - UINTN LocalApicX2ApicNmiInfoCount; - CM_X64_LOCAL_APIC_X2APIC_AFFINITY_INFO *LocalApicX2ApicAffinityInfo; - UINTN LocalApicX2ApicAffinityInfoCount; - CM_ARCH_COMMON_MEMORY_AFFINITY_INFO *MemoryAffinityInfo; - UINTN MemoryAffinityInfoCount; -} EDKII_PLATFORM_REPOSITORY_INFO; -#pragma pack() - -#endif // AMD_CONFIGURATION_MANAGER_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Include/FchRegistersCommon.h b/Platform/AMD/AmdPlatformPkg/Include/FchRegistersCommon.h deleted file mode 100644 index ec00486c57b143a977c3a3236cd74241a8553401..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/Include/FchRegistersCommon.h +++ /dev/null @@ -1,85 +0,0 @@ -/** @file - - Copyright (C) 2008-2024 Advanced Micro Devices, Inc. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef FCH_REGISTER_COMMON_H_ -#define FCH_REGISTER_COMMON_H_ - -// Misc -#define R_FCH_ACPI_PM1_STATUS 0x00 -#define R_FCH_ACPI_PM1_ENABLE 0x02 -#define R_FCH_ACPI_PM_CONTROL 0x04 - -#define FCH_LPC_BUS 0 -#define FCH_LPC_DEV 20 -#define FCH_LPC_FUNC 3 - -#define ACPI_MMIO_BASE 0xFED80000ul -#define SMI_BASE 0x200 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define PMIO_BASE 0x300 // DWORD - -// -// FCH LPC Device 0x780E -// Device 20 (0x14) Func 3 -// -#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW -#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R -#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R -#define FCH_LPC_REGA0 0x0A0 // SPI base address -#define FCH_LPC_REGB8 0x0B8 - -// -// FCH MMIO Base (SMI) -// offset : 0x200 -// -#define FCH_SMI_REG80 0x80 // SmiStatus0 -#define FCH_SMI_REG84 0x84 // SmiStatus1 -#define FCH_SMI_REG88 0x88 // SmiStatus2 -#define FCH_SMI_REG8C 0x8C // SmiStatus3 -#define FCH_SMI_REG90 0x90 // SmiStatus4 -#define FCH_SMI_REG98 0x98 // SmiTrig -#define FCH_SMI_REGA0 0xA0 -#define FCH_SMI_REGB0 0xB0 -#define FCH_SMI_REGC4 0xC4 - -// -// FCH MMIO Base (PMIO) -// offset : 0x300 -// -#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk - -// -// -#define FCH_MISC_REG80 0x80 -// FCH SPI -// - -#define FCH_SPI_BASE_ADDRESS 0xFEC10000 - -#define FCH_SPI_MMIO_REG00 0x00 -#define FCH_SPI_FIFO_PTR_CRL 0x00100000l // -#define FCH_SPI_BUSY 0x80000000l // -#define FCH_SPI_MMIO_REG1D 0x1D // -#define FCH_SPI_MMIO_REG20 0x20 -#define FCH_SPI_MMIO_REG22 0x22 // -#define FCH_SPI_MMIO_REG30 0x30 // -#define FCH_SPI_R2VAL24 0x00000001l // -#define FCH_SPI_R2VAL25 0x00000002l // -#define FCH_SPI_R2MSK24 0x00000004l // -#define FCH_SPI_R2MSK25 0x00000008l // -#define FCH_SPI_MMIO_REG45_CMDCODE 0x45 // -#define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 // -#define FCH_SPI_MMIO_REG48_TX_BYTE_COUNT 0x48 // -#define FCH_SPI_MMIO_REG4B_RX_BYTE_COUNT 0x4B // -#define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C // -#define FCH_SPI_MMIO_REG5C_ADDR32_CTRL3 0x5C // -#define FCH_SPI_SPIROM_PAGE_MASK 0xFF // -#define FCH_SPI_MMIO_REG80_FIFO 0x80 // - -#endif /* FCH_REGISTER_COMMON_H_ */ diff --git a/Platform/AMD/AmdPlatformPkg/Include/Library/AmdPlatformSocLib.h b/Platform/AMD/AmdPlatformPkg/Include/Library/AmdPlatformSocLib.h index 11939f87de8ef56a28f8f0c5c8dbb135db3f8e6f..d37c2ed765ae4f5ed169422b34bfb3e71d8ad646 100644 --- a/Platform/AMD/AmdPlatformPkg/Include/Library/AmdPlatformSocLib.h +++ b/Platform/AMD/AmdPlatformPkg/Include/Library/AmdPlatformSocLib.h @@ -2,7 +2,7 @@ AMD Platform SoC Library. Provides interface to Get/Set platform specific data. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent @@ -19,12 +19,6 @@ #define PCIE_MAX_DEVICES 32 #define PCIE_MAX_ROOTPORT (PCIE_MAX_DEVICES * PCIE_MAX_FUNCTIONS) -#define F1A_BRH_A0_RAW_ID 0x00B00F00ul -#define F1A_BRH_B0_RAW_ID 0x00B00F10ul -#define F1A_BRH_B1_RAW_ID 0x00B00F11ul -#define F1A_BRHD_A0_RAW_ID 0x00B10F00ul -#define F1A_BRHD_B0_RAW_ID 0x00B10F10ul - typedef struct { UINTN Index; BOOLEAN Enabled; diff --git a/Platform/AMD/AmdPlatformPkg/Include/Library/AmdSmmCorePlatformHookLib.h b/Platform/AMD/AmdPlatformPkg/Include/Library/AmdSmmCorePlatformHookLib.h index 6ae76920b4b1da82f93d691aa9013a812a5094b3..1db52f63af23d189a2f7c37ac6817e556b871cdc 100644 --- a/Platform/AMD/AmdPlatformPkg/Include/Library/AmdSmmCorePlatformHookLib.h +++ b/Platform/AMD/AmdPlatformPkg/Include/Library/AmdSmmCorePlatformHookLib.h @@ -1,8 +1,7 @@ /** @file AMD Smm Core Platform Hook Library - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AmdPlatformPkg/Include/Pcd/SmbiosPcd.h b/Platform/AMD/AmdPlatformPkg/Include/Pcd/SmbiosPcd.h index 2dd0480df929c8ba294d22148d44d355072be462..58204dd7641b51cebdbcd1fc83000a819980d3e0 100644 --- a/Platform/AMD/AmdPlatformPkg/Include/Pcd/SmbiosPcd.h +++ b/Platform/AMD/AmdPlatformPkg/Include/Pcd/SmbiosPcd.h @@ -1,11 +1,10 @@ /** @file Miscellaneous smbios data structures. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent -**/ +**/ #ifndef AMD_SMBIOS_PCD_H_ #define AMD_SMBIOS_PCD_H_ @@ -16,43 +15,43 @@ #define AMD_SMBIOS_TYPE41_MAX_ONBOARD_DEVICES 16 typedef struct { - CHAR8 IntDesignatorStr[SMBIOS_STRING_MAX_LENGTH]; - CHAR8 ExtDesignatorStr[SMBIOS_STRING_MAX_LENGTH]; + CHAR8 IntDesignatorStr[SMBIOS_STRING_MAX_LENGTH]; + CHAR8 ExtDesignatorStr[SMBIOS_STRING_MAX_LENGTH]; } PORT_CONNECTOR_STR; // // AMD SMBIOS type 8 record structure. // typedef struct { - SMBIOS_TABLE_TYPE8 Type8Data; - PORT_CONNECTOR_STR DesinatorStr; + SMBIOS_TABLE_TYPE8 Type8Data; + PORT_CONNECTOR_STR DesinatorStr; } SMBIOS_PORT_CONNECTOR_RECORD; // // AMD SMBIOS type 8 record structure array. // typedef struct { - SMBIOS_PORT_CONNECTOR_RECORD SmbiosPortConnectorRecords[AMD_SMBIOS_TYPE8_MAX_PORT_CONNETORS]; + SMBIOS_PORT_CONNECTOR_RECORD SmbiosPortConnectorRecords[AMD_SMBIOS_TYPE8_MAX_PORT_CONNETORS]; } SMBIOS_PORT_CONNECTOR_RECORD_ARRAY; // // AMD SMBIOS type 41 record structure // typedef struct { - SMBIOS_TABLE_STRING ReferenceDesignation; - UINT8 DeviceType; - UINT8 DeviceEnabled; - UINT8 DeviceTypeInstance; - UINT16 VendorId; - UINT16 DeviceId; - CHAR8 RefDesignationStr[SMBIOS_STRING_MAX_LENGTH]; + SMBIOS_TABLE_STRING ReferenceDesignation; + UINT8 DeviceType; + UINT8 DeviceEnabled; + UINT8 DeviceTypeInstance; + UINT16 VendorId; + UINT16 DeviceId; + CHAR8 RefDesignationStr[SMBIOS_STRING_MAX_LENGTH]; } SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD; // // AMD SMBIOS type 41 record structure array. // typedef struct { - SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD SmbiosOnboardDevExtInfos[AMD_SMBIOS_TYPE41_MAX_ONBOARD_DEVICES]; + SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD SmbiosOnboardDevExtInfos[AMD_SMBIOS_TYPE41_MAX_ONBOARD_DEVICES]; } SMBIOS_ONBOARD_DEV_EXT_INFO_ARRAY; #endif // AMD_SMBIOS_PCD_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Include/Protocol/AmdSpiSmmHcState.h b/Platform/AMD/AmdPlatformPkg/Include/Protocol/AmdSpiSmmHcState.h index 0e2bccb3ef0e652e28ffd097f3ed8bb7a0737076..88c7dd4d9f9e0d028194ebc44ebcfd7bb9e3670a 100644 --- a/Platform/AMD/AmdPlatformPkg/Include/Protocol/AmdSpiSmmHcState.h +++ b/Platform/AMD/AmdPlatformPkg/Include/Protocol/AmdSpiSmmHcState.h @@ -1,9 +1,9 @@ /** @file Header file of AMD SMM SPI host controller state protocol - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #ifndef AMD_SMM_SPI_HC_STATE_PROTOCOL_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Include/Register/AmdIoApic.h b/Platform/AMD/AmdPlatformPkg/Include/Register/AmdIoApic.h new file mode 100644 index 0000000000000000000000000000000000000000..99f09801ecaae5b5376d993e8302a7b61bd5a911 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Include/Register/AmdIoApic.h @@ -0,0 +1,87 @@ +/** @file + I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt + Controller (IOAPIC), 1996. + + Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef AMD_IO_APIC_H_ +#define AMD_IO_APIC_H_ + +/// +/// I/O APIC Register Offsets +/// +#define IOAPIC_INDEX_OFFSET 0x00 +#define IOAPIC_DATA_OFFSET 0x10 + +/// +/// I/O APIC Indirect Register Indexes +/// +#define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00 +#define IO_APIC_VERSION_REGISTER_INDEX 0x01 +#define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10 + +/// +/// I/O APIC Interrupt Deliver Modes +/// +#define IO_APIC_DELIVERY_MODE_FIXED 0 +#define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1 +#define IO_APIC_DELIVERY_MODE_SMI 2 +#define IO_APIC_DELIVERY_MODE_NMI 4 +#define IO_APIC_DELIVERY_MODE_INIT 5 +#define IO_APIC_DELIVERY_MODE_EXTINT 7 + +#pragma pack(1) + +/// +/// The AMD IOAPIC requires an 8-bit Identification field. +/// +/// IOAPIC_ID_REGISTER Bits Description: +/// 31:24 id +/// 23:0 Reserved. +/// +typedef union { + struct { + UINT32 Reserved0:24; + UINT32 Identification:8; + } Bits; + UINT32 Uint32; +} IO_APIC_IDENTIFICATION_REGISTER; + +typedef union { + struct { + UINT32 Version:8; + UINT32 Reserved0:8; + UINT32 MaximumRedirectionEntry:8; + UINT32 Reserved1:8; + } Bits; + UINT32 Uint32; +} IO_APIC_VERSION_REGISTER; + +typedef union { + struct { + UINT32 Vector: 8; + UINT32 DeliveryMode: 3; + UINT32 DestinationMode: 1; + UINT32 DeliveryStatus: 1; + UINT32 Polarity: 1; + UINT32 RemoteIRR: 1; + UINT32 TriggerMode: 1; + UINT32 Mask: 1; + UINT32 Reserved0: 15; + UINT32 Reserved1: 24; + UINT32 DestinationID: 8; + } Bits; + struct { + UINT32 Low; + UINT32 High; + } Uint32; + UINT64 Uint64; +} IO_APIC_REDIRECTION_TABLE_ENTRY; + +#pragma pack() + +#endif diff --git a/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiDevicePaths.h b/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiDevicePaths.h index 1631e952afcad6115769ce565b7c4abfc5ab485e..84092dd2b28c2fdbfe1bdafcc9c79b584857177a 100644 --- a/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiDevicePaths.h +++ b/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiDevicePaths.h @@ -1,40 +1,41 @@ /** @file - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ - -#ifndef SPI_DEVICE_PATHS_H_ -#define SPI_DEVICE_PATHS_H_ +#ifndef AMD_SPI_DEVICE_PATHS_H_ +#define AMD_SPI_DEVICE_PATHS_H_ #include #include #include +#include typedef struct { - CONTROLLER_DEVICE_PATH ControllerDevicePath; - EFI_DEVICE_PATH_PROTOCOL End; + CONTROLLER_DEVICE_PATH ControllerDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; } SPI_CONTROLLER_DEVICE_PATH; -#define FCH_DEVICE_PATH { \ - { \ - { \ - HARDWARE_DEVICE_PATH, \ - HW_CONTROLLER_DP, \ - { \ - (UINT8)(sizeof (CONTROLLER_DEVICE_PATH)), \ - (UINT8)((sizeof (CONTROLLER_DEVICE_PATH)) >> 8) \ - } \ - }, \ - 0 \ - }, \ - { \ - END_DEVICE_PATH_TYPE, \ - END_ENTIRE_DEVICE_PATH_SUBTYPE, \ - { 0x4 } \ - } \ + +SPI_CONTROLLER_DEVICE_PATH mFchDevicePath = { + { + { + HARDWARE_DEVICE_PATH, + HW_CONTROLLER_DP, + { + (UINT8)(sizeof (CONTROLLER_DEVICE_PATH)), + (UINT8)((sizeof (CONTROLLER_DEVICE_PATH)) >> 8) + } + }, + FCH_LPC_BUS << 16 | FCH_LPC_DEV << 8 | FCH_LPC_FUNC + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + {0x4} } +}; -#endif // SPI_DEVICE_PATHS_H_ +#endif // AMD_SPI_DEVICE_PATHS_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiHcChipSelectParameters.h b/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiHcChipSelectParameters.h index c4b16e0975880cb57a07b7329c6b7740faeced1e..e99d0975a33e54f056e30714d86fbf3ae702c08e 100644 --- a/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiHcChipSelectParameters.h +++ b/Platform/AMD/AmdPlatformPkg/Include/Spi/AmdSpiHcChipSelectParameters.h @@ -1,25 +1,23 @@ /** @file Header file of AMD SMM SPI host controller state protocol - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ - -#ifndef SPI_HC_CHIP_SELECT_PARAMETERS_H_ -#define SPI_HC_CHIP_SELECT_PARAMETERS_H_ +#ifndef AMD_SPI_HC_CHIP_SELECT_PARAMETERS_H_ +#define AMD_SPI_HC_CHIP_SELECT_PARAMETERS_H_ #include #pragma pack (1) typedef struct _CHIP_SELECT_PARAMETERS { - UINT8 AndValue; - UINT8 OrValue; + UINT8 AndValue; + UINT8 OrValue; } CHIP_SELECT_PARAMETERS; #pragma pack () -#define CHIP_SELECT_1 { (UINT8)~((UINT8)0x03), 0x0 } -#define CHIP_SELECT_2 { (UINT8)~((UINT8)0x03), 0x1 } +CONST CHIP_SELECT_PARAMETERS ChipSelect1 = { (UINT8)~((UINT8)0x03), 0x0 }; // SPI_CS1_L +CONST CHIP_SELECT_PARAMETERS ChipSelect2 = { (UINT8)~((UINT8)0x03), 0x1 }; // SPI_CS1_L -#endif // SPI_HC_CHIP_SELECT_PARAMETERS_H_ +#endif // AMD_SPI_HC_CHIP_SELECT_PARAMETERS_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfig.h b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfig.h new file mode 100644 index 0000000000000000000000000000000000000000..cd9fd94736fa2419403d4e0e56e3d1dcf76200bc --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfig.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ +**/ + +#ifndef BOOT_OPTION_CONFIG_H_ +#define BOOT_OPTION_CONFIG_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UEFI_HARD_DRIVE_NAME L"UEFI Hard Drive" + +/** + Find the Lan-On-Motherboard device path. + + @param[out] LomDevicePath DevicePath of the LOM device. NULL if the LOM + is not found + @retval EFI NOT_FOUND LOM device path is not found + @retval EFI_SUCCESS LOM device path found +**/ +EFI_STATUS +EFIAPI +GetLomDevicePath ( + OUT EFI_DEVICE_PATH_PROTOCOL **LomDevicePath + ); + +#endif diff --git a/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.c b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.c new file mode 100644 index 0000000000000000000000000000000000000000..44f8a004860827183c1ac80657b9d76a4a67940d --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.c @@ -0,0 +1,259 @@ +/** @file + This library registers the BootOptionPriorityProtocol, if necessary. Searches + through PCIE devices to find the LOM to set as default PXE boot. + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ +**/ + +#include +#include +#include +#include +#include "AmdBdsBootConfig.h" + +EFI_HANDLE mBoardBdsHandle = NULL; +AMD_BOARD_BDS_BOOT_OPTION_PRIORITY_PROTOCOL mBootOptionPriorityProtocol; +EFI_DEVICE_PATH_PROTOCOL *mLomDevicePath; + +/** + Compares two device paths to see if FullDevicePath starts with PartialDevicePath. + + @param[in] PartialDevicePath Partial device path pointer. + @param[in] FullDevicePath Complete device path pointer + + @retval TRUE PartialDevicePath was found in FullDevicePath. + @retval FALSE PartialDevicePath was not found in FullDevicePath. + +**/ +BOOLEAN +StartsWithDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *PartialDevicePath, + IN EFI_DEVICE_PATH_PROTOCOL *FullDevicePath + ) +{ + INTN PartialSize; + INTN FullSize; + + // Size includes end of device path node, don't want this to be included in comparison + PartialSize = (INTN)GetDevicePathSize (PartialDevicePath) - sizeof (EFI_DEVICE_PATH_PROTOCOL); + FullSize = (INTN)GetDevicePathSize (FullDevicePath) - sizeof (EFI_DEVICE_PATH_PROTOCOL); + + if ((PartialSize <= 0) || (FullSize <= 0)) { + return FALSE; + } + + if (CompareMem (PartialDevicePath, FullDevicePath, PartialSize) != 0) { + return FALSE; + } + + return TRUE; +} + +/** + Returns the priority number. + + @param[in] BootOption Load option + @retval + OptionType EFI + ------------------------------------ + PXE 2 + DVD 4 + USB 6 + NVME 7 + HDD 8 + EFI Shell 9 + Others 100 +**/ +UINTN +PlatformBootOptionPriority ( + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption + ) +{ + // + // EFI boot options + // + switch (BootOptionType (BootOption->FilePath)) { + case MSG_MAC_ADDR_DP: + case MSG_VLAN_DP: + case MSG_IPv4_DP: + case MSG_IPv6_DP: + return 2; + + case MSG_SATA_DP: + case MSG_ATAPI_DP: + case MSG_UFS_DP: + case MSG_NVME_NAMESPACE_DP: + return 4; + + case MSG_USB_DP: + return 6; + } + + if (StrCmp (BootOption->Description, (CHAR16 *)PcdGetPtr (PcdShellFileDesc)) == 0) { + if (PcdGetBool (PcdBootToShellOnly)) { + return 0; + } + + return 9; + } + + if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) { + return 8; + } + + return 100; +} + +/** + Returns the priority number, giving the LOM device highest priority. + + @param[in] BootOption Load option + @retval + OptionType EFI + ------------------------------------ + PXE 2 + DVD 4 + USB 6 + NVME 7 + HDD 8 + EFI Shell 9 + Others 100 +**/ +UINTN +PlatformBootOptionLomPriority ( + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption + ) +{ + // highest priority for LOM + if (StartsWithDevicePath (mLomDevicePath, BootOption->FilePath) && + (BootOptionType (BootOption->FilePath) == MSG_IPv4_DP)) + { + return 0; + } + + // + // EFI boot options + // + switch (BootOptionType (BootOption->FilePath)) { + case MSG_MAC_ADDR_DP: + case MSG_VLAN_DP: + case MSG_IPv4_DP: + case MSG_IPv6_DP: + return 2; + + case MSG_SATA_DP: + case MSG_ATAPI_DP: + case MSG_UFS_DP: + case MSG_NVME_NAMESPACE_DP: + return 4; + + case MSG_USB_DP: + return 6; + } + + if (StrCmp (BootOption->Description, (CHAR16 *)PcdGetPtr (PcdShellFileDesc)) == 0) { + if (PcdGetBool (PcdBootToShellOnly)) { + return 0; + } + + return 9; + } + + if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) { + return 8; + } + + return 100; +} + +/** + Compares boot priorities of two boot options while giving + the LOM device the highest priority. + + @param[in] Left The left boot option + @param[in] Right The right boot option + + @return The difference between the Left and Right + boot options + **/ +INTN +EFIAPI +CompareBootOptionPlatformPriorityLom ( + IN CONST VOID *Left, + IN CONST VOID *Right + ) +{ + return PlatformBootOptionLomPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *)Left) - + PlatformBootOptionLomPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *)Right); +} + +/** + PciEnumerationComplete Protocol notification event handler. + + @param[in] Event Event whose notification function is being invoked. + @param[in] Context Pointer to the notification function's context. +**/ +VOID +EFIAPI +OnPciEnumerationComplete ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + // Handle LOM Device path here + Status = GetLomDevicePath (&mLomDevicePath); + DEBUG ((DEBUG_INFO, "Searching for LOM device path, Status = %r\n", Status)); + + if (!EFI_ERROR (Status)) { + mBootOptionPriorityProtocol.IpmiBootDeviceSelectorType = IPMI_BOOT_DEVICE_SELECTOR_PXE; + mBootOptionPriorityProtocol.Compare = CompareBootOptionPlatformPriorityLom; + // Install Boot Option Priority Protocol here + Status = gBS->InstallProtocolInterface ( + &mBoardBdsHandle, + &gAmdBoardBdsBootOptionPriorityProtocolGuid, + EFI_NATIVE_INTERFACE, + &mBootOptionPriorityProtocol + ); + DEBUG ((DEBUG_INFO, "Installing gBoardBdsBootOptionPriorityProtocolGuid, Status = %r\n", Status)); + } +} + +/** + Constructor function for AmdBdsBootConfig. Register PcieEnumerationComplete + Callback to handle IPMI seelctor choice and + BootOptionPriorityProtocol installation + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The data was successfully stored. + +**/ +EFI_STATUS +EFIAPI +AmdBdsBootConfigConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_EVENT ProtocolNotifyEvent; + VOID *Registration; + + ProtocolNotifyEvent = EfiCreateProtocolNotifyEvent ( + &gEfiPciEnumerationCompleteProtocolGuid, + TPL_CALLBACK, + OnPciEnumerationComplete, + NULL, + &Registration + ); + + if (ProtocolNotifyEvent == NULL) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.inf b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..0e90e61f16787a2460ed63843892de06b17ff71d --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.inf @@ -0,0 +1,71 @@ +## @file +# +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmdBdsBootConfigLib + FILE_GUID = c2481551-17f3-4ac5-ab4c-ea5396056c9b + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + CONSTRUCTOR = AmdBdsBootConfigConstructor +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + AmdBdsBootConfig.h + AmdBdsBootConfigLib.c + DefaultLomDevicePath.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + AmdCpmPkg/AmdCpmPkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + AgesaModulePkg/AgesaEdk2Pkg.dec + BoardModulePkg/BoardModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AmdMinBoardPkg/AmdMinBoardPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + HobLib + MemoryAllocationLib + NbioCommonDxeLib + NbioHandleLib + PcdLib + PcieConfigLib + PciSegmentLib + UefiDriverEntryPoint + UefiLib + IpmiLib + IpmiCommandLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BoardBdsHookLib + +[Protocols] + gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES + gAmdSocLogicalIdProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + gAmdBoardBdsBootOptionPriorityProtocolGuid ## PRODUCES SOMETIMES + +[Pcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41 ## CONSUMES + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc ## CONSUMES + +[Depex] + TRUE diff --git a/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/DefaultLomDevicePath.c b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/DefaultLomDevicePath.c new file mode 100644 index 0000000000000000000000000000000000000000..c8a4b1b4c006925998da0239fa78a27d829cff61 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Library/AmdBdsBootConfigLib/DefaultLomDevicePath.c @@ -0,0 +1,108 @@ +/***************************************************************************** + * Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + * +*******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Find the Lan-On-Motherboard device path. + + @param[out] LomDevicePath DevicePath of the LOM device. NULL if the LOM + is not found + @retval EFI NOT_FOUND LOM device path is not found + @retval EFI_SUCCESS LOM device path found +**/ +EFI_STATUS +EFIAPI +GetLomDevicePath ( + OUT EFI_DEVICE_PATH **LomDevicePath + ) +{ + SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD *DevExtInfoRecord; + EFI_STATUS Status; + EFI_HANDLE *PciHandles; + UINTN PciHandlesSize; + UINTN Index; + EFI_PCI_IO_PROTOCOL *PciProtocol; + PCI_IO_DEVICE *PciIoDevice; + UINT8 NumberOfDevices; + UINT8 DevIdx; + UINTN SegmentNumber; + UINTN BusNumber; + UINTN DeviceNumber; + UINTN FunctionNumber; + + NumberOfDevices = PcdGet8 (PcdAmdSmbiosType41Number); + DevExtInfoRecord = (SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD *)PcdGetPtr (PcdAmdSmbiosType41); + + // No device entries found + if (NumberOfDevices == 0) { + DEBUG ((DEBUG_INFO, "No onboard devices found.\n")); + return EFI_NOT_FOUND; + } + + // search through present on board devices, look for onboard ethernet + for (DevIdx = 0; DevIdx < NumberOfDevices; DevIdx++) { + if (AsciiStrCmp (DevExtInfoRecord->RefDesignationStr, "Onboard Ethernet") == 0) { + break; + } + + DevExtInfoRecord++; + } + + // edge case, no Onboard Ethernet designator + if (AsciiStrCmp (DevExtInfoRecord->RefDesignationStr, "Onboard Ethernet") != 0) { + DEBUG ((DEBUG_INFO, "No Onboard ethernet SMBIOS designator found!\n")); + return EFI_NOT_FOUND; + } + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &PciHandlesSize, + &PciHandles + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Can't locate gEfiPciIoProtocolGuid Protocol: Status = %r\n\n", Status)); + return Status; + } + + for (Index = 0; Index < PciHandlesSize; Index++) { + Status = gBS->HandleProtocol ( + PciHandles[Index], + &gEfiPciIoProtocolGuid, + (VOID **)&PciProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "ERROR - Status = %r when locating PciIoProtocol\n", Status)); + continue; + } + + PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciProtocol); + Status = PciIoDevice->PciIo.GetLocation (&PciIoDevice->PciIo, &SegmentNumber, &BusNumber, &DeviceNumber, &FunctionNumber); + + if ((PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SegmentNumber, BusNumber, DeviceNumber, FunctionNumber, 2)) == DevExtInfoRecord->DeviceId) && + (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SegmentNumber, BusNumber, DeviceNumber, FunctionNumber, 0)) == DevExtInfoRecord->VendorId)) + { + // Making Lan0 default for systems with two LANs + if (FunctionNumber == 0) { + DEBUG ((DEBUG_INFO, "Found Onboard LOM Device with DeviceID=0x%X, VendorID=0x%X\n", DevExtInfoRecord->DeviceId, DevExtInfoRecord->VendorId)); + Status = EFI_SUCCESS; + *LomDevicePath = PciIoDevice->DevicePath; + break; + } + } + } + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.c b/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.c index e9f176223d9a1154cdffa58a2ac6085a0f17d980..b6fcd9cdbaed0fad79816556263b1070bafceea6 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.c +++ b/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.c @@ -1,7 +1,7 @@ /** @file No functionality of this file. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf b/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf index 4e86256497b4e24a435151fd77d996013f1dafb3..69c76af540d36ac5fed2ce7290b5a23c3232f28e 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf @@ -7,7 +7,7 @@ # The module linked with the NULL class BaseAlwaysFalseDepexLib is still # put in the FV however it won't be executed. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.uni b/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.uni index 5c7ccf1840e8e7724401d7837a6734237933e147..327df5f9955c6a0f590f25d111ff627ae321ef46 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.uni +++ b/Platform/AMD/AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.uni @@ -1,6 +1,6 @@ ## @file # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.c b/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.c index 142c3b66a70c1113056e729843c1397f7f447b81..e1d7d6b865832b65e0b3a6d34e1d603a8da9bd61 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.c +++ b/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.c @@ -2,7 +2,7 @@ Implements AMD Platform SoC Library. Provides interface to Get/Set platform specific data. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf b/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf index df8eb6b6041df592d96fe289bf92e5bb2c28d3db..4b8aa560d08fefe7ee270c4492d657da1f9b5121 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.inf @@ -1,7 +1,7 @@ ## @file # INF file of AMD Platform SoC library # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent ## diff --git a/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.uni b/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.uni index aa2ce2bc2fa058b8df60fe5e0dcd81ed4043fd23..564ed8e0af0aaf0715771e1937b5469f081e821b 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.uni +++ b/Platform/AMD/AmdPlatformPkg/Library/DxePlatformSocLib/DxePlatformSocLibNull.uni @@ -1,7 +1,7 @@ ## @file # UNI file of AMD Platform SoC library # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.c b/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.c index 35842ecddcb3674828ba818eb5934e18219caca4..1eb456e5d75d9041746bba39974146f5ddc3a33c 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.c @@ -1,7 +1,7 @@ /** @file AMD simulator port80 serial port library functions. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf b/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf index 61e2d77f464da737ed1e22d6351c6ee51399d2ae..08a163fc8959e7845addd44ba3fe47dbe172d937 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf @@ -1,7 +1,7 @@ ## @file # Simlator port80 instance of serial port library functions. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.c b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.c index 4284f13a5ee0c0b38e3fdc1bd8b384053560e936..17751b8de616a70a97d880e91d151e3fa02d0400 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.c @@ -1,9 +1,9 @@ /** @file SMM core hook for AMD SPI Host Controller State - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include #include diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.h b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.h index 8a5dfe623ca1b8e5224118bb30f66473f88d548e..03b559354b151d80a1ab4cc099840278a66f02bf 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.h +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.h @@ -1,13 +1,13 @@ /** @file Header file of SMM core platform hook for AMD SPI Host Controller state library - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ -#ifndef SMM_CORE_AMD_SPI_HC_HOOK_LIB_H_ -#define SMM_CORE_AMD_SPI_HC_HOOK_LIB_H_ +#ifndef SMM_CORE_HOOK_AMD_SPI_HC_H_ +#define SMM_CORE_HOOK_AMD_SPI_HC_H_ /// /// Structure of AMD SPI HC State record @@ -17,4 +17,4 @@ typedef struct { EFI_HANDLE SmmSpiHcStateHandle; ///< Handle of MD SMM SPI HC State Protocol handle } SMM_CORE_HOOK_AMD_SPI_HC_STATE_CONTEXT; -#endif // SMM_CORE_AMD_SPI_HC_HOOK_LIB_H_ +#endif // SMM_CORE_HOOK_AMD_SPI_HC_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf index 9855aa8543ac01543678fea832cec0fd863b071e..626d73f687fc0027a0a12751325b487fff4e217e 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf @@ -1,8 +1,7 @@ ## @file # INF of SMM Core AMD SPI Host Contoller State hook library. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent ## [Defines] @@ -24,7 +23,6 @@ [Sources] SmmCoreAmdSpiHcHookLib.c - SmmCoreAmdSpiHcHookLib.h [Packages] AmdPlatformPkg/AmdPlatformPkg.dec diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.uni b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.uni index 0a73c4acb4d1808b8250ffb4c22ac911cdce0765..60073b9754e011d2e711579204b52429a3025bdd 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.uni +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.uni @@ -1,9 +1,9 @@ ## @file # UNI file of SMM Core AMD SPI Host Controller State hook library module # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent +# ## #string STR_MODULE_ABSTRACT #language en-US "SMM Core AMD SPI HC State Hook Library instance" diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.c b/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.c index ad6a40749f16c63b782fc53a0e9420dcef6fe277..796582fb660efb7e85c05227d503a0aa33524dda 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.c @@ -1,8 +1,7 @@ /** @file AMD SMM core hook library - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf b/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf index a79fc56077256b91bbb931ba6bee09a628b73f6e..8780bca8e3881878e2b2f52b8e7f836528112f59 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf @@ -1,9 +1,9 @@ ## @file # INF of SMM Core hook library INF file. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent +# ## [Defines] INF_VERSION = 0x00010005 @@ -37,3 +37,5 @@ MemoryAllocationLib SmmServicesTableLib +[Protocols] + gAmdSpiHcStateProtocolGuid diff --git a/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.uni b/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.uni index 0b326c159b010ac79e57b863623f139f86072ccb..b7be31000ad881f71a21177d4821d1c93f5c45b8 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.uni +++ b/Platform/AMD/AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.uni @@ -1,8 +1,7 @@ ## @file # UNI file of SMM Core hook library module # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # ## diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcInternal.c b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcInternal.c similarity index 84% rename from Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcInternal.c rename to Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcInternal.c index 19750e9c5fc6a07bf52f564cbf8dce4635c0015f..a1811536cce35ecd9a01b197decaaa97827dab51 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcInternal.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcInternal.c @@ -2,8 +2,7 @@ Internal functions used by platform SPI HC library - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -15,12 +14,12 @@ #include #include #include -#include "SpiHcInternal.h" +#include "AmdSpiHcInternal.h" extern EFI_PHYSICAL_ADDRESS mHcAddress; /** - Check that SPI Conroller is Not Busy. + Check that SPI Conroller is Not Busy @retval EFI_SUCCESS Spi Execute command executed properly @retval EFI_DEVICE_ERROR Spi Execute command failed @@ -67,7 +66,7 @@ FchSpiControllerNotBusy ( } /** - Check for SPI transaction failure(s). + Check for SPI transaction failure(s) @retval EFI_SUCCESS Spi Execute command executed properly @retval others Spi Execute command failed @@ -131,11 +130,6 @@ FchSpiExecute ( Calls to these functions from SMM will only be valid during SMM, restore state will wipe out any changes. - - @param[in] HcAddress Host controller physical address. - @param[in] Opcode SPI opcode to be passed. - @retval EFI_SUCCESS If executed successfully. - Others If fails. **/ EFI_STATUS EFIAPI @@ -186,10 +180,6 @@ InternalFchSpiBlockOpcode ( Calls to these functions from SMM will only be valid during SMM, restore state will wipe out any changes. - @param[in] HcAddress Host controller physical address. - @param[in] Opcode SPI opcode to be passed. - @retval EFI_SUCCESS If executed successfully. - Others If fails. **/ EFI_STATUS EFIAPI @@ -223,10 +213,6 @@ InternalFchSpiUnblockOpcode ( Calls to these functions from SMM will only be valid during SMM, restore state will wipe out any changes. - - @param[in] HcAddress Host controller physical address - @retval EFI_SUCCESS If executed successfully. - Others If fails **/ EFI_STATUS EFIAPI @@ -246,10 +232,6 @@ InternalFchSpiUnblockAllOpcodes ( Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, then you can clear RestrictedCmd0..3 (SPIx04) - - @param[in] HcAddress Host controller physical address - @retval EFI_SUCCESS If executed successfully. - Others If fails **/ EFI_STATUS EFIAPI @@ -280,11 +262,7 @@ InternalFchSpiLockSpiHostControllerRegisters ( SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, - then you can clear RestrictedCmd0..3 (SPIx04). - - @param[in] HcAddress Host controller physical address - @retval EFI_SUCCESS If executed successfully. - Others If fails + then you can clear RestrictedCmd0..3 (SPIx04) **/ EFI_STATUS EFIAPI diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcInternal.h b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcInternal.h similarity index 92% rename from Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcInternal.h rename to Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcInternal.h index a7a6a23c8939ada4f9155352aa8a33d28252c38b..2faa7bdba1f47f8e2d68f8987c63c4102242ea35 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcInternal.h +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcInternal.h @@ -2,14 +2,13 @@ Internal functions used by platform SPI HC library - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef SPI_HC_INTERNAL_H_ -#define SPI_HC_INTERNAL_H_ +#ifndef AMD_SPI_HC_INTERNAL_H_ +#define AMD_SPI_HC_INTERNAL_H_ #include #include @@ -125,4 +124,4 @@ InternalFchSpiUnlockSpiHostControllerRegisters ( IN CONST EFI_PHYSICAL_ADDRESS HcAddress ); -#endif // SPI_HC_INTERNAL_H__ +#endif // __AMD_SPI_HC_INTERNAL_H__ diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcSmmState.c b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcSmmState.c similarity index 85% rename from Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcSmmState.c rename to Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcSmmState.c index ce0176e076988c2d190271a067fd90a4ad612bb6..584869d0aa80e8991fab6e648caa6876583cd26e 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcSmmState.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcSmmState.c @@ -2,18 +2,18 @@ SPI HC SMM state registration function definitions - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include +#include #include #include #include #include -#include "SpiHcSmmState.h" -#include "SpiHcInternal.h" +#include "AmdSpiHcSmmState.h" +#include "AmdSpiHcInternal.h" extern EFI_PHYSICAL_ADDRESS mHcAddress; extern BOOLEAN mSmmAlreadySavedState; @@ -21,7 +21,7 @@ extern VOID *mState; extern UINT32 mStateSize; extern UINT32 mStateRecordCount; -CONST SPI_HC_REGISTER_STATE mSpiHcState[] = { +CONST struct SpiHcRegisterState mSpiHcState[] = { // {Register, Size, Count} { 0x04, 0x4, 0x1 }, // SPI_RestrictedCmd { 0x08, 0x4, 0x1 }, // SPI_RestrictedCmd2 @@ -45,7 +45,7 @@ CONST SPI_HC_REGISTER_STATE mSpiHcState[] = { }; /** - Allocate the save state space and update the instance structure. + Allocate the save state space and update the instance structure @retval EFI_SUCCESS The Save State space was allocated @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate @@ -59,7 +59,7 @@ AllocateState ( UINT32 NumRecords; UINT32 Record; - NumRecords = sizeof (mSpiHcState) / sizeof (SPI_HC_REGISTER_STATE); + NumRecords = sizeof (mSpiHcState) / sizeof (struct SpiHcRegisterState); // calculate space needed mStateSize = 0; @@ -81,7 +81,7 @@ AllocateState ( } /** - Save the Host controller state to restore after transaction is complete. + Save the Host controler state to restore after transaction is complete @param[in] This SPI host controller Preserve State Protocol; @@ -150,7 +150,7 @@ SaveState ( } /** - Restore the Host Controller state. + Restore the Host Controller state @param[in] This SPI host controller Preserve State Protocol; @@ -224,10 +224,6 @@ RestoreState ( Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, then you can clear RestrictedCmd0..3 (SPIx04) - - @param[in] This A pointer to the SMM_EFI_SPI_HC_STATE_PROTOCOL structure. - @param[in] Opcode SPI opcode value. - @retval Others return various return values. **/ EFI_STATUS EFIAPI @@ -250,10 +246,6 @@ FchSpiBlockOpcode ( Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, then you can clear RestrictedCmd0..3 (SPIx04) - - @param[in] This A pointer to the SMM_EFI_SPI_HC_STATE_PROTOCOL structure. - @param[in] Opcode SPI opcode value. - @retval Others Various return values. **/ EFI_STATUS EFIAPI @@ -276,9 +268,6 @@ FchSpiUnblockOpcode ( Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, then you can clear RestrictedCmd0..3 (SPIx04) - - @param[in] This A pointer to the SMM_EFI_SPI_HC_STATE_PROTOCOL structure. - @retval Others return various return values. **/ EFI_STATUS EFIAPI @@ -300,9 +289,6 @@ FchSpiUnblockAllOpcodes ( Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, then you can clear RestrictedCmd0..3 (SPIx04) - - @param[in] This A pointer to the SMM_EFI_SPI_HC_STATE_PROTOCOL structure. - @retval Others return various return values. **/ EFI_STATUS EFIAPI @@ -317,17 +303,14 @@ FchSpiLockSpiHostControllerRegisters ( } /** - Unlock SPI host controller registers. - This unlock function will only work in SMM. + Unlock SPI host controller registers. This unlock function will only work in + SMM. RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. Once SPIx00[23:22] = 00b, they can only be written in SMM, to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, then you can clear RestrictedCmd0..3 (SPIx04) - - @param[in] This A pointer to the SMM_EFI_SPI_HC_STATE_PROTOCOL - @retval Others Various return values **/ EFI_STATUS EFIAPI diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcSmmState.h b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcSmmState.h similarity index 91% rename from Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcSmmState.h rename to Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcSmmState.h index 32e9869593401dc246c9cd4da2ece127dfc66b74..1039864dbade7657eec72b3e7e850cd90964e381 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcSmmState.h +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/AmdSpiHcSmmState.h @@ -2,25 +2,24 @@ SPI HC SMM state registration function declarations - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef SPI_HC_SMM_STATE_H_ -#define SPI_HC_SMM_STATE_H_ +#ifndef AMD_SPI_HC_SMM_STATE_H_ +#define AMD_SPI_HC_SMM_STATE_H_ #include #include #include -#include "SpiHcInternal.h" +#include "AmdSpiHcInternal.h" -typedef struct { +struct SpiHcRegisterState { UINT32 Register; UINT8 Size; // Size in Bytes UINT8 Count; // Number of contiguous registers to store -} SPI_HC_REGISTER_STATE; +}; /** Allocate the save state space and update the instance structure @@ -140,4 +139,4 @@ FchSpiUnlockSpiHostControllerRegisters ( IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This ); -#endif // SPI_HC_SMM_STATE_H__ +#endif // __AMD_SPI_HC_SMM_STATE_H__ diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.c b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.c index 041676ed5b7e252c205a437f312116deafed7793..45238af377d93dd2b6584c6339d2c65dca93f25a 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.c @@ -3,8 +3,7 @@ SPI HC platform library implementation. This code touches the SPI controllers and performs the hardware transaction - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -17,18 +16,17 @@ #include #include #include +#include #include #include #include #include -#include "SpiHcInternal.h" +#include "AmdSpiHcInternal.h" #include #include extern EFI_PHYSICAL_ADDRESS mHcAddress; -SPI_CONTROLLER_DEVICE_PATH mFchDevicePath = FCH_DEVICE_PATH; - /** This function reports the device path of SPI host controller. This is needed in order for the SpiBus to match the correct SPI_BUS to the SPI host controller @@ -36,7 +34,7 @@ SPI_CONTROLLER_DEVICE_PATH mFchDevicePath = FCH_DEVICE_PATH; @param[out] DevicePath The device path for this SPI HC is returned in this variable @retval EFI_SUCCESS -**/ +*/ EFI_STATUS EFIAPI GetSpiHcDevicePath ( @@ -49,7 +47,7 @@ GetSpiHcDevicePath ( /** This is the platform specific Spi Chip select function. - Assert or de-assert the SPI chip select. + Assert or deassert the SPI chip select. This routine is called at TPL_NOTIFY. Update the value of the chip select line for a SPI peripheral. The SPI bus @@ -265,11 +263,11 @@ PlatformSpiHcTransaction ( Status = FchSpiControllerNotBusy (); if (!EFI_ERROR (Status)) { MmioWrite8 ( - HcAddress + FCH_SPI_MMIO_REG48_TX_BYTE_COUNT, + HcAddress + FCH_SPI_MMIO_REG48_TX_BYTECOUNT, (UINT8)WriteBytes ); MmioWrite8 ( - HcAddress + FCH_SPI_MMIO_REG4B_RX_BYTE_COUNT, + HcAddress + FCH_SPI_MMIO_REG4B_RXBYTECOUNT, (UINT8)ReadBytes ); diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.uni b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.uni index e36816d5d138713a8c216e4f31256f0f64e116db..ca72599eeeed4f7a639bf15b0622d02c94720b83 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.uni +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLib.uni @@ -1,6 +1,6 @@ // /***************************************************************************** // * -// * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// * Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. // * // * // * SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.c b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.c index 8f1e2304f8c339bb6b34b0db2602193c6762405d..1292ab697caa2267fb081181620d369800dfebca 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.c @@ -2,8 +2,7 @@ Implementation of SpiHcPlatformLib for DXE - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -15,9 +14,10 @@ #include #include #include +#include #include #include -#include "SpiHcInternal.h" +#include "AmdSpiHcInternal.h" #include #include @@ -35,7 +35,7 @@ EFI_PHYSICAL_ADDRESS mHcAddress; @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated -**/ +*/ EFI_STATUS EFIAPI GetPlatformSpiHcDetails ( diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf index de4b9235c38ee043e12476351287901cae31cdfd..e7261daefda1cdd3404dc974310827569f43d18c 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf @@ -1,22 +1,23 @@ -## @file -# SpiHcPlatformLibrary DXE_DRIVER inf +#/** @file # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# SpiHcPlatformLibrary DXE_DRIVER inf # +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # -## - +#**/ [Defines] INF_VERSION = 0x00010019 BASE_NAME = SpiHcPlatformLibDxe - FILE_GUID = 1B53F26A-971D-4DFC-A13D-2626CFDF863D + FILE_GUID = 3C230948-6DF5-4802-8177-967A190579CF MODULE_TYPE = DXE_DRIVER VERSION_STRING = 0.1 PI_SPECIFICATION_VERSION = 0x0001000A LIBRARY_CLASS = SpiHcPlatformLib [Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec AmdPlatformPkg/AmdPlatformPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -38,15 +39,15 @@ [Sources] SpiHcPlatformLibDxe.c SpiHcPlatformLib.c - SpiHcInternal.h - SpiHcInternal.c + AmdSpiHcInternal.h + AmdSpiHcInternal.c [Protocols] gEfiSpiHcProtocolGuid [FixedPcd] gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount - gEfiMdeModulePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds [Depex] TRUE diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.c b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.c index c4b4f5e0e17599f84737eb8baf71fc66d622d6dc..85b4eaaf5d9c3a78b066e3e9a49fd5d64b7fed4c 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.c +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.c @@ -2,8 +2,7 @@ Implementation of SpiHcPlatformLibrary for SMM - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -18,12 +17,13 @@ #include #include #include +#include #include #include #include #include -#include "SpiHcInternal.h" -#include "SpiHcSmmState.h" +#include "AmdSpiHcInternal.h" +#include "AmdSpiHcSmmState.h" #define SPI_HC_MAXIMUM_TRANSFER_BYTES 64 @@ -49,7 +49,7 @@ UINT32 mStateRecordCount; @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated -**/ +*/ EFI_STATUS EFIAPI GetPlatformSpiHcDetails ( diff --git a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf index 80c7518807c7879ae31ff6d7bfdcd2d2f00ef5e4..8d248f5f854718d61dfaea0bf4b0ec1f111ec664 100644 --- a/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf +++ b/Platform/AMD/AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf @@ -1,12 +1,11 @@ -## @file -# SpiHcPlatformLibrary DXE_SMM_DRIVER inf +#/** @file # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# SpiHcPlatformLibrary DXE_SMM_DRIVER inf # +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # -## - +#**/ [Defines] INF_VERSION = 0x00010019 BASE_NAME = SpiHcPlatformLibSmm @@ -17,6 +16,8 @@ LIBRARY_CLASS = SpiHcPlatformLib [Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec AmdPlatformPkg/AmdPlatformPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -36,10 +37,10 @@ [Sources] SpiHcPlatformLibSmm.c SpiHcPlatformLib.c - SpiHcInternal.h - SpiHcInternal.c - SpiHcSmmState.h - SpiHcSmmState.c + AmdSpiHcInternal.h + AmdSpiHcInternal.c + AmdSpiHcSmmState.h + AmdSpiHcSmmState.c [Protocols] gEfiSmmVariableProtocolGuid @@ -49,7 +50,7 @@ [FixedPcd] gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount - gEfiMdeModulePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds [Depex] TRUE diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.c b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.c new file mode 100644 index 0000000000000000000000000000000000000000..bfc19788e15f4523dcd0608c8d37e6678bb84f94 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.c @@ -0,0 +1,224 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "AcpiCommon.h" + +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; + +/** + Locates an existing ACPI Table + + @param[in] Signature - The Acpi table signature + @param[in] OemTableId - The Acpi table OEM Table ID. Ignored if 0 + @param[out] Table - Table if Found or NULL + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +GetExistingAcpiTable ( + IN UINT32 Signature, + IN UINT64 OemTableId, + OUT EFI_ACPI_SDT_HEADER **Table +) +{ + EFI_STATUS Status; + UINTN Index; + EFI_ACPI_SDT_HEADER *LocalTable; + EFI_ACPI_TABLE_VERSION LocalVersion; + UINTN LocalTableKey; + + Status = EFI_NOT_FOUND; + *Table = NULL; + + for (Index = 0; ; Index++) { + Status = mAcpiSdtProtocol->GetAcpiTable (Index, &LocalTable, &LocalVersion, &LocalTableKey); + if (EFI_ERROR (Status)) { + return Status; + } + + if (!(LocalTable->Signature == Signature)) { + continue; + } + // Accept table if OemTableId is zero. + if (OemTableId == 0 || + CompareMem (&LocalTable->OemTableId, &OemTableId, 8) == 0) { + *Table = LocalTable; + return EFI_SUCCESS; + } + } +} + +/** + Appends generated AML to an existing ACPI Table + + 1. Locate the existing ACPI table + 2. Allocate pool for original table plus new data size + 3. Copy original table to new buffer + 4. Append new data to buffer + 5. Update Table header length (Checksum will be calculated on install) + 6. Uninstall original ACPI table + 7. Install appended table + 8. Free new table buffer since ACPI made a copy. + + @param[in] Signature - The Acpi table signature + @param[in] OemId - The Acpi table OEM ID + @param[in] AmlData - The AML data to append + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +AppendExistingAcpiTable ( + IN UINT32 Signature, + IN UINT64 OemId, + IN EFI_ACPI_DESCRIPTION_HEADER *AmlData + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_ACPI_SDT_HEADER *Table; + EFI_ACPI_TABLE_VERSION Version; + UINTN TableKey; + EFI_ACPI_SDT_HEADER *ReplacementAcpiTable; + UINT32 ReplacementAcpiTableLength; + UINTN TableHandle; + + for (Index = 0; ; Index++) { + Status = mAcpiSdtProtocol->GetAcpiTable (Index, &Table, &Version, &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR: ACPI table not found with signature=0x%X\n", Signature)); + return Status; + } + + if ((Table->Signature == Signature) && + (CompareMem (&Table->OemTableId, &OemId, 8) == 0)) + { + break; + } + } + + // Calculate new DSDT Length and allocate space + ReplacementAcpiTableLength = Table->Length + (UINT32)(AmlData->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)); + ReplacementAcpiTable = AllocatePool (ReplacementAcpiTableLength); + if (ReplacementAcpiTable == NULL) { + DEBUG ((DEBUG_ERROR, "ERROR: Unable to allocate Replacement Table space.\n")); + return EFI_OUT_OF_RESOURCES; + } + + // Copy the old DSDT to the new buffer + CopyMem (ReplacementAcpiTable, Table, Table->Length); + // Append new data to DSDT + CopyMem ( + (UINT8 *)ReplacementAcpiTable + Table->Length, + (UINT8 *)AmlData + sizeof (EFI_ACPI_DESCRIPTION_HEADER), + AmlData->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER) + ); + ReplacementAcpiTable->Length = ReplacementAcpiTableLength; + + // Uninstall the original DSDT + Status = mAcpiTableProtocol->UninstallAcpiTable ( + mAcpiTableProtocol, + TableKey + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR: Unable to uninstall original ACPI Table signature=0x%X\n", Signature)); + } else { + // Install ACPI table + Status = mAcpiTableProtocol->InstallAcpiTable ( + mAcpiTableProtocol, + ReplacementAcpiTable, + ReplacementAcpiTableLength, + &TableHandle + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR: Unable to re-install ACPI Table signature=0x%X\n", Signature)); + } + } + + // Release this copy of table + FreePool (ReplacementAcpiTable); + return Status; +} + +/** + Install common platform SSDTs and DSDT additions + + Place to install all generically identifiable SSDT tables. These tables will + be programmattically created from UEFI or AGESA resources and should cover + many different Processor Family IPs. + + Might need to split this driver into LibraryClasses for each + functionality/SSDT while keeping a single driver to reduce the AmlLib overhead. + + @param[in] ImageHandle - Standard UEFI entry point Image Handle + @param[in] SystemTable - Standard UEFI entry point System Table + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +InstallAllAcpiTables ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + // Get Acpi Table Protocol + Status = gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&mAcpiTableProtocol + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Get Acpi SDT Protocol + Status = gBS->LocateProtocol ( + &gEfiAcpiSdtProtocolGuid, + NULL, + (VOID **)&mAcpiSdtProtocol + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = InstallCpuAcpi (ImageHandle, SystemTable); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: CPU SSDT install error: Status=%r\n", + __FUNCTION__, + Status + )); + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = InstallPciAcpi (ImageHandle, SystemTable); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: PCI SSDT install error: Status=%r\n", + __FUNCTION__, + Status + )); + ASSERT_EFI_ERROR (Status); + return Status; + } + + InstallAcpiSpmiTable (); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.h b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.h new file mode 100644 index 0000000000000000000000000000000000000000..aae1fa996d8fd83d936e7427e5d2142d6db15f27 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.h @@ -0,0 +1,120 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef ACPI_COMMON_H_ +#define ACPI_COMMON_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_DSDT_OEMID SIGNATURE_64 ('A', 'm', 'd', 'T','a','b','l','e') +#define CREATOR_REVISION 2 +#define MAX_LOCAL_STRING_SIZE 20 +#define OEM_REVISION_NUMBER 0 +#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') /// "CEDT" CXL Early Discovery Table + +extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; +extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; + +/** + Locates an existing ACPI Table + + @param[in] Signature - The Acpi table signature + @param[in] OemTableId - The Acpi table OEM Table ID. Ignored if 0 + @param[out] Table - Table if Found or NULL + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +GetExistingAcpiTable ( + IN UINT32 Signature, + IN UINT64 OemTableId, + OUT EFI_ACPI_SDT_HEADER **Table +); + +/** + Appends generated AML to an existing ACPI Table + + 1. Locate the existing ACPI table + 2. Allocate pool for original table plus new data size + 3. Copy original table to new buffer + 4. Append new data to buffer + 5. Update Table header length (Checksum will be calculated on install) + 6. Uninstall original ACPI table + 7. Install appended table + 8. Free new table buffer since ACPI made a copy. + + @param[in] Signature - The Acpi table signature + @param[in] OemId - The Acpi table OEM ID + @param[in] AmlData - The AML data to append + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +AppendExistingAcpiTable ( + IN UINT32 Signature, + IN UINT64 OemId, + IN EFI_ACPI_DESCRIPTION_HEADER *AmlData + ); + +/** + Install CPU devices scoped under \_SB into DSDT + + Determine all the CPU threads and create ACPI Device nodes for each thread. + AGESA will scope to these CPU records when installing CPU power and + performance capabilities. + + @param[in] ImageHandle - Standard UEFI entry point Image Handle + @param[in] SystemTable - Standard UEFI entry point System Table + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +InstallCpuAcpi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + Install PCI devices scoped under \_SB into DSDT + + Determine all the PCI Root Bridges and PCI root ports and install resources + including needed _HID, _CID, _UID, _ADR, _CRS and _PRT Nodes. + + @param[in] ImageHandle - Standard UEFI entry point Image Handle + @param[in] SystemTable - Standard UEFI entry point System Table + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +InstallPciAcpi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +VOID +EFIAPI +InstallAcpiSpmiTable ( + VOID + ); + +#endif // ACPI_COMMON_H__ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf new file mode 100644 index 0000000000000000000000000000000000000000..60afdd7664d3177a4c0318788a758d3572e13b9d --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf @@ -0,0 +1,73 @@ +#/** @file +# +# Component description file for SpiFvbDxe module +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiCommon + FILE_GUID = 66838F31-1062-415C-957A-CC2871D9E6B7 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallAllAcpiTables + +[Sources.common] + AcpiCommon.c + AcpiCommon.h + CpuSsdt.c + PciSsdt.c + Spmi.c + +[Packages] + AmdPlatformPkg/AmdPlatformPkg.dec + DynamicTablesPkg/DynamicTablesPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + AmlLib + BaseLib + BaseMemoryLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + PcdLib + PlatformSocLib + SortLib + UefiDriverEntryPoint + +[Protocols] + gEfiAcpiSdtProtocolGuid ## CONSUMES + gEfiAcpiTableProtocolGuid ## CONSUMES + gEfiMpServiceProtocolGuid ## CONSUMES + gEfiPciRootBridgeIoProtocolGuid ## CONSUMES + +[Pcd] + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase + +[Guids] + gEfiHobListGuid + +[Depex] + gEfiMpServiceProtocolGuid AND + gEfiAcpiTableProtocolGuid AND + gEfiPciRootBridgeIoProtocolGuid AND + gEfiPciEnumerationCompleteProtocolGuid + diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/CpuSsdt.c b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/CpuSsdt.c new file mode 100644 index 0000000000000000000000000000000000000000..f4edc4d5ca6b61a375ebfb9fb37e7d339cbf6828 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/CpuSsdt.c @@ -0,0 +1,341 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "AcpiCommon.h" + +#include +#include +#include +#include // for CPUID_EXTENDED_TOPOLOGY + +#define AMD_CPUID_EXTENDED_TOPOLOGY_V2 0x26 +#define AMD_CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_CCD 0x04 +#define AMD_CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_CCX 0x03 +#define AMD_CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05 +#define CREATOR_REVISION 2 +#define DEVICE_BATTERY_BIT 0x0010// Control Method Battery Device Only +#define DEVICE_ENABLED_BIT 0x0002 +#define DEVICE_HEALTH_BIT 0x0008 +#define DEVICE_IN_UI_BIT 0x0004 +#define DEVICE_PRESENT_BIT 0x0001 +#define MAX_TEST_CPU_STRING_SIZE 20 +#define OEM_REVISION_NUMBER 0 + +EFI_PROCESSOR_INFORMATION *mApicIdtoUidMap = NULL; +UINT32 mCcdOrder[16] = { 0, 4, 8, 12, 2, 6, 10, 14, 3, 7, 11, 15, 1, 5, 9, 13 }; +UINTN mNumberOfCpus = 0; +UINTN mNumberOfEnabledCPUs = 0; + +/** + Callback compare function. + Compares CCD number of provided arguments. + + @param[in] LocalX2ApicLeft Pointer to Left Buffer. + @param[in] LocalX2ApicRight Pointer to Right Buffer. + @return 0 If both are same + -1 If left value is less than righ value. + 1 If left value is greater than righ value. + +**/ +INTN +EFIAPI +SortByCcd ( + IN CONST VOID *LocalX2ApicLeft, + IN CONST VOID *LocalX2ApicRight + ) +{ + EFI_PROCESSOR_INFORMATION *Left; + EFI_PROCESSOR_INFORMATION *Right; + UINT32 Index; + UINT32 LeftCcdIndex; + UINT32 RightCcdIndex; + + Left = (EFI_PROCESSOR_INFORMATION *)LocalX2ApicLeft; + Right = (EFI_PROCESSOR_INFORMATION *)LocalX2ApicRight; + + // Get the CCD Index number + LeftCcdIndex = MAX_UINT32; + for (Index = 0; Index < ARRAY_SIZE (mCcdOrder); Index++) { + if (Left->ExtendedInformation.Location2.Die == mCcdOrder[Index]) { + LeftCcdIndex = Index; + break; + } + } + + RightCcdIndex = MAX_UINT32; + for (Index = 0; Index < ARRAY_SIZE (mCcdOrder); Index++) { + if (Right->ExtendedInformation.Location2.Die == mCcdOrder[Index]) { + RightCcdIndex = Index; + break; + } + } + + // Now compare for quick sort + if (LeftCcdIndex < RightCcdIndex) { + return -1; + } + + if (LeftCcdIndex > RightCcdIndex) { + return 1; + } + + return 0; +} + +EFI_STATUS +GenerateApicIdtoUidMap ( + VOID + ) +{ + EFI_MP_SERVICES_PROTOCOL *MpService; + EFI_STATUS Status; + UINTN Index; + + // Get MP service + Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpService); + if (EFI_ERROR (Status) || (MpService == NULL)) { + return EFI_NOT_FOUND; + } + + // Load MpServices + Status = MpService->GetNumberOfProcessors (MpService, &mNumberOfCpus, &mNumberOfEnabledCPUs); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_ERROR, "%a: NumberOfCpus = %d mNumberOfEnabledCPUs = %d\n", __func__, mNumberOfCpus, mNumberOfEnabledCPUs)); + + mApicIdtoUidMap = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_PROCESSOR_INFORMATION)); + if (mApicIdtoUidMap == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index = 0; Index < mNumberOfCpus; Index++) { + Status = MpService->GetProcessorInfo ( + MpService, + Index | CPU_V2_EXTENDED_TOPOLOGY, + &mApicIdtoUidMap[Index] + ); + } + + if (FixedPcdGet32 (PcdMaxCpuSocketCount) > 1) { + /// Sort by CCD location + PerformQuickSort (mApicIdtoUidMap, mNumberOfCpus/2, sizeof (EFI_PROCESSOR_INFORMATION), SortByCcd); + PerformQuickSort (mApicIdtoUidMap+(mNumberOfCpus/2), mNumberOfCpus/2, sizeof (EFI_PROCESSOR_INFORMATION), SortByCcd); + } else { + /// Sort by CCD location + PerformQuickSort (mApicIdtoUidMap, mNumberOfCpus, sizeof (EFI_PROCESSOR_INFORMATION), SortByCcd); + } + + // Now allocate the Uid + for (Index = 0; Index < mNumberOfCpus; Index++) { + // Now make Processor as Uid + mApicIdtoUidMap[Index].ProcessorId = Index; + } + + return EFI_SUCCESS; +} + +/** + Install CPU devices scoped under \_SB into DSDT + + Determine all the CPU threads and create ACPI Device nodes for each thread. + AGESA will scope to these CPU records when installing CPU power and + performance capabilities. + + @param[in] ImageHandle - Standard UEFI entry point Image Handle + @param[in] SystemTable - Standard UEFI entry point System Table + + @retval EFI_SUCCESS, various EFI FAILUREs. +**/ +EFI_STATUS +EFIAPI +InstallCpuAcpi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + AML_OBJECT_NODE_HANDLE CpuInstanceNode; + AML_OBJECT_NODE_HANDLE CpuNode; + AML_OBJECT_NODE_HANDLE ScopeNode; + AML_ROOT_NODE_HANDLE RootNode; + CHAR8 *String; + CHAR8 Identifier[MAX_TEST_CPU_STRING_SIZE]; + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_MP_SERVICES_PROTOCOL *MpServices; + EFI_STATUS Status; + EFI_STATUS Status1; + UINTN DeviceStatus; + UINTN Index; + UINTN NumberOfEnabledProcessors; + UINTN NumberOfLogicProcessors; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + String = &Identifier[0]; + + // Get MP service + MpServices = NULL; + Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices); + if (EFI_ERROR (Status) || (MpServices == NULL)) { + return EFI_NOT_FOUND; + } + + // Generate ACPI UID Map + Status = GenerateApicIdtoUidMap (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Could not generate ApicId to ProcessorUid map.\n", __func__)); + return EFI_NOT_FOUND; + } + + // Load MpServices + Status = MpServices->GetNumberOfProcessors (MpServices, &NumberOfLogicProcessors, &NumberOfEnabledProcessors); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = AmlCodeGenDefinitionBlock ( + "SSDT", + "AMD ", + "SSDTPROC", + 0x00, + &RootNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlCodeGenScope ("\\_SB_", RootNode, &ScopeNode); // START: Scope (\_SB) + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + CpuNode = ScopeNode; + + for (Index = 0; Index < NumberOfLogicProcessors; Index++) { + // Check for valid Processor under the current socket + if (!mApicIdtoUidMap[Index].StatusFlag) { + continue; + } + + // Assumption is that AGESA will have to do the same thing. + AsciiSPrint (String, MAX_TEST_CPU_STRING_SIZE, "C%03X", Index); + Status = AmlCodeGenDevice (String, CpuNode, &CpuInstanceNode); // START: Device (CXXX) + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // _HID + Status = AmlCodeGenNameString ("_HID", "ACPI0007", CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DeviceStatus = DEVICE_PRESENT_BIT | DEVICE_IN_UI_BIT; + if (mApicIdtoUidMap[Index].StatusFlag & PROCESSOR_ENABLED_BIT) { + DeviceStatus |= DEVICE_ENABLED_BIT; + } + + if (mApicIdtoUidMap[Index].StatusFlag & PROCESSOR_HEALTH_STATUS_BIT) { + DeviceStatus |= DEVICE_HEALTH_BIT; + } + + // _UID - Must match ACPI Processor UID in MADT + Status = AmlCodeGenNameInteger ("_UID", mApicIdtoUidMap[Index].ProcessorId, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // _STA - As defined by 6.3.7 + Status = AmlCodeGenMethodRetInteger ("_STA", DeviceStatus, 0, FALSE, 0, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // PACK -> Package + Status = AmlCodeGenNameInteger ("PACK", mApicIdtoUidMap[Index].ExtendedInformation.Location2.Package, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // CCD_ -> Ccd + Status = AmlCodeGenNameInteger ("CCD_", mApicIdtoUidMap[Index].ExtendedInformation.Location2.Die, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // CCX_ -> Ccx + Status = AmlCodeGenNameInteger ("CCX_", mApicIdtoUidMap[Index].ExtendedInformation.Location2.Module, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // CORE -> Core Number + Status = AmlCodeGenNameInteger ("CORE", mApicIdtoUidMap[Index].ExtendedInformation.Location2.Core, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // THRD -> Thread + Status = AmlCodeGenNameInteger ("THRD", mApicIdtoUidMap[Index].ExtendedInformation.Location2.Thread, CpuInstanceNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + } + + Table = NULL; + // Serialize the tree. + Status = AmlSerializeDefinitionBlock ( + RootNode, + &Table + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: SSDT-PCI: Failed to Serialize SSDT Table Data." + " Status = %r\n", + Status + )); + return (Status); + } + + // Cleanup + Status1 = AmlDeleteTree (RootNode); + if (EFI_ERROR (Status1)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: SSDT-PCI: Failed to cleanup AML tree." + " Status = %r\n", + Status1 + )); + // If Status was success but we failed to delete the AML Tree + // return Status1 else return the original error code, i.e. Status. + if (!EFI_ERROR (Status)) { + return Status1; + } + } + + Status = AppendExistingAcpiTable ( + EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + AMD_DSDT_OEMID, + Table + ); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.c b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/PciSsdt.c similarity index 72% rename from Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.c rename to Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/PciSsdt.c index 5646479d2dc4b786eebfa097663e4db31ed6f933..cfcb99210888922ceeaea214a3298a6968263cb6 100644 --- a/Platform/AMD/AmdPlatformPkg/DynamicTables/Library/Acpi/AcpiSsdtPciLib/AcpiSsdtPciLib.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/PciSsdt.c @@ -1,38 +1,28 @@ /** @file + Creates SSDT table for PCIe devices - Generate ACPI SSDT PCI table for AMD platforms. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent - Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier BSD-2-Clause-Patent **/ - #include #include #include -#include #include #include -#include #include -#include #include -#include -#include #include -#include +#include #include +#include "AcpiCommon.h" -/// "CEDT" CXL Early Discovery Table -#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') -#define MAX_PCI_BUS_NUMBER_PER_SEGMENT 0x100 +#define MAX_PCI_BUS_NUMBER_PER_SEGMENT 0x100 -EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; -EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; -EFI_HANDLE mDriverHandle; +EFI_HANDLE mDriverHandle; /** - Collect and sort the root bridge devices + Create sorted Root Bridge instances from AGESA NBIO resources. Does not include the Root Bridge resources @@ -65,24 +55,13 @@ InternalCollectSortedRootBridges ( LocalRootBridgeCount = 0; Status = GetPcieInfo (&LocalRootBridge, &LocalRootBridgeCount); if (EFI_ERROR (Status) || (LocalRootBridge == NULL) || (LocalRootBridgeCount == 0)) { - DEBUG (( - DEBUG_ERROR, - "%a:%d Cannot obtain Platform PCIe configuration information.\n", - __func__, - __LINE__ - )); + DEBUG ((DEBUG_ERROR, "%a:%d Cannot obtain Platform PCIe configuration information.\n", __func__, __LINE__)); return EFI_NOT_FOUND; } // Sort by PCIe bus number - for (SortedIndex = 0, SortedRb = LocalRootBridge; - SortedIndex < LocalRootBridgeCount; - SortedIndex++, SortedRb++) - { - for (UnsortedIndex = 0, UnsortedRb = LocalRootBridge; - UnsortedIndex < LocalRootBridgeCount; - UnsortedIndex++, UnsortedRb++) - { + for (SortedIndex = 0, SortedRb = LocalRootBridge; SortedIndex < LocalRootBridgeCount; SortedIndex++, SortedRb++) { + for (UnsortedIndex = 0, UnsortedRb = LocalRootBridge; UnsortedIndex < LocalRootBridgeCount; UnsortedIndex++, UnsortedRb++) { if (SortedRb->Object->BaseBusNumber < UnsortedRb->Object->BaseBusNumber) { CopyMem (&TempRootBridge, UnsortedRb, sizeof (AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE)); CopyMem (UnsortedRb, SortedRb, sizeof (AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE)); @@ -124,9 +103,6 @@ InternalInsertRootBridgeInterrupts ( Status = AmlCodeGenNamePackage ("_PRT", NULL, &PrtNode); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - return Status; - } if ((RootBridge->Object->BaseBusNumber == 0) && (RootBridge->Object->Segment == 0)) { // Package () {0x0014FFFF, 0, 0, 16}, // 0 + 16 @@ -137,9 +113,7 @@ InternalInsertRootBridgeInterrupts ( 16, PrtNode ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + ASSERT_EFI_ERROR (Status); // Package () {0x0014FFFF, 1, 0, 17}, // 0 + 17 Status = AmlAddPrtEntry ( @@ -149,9 +123,7 @@ InternalInsertRootBridgeInterrupts ( 17, PrtNode ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + ASSERT_EFI_ERROR (Status); // Package () {0x0014FFFF, 2, 0, 18}, // 0 + 18 Status = AmlAddPrtEntry ( @@ -161,9 +133,7 @@ InternalInsertRootBridgeInterrupts ( 18, PrtNode ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + ASSERT_EFI_ERROR (Status); // Package () {0x0014FFFF, 3, 0, 19}, // 0 + 19 Status = AmlAddPrtEntry ( @@ -173,12 +143,12 @@ InternalInsertRootBridgeInterrupts ( 19, PrtNode ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + ASSERT_EFI_ERROR (Status); } /// Add interrupt for Device 0 function 3 (generic to all function) + /// Value is taken from CRB BIOS + /// Fix the "pcieport 0000:XX:XX.3: can't derive routing for PCI INT A" error Status = AmlAddPrtEntry ( 0xFFFF, 0, @@ -189,9 +159,7 @@ InternalInsertRootBridgeInterrupts ( ASSERT_EFI_ERROR (Status); for (Index = 1; Index <= RootBridge->RootPortCount; Index++) { - if ((RootBridge->RootPort[Index]->PortPresent == 0) && - (RootBridge->RootPort[Index]->Enabled == 0)) - { + if ((RootBridge->RootPort[Index]->PortPresent == 0) && (RootBridge->RootPort[Index]->Enabled == 0)) { continue; } @@ -204,35 +172,33 @@ InternalInsertRootBridgeInterrupts ( (UINT32)(RootBridge->GlobalInterruptStart + RootBridge->RootPort[Index]->EndpointInterruptArray[RootBridge->RootPort[Index]->Function - 1]), PrtNode ); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + ASSERT_EFI_ERROR (Status); } } // Attach the _PRT entry. Status = AmlAttachNode (PciNode, PrtNode); if (EFI_ERROR (Status)) { - goto exit_handler; + AmlDeleteTree (PrtNode); + ASSERT_EFI_ERROR (Status); } PrtNode = NULL; - return Status; + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } -exit_handler: - ASSERT_EFI_ERROR (Status); - AmlDeleteTree (PrtNode); return Status; } /** - Insert Root Bridge resources into AML table + Insert Root Bridge resources into the AML table @param[in] RootBridge - Single Root Bridge instance - @param[in, out] CrsNode - AML tree node + @param[in,out] Crs - AmlLib tree node for CRS - @retval EFI_SUCCESS, various EFI FAILURES. + @retval EFI_SUCCESS, various EFI FAILUREs. **/ EFI_STATUS EFIAPI @@ -241,14 +207,14 @@ InternalInsertRootBridgeResources ( IN OUT AML_OBJECT_NODE_HANDLE CrsNode ) { - EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR *LocalBuffer; + EFI_STATUS Status; EFI_HANDLE *HandleBuffer; + UINTN NumHandles; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Io; - EFI_STATUS Status; - UINTN BaseBusNumber; UINTN Index; - UINTN NumHandles; VOID *Configuration; // Never free this buffer + EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR *LocalBuffer; + UINTN BaseBusNumber; BaseBusNumber = ~(UINTN)0; // Get EFI Pci Root Bridge I/O Protocols @@ -276,19 +242,13 @@ InternalInsertRootBridgeResources ( EFI_OPEN_PROTOCOL_GET_PROTOCOL ); if (EFI_ERROR (Status)) { - FreePool (HandleBuffer); return Status; } if (Io->SegmentNumber == RootBridge->Object->Segment) { Status = Io->Configuration (Io, &Configuration); if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a: ERROR: Retrieve Root Bridge Configuration failed\n", - __func__ - )); - FreePool (HandleBuffer); + DEBUG ((DEBUG_ERROR, "%a: ERROR: Retrieve Root Bridge Configuration failed\n", __func__)); return Status; } @@ -301,7 +261,7 @@ InternalInsertRootBridgeResources ( if ((LocalBuffer->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) && (LocalBuffer->AddrRangeMin == RootBridge->Object->BaseBusNumber)) { - BaseBusNumber = (UINTN)LocalBuffer->AddrRangeMin; + BaseBusNumber = LocalBuffer->AddrRangeMin; break; } } @@ -315,13 +275,8 @@ InternalInsertRootBridgeResources ( } } - FreePool (HandleBuffer); if ((Configuration == NULL) || (LocalBuffer == NULL)) { - DEBUG (( - DEBUG_ERROR, - "%a: ERROR: Retrieve Root Bridge Configuration failed\n", - __func__ - )); + DEBUG ((DEBUG_ERROR, "%a: ERROR: Retrieve Root Bridge Configuration failed\n", __func__)); return EFI_NOT_FOUND; } @@ -335,7 +290,7 @@ InternalInsertRootBridgeResources ( break; } else if (LocalBuffer->Header.Header.Byte == ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR) { if (LocalBuffer->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) { - BaseBusNumber = (UINTN)LocalBuffer->AddrRangeMin; + BaseBusNumber = LocalBuffer->AddrRangeMin; Status = AmlCodeGenRdWordBusNumber ( FALSE, TRUE, @@ -351,9 +306,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } } else if (LocalBuffer->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) { Status = AmlCodeGenRdWordIo ( FALSE, @@ -373,9 +325,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } } else if (LocalBuffer->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { Status = AmlCodeGenRdQWordMemory ( FALSE, @@ -396,9 +345,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } } } else { DEBUG ((DEBUG_ERROR, "%a: ERROR: Invalid Configuration Entry\n", __func__)); @@ -427,9 +373,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } Status = AmlCodeGenRdQWordMemory ( FALSE, @@ -439,7 +382,7 @@ InternalInsertRootBridgeResources ( FALSE, // non cacheable TRUE, 0, - PcdGet32 (PcdIoApicBaseAddress), + PcdGet32 (PcdPcIoApicAddressBase), 0xFED3FFFF, 0x0, 0x140000, @@ -450,9 +393,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } Status = AmlCodeGenRdQWordMemory ( FALSE, @@ -463,9 +403,29 @@ InternalInsertRootBridgeResources ( TRUE, 0, 0xFED45000, + 0xFED811FF, + 0x0, + 0x3C200, + 0, + NULL, + 0, + TRUE, + CrsNode, + NULL + ); + + Status = AmlCodeGenRdQWordMemory ( + FALSE, + TRUE, + TRUE, + TRUE, + FALSE, // non cacheable + TRUE, + 0, + 0xFED81900, 0xFEDC1FFF, 0x0, - 0x7D000, + 0x40700, 0, NULL, 0, @@ -473,9 +433,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } Status = AmlCodeGenRdQWordMemory ( FALSE, @@ -496,9 +453,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } Status = AmlCodeGenRdQWordMemory ( FALSE, @@ -519,9 +473,6 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } Status = AmlCodeGenRdQWordMemory ( FALSE, @@ -542,9 +493,11 @@ InternalInsertRootBridgeResources ( CrsNode, NULL ); - if (EFI_ERROR (Status)) { - return Status; - } + } + + if (EFI_ERROR (Status)) { + Status = EFI_DEVICE_ERROR; + return Status; } return EFI_SUCCESS; @@ -567,22 +520,19 @@ InternalInsertRootPorts ( IN OUT AML_OBJECT_NODE_HANDLE PciNode ) { - AML_METHOD_PARAM MethodParam[7]; - AML_OBJECT_NODE_HANDLE DeviceNode; - AML_OBJECT_NODE_HANDLE DsmMethod; - AML_OBJECT_NODE_HANDLE OstMethod; - AML_OBJECT_NODE_HANDLE PrtNode; + EFI_STATUS Status; CHAR8 NameSeg[5]; CHAR8 RpName[15]; - EFI_STATUS Status; - UINTN Index; UINTN RPIndex; + UINTN Index; + AML_OBJECT_NODE_HANDLE DeviceNode; + AML_OBJECT_NODE_HANDLE PrtNode; + AML_OBJECT_NODE_HANDLE DsmMethod; + AML_OBJECT_NODE_HANDLE OstMethod; + AML_METHOD_PARAM MethodParam[7]; - Status = EFI_SUCCESS; for (RPIndex = 1; RPIndex <= RootBridge->RootPortCount; RPIndex++) { - if ((RootBridge->RootPort[RPIndex]->PortPresent == 0) && - (RootBridge->RootPort[RPIndex]->Enabled == 0)) - { + if ((RootBridge->RootPort[RPIndex]->PortPresent == 0) && (RootBridge->RootPort[RPIndex]->Enabled == 0)) { continue; } @@ -592,6 +542,7 @@ InternalInsertRootPorts ( Status = AmlCodeGenDevice (NameSeg, PciNode, &DeviceNode); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -602,6 +553,7 @@ InternalInsertRootPorts ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -614,15 +566,14 @@ InternalInsertRootPorts ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } } // _DSM and _OST, handling for root port EDR feature. // Device 1 to 4 are external PCIe ports, only include them. - if ((RootBridge->RootPort[RPIndex]->Device > 0) && - (RootBridge->RootPort[RPIndex]->Device < 5)) - { + if ((RootBridge->RootPort[RPIndex]->Device > 0) && (RootBridge->RootPort[RPIndex]->Device < 5)) { DEBUG (( DEBUG_INFO, "%a:Add EDR support for Uid 0x%x Addr 0x%x\n", @@ -647,6 +598,7 @@ InternalInsertRootPorts ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -657,6 +609,7 @@ InternalInsertRootPorts ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -671,6 +624,7 @@ InternalInsertRootPorts ( &DsmMethod ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -698,6 +652,7 @@ InternalInsertRootPorts ( DsmMethod ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -712,6 +667,7 @@ InternalInsertRootPorts ( &OstMethod ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -733,15 +689,14 @@ InternalInsertRootPorts ( OstMethod ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } } // Build Root Port _PRT entry and insert in main ACPI Object list Status = AmlCodeGenNamePackage ("_PRT", NULL, &PrtNode); - if (EFI_ERROR (Status)) { - return Status; - } + ASSERT_EFI_ERROR (Status); for (Index = 0; Index <= 3; Index++) { Status = AmlAddPrtEntry ( @@ -752,8 +707,7 @@ InternalInsertRootPorts ( PrtNode ); if (EFI_ERROR (Status)) { - AmlDeleteTree (PrtNode); - return Status; + ASSERT_EFI_ERROR (Status); } } @@ -761,21 +715,23 @@ InternalInsertRootPorts ( Status = AmlAttachNode (DeviceNode, PrtNode); if (EFI_ERROR (Status)) { AmlDeleteTree (PrtNode); - return Status; + ASSERT_EFI_ERROR (Status); } PrtNode = NULL; } + if (EFI_ERROR (Status)) { + Status = EFI_DEVICE_ERROR; + } + return Status; } /** - Insert CXL Root Bridge into the AML table + Insert CXL Root Bridge Port into the AML table - @param[in] RootBridgeHead - RootBridge information pointer - @param[in] RootBridgeCount - Number of root bridges - @param[in,out] PciNode - AmlLib table node + @param[in,out] PciNode - AmlLib table node @retval EFI_SUCCESS, various EFI FAILUREs. **/ @@ -789,16 +745,16 @@ InternalInsertCxlRootBridge ( { AMD_PCI_ADDR PciAddr; AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE *RootBridge; - AML_METHOD_PARAM MethodParam[7]; AML_OBJECT_NODE_HANDLE CrsNode; AML_OBJECT_NODE_HANDLE DeviceNode; - AML_OBJECT_NODE_HANDLE OscMethod; AML_OBJECT_NODE_HANDLE PackageNode; CHAR8 NameSeg[5]; EFI_STATUS Status; UINT32 EisaId; UINT8 DevIndex; UINT8 Index; + AML_METHOD_PARAM MethodParam[7]; + AML_OBJECT_NODE_HANDLE OscMethod; DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); ZeroMem ((VOID *)&PciAddr, sizeof (PciAddr)); @@ -808,7 +764,6 @@ InternalInsertCxlRootBridge ( // the ACPI Table // DevIndex = 0; - Status = EFI_SUCCESS; for (Index = 0, RootBridge = RootBridgeHead; Index < RootBridgeCount; Index++, RootBridge++) { if ((RootBridge->CxlCount == 0) || (RootBridge->CxlPortInfo.IsCxl2 == TRUE)) { continue; @@ -825,38 +780,42 @@ InternalInsertCxlRootBridge ( Status = AmlCodeGenDevice (NameSeg, PciNode, &DeviceNode); // RootBridge if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } Status = AmlCodeGenNameString ("_HID", "ACPI0016", DeviceNode, NULL); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } Status = AmlCodeGenNamePackage ("_CID", DeviceNode, &PackageNode); - if (EFI_ERROR (Status)) { - return Status; - } + ASSERT_EFI_ERROR (Status); // Name (_CID, EISAID("PNP0A03")) Status = AmlGetEisaIdFromString ("PNP0A03", &EisaId); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } - Status = AmlAddIntegerToNamedPackage (EisaId, PackageNode); + Status = AmlAddIntegerPackageEntry (EisaId, PackageNode); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } // Name (_CID, EISAID("PNP0A03")) Status = AmlGetEisaIdFromString ("PNP0A08", &EisaId); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } - Status = AmlAddIntegerToNamedPackage (EisaId, PackageNode); + Status = AmlAddIntegerPackageEntry (EisaId, PackageNode); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -868,12 +827,14 @@ InternalInsertCxlRootBridge ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } // Name (_UID, ) Status = AmlCodeGenNameInteger ("_UID", DevIndex, DeviceNode, NULL); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -885,6 +846,7 @@ InternalInsertCxlRootBridge ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -896,6 +858,7 @@ InternalInsertCxlRootBridge ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } @@ -910,24 +873,27 @@ InternalInsertCxlRootBridge ( NULL ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } // Name (_CRS, ) Status = AmlCodeGenNameResourceTemplate ("_CRS", DeviceNode, &CrsNode); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } Status = InternalInsertRootBridgeResources (RootBridge, CrsNode); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } /// Create AML code for below method /// Method (_OSC, 4, NotSerialized, 4) // _OSC: Operating System Capabilities /// { - /// \_SB.OSCI (Arg0, Arg1, Arg2, Arg3) + /// \_SB.OSCI (Arg0, Arg1, Arg2, Arg3, _ADR, _BBN) /// } Status = AmlCodeGenMethodRetNameString ( "_OSC", @@ -939,31 +905,45 @@ InternalInsertCxlRootBridge ( &OscMethod ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } // fill the AML_METHOD_PARAM structure to call the \\_SB.OSCI method ZeroMem (MethodParam, sizeof (MethodParam)); MethodParam[0].Type = AmlMethodParamTypeArg; - MethodParam[0].Data.Arg = 0x0; // Arg0 is the first argument to the method + MethodParam[0].Data.Arg = 0x0; // Arg0 is the first argument to the method MethodParam[1].Type = AmlMethodParamTypeArg; - MethodParam[1].Data.Arg = 0x1; // Arg1 is the second argument to the method + MethodParam[1].Data.Arg = 0x1; // Arg1 is the second argument to the method MethodParam[2].Type = AmlMethodParamTypeArg; - MethodParam[2].Data.Arg = 0x2; // Arg2 is the third argument to the method + MethodParam[2].Data.Arg = 0x2; // Arg2 is the third argument to the method MethodParam[3].Type = AmlMethodParamTypeArg; - MethodParam[3].Data.Arg = 0x3; // Arg3 is the fourth argument to the method + MethodParam[3].Data.Arg = 0x3; // Arg3 is the fourth argument to the method + // _ADR is the fifth argument to the method + MethodParam[4].Type = AmlMethodParamTypeInteger; + MethodParam[4].Data.Integer = (RootBridge->CxlPortInfo.EndPointBDF.Address.Device << 16) + + RootBridge->CxlPortInfo.EndPointBDF.Address.Function; + // _BBN is the sixth argument to the method + MethodParam[5].Type = AmlMethodParamTypeInteger; + MethodParam[5].Data.Integer = RootBridge->CxlPortInfo.EndPointBDF.Address.Bus; // call the \\_SB.OSCI method Status = AmlCodeGenInvokeMethod ( "\\_SB.OSCI", - 4, + 6, MethodParam, OscMethod ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } } + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Failed with Status: %r, Not Critical return SUCCESS\n", __func__, Status)); + Status = EFI_SUCCESS; + } + return Status; } @@ -1015,171 +995,77 @@ InternalInsertPciExpressBaseSize ( return EFI_SUCCESS; } -/** - Locates an existing ACPI Table - - @param[in] Signature - The Acpi table signature - @param[in] OemTableId - The Acpi table OEM Table ID. Ignored if 0 - @param[out] Table - Table if Found or NULL - - @retval EFI_SUCCESS, various EFI FAILUREs. -**/ -EFI_STATUS -EFIAPI -GetExistingAcpiTable ( - IN UINT32 Signature, - IN UINT64 OemTableId, - OUT EFI_ACPI_SDT_HEADER **Table - ) -{ - EFI_ACPI_SDT_HEADER *LocalTable; - EFI_ACPI_TABLE_VERSION LocalVersion; - EFI_STATUS Status; - UINTN Index; - UINTN LocalTableKey; - - Status = EFI_NOT_FOUND; - *Table = NULL; - - for (Index = 0; ; Index++) { - Status = mAcpiSdtProtocol->GetAcpiTable (Index, &LocalTable, &LocalVersion, &LocalTableKey); - if (EFI_ERROR (Status)) { - return Status; - } - - if (!(LocalTable->Signature == Signature)) { - continue; - } - - // Accept table if OemTableId is zero. - if ((OemTableId == 0) || - (CompareMem (&LocalTable->OemTableId, &OemTableId, 8) == 0)) - { - *Table = LocalTable; - return EFI_SUCCESS; - } - } -} - /** Install PCI devices scoped under \_SB into DSDT Determine all the PCI Root Bridges and PCI root ports and install resources including needed _HID, _CID, _UID, _ADR, _CRS and _PRT Nodes. + @param[in] ImageHandle - Standard UEFI entry point Image Handle + @param[in] SystemTable - Standard UEFI entry point System Table + @retval EFI_SUCCESS, various EFI FAILUREs. **/ EFI_STATUS -GenerateAcpiSsdtPciTable ( - VOID +EFIAPI +InstallPciAcpi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) { AMD_PCI_ADDR PciAddr; AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE *RootBridge; AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE *RootBridgeHead; - AML_METHOD_PARAM MethodParam[7]; AML_OBJECT_NODE_HANDLE AmdmNode; AML_OBJECT_NODE_HANDLE CrsNode; - AML_OBJECT_NODE_HANDLE CxldNode; - AML_OBJECT_NODE_HANDLE DsmMethod; - AML_OBJECT_NODE_HANDLE OscMethod; AML_OBJECT_NODE_HANDLE PackageNode; AML_OBJECT_NODE_HANDLE PciNode; AML_OBJECT_NODE_HANDLE ScopeNode; + AML_OBJECT_NODE_HANDLE CxldNode; + AML_OBJECT_NODE_HANDLE DsmMethod; AML_ROOT_NODE_HANDLE RootNode; CHAR8 AslName[AML_NAME_SEG_SIZE + 1]; EFI_ACPI_DESCRIPTION_HEADER *Table; - EFI_ACPI_SDT_HEADER *DsdtTable; - EFI_ACPI_SDT_HEADER *ReplacementAcpiTable; EFI_ACPI_SDT_HEADER *SdtTable; - EFI_ACPI_TABLE_VERSION DsdtVersion; EFI_STATUS Status; EFI_STATUS Status1; UINT32 EisaId; - UINT32 ReplacementAcpiTableLength; - UINTN DsdtTableKey; UINTN GlobalInterruptBase; - UINTN Index; UINTN RbIndex; UINTN RootBridgeCount; - UINTN TableHandle; - - DEBUG ((DEBUG_INFO, "Generating ACPI SSDT PCI Table.\n")); - - // Get Acpi Table Protocol - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID **)&mAcpiTableProtocol - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // Get Acpi SDT Protocol - Status = gBS->LocateProtocol ( - &gEfiAcpiSdtProtocolGuid, - NULL, - (VOID **)&mAcpiSdtProtocol - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // Find the DSDT table and append to it - for (Index = 0; ; Index++) { - Status = mAcpiSdtProtocol->GetAcpiTable ( - Index, - &DsdtTable, - &DsdtVersion, - &DsdtTableKey - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "ERROR: ACPI DSDT table not found. Status(%r)\n", - Status - )); - return Status; - } + AML_METHOD_PARAM MethodParam[7]; + AML_OBJECT_NODE_HANDLE OscMethod; + AML_OBJECT_NODE_HANDLE CdsmMethod; - if (DsdtTable->Signature == EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { - break; - } - } + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); Status = AmlCodeGenDefinitionBlock ( "SSDT", "AMD ", - "PCIE DEV", + "AmdTable", 0x00, &RootNode ); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - return Status; - } ZeroMem ((VOID *)&PciAddr, sizeof (PciAddr)); + mDriverHandle = ImageHandle; GlobalInterruptBase = 0; Status = InternalCollectSortedRootBridges (&RootBridgeHead, &RootBridgeCount); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = AmlCodeGenScope ("\\_SB_", RootNode, &ScopeNode); // START: Scope (\_SB) if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Create Root Bridge PCXX devices - for (RbIndex = 0, RootBridge = RootBridgeHead; - RbIndex < RootBridgeCount; - RbIndex++, RootBridge++) - { + for (RbIndex = 0, RootBridge = RootBridgeHead; RbIndex < RootBridgeCount; RbIndex++, RootBridge++) { GlobalInterruptBase = RootBridge->GlobalInterruptStart; // Make sure there is always PCI0 since this is a defacto standard. And // therefore PCI0-PCIF and then PC10-PCFF @@ -1191,69 +1077,80 @@ GenerateAcpiSsdtPciTable ( Status = AmlCodeGenDevice (AslName, ScopeNode, &PciNode); // RootBridge if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } if ((RootBridge->CxlCount > 0) && (RootBridge->CxlPortInfo.IsCxl2 == TRUE)) { Status = AmlCodeGenNameString ("_HID", "ACPI0016", PciNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = AmlCodeGenNamePackage ("_CID", PciNode, &PackageNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); } // Name (_CID, EISAID("PNP0A03")) Status = AmlGetEisaIdFromString ("PNP0A03", &EisaId); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } - Status = AmlAddIntegerToNamedPackage (EisaId, PackageNode); + Status = AmlAddIntegerPackageEntry (EisaId, PackageNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_CID, EISAID("PNP0A03")) Status = AmlGetEisaIdFromString ("PNP0A08", &EisaId); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } - Status = AmlAddIntegerToNamedPackage (EisaId, PackageNode); + Status = AmlAddIntegerPackageEntry (EisaId, PackageNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } } else { // Name (_HID, EISAID("PNP0A08")) Status = AmlGetEisaIdFromString ("PNP0A08", &EisaId); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = AmlCodeGenNameInteger ("_HID", EisaId, PciNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_CID, EISAID("PNP0A03")) Status = AmlGetEisaIdFromString ("PNP0A03", &EisaId); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = AmlCodeGenNameInteger ("_CID", EisaId, PciNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } } // Name (_UID, ) Status = AmlCodeGenNameInteger ("_UID", RootBridge->Uid, PciNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_BBN, ) @@ -1264,7 +1161,20 @@ GenerateAcpiSsdtPciTable ( NULL ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Name (_ADR, 0); 0 address for root bridges + Status = AmlCodeGenNameInteger ( + "_ADR", + 0, + PciNode, + NULL + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_SEG, ) @@ -1275,7 +1185,8 @@ GenerateAcpiSsdtPciTable ( NULL ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_PXM, SocketId>) @@ -1289,39 +1200,37 @@ GenerateAcpiSsdtPciTable ( NULL ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_CRS, ) Status = AmlCodeGenNameResourceTemplate ("_CRS", PciNode, &CrsNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = InternalInsertRootBridgeResources (RootBridge, CrsNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_PRT, ) Status = InternalInsertRootBridgeInterrupts (RootBridge, &GlobalInterruptBase, PciNode); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + ASSERT_EFI_ERROR (Status); // Create Root Port PXXX devices // Name (_ADR, ) // Name (_PRT, ) // Needs to be offset by previous IOAPICs interrupt count - Status = InternalInsertRootPorts (RootBridge, RootBridge->GlobalInterruptStart, PciNode); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + InternalInsertRootPorts (RootBridge, RootBridge->GlobalInterruptStart, PciNode); /// AML code to generate _OSC method /// Method (_OSC, 4, NotSerialized, 4) // _OSC: Operating System Capabilities /// { - /// \_SB.OSCI (Arg0, Arg1, Arg2, Arg3) + /// \_SB.OSCI (Arg0, Arg1, Arg2, Arg3, _ADR, _BBN) /// } Status = AmlCodeGenMethodRetNameString ( "_OSC", @@ -1333,11 +1242,57 @@ GenerateAcpiSsdtPciTable ( &OscMethod ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // fill the AML_METHOD_PARAM structure to call the \\_SB.OSCI method ZeroMem (MethodParam, sizeof (MethodParam)); + MethodParam[0].Type = AmlMethodParamTypeArg; + MethodParam[0].Data.Arg = 0x0; // Arg0 is the first argument to the method + MethodParam[1].Type = AmlMethodParamTypeArg; + MethodParam[1].Data.Arg = 0x1; // Arg1 is the second argument to the method + MethodParam[2].Type = AmlMethodParamTypeArg; + MethodParam[2].Data.Arg = 0x2; // Arg2 is the third argument to the method + MethodParam[3].Type = AmlMethodParamTypeArg; + MethodParam[3].Data.Arg = 0x3; // Arg3 is the fourth argument to the method + MethodParam[4].Type = AmlMethodParamTypeInteger; + MethodParam[4].Data.Integer = 0; // _ADR is the fifth argument to the method + MethodParam[5].Type = AmlMethodParamTypeInteger; + MethodParam[5].Data.Integer = RootBridge->Object->BaseBusNumber; // _BBN is the sixth argument to the method + // call the \\_SB.OSCI method + Status = AmlCodeGenInvokeMethod ( + "\\_SB.OSCI", + 6, + MethodParam, + OscMethod + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + /// AML code to generate _DSM method + /// Method (_DSM, 4, Serialized) // _DSM device specific method + /// { + /// \_SB.CDSM (Arg0, Arg1, Arg2, Arg3) + /// } + Status = AmlCodeGenMethodRetNameString ( + "_DSM", + NULL, + 4, + TRUE, + 0, + PciNode, + &CdsmMethod + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // fill the AML_METHOD_PARAM structure to call the \\_SB.CDSM method + ZeroMem (MethodParam, sizeof (MethodParam)); MethodParam[0].Type = AmlMethodParamTypeArg; MethodParam[0].Data.Arg = 0x0; // Arg0 is the first argument to the method MethodParam[1].Type = AmlMethodParamTypeArg; @@ -1348,16 +1303,20 @@ GenerateAcpiSsdtPciTable ( MethodParam[3].Data.Arg = 0x3; // Arg3 is the fourth argument to the method // call the \\_SB.OSCI method Status = AmlCodeGenInvokeMethod ( - "\\_SB.OSCI", + "\\_SB.CDSM", 4, MethodParam, - OscMethod + CdsmMethod ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } } + // + // Look for CEDT table, As Table Type 1 (CFMWS) is needed for the CXL DSM method + // Status = GetExistingAcpiTable ( CXL_EARLY_DISCOVERY_TABLE_SIGNATURE, 0, @@ -1367,13 +1326,15 @@ GenerateAcpiSsdtPciTable ( // CXL Root Device Specific Methods (_DSM) Status = AmlCodeGenDevice ("CXLD", ScopeNode, &CxldNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // _DSM Functions that are associated with the CXL Root Device (HID="ACPI0017") Status = AmlCodeGenNameString ("_HID", "ACPI0017", CxldNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Create a _DSM method @@ -1387,7 +1348,8 @@ GenerateAcpiSsdtPciTable ( &DsmMethod ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // fill the AML_METHOD_PARAM structure to call the \\_SB.HDSM method @@ -1411,7 +1373,8 @@ GenerateAcpiSsdtPciTable ( DsmMethod ); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } } @@ -1419,42 +1382,45 @@ GenerateAcpiSsdtPciTable ( // CXL device are added as Root Bridges but are not part of // the AMD PCI Resource Protocol // - Status = InternalInsertCxlRootBridge (RootBridgeHead, RootBridgeCount, ScopeNode); - if (EFI_ERROR (Status)) { - goto exit_handler; - } + InternalInsertCxlRootBridge (RootBridgeHead, RootBridgeCount, ScopeNode); // Add Pcie Base Size Status = AmlCodeGenDevice ("AMDM", ScopeNode, &AmdmNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_HID, EISAID("PNP0C02")) Status = AmlGetEisaIdFromString ("PNP0C02", &EisaId); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = AmlCodeGenNameInteger ("_HID", EisaId, AmdmNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } // Name (_UID, ) Status = AmlCodeGenNameInteger ("_UID", 0, AmdmNode, NULL); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = AmlCodeGenNameResourceTemplate ("_CRS", AmdmNode, &CrsNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Status = InternalInsertPciExpressBaseSize (CrsNode); if (EFI_ERROR (Status)) { - goto exit_handler; + ASSERT_EFI_ERROR (Status); + return Status; } Table = NULL; @@ -1470,7 +1436,7 @@ GenerateAcpiSsdtPciTable ( " Status = %r\n", Status )); - goto exit_handler; + return (Status); } // Cleanup @@ -1491,157 +1457,11 @@ GenerateAcpiSsdtPciTable ( FreePool (RootBridgeHead); - // Update the Table header - Table->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId); - Table->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision); - CopyMem (&Table->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (Table->OemId)); - - // Calculate new DSDT Length and allocate space - ReplacementAcpiTableLength = DsdtTable->Length + (UINT32)(Table->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)); - ReplacementAcpiTable = AllocatePool (ReplacementAcpiTableLength); - if (ReplacementAcpiTable == NULL) { - ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); - DEBUG ((DEBUG_ERROR, "ERROR: Unable to allocate Replacement Table space.\n")); - FreePool (Table); - return EFI_OUT_OF_RESOURCES; - } - - // Copy the old DSDT to the new buffer - CopyMem (ReplacementAcpiTable, DsdtTable, DsdtTable->Length); - - // Append new data to DSDT - CopyMem ( - (UINT8 *)ReplacementAcpiTable + DsdtTable->Length, - (UINT8 *)Table + sizeof (EFI_ACPI_DESCRIPTION_HEADER), - Table->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - ); - - ReplacementAcpiTable->Length = ReplacementAcpiTableLength; - - // Uninstall the original DSDT - Status = mAcpiTableProtocol->UninstallAcpiTable ( - mAcpiTableProtocol, - DsdtTableKey - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - DEBUG (( - DEBUG_ERROR, - "ERROR: Unable to uninstall original DSDT table. Status(%r)\n", - Status - )); - } else { - // Install ACPI table - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - ReplacementAcpiTable, - ReplacementAcpiTableLength, - &TableHandle - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - DEBUG (( - DEBUG_ERROR, - "ERROR: Unable to re-install ACPI DSDT Table. Status(%r)\n", - Status - )); - } - } - - FreePool (ReplacementAcpiTable); - FreePool (Table); - return Status; - -exit_handler: - ASSERT_EFI_ERROR (Status); - AmlDeleteTree (RootNode); - return Status; -} - -/** - Event notification function for AcpiSsdtPciLib. - - @param[in] Event Event whose notification function is being invoked. - @param[in] Context Pointer to the notification function's context, which is - implementation-dependent. -**/ -STATIC -VOID -EFIAPI -AcpiSsdtPciLibEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - /// Close the Event - gBS->CloseEvent (Event); - - /// Update the PCI SSDT Table - GenerateAcpiSsdtPciTable (); -} - -/** - Implementation of AcpiSsdtPciLibConstructor for AMD platforms. - This is library constructor for AcpiSsdtPciLib. - - @param[in] ImageHandle Image handle of the loaded driver. - @param[in] SystemTable Pointer to the EFI System Table. - - @retval EFI_SUCCESS Successfully generated ACPI SSDT PCI Table. - @retval Others Failed to generate ACPI SSDT PCI Table. -**/ -EFI_STATUS -EFIAPI -AcpiSsdtPciLibConstructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_EVENT Event; - - mDriverHandle = ImageHandle; - - // - // Register notify function - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - AcpiSsdtPciLibEvent, - NULL, - &gEfiEventReadyToBootGuid, - &Event - ); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a: Failed to create gEfiEventReadyToBootGuid event. Status(%r)\n", - __func__, - Status - )); - } + Status = AppendExistingAcpiTable ( + EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + AMD_DSDT_OEMID, + Table + ); return Status; } - -/** - Implementation of AcpiSsdtPciLibDestructor for AMD platforms. - This is library destructor for AcpiSsdtPciLib. - - @param[in] ImageHandle Image handle of the loaded driver. - @param[in] SystemTable Pointer to the EFI System Table. - - @retval EFI_SUCCESS Successfully destroyed ACPI SSDT PCI Table. - @retval Others Failed to destroy ACPI SSDT PCI Table. -**/ -EFI_STATUS -EFIAPI -AcpiSsdtPciLibDestructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - return EFI_SUCCESS; -} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/Spmi.c b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/Spmi.c new file mode 100644 index 0000000000000000000000000000000000000000..21d179528ba0db40b33c9d78657e878f29e8ac8a --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Acpi/AcpiCommon/Spmi.c @@ -0,0 +1,111 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include "AcpiCommon.h" + +EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE gSpmi = { + { + EFI_ACPI_6_5_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE, + sizeof (EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE), + 5, + // + // Checksum will be updated at runtime + // + 0x00, + // + // It is expected that these values will be programmed at runtime + // + { 'A', 'M', 'D', 'I', 'N', 'C' }, + SIGNATURE_64 ('S', 'P', 'M', 'I', 'T', 'a', 'b', 'l'), // updated during installation + 0x00, // Spmi revision, + SIGNATURE_32 ('A', 'M', 'D', ' '), + 0x00 // OEM Revision + }, + 0x00, // Interface type + 0x01, // Reserved + 0x0200, // IPMI specification revision + 0x00, // InterruptType + 0x00, // Gpe + 0x00, // Reserved2 + 0x00, // PciDeviceFlag or _UID + 0x00, // GobalSystemInterrupt + { // BaseAddress + EFI_ACPI_6_5_SYSTEM_IO, + 0x08, // BASE_ADDRESS_BIT_WIDTH, + 0x00, // BASE_ADDRESS_BIT_OFFSET, + 0x00, // RESERVED_BYTE, + 0x0CA2 // BASE_ADDRESS_ADDRESS, + }, + { + { 0x00000000 } + }, + 0x00 +}; + +/** + Installs the ACPI SPMI Table to the System Table. +**/ +VOID +EFIAPI +InstallAcpiSpmiTable ( + VOID + ) +{ + UINT64 AcpiTableOemId; + UINTN TurnKey; + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTablProtocol; + + if (!PcdGet8 (PcdIpmiInterfaceType)) { + return; + } + + Status = gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&AcpiTablProtocol + ); + if (EFI_ERROR (Status)) { + // return if ACPI protocol not found + return; + } + + DEBUG ((DEBUG_ERROR, "Installing ACPI SPMI Table.\n")); + // OEM info + CopyMem ( + (VOID *)&gSpmi.Header.OemId, + PcdGetPtr (PcdAcpiDefaultOemId), + sizeof (gSpmi.Header.OemId) + ); + + AcpiTableOemId = PcdGet64 (PcdAcpiDefaultOemTableId); + CopyMem ( + (VOID *)&gSpmi.Header.OemTableId, + (VOID *)&AcpiTableOemId, + sizeof (gSpmi.Header.OemTableId) + ); + + gSpmi.Header.OemRevision = 0; + gSpmi.Header.CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId); + gSpmi.Header.CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision); + + gSpmi.InterfaceType = PcdGet8 (PcdIpmiInterfaceType); + gSpmi.BaseAddress.Address = PcdGet16 (PcdIpmiKcsIoBaseAddress); + // + // Add table + // + Status = AcpiTablProtocol->InstallAcpiTable ( + AcpiTablProtocol, + &gSpmi, + sizeof (EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE), + &TurnKey + ); + ASSERT_EFI_ERROR (Status); +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf index 6cfb1dcceba1176c1a8747ba6f2eda0adf81f69e..f689036b41a815c4eb86b6251fc9a745878102e7 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf @@ -3,7 +3,7 @@ # This module provides better performance of BlockToConfig and ConfigToBlock # functions. # -# Copyright (C) 2021 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRoutingEntry.c b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRoutingEntry.c index 29246ac1b22f569cdf9d10cc2760238450eaef1f..7652af165b56552eb0dbee6c4089bdaf554e658f 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRoutingEntry.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRoutingEntry.c @@ -2,7 +2,7 @@ AMD implementation of interface functions for EFI_HII_CONFIG_ROUTING_PROTOCOL. This module overrides BlockToConfig and ConfigToBlock for the better performance. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.c b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.c index 89d1ddbdf34930d6f50213deb7824623826f7b0c..b5ccb3f22cbedc81ba6bb58cc592dc3de9771781 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.c @@ -4,14 +4,14 @@ functions. Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include "AmdHiiConfigRouting.h" -#include HII_ELEMENT gElementInfo[] = { { L"GUID=", FIXED_STR_LEN (L"GUID=") }, @@ -22,9 +22,6 @@ HII_ELEMENT gElementInfo[] = { { L"VALUE=", FIXED_STR_LEN (L"VALUE=") } }; -CHAR16 mAmpersand[] = L"&"; -CHAR16 mAmpersandValueEqual[] = L"&VALUE="; - /** Converts the unicode character of the string from uppercase to lowercase. This is a internal function. @@ -254,10 +251,6 @@ GetValueOfNumber ( while (*EndOfString != L'\0' && *EndOfString != L'&') { EndOfString++; - if (StringLength == (MAX_UINTN - 1)) { - return EFI_OUT_OF_RESOURCES; - } - StringLength++; } @@ -291,11 +284,7 @@ GetValueOfNumber ( if ((Index & 1) == 0) { This->NumberPtr[Index / 2] = DigitUint8; } else { - if (((DigitUint8 << 4) + This->NumberPtr[Index / 2]) > MAX_UINT8) { - return EFI_OUT_OF_RESOURCES; - } - - This->NumberPtr[Index / 2] = (UINT8)(UINTN)(((DigitUint8 << 4) + This->NumberPtr[Index / 2]) & 0xFF); + This->NumberPtr[Index / 2] = (UINT8)((DigitUint8 << 4) + This->NumberPtr[Index / 2]); } } @@ -391,18 +380,6 @@ HiiStringSetMinBufferSize ( UINTN ThisStringSize; EFI_STRING NewAlloc; - if (This == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (This->StringLength == (MAX_UINTN - 1)) { - return EFI_OUT_OF_RESOURCES; - } - - if (This->StringLength >= (MAX_UINTN - 1) / sizeof (CHAR16)) { - return EFI_OUT_OF_RESOURCES; - } - ThisStringSize = (This->StringLength + 1) * sizeof (CHAR16); if (Size > This->PrivateBufferSize) { @@ -448,7 +425,7 @@ HiiStringAppend ( ThisStringSize = (This->StringLength + 1) * sizeof (CHAR16); StringSize = HII_STR_SIZE (String); - if ((ThisStringSize > (MAX_UINTN - StringSize)) || ((ThisStringSize + StringSize) > This->PrivateBufferSize)) { + if (ThisStringSize + StringSize > This->PrivateBufferSize) { MaxLen = (ThisStringSize + StringSize) * 2; Status = HiiStringSetMinBufferSize (This, MaxLen); if (EFI_ERROR (Status)) { @@ -477,9 +454,9 @@ HiiStringAppend ( **/ EFI_STATUS HiiStringAppendValue ( - IN OUT HII_STRING *This, - IN CONST UINT8 *Number, - IN UINTN Length + IN OUT HII_STRING *This, + IN UINT8 *Number, + IN UINTN Length ) { EFI_STATUS Status; @@ -495,20 +472,8 @@ HiiStringAppendValue ( return EFI_INVALID_PARAMETER; } - if ((This == NULL) || (Number == NULL)) { - return EFI_INVALID_PARAMETER; - } - - if (This->StringLength >= (MAX_UINTN - 1) / sizeof (CHAR16)) { - return EFI_OUT_OF_RESOURCES; - } - ThisStringSize = (This->StringLength + 1) * sizeof (CHAR16); - if (ThisStringSize > (MAX_UINTN - Length * 2 * sizeof (CHAR16))) { - return EFI_OUT_OF_RESOURCES; - } - if (ThisStringSize + Length * 2 * sizeof (CHAR16) > This->PrivateBufferSize) { MaxLen = (ThisStringSize + Length * 2 * sizeof (CHAR16)) * 2; // Double requested string length. Status = HiiStringSetMinBufferSize (This, MaxLen); @@ -691,15 +656,15 @@ HiiBlockToConfig ( OUT EFI_STRING *Progress ) { - EFI_STATUS Status; - EFI_STRING StringPtr; - EFI_STRING OrigPtr; - CHAR16 CharBackup; - UINTN Offset; - UINTN Width; - CONST UINT8 *Value; - HII_STRING HiiString; - HII_NUMBER HiiNumber; + EFI_STATUS Status; + EFI_STRING StringPtr; + EFI_STRING OrigPtr; + CHAR16 CharBackup; + UINTN Offset; + UINTN Width; + UINT8 *Value; + HII_STRING HiiString; + HII_NUMBER HiiNumber; if ((This == NULL) || (Progress == NULL) || (Config == NULL)) { return EFI_INVALID_PARAMETER; @@ -828,7 +793,7 @@ HiiBlockToConfig ( goto Exit; } - Value = Block + Offset; + Value = (UINT8 *)Block + Offset; CharBackup = *StringPtr; *StringPtr = L'\0'; @@ -841,7 +806,7 @@ HiiBlockToConfig ( *StringPtr = CharBackup; // End of section of string OrigPtr - Status = HiiStringAppend (&HiiString, mAmpersandValueEqual); + Status = HiiStringAppend (&HiiString, L"&VALUE="); if (EFI_ERROR (Status)) { *Progress = ConfigRequest; // Out of memory goto Exit; @@ -865,7 +830,7 @@ HiiBlockToConfig ( break; } - Status = HiiStringAppend (&HiiString, mAmpersand); + Status = HiiStringAppend (&HiiString, L"&"); if (EFI_ERROR (Status)) { *Progress = ConfigRequest; // Out of memory goto Exit; diff --git a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.h b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.h index bce606f7dd20ea68884dc33936538646691f087b..84dfc78c57459d3b98f7f3136ec0867519604cd4 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.h +++ b/Platform/AMD/AmdPlatformPkg/Universal/HiiConfigRouting/AmdHiiConfigRouting.h @@ -2,7 +2,7 @@ Provide optimized implementation of HII_CONFIG_ROUTING Protocol functions HiiBlockToConfig and HiiConfigToBlock. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogo.idf b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogo.idf index 2d12b78c5c2455df7e834be4f425ea153d8eb6b1..91bc4bf9ead5eb4bb37f889ac89bc025afdf7090 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogo.idf +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogo.idf @@ -1,7 +1,7 @@ // /** @file // Platform Logo image definition file. // -// Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +// Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogoDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogoDxe.inf index 6a3bbb8d5b57f92bdbd3f15074bcce13e460a8ca..6992f4b685636673ef6a5f2d4f237c97bc6d7d8e 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogoDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/JpegLogoDxe.inf @@ -1,7 +1,7 @@ ## @file # The default logo JPEG picture shown on setup screen. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c index 69fa1dc0e578d766ba0803e9e42b7818d0fe4d24..2d5edd4447e5f2925baf7b8d4f4f0909b11e7f16 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.c @@ -2,7 +2,7 @@ Logo DXE Driver, install Edk2 Platform Logo protocol. Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
- Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.h b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.h index 7f72f5f57bdd55062dffa296dc1336d53053c524..de8a2c384284e4eeff2d1a9a2448b0fd895d8274 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.h +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.h @@ -1,7 +1,7 @@ /** @file LogoDxe header file - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.idf b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.idf index 3ef07a229f8fe646e38aa9c4e5b71010643bbf2c..42fe151177ae7cf0f6fd34f5f7b376afffa4df77 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.idf +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/Logo.idf @@ -1,7 +1,7 @@ // /** @file // Platform Logo image definition file. // -// Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +// Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf index ea07e15d1a233d3e6959f1212caf54d47d7be00e..611bedbdfdc3a5b41ea82659952cbf4d32878a9a 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf @@ -1,7 +1,7 @@ ## @file # The default logo bitmap picture shown on setup screen. # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf index 3735ad0b66fd6bf702b37a3cdffb3f1be2241317..5e80e3ce1e59a0ee5884cc9eee812599d75acc21 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3Logo.idf @@ -1,7 +1,7 @@ // /** @file // Platform Logo image definition file. // -// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // diff --git a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf index be4c5ad59d4f3cd75839c8d86affe412fe8c32d0..33eaeb32340332171e078082c2bfae936a42ca89 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/LogoDxe/S3LogoDxe.inf @@ -1,7 +1,7 @@ ## @file # The default logo bitmap picture shown on setup screen. # -# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.c b/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.c index 071bfe5b68fb5e690d74dcdd13b6a7fb43500ac5..95d89bde55104b9d554228de1e83f99f4792bd5c 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.c @@ -6,7 +6,7 @@ Copyright (c) 2021, ARM Ltd. All rights reserved.
Copyright (c) 2021, Semihalf All rights reserved.
Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
- Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf b/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf index 345fbdc6aee32d48ca25842257f6dedb9a978af2..8d28a9aaf36816751904a2b7913cc8310ef723ac 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf @@ -3,7 +3,7 @@ # # Copyright (c) 2021, ARM Ltd. All rights reserved.
# Copyright (c) 2021, Semihalf All rights reserved.
-# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/DefaultLomDevicePath.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/DefaultLomDevicePath.c new file mode 100644 index 0000000000000000000000000000000000000000..a3c67235eddd52e0d0bf02173ee4d7b8f4fc9974 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/DefaultLomDevicePath.c @@ -0,0 +1,121 @@ +/***************************************************************************** + * Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + * +*******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "SmbiosCommon.h" +#include +#include + +EFI_HANDLE mBoardBdsHandle = NULL; +BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL mBootDevicePathProtocol; + +/** + Find the Lan-On-Motherboard device path. Installs BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL + with the LOM device path protocol + + @retval EFI NOT_FOUND LOM device path is not found + @retval EFI_SUCCESS LOM device path found +**/ +EFI_STATUS +EFIAPI +InstallLomDevicePath ( + ) +{ + SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD *DevExtInfoRecord; + EFI_STATUS Status; + EFI_HANDLE *PciHandles; + UINTN PciHandlesSize; + UINTN Index; + EFI_PCI_IO_PROTOCOL *PciProtocol; + PCI_IO_DEVICE *PciIoDevice; + UINT8 NumberOfDevices; + UINT8 DevIdx; + UINTN SegmentNumber; + UINTN BusNumber; + UINTN DeviceNumber; + UINTN FunctionNumber; + + NumberOfDevices = PcdGet8 (PcdAmdSmbiosType41Number); + DevExtInfoRecord = (SMBIOS_ONBOARD_DEV_EXT_INFO_RECORD *)PcdGetPtr (PcdAmdSmbiosType41); + + // No device entries found + if (NumberOfDevices == 0) { + DEBUG ((DEBUG_INFO, "No onboard devices found.\n")); + return EFI_NOT_FOUND; + } + + //search through present on board devices, look for onboard ethernet + for (DevIdx = 0; DevIdx < NumberOfDevices; DevIdx++) { + if (AsciiStrCmp(DevExtInfoRecord->RefDesignationStr, "Onboard Ethernet") == 0) { + break; + } + DevExtInfoRecord++; + } + + //edge case, no Onboard Ethernet designator + if (AsciiStrCmp(DevExtInfoRecord->RefDesignationStr, "Onboard Ethernet") != 0) { + DEBUG((DEBUG_INFO, "No Onboard ethernet SMBIOS designator found!\n")); + return EFI_NOT_FOUND; + } + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &PciHandlesSize, + &PciHandles + ); + + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_INFO, "Can't locate gEfiPciIoProtocolGuid Protocol: Status = %r\n\n", Status)); + return Status; + } + + for (Index = 0; Index < PciHandlesSize; Index++) { + Status = gBS->HandleProtocol ( + PciHandles[Index], + &gEfiPciIoProtocolGuid, + (VOID **) &PciProtocol + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_INFO, "ERROR - Status = %r when locating PciIoProtocol\n", Status)); + continue; + } + + PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS(PciProtocol); + Status = PciIoDevice->PciIo.GetLocation(&PciIoDevice->PciIo, &SegmentNumber, &BusNumber, &DeviceNumber, &FunctionNumber); + + if ((PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SegmentNumber, BusNumber, DeviceNumber, FunctionNumber, 2)) == DevExtInfoRecord->DeviceId) && + (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SegmentNumber, BusNumber, DeviceNumber,FunctionNumber, 0)) == DevExtInfoRecord->VendorId)) { + //Making Lan0 default for systems with two LANs + if (FunctionNumber == 0) { + DEBUG((DEBUG_INFO, "Found Onboard Device with DeviceID=0x%X, VendorID=0x%X\n", DevExtInfoRecord->DeviceId, DevExtInfoRecord->VendorId)); + Status = EFI_SUCCESS; + //install device path protocol here + mBootDevicePathProtocol.Device = PciIoDevice->DevicePath; + mBootDevicePathProtocol.IpmiBootDeviceSelectorType = IPMI_BOOT_DEVICE_SELECTOR_PXE; + Status = gBS->InstallProtocolInterface ( + &mBoardBdsHandle, + &gBoardBdsBootFromDevicePathProtocolGuid, + EFI_NATIVE_INTERFACE, + &mBootDevicePathProtocol + ); + if (!EFI_ERROR (Status)) { + DEBUG((DEBUG_INFO, "BoardBdsBootFromDevicePathProtocol installed successfully\n")); + } + break; + } + } + } + + return Status; +} \ No newline at end of file diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommon.h b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommon.h index 0ea343491691b40fc79fceda42db0e35bf0509ee..b7dfe72ad5a8b4f758a83b57c45b2dad389def44 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommon.h +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommon.h @@ -1,8 +1,7 @@ /** @file AMD Smbios common header file. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -186,6 +185,18 @@ OnboardDevExtInfoFunction ( IN EFI_SMBIOS_PROTOCOL *Smbios ); +/** + Find the Lan-On-Motherboard device path. Installs BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL + with the LOM device path protocol + + @retval EFI NOT_FOUND LOM device path is not found + @retval EFI_SUCCESS LOM device path found +**/ +EFI_STATUS +EFIAPI +InstallLomDevicePath ( + ); + typedef EFI_STATUS (EFIAPI EFI_COMMON_SMBIOS_DATA_FUNCTION)( diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf index 548a6b0af455dafd294d567a7ebbcc20bf2b69e5..6541a6a39368184050f4ffa92d46fd5f75fde18a 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf @@ -1,10 +1,9 @@ ## @file # AMD common SMBIOS DXE library Description File # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent -## +# [Defines] INF_VERSION = 0x00010005 @@ -30,11 +29,13 @@ Type12SystemCfgOptionsFunction.c Type13BiosLanguageInfoFunction.c Type41OnboardDevExtInfoFunction.c + DefaultLomDevicePath.c [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec AmdPlatformPkg/AmdPlatformPkg.dec + BoardModulePkg/BoardModulePkg.dec [LibraryClasses] BaseLib @@ -47,11 +48,13 @@ UefiDriverEntryPoint UefiLib PlatformSocLib + PciSegmentLib [Protocols] gEfiSmbiosProtocolGuid ## PROTOCOL ALWAYS_CONSUMED gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES gEfiPciIoProtocolGuid ## CONSUMES + gBoardBdsBootFromDevicePathProtocolGuid ## PRODUCES [Pcd] gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8 ## CONSUMES diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonEntryPoint.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonEntryPoint.c index eb3635ca3445a3d3eb55f958a33be5a86c42e089..519a1fc2d9d79235fa79caf821cc02726b97e87b 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonEntryPoint.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonEntryPoint.c @@ -1,9 +1,9 @@ /** @file AMD Smbios Common DXE entry point. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include "SmbiosCommon.h" @@ -80,6 +80,8 @@ OnPciEnumerationComplete ( EfiStatus )); } + + EfiStatus = InstallLomDevicePath(); } /** diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type11OemStringsFunction.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type11OemStringsFunction.c index 53e7a573554df16a601b83e3a97d5edd9dc92c11..760661e274526b9e33ae389e381923c9fe2a7b9a 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type11OemStringsFunction.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type11OemStringsFunction.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 11 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type12SystemCfgOptionsFunction.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type12SystemCfgOptionsFunction.c index befb1223720a3894b3cf116d4ab04723233fcc5e..d8fcb0a5bf764f82326549ea9a62cf0b576a7879 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type12SystemCfgOptionsFunction.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type12SystemCfgOptionsFunction.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 12 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type13BiosLanguageInfoFunction.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type13BiosLanguageInfoFunction.c index 7d3ada2769702f70521270e229318bdf42aa1cc4..7ca81b53b4ddd72ffa8ad123907229b378f899fa 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type13BiosLanguageInfoFunction.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type13BiosLanguageInfoFunction.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 13 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type38IpmiDeviceInformation.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type38IpmiDeviceInformation.c index e2ad2ddb3d3eae9643edcf91f217499ee077b14d..91532a2ae9432f85b98f48d9a8a1698acc1b1816 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type38IpmiDeviceInformation.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type38IpmiDeviceInformation.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 38 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type41OnboardDevExtInfoFunction.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type41OnboardDevExtInfoFunction.c index cbd4c75eaf7ba27e99257041f7eddd6d81d73d51..b69de3c183ceee310041452c2eba6cf56b65bce7 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type41OnboardDevExtInfoFunction.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type41OnboardDevExtInfoFunction.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 41 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type8PortConnectorInfoFunction.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type8PortConnectorInfoFunction.c index 844529d1f09ef195c3207dcc20875ee4ab945af5..9d59beb3e54552e9c954f35298dc08785f223631 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type8PortConnectorInfoFunction.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type8PortConnectorInfoFunction.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 8 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type9SystemSlotInfoFunction.c b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type9SystemSlotInfoFunction.c index 568f44b427971c0553a2fc93c1c74d3862827c81..803f84ca52a6e90c7ea9cc0a323aba344024beba 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type9SystemSlotInfoFunction.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/SmbiosCommonDxe/Type9SystemSlotInfoFunction.c @@ -1,9 +1,9 @@ /** @file AMD SMBIOS Type 9 Record - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include #include "SmbiosCommon.h" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf similarity index 69% rename from Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.inf rename to Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf index 7f78f36055f6d3814f8d5236c3961ac75141c9f1..9bd1983ac8214c992bdcbbf4f34a9cf9a5dc1839 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf @@ -1,14 +1,15 @@ -## @file -# AMD SPI FVB DXE driver description File +#/** @file # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Component description file for SpiFvbDxe module # +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent -## +# +#**/ [Defines] INF_VERSION = 0x00010017 - BASE_NAME = SpiFvbDxe + BASE_NAME = AmdSpiFvbDxe FILE_GUID = 0895B765-D2ED-4FDF-AB44-BE48A761CE34 MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 @@ -20,10 +21,13 @@ SpiFvbCommon.c [Packages] + AgesaPkg/AgesaPkg.dec AmdPlatformPkg/AmdPlatformPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec UefiCpuPkg/UefiCpuPkg.dec + AgesaModulePkg/AgesaModuleFchPkg.dec [LibraryClasses] BaseLib @@ -37,11 +41,11 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES [FixedPcd] - gAmdPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBlockSize ## CONSUMES + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES - gAmdPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress ## CONSUMES [Protocols] gEfiFirmwareVolumeBlockProtocolGuid @@ -51,4 +55,4 @@ gEfiSpiNorFlashProtocolGuid [UserExtensions.TianoCore."ExtraFiles"] - SpiFvbExtra.uni + AmdSpiFvbExtra.uni diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbExtra.uni b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..364e82e18e71af72fddd2e2581de9fbe4c2aaef6 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbExtra.uni @@ -0,0 +1,9 @@ +// /***************************************************************************** +// * +// * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +// * +// * SPDX-License-Identifier: BSD-2-Clause-Patent +// *****************************************************************************/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "AMD SPI Firmware Volume Block Driver" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf similarity index 73% rename from Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.inf rename to Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf index 2c2fb17daf260010f148864ea69babe98e93b835..3b23eb46fd5a8d10b8e64faeff932fdbe515edc2 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf @@ -1,14 +1,15 @@ -## @file -# AMD SPI FVB SMM driver description File +#/** @file # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Component description file for SpiFvbDxe module # +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent -## +# +#**/ [Defines] INF_VERSION = 0x00010005 - BASE_NAME = SpiFvbSmm + BASE_NAME = AmdSpiFvbSmm FILE_GUID = 7EF9447C-C5D4-4DFC-A86E-64B4A19C9892 MODULE_TYPE = DXE_SMM_DRIVER VERSION_STRING = 1.0 @@ -20,10 +21,13 @@ SpiFvbCommon.c [Packages] + AgesaPkg/AgesaPkg.dec AmdPlatformPkg/AmdPlatformPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec UefiCpuPkg/UefiCpuPkg.dec + AgesaModulePkg/AgesaModuleFchPkg.dec [LibraryClasses] BaseLib @@ -35,6 +39,7 @@ MemoryAllocationLib IoLib PciLib + FchEspiCmdLib [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES @@ -43,8 +48,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES - gAmdPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBlockSize ## CONSUMES - gAmdPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize ## CONSUMES + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress ## CONSUMES [Protocols] gEfiSmmFirmwareVolumeBlockProtocolGuid ## PRODUCES @@ -56,4 +61,4 @@ gAmdEspiSmmNorFlashProtocolGuid [UserExtensions.TianoCore."ExtraFiles"] - SpiFvbExtra.uni + AmdSpiFvbExtra.uni diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbCommon.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbCommon.c similarity index 68% rename from Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbCommon.c rename to Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbCommon.c index 1e325a8ea865ca86ae3862f2672fccb37710fda6..9187df65f53c6f2aa240ff99e9ad10d68eee173d 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbCommon.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbCommon.c @@ -2,9 +2,9 @@ FV block I/O protocol driver for SPI flash libary. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include @@ -16,56 +16,61 @@ #include #include #include -#include +#include + #include #include #include -#define BLOCK_SIZE (FixedPcdGet32 (PcdFlashNvStorageBlockSize)) +#define BLOCK_SIZE (FixedPcdGet32 (PcdAgesaFlashNvStorageBlockSize)) // Set to 1 to turn on FVB writes and erases. Shouldn't be needed anymore. -#define SPI_FVB_VERIFY 1 +#define SPI_FVB_VERIFY 1 -EFI_SPI_NOR_FLASH_PROTOCOL *mSpiNorFlashProtocol; +EFI_SPI_NOR_FLASH_PROTOCOL *mSpiNorFlashProtocol; -extern UINT32 mSpiFlashOffset; +extern UINT32 mSpiFlashOffset; -UINT64 mNvStorageBase; -EFI_LBA mNvStorageLbaOffset; +UINT64 mNvStorageBase; +EFI_LBA mNvStorageLbaOffset; -STATIC CONST UINT64 mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) + - FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + - FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize); +STATIC CONST UINT64 mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize); -/** - Set the flash offset for SPI boot based on SoC. - @param[in] FlashSize - Size of physical flash part - @retval SPI Offset of current ROM image. -**/ +/* + * Calculates the SPI offset of the current image using the + * ROM OVERRIDE register bits. + * This is calculated from the SPI Base offset which is + * Computed using FlashSize for Turin Ax and Bx + * 0xFC00 0000 for Turin Cx and Genoa + * @param[in] FlashSize - Size of physical flash part + * + * @return SPI Offset of current ROM image. + */ UINT32 SetSpiFlashOffset ( - IN UINT32 FlashSize + UINT32 FlashSize ) { - UINT32 Value32; - UINT8 SpiRomPageXor; - UINT32 RomPage; - UINT32 RomBase; + UINT32 Value32; + UINT8 SpiRomPageXor; + UINT32 RomPage; + UINT32 RomBase; CPUID_VERSION_INFO_EAX VersionInfoEax; - RomPage = FixedPcdGet32 (PcdFlashAreaBaseAddress) >> 24; + RomPage = FixedPcdGet32 (PcdAgesaFlashAreaBaseAddress) >> 24; /// /// Set Base SPI address /// VersionInfoEax.Uint32 = 0; AsmCpuid (CPUID_VERSION_INFO, &VersionInfoEax.Uint32, NULL, NULL, NULL); - switch (VersionInfoEax.Uint32) { + switch(VersionInfoEax.Uint32) { case F1A_BRH_A0_RAW_ID: case F1A_BRH_B0_RAW_ID: case F1A_BRH_B1_RAW_ID: case F1A_BRHD_A0_RAW_ID: - case F1A_BRHD_B0_RAW_ID: DEBUG ((DEBUG_VERBOSE, "Turin A/B Detected\n")); RomBase = (0xFFFFFFFF - FlashSize) + 1; break; @@ -73,133 +78,99 @@ SetSpiFlashOffset ( RomBase = 0xFC000000; break; } - // Determine Bit [24], [25] Address Override Settings // SPI ROM Addr[25:24] |= Bit Override Settings Value32 = MmioRead32 ((UINTN)(FCH_SPI_BASE_ADDRESS + FCH_SPI_MMIO_REG30)); - if (Value32 & FCH_SPI_R2MSK24) { + if (Value32 & FCH_SPI_R2MSK24){ RomPage &= ~FCH_SPI_R2VAL24; RomPage |= Value32 & FCH_SPI_R2VAL24; } - - if (Value32 & FCH_SPI_R2MSK25) { + if (Value32 & FCH_SPI_R2MSK25){ RomPage &= ~FCH_SPI_R2VAL25; RomPage |= Value32 & FCH_SPI_R2VAL25; } // Read SPI XOR Value from Register 0x5C // SPI ROM Addr[31:24] = SPI ROM Page [31:24] ^ Host Mem Addr [31:24] - Value32 = MmioRead32 ((UINTN)(FCH_SPI_BASE_ADDRESS + FCH_SPI_MMIO_REG5C_ADDR32_CTRL3)); - DEBUG ((DEBUG_INFO, "%a - ROM 0x5C ADDR32Ctrl3 = 0x%X\n", __func__, Value32)); + Value32 = MmioRead32 ((UINTN)(FCH_SPI_BASE_ADDRESS + FCH_SPI_MMIO_REG5C_Addr32_Ctrl3)); + DEBUG((DEBUG_INFO, "%a - ROM 0x5C ADDR32Ctrl3 = 0x%X\n", __FUNCTION__, Value32)); // Compute SPI Address SpiRomPageXor = (UINT8)(Value32 & FCH_SPI_SPIROM_PAGE_MASK); - RomPage ^= SpiRomPageXor; + RomPage ^= SpiRomPageXor; // SPI ROM Addr = Current SPI address - SPI Address Base return ((RomPage << 24) - RomBase); } - -/** +/* Set the flash offset for Espi boot. - @param[in] FlashSize - Size of physical flash part @retval SPI Offset of current ROM image. -**/ +*/ UINT32 SetEspiFlashOffset ( - IN UINT32 FlashSize + UINT32 FlashSize ) { return 0; } #if SPI_FVB_VERIFY - -/** - Verify the write operation. - - @param[in] Address - Address to verify - @param[in] WriteBytes - Number of bytes to verify - @param[in] WriteBuffer - Buffer to verify - @retval EFI_STATUS -**/ EFI_STATUS EFIAPI VerifyWrite ( - IN UINT32 Address, - IN UINT32 WriteBytes, - IN UINT8 *WriteBuffer + IN UINT32 Address, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer ) { - EFI_STATUS Status; - UINTN Index; - UINT8 *VerifyBuffer; + EFI_STATUS Status; + UINTN Index; + UINT8 *VerifyBuffer; - VerifyBuffer = AllocateZeroPool (WriteBytes); + VerifyBuffer = AllocateZeroPool(WriteBytes); // Compare Write request with data read back Status = mSpiNorFlashProtocol->ReadData (mSpiNorFlashProtocol, Address, WriteBytes, VerifyBuffer); if (!EFI_ERROR (Status)) { Index = CompareMem (VerifyBuffer, WriteBuffer, WriteBytes); if (Index != 0) { Status = EFI_DEVICE_ERROR; - DEBUG (( - DEBUG_ERROR, - "%a: Comparison Failure: Address=0x%X, WriteBytes=0x%X, WriteBuffer=0x%lX, VerifyBuffer=0x%lX\n", - __func__, - Address, - WriteBytes, - WriteBuffer, - VerifyBuffer - )); + DEBUG((DEBUG_ERROR, "%a: Comparison Failure: Address=0x%X, WriteBytes=0x%X, WriteBuffer=0x%lX, VerifyBuffer=0x%lX\n", + __FUNCTION__, + Address, WriteBytes, WriteBuffer, VerifyBuffer)); for (Index = 0; Index < WriteBytes; Index++) { - DEBUG (( - DEBUG_ERROR, - "%a: Address=0x%X, WriteBuffer[0x%X]=0x%X, VerifyBuffer[0x%X]=0x%X", - __func__, - Address + Index, - Index, - WriteBuffer[Index], - Index, - VerifyBuffer[Index] - )); + DEBUG((DEBUG_ERROR, "%a: Address=0x%X, WriteBuffer[0x%X]=0x%X, VerifyBuffer[0x%X]=0x%X", + __FUNCTION__, + Address + Index, + Index, WriteBuffer[Index], + Index, VerifyBuffer[Index])); if (WriteBuffer[Index] != VerifyBuffer[Index]) { - DEBUG ((DEBUG_ERROR, " *** FAILED ***\n")); + DEBUG((DEBUG_ERROR, " *** FAILED ***\n")); } else { - DEBUG ((DEBUG_ERROR, "\n")); + DEBUG((DEBUG_ERROR, "\n")); } } - - ASSERT (FALSE); + ASSERT(FALSE); } } - if (VerifyBuffer != NULL) { FreePool (VerifyBuffer); } - return Status; } -/** - Verify the erase operation. - - @param[in] Address - Address to verify - @param[in] Length - Number of bytes to verify - @retval EFI_STATUS -**/ EFI_STATUS EFIAPI VerifyErase ( - IN UINT32 Address, - IN UINT32 Length + IN UINT32 Address, + IN UINT32 Length ) { - EFI_STATUS Status; - UINT32 Index; - UINT8 *VerifyBuffer; + EFI_STATUS Status; + UINT32 Index; + UINT8 *VerifyBuffer; - VerifyBuffer = AllocateZeroPool (Length); + VerifyBuffer = AllocateZeroPool(Length); Status = mSpiNorFlashProtocol->ReadData (mSpiNorFlashProtocol, Address, Length, VerifyBuffer); if (!EFI_ERROR (Status)) { @@ -207,26 +178,18 @@ VerifyErase ( for (Index = 0; Index < Length; Index++) { if (VerifyBuffer[Index] != 0xFF) { Status = EFI_DEVICE_ERROR; - DEBUG (( - DEBUG_ERROR, - "%a: Failure: SpiAddress=0x%X VerifyBuffer[0x%X]=0x%X *** FAILED ***\n", - __func__, - Address + Index, - Index, - VerifyBuffer[Index] - )); - ASSERT (FALSE); + DEBUG((DEBUG_ERROR, "%a: Failure: SpiAddress=0x%X VerifyBuffer[0x%X]=0x%X *** FAILED ***\n", + __FUNCTION__, + Address + Index, Index, VerifyBuffer[Index])); + ASSERT(FALSE); } } } - if (VerifyBuffer != NULL) { FreePool (VerifyBuffer); } - return Status; } - #endif // SPI_FVB_VERIFY /** @@ -248,11 +211,11 @@ STATIC EFI_STATUS EFIAPI SpiFvbGetAttributes ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, - OUT EFI_FVB_ATTRIBUTES_2 *Attributes + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes ) { - *Attributes = EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled + *Attributes = EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled EFI_FVB2_READ_STATUS | // Reads are currently enabled EFI_FVB2_WRITE_STATUS | // Writes are currently enabled EFI_FVB2_WRITE_ENABLED_CAP | // Writes may be enabled @@ -289,8 +252,8 @@ STATIC EFI_STATUS EFIAPI SpiFvbSetAttributes ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, - IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes ) { return EFI_SUCCESS; // ignore for now @@ -317,11 +280,11 @@ STATIC EFI_STATUS EFIAPI SpiFvbGetPhysicalAddress ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, - OUT EFI_PHYSICAL_ADDRESS *Address + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address ) { - *Address = (EFI_PHYSICAL_ADDRESS)mNvStorageBase; + *Address = (EFI_PHYSICAL_ADDRESS)mNvStorageBase; return EFI_SUCCESS; } @@ -355,13 +318,13 @@ STATIC EFI_STATUS EFIAPI SpiFvbGetBlockSize ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, - IN EFI_LBA Lba, - OUT UINTN *BlockSize, - OUT UINTN *NumberOfBlocks + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks ) { - *BlockSize = BLOCK_SIZE; + *BlockSize = BLOCK_SIZE; *NumberOfBlocks = mNvStorageSize / BLOCK_SIZE - (UINTN)Lba; return EFI_SUCCESS; @@ -418,53 +381,37 @@ STATIC EFI_STATUS EFIAPI SpiFvbRead ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, - IN EFI_LBA Lba, - IN UINTN Offset, - IN OUT UINTN *NumBytes, - IN OUT UINT8 *Buffer + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer ) { - EFI_STATUS Status; - UINT32 SpiOffset; + EFI_STATUS Status; + UINT32 SpiOffset; if (Offset >= BLOCK_SIZE) { return EFI_INVALID_PARAMETER; } - - DEBUG (( - DEBUG_VERBOSE, - "%a(Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", - __func__, - Lba, - Offset, - *NumBytes, - Buffer - )); + DEBUG((DEBUG_VERBOSE, "%a(Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", + __FUNCTION__, Lba, Offset, *NumBytes, Buffer)); if (Offset + *NumBytes > BLOCK_SIZE) { *NumBytes = ((Offset + *NumBytes) & ~(BLOCK_SIZE - 1)) - Offset; } - - DEBUG (( - DEBUG_VERBOSE, - "%a(AfterBlockBoundary Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", - __func__, - Lba, - Offset, - *NumBytes, - Buffer - )); + DEBUG((DEBUG_VERBOSE, "%a(AfterBlockBoundary Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", + __FUNCTION__, Lba, Offset, *NumBytes, Buffer)); SpiOffset = ((UINT32)mNvStorageLbaOffset + (UINT32)(Lba)) - * BLOCK_SIZE + (UINT32)Offset; + * BLOCK_SIZE + (UINT32)Offset; SpiOffset += mSpiFlashOffset; Status = mSpiNorFlashProtocol->ReadData ( - mSpiNorFlashProtocol, - SpiOffset, - (UINT32)*NumBytes, - Buffer - ); + mSpiNorFlashProtocol, + SpiOffset, + (UINT32)*NumBytes, + Buffer + ); return Status; } @@ -532,57 +479,41 @@ STATIC EFI_STATUS EFIAPI SpiFvbWrite ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, - IN EFI_LBA Lba, - IN UINTN Offset, - IN OUT UINTN *NumBytes, - IN UINT8 *Buffer + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer ) { - EFI_STATUS Status; - UINT32 SpiOffset; + EFI_STATUS Status; + UINT32 SpiOffset; if (Offset >= BLOCK_SIZE) { return EFI_INVALID_PARAMETER; } - - DEBUG (( - DEBUG_VERBOSE, - "%a(Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", - __func__, - Lba, - Offset, - *NumBytes, - Buffer - )); + DEBUG((DEBUG_VERBOSE, "%a(Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", + __FUNCTION__, Lba, Offset, *NumBytes, Buffer)); if (Offset + *NumBytes > BLOCK_SIZE) { *NumBytes = ((Offset + *NumBytes) & ~(BLOCK_SIZE - 1)) - Offset; } - - DEBUG (( - DEBUG_VERBOSE, - "%a(AfterBlockBoundary Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", - __func__, - Lba, - Offset, - *NumBytes, - Buffer - )); + DEBUG((DEBUG_VERBOSE, "%a(AfterBlockBoundary Lba=%lX, Offset=%lX, *NumBytes=%lX, Buffer=%lX)\n", + __FUNCTION__, Lba, Offset, *NumBytes, Buffer)); SpiOffset = ((UINT32)mNvStorageLbaOffset + (UINT32)(Lba)) - * BLOCK_SIZE + (UINT32)Offset; + * BLOCK_SIZE + (UINT32)Offset; SpiOffset += mSpiFlashOffset; Status = mSpiNorFlashProtocol->WriteData ( - mSpiNorFlashProtocol, - SpiOffset, - (UINT32)*NumBytes, - Buffer - ); + mSpiNorFlashProtocol, + SpiOffset, + (UINT32)*NumBytes, + Buffer + ); - #if SPI_FVB_VERIFY +#if SPI_FVB_VERIFY Status = VerifyWrite (SpiOffset, (UINT32)*NumBytes, Buffer); - #endif // SPI_FVB_VERIFY +#endif // SPI_FVB_VERIFY return Status; } @@ -639,48 +570,41 @@ STATIC EFI_STATUS EFIAPI SpiFvbErase ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ... ) { - VA_LIST Args; - EFI_LBA Start; - UINTN Length; - EFI_STATUS Status; - UINT32 SpiOffset; + VA_LIST Args; + EFI_LBA Start; + UINTN Length; + EFI_STATUS Status; + UINT32 SpiOffset; Status = EFI_SUCCESS; VA_START (Args, This); for (Start = VA_ARG (Args, EFI_LBA); Start != EFI_LBA_LIST_TERMINATOR; - Start = VA_ARG (Args, EFI_LBA)) - { + Start = VA_ARG (Args, EFI_LBA)) { Length = VA_ARG (Args, UINTN); - DEBUG (( - DEBUG_VERBOSE, - "%a(StartLba=%lX, NumBlocks=%lX)\n", - __func__, - Start, - Length - )); + DEBUG((DEBUG_VERBOSE, "%a(StartLba=%lX, NumBlocks=%lX)\n", + __FUNCTION__, Start, Length)); Length *= BLOCK_SIZE; - SpiOffset = ((UINT32)Start + (UINT32)mNvStorageLbaOffset) * BLOCK_SIZE; + SpiOffset = ((UINT32)Start + (UINT32)mNvStorageLbaOffset) * BLOCK_SIZE; SpiOffset += mSpiFlashOffset; Status = mSpiNorFlashProtocol->Erase ( - mSpiNorFlashProtocol, - SpiOffset, - (UINT32)Length / SIZE_4KB - ); - if (EFI_ERROR (Status)) { + mSpiNorFlashProtocol, + SpiOffset, + (UINT32)Length / SIZE_4KB + ); + if (EFI_ERROR(Status)) { break; } - - #if SPI_FVB_VERIFY +#if SPI_FVB_VERIFY Status = VerifyErase (SpiOffset, (UINT32)Length); - #endif // SPI_FVB_VERIFY +#endif // SPI_FVB_VERIFY } VA_END (Args); @@ -688,7 +612,7 @@ SpiFvbErase ( return Status; } -EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mSpiFvbProtocol = { +EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mSpiFvbProtocol = { SpiFvbGetAttributes, SpiFvbSetAttributes, SpiFvbGetPhysicalAddress, diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbDxe.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..22c505bd49c6dba0643d5031e34b26ce92e963c7 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbDxe.c @@ -0,0 +1,93 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BLOCK_SIZE (FixedPcdGet32 (PcdAgesaFlashNvStorageBlockSize)) + + +extern EFI_SPI_NOR_FLASH_PROTOCOL *mSpiNorFlashProtocol; +extern EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mSpiFvbProtocol; + +extern EFI_PHYSICAL_ADDRESS mNvStorageBase; +extern EFI_LBA mNvStorageLbaOffset; +UINT32 mSpiFlashOffset; + +STATIC EFI_HANDLE mSpiFvbHandle; +extern UINT32 SetSpiFlashOffset(UINT32 FlashSize); + +/** + EntryPoint + + @param[in] ImageHandle Driver Image Handle + @param[in] SystemTable System Table + + @retval EFI_SUCCESS Driver initialization succeeded + @retval all others Driver initialization failed + +**/ +EFI_STATUS +EFIAPI +SpiFvbDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + // Retrieve SPI NOR flash driver + Status = gBS->LocateProtocol ( + &gEfiSpiNorFlashProtocolGuid, + NULL, + (VOID **)&mSpiNorFlashProtocol + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + mNvStorageBase = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashNvStorageVariableBase); + DEBUG (( + DEBUG_INFO, + "%a - mNvStorageBase = %X\n", + __FUNCTION__, + mNvStorageBase + )); + mNvStorageLbaOffset = (EFI_LBA)((PcdGet32 (PcdFlashNvStorageVariableBase) + - FixedPcdGet32 (PcdAgesaFlashAreaBaseAddress)) + / FixedPcdGet32 (PcdAgesaFlashNvStorageBlockSize)); + DEBUG (( + DEBUG_INFO, + "%a - mNvStorageLbaOffset = %X\n", + __FUNCTION__, + mNvStorageLbaOffset + )); + + mSpiFvbHandle=NULL; + Status = gBS->InstallProtocolInterface ( + &mSpiFvbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + EFI_NATIVE_INTERFACE, + &mSpiFvbProtocol + ); + mSpiFlashOffset = SetSpiFlashOffset (mSpiNorFlashProtocol->FlashSize); + + DEBUG((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __FUNCTION__, Status)); + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbSmm.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..7781f9274a7a0880f73b4db3a2ecda87ed1dbe3d --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiFvb/SpiFvbSmm.c @@ -0,0 +1,110 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define BLOCK_SIZE (FixedPcdGet32 (PcdAgesaFlashNvStorageBlockSize)) + +extern EFI_SPI_NOR_FLASH_PROTOCOL *mSpiNorFlashProtocol; +extern EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mSpiFvbProtocol; +extern EFI_PHYSICAL_ADDRESS mNvStorageBase; +extern EFI_LBA mNvStorageLbaOffset; + +STATIC EFI_HANDLE mSpiFvbHandle; +UINT32 mSpiFlashOffset; + +extern UINT32 SetSpiFlashOffset(UINT32 FlashSize); +extern UINT32 SetEspiFlashOffset(UINT32 FlashSize); + +/** + Check if SAFS mode is enabled + + @retval TRUE SAFS mode is enabled. + @retval FALSE MAFS mode is enabled + +**/ +BOOLEAN +EFIAPI +IsEspiSafsMode ( + ) +{ + UINT32 MISC80; + MISC80 = MmioRead32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80); + if ((MISC80 & BIT3)) { // romtype [5:4] 10: eSPI with SAFS support + return TRUE; + } + return FALSE; +} + +/** + EntryPoint + + @param[in] ImageHandle Driver Image Handle + @param[in] MmSystemTable MM System Table + + @retval EFI_SUCCESS Driver initialization succeeded + @retval all others Driver initialization failed + +**/ +EFI_STATUS +EFIAPI +SpiFvbSmmEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 (*SetFlashOffset)(UINT32); + DEBUG((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + if (IsEspiSafsMode()) { + DEBUG((DEBUG_INFO, "Espi SAFS boot mode detected!\n")); + Status = gSmst->SmmLocateProtocol (&gAmdEspiSmmNorFlashProtocolGuid, + NULL, + (VOID **)&mSpiNorFlashProtocol); + SetFlashOffset = &SetEspiFlashOffset; + } + else { + DEBUG((DEBUG_INFO, "Default (SPIROM) boot mode detected!\n")); + // Retrieve SPI NOR flash driver + Status = gSmst->SmmLocateProtocol (&gEfiSpiSmmNorFlashProtocolGuid, + NULL, + (VOID **)&mSpiNorFlashProtocol); + SetFlashOffset = &SetSpiFlashOffset; + } + + if (EFI_ERROR(Status)) { + return Status; + } + + mNvStorageBase = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashNvStorageVariableBase); + DEBUG((DEBUG_INFO, "%a - mNvStorageBase = %X\n", __FUNCTION__, mNvStorageBase)); + mNvStorageLbaOffset = (EFI_LBA)((PcdGet32 (PcdFlashNvStorageVariableBase) + - FixedPcdGet32 (PcdAgesaFlashAreaBaseAddress)) + / FixedPcdGet32 (PcdAgesaFlashNvStorageBlockSize)); + DEBUG((DEBUG_INFO, "%a - mNvStorageLbaOffset = 0x%X\n", __FUNCTION__, mNvStorageLbaOffset)); + + mSpiFvbHandle=NULL; + Status = gSmst->SmmInstallProtocolInterface(&mSpiFvbHandle, + &gEfiSmmFirmwareVolumeBlockProtocolGuid, EFI_NATIVE_INTERFACE, + &mSpiFvbProtocol); + mSpiFlashOffset = (*SetFlashOffset)(mSpiNorFlashProtocol->FlashSize); + + DEBUG((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __FUNCTION__, Status)); + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHc.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHc.c new file mode 100644 index 0000000000000000000000000000000000000000..5f03447f71d8285f947b2415bec17562603a0cf4 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHc.c @@ -0,0 +1,326 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include "AmdSpiHc.h" +#include "AmdSpiHcInstance.h" +#include "AmdSpiHcInternal.h" +#include + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +ChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ) +{ + // PinValue doesn't have any context here. This HC only supports Chip Select + // value of low active. This will select which chip select will be toggled + // on the subsequent transactions. + EFI_STATUS Status; + SPI_HOST_CONTROLLER_INSTANCE *Instance; + CHIP_SELECT_PARAMETERS *ChipSelectParameter; + + Status = EFI_DEVICE_ERROR; + Instance = SPI_HOST_CONTROLLER_FROM_THIS (This); + + ChipSelectParameter = SpiPeripheral->ChipSelectParameter; + + if (SpiPeripheral->ChipSelect == NULL && + ChipSelectParameter->OrValue <= 1) { + if (!Instance->PspMailboxSpiMode) { + MmioAndThenOr8 (Instance->HcAddress + FCH_SPI_MMIO_REG1D, + ChipSelectParameter->AndValue, + ChipSelectParameter->OrValue); + Status = EFI_SUCCESS; + } else { + Instance->SpiCommunicationBuffer.SpiCommand[0].ChipSelect = + ChipSelectParameter->OrValue + 1; + Status = EFI_SUCCESS; + } + } else { + Status = EFI_INVALID_PARAMETER; + } + + return Status; +} + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +Clock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ) +{ + EFI_STATUS Status; + SPI_HOST_CONTROLLER_INSTANCE *Instance; + UINT32 InternalClockHz; + UINT16 InternalClockValue; + + Instance = SPI_HOST_CONTROLLER_FROM_THIS (This); + + Status = EFI_SUCCESS; + InternalClockHz = *ClockHz; + InternalClockValue = 0x00; + if (SpiPeripheral->MaxClockHz != 0 && + SpiPeripheral->MaxClockHz < InternalClockHz) { + InternalClockHz = SpiPeripheral->MaxClockHz; + } + if (SpiPeripheral->SpiPart->MaxClockHz != 0 && + SpiPeripheral->SpiPart->MaxClockHz < InternalClockHz) { + InternalClockHz = SpiPeripheral->SpiPart->MaxClockHz; + } + if (SpiPeripheral->SpiPart->MinClockHz != 0 && + SpiPeripheral->SpiPart->MinClockHz > InternalClockHz) { + Status = EFI_UNSUPPORTED; + } + if (!EFI_ERROR (Status)) { + if (InternalClockHz >= MHz(100)) { + InternalClockValue = 0x4; + } else if (InternalClockHz >= MHz(66)) { + InternalClockValue = 0x0; + } else if (InternalClockHz >= MHz(33)) { + InternalClockValue = 0x1; + } else if (InternalClockHz >= MHz(22)) { + InternalClockValue = 0x2; + } else if (InternalClockHz >= MHz(16)) { + InternalClockValue = 0x3; + } else if (InternalClockHz >= KHz(800)) { + InternalClockValue = 0x5; + } else { + Status = EFI_UNSUPPORTED; + } + if (!EFI_ERROR (Status)) { + if (!Instance->PspMailboxSpiMode) { + // Enable UseSpi100 + MmioOr8 (Instance->HcAddress + FCH_SPI_MMIO_REG20, + BIT0); + // Set the Value for NormSpeed and FastSpeed + InternalClockValue = InternalClockValue << 12 | InternalClockValue << 8; + MmioAndThenOr16 (Instance->HcAddress + FCH_SPI_MMIO_REG22, + 0x00FF, InternalClockValue); + } else { + Instance->SpiCommunicationBuffer.SpiCommand[0].Frequency = + (UINT8)InternalClockValue; + } + } + } + + return Status; +} + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + @retval EFI_DEVICE_ERROR SPI Host Controller failed transaction + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ) +{ + EFI_STATUS Status; + UINT8 Opcode; + UINT32 WriteBytes; + UINT8 *WriteBuffer; + UINT32 ReadBytes; + UINT8 *ReadBuffer; + EFI_PHYSICAL_ADDRESS HcAddress; + SPI_HOST_CONTROLLER_INSTANCE *Instance; + + WriteBytes = BusTransaction->WriteBytes; + WriteBuffer = BusTransaction->WriteBuffer; + + ReadBytes = BusTransaction->ReadBytes; + ReadBuffer = BusTransaction->ReadBuffer; + + if (WriteBytes > This->MaximumTransferBytes + 6 + || ReadBytes > (This->MaximumTransferBytes + 6 - WriteBytes) + || (WriteBytes != 0 && WriteBuffer == NULL) + || (ReadBytes != 0 && ReadBuffer == NULL)) { + return EFI_BAD_BUFFER_SIZE; + } + + Opcode = 0; + if (WriteBytes >= 1) { + Opcode = WriteBuffer[0]; + // Skip Opcode + WriteBytes -= 1; + WriteBuffer += 1; + } + + Status = EFI_SUCCESS; + Instance = SPI_HOST_CONTROLLER_FROM_THIS (This); + + HcAddress = Instance->HcAddress; + + if (!Instance->PspMailboxSpiMode) { + Status = FchSpiControllerNotBusy (Instance); + if (!EFI_ERROR (Status)) { + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG48_TX_BYTECOUNT, + (UINT8)WriteBytes + ); + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG4B_RXBYTECOUNT, + (UINT8)ReadBytes + ); + + // Fill in Write Data including Address + if (WriteBytes != 0) { + MmioWriteBuffer8 ( + HcAddress + FCH_SPI_MMIO_REG80_FIFO, + WriteBytes, + WriteBuffer + ); + } + + // Set Opcode + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG45_CMDCODE, + Opcode + ); + + // Execute the Transaction + Status = FchSpiExecute (Instance); + if (!EFI_ERROR (Status)) { + if (ReadBytes != 0) { + MmioReadBuffer8 ( + HcAddress + + FCH_SPI_MMIO_REG80_FIFO + + WriteBytes, + ReadBytes, + ReadBuffer + ); + } + } + } + } else { + // Execute SPI transaction through PSP Mailbox + Instance->SpiCommunicationBuffer.SpiCommand[0].OpCode = Opcode; + Instance->SpiCommunicationBuffer.SpiCommand[0].BytesToTx = (UINT8)WriteBytes; + if (WriteBytes != 0) { + CopyMem ( + &Instance->SpiCommunicationBuffer.SpiCommand[0].Buffer, + WriteBuffer, + WriteBytes); + } + Instance->SpiCommunicationBuffer.SpiCommand[0].BytesToRx = (UINT8)ReadBytes; + Instance->SpiCommunicationBuffer.CommandCount = 1; + Instance->SpiCommunicationBuffer.SpiCommunicationResult.Value = 0x0; + Instance->SpiCommunicationBuffer.ReadyToRun = TRUE; + Status = PspExecuteSpiCommand (); + if (!EFI_ERROR (Status)) { + if (Instance->SpiCommunicationBuffer.SpiCommunicationResult.Value == 0x1000) { + Status = EFI_INVALID_PARAMETER; + } else { + switch (Instance->SpiCommunicationBuffer.SpiCommunicationResult.Field.Command0Result) { + case SPI_COMMAND_MALFORMED: + Status = EFI_INVALID_PARAMETER; + break; + case SPI_COMMAND_COMPLETED: + Status = EFI_SUCCESS; + if (ReadBytes > 0) { + CopyMem ( + ReadBuffer, + &Instance->SpiCommunicationBuffer.SpiCommand[0].Buffer[0] + WriteBytes, + ReadBytes + ); + } + break; + case SPI_COMMAND_NOT_ALLOWED: + Status = EFI_WRITE_PROTECTED; + break; + default: + Status = EFI_DEVICE_ERROR; + break; + } + } + } + } + + return Status; +} + diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHc.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHc.h new file mode 100644 index 0000000000000000000000000000000000000000..56a06c8930bbfd06e2e00721a1ffff65035218db --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHc.h @@ -0,0 +1,113 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef AMD_SPI_HC_H_ +#define AMD_SPI_HC_H_ + +#include +#include +#include + +#define SPI_HC_MAXIMUM_TRANSFER_BYTES 64 + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +ChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +Clock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ); + +#endif // AMD_SPI_HC_SMM_PROTOCOL_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..0343c887dd606d28e26377baa2948f4dede765ae --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.c @@ -0,0 +1,92 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHc.h" +#include "AmdSpiHcNull.h" +#include "AmdSpiHcInstance.h" +#include "AmdSpiHcInternal.h" + +/** + Entry point of the AMD SPI Host Controller driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_OF_RESOURCES Fail to install EFI_SPI_SMM_HC_PROTOCOL protocol. + @retval EFI_DEVICE_ERROR Fail to install EFI_SPI_SMM_HC_PROTOCOL protocol. +**/ +EFI_STATUS +EFIAPI +AmdSpiHcProtocolEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SPI_HOST_CONTROLLER_INSTANCE *Instance; + + DEBUG((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + // Allocate the SPI Host Controller Instance + Instance = AllocateZeroPool (sizeof (SPI_HOST_CONTROLLER_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + Instance->Signature = SPI_HOST_CONTROLLER_SIGNATURE; + + // Fill in the SPI Host Controller Protocol + Instance->HcAddress = ( + PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS (0x00, FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0) + ) + ) & 0xFFFFFF00; + Instance->Protocol.Attributes = HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS | + HC_SUPPORTS_READ_ONLY_OPERATIONS | + HC_SUPPORTS_WRITE_ONLY_OPERATIONS; + + Instance->Protocol.FrameSizeSupportMask = FCH_SPI_FRAME_SIZE_SUPPORT_MASK; + Instance->Protocol.MaximumTransferBytes = SPI_HC_MAXIMUM_TRANSFER_BYTES; + + if (FeaturePcdGet (PcdRomArmorEnable)) { + Instance->PspMailboxSpiMode = TRUE; + Instance->Protocol.ChipSelect = ChipSelectNull; + Instance->Protocol.Clock = ClockNull; + Instance->Protocol.Transaction = TransactionNull; + } else { + Instance->PspMailboxSpiMode = FALSE; + Instance->Protocol.ChipSelect = ChipSelect; + Instance->Protocol.Clock = Clock; + Instance->Protocol.Transaction = Transaction; + } + // Install Host Controller protocol + Status = gBS->InstallProtocolInterface ( + &Instance->Handle, + &gEfiSpiHcProtocolGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + + DEBUG((DEBUG_INFO, "%a - EXIT Status=%r\n", __FUNCTION__, Status)); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..a47932a8fd5fb7ec374f143b30917605845b9d75 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.inf @@ -0,0 +1,66 @@ +#/** @file +# +# Component description file for SpiFvbDxe module +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = AmdSpiHcProtocolDxe + FILE_GUID = E3498244-5E16-4FA2-A023-5D34559AC87F + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = AmdSpiHcProtocolEntry + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + MemoryAllocationLib + PciSegmentLib + IoLib + PcdLib + TimerLib + DebugLib + UefiLib + AmdPspRomArmorLib + BaseMemoryLib + +[Sources] + AmdSpiHcDxe.c + AmdSpiHc.c + AmdSpiHcNull.c + AmdSpiHc.h + AmdSpiHcInstance.h + AmdSpiHcInternal.c + AmdSpiHcInternal.h + +[Protocols] + gEfiSpiHcProtocolGuid + gEfiDxeMmReadyToLockProtocolGuid + +[FeaturePcd] + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Guids] + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + AmdSpiHcExtra.uni diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcExtra.uni b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..e0372c38b2b1d05c63751dc3903b1c363a083f99 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcExtra.uni @@ -0,0 +1,9 @@ +// /***************************************************************************** +// * +// * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +// * SPDX-License-Identifier: BSD-2-Clause-Patent +// * +// * + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "AMD SPI Host Controller Driver" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInstance.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInstance.h new file mode 100644 index 0000000000000000000000000000000000000000..b48dacc05f27940b4069a66b8ae4fd99faa4bb74 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInstance.h @@ -0,0 +1,43 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef AMD_SPI_HC_INSTANCE_H_ +#define AMD_SPI_HC_INSTANCE_H_ + +#include +#include +#include +#include +#include +#include "AmdSpiHc.h" + +#define SPI_HOST_CONTROLLER_SIGNATURE SIGNATURE_32 ('s', 'h', 'c', 'd') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_EVENT Event; + BOOLEAN PspMailboxSpiMode; + SPI_COMMUNICATION_BUFFER SpiCommunicationBuffer; + VOID *Registration; + EFI_PHYSICAL_ADDRESS HcAddress; + EFI_SPI_HC_PROTOCOL Protocol; +} SPI_HOST_CONTROLLER_INSTANCE; + +#define SPI_HOST_CONTROLLER_FROM_THIS(a) \ + CR (a, SPI_HOST_CONTROLLER_INSTANCE, Protocol, \ + SPI_HOST_CONTROLLER_SIGNATURE) + +#define SPI_HOST_CONTROLLER_FROM_CONFIG_ACCESS(a) \ + CR (a, SPI_HOST_CONTROLLER_INSTANCE, ConfigAccess, \ + SPI_HOST_CONTROLLER_SIGNATURE) + +extern UINT8 AmdSpiHcFormBin[]; +extern UINT8 AmdSpiHcProtocolDxeStrings[]; + +#endif // AMD_SPI_HC_SMM_PROTOCOL_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInternal.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInternal.c new file mode 100644 index 0000000000000000000000000000000000000000..358ab46fe69557fa62389371b36e26aed4d05558 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInternal.c @@ -0,0 +1,286 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHc.h" +#include "AmdSpiHcInternal.h" + +/** + Check that SPI Conroller is Not Busy + + @param[in] Instance SpiHostControllerInstance; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiControllerNotBusy ( + SPI_HOST_CONTROLLER_INSTANCE *Instance + ) +{ + UINT32 SpiReg00; + UINT32 LpcDmaStatus; + UINT32 RetryCount; + UINTN DelayMicroseconds; + + if (Instance->PspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + DelayMicroseconds = FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + SpiReg00 = FCH_SPI_BUSY; + RetryCount = FixedPcdGet32 (PcdAmdSpiRetryCount); + do { + SpiReg00 = MmioRead32 (Instance->HcAddress + FCH_SPI_MMIO_REG4C_SPISTATUS); + LpcDmaStatus = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0x00, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REGB8)); + if ((SpiReg00 & FCH_SPI_BUSY) == 0 + && (LpcDmaStatus & FCH_LPC_DMA_SPI_BUSY) == 0) { + break; + } + MicroSecondDelay (DelayMicroseconds); + RetryCount--; + } while (RetryCount > 0); + if (RetryCount == 0) { + return EFI_DEVICE_ERROR; + } + return EFI_SUCCESS; +} + +/** + Check for SPI transaction failure(s) + + @param[in] Instance SpiHostControllerInstance; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiTransactionCheckFailure ( + SPI_HOST_CONTROLLER_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 Data; + + if (Instance->PspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + Status = FchSpiControllerNotBusy (Instance); + if (!EFI_ERROR (Status)) { + Data = MmioRead32 (Instance->HcAddress + FCH_SPI_MMIO_REG00); + if ((Data & FCH_SPI_FIFO_PTR_CRL) != 0) { + Status = EFI_ACCESS_DENIED; + } + } + return Status; +} + +/** + If SPI controller is not busy, execute SPI command. Then wait until SPI + controller is not busy. + + @param[in] Instance SpiHostControllerInstance; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiExecute ( + SPI_HOST_CONTROLLER_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + + if (Instance->PspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + Status = FchSpiControllerNotBusy (Instance); + if (!EFI_ERROR (Status)) { + MmioOr8 (Instance->HcAddress + FCH_SPI_MMIO_REG47_CMDTRIGGER, BIT7); + Status = FchSpiControllerNotBusy (Instance); + if (!EFI_ERROR (Status)) { + Status = FchSpiTransactionCheckFailure (Instance); + } + } + return Status; +} + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiBlockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + BOOLEAN OpcodeBlocked; + UINTN RestrictedCmd; + UINT8 Data; + + Status = EFI_OUT_OF_RESOURCES; + OpcodeBlocked = FALSE; + + // Allow only one copy of Opcode in RestrictedCmd register + for (RestrictedCmd = 0; RestrictedCmd <= 3; RestrictedCmd++) { + Data = MmioRead8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd); + + if (Data == Opcode && OpcodeBlocked == FALSE) { + OpcodeBlocked = TRUE; + } else if (Data == Opcode && OpcodeBlocked == TRUE) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, 0x00); + } else if (Data == 0x00 && OpcodeBlocked == FALSE) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, Opcode); + OpcodeBlocked = TRUE; + } + } + if (OpcodeBlocked) { + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ) +{ + UINTN RestrictedCmd; + + // Unblock any copies of the Opcode + for (RestrictedCmd = 0; RestrictedCmd <= 3; RestrictedCmd++) { + if (MmioRead8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd) == Opcode) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, 0x00); + } + } + return EFI_SUCCESS; +} + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockAllOpcodes ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioWrite32 (HcAddress + FCH_SPI_MMIO_REG04, 0x00); + return EFI_SUCCESS; +} + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiLockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioBitFieldAnd32 ( + HcAddress + FCH_SPI_MMIO_REG00, + 22, + 23, + 0x0 + ); + if (MmioBitFieldRead32 (HcAddress + FCH_SPI_MMIO_REG00, 22, 23) + == 0x0) { + return EFI_SUCCESS; + } + return EFI_DEVICE_ERROR; +} + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnlockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioBitFieldOr32 ( + HcAddress + FCH_SPI_MMIO_REG00, + 22, + 23, + BIT0 | BIT1 + ); + if (MmioBitFieldRead32 (HcAddress + FCH_SPI_MMIO_REG00, 22, 23) + == (BIT0 | BIT1)) { + return EFI_SUCCESS; + } + return EFI_DEVICE_ERROR; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInternal.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInternal.h new file mode 100644 index 0000000000000000000000000000000000000000..e79ba588114b68d46a5ad24c9fdbcefcac17711c --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcInternal.h @@ -0,0 +1,130 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef AMD_SPI_HC_INTERNAL_H_ +#define AMD_SPI_HC_INTERNAL_H_ + +#include +#include "AmdSpiHc.h" +#include "AmdSpiHcInstance.h" + +#define FCH_LPC_DMA_SPI_BUSY BIT0 + +#define FCH_SPI_MMIO_REG04 0x04 // SPI_RestrictedCmd +#define FCH_SPI_FRAME_SIZE_SUPPORT_MASK (1 << (8 - 1)) +#define FCH_SPI_LOCK_CONTROLLER 0x00 +#define FCH_SPI_UNLOCK_CONTROLLER BIT0 | BIT1 + +/** + Check that SPI Conroller is Not Busy + + @param[in] Instance SpiHostControllerInstance; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiControllerNotBusy ( + SPI_HOST_CONTROLLER_INSTANCE *Instance + ); + +/** + Execute SPI command + + @param[in] Instance SpiHostControllerInstance; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiExecute ( + SPI_HOST_CONTROLLER_INSTANCE *Instance + ); + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiBlockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ); + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ); + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockAllOpcodes ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiLockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnlockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +#endif // __AMD_SPI_HC_INTERNAL_H__ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcNull.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcNull.c new file mode 100644 index 0000000000000000000000000000000000000000..f3b1b18ce24ef3cee531712a204c0f6600e17c01 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcNull.c @@ -0,0 +1,128 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include "AmdSpiHcNull.h" + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +ChipSelectNull ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ) +{ + EFI_STATUS Status; + + Status = EFI_UNSUPPORTED; + return Status; +} + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +ClockNull ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ) +{ + EFI_STATUS Status; + + Status = EFI_UNSUPPORTED; + return Status; +} + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + @retval EFI_DEVICE_ERROR SPI Host Controller failed transaction + +**/ +EFI_STATUS +EFIAPI +TransactionNull ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ) +{ + EFI_STATUS Status; + + Status = EFI_UNSUPPORTED; + return Status; +} + diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcNull.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcNull.h new file mode 100644 index 0000000000000000000000000000000000000000..7142653906774c0aef69cecafbba3c16c95b9205 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcNull.h @@ -0,0 +1,111 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef AMD_SPI_HC_NULL_H_ +#define AMD_SPI_HC_NULL_H_ + +#include +#include +#include + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +ChipSelectNull ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +ClockNull ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + +**/ +EFI_STATUS +EFIAPI +TransactionNull ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ); + +#endif // AMD_SPI_HC_NULL_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..a90f60bd1ac85869cf8fb9713316ebefc80ece26 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.c @@ -0,0 +1,194 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHc.h" +#include "AmdSpiHcInternal.h" +#include "AmdSpiHcInstance.h" +#include "AmdSpiHcSmmState.h" + +/** + SPI host controller event notify callback to lock down the SPI chipset + + @param + @param + + @retval +**/ +EFI_STATUS +EFIAPI +AmdSpiHcEventNotify ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + SPI_HOST_CONTROLLER_INSTANCE *Instance; + EFI_SPI_HC_PROTOCOL *SpiHc; + SPI_WHITE_LIST *SpiWhitelist; + SMM_EFI_SPI_HC_STATE_PROTOCOL *SpiStateProtocol; + + // There can only be one SPI host controller driver in SMM + Status = gSmst->SmmLocateProtocol ( + &gEfiSpiSmmHcProtocolGuid, + NULL, + (VOID **)&SpiHc + ); + + Instance = SPI_HOST_CONTROLLER_FROM_THIS (SpiHc); + + if (FeaturePcdGet (PcdRomArmorEnable)) { + // Call PSP MailBox to change to PSP SPI mode + // Pass address of buffer found in Instance. + Status = gSmst->SmmLocateProtocol ( + &gAmdSpiHcStateProtocolGuid, + NULL, + (VOID **)&SpiStateProtocol + ); + SpiStateProtocol->Lock(SpiStateProtocol); + + Status = PspEnterSmmOnlyMode (&Instance->SpiCommunicationBuffer); + if (!EFI_ERROR (Status)) { + Instance->PspMailboxSpiMode = TRUE; + } else { + return EFI_DEVICE_ERROR; + } + if (FeaturePcdGet (PcdRomArmorWhitelistEnable)) { + // Retrieve allocated Whitelist table + Status = GetPspRomArmorWhitelist (&SpiWhitelist); + if (EFI_ERROR (Status)) { + if (SpiWhitelist != NULL) { + FreePool (SpiWhitelist); + } + return Status; + } + // Send Whitelist to PSP + Status = PspEnforceWhitelist (SpiWhitelist); + if (SpiWhitelist != NULL) { + FreePool (SpiWhitelist); + } + } + } + + return Status; +} + +/** + Entry point of the AMD SPI Host Controller driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_OF_RESOURCES Fail to install EFI_SPI_SMM_HC_PROTOCOL protocol. + @retval EFI_DEVICE_ERROR Fail to install EFI_SPI_SMM_HC_PROTOCOL protocol. +**/ +EFI_STATUS +EFIAPI +AmdSpiHcProtocolEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SPI_HOST_CONTROLLER_INSTANCE *Instance; + SPI_SMM_HC_STATE_INSTANCE *SpiState; + + + DEBUG((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + // Allocate the SPI Host Controller Instance + Instance = AllocateZeroPool (sizeof (SPI_HOST_CONTROLLER_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + Instance->Signature = SPI_HOST_CONTROLLER_SIGNATURE; + Instance->PspMailboxSpiMode = FALSE; + + SpiState = AllocateZeroPool (sizeof (SPI_SMM_HC_STATE_INSTANCE)); + ASSERT (SpiState != NULL); + if (SpiState == NULL) { + FreePool (Instance); + return EFI_OUT_OF_RESOURCES; + } + SpiState->Signature = SPI_SMM_HC_STATE_SIGNATURE; + SpiState->HcInstance = Instance; + + // Allocate Host Controller save state space + Status = AllocateState (SpiState); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + FreePool (SpiState); + FreePool (Instance); + return EFI_OUT_OF_RESOURCES; + } + + // Fill in the SPI Host Controller Protocol + Instance->HcAddress = ( + PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS (0x00, FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0) + ) + ) & 0xFFFFFF00; + Instance->Protocol.Attributes = HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS | + HC_SUPPORTS_READ_ONLY_OPERATIONS | + HC_SUPPORTS_WRITE_ONLY_OPERATIONS; + + Instance->Protocol.FrameSizeSupportMask = FCH_SPI_FRAME_SIZE_SUPPORT_MASK; + Instance->Protocol.MaximumTransferBytes = SPI_HC_MAXIMUM_TRANSFER_BYTES; + Instance->Protocol.ChipSelect = ChipSelect; + Instance->Protocol.Clock = Clock; + Instance->Protocol.Transaction = Transaction; + + // Fill in the SPI HC Save State Protocol + SpiState->HcAddress = Instance->HcAddress; + SpiState->Protocol.SaveState = SaveState; + SpiState->Protocol.RestoreState = RestoreState; + SpiState->Protocol.Lock = FchSpiLockSpiHostControllerRegisters; + SpiState->Protocol.Unlock = FchSpiUnlockSpiHostControllerRegisters; + SpiState->Protocol.BlockOpcode = FchSpiBlockOpcode; + SpiState->Protocol.UnblockOpcode = FchSpiUnblockOpcode; + SpiState->Protocol.UnblockAllOpcodes = FchSpiUnblockAllOpcodes; + + // Install Host Controller protocol and Save State Protocol + Status = gSmst->SmmInstallProtocolInterface( + &Instance->Handle, + &gEfiSpiSmmHcProtocolGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + Status = gSmst->SmmInstallProtocolInterface( + &Instance->Handle, + &gAmdSpiHcStateProtocolGuid, + EFI_NATIVE_INTERFACE, + &SpiState->Protocol + ); + Status = gSmst->SmmRegisterProtocolNotify ( + &gEfiMmReadyToLockProtocolGuid, + AmdSpiHcEventNotify, + &Instance->Registration + ); + + DEBUG((DEBUG_INFO, "%a - EXIT Status=%r\n", __FUNCTION__, Status)); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..df0d8be8b2b835269735e36718028a8a49894d48 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.inf @@ -0,0 +1,69 @@ +#/** @file +# +# Component description file for SpiFvbDxe module +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = AmdSpiHcProtocolSmm + FILE_GUID = 47543205-FBCC-435A-9467-37D31B728DEB + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = AmdSpiHcProtocolEntry + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + UefiDriverEntryPoint + SmmServicesTableLib + MemoryAllocationLib + PciSegmentLib + IoLib + PcdLib + TimerLib + DebugLib + AmdPspRomArmorLib + PlatformPspRomArmorWhitelistLib + BaseMemoryLib + +[Sources] + AmdSpiHcSmm.c + AmdSpiHc.c + AmdSpiHc.h + AmdSpiHcInstance.h + AmdSpiHcInternal.c + AmdSpiHcInternal.h + AmdSpiHcSmmState.c + AmdSpiHcSmmState.h + +[Protocols] + gEfiSmmVariableProtocolGuid + gEfiSpiSmmHcProtocolGuid + gAmdSpiHcStateProtocolGuid + gEfiMmReadyToLockProtocolGuid + +[FeaturePcd] + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorWhitelistEnable + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Guids] + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + AmdSpiHcExtra.uni diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmmState.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmmState.c new file mode 100644 index 0000000000000000000000000000000000000000..0cb9facf2a29f2c1f26ef85a08f9b8e762fceba9 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmmState.c @@ -0,0 +1,357 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcSmmState.h" +#include "AmdSpiHcInternal.h" + +CONST struct SpiHcRegisterState mSpiHcState[] = { + // {Register, Size, Count} + {0x04, 0x4, 0x1}, // SPI_RestrictedCmd + {0x08, 0x4, 0x1}, // SPI_RestrictedCmd2 + {0x0D, 0x1, 0x1}, // SPI_Cntrl1[15:8] + {0x0E, 0x2, 0x1}, // SPI_Cntrl1[31:16] + {0x10, 0x4, 0x1}, // SPI_CmdValue0 + {0x14, 0x4, 0x1}, // SPI_CmdValue1 + {0x18, 0x4, 0x1}, // SPI_CmdValue2 + {0x1D, 0x1, 0x1}, // Alt_SPI_CS + {0x20, 0x1, 0x1}, // SPI100 Enable + {0x22, 0x2, 0x1}, // SPI100 Speed Config + {0x24, 0x4, 0x1}, // SPI100 Clock Config + {0x32, 0x2, 0x1}, // SPI100 Dummy Cycle Config + {0x34, 0x2, 0x1}, // SPI100 RX Timing Config 1 + {0x44, 0x1, 0x1}, // ModeByte + {0x45, 0x1, 0x1}, // CmdCode + {0x48, 0x1, 0x1}, // TxByteCount + {0x4B, 0x1, 0x1}, // RxByteCount + {0x80, 0x1, 70}, // FIFO [70:0] + {0x00, 0x4, 0x1} // SpiCntrl0 ** Save last so restore last ** +}; + +/** + Allocate the save state space and update the instance structure + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + + @retval EFI_SUCCESS The Save State space was allocated + @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate +**/ +EFI_STATUS +EFIAPI +AllocateState ( + IN SPI_SMM_HC_STATE_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + + NumRecords = sizeof (mSpiHcState) / sizeof (struct SpiHcRegisterState); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return EFI_SUCCESS; + } + + // calculate space needed + Instance->StateSize = 0; + for (Record = 0; Record < NumRecords; Record++) { + Instance->StateSize += mSpiHcState[Record].Size + * mSpiHcState[Record].Count; + } + Instance->StateRecordCount = NumRecords; + Instance->State = AllocateZeroPool (Instance->StateSize); + if (Instance->State == NULL) { + Instance->StateRecordCount = 0; + Status = EFI_OUT_OF_RESOURCES; + } else { + Status = EFI_SUCCESS; + } + return Status; +} + +/** + Save the Host controler state to restore after transaction is complete + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +SaveState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + UINT32 NumRecords; + UINT32 Record; + UINT32 Count; + UINT8 *State; + + Status = EFI_SUCCESS; + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return Status; + } + + Status = FchSpiControllerNotBusy (Instance->HcInstance); + if (!EFI_ERROR (Status)) { + State = Instance->State; + NumRecords = Instance->StateRecordCount; + if (!Instance->SmmAlreadySavedState) { + for (Record = 0; Record < NumRecords; Record++) { + switch (mSpiHcState[Record].Size) { + case 0x1: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT8 *)State = MmioRead8 (Instance->HcAddress + + mSpiHcState[Record].Register); + State += 1; + } + break; + case 0x2: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT16 *)State = MmioRead16 (Instance->HcAddress + + mSpiHcState[Record].Register); + State += 2; + } + break; + case 0x4: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT32 *)State = MmioRead32 (Instance->HcAddress + + mSpiHcState[Record].Register); + State += 4; + } + break; + } + } + Instance->SmmAlreadySavedState = TRUE; + } + } + return Status; +} + +/** + Restore the Host Controller state + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +RestoreState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + UINT32 NumRecords; + UINT32 Record; + UINT32 Count; + UINT8 *State; + + Status = EFI_SUCCESS; + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return Status; + } + + State = Instance->State; + NumRecords = Instance->StateRecordCount; + if (Instance->SmmAlreadySavedState) { + for (Record = 0; Record < NumRecords; Record++) { + switch (mSpiHcState[Record].Size) { + case 0x1: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite8 (Instance->HcAddress + mSpiHcState[Record].Register, + *(UINT8 *)State); + State += 1; + } + break; + case 0x2: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite16 (Instance->HcAddress + mSpiHcState[Record].Register, + *(UINT16 *)State); + State += 2; + } + break; + case 0x4: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite32 (Instance->HcAddress + mSpiHcState[Record].Register, + *(UINT32 *)State); + State += 4; + } + break; + } + } + Instance->SmmAlreadySavedState = FALSE; + } + return Status; +} + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiBlockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiBlockOpcode (Instance->HcAddress, Opcode); + return Status; +} + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnblockOpcode (Instance->HcAddress, Opcode); + return Status; +} + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockAllOpcodes ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnblockAllOpcodes (Instance->HcAddress); + return Status; +} + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiLockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiLockSpiHostControllerRegisters (Instance->HcAddress); + return Status; +} + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnlockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + SPI_SMM_HC_STATE_INSTANCE *Instance; + + Instance = SPI_HC_SMM_STATE_FROM_THIS (This); + + // If PSP is in control, cannot save state + if (Instance->HcInstance->PspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnlockSpiHostControllerRegisters (Instance->HcAddress); + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmmState.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmmState.h new file mode 100644 index 0000000000000000000000000000000000000000..615edb8af28513d9642a3cff0170212265d050e4 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmmState.h @@ -0,0 +1,162 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef AMD_SPI_HC_SMM_STATE_H_ +#define AMD_SPI_HC_SMM_STATE_H_ + +#include +#include +#include +#include "AmdSpiHcInstance.h" + + +#define SPI_SMM_HC_STATE_SIGNATURE SIGNATURE_32 ('s', 'h', 'c', 's') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_PHYSICAL_ADDRESS HcAddress; + SPI_HOST_CONTROLLER_INSTANCE *HcInstance; + SMM_EFI_SPI_HC_STATE_PROTOCOL Protocol; + BOOLEAN SmmAlreadySavedState; + VOID *State; + UINT32 StateSize; + UINT32 StateRecordCount; +} SPI_SMM_HC_STATE_INSTANCE; + +#define SPI_HC_SMM_STATE_FROM_THIS(a) \ + CR (a, SPI_SMM_HC_STATE_INSTANCE, Protocol, \ + SPI_SMM_HC_STATE_SIGNATURE) + +struct SpiHcRegisterState { + UINT32 Register; + UINT8 Size; // Size in Bytes + UINT8 Count; // Number of contiguous registers to store +}; + +/** + Allocate the save state space and update the instance structure + + @param[in] Instance Pointer to SPI_SMM_HC_STATE_INSTANCE + + @retval EFI_SUCCESS The Save State space was allocated + @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate +**/ +EFI_STATUS +EFIAPI +AllocateState ( + IN SPI_SMM_HC_STATE_INSTANCE *Instance + ); + +/** + Save the Host Controller state to restore after transaction is complete + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +SaveState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Restore the Host Controller state + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +RestoreState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiBlockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ); + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ); + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockAllOpcodes ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiLockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnlockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); +#endif // __AMD_SPI_HC_SMM_STATE_H__ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBus.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBus.c new file mode 100644 index 0000000000000000000000000000000000000000..474235bd81e163bfff818cc912e7cf729f98eab3 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBus.c @@ -0,0 +1,180 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include "BoardSpiBus.h" +#include "BoardSpiBusInstance.h" + +/** + Initiate a SPI transaction between the host and a SPI peripheral. + + This routine must be called at or below TPL_NOTIFY. + This routine works with the SPI bus layer to pass the SPI transaction to the + SPI controller for execution on the SPI bus. There are four types of + supported transactions supported by this routine: + * Full Duplex: WriteBuffer and ReadBuffer are the same size. + * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0 + * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0 + * Write Then Read: WriteBuffer contains control data to write to SPI + peripheral before data is placed into the ReadBuffer. + Both WriteBytes and ReadBytes must be non-zero. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] TransactionType Type of SPI transaction. + @param[in] DebugTransaction Set TRUE only when debugging is desired. + Debugging may be turned on for a single SPI + transaction. Only this transaction will display + debugging messages. All other transactions with + this value set to FALSE will not display any + debugging messages. + @param[in] ClockHz Specify the ClockHz value as zero (0) to use + the maximum clock frequency supported by the + SPI controller and part. Specify a non-zero + value only when a specific SPI transaction + requires a reduced clock rate. + @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4 + @param[in] FrameSize Frame size in bits, range: 1 - 32 + @param[in] WriteBytes The length of the WriteBuffer in bytes. + Specify zero for read-only operations. + @param[in] WriteBuffer The buffer containing data to be sent from the + host to the SPI chip. Specify NULL for read + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The transmit frame is in the least + significant N bits. + @param[in] ReadBytes The length of the ReadBuffer in bytes. + Specify zero for write-only operations. + @param[out] ReadBuffer The buffer to receeive data from the SPI chip + during the transaction. Specify NULL for write + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The received frame is in the least + significant N bits. + + @retval EFI_SUCCESS The SPI transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The writeBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN EFI_SPI_TRANSACTION_TYPE TransactionType, + IN BOOLEAN DebugTransaction, + IN UINT32 ClockHz OPTIONAL, + IN UINT32 BusWidth, + IN UINT32 FrameSize, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT32 ReadBytes, + OUT UINT8 *ReadBuffer + ) +{ + EFI_STATUS Status; + SPI_IO_INSTANCE *Instance; + UINT32 MaxClockHz; + + Instance = SPI_IO_FROM_THIS (This); + + Instance->BusTransaction.SpiPeripheral = + (EFI_SPI_PERIPHERAL *)Instance->Protocol.SpiPeripheral; + Instance->BusTransaction.TransactionType = TransactionType; + Instance->BusTransaction.DebugTransaction = DebugTransaction; + Instance->BusTransaction.BusWidth = BusWidth; + Instance->BusTransaction.FrameSize = FrameSize; + Instance->BusTransaction.WriteBytes = WriteBytes; + Instance->BusTransaction.WriteBuffer = WriteBuffer; + Instance->BusTransaction.ReadBytes = ReadBytes; + Instance->BusTransaction.ReadBuffer = ReadBuffer; + + Status = Instance->SpiHc->ChipSelect(Instance->SpiHc, + Instance->BusTransaction.SpiPeripheral, + 0); + if (!EFI_ERROR (Status)) { + if (Instance->BusTransaction.SpiPeripheral->MaxClockHz != 0) { + MaxClockHz = Instance->BusTransaction.SpiPeripheral->MaxClockHz; + } else { + MaxClockHz = Instance->BusTransaction.SpiPeripheral->SpiPart->MaxClockHz; + } + Status = Instance->SpiHc->Clock(Instance->SpiHc, + Instance->BusTransaction.SpiPeripheral, + &MaxClockHz); + if (!EFI_ERROR (Status)) { + Status = Instance->SpiHc->Transaction(Instance->SpiHc, + &Instance->BusTransaction); + } + } + return Status; +} + +/** + Update the SPI peripheral associated with this SPI 10 instance. + + Support socketed SPI parts by allowing the SPI peripheral driver to replace + the SPI peripheral after the connection is made. An example use is socketed + SPI NOR flash parts, where the size and parameters change depending upon + device is in the socket. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure. + + @retval EFI_SUCCESS The SPI peripheral was updated successfully + @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL, + or the SpiPeripheral->SpiBus is NULL, + or the SpiP eripheral - >SpiBus pointing at + wrong bus, + or the SpiP eripheral - >SpiPart is NULL + +**/ +EFI_STATUS +EFIAPI +UpdateSpiPeripheral ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral + ) +{ + EFI_STATUS Status; + SPI_IO_INSTANCE *Instance; + + DEBUG((DEBUG_INFO, "%a: SPI Bus - Entry\n", __FUNCTION__)); + + Instance = SPI_IO_FROM_THIS (This); + + Instance->Protocol.SpiPeripheral = SpiPeripheral; + + Status = EFI_SUCCESS; + DEBUG((DEBUG_INFO, "%a: SPI Bus - Exit Status=%r\n", + __FUNCTION__, Status)); + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBus.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBus.h new file mode 100644 index 0000000000000000000000000000000000000000..7ee29de986e0cd79ef91e92188871b746e29f161 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBus.h @@ -0,0 +1,130 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef BOARD_SPI_BUS_H_ +#define BOARD_SPI_BUS_H_ + +#include +#include +#include + +/** + Initiate a SPI transaction between the host and a SPI peripheral. + + This routine must be called at or below TPL_NOTIFY. + This routine works with the SPI bus layer to pass the SPI transaction to the + SPI controller for execution on the SPI bus. There are four types of + supported transactions supported by this routine: + * Full Duplex: WriteBuffer and ReadBuffer are the same size. + * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0 + * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0 + * Write Then Read: WriteBuffer contains control data to write to SPI + peripheral before data is placed into the ReadBuffer. + Both WriteBytes and ReadBytes must be non-zero. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] TransactionType Type of SPI transaction. + @param[in] DebugTransaction Set TRUE only when debugging is desired. + Debugging may be turned on for a single SPI + transaction. Only this transaction will display + debugging messages. All other transactions with + this value set to FALSE will not display any + debugging messages. + @param[in] ClockHz Specify the ClockHz value as zero (0) to use + the maximum clock frequency supported by the + SPI controller and part. Specify a non-zero + value only when a specific SPI transaction + requires a reduced clock rate. + @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4 + @param[in] FrameSize Frame size in bits, range: 1 - 32 + @param[in] WriteBytes The length of the WriteBuffer in bytes. + Specify zero for read-only operations. + @param[in] WriteBuffer The buffer containing data to be sent from the + host to the SPI chip. Specify NULL for read + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The transmit frame is in the least + significant N bits. + @param[in] ReadBytes The length of the ReadBuffer in bytes. + Specify zero for write-only operations. + @param[out] ReadBuffer The buffer to receeive data from the SPI chip + during the transaction. Specify NULL for write + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The received frame is in the least + significant N bits. + + @retval EFI_SUCCESS The SPI transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The writeBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN EFI_SPI_TRANSACTION_TYPE TransactionType, + IN BOOLEAN DebugTransaction, + IN UINT32 ClockHz OPTIONAL, + IN UINT32 BusWidth, + IN UINT32 FrameSize, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT32 ReadBytes, + OUT UINT8 *ReadBuffer + ); + +/** + Update the SPI peripheral associated with this SPI 10 instance. + + Support socketed SPI parts by allowing the SPI peripheral driver to replace + the SPI peripheral after the connection is made. An example use is socketed + SPI NOR flash parts, where the size and parameters change depending upon + device is in the socket. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure. + + @retval EFI_SUCCESS The SPI peripheral was updated successfully + @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL, + or the SpiPeripheral->SpiBus is NULL, + or the SpiP eripheral - >SpiBus pointing at + wrong bus, + or the SpiP eripheral - >SpiPart is NULL + +**/ +EFI_STATUS +EFIAPI +UpdateSpiPeripheral ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral + ); + +#endif // BOARD_SPI_BUS diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..efe1dc542285ddf55db4dbb9c09f90a72b7c8e83 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.c @@ -0,0 +1,123 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include "BoardSpiBus.h" +#include "BoardSpiBusInstance.h" + +/** + Entry point of the Board SPI Configuration driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_DEVICE_ERROR Fail to install EFI_SPI_HC_PROTOCOL protocol. +**/ +EFI_STATUS +EFIAPI +BoardSpiBusEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SPI_IO_INSTANCE *Instance; + EFI_SPI_HC_PROTOCOL *SpiHc; + EFI_SPI_CONFIGURATION_PROTOCOL *SpiConfiguration; + EFI_SPI_PERIPHERAL *SpiPeripheral; + EFI_SPI_BUS *Bus; + UINTN Index; + + DEBUG((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + Status = gBS->LocateProtocol ( + &gEfiSpiHcProtocolGuid, + NULL, + (VOID **)&SpiHc + ); + + if (!EFI_ERROR (Status)) { + // Locate the SPI Configuration Protocol. + Status = gBS->LocateProtocol ( + &gEfiSpiConfigurationProtocolGuid, + NULL, + (VOID **)&SpiConfiguration + ); + + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < SpiConfiguration->BusCount; Index++) { + Bus = (EFI_SPI_BUS *)SpiConfiguration->Buslist[Index]; + DEBUG ((DEBUG_INFO, "%a: Enumerating SPI BUS: %s\n", __FUNCTION__, + Bus->FriendlyName)); + SpiPeripheral = (EFI_SPI_PERIPHERAL *)Bus->Peripherallist; + if (SpiPeripheral != NULL) { + do { + DEBUG ((DEBUG_INFO, + "%a: Installing SPI IO protocol for %s, by %s, PN=%s\n", + __FUNCTION__, SpiPeripheral->FriendlyName, + SpiPeripheral->SpiPart->Vendor, + SpiPeripheral->SpiPart->PartNumber)); + // Allocate the SPI IO Instance + Instance = AllocateZeroPool (sizeof (SPI_IO_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance !=NULL) { + // fill in the instance + Instance->Signature = SPI_IO_SIGNATURE; + Instance->SpiConfig = SpiConfiguration; + Instance->SpiHc = SpiHc; + Instance->Protocol.SpiPeripheral = SpiPeripheral; + Instance->Protocol.OriginalSpiPeripheral = SpiPeripheral; + Instance->Protocol.FrameSizeSupportMask = SpiHc->FrameSizeSupportMask; + Instance->Protocol.MaximumTransferBytes = SpiHc->MaximumTransferBytes; + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_ADDRESS) != 0) { + Instance->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS; + } + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_OPCODE) != 0) { + Instance->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE; + } + if ((SpiHc->Attributes & HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH) != 0) { + Instance->Protocol.Attributes |= SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH; + } + if ((SpiHc->Attributes & HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH) != 0) { + Instance->Protocol.Attributes |= SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH; + } + Instance->Protocol.Transaction = Transaction; + Instance->Protocol.UpdateSpiPeripheral = UpdateSpiPeripheral; + // Install the SPI IO Protocol + Status = gBS->InstallProtocolInterface( + &Instance->Handle, + (GUID *)SpiPeripheral->SpiPeripheralDriverGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + } else { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: Out of Memory resources\n", + __FUNCTION__)); + break; + } + SpiPeripheral = (EFI_SPI_PERIPHERAL *)SpiPeripheral->NextSpiPeripheral; + } while (SpiPeripheral != NULL); + } else { + Status = EFI_DEVICE_ERROR; + } + } + } + } + + DEBUG((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __FUNCTION__, Status)); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..e0074d37d5feebb41e2cc1ee0a4d28f7eca2aeac --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Component description file for SpiFvbDxe module +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = BoardSpiBusDxe + FILE_GUID = DF234C93-C02B-4EC7-8E8F-E5DD11F7DB6B + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = BoardSpiBusEntry + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib + UefiDriverEntryPoint + UefiBootServicesTableLib + +[Sources] + BoardSpiBusDxe.c + BoardSpiBus.c + BoardSpiBus.h + BoardSpiBusInstance.h + +[Protocols] + gEfiSpiConfigurationProtocolGuid ## CONSUMES + gEfiSpiHcProtocolGuid ## CONSUMES + +[Guids] + +[Depex] + gEfiSpiConfigurationProtocolGuid AND + gEfiSpiHcProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + BoardSpiBusExtra.uni diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusExtra.uni b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..7a881af6c6f38a42693035f013b5e1f33dc27548 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusExtra.uni @@ -0,0 +1,9 @@ +// /***************************************************************************** +// * +// * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. +// * SPDX-License-Identifier: BSD-2-Clause-Patent +// * +// *****************************************************************************/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "SPI Bus Driver" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusInstance.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusInstance.h new file mode 100644 index 0000000000000000000000000000000000000000..eb7c5eea3c904f130f1c7debec02ac945cec1aab --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusInstance.h @@ -0,0 +1,32 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef BOARD_SPI_BUS_INSTANCE_H_ +#define BOARD_SPI_BUS_INSTANCE_H_ + +#include +#include +#include +#include + +#define SPI_IO_SIGNATURE SIGNATURE_32 ('s', 'i', 'o', 's') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SPI_IO_PROTOCOL Protocol; + EFI_SPI_BUS_TRANSACTION BusTransaction; + EFI_SPI_CONFIGURATION_PROTOCOL *SpiConfig; + EFI_SPI_HC_PROTOCOL *SpiHc; +} SPI_IO_INSTANCE; + +#define SPI_IO_FROM_THIS(a) \ + CR (a, SPI_IO_INSTANCE, Protocol, \ + SPI_IO_SIGNATURE) + +#endif // BOARD_SPI_BUS_INSTANCE_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..383ecdb238c537dd3a48a9bb1eea213273ae5cb6 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.c @@ -0,0 +1,117 @@ +/** @file + + FV block I/O protocol driver for SPI flash libary. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include "BoardSpiBus.h" +#include "BoardSpiBusInstance.h" + +/** + Entry point of the Board SPI Configuration driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_DEVICE_ERROR Fail to install EFI_SPI_SMM_HC_PROTOCOL protocol. +**/ +EFI_STATUS +EFIAPI +BoardSpiBusEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SPI_IO_INSTANCE *Instance; + EFI_SPI_HC_PROTOCOL *SpiHc; + EFI_SPI_CONFIGURATION_PROTOCOL *SpiConfiguration; + EFI_SPI_PERIPHERAL *SpiPeripheral; + EFI_SPI_BUS *Bus; + + DEBUG((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + // Locate the SPI HC Protocol. Only one supported in SMM anyway + Status = gSmst->SmmLocateProtocol ( + &gEfiSpiSmmHcProtocolGuid, + NULL, + (VOID **)&SpiHc + ); + + // Locate the SPI Configuration Protocol. + Status = gSmst->SmmLocateProtocol ( + &gEfiSpiSmmConfigurationProtocolGuid, + NULL, + (VOID **)&SpiConfiguration + ); + + // SMM SPI Bus driver only supports one bus. + if (SpiConfiguration->BusCount != 1) { + DEBUG ((DEBUG_ERROR, "%a: Smm SPI Configuration Bus Count > 1.\n", + __FUNCTION__)); + ASSERT (FALSE); + } + Bus = (EFI_SPI_BUS *)SpiConfiguration->Buslist[0]; + DEBUG ((DEBUG_INFO, "%a: Enumerating SPI BUS: %s\n", __FUNCTION__, + Bus->FriendlyName)); + SpiPeripheral = (EFI_SPI_PERIPHERAL *)Bus->Peripherallist; + do { + DEBUG ((DEBUG_INFO, "%a: Installing SPI IO protocol for %s, by %s, PN=%s\n", + __FUNCTION__, SpiPeripheral->FriendlyName, + SpiPeripheral->SpiPart->Vendor, SpiPeripheral->SpiPart->PartNumber)); + // Allocate the SPI IO Instance + Instance = AllocateZeroPool (sizeof (SPI_IO_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance !=NULL) { + // fill in the instance + Instance->Signature = SPI_IO_SIGNATURE; + Instance->SpiConfig = SpiConfiguration; + Instance->SpiHc = SpiHc; + Instance->Protocol.SpiPeripheral = SpiPeripheral; + Instance->Protocol.OriginalSpiPeripheral = SpiPeripheral; + Instance->Protocol.FrameSizeSupportMask = SpiHc->FrameSizeSupportMask; + Instance->Protocol.MaximumTransferBytes = SpiHc->MaximumTransferBytes; + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_ADDRESS) != 0) { + Instance->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS; + } + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_OPCODE) != 0) { + Instance->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE; + } + if ((SpiHc->Attributes & HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH) != 0) { + Instance->Protocol.Attributes |= SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH; + } + if ((SpiHc->Attributes & HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH) != 0) { + Instance->Protocol.Attributes |= SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH; + } + Instance->Protocol.Transaction = Transaction; + Instance->Protocol.UpdateSpiPeripheral = UpdateSpiPeripheral; + // Install the SPI IO Protocol + Status = gSmst->SmmInstallProtocolInterface( + &Instance->Handle, + (GUID *)SpiPeripheral->SpiPeripheralDriverGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + } else { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "%a: Out of Memory resources\n", + __FUNCTION__)); + break; + } + SpiPeripheral = (EFI_SPI_PERIPHERAL *)SpiPeripheral->NextSpiPeripheral; + } while (SpiPeripheral != NULL); + + DEBUG((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __FUNCTION__, Status)); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..8b51aa1a27140f18d210421b71d7e3a0e5ca47d6 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Component description file for SpiFvbDxe module +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = BoardSpiBusSmm + FILE_GUID = A9B5FA1E-6CC1-424E-A5DC-D45C4384B44F + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = BoardSpiBusEntry + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib + SmmServicesTableLib + UefiDriverEntryPoint + +[Sources] + BoardSpiBusSmm.c + BoardSpiBus.c + BoardSpiBus.h + BoardSpiBusInstance.h + +[Protocols] + gEfiSpiSmmConfigurationProtocolGuid ## CONSUMES + gEfiSpiSmmHcProtocolGuid ## CONSUMES + +[Guids] + +[Depex] + gEfiSpiSmmConfigurationProtocolGuid AND + gEfiSpiSmmHcProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + BoardSpiBusExtra.uni diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.c index e3e9e2eb5b8d58455c73bda22ff4ebcd153c8a26..a28269f970c0e4d25125b4c37c3befe86b06d40e 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.c @@ -2,9 +2,9 @@ FV block I/O protocol driver for SPI flash libary. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include @@ -14,50 +14,45 @@ #include #include -SPI_CONTROLLER_DEVICE_PATH mFchDevicePath = FCH_DEVICE_PATH; - -CHIP_SELECT_PARAMETERS ChipSelect1 = CHIP_SELECT_1; -CHIP_SELECT_PARAMETERS ChipSelect2 = CHIP_SELECT_2; +EFI_HANDLE mSpiConfigHandle = NULL; -EFI_HANDLE mSpiConfigHandle = NULL; - -CONST EFI_SPI_PART Mx25u6435f = { +CONST EFI_SPI_PART Mx25u6435f = { L"Macronix", // Vendor L"MX25U6435F", // PartNumber 0, // MinClockHz - MHz (104), // MaxClockHz + MHz(104), // MaxClockHz FALSE // ChipSelectPolarity }; -CONST EFI_SPI_PART FakeDevice = { +CONST EFI_SPI_PART FakeDevice = { L"Fake", // Vendor L"Fake Device", // PartNumber - 0, // MinClockHz - MHz (22), // MaxClockHz - FALSE // ChipSelectPolarity + 0, // MinClockHz + MHz(22), // MaxClockHz + FALSE // ChipSelectPolarity }; -EFI_SPI_PERIPHERAL mPeripherallist[] = { - { // Flash Memory = SPI ROM - NULL, // *NextSpiPeripheral - L"Device", // *FriendlyName - &gFakeDeviceIoProtocolGuid, // *SpiPeripheralDriverGuid - &FakeDevice, // *SpiPart - MHz (33), // MaxClockHz - 1, // ClockPolarity - 0, // ClockPhase - 0, // Attributes - NULL, // *ConfigurationData - NULL, // *SpiBus - NULL, // ChipSelect() - (VOID *)&ChipSelect2 // *ChipSelectParameter +EFI_SPI_PERIPHERAL mPeripherallist[] = { + { // Flash Memory = SPI ROM + NULL, // *NextSpiPeripheral + L"Device", // *FriendlyName + &gFakeDeviceIoProtocolGuid, // *SpiPeripheralDriverGuid + &FakeDevice, // *SpiPart + MHz(33), // MaxClockHz + 1, // ClockPolarity + 0, // ClockPhase + 0, // Attributes + NULL, // *ConfigurationData + NULL, // *SpiBus + NULL, // ChipSelect() + (VOID *)&ChipSelect2 // *ChipSelectParameter }, - { // Flash Memory = SPI ROM + { // Flash Memory = SPI ROM NULL, // *NextSpiPeripheral L"Flash Memory", // *FriendlyName &gEdk2JedecSfdpSpiDxeDriverGuid, // *SpiPeripheralDriverGuid &Mx25u6435f, // *SpiPart - MHz (33), // MaxClockHz + MHz(33), // MaxClockHz 1, // ClockPolarity 0, // ClockPhase 0, // Attributes, only support 1 bit bus width @@ -68,6 +63,7 @@ EFI_SPI_PERIPHERAL mPeripherallist[] = { } }; + /* EFI_DEVICE_PATH_PROTOCOL mDevicePath = { 0x01, @@ -76,56 +72,48 @@ EFI_DEVICE_PATH_PROTOCOL mDevicePath = { }; */ -EFI_SPI_BUS mSpiBus1 = { - L"FCH SPI BUS", // FriendlyName - NULL, // Peripherallist - (EFI_DEVICE_PATH_PROTOCOL *)&mFchDevicePath, // ControllerPath - NULL, // Clock - NULL // ClockParameter + +EFI_SPI_BUS mSpiBus1 = { + L"FCH SPI BUS", // FriendlyName + NULL, // Peripherallist + (EFI_DEVICE_PATH_PROTOCOL *)&mFchDevicePath, // ControllerPath + NULL, // Clock + NULL // ClockParameter }; -CONST EFI_SPI_BUS *CONST mSpiBusList[] = { +CONST EFI_SPI_BUS *CONST mSpiBusList[] = { &mSpiBus1 }; -EFI_SPI_CONFIGURATION_PROTOCOL mBoardSpiConfigProtocol = { +EFI_SPI_CONFIGURATION_PROTOCOL mBoardSpiConfigProtocol = { 0x1, // BusCount mSpiBusList // BusList }; -/** - Build the SPI peripheral list. - @retval EFI_SUCCESS The SPI peripheral list is built successfully. - @retval EFI_DEVICE_ERROR Failed to build the SPI peripheral list. -**/ EFI_STATUS EFIAPI BuildSpiList ( ) { - EFI_STATUS Status; - UINTN Index; - EFI_SPI_BUS **SpiBus; - EFI_SPI_PERIPHERAL **Peripheral; + EFI_STATUS Status; + UINTN Index; + EFI_SPI_BUS **SpiBus; + EFI_SPI_PERIPHERAL **Peripheral; - DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); Status = EFI_DEVICE_ERROR; // Update all Peripherals for the single SpiBus for (Index = 0; Index < (sizeof (mPeripherallist) / sizeof (EFI_SPI_PERIPHERAL)); - Index++) - { - DEBUG (( - DEBUG_INFO, - "%a: Setting up SpiPeripheral: %s, by %s, PN=%s\n", - __func__, - mPeripherallist[Index].FriendlyName, - mPeripherallist[Index].SpiPart->Vendor, - mPeripherallist[Index].SpiPart->PartNumber - )); + Index++) { + DEBUG((DEBUG_INFO, "%a: Setting up SpiPeripheral: %s, by %s, PN=%s\n", + __FUNCTION__, + mPeripherallist[Index].FriendlyName, + mPeripherallist[Index].SpiPart->Vendor, + mPeripherallist[Index].SpiPart->PartNumber)); // Put bus address in peripheral - SpiBus = (EFI_SPI_BUS **)&mPeripherallist[Index].SpiBus; + SpiBus = (EFI_SPI_BUS **)&mPeripherallist[Index].SpiBus; *SpiBus = &mSpiBus1; if (Index > 0) { // Fill NextSpiPeripheral @@ -136,14 +124,13 @@ BuildSpiList ( } // Put Peripheral list in bus - Peripheral = (EFI_SPI_PERIPHERAL **)&mSpiBus1.Peripherallist; + Peripheral = (EFI_SPI_PERIPHERAL **)&mSpiBus1.Peripherallist; *Peripheral = &mPeripherallist[0]; Status = EFI_SUCCESS; - DEBUG ((DEBUG_INFO, "%a: Exit Status=%r\n", __func__, Status)); + DEBUG((DEBUG_INFO, "%a: Exit Status=%r\n", __FUNCTION__, Status)); return Status; } - /** Entry point of the Board SPI Configuration driver. @@ -156,24 +143,24 @@ BuildSpiList ( EFI_STATUS EFIAPI BoardSpiConfigProtocolEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; - DEBUG ((DEBUG_INFO, "%a - ENTRY\n", __func__)); + DEBUG((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); Status = BuildSpiList (); Status = gBS->InstallProtocolInterface ( - &mSpiConfigHandle, - &gEfiSpiConfigurationProtocolGuid, - EFI_NATIVE_INTERFACE, - &mBoardSpiConfigProtocol - ); + &mSpiConfigHandle, + &gEfiSpiConfigurationProtocolGuid, + EFI_NATIVE_INTERFACE, + &mBoardSpiConfigProtocol + ); - DEBUG ((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __func__, Status)); + DEBUG((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __FUNCTION__, Status)); return Status; } diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf index 2f125cdfa829d02046f6da81bcd3a3eb080ad453..854ccbb58203242d1c6297e1a24033f441a49bd7 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf @@ -1,10 +1,11 @@ -## @file -# AMD Board SPI config Description File +#/** @file # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Component description file for SpiFvbDxe module # +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent -## +# +#**/ [Defines] INF_VERSION = 0x00010019 @@ -17,8 +18,8 @@ [Packages] MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec AmdPlatformPkg/AmdPlatformPkg.dec + AgesaModulePkg/AgesaModuleFchPkg.dec [LibraryClasses] DebugLib diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigExtra.uni b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigExtra.uni index d148f694696732dfa36338a87d400a9ee83d5c87..f50962b42f7e5605931b7269ea0fbddd1ef14c07 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigExtra.uni +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigExtra.uni @@ -1,9 +1,9 @@ -// /** @file -// -// Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// **/ +// /***************************************************************************** +// * +// * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +// * SPDX-License-Identifier: BSD-2-Clause-Patent +// * +// *****************************************************************************/ #string STR_PROPERTIES_MODULE_NAME #language en-US "SPI Configuration Protocol Driver" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.c index 4e1c5577364f46d695707eca4317ac9ffa11ad2f..fe9e0cdc4ceffc6ecbf9d4f1606db4f20540a75a 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.c +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.c @@ -2,9 +2,9 @@ FV block I/O protocol driver for SPI flash libary. - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include @@ -17,14 +17,9 @@ #include #include -SPI_CONTROLLER_DEVICE_PATH mFchDevicePath = FCH_DEVICE_PATH; - -CHIP_SELECT_PARAMETERS ChipSelect1 = CHIP_SELECT_1; -CHIP_SELECT_PARAMETERS ChipSelect2 = CHIP_SELECT_2; - -EFI_HANDLE mSpiConfigHandle = NULL; +EFI_HANDLE mSpiConfigHandle = NULL; -CONST EFI_SPI_PART Mx25u6435f = { +CONST EFI_SPI_PART Mx25u6435f = { L"Macronix", // Vendor L"MX25U6435F", // PartNumber 0, // MinClockHz @@ -65,7 +60,6 @@ EFI_SPI_CONFIGURATION_PROTOCOL mBoardSpiConfigProtocol = { 0x1, // BusCount mSpiBusList // BusList }; - /** Check if SAFS mode is enabled @@ -85,7 +79,6 @@ IsEspiSafsMode ( // romtype [5:4] 10: eSPI with SAFS support return TRUE; } - return FALSE; } @@ -143,7 +136,6 @@ BuildSpiList ( DEBUG ((DEBUG_INFO, "%a: Exit Status=%r\n", __func__, Status)); return Status; } - /** Entry point of the Board SPI Configuration driver. diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf index a8125777236e2b2ad610a10b3de30b9060b7678f..cfc4376cf902fa685659b6841c06838c092ca221 100644 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf @@ -1,10 +1,11 @@ -## @file -# AMD Board SPI config SMM Description File +#/** @file # -# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# Component description file for SpiFvbDxe module # +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent -## +# +#**/ [Defines] INF_VERSION = 0x00010019 @@ -17,8 +18,8 @@ [Packages] MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec AmdPlatformPkg/AmdPlatformPkg.dec + AgesaModulePkg/AgesaModuleFchPkg.dec [LibraryClasses] DebugLib @@ -27,6 +28,7 @@ UefiDriverEntryPoint UefiBootServicesTableLib IoLib + PciLib [Sources] BoardSpiConfigSmm.c diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlash.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlash.c new file mode 100644 index 0000000000000000000000000000000000000000..95d7c3cdc45209daac643145e3804dbcf1256064 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlash.c @@ -0,0 +1,1191 @@ +/***************************************************************************** + * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "EspiNorFlashInstance.h" +#include +#include +#include +#include + +/** + Fill Write Buffer with Opcode, Address, Dummy Bytes, and Data + + @param[in] Opcode - Opcode for transaction + @param[in] Address - SPI Offset Start Address + @param[in] WriteBytes - Number of bytes to write to SPI device + @param[in] WriteBuffer - Buffer containing bytes to write to SPI device + + @retval Size of Data in Buffer +**/ +UINT32 +FillWriteBuffer ( + IN ESPI_NOR_FLASH_INSTANCE *Instance, + IN UINT8 Opcode, + IN UINT32 DummyBytes, + IN UINT8 AddressBytesSupported, + IN BOOLEAN UseAddress, + IN UINT32 Address, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer + ) +{ + UINT32 AddressSize; + UINT32 BigEndianAddress; + UINT32 Index; + + // Copy Opcode into Write Buffer + Instance->SpiTransactionWriteBuffer[0] = Opcode; + Index = 1; + if (UseAddress == TRUE) { + if (AddressBytesSupported == SPI_ADDR_3BYTE_ONLY) { + AddressSize = 3; + } else if (AddressBytesSupported == SPI_ADDR_4BYTE_ONLY) { + AddressSize = 4; + // EPYC processor will always have SPI HC and SPI part configured for + // 4-byte addressing if the SPI part is > 16MB. + } else if (Instance->Protocol.FlashSize <= SIZE_16MB) { + AddressSize = 3; + } else { + // SPI part is > 16MB use 4-byte addressing. + AddressSize = 4; + } + + BigEndianAddress = SwapBytes32 ((UINT32)Address); + BigEndianAddress >>= ((sizeof (UINT32) - AddressSize) * 8); + CopyMem ( + &Instance->SpiTransactionWriteBuffer[Index], + &BigEndianAddress, + AddressSize + ); + Index += AddressSize; + } + + // Fill DummyBytes + if (DummyBytes != 0) { + SetMem ( + &Instance->SpiTransactionWriteBuffer[Index], + DummyBytes, + 0 + ); + Index += DummyBytes; + } + + // Fill Data + if (WriteBytes > 0) { + CopyMem ( + &Instance->SpiTransactionWriteBuffer[Index], + WriteBuffer, + WriteBytes + ); + Index += WriteBytes; + } + + return Index; +} + +/** + Internal Read the flash status register. + + This routine reads the flash part status register. + + @param[in] Instance SPI_NOR_FLASH_INSTANCE + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +EFI_STATUS +EFIAPI +InternalReadStatus ( + IN ESPI_NOR_FLASH_INSTANCE *Instance, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + + // Read Status register + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSR, + SPI_FLASH_RDSR_DUMMY, + SPI_FLASH_RDSR_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 1, + FlashStatus + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + Set Write Enable Latch + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS SPI Write Enable succeeded + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +SetWel ( + IN ESPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_WREN, + SPI_FLASH_WREN_DUMMY, + SPI_FLASH_WREN_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Check for not device write in progress + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS Device does not have a write in progress + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +WaitNotWip ( + IN ESPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT8 DeviceStatus; + UINTN RetryCount; + UINTN DelayMicroseconds; + + DelayMicroseconds = FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + RetryCount = FixedPcdGet32 (PcdSpiNorFlashOperationRetryCount); + if (RetryCount == 0) { + RetryCount = 1; + } + + do { + Status = InternalReadStatus (Instance, 1, &DeviceStatus); + ASSERT_EFI_ERROR (Status); + if ( EFI_ERROR (Status) + || ((DeviceStatus & SPI_FLASH_SR_WIP) == SPI_FLASH_SR_NOT_WIP)) + { + break; + } + + MicroSecondDelay (DelayMicroseconds); + RetryCount--; + } while (RetryCount > 0); + + if (RetryCount == 0) { + DEBUG ((DEBUG_ERROR, "SpiNorFlash:%a: Timeout error\n", __FUNCTION__)); + Status = EFI_DEVICE_ERROR; + } + + return Status; +} + +/** + Check for write enable latch set and not device write in progress + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +WaitWelNotWip ( + IN ESPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT8 DeviceStatus; + UINTN RetryCount; + UINTN DelayMicroseconds; + + DelayMicroseconds = FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + RetryCount = FixedPcdGet32 (PcdSpiNorFlashOperationRetryCount); + if (RetryCount == 0) { + RetryCount = 1; + } + + do { + Status = InternalReadStatus (Instance, 1, &DeviceStatus); + ASSERT_EFI_ERROR (Status); + if ( EFI_ERROR (Status) + || ((DeviceStatus & (SPI_FLASH_SR_WIP | SPI_FLASH_SR_WEL)) + == SPI_FLASH_SR_WEL)) + { + break; + } + + MicroSecondDelay (DelayMicroseconds); + RetryCount--; + } while (RetryCount > 0); + + if (RetryCount == 0) { + DEBUG ((DEBUG_ERROR, "SpiNorFlash:%a: Timeout error\n", __FUNCTION__)); + Status = EFI_DEVICE_ERROR; + } + + return Status; +} + +/** + Check for not write enable latch set and not device write in progress + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is not set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +WaitNotWelNotWip ( + IN ESPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT8 DeviceStatus; + UINTN RetryCount; + UINTN DelayMicroseconds; + + DelayMicroseconds = FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + RetryCount = FixedPcdGet32 (PcdSpiNorFlashOperationRetryCount); + if (RetryCount == 0) { + RetryCount = 1; + } + + do { + Status = InternalReadStatus (Instance, 1, &DeviceStatus); + ASSERT_EFI_ERROR (Status); + if ( EFI_ERROR (Status) + || ((DeviceStatus & (SPI_FLASH_SR_WIP | SPI_FLASH_SR_WEL)) + == SPI_FLASH_SR_NOT_WIP)) + { + break; + } + + MicroSecondDelay (DelayMicroseconds); + RetryCount--; + } while (RetryCount > 0); + + if (RetryCount == 0) { + DEBUG ((DEBUG_ERROR, "SpiNorFlash:%a: Timeout error\n", __FUNCTION__)); + Status = EFI_DEVICE_ERROR; + } + + return Status; +} + +/** + Read the 3 byte manufacture and device ID from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the 3 byte manufacture and device ID from the flash part + filling the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure. + @param[out] Buffer Pointer to a 3 byte buffer to receive the manufacture and + device ID. + + + + @retval EFI_SUCCESS The manufacture and device ID was read + successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +GetFlashId ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT32 TransactionBufferLength; + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + if (Instance->EspiSafsMode) { + // ESPI SAFS + Buffer[0] = 0; + Buffer[1] = 0; + Buffer[2] = 0; + return EFI_SUCCESS; + } + + // Check not WIP + Status = WaitNotWip (Instance); + + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDID, + SPI_FLASH_RDID_DUMMY, + SPI_FLASH_RDID_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 3, + Buffer + ); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + Check if SAFS mode is enabled + + @param[out] EspiBaseAddress Base Address of Espi Controller + + @retval TRUE SAFS mode is enabled. + @retval FALSE MAFS mode is enabled + +**/ +BOOLEAN +EFIAPI +IsEspiSafsMode ( + OUT UINT32 *EspiBaseAddress + ) +{ + UINT32 MISC80; + + MISC80 = MmioRead32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80); + if ((MISC80 & BIT3)) { + // romtype [5:4] 10: eSPI with SAFS support + *EspiBaseAddress = (( + PciRead32 (PCI_LIB_ADDRESS (FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0)) + ) & 0xFFFFFF00) + PcdGet32(PcdAmdEspiOffset); + return TRUE; + } + return FALSE; +} + +/** + Read data from the SPI flash at not fast speed + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +LfReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT8 *CurrentBuffer; + UINT32 Length; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + + Status = EFI_DEVICE_ERROR; + if ((Buffer == NULL) || + (FlashAddress >= This->FlashSize) || + (LengthInBytes > This->FlashSize - FlashAddress)) + { + return EFI_INVALID_PARAMETER; + } + + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + + CurrentBuffer = Buffer; + Length = 0; + for (ByteCounter = 0; ByteCounter < LengthInBytes;) { + CurrentAddress = FlashAddress + ByteCounter; + CurrentBuffer = Buffer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Check not WIP + Status = WaitNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Read Data + if (EFI_ERROR (Status)) { + break; + } + + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_READ, + SPI_FLASH_READ_DUMMY, + SPI_FLASH_READ_ADDR_BYTES, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + Length, + CurrentBuffer + ); + ASSERT_EFI_ERROR (Status); + ByteCounter += Length; + } + + return Status; +} + +/** + Read data from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +ReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT8 *CurrentBuffer; + UINT32 Length; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + + Status = EFI_DEVICE_ERROR; + if ((Buffer == NULL) || + (FlashAddress >= This->FlashSize) || + (LengthInBytes > This->FlashSize - FlashAddress)) + { + return EFI_INVALID_PARAMETER; + } + + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + if (Instance->EspiSafsMode) { + // ESPI SAFS + MaximumTransferBytes = Instance->EspiMaxReadReqSize; + } + + CurrentBuffer = Buffer; + for (ByteCounter = 0; ByteCounter < LengthInBytes;) { + CurrentAddress = FlashAddress + ByteCounter; + CurrentBuffer = Buffer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + if (Instance->EspiSafsMode) { + // ESPI SAFS + Status = FchEspiCmd_SafsFlashRead (Instance->EspiBaseAddress, CurrentAddress, Length, CurrentBuffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Espi Read Data FchEspiCmd_SafsFlashRead ERROR Status -%r\n", Status)); + } + } else { + // MAFS + // Check not WIP + Status = WaitNotWip (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Espi read data ERROR after WaitNotWip: Status = %r\n", Status)); + break; + } + + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_FAST_READ, + SPI_FLASH_FAST_READ_DUMMY, + SPI_FLASH_FAST_READ_ADDR_BYTES, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + Length, + CurrentBuffer + ); + } + + ASSERT_EFI_ERROR (Status); + ByteCounter += Length; + } + + return Status; +} + +/** + Read the flash status register. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +EFI_STATUS +EFIAPI +ReadStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + + if (LengthInBytes != 1) { + return EFI_INVALID_PARAMETER; + } + + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + + Status = InternalReadStatus (Instance, LengthInBytes, FlashStatus); + + return Status; +} + +/** + Write the flash status register. + + This routine must be called at or below TPL_N OTIFY. + This routine writes the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to write. + @param[in] FlashStatus Pointer to a buffer containing the new status. + + @retval EFI_SUCCESS The status write was successful. + @retval EFI_OUT_OF_RESOURCES Failed to allocate the write buffer. + +**/ +EFI_STATUS +EFIAPI +WriteStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + IN UINT8 *FlashStatus + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT32 TransactionBufferLength; + + if (LengthInBytes != 1) { + return EFI_INVALID_PARAMETER; + } + + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + + // Check not WIP + Status = WaitNotWip (Instance); + + // Set Write Enable + if (!EFI_ERROR (Status)) { + Status = SetWel (Instance); + ASSERT_EFI_ERROR (Status); + + // Check not WIP & WEL enabled + if (!EFI_ERROR (Status)) { + Status = WaitWelNotWip (Instance); + + // Write the Status Register + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_WRSR, + SPI_FLASH_WRSR_DUMMY, + SPI_FLASH_WRSR_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + } + } + } + + return Status; +} + +/** + Write data to the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine breaks up the write operation as necessary to write the data to + the SPI part. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start writing + @param[in] LengthInBytes Write length in bytes + @param[in] Buffer Address of a buffer containing the data + + @retval EFI_SUCCESS The data was written successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + @retval EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer. + +**/ +EFI_STATUS +EFIAPI +WriteData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT32 Length; + UINT32 BytesUntilBoundary; + UINT8 *CurrentBuffer; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + UINT32 SpiFlashPageSize; + + Status = EFI_DEVICE_ERROR; + if ((Buffer == NULL) || + (LengthInBytes == 0) || + (FlashAddress >= This->FlashSize) || + (LengthInBytes > This->FlashSize - FlashAddress)) + { + return EFI_INVALID_PARAMETER; + } + + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + if (Instance->EspiSafsMode) { + // ESPI SAFS + MaximumTransferBytes = Instance->EspiMaxPayloadSize; + } + + if (Instance->SfdpBasicFlashByteCount >= 11 * 4) { + // JESD216C spec DWORD 11 + SpiFlashPageSize = 1 << (Instance->SfdpBasicFlash->PageSize); + } else { + SpiFlashPageSize = 256; + } + + CurrentBuffer = Buffer; + for (ByteCounter = 0; ByteCounter < LengthInBytes;) { + CurrentAddress = FlashAddress + ByteCounter; + CurrentBuffer = Buffer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Cannot cross SpiFlashPageSize boundary + BytesUntilBoundary = SpiFlashPageSize + - (CurrentAddress % SpiFlashPageSize); + if ((BytesUntilBoundary != 0) && (Length > BytesUntilBoundary)) { + Length = BytesUntilBoundary; + } + + if (Instance->EspiSafsMode) { + // ESPI SAFS + Status = FchEspiCmd_SafsFlashWrite (Instance->EspiBaseAddress, CurrentAddress, Length, CurrentBuffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "ESPI %a - ERROR after FchEspiCmd_SafsFlashWrite Status -%r\n", __FUNCTION__, Status)); + ASSERT_EFI_ERROR (Status); + break; + } + } else { + // SPI MAFS + // Check not WIP + Status = WaitNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Set Write Enable + Status = SetWel (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Check not WIP & WEL enabled + Status = WaitWelNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Write Data + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_PP, + SPI_FLASH_PP_DUMMY, + SPI_FLASH_PP_ADDR_BYTES, + TRUE, + CurrentAddress, + Length, + CurrentBuffer + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + break; + } + + // Check not WIP & not WEL + Status = WaitNotWelNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + } + + ASSERT_EFI_ERROR (Status); + ByteCounter += Length; + } + + return Status; +} +/** + Force a 64KB erase for eSPI SAFS mode. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address within a 4 KiB block to start erasing + @param[in] BlockCount Number of 4 KiB blocks to erase + + @retval EFI_SUCCESS The erase was completed successfully. + @retval EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize, or + BlockCount * 4 KiB + > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +SafsFlashEraseForce64k ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 BlockCount + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT32 EraseLength; + UINT32 CurrentAddress4k; + UINT32 CurrentAddress; + UINT32 Length; + ESPI_SL44_SLAVE_FA_CAPCFG2 FaCapCfg2; + UINT32 EndAddress64k; + UINT32 StartAddress64k; + UINT32 EndAddress4k; + UINT8 *WriteBackBufferBlock1; + UINT8 *WriteBackBufferBlock2; + UINT32 WriteBackSize1; + UINT32 WriteBackSize2; + + Status = EFI_DEVICE_ERROR; + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + EraseLength = BlockCount * SIZE_4KB; + + // Align start Address to 64KB + CurrentAddress4k = FlashAddress & ~(SIZE_4KB - 1); + if ((BlockCount == 0) || + (CurrentAddress4k >= This->FlashSize) || + (EraseLength > This->FlashSize - CurrentAddress4k)) + { + DEBUG ((DEBUG_INFO, "ERROR in Erase, EraseLength=%X, CurrentAddress=%X, BlockCount=%X\n", EraseLength, CurrentAddress4k, BlockCount)); + return EFI_INVALID_PARAMETER; + } + + EndAddress4k = CurrentAddress4k + EraseLength; + // Round down to 64K aligned boundary + StartAddress64k = FlashAddress & ~(SIZE_64KB - 1); + + EndAddress64k = EndAddress4k + (SIZE_64KB - 1); + EndAddress64k = EndAddress64k & ~(SIZE_64KB - 1); + + WriteBackSize1 = CurrentAddress4k - StartAddress64k; + WriteBackSize2 = EndAddress64k - EndAddress4k; + + WriteBackBufferBlock1 = AllocateZeroPool (CurrentAddress4k - StartAddress64k); + WriteBackBufferBlock2 = AllocateZeroPool (EndAddress64k - EndAddress4k); + + // now read from [startAddress64k, CurrentAddress] + if (CurrentAddress4k != StartAddress64k) { + Status = ReadData (This, StartAddress64k, CurrentAddress4k-StartAddress64k, WriteBackBufferBlock1); + } + + if (EndAddress4k != EndAddress64k) { + Status = ReadData (This, EndAddress4k, EndAddress64k-EndAddress4k, WriteBackBufferBlock2); + } + + for (CurrentAddress = StartAddress64k; CurrentAddress < EndAddress64k;) { + Length = EndAddress64k - CurrentAddress; + FaCapCfg2.Value = Instance->EspiEraseBlockMap; + + if (((CurrentAddress % SIZE_64KB) == 0) && + (Length >= SIZE_64KB) && + ((FaCapCfg2.Field.RO_TargetFlashEraseBlockSize & BIT6) != 0)) { + Length = SIZE_64KB; + DEBUG ((DEBUG_INFO, " 64KB Block Erase at Address=0x%x\n", CurrentAddress)); + Status = FchEspiCmd_SafsFlashErase (Instance->EspiBaseAddress, CurrentAddress, 2); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "ESPI %a - ERROR after FchEspiCmd_SafsFlashErase Status -%r\n", __FUNCTION__, Status)); + ASSERT_EFI_ERROR (Status); + break; + } + + ASSERT_EFI_ERROR (Status); + CurrentAddress += Length; + } + + if (WriteBackSize1 > 0) { + Status = WriteData (This, StartAddress64k, WriteBackSize1, WriteBackBufferBlock1); + } + + if (WriteBackSize2 > 0 ) { + Status = WriteData (This, EndAddress4k, WriteBackSize2, WriteBackBufferBlock2); + } + + FreePool (WriteBackBufferBlock1); + FreePool (WriteBackBufferBlock2); + return Status; +} + +/** + Efficiently erases one or more 4KiB regions in the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine uses a combination of 4 KiB and larger blocks to erase the + specified area. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address within a 4 KiB block to start erasing + @param[in] BlockCount Number of 4 KiB blocks to erase + + @retval EFI_SUCCESS The erase was completed successfully. + @retval EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize, or + BlockCount * 4 KiB + > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +Erase ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 BlockCount + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + UINT8 Opcode; + UINT32 Dummy; + UINT8 AddrBytes; + UINT32 ByteCounter; + UINT32 EraseLength; + UINT32 CurrentAddress; + UINT32 Length; + UINT32 TransactionBufferLength; + ESPI_SL44_SLAVE_FA_CAPCFG2 FaCapCfg2; + + Status = EFI_DEVICE_ERROR; + Instance = ESPI_NOR_FLASH_FROM_THIS (This); + EraseLength = BlockCount * SIZE_4KB; + // Align start Address to 4KB + CurrentAddress = FlashAddress & ~(SIZE_4KB - 1); + if ((BlockCount == 0) || + (CurrentAddress >= This->FlashSize) || + (EraseLength > This->FlashSize - CurrentAddress)) + { + return EFI_INVALID_PARAMETER; + } + + for (ByteCounter = 0; ByteCounter < EraseLength;) { + CurrentAddress = FlashAddress + ByteCounter; + Length = EraseLength - ByteCounter; + + if (Instance->EspiSafsMode) { + // ESPI SAFS + FaCapCfg2.Value = Instance->EspiEraseBlockMap; + // Calculate largest erase size for this pass + if (((CurrentAddress % SIZE_128KB) == 0) && + (Length >= SIZE_128KB) && + ((FaCapCfg2.Field.RO_TargetFlashEraseBlockSize & BIT7) != 0)) + { + Length = SIZE_128KB; + DEBUG ((DEBUG_INFO, " 128KB Block Erase at Address=0x%x\n", CurrentAddress)); + Status = FchEspiCmd_SafsFlashErase (Instance->EspiBaseAddress, CurrentAddress, 3); + } else if (((CurrentAddress % SIZE_64KB) == 0) && + (Length >= SIZE_64KB) && + ((FaCapCfg2.Field.RO_TargetFlashEraseBlockSize & BIT6) != 0)) + { + Length = SIZE_64KB; + DEBUG ((DEBUG_INFO, " 64KB Block Erase at Address=0x%x\n", CurrentAddress)); + Status = FchEspiCmd_SafsFlashErase (Instance->EspiBaseAddress, CurrentAddress, 2); + } else if (((CurrentAddress % SIZE_32KB) == 0) && + (Length >= SIZE_32KB) && + ((FaCapCfg2.Field.RO_TargetFlashEraseBlockSize & BIT5) != 0)) + { + Length = SIZE_32KB; + DEBUG ((DEBUG_INFO, " 32KB Block Erase at Address=0x%x\n", CurrentAddress)); + Status = FchEspiCmd_SafsFlashErase (Instance->EspiBaseAddress, CurrentAddress, 1); + } else if ((FaCapCfg2.Field.RO_TargetFlashEraseBlockSize & BIT6) != 0) { + // force 64K erase as a workaround + Status = SafsFlashEraseForce64k (This, FlashAddress, BlockCount); + break; + } else { + DEBUG ((DEBUG_INFO, " 4KB Block Erase at Address=0x%x\n", CurrentAddress)); + Length = SIZE_4KB; + Status = FchEspiCmd_SafsFlashErase (Instance->EspiBaseAddress, CurrentAddress, 0); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "ESPI %a - ERROR after FchEspiCmd_SafsFlashErase Status -%r\n", __func__, Status)); + ASSERT_EFI_ERROR (Status); + break; + } + } else { + // SPI MAFS + // Calculate largest erase size for this pass + if (Length == This->FlashSize) { + Opcode = SPI_FLASH_CE; + Dummy = SPI_FLASH_CE_DUMMY; + AddrBytes = SPI_FLASH_CE_ADDR_BYTES; + } else if (((CurrentAddress % SIZE_64KB) == 0) && + (Length >= SIZE_64KB)) + { + Opcode = SPI_FLASH_BE; + Dummy = SPI_FLASH_BE_DUMMY; + AddrBytes = SPI_FLASH_BE_ADDR_BYTES; + Length = SIZE_64KB; + } else if (((CurrentAddress % SIZE_32KB) == 0) && + (Length >= SIZE_32KB)) + { + Opcode = SPI_FLASH_BE32K; + Dummy = SPI_FLASH_BE32K_DUMMY; + AddrBytes = SPI_FLASH_BE32K_ADDR_BYTES; + Length = SIZE_32KB; + } else { + Opcode = SPI_FLASH_SE; + Dummy = SPI_FLASH_SE_DUMMY; + AddrBytes = SPI_FLASH_SE_ADDR_BYTES; + Length = SIZE_4KB; + } + + // Check not WIP + Status = WaitNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Set Write Enable + Status = SetWel (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Check not WIP & WEL enabled + Status = WaitWelNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Erase Block + TransactionBufferLength = FillWriteBuffer ( + Instance, + Opcode, + Dummy, + AddrBytes, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + break; + } + + // Check not WIP & not WEL + Status = WaitNotWelNotWip (Instance); + if (EFI_ERROR (Status)) { + break; + } + } + + ASSERT_EFI_ERROR (Status); + ByteCounter += Length; + } + + return Status; +} \ No newline at end of file diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlash.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlash.h new file mode 100644 index 0000000000000000000000000000000000000000..523a2826cdc57e0b5c780cec27b366af72d10028 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlash.h @@ -0,0 +1,327 @@ +/***************************************************************************** + * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + *****************************************************************************/ + +#ifndef ESPI_NOR_FLASH_H_ +#define ESPI_NOR_FLASH_H_ + +#include +#include +#include +#include "EspiNorFlashInstance.h" + +/** + Fill Write Buffer with Opcode, Address, Dummy Bytes, and Data + + @param[in] Opcode - Opcode for transaction + @param[in] Address - SPI Offset Start Address + @param[in] WriteBytes - Number of bytes to write to SPI device + @param[in] WriteBuffer - Buffer containing bytes to write to SPI device + + @retval Size of Data in Buffer +**/ +UINT32 +FillWriteBuffer ( + IN ESPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT8 Opcode, + IN UINT32 DummyBytes, + IN UINT8 AddressBytesSupported, + IN BOOLEAN UseAddress, + IN UINT32 Address, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer + ); + +/** + Set Write Enable Latch + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS SPI Write Enable succeeded + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +SetWel ( + IN ESPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance + ); + +/** + Check for not device write in progress + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS Device does not have a write in progress + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +WaitNotWip ( + IN ESPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance + ); + +/** + Check for write enable latch set and not device write in progress + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +WaitWelNotWip ( + IN ESPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance + ); + +/** + Check for not write enable latch set and not device write in progress + + @param[in] Instance - SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is not set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +EFIAPI +WaitNotWelNotWip ( + IN ESPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance + ); + +/** + Set the flash size based on the chip connected. + + This routine reads parameters from the SPI chip to determine the SPI flash + size. + + @param[in] SpiNorInstance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +InstallFlashSize ( + IN ESPI_NOR_FLASH_INSTANCE *SpiNorInstance + ); + +/** + Read the 3 byte manufacture and device ID from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the 3 byte manufacture and device ID from the flash part + filling the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure. + @param[out] Buffer Pointer to a 3 byte buffer to receive the manufacture and + device ID. + + + + @retval EFI_SUCCESS The manufacture and device ID was read + successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +GetFlashId ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + OUT UINT8 *Buffer + ); + +/** + Read data from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +ReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ); + +/** + Read data from the SPI flash at not fast speed + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +LfReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ); + +/** + Read the flash status register. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +EFI_STATUS +EFIAPI +ReadStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ); + +/** + Write the flash status register. + + This routine must be called at or below TPL_N OTIFY. + This routine writes the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to write. + @param[in] FlashStatus Pointer to a buffer containing the new status. + + @retval EFI_SUCCESS The status write was successful. + @retval EFI_OUT_OF_RESOURCES Failed to allocate the write buffer. + +**/ +EFI_STATUS +EFIAPI +WriteStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + IN UINT8 *FlashStatus + ); + +/** + Write data to the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine breaks up the write operation as necessary to write the data to + the SPI part. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start writing + @param[in] LengthInBytes Write length in bytes + @param[in] Buffer Address of a buffer containing the data + + @retval EFI_SUCCESS The data was written successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + @retval EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer. + +**/ +EFI_STATUS +EFIAPI +WriteData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + IN UINT8 *Buffer + ); + +/** + Efficiently erases one or more 4KiB regions in the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine uses a combination of 4 KiB and larger blocks to erase the + specified area. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address within a 4 KiB block to start erasing + @param[in] BlockCount Number of 4 KiB blocks to erase + + @retval EFI_SUCCESS The erase was completed successfully. + @retval EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize, or + BlockCount * 4 KiB + > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +Erase ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 BlockCount + ); + +/** + Read SFDP parameters into buffer + + This routine reads the JEDEC SPI Flash Discoverable Parameters from the SPI + chip. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +ReadSfdpBasicParameterTable ( + IN ESPI_NOR_FLASH_INSTANCE *Instance + ); + +/** + Check if SAFS mode is enabled + + @param[out] EspiBaseAddress Base Address of Espi Controller + + @retval TRUE SAFS mode is enabled. + @retval FALSE MAFS mode is enabled + +**/ +BOOLEAN +EFIAPI +IsEspiSafsMode ( + OUT UINT32 *EspiBaseAddress + ); + +#endif // ESPI_NOR_FLASH_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashInstance.h b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashInstance.h new file mode 100644 index 0000000000000000000000000000000000000000..75b399caba100734a68ec17d4f9f9aec8b62df37 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashInstance.h @@ -0,0 +1,38 @@ +/***************************************************************************** + * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + *****************************************************************************/ + +#ifndef ESPI_NOR_FLASH_INSTANCE_H_ +#define ESPI_NOR_FLASH_INSTANCE_H_ + +#include +#include +#include +#include +#include +#include + +#define ESPI_NOR_FLASH_SIGNATURE SIGNATURE_32 ('e', 's', 'n', 'f') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SPI_NOR_FLASH_PROTOCOL Protocol; + EFI_SPI_IO_PROTOCOL *SpiIo; + UINT32 SfdpBasicFlashByteCount; + SFDP_BASIC_FLASH_PARAMETER *SfdpBasicFlash; + UINT8 *SpiTransactionWriteBuffer; + UINT32 SpiTransactionWriteBufferIndex; + BOOLEAN EspiSafsMode; + UINT32 EspiBaseAddress; + UINT32 EspiMaxReadReqSize; + UINT32 EspiMaxPayloadSize; + UINT32 EspiEraseBlockMap; +} ESPI_NOR_FLASH_INSTANCE; + +#define ESPI_NOR_FLASH_FROM_THIS(a) \ + CR (a, ESPI_NOR_FLASH_INSTANCE, Protocol, \ + ESPI_NOR_FLASH_SIGNATURE) + +#endif // ESPI_NOR_FLASH_INSTANCE_H_ diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSfdp.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSfdp.c new file mode 100644 index 0000000000000000000000000000000000000000..2bae269a2879961ecb4c4a8d951af0405b744e10 --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSfdp.c @@ -0,0 +1,254 @@ +/***************************************************************************** + * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include "EspiNorFlash.h" +#include "EspiNorFlashInstance.h" + +/** + Read SFDP Header + + This routine reads the JEDEC SPI Flash Discoverable Parameter header from the + SPI chip. Fails if Major Revision is not = 1 + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] SfdpHeader SFDP Header Buffer Pointer + + @retval EFI_SUCCESS Header is filled in + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +ReadSfdpHeader ( + IN ESPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_HEADER *SfdpHeader + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + + // Check not WIP + Status = WaitNotWip (Instance); + + // Read SFDP Header + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSFDP, + SPI_FLASH_RDSFDP_DUMMY, + SPI_FLASH_RDSFDP_ADDR_BYTES, + TRUE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + sizeof (SFDP_HEADER), + (UINT8 *)SfdpHeader + ); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + // Read Basic Flash Parameter Header + if ((SfdpHeader->Signature != SFDP_HEADER_SIGNATURE) || + (SfdpHeader->MajorRev != SFDP_SUPPORTED_MAJOR_REVISION)) + { + Status = EFI_DEVICE_ERROR; + } + } + + return Status; +} + +/** + Read SFDP Basic Parameter Header + + This routine reads the JEDEC SPI Flash Discoverable Parameter header from the + SPI chip. Fails if Major Revision is not = 1 + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] SfdpHeader SFDP Header Buffer Pointer + + @retval EFI_SUCCESS Header is filled in + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +ReadSfdpBasicParameterHeader ( + IN ESPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_PARAMETER_HEADER *SfdpParameterHeader + ) +{ + EFI_STATUS Status; + UINT32 Index; + SFDP_HEADER SfdpHeader; + SFDP_PARAMETER_HEADER LocalSfdpParameterHeader; + UINT32 TransactionBufferLength; + + Status = ReadSfdpHeader (Instance, &SfdpHeader); + if (!EFI_ERROR (Status)) { + // Parse Parameter Headers Starting at Index 1 = Byte 8 + ZeroMem (SfdpParameterHeader, sizeof (SFDP_PARAMETER_HEADER)); + for (Index = 1; Index <= (UINT32)(SfdpHeader.NumParameterHeaders + 1); Index++) { + // Check not WIP + Status = WaitNotWip (Instance); + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSFDP, + SPI_FLASH_RDSFDP_DUMMY, + SPI_FLASH_RDSFDP_ADDR_BYTES, + TRUE, + Index * 8, // Parameter Header Index + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + sizeof (LocalSfdpParameterHeader), + (UINT8 *)&LocalSfdpParameterHeader + ); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + // Break if SfdParamHeader is Type 0, Basic SPI Protocol Parameters + if ((LocalSfdpParameterHeader.IdLsb == 0x00) && + (LocalSfdpParameterHeader.IdMsb == 0xFF) && + (LocalSfdpParameterHeader.MajorRev == 1) && + (LocalSfdpParameterHeader.MinorRev >= SfdpParameterHeader->MinorRev)) + { + CopyMem ( + SfdpParameterHeader, + &LocalSfdpParameterHeader, + sizeof (SFDP_PARAMETER_HEADER) + ); + } + } else { + break; + } + } else { + break; + } + } + + if ((SfdpParameterHeader->IdLsb != 0x00) || + (SfdpParameterHeader->IdMsb != 0xFF)) + { + Status = EFI_DEVICE_ERROR; + } + } + + return Status; +} + +/** + Read SFDP parameters into buffer + + This routine reads the JEDEC SPI Flash Discoverable Parameters from the SPI + chip. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +ReadSfdpBasicParameterTable ( + IN ESPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + SFDP_PARAMETER_HEADER SfdpBasicFlashParamHeader; + UINT32 LengthInBytes; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT8 *CurrentBuffer; + UINT32 Length; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + + Status = ReadSfdpBasicParameterHeader (Instance, &SfdpBasicFlashParamHeader); + + if (!EFI_ERROR (Status)) { + // Read Basic Flash Parameters. Already know it is MajorRev = 1 + Instance->SfdpBasicFlashByteCount = SfdpBasicFlashParamHeader.Length * 4; + LengthInBytes = Instance->SfdpBasicFlashByteCount; + Instance->SfdpBasicFlash = AllocateZeroPool (LengthInBytes); + + if (Instance->SfdpBasicFlash != NULL) { + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + + CurrentBuffer = (UINT8 *)Instance->SfdpBasicFlash; + for (ByteCounter = 0; ByteCounter < LengthInBytes; ByteCounter += MaximumTransferBytes) { + CurrentAddress = SfdpBasicFlashParamHeader.TablePointer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Check not WIP + Status = WaitNotWip (Instance); + + // Read Data + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSFDP, + SPI_FLASH_RDSFDP_DUMMY, + SPI_FLASH_RDSFDP_ADDR_BYTES, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + Length, + CurrentBuffer + ); + ASSERT_EFI_ERROR (Status); + CurrentBuffer += Length; + } else { + break; + } + } + } + } + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..c177fc9ce9935bd35a093c878da6bfcb566b5a9b --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.c @@ -0,0 +1,169 @@ +/***************************************************************************** + * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "EspiNorFlash.h" +#include "EspiNorFlashInstance.h" + +/** + Entry point of the Macronix SPI NOR Flash driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_DEVICE_ERROR Fail to install EFI_ESPI_SMM_NOR_FLASH_PROTOCOL. +**/ +EFI_STATUS +EFIAPI +EspiNorFlashEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + ESPI_NOR_FLASH_INSTANCE *Instance; + EFI_SPI_NOR_FLASH_PROTOCOL *Protocol; + ESPI_SL40_SLAVE_FA_CAPCFG FaCapCfg; + ESPIx68_SLAVE0_CONFIG EspiReg68; + + DEBUG ((DEBUG_INFO, "%a - ENTRY\n", __FUNCTION__)); + + if (PcdGet8 (PcdAmdPspRomArmorSelection) >= 2) { + // If RomArmor2 or 3 is enabled, skip + DEBUG ((DEBUG_INFO, "PcdAmdPspRomArmorSelection >= 2")); + return EFI_UNSUPPORTED; + } + + // Allocate the Board SPI Configuration Instance + Instance = AllocateZeroPool (sizeof (ESPI_NOR_FLASH_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->Signature = ESPI_NOR_FLASH_SIGNATURE; + + // Locate the SPI IO Protocol + Status = gSmst->SmmLocateProtocol ( + &gEdk2EspiSmmDriverProtocolGuid, + NULL, + (VOID **)&Instance->SpiIo + ); + + if (EFI_ERROR (Status) || + ((Instance->SpiIo->Attributes & (SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS | + SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE)) != 0)) + { + FreePool (Instance); + Status = EFI_UNSUPPORTED; + } else { + // Allocate write buffer for SPI IO transactions with extra room for Opcode + // and Address + Instance->SpiTransactionWriteBuffer = AllocatePool ( + Instance->SpiIo->MaximumTransferBytes + 10 // Add extra room + ); + Protocol = &Instance->Protocol; + Protocol->SpiPeripheral = Instance->SpiIo->SpiPeripheral; + Protocol->GetFlashid = GetFlashId; + Protocol->ReadData = ReadData; + Protocol->LfReadData = LfReadData; + Protocol->ReadStatus = ReadStatus; + Protocol->WriteStatus = WriteStatus; + Protocol->WriteData = WriteData; + Protocol->Erase = Erase; + Protocol->EraseBlockBytes = SIZE_4KB; + + if (IsEspiSafsMode (&(Instance->EspiBaseAddress))) { + // ESPI SAFS + Instance->EspiSafsMode = TRUE; + Protocol->FlashSize = PcdGet32 (PcdFlashAreaSize); + Instance->EspiEraseBlockMap = FchEspiCmd_GetConfiguration (Instance->EspiBaseAddress, SLAVE_FA_CAPCFG2); + FaCapCfg.Value = FchEspiCmd_GetConfiguration (Instance->EspiBaseAddress, SLAVE_FA_CAPCFG); + + if (FaCapCfg.Field.ChMaxReadReqSize != 0) { + Instance->EspiMaxReadReqSize = 64 << (FaCapCfg.Field.ChMaxReadReqSize - 1); + } else { + Instance->EspiMaxReadReqSize = 64; // Set 64 bytes as default + } + + EspiReg68.Value = FchEspiCmd_GetConfiguration (Instance->EspiBaseAddress, ESPI_SLAVE0_CONFIG); + if (EspiReg68.Field.FlashMaxPayloadSize == 0x01) { + Instance->EspiMaxPayloadSize = 64; + } else if (EspiReg68.Field.FlashMaxPayloadSize == 0x02) { + Instance->EspiMaxPayloadSize = 128; + } else if (EspiReg68.Field.FlashMaxPayloadSize == 0x03) { + Instance->EspiMaxPayloadSize = 256; + } else { + Instance->EspiMaxPayloadSize = 64; // Set 64 bytes as default + } + + DEBUG ((DEBUG_INFO, "ESPI SAFS mode, EspiBaseAddress = 0x%x\n", Instance->EspiBaseAddress)); + DEBUG ((DEBUG_INFO, " EspiEraseBlockMap = 0x%x\n", Instance->EspiEraseBlockMap)); + DEBUG ((DEBUG_INFO, " EspiMaxReadReqSize = 0x%x\n", Instance->EspiMaxReadReqSize)); + DEBUG ((DEBUG_INFO, " EspiMaxPayloadSize = 0x%x\n", Instance->EspiMaxPayloadSize)); + } else { + // SPI MAFS + Instance->EspiSafsMode = FALSE; + Status = Protocol->GetFlashid ( + Protocol, + (UINT8 *)&Protocol->Deviceid + ); + ASSERT_EFI_ERROR (Status); + DEBUG (( + DEBUG_INFO, + "%a: Flash ID: Manufacturer=0x%02X, Device=0x%02X%02X\n", + __FUNCTION__, + Protocol->Deviceid[0], + Protocol->Deviceid[1], + Protocol->Deviceid[2] + )); + + Status = ReadSfdpBasicParameterTable (Instance); + ASSERT_EFI_ERROR (Status); + + // SFDP DWORD 2 + Protocol->FlashSize = (Instance->SfdpBasicFlash->Density + 1) / 8; + DEBUG ((DEBUG_INFO, "%a: Flash Size=0x%X\n", __FUNCTION__, Protocol->FlashSize)); + + if (Protocol->FlashSize > SIZE_16MB) { + // If flash size is more than 16MB, enable 4byte mode + Instance->SpiTransactionWriteBuffer[0] = 0xb7;// SPI_FLASH_4BYTEMODE; // 4byte mode opcode + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + 1, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + DEBUG ((DEBUG_INFO, "%a: enable 4-Byte mode (OpCode 0xB7) %r\n", __FUNCTION__, Status)); + ASSERT_EFI_ERROR (Status); + } + } + + Status = gSmst->SmmInstallProtocolInterface ( + &Instance->Handle, + &gAmdEspiSmmNorFlashProtocolGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + } + + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __FUNCTION__, Status)); + + return Status; +} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..0082177720eb33b9d87a87771d4c5c9391a6b7bd --- /dev/null +++ b/Platform/AMD/AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf @@ -0,0 +1,58 @@ +#/***************************************************************************** +# * +# * Copyright (C) 2018-2025 Advanced Micro Devices, Inc. All rights reserved. +# * SPDX-License-Identifier: BSD-2-Clause-Patent +# *****************************************************************************/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = EspiNorFlashSmm + FILE_GUID = 83705B89-CBF9-44f8-8546-E0124C682D08 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = EspiNorFlashEntry + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaModuleFchPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + SmmServicesTableLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + TimerLib + DebugLib + IoLib + PciLib + FchEspiCmdLib + BaseMemoryLib + MemoryAllocationLib +[Sources] + EspiNorFlashSmm.c + EspiNorFlash.c + EspiNorFlashSfdp.c + EspiNorFlashInstance.h + EspiNorFlash.h + +[Protocols] + gAmdEspiSmmNorFlashProtocolGuid ## PRODUCES + gEdk2EspiSmmDriverProtocolGuid ## CONSUMES + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationRetryCount + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + gAmdPlatformPkgTokenSpaceGuid.PcdAmdEspiOffset + +[Pcd] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspRomArmorSelection ## CONSUMES + +[Depex] + gEdk2EspiSmmDriverProtocolGuid \ No newline at end of file diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.c deleted file mode 100644 index 329a24a0e585ae65667cd539ec9b7118f494ed31..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbDxe.c +++ /dev/null @@ -1,95 +0,0 @@ -/** @file - - FV block I/O protocol driver for SPI flash libary. - - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#define BLOCK_SIZE (FixedPcdGet32 (PcdFlashNvStorageBlockSize)) - -extern EFI_SPI_NOR_FLASH_PROTOCOL *mSpiNorFlashProtocol; -extern EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mSpiFvbProtocol; - -extern EFI_PHYSICAL_ADDRESS mNvStorageBase; -extern EFI_LBA mNvStorageLbaOffset; -UINT32 mSpiFlashOffset; - -STATIC EFI_HANDLE mSpiFvbHandle; -extern UINT32 -SetSpiFlashOffset ( - UINT32 FlashSize - ); - -/** - SPI firmware volume driver EntryPoint. - - @param[in] ImageHandle Driver Image Handle - @param[in] SystemTable System Table - - @retval EFI_SUCCESS Driver initialization succeeded - @retval all others Driver initialization failed - -**/ -EFI_STATUS -EFIAPI -SpiFvbDxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "%a - ENTRY\n", __func__)); - - // Retrieve SPI NOR flash driver - Status = gBS->LocateProtocol ( - &gEfiSpiNorFlashProtocolGuid, - NULL, - (VOID **)&mSpiNorFlashProtocol - ); - - if (EFI_ERROR (Status)) { - return Status; - } - - mNvStorageBase = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashNvStorageVariableBase); - DEBUG (( - DEBUG_INFO, - "%a - mNvStorageBase = %X\n", - __func__, - mNvStorageBase - )); - mNvStorageLbaOffset = (EFI_LBA)((PcdGet32 (PcdFlashNvStorageVariableBase) - - FixedPcdGet32 (PcdFlashAreaBaseAddress)) - / FixedPcdGet32 (PcdFlashNvStorageBlockSize)); - DEBUG (( - DEBUG_INFO, - "%a - mNvStorageLbaOffset = %X\n", - __func__, - mNvStorageLbaOffset - )); - - mSpiFvbHandle = NULL; - Status = gBS->InstallProtocolInterface ( - &mSpiFvbHandle, - &gEfiFirmwareVolumeBlockProtocolGuid, - EFI_NATIVE_INTERFACE, - &mSpiFvbProtocol - ); - mSpiFlashOffset = SetSpiFlashOffset (mSpiNorFlashProtocol->FlashSize); - - DEBUG ((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __func__, Status)); - return Status; -} diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbExtra.uni b/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbExtra.uni deleted file mode 100644 index 1f7c471f4360f3b30f185f1380f1e8c990381a04..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbExtra.uni +++ /dev/null @@ -1,9 +0,0 @@ -// /** @file -// -// Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// **/ - -#string STR_PROPERTIES_MODULE_NAME -#language en-US "AMD SPI Firmware Volume Block Driver" diff --git a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.c b/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.c deleted file mode 100644 index 16b8f345216a14a5bb91704bc883d8a7373265bb..0000000000000000000000000000000000000000 --- a/Platform/AMD/AmdPlatformPkg/Universal/Spi/SpiFvb/SpiFvbSmm.c +++ /dev/null @@ -1,130 +0,0 @@ -/** @file - - FV block I/O protocol driver for SPI flash libary. - - Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#define BLOCK_SIZE (FixedPcdGet32 (PcdFlashNvStorageBlockSize)) - -extern EFI_SPI_NOR_FLASH_PROTOCOL *mSpiNorFlashProtocol; -extern EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mSpiFvbProtocol; -extern EFI_PHYSICAL_ADDRESS mNvStorageBase; -extern EFI_LBA mNvStorageLbaOffset; - -STATIC EFI_HANDLE mSpiFvbHandle; -UINT32 mSpiFlashOffset; - -extern UINT32 -SetSpiFlashOffset ( - UINT32 FlashSize - ); - -extern UINT32 -SetEspiFlashOffset ( - UINT32 FlashSize - ); - -/** - Check if SAFS mode is enabled - - @retval TRUE SAFS mode is enabled. - @retval FALSE MAFS mode is enabled - -**/ -BOOLEAN -EFIAPI -IsEspiSafsMode ( - VOID - ) -{ - UINT32 MISC80; - - MISC80 = MmioRead32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80); - if ((MISC80 & BIT3)) { - // romtype [5:4] 10: eSPI with SAFS support - return TRUE; - } - - return FALSE; -} - -/** - SPI firmware volume SMM driver EntryPoint. - - @param[in] ImageHandle Driver Image Handle - @param[in] MmSystemTable MM System Table - - @retval EFI_SUCCESS Driver initialization succeeded - @retval all others Driver initialization failed - -**/ -EFI_STATUS -EFIAPI -SpiFvbSmmEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - UINT32 (*SetFlashOffset)( - UINT32 - ); - DEBUG ((DEBUG_INFO, "%a - ENTRY\n", __func__)); - - if (IsEspiSafsMode ()) { - DEBUG ((DEBUG_INFO, "Espi SAFS boot mode detected!\n")); - Status = gSmst->SmmLocateProtocol ( - &gAmdEspiSmmNorFlashProtocolGuid, - NULL, - (VOID **)&mSpiNorFlashProtocol - ); - SetFlashOffset = &SetEspiFlashOffset; - } else { - DEBUG ((DEBUG_INFO, "Default (SPIROM) boot mode detected!\n")); - // Retrieve SPI NOR flash driver - Status = gSmst->SmmLocateProtocol ( - &gEfiSpiSmmNorFlashProtocolGuid, - NULL, - (VOID **)&mSpiNorFlashProtocol - ); - SetFlashOffset = &SetSpiFlashOffset; - } - - if (EFI_ERROR (Status)) { - return Status; - } - - mNvStorageBase = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashNvStorageVariableBase); - DEBUG ((DEBUG_INFO, "%a - mNvStorageBase = %X\n", __func__, mNvStorageBase)); - mNvStorageLbaOffset = (EFI_LBA)((PcdGet32 (PcdFlashNvStorageVariableBase) - - FixedPcdGet32 (PcdFlashAreaBaseAddress)) - / FixedPcdGet32 (PcdFlashNvStorageBlockSize)); - DEBUG ((DEBUG_INFO, "%a - mNvStorageLbaOffset = 0x%X\n", __func__, mNvStorageLbaOffset)); - - mSpiFvbHandle = NULL; - Status = gSmst->SmmInstallProtocolInterface ( - &mSpiFvbHandle, - &gEfiSmmFirmwareVolumeBlockProtocolGuid, - EFI_NATIVE_INTERFACE, - &mSpiFvbProtocol - ); - mSpiFlashOffset = (*SetFlashOffset)(mSpiNorFlashProtocol->FlashSize); - - DEBUG ((DEBUG_INFO, "%a - EXIT (Status = %r)\n", __func__, Status)); - return Status; -} diff --git a/Platform/AMD/GenoaBoard/Apcb/ApcbToken.h b/Platform/AMD/GenoaBoard/Apcb/ApcbToken.h new file mode 100644 index 0000000000000000000000000000000000000000..b2749e36ef953cacdba354ca1e2faf4068b7d011 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Apcb/ApcbToken.h @@ -0,0 +1,25 @@ +//***************************************************************************** +// +// Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//***************************************************************************** + +// Add override tokens here + +#ifdef ESPI_UART +#ifdef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE + #undef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE +#endif +#define APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE 0 + +#ifdef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE + #undef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE +#endif +#define APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE 0 +#endif /// end of ESPI_UART + +#ifdef PCIE_MULTI_SEGMENT + #define APCB_TOKEN_UID_DF_PCI_MMIO_BASE_VALUE 0x0 + #define APCB_TOKEN_UID_DF_PCI_MMIO_HI_BASE_VALUE 0x3FFB +#endif /// end of PCIE_MULTI_SEGMENT \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/Binaries/EarlyVgaProg.bin b/Platform/AMD/GenoaBoard/Binaries/EarlyVgaProg.bin new file mode 100644 index 0000000000000000000000000000000000000000..27535ee85aa0820783137771e2e7f7726ce378e7 Binary files /dev/null and b/Platform/AMD/GenoaBoard/Binaries/EarlyVgaProg.bin differ diff --git a/Platform/AMD/GenoaBoard/Binaries/earlyVgaProgOnly.bin b/Platform/AMD/GenoaBoard/Binaries/earlyVgaProgOnly.bin new file mode 100644 index 0000000000000000000000000000000000000000..fbf4b4ef76ca7580f967a9d373f6e42e196ee26b Binary files /dev/null and b/Platform/AMD/GenoaBoard/Binaries/earlyVgaProgOnly.bin differ diff --git a/Platform/AMD/GenoaBoard/Binaries/epyc2_image.bin b/Platform/AMD/GenoaBoard/Binaries/epyc2_image.bin new file mode 100644 index 0000000000000000000000000000000000000000..20c20491e3cb8b824310f023e2b9f2d8ddf5c5f1 Binary files /dev/null and b/Platform/AMD/GenoaBoard/Binaries/epyc2_image.bin differ diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..946eb983a6a674a681aefbc3d8011e0f2b53786a --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf + !endif \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..aaf598d5ec7e510ff8a4f9c5b35dc94c34d50c16 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# CRB specific - External AGESA build. +# +## + # + # AMD AGESA Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.inc.dsc + !endif diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..1c410d4c93bbb2061c8446d7be5eaecba022c254 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf + !endif diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..1b35faccba0e6824567727af8459803ec1110867 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf @@ -0,0 +1,15 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.dxe.inc.fdf diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..d1b1fd9a09abaa1622c546fe355560a7a6cc27dc --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# CRB specific - Internal AGESA build. +# +## + # + # AMD AGESA Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !include AgesaModulePkg/AgesaIdsIntRs.inc.dsc + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.inc.dsc diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..959d51899b06aa9ca4c481bcdd2742019526996e --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf @@ -0,0 +1,15 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.pei.inc.fdf diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..acececcf56c4c38bc09ae5053b8c42bdff6d287b --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"Default String" + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|{0} + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("B588BA40-ADBD-4D68-A4B1-B850515E0B20")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"Default String" + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"Default String" + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"Default String" + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"Default String"} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"Default String"} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000000000000000000000000000000000..f35642da541a4452c4044ba4ac4626dea04c3325 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,159 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# GenoaCinnabar reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +############################################################################## +# +# BIOS image layout +# +############################################################################## +# +===============================+ +# |Flash Device (FD) | +# |BaseAddress = 0xFF000000 | +# | ONLY 0xFF000000-0xFFFFFFFF | +# | Visible in MMIO < 4GB | +# |Size = 0x02000000 (32MB)| +# +===============================+ + DEFINE ROM2_FLASH_BASE = 0xFF000000 + DEFINE ROM2_FLASH_SIZE = 0x01000000 + DEFINE ROM3_FLASH_BASE = 0xFD02000000 + DEFINE ROM3_FLASH_SIZE = 0x02000000 + DEFINE SPI_BLOCK_SIZE = 0x1000 + DEFINE SPI_NUM_BLOCKS = 0x2000 + DEFINE ROM3_FLASH_ENABLE = TRUE +# +===============================+ +# Section FD Offset SPI Addr. RAM Addr +# +===============================+ 0x00000000 0xFF000000 +# |Unused Size=0x20000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0001FFFF 0xFF01FFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00020000 0xFF020000 +# |Embedded FW Sig Size=0x1000 | + DEFINE FV_FW_SIG_OFFSET = 0x00020000 + DEFINE FV_FW_SIG_SIZE = 0x00001000 +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00020FFF 0xFF020FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00021000 0xFF021000 +# |Unused Size=0x16000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00036FFF 0xFF036FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00037000 0xFF037000 +# |UEFI NVRAM Size=0x20000| + DEFINE NVRAM_AREA_VAR_OFFSET = 0x00037000 + DEFINE NVRAM_AREA_VAR_SIZE = 0x0000E000 + DEFINE NVRAM_AREA_SIZE = 0x00020000 + + DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE) + DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE) + + DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE) +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00056FFF 0xFF056FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00057000 0xFF057000 +# |Unused Size=0xb000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00061FFF 0xFF061FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00062000 0xFF062000 +# |PSP Dir1 Size=0x200000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x002C5FFF 0xFF2C5FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x002C6000 0xFF2C6000 +# |BIOS Dir1 Size=0x40000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00306FFF 0xFF306FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00307000 0xFF307000 +# |PSP Dir2 Size=0x234000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0053AFFF 0xFF53AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0053B000 0xFF53B000 +# |BIOS Dir2 Size=0x100000 | +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0063AFFF 0xFF63AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0063B000 0xFF63B000 +# |FV.FvAdvanced Size=0x90000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x006CAFFF 0xFF6CAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x006CB000 0xFF6CB000 +# |FV.FvAdvancedSecurity 0x40000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0070AFFF 0xFF70AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0070B000 0xFF70B000 +# |FV. FvOsBoot Size=0x100000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0080AFFF 0xFF80AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0080B000 0xFF80B000 +# |FV.FvUefiBoot Size=0x2C0000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00ACAFFF 0xFFACAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00ACB000 0xFFCAB000 +# |FV.FvSecurity Size=0x010000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00ADAFFF 0xFFADAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00ADB000 0xFFADB000 +# |FV.FvPostMemory Size=0x040000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00B1AFFF 0xFFB1AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00B1B000 0xFFB1B000 +# |FV.FvAdvancedPreMemory 0x1E5000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00CFFFFF 0xFFCFFFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00D00000 0xFFD00000 0x76D00000 +# |FV.FvPreMemory Size=0x300000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00FFFFFF 0xFFFFFFFF 0x76FFFFFF + DEFINE BOOT_FV_BASE = 0x76D00000 +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x01000000 +# |Unused Size=0x00100000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x010FFFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x01100000 +# |Unused Size=0x00F00000| +# +===============================+ 0x01FFFFFF + +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF800000 +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE) + +# FV offset and size assignment +# FvSecurity +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00ACB000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00010000 +# FvPostMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00040000 +# FvAdvancedPreMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x001E5000 +# FvPreMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00300000 + +# FvAdvanced +!if $(ROM3_FLASH_ENABLE) == TRUE + # if ROM3 is enabled then continue the offset update + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize) +!else + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x0063B000 +!endif +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00090000 +# FvAdvancedSecurity +SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) +SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = 0x00040000 +# FvOsBoot +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00100000 +# FvUefiBoot +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x002C0000 + +SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE) + +!if $(ROM3_FLASH_ENABLE) == TRUE + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +!endif diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..6c9e5fa2ce62eddb1428acd885b7157b41705edf --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Project.dsc @@ -0,0 +1,175 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Cinnabar +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 12DE9B28-76BE-454C-A337-297ECCB359B7 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "CINNABAR" + + DEFINE SATA_OVERRIDE = FALSE + +!ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE +!else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE +!endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + + # Add platform includes AGESA, CPM etc + !include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + + # Board specific SMBIOS defines + !include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs + !include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x454E4F54534E5553 # "CINNABAR" + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|96 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|192 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|1 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|1 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..9f53c017bc1c6f08aa01fc0756c591f4130cb115 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/Project.fdf @@ -0,0 +1,37 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/PspDataRs.xml b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/PspDataRs.xml new file mode 100644 index 0000000000000000000000000000000000000000..58cde3c4e20175cb7e9968adced02bed81dbadb6 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/PspDataRs.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/PspDataRs_unencrypted.xml b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/PspDataRs_unencrypted.xml new file mode 100644 index 0000000000000000000000000000000000000000..f0777198330ccd2d029929522bb2b97222b24443 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/PspDataRs_unencrypted.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..c8b3a9b560883ea554252a3f567a00b469f269b2 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,146 @@ +{ + "rs6bi": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6bi_simnow": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "INTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6be": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6be_simnow": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "EXTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6bis": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6bis_simnow": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "INTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6bes": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6bes_simnow": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "EXTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6be_nocbs": { + "platform": "CinnabarBoardPkg", + "sku": "6B", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Cinnabar", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..cc861d8ae79e7177d7fae6df342f7a7090ac2aac --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..084d4c1c2318fdca98ba15b4074a6eb22fa147af --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP6") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Cinnabar' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..b9755ad915067be51b60d9bb7cbc2a9f4999dcf5 --- /dev/null +++ b/Platform/AMD/GenoaBoard/CinnabarBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP6") diff --git a/Platform/AMD/GenoaBoard/GenoaOpenBoardPkg.dec b/Platform/AMD/GenoaBoard/GenoaOpenBoardPkg.dec new file mode 100644 index 0000000000000000000000000000000000000000..0daa769c07993f0dcf1cfabb2774fc1b5f58f646 --- /dev/null +++ b/Platform/AMD/GenoaBoard/GenoaOpenBoardPkg.dec @@ -0,0 +1,25 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +[Defines] + DEC_SPECIFICATION = 1.27 + PACKAGE_NAME = GenoaOpenBoardPkg + PACKAGE_GUID = C444E72E-1F8E-428C-AB47-AAB943A74813 + PACKAGE_VERSION = 1.0 + +[Includes] + +[Guids] + gGenoaOpenBoardPkgTokenSpaceGuid = { 0x11212FC3, 0xA0ED, 0x4A97, { 0xA0, 0xC7, 0x0D, 0x2C, 0x20, 0x9F, 0x92, 0x40 }} + +[Ppis] + +[PcdsFixedAtBuild] + # + # Console + # + gGenoaOpenBoardPkgTokenSpaceGuid.PcdFchUartPort|0|UINT8|0x40000000 diff --git a/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..76dc230a4f601dc3ced910d1c464eea12f2378be --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf @@ -0,0 +1,18 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf + !endif diff --git a/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.inc.dsc b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..7402fe15ab8974ba697e62780811b8520d148721 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.inc.dsc @@ -0,0 +1,18 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA build. +# +## + # + # AMD AGESA Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.inc.dsc + !endif diff --git a/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..a395f127c4257989be0dbe6ecb1da693a51648ee --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf @@ -0,0 +1,18 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf + !endif diff --git a/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..c5b6fb64f84089adc9e3be31d460d42ec90ad507 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.dxe.inc.fdf diff --git a/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.inc.dsc b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..3ce6f9b378225035c922bda8f9f6b8aa94aea2b0 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.inc.dsc @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA build. +# +## + # + # AMD AGESA Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !include AgesaModulePkg/AgesaIdsIntRs.inc.dsc + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.inc.dsc diff --git a/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..bec17f4c218e2bff191d590eee63efa013f1741d --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.pei.inc.fdf diff --git a/Platform/AMD/GenoaBoard/Include/Dsc/Platform.inc.dsc b/Platform/AMD/GenoaBoard/Include/Dsc/Platform.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..d5385427813ed6abe6fdbe4c69c51ccf26b9bd51 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Dsc/Platform.inc.dsc @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + +# CPM patch +!include AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR)$(PLATFORM_CRB)Pkg.inc.dsc + +# AMD AGESA Include Path +!ifdef $(INTERNAL_IDS) + !include $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.inc.dsc +!else + !include $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.inc.dsc +!endif diff --git a/Platform/AMD/GenoaBoard/Include/Dsc/PlatformCommonPcd.dsc.inc b/Platform/AMD/GenoaBoard/Include/Dsc/PlatformCommonPcd.dsc.inc new file mode 100644 index 0000000000000000000000000000000000000000..cc8d5fff9b58bd3cc096fff3d1a828bfaaf70b60 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Dsc/PlatformCommonPcd.dsc.inc @@ -0,0 +1,738 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#;***************************************************************************** + +[Defines] +!ifndef SECURE_BOOT_ENABLE + DEFINE SECURE_BOOT_ENABLE = TRUE +!endif +!ifndef PLATFORM_SECURE + DEFINE PLATFORM_SECURE = FALSE +!endif + DEFINE NETWORK_IP6_ENABLE = FALSE + + # + # Redfish support + # + DEFINE REDFISH_ENABLE = FALSE + + # + # Set Platform Redfish configuration + # +!if $(REDFISH_ENABLE) == TRUE + + # Enable BMC USB NIC as the Redfish transport interface + DEFINE USB_NETWORK_SUPPORT = TRUE + + # Allow HTTP connection for Redfish + DEFINE NETWORK_SNP_ENABLE = TRUE + DEFINE NETWORK_IP6_ENABLE = TRUE + DEFINE NETWORK_IP4_ENABLE = TRUE + DEFINE NETWORK_HTTP_ENABLE = TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE +!endif + +[Packages] + AmdCpmPkg/AmdCpmPkg.dec + AmdMinBoardPkg/AmdMinBoardPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + ManageabilityPkg/ManageabilityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + Network/NetworkFeaturePkg/NetworkFeaturePkg.dec + PcAtChipsetPkg/PcAtChipsetPkg.dec + SecurityPkg/SecurityPkg.dec + SpcrFeaturePkg/SpcrFeaturePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +# MinPlatformPkg includes +!include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc + +[PcdsFixedAtBuild] + # + # Key Boot Stage + # + # Please select the Boot Stage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchI2c2Irq|0x0C + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchI2c3Irq|0x0D + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiBertTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiHestTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiEinjTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + + # Set ROM Armor Selection + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspRomArmorSelection|1 + + # + # Set EFI Shell file description + # + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc|L"Internal UEFI Shell 2.2" + + # + # BSP Broadcast Method for the first-time wakeup of APs + # + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE + +[PcdsFeatureFlag] + # + # MinPlatformPkg Configuration + # + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|$(SECURE_BOOT_ENABLE) + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + !endif + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable|TRUE + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable|TRUE + !endif + +# Below include file should be here +# after PcdBootStage is set. +# and after respective features are enabled/disabled depends on PcdBootStage +!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + + # + # Below are Manageability feature knobs. + # + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiBmcAcpi|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiBmcElog|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiFrb|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiFru|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiOsWdt|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiSolStatus|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeMctpEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxePldmEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxePldmSmbiosTransferEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityPeiIpmiEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityPeiIpmiFrb|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilitySmmIpmiEnable|FALSE + # Enable IPMI feature for boot stage >=5 and only for real SoC + !if (gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5) && ($(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE) + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiEnable|TRUE + !endif + + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + !endif + + # MdeModulePkg + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Uefi Cpu Package + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|FALSE + + # ACPI + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + # Enable ROM Armor + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable|TRUE + +[PcdsFixedAtBuild.IA32] + # + # Temporary DRAM space for SEC->PEI transition (256KB) + # AMD_ENABLE_UEFI_STACK (Flat32.asm) divides: 1/2 Heap + 1/2 Stack + # + gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamBase|0x00100000 + gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamSize|0x00100000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x80000 + +[PcdsFixedAtBuild] + # Console/Uart settings + !if $(SERIAL_PORT) == "FCH_MMIO" + # MMIO based flow control UART0, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|0 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFEDC9000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|48000000 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0001 + !endif + + !if $(SERIAL_PORT) == "FCH_IO" + # Legacy based flow control UART0, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|0 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0100 + !endif + + !if $(SERIAL_PORT) == "BMC_SOL" + # MMIO based non-flow control UART1, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|1 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFEDCA000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|48000000 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|0xE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0002 + !endif + + !if $(SERIAL_PORT) == "BMC_SOL_IO" + # Legacy based non-flow control UART1, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|1 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|0xE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0200 + !endif + + !if $(SERIAL_PORT) == "BMC_ESPI" + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0000 + !endif + + # Indicates the receive FIFO depth of UART controller. + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|64 + + # Default Value of PlatformLangCodes Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + + ## The mask is used to control ReportStatusCodeLib behavior. + # BIT0 - Enable Progress Code. + # BIT1 - Enable Error Code. + # BIT2 - Enable Debug Code. + !ifdef $(INTERNAL_IDS) + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + !else + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x00 + !endif + + # + # Debug Masks + # + # // + # // Declare bits for PcdDebugPropertyMask + # // + # DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PROPERTY_DEBUG_PRINT_ENABLED 0x02 + # DEBUG_PROPERTY_DEBUG_CODE_ENABLED 0x04 + # DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED 0x08 + # DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED 0x10 + # DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED 0x20 + # // + # // Declare bits for PcdFixedDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint() + # // + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload message of manageability + # // related modules, such Redfish, IPMI, MCTP and etc. + # DEBUG_ERROR 0x80000000 // Error + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + !if $(DEBUG_DISPATCH_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x808000CF + !else + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x8080004F + !endif + + # + # AGESA Debug + # + !if ($(IDS_DEBUG_ENABLE) == TRUE) AND ($(SERIAL_PORT) != "NONE") + # IdsDebugPrint Filter. Refer to Library/IdsLib.h for details. + # 0x100401008A30042C (GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC | CPU_TRACE | MEM_FLOW | + # MEM_STATUS | MEM_PMU | FCH_TRACE | MAIN_FLOW | TEST_POINT | PSP_TRACE) + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintFilter|0x1004010300300400 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortDetectCableConnection|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPort|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + !else + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEnable|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortEnable|FALSE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80 + !else + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00 + !endif + + # + # Specifies the initial value for Register_D in RTC. + # Reason for change: + # PcRtc.c wants to see register D bit 7 (VRT) high almost immediately after writing the below value, + # which clears it with the default UEFI value of zero. The AMD FCH updates this bit only once per 4-1020ms (1020ms default). + # This causes function RtcWaitToUpdate to return an error. Preset VRT to 1 to avoid this. + # + gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x80 + + # + # SMBIOS + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosT16MaximumCapacity|0x80000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + + # + # PCIe Config-space MMIO (1MB per bus, 256MB) + # + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE + !endif + + !if $(PCIE_MULTI_SEGMENT) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x3FFB00000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow|0x0 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi|0x3FFB + !else + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow|0xE0000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi|0x0 + !endif + + # + # Boot + # + # PCDs to set the default size of the different UEFI memory types to promote + # contiguous UEFI memory allocation. These values are used by + # AmdCommon/Pei/PlatformInitPei/MemoryInitPei.c to reserve + # default chunks for each memory type when gEfiMemoryTypeInformationGuid + # variable is not set. These values can be updated to prevent reboot because + # MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c: + # BmSetMemoryTypeInformationVariable() sets gEfiMemoryTypeInformationGuid at + # the end of post to reserve more memory. Serial output from this code will + # display sizes required, which can then be updated in these PCDs. + # Memory Type 09 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize | 0x400 + # Memory Type 0A + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize | 0x400 + # Memory Type 00 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize | 0x5000 + # Memory Type 06 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize | 0x800 + # Memory Type 05 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize | 0x100 + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 + !if $(EMULATION) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + !endif + # 462CAA21-7614-4503-836E-8AB6F4662331 (UiApp FILE_GUID) + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ GUID("462CAA21-7614-4503-836E-8AB6F4662331") } + + # 1GB page support + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + + # + # ACPI + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemEnableAcpiSwSmi|0xA0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemDisableAcpiSwSmi|0xA1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"AMD " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20444D41 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x00000001 + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|4 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x0002052D + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdAcpiCpuSsdtProcessorScopeInSb|TRUE + + # NOTE, below PCD should match with gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgFchIoapicId + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x80 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|4 + # NOTE, below PCD should match with gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0xF1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemEnableAcpiSwSmi + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemDisableAcpiSwSmi + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + !endif + + # Max Cpu constraints + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + + # + # EFI NV Storage + # + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0xA000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0xA000 + + # + # AGESA NBIO + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIommuMMIOAddressReservedEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicMMIOAddressReservedEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdPreDefineEn|TRUE #### Makes PEI assign IOAPIC IDs + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase|0xF1 + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCompliantEdkIIAcpiSdtProtocol|TRUE + + # AGESA FCH + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1EvtBlkAddr|0x800 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1CntBlkAddr|0x804 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr|0x808 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgCpuControlBlkAddr|0x810 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiGpe0BlkAddr|0x820 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemBeforePciRestoreSwSmi|0x00 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemAfterPciRestoreSwSmi|0x00 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemSpiUnlockSwSmi|0xB7 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemSpiLockSwSmi|0xB8 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemCfgMaxPostPackageRepairEntries|0x3F + + # Disable S3 support + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE + + ## Toggle for whether the VariablePolicy engine should allow disabling. + # The engine is enabled at power-on, but the interface allows the platform to + # disable enforcement for servicing flexibility. If this PCD is disabled, it will block the ability to + # disable the enforcement and VariablePolicy enforcement will always be ON. + # TRUE - VariablePolicy can be disabled by request through the interface (until interface is locked) + # FALSE - VariablePolicy interface will not accept requests to disable and is ALWAYS ON + # @Prompt Allow VariablePolicy enforcement to be disabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdAllowVariablePolicyEnforcementDisable|TRUE + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE + + # TRUE - 5-Level Paging will be enabled. + # FALSE - 5-Level Paging will not be enabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable|FALSE + + # Specifies stack size in bytes for each processor in SMM. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x10000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdAcpiTableHeaderOemId|gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + !if $(EMULATION) == TRUE + # enable IDS prints for emulation to port80 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEmulationAutoDetect|$(IDS_DEBUG_ENABLE) + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdPspRecoveryFlagDetectEnable|FALSE + !endif + + # Secureboot + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE + !endif + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiGpe0BlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1CntBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1EvtBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockLength|0x8 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aEvtBlkAccessSize|0x2 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aCntBlkAccessSize|0x2 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize|0x03 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize|0x1 + + # + # The base address of temporary page table for accessing PCIE MMIO base address above 4G in PEI phase. + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPeiTempPageTableBaseAddress|0x60000000 + !if $(DRAM_BOOT) == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdShellFile|{GUID(68198A68-D249-4826-BC5E-45DF0CCA2A53)} + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc|L"Emulation Linux Loader" + !endif + + # To create MPDMA devices under RB named as PCIx + gAmdCpmPkgTokenSpaceGuid.UsePciXAslName|TRUE + + # + # edk2 Redfish foundation + # + !if $(REDFISH_ENABLE) == TRUE + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePathMatchMode|DEVICE_PATH_MATCH_MAC_NODE + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePathNum|1 + # + # Below is the MAC address of network adapter on EDK2 Emulator platform. + # You can use ifconfig under EFI shell to get the MAC address of network adapter on EDK2 Emulator platform. + # + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePath|{DEVICE_PATH("MAC(005056c00009,0x1)")} + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceAccessModeInBand|True + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishDiscoverAccessModeInBand|True + !endif + + # + # USB Network (Communication Device Class) drivers + # + !if $(USB_NETWORK_SUPPORT) == TRUE + # Set USB NIC Rate Limiting + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableUsbNetworkRateLimiting|TRUE + !endif + +[PcdsDynamicDefault.common] + # + # Set MMIO Above4GB at the 1TB boundary + # + !if $(PCIE_MULTI_SEGMENT) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMmioAbove4GLimit|0x3FFBFFFFFFFF + !else + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMmioAbove4GLimit|0x7FBFFFFFFFF + !endif + + # IO Resource padding in bytes, default 4KB, override to 0. + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIo|0x00 + + # + # Flash NV Storage + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0 + + # + # AGESA FCH + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdHpetEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdHpetMsiDis|FALSE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdNoneSioKbcSupport|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgFchIoapicId|gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + + # Tell AGESA how you want the UART configured for serial output + # FchRTDeviceEnableMap + # < BIT4 - LPC : PcdLpcEnable + # < BIT5 - I2C0 : FchRTDeviceEnableMap[BIT5] + # < BIT6 - I2C1 : FchRTDeviceEnableMap[BIT6] + # < BIT7 - I2C2 : FchRTDeviceEnableMap[BIT7] + # < BIT8 - I2C3 : FchRTDeviceEnableMap[BIT8] + # < BIT9 - I2C4 : FchRTDeviceEnableMap[BIT9] + # < BIT10 - I2C5 : FchRTDeviceEnableMap[BIT10] + # < BIT11 - UART0 : FchRTDeviceEnableMap[BIT11] + # < BIT12 - UART1 : FchRTDeviceEnableMap[BIT12] + # < BIT16 - UART2 : FchRTDeviceEnableMap[BIT13] + # < BIT18 - SD : PcdEmmcEnable and PcdEmmcType < 5 + # < BIT26 - UART3 : FchRTDeviceEnableMap[BIT26] + # < BIT27 - eSPI : PcdEspiEnable - read-only. + # < BIT28 - eMMC : PcdEmmcEnable - read-only. + gEfiAmdAgesaModulePkgTokenSpaceGuid.FchRTDeviceEnableMap|0x00001F60 + # FchUartLegacyEnable + # 0-disable, 1- 0x2E8/2EF, 2 - 0x2F8/2FF, 3 - 0x3E8/3EF, 4 - 0x3F8/3FF + !if $(SERIAL_PORT) == "FCH_IO" + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart0LegacyEnable|0x04 + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart1LegacyEnable|0x03 + !elseif $(SERIAL_PORT) == "BMC_SOL_IO" + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart0LegacyEnable|0x03 + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart1LegacyEnable|0x04 + !endif + + # + # AGESA APCB Recovery + # + # TO-DO: Temporarily disable Apcb Recovery, to suppress debug ASSERT. + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspApcbRecoveryEnable|FALSE + !endif + + # + # AGESA NBIO + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgGnbIoapicId|gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase + + # + # AGESA BMC (NBIO) + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkTraining|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkSocket|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkDie|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + + # + # AGESA USB + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + + !if $(USB_SUPPORT) + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|TRUE + ### USB 3.0 controller1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci1Enable|TRUE + ### USB3.0 controller0 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci2Enable|FALSE + ### USB3.0 controller1 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci3Enable|FALSE + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciSsid|0x00000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhciECCDedErrRptEn|FALSE + !else + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|FALSE + ### USB 3.0 controller1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci1Enable|FALSE + ### USB3.0 controller0 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci2Enable|FALSE + ### USB3.0 controller1 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci3Enable|FALSE + !endif + +!if $(SATA_SUPPORT) + ### @brief FCH-SATA enables + ### @details Select whether or not the FCH Sata controller is active. + ### @li TRUE - This option is active. + ### @li FALSE - This option is turned off. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataStaggeredSpinup|TRUE +!else + ### @brief FCH-SATA enables + ### @details Select whether or not the FCH Sata controller is active. + ### @li TRUE - This option is active. + ### @li FALSE - This option is turned off. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable|FALSE +!endif + + # NVDIMM feature + gEfiAmdAgesaPkgTokenSpaceGuid.PcdNvdimmEnable|FALSE + + # + # Firmware Revision + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(FIRMWARE_REVISION_NUM) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VERSION_STR)" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"$(RELEASE_DATE)" + + # MinPlatformPkg, 1's position enables respective ioapic + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0F + +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel + +[PcdsDynamicHii.X64.DEFAULT] + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x8|4|NV,BS + !endif + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCcxCfgPFEHEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLegacyFree|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCxlProtocolErrorReporting|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCxlComponentErrorReporting|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEgressPoisonSeverityLo|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEgressPoisonSeverityHi|0 + + !ifdef $(INTERNAL_IDS) + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdCcxSingleBitErrLogging|TRUE + !endif + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdS3LibTableSize|0x100000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspAntiRollbackLateSplFuse|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdUsbRSOemConfigurationTable|{0x0D,0x10,0xB1,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x01,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x01,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05} + + # Enable/Disable IOMMU (default TRUE) + # gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgIommuSupport|FALSE + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdIvInfoDmaReMap|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCStateIoBaseAddress|0x813 + + # AGESA I2C SDA hold delay + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchI2c0SdaHold|0x35 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchI2c1SdaHold|0x35 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchI2c2SdaHold|0x35 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchI2c3SdaHold|0x35 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchI2c4SdaHold|0x35 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchI2c5SdaHold|0x35 + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdResetMode|0x07 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgSmiCmdPortAddr|0xB2 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdTelemetry_VddcrSocfull_Scale_Current|0x50 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdTelemetry_VddcrVddfull_Scale_Current|0xFF + + !if $(SIMNOW_SUPPORT) == TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdSmuFeatureControlDefines|0x00030000 + !endif + + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemPostPackageRepair|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemBootTimePostPackageRepair|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemRuntimePostPackageRepair|FALSE + !endif + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLpcEnable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{GUID({ 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } })} + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{DEVICE_PATH("VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(E0C14753-F9BE-11D2-9A0C-0090273FC14D),UsbClass(0xFFFF,0xFFFF,0x03,0x01,0x01)")} + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{DEVICE_PATH("VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(E0C14753-F9BE-11D2-9A0C-0090273FC14D),PcieRoot(0xB)/Pci(0x05,0x02)/Pci(0x00,0x00)/Pci(0x00,0x00)/Pci(0x00,0x00)/AcpiAdr(0x80010100)")} + gEfiSecurityPkgTokenSpaceGuid.PcdActiveTpmInterfaceType|0x00 + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x700E0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspSystemTpmConfig|0x00 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000 diff --git a/Platform/AMD/GenoaBoard/Include/Dsc/ProjectCommon.inc.dsc b/Platform/AMD/GenoaBoard/Include/Dsc/ProjectCommon.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..60bb237c70a392909f0850a72612be44c9c3b84e --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Dsc/ProjectCommon.inc.dsc @@ -0,0 +1,538 @@ +#;***************************************************************************** +#; Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +[LibraryClasses] + # AML library + AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf + AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf + + # AMD AGESA + AmdCalloutLib|AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf + AmlGenerationLib|AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf + OemAgesaCcxPlatformLib|AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf + PciHostBridgeLib|AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + ResetSystemLib|AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf + !if $(SIMNOW_SUPPORT) == TRUE + AmdPostCodeLib|AgesaModulePkg/Library/AmdPostCodeEmuLib2/AmdPostCodeEmuLib.inf + !endif + + # EDKII Generic + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf + + # MinPlatformPkg + AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + BoardAcpiTableLib|MinPlatformPkg/Acpi/Library/BoardAcpiTableLibNull/BoardAcpiTableLibNull.inf + PlatformBootManagerLib|MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf + + # AMD Platform + PlatformSecLib|AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf + ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf + FchEspiCmdLib|AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf + + # Manageability + IpmiCommandLib|ManageabilityPkg/Library/IpmiCommandLib/IpmiCommandLib.inf + + # SPCR Device + SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf + + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + + !if $(SOURCE_DEBUG_ENABLE) + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + !else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + !endif + + !if $(SERIAL_PORT) == "NONE" + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + + !if $(SIMNOW_PORT80_DEBUG) == TRUE + SerialPortLib|AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf + !endif + + PlatformHookLib|AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf + +!if $(REDFISH_ENABLE) == TRUE + # + # edk2 Redfish foundation + # + !include RedfishPkg/RedfishLibs.dsc.inc + # + # edk2 Redfish foundation platform libraries + # + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceBmcUsbNicLib/PlatformHostInterfaceBmcUsbNicLib.inf + RedfishPlatformCredentialLib|RedfishPkg/Library/PlatformCredentialLibNull/PlatformCredentialLibNull.inf + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf +!endif + +[LibraryClasses.IA32.SEC] + # AGESA + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf + + # MinPlatformPkg + SetCacheMtrrLib|MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf + +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE] + # AGESA + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf + +[LibraryClasses.common.PEIM] + + # EDKII generic + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf + + # MinPlatformPkg + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf + !endif + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf + + # AMD Platform + SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM, LibraryClasses.common.PEI_CORE] + PciLib|MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf + PciSegmentLib|MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf + +[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf + +[LibraryClasses.Common.DXE_DRIVER] + PlatformSocLib|GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf + # MinPlatformPkg + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf + !endif + + # IPMI Library for invoking IPMI protocol + IpmiLib|MdeModulePkg/Library/DxeIpmiLibIpmiProtocol/DxeIpmiLibIpmiProtocol.inf + +[LibraryClasses.Common.DXE_CORE, LibraryClasses.Common.DXE_DRIVER, LibraryClasses.Common.DXE_SMM_DRIVER] + # MinPlatformPkg + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf + BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf + +[LibraryClasses.Common.DXE_SMM_DRIVER] + # EDKII Generic + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf + !endif + + # AMD Platform + AmdPspFlashAccLib|AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf + PlatformPspRomArmorWhitelistLib|AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf + +[LibraryClasses.Common.SMM_CORE] + # EDKII Generic + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + +[LibraryClasses.Common.DXE_RUNTIME_DRIVER] + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf + + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + +[Components.IA32] + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc + + # AGESA + AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf { + + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + + # AGESA FCH Platform initialization + !if $(EMULATION) == FALSE + TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf + !endif + + # EDKII Generic + # SEC Core + UefiCpuPkg/SecCore/SecCore.inf { + + SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + } + + # PEIM + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + } + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + + # MinPlatformPkg + MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + BoardInitLib|AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf + } + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf + } + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + # AMD Platform + !if $(PREDEFINED_FABRIC_RESOURCES) == TRUE + $(PROCESSOR_PATH)/Universal/DfResourcesPei/DfResourcesPei.inf + !endif + +[Components.X64] + !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc + + # CPM + AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.inf + AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/PspPlatformDriver/PspPlatform.inf + + # MinPlatformPkg + MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { + + BoardInitLib|AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf + } + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf + MinPlatformPkg/Test/TestPointStubDxe/TestPointStubDxe.inf + + # EDKII Generic + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + !if $(SOURCE_DEBUG_ENABLE) + SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf { + + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + } + !endif + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # USB + !if $(USB_SUPPORT) + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + !endif + + # NVME + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(NVME_SUPPORT) == TRUE + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + !endif + + # SATA + !if $(SATA_SUPPORT) + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + !endif + + # SMM + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + !if $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf + !endif + + # + # Disable DEBUG_CACHE because SMI entry/exit may change MTRRs + # + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x801000C7 + } + + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf { + + # AMD Platform SMM Core hook + SmmCorePlatformHookLib|AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf + # SMM core hook for SPI host controller + NULL|AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf + } + + # File System Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + !endif + + # EFI Shell + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + ## NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000 + } + + # Security + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf { + + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf + } + UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf + MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + !endif + + !if $(USE_EMULATED_VARIABLE_STORE) == TRUE + # these modules are included in MinPlatformPkg in + # edk2-platforms\Platform\Intel\MinPlatformPkg\Include\Dsc\CoreDxeInclude.dsc + # removing these modules being loaded by adding depex condition which is + # always false + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + # emulation bios uses emulated variable store + # hence turning off the variable protection feature + AmdCpmPkg/Features/AmdVariableProtection/AmdVariableProtection.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !else + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + !endif + !endif + + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2600GopDxe.inf + !endif + + # ACPI + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + $(PROCESSOR_PATH)/Universal/BoardAcpiDxe/BoardAcpiDxe.inf + AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + !endif + + # SPI + AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.inf + AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf + AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.inf + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(USE_EMULATED_VARIABLE_STORE) == FALSE + AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf + AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.inf + AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.inf + MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf + !else + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + !endif + + # HII + AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf + + # LOGO + AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf + + # PCI HotPlug + !if gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport == TRUE + AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf +AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf + !endif + + # AGESA OVERRIDE + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == TRUE + AgesaModulePkg/Fch/Songshan/FchSongshanSmmControlDxe/SmmControl.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !endif + + # Turn off post package repair for emulation + !if $(EMULATION) == TRUE + AgesaModulePkg/Mem/AmdMemPprSmmDriver/AmdMemPprSmmDriver.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + EmulationToolsPkg/EmuLinuxLoader/EmuLinuxLoader.inf + !endif + + !include ManageabilityPkg/Include/Manageability.dsc + ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf { + + ManageabilityTransportLib|ManageabilityPkg/Library/ManageabilityTransportKcsLib/Dxe/DxeManageabilityTransportKcs.inf + } + + # + # edk2 Redfish foundation + # +!if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/RedfishComponents.dsc.inc +!endif + + # + # USB Network (Communication Device Class) drivers + # +!if $(USB_NETWORK_SUPPORT) == TRUE + MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf +!endif + +!if $(SIMNOW_SUPPORT) == FALSE && $(EMULATION) == FALSE + AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +!endif + + # + ##For AMD PRM Feature Support## + # + + # + # PRM Libraries + # + PrmPkg/Library/DxePrmContextBufferLib/DxePrmContextBufferLib.inf + + # + # PRM Module Discovery Library + # + PrmPkg/Library/DxePrmModuleDiscoveryLib/DxePrmModuleDiscoveryLib.inf + + # + # PRM PE/COFF Library + # + PrmPkg/Library/DxePrmPeCoffLib/DxePrmPeCoffLib.inf + + # + # PRM Module Loader Driver + # + PrmPkg/PrmLoaderDxe/PrmLoaderDxe.inf + + # Adds secure boot dependency to AmdVariableProtection feature + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == FALSE + AmdCpmPkg/Features/AmdVariableProtection/AmdVariableProtection.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !endif + +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + # + # PRM Package + # + PrmContextBufferLib|PrmPkg/Library/DxePrmContextBufferLib/DxePrmContextBufferLib.inf + PrmModuleDiscoveryLib|PrmPkg/Library/DxePrmModuleDiscoveryLib/DxePrmModuleDiscoveryLib.inf + PrmPeCoffLib|PrmPkg/Library/DxePrmPeCoffLib/DxePrmPeCoffLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER,LibraryClasses.common.SMM_CORE] + PciExpressLib|MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + MSFT:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + + GCC:*_*_*_CC_FLAGS = -D USE_EDKII_HEADER_FILE + + # Turn off DEBUG messages for Release Builds + GCC:RELEASE_*_*_CC_FLAGS = -D MDEPKG_NDEBUG + INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + + !ifdef $(INTERNAL_IDS) + GCC:*_*_*_CC_FLAGS = -DINTERNAL_IDS + INTEL:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_VFRPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLCC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_PP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_APP_FLAGS = /D INTERNAL_IDS + !endif + + !if $(EMULATION) == TRUE + GCC:*_*_*_CC_FLAGS = -D IDSOPT_PRESILICON_ENABLED=1 + INTEL:*_*_*_CC_FLAGS = /D IDSOPT_PRESILICON_ENABLED=1 + MSFT:*_*_*_CC_FLAGS = /D IDSOPT_PRESILICON_ENABLED=1 + !endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + #Force modules to 4K alignment + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER] + #Force modules to 4K alignment + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + diff --git a/Platform/AMD/GenoaBoard/Include/Fdf/FlashMapInclude.fdf b/Platform/AMD/GenoaBoard/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000000000000000000000000000000000..b6408ecc2b584e70d708203aea39c6a25b94af6d --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,232 @@ +#;***************************************************************************** +#; +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +################################################################################ + +################################################################################ +# +# BIOS image layout +# +################################################################################ +### Flash layout, 16MB and 32MB iamge size with ROM3_FLASH_ENABLE = FALSE +################################################################################ +# Start End Size FV Name +################################################################################ +# 0x00000000 0x0001ffff 0x00020000 None Unused +# 0x00020000 0x00020fff 0x00001000 DATA EFS +# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM +# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW +# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved +# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory +# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory +# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory +# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory +# 0x00700000 0x007cffff 0x000d0000 FV FVADVANCED +# 0x007d0000 0x0084ffff 0x00080000 FV FVADVANCEDSECURITY +# 0x00850000 0x008effff 0x000a0000 FV FVOSBOOT +# 0x008f0000 0x00bc7fff 0x002d8000 FV FVUEFIBOOT +# 0x00bc8000 0x00beffff 0x00028000 FV FVSECURITY +# 0x00bf0000 0x00bf7fff 0x00008000 FV FVPOSTMEMORY +# 0x00bf8000 0x00bfffff 0x00008000 FV FVADVANCEDPREMEMORY +# 0x00c00000 0x00ffffff 0x00400000 FV FVPREMEMORY +################################################################################ +# Extra padding for 32MB image size +# 0x01000000 0x01ffffff 0x01000000 None unused +################################################################################ +### Flash layout, 32MB with ROM3_FLASH_ENABLE = TRUE +################################################################################ +# Start End Size FV Name +################################################################################ +# 0x00000000 0x0001ffff 0x00020000 None Unused +# 0x00020000 0x00020fff 0x00001000 DATA EFS +# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM +# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW +# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved +# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory +# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory +# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory +# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory +# 0x00bb0000 0x00bd7fff 0x00028000 FV FVSECURITY +# 0x00bd8000 0x00bf7fff 0x00020000 FV FVPOSTMEMORY +# 0x00bf8000 0x00bfffff 0x00008000 FV FVADVANCEDPREMEMORY +# 0x00c00000 0x00ffffff 0x00400000 FV FVPREMEMORY +# 0x01000000 0x010cffff 0x000d0000 FV FVADVANCED +# 0x010d0000 0x0114ffff 0x00080000 FV FVADVANCEDSECURITY +# 0x01150000 0x011effff 0x000a0000 FV FVOSBOOT +# 0x011f0000 0x014c7fff 0x002d8000 FV FVUEFIBOOT +# 0x014bc000 0x01ffefff 0x00b43000 None Unused +# 0x01fff000 0x01ffffff 0x00001000 None Unused +################################################################################ + + DEFINE ROM2_FLASH_BASE = 0xFF000000 + DEFINE ROM2_FLASH_SIZE = 0x01000000 + DEFINE ROM3_FLASH_SIZE = 0x02000000 + DEFINE SPI_BLOCK_SIZE = 0x1000 + + !ifndef BUILD_16MB_IMAGE + DEFINE BUILD_16MB_IMAGE = FALSE + !endif + !ifndef ROM3_FLASH_ENABLE + DEFINE ROM3_FLASH_ENABLE = FALSE + !endif + !ifndef ROM3_FLASH_BASE + DEFINE ROM3_FLASH_BASE = 0xFD02000000 + !endif + + !if $(BUILD_16MB_IMAGE) == TRUE + DEFINE SPI_NUM_BLOCKS = 0x1000 + !else + DEFINE SPI_NUM_BLOCKS = 0x2000 + !endif + !if ($(ROM3_FLASH_ENABLE) == TRUE) && ($(BUILD_16MB_IMAGE) == TRUE) + !error "ROM3 cannot be enabled on 16MB image" + !endif + + !ifndef FV_PRE_MEMORY_SIZE + # Do not reduce the FvPreMemorySize + DEFINE FV_PRE_MEMORY_SIZE = 0x00400000 + !endif + !ifndef FV_ADVANCED_PRE_MEMORY_SIZE + DEFINE FV_ADVANCED_PRE_MEMORY_SIZE = 0x00008000 + !endif + !ifndef FV_POST_MEMORY_SIZE + !if ($(ROM3_FLASH_ENABLE) == TRUE) + # Need extra space for DxeMain + DEFINE FV_POST_MEMORY_SIZE = 0x00020000 + !else + DEFINE FV_POST_MEMORY_SIZE = 0x00008000 +!endif + !endif + !ifndef FV_SECURITY_SIZE + DEFINE FV_SECURITY_SIZE = 0x00028000 + !endif + !ifndef FV_UEFI_BOOT_SIZE + DEFINE FV_UEFI_BOOT_SIZE = 0x002D8000 + !endif + !ifndef FV_OS_BOOT_SIZE + DEFINE FV_OS_BOOT_SIZE = 0x000A0000 + !endif + !ifndef FV_ADVANCED_SECURITY_SIZE + DEFINE FV_ADVANCED_SECURITY_SIZE = 0x00080000 + !endif + !ifndef FV_ADVANCED_SIZE + DEFINE FV_ADVANCED_SIZE = 0x000D0000 + !endif + + DEFINE FV_FW_SIG_OFFSET = 0x00020000 + DEFINE FV_FW_SIG_SIZE = 0x00001000 + + DEFINE NVRAM_AREA_VAR_OFFSET = 0x00021000 + DEFINE NVRAM_AREA_VAR_SIZE = 0x0003E000 + DEFINE NVRAM_AREA_SIZE = 0x00080000 + + DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE) + DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE) + + DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE) +# NOTE: +# +# BOOT_FV_BASE value should match with the PspData.xml ResetImage address +# e.g. +# +# +# +# +# Also note that C00000 from 0x76C000000 came from PcdFlashFvPreMemoryOffset +# if PcdFlashFvPreMemoryOffset gets changed then the below value should also +# need to be change. +# +!ifndef BOOT_FV_BASE + DEFINE BOOT_FV_BASE = 0x76C00000 +!endif + +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000 +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE) + +# +# FV offset and size assignment +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = $(FV_PRE_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = ($(ROM2_FLASH_SIZE) - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = $(FV_ADVANCED_PRE_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = $(FV_POST_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = $(FV_SECURITY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + +!if $(ROM3_FLASH_ENABLE) == FALSE + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) + + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset - gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + # NOTE: + # for ROM3_FLASH_ENABLE disabled BIOS image max address (PcdFlashFvAdvancedSize + PcdFlashFvAdvancedOffset) + # should not overlap with BIOS DIR2 offset + size in PspData.xml + # e.g + # + # +!endif + +!if $(ROM3_FLASH_ENABLE) == TRUE + # if ROM3 is enabled then continue the offset update + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = $(ROM2_FLASH_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE) + + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE) + # NOTE: + # for ROM3_FLASH_ENABLE enabled BIOS image max address (PcdFlashFvSecuritySize + PcdFlashFvSecurityOffset) + # should not overlap with BIOS DIR2 offset + size in PspData.xml + # e.g + # +!endif + +SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE) + +!if $(ROM3_FLASH_ENABLE) == TRUE + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +!endif + + diff --git a/Platform/AMD/GenoaBoard/Include/Fdf/Platform.inc.fdf b/Platform/AMD/GenoaBoard/Include/Fdf/Platform.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..b09588f8de3242a6d8a6ae1a8dbcaa133686aa8b --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Fdf/Platform.inc.fdf @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + +!ifdef $(INTERNAL_IDS) + DEFINE AGESA_PEI_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.pei.inc.fdf + DEFINE AGESA_DXE_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.dxe.inc.fdf +!else + DEFINE AGESA_PEI_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.pei.inc.fdf + DEFINE AGESA_DXE_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.dxe.inc.fdf +!endif + +DEFINE CPM_PEI_INC_FDF = AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR)$(PLATFORM_CRB)Pkg.pei.inc.fdf +DEFINE CPM_DXE_INC_FDF = AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR)$(PLATFORM_CRB)Pkg.dxe.inc.fdf diff --git a/Platform/AMD/GenoaBoard/Include/Fdf/PlatformEfs.inc.fdf b/Platform/AMD/GenoaBoard/Include/Fdf/PlatformEfs.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..de0a46c9b29acd6ed1e9c66276ee6e0b12c7194b --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Fdf/PlatformEfs.inc.fdf @@ -0,0 +1,6 @@ +#;***************************************************************************** +#; Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + diff --git a/Platform/AMD/GenoaBoard/Include/Fdf/ProjectCommon.inc.fdf b/Platform/AMD/GenoaBoard/Include/Fdf/ProjectCommon.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..c3baeb0b22b8dc7850eb94396ca83beaa740f212 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Include/Fdf/ProjectCommon.inc.fdf @@ -0,0 +1,901 @@ +#;***************************************************************************** +#; Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + +# EFS multi gen is 32bit value +!ifndef EFS_MULTI_GEN_BYTE0 + DEFINE EFS_MULTI_GEN_BYTE0 = 0xFE +!endif + +# EFS PSP address, 32-bit value, 0x00121000 +!ifndef EFS_PSP_ADDR_BYTE0 + DEFINE EFS_PSP_ADDR_BYTE0 = 0x00 +!endif +!ifndef EFS_PSP_ADDR_BYTE1 + DEFINE EFS_PSP_ADDR_BYTE1 = 0x10 +!endif +!ifndef EFS_PSP_ADDR_BYTE2 + DEFINE EFS_PSP_ADDR_BYTE2 = 0x12 +!endif +!ifndef EFS_PSP_ADDR_BYTE3 + DEFINE EFS_PSP_ADDR_BYTE3 = 0x00 +!endif + +# EFS BIOS address, 32-bit value, 0x0034A000 +!ifndef EFS_BIOS_ADDR_BYTE0 + DEFINE EFS_BIOS_ADDR_BYTE0 = 0x00 +!endif +!ifndef EFS_BIOS_ADDR_BYTE1 + DEFINE EFS_BIOS_ADDR_BYTE1 = 0xA0 +!endif +!ifndef EFS_BIOS_ADDR_BYTE2 + DEFINE EFS_BIOS_ADDR_BYTE2 = 0x34 +!endif +!ifndef EFS_BIOS_ADDR_BYTE3 + DEFINE EFS_BIOS_ADDR_BYTE3 = 0x00 +!endif + +# EFS ESPI defination +!ifndef EFS_ESPI_BYTE0 + DEFINE EFS_ESPI_BYTE0 = 0x0E +!endif +!ifndef EFS_ESPI_BYTE1 + DEFINE EFS_ESPI_BYTE1 = 0xFF +!endif + +[FD.Platform] + # Need ROM 2 flash base for calculated Addresses of FVs below 4GB + BaseAddress = $(ROM2_FLASH_BASE)|gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + # Need full flash size for FD Image size + !if $(BUILD_16MB_IMAGE) == TRUE + Size = $(ROM2_FLASH_SIZE) + !else + Size = $(ROM3_FLASH_SIZE) + !endif + ErasePolarity = 1 + BlockSize = $(SPI_BLOCK_SIZE) + NumBlocks = $(SPI_NUM_BLOCKS) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = $(ROM2_FLASH_SIZE) + SET gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaBase = $(ROM3_FLASH_BASE) + SET gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaSize = $(ROM3_FLASH_SIZE) + + # + # Embedded Firmware Signature + # + $(FV_FW_SIG_OFFSET)|$(FV_FW_SIG_SIZE) +!ifdef EMBEDDED_FIRMWARE_SIGNATURE + !include $(PROCESSOR_PATH)/Include/Fdf/PlatformEfs.inc.fdf +!else + DATA = { + 0xAA, 0x55, 0xAA, 0x55, # 0x00: Signature + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_PSP_ADDR_BYTE0), # + $(EFS_PSP_ADDR_BYTE1), # + $(EFS_PSP_ADDR_BYTE2), # + $(EFS_PSP_ADDR_BYTE3), # 0x14: PSP Dir1 + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_MULTI_GEN_BYTE0), # + 0xFF, 0xFF, 0xFF, # 0x24: BRH 4:0 as 00011b + $(EFS_BIOS_ADDR_BYTE0), # + $(EFS_BIOS_ADDR_BYTE1), # + $(EFS_BIOS_ADDR_BYTE2), # + $(EFS_BIOS_ADDR_BYTE3), # 0x28: BIOS Dir1 + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # 0x40 + 0xFF, 0xFF, 0xFF, 0xFF, # + 0xFF, 0xFF, 0xFF, 0xFF, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_ESPI_BYTE0), # + $(EFS_ESPI_BYTE1), # + 0xFF, 0xFF # 0x50: eSPI0 Configuration + # Default value = 0x0E (eSPI0, bus1, Alert mode, Port 80h, CLK1) + # + # bit[0]: eSPI PSP configuration valid bit. + # 0-Valid, 1-Not Valid + # bit[1]: enable 80h port. + # 0-disable, 1-enable + # bit[2]: Alert mode. + # 0-non-Alert, 1-dedicated Alert Pin. + # bit[3]: Data Bus, + # 0-bus0, 1-bus1. + # bit[4]: Clock pin. ignore for controller0 (always CLK0). + # for controller1, 0-CLK1, 1-CLK2 + # bit[7:5]: reserved + # 0x51: eSPI1 Configuration + # bit[0]: eSPI PSP configuration valid bit. + # 0-Valid, 1-Not Valid + # bit[1]: enable 80h port. + # 0-disable, 1-enable + # bit[2]: Alert mode. + # 0-non-Alert, 1-dedicated Alert Pin. + # bit[3]: Data Bus, + # 0-bus0, 1-bus1. + # bit[4]: Clock pin. ignore for controller0 (always CLK0). + # for controller1, 0-CLK1, 1-CLK2 + # bit[7:5]: reserved + } +!endif + # + # PSP NVRAM: NV Storage Area + # NV_VARIABLE_STORE + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x80 Blocks * 0x1000 Bytes / Block + 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End (null-terminated) + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + # Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + # Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + + # + # NV_FTW_WORKING + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, + # { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0x2C, 0xAF, 0x2C, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x1000(SPI_BLOCK_SIZE) - 0x20 (FTW_WORKING_HEADER) = 0x0FE0 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + + # + # NV_FTW_SPARE + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + + # Advance firmware volume where advance Board features are enabled. + !if $(ROM3_FLASH_ENABLE) == FALSE + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + FV = FvAdvancedSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + FV = FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + FV = FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize + FV = FvAdvancedPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + FV = FvPreMemory + + !if $(ROM3_FLASH_ENABLE) == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + FV = FvAdvancedSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + + # Fill unused space to create 32 MB FD image + $(ROM3_FLASH_SIZE) - 0x1000|0x1000 + + !elseif $(BUILD_16MB_IMAGE) == FALSE + # Fill unused space to create 32 MB FD image + 0x01000000|0x01000000 + !endif + +[FV.FvPreMemory] + FvNameGuid = 1BD2AB8A-BD04-4ee1-83B0-B05E5500121D + FvBaseAddress = $(BOOT_FV_BASE) + FvForceRebase = TRUE + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + + APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + } + + # SEC Core + INF UefiCpuPkg/SecCore/SecCore.inf + + # PEI Core + INF MdeModulePkg/Core/Pei/PeiMain.inf + + !include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf + INF AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf + + !if $(PREDEFINED_FABRIC_RESOURCES) == TRUE + INF $(PROCESSOR_PATH)/Universal/DfResourcesPei/DfResourcesPei.inf + !endif + + !if $(EMULATION) == FALSE + INF TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf + !endif + + # PEIM + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf + # INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf + # INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf + + # AMD AGESA, CPM PEI Includes + !include $(CPM_PEI_INC_FDF) + !include $(AGESA_PEI_INC_FDF) + +[FV.FvAdvancedPreMemory] + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 87F76F65-4128-4B77-85D8-DE0F757B40F8 + + # !include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvPostMemoryUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 09F55EB9-7181-4919-8755-9185E3E35CA9 + + !include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf + + # Init Board Config PCD + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + +[FV.FvPostMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 3445B977-C771-4928-9851-2EFBD55CAACD + + FILE FV_IMAGE = F38D7A3E-35F1-4CE4-ACC8-AA059ABEA622{ + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvPostMemoryUncompact + } + } + !if $(ROM3_FLASH_ENABLE) == TRUE + FILE FV_IMAGE = 8DA879CE-D6D0-4687-8025-0EA967F506BD { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvDxeMain + } + } + !endif + +[FV.FvUefiBootUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = E889A6E3-385B-4DAF-A19A-E9B1D41EB046 + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + } + !include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf + + # AMD AGESA, CPM DXE Includes + !include $(CPM_DXE_INC_FDF) + !include $(AGESA_DXE_INC_FDF) + + + # AMD PRM feature support + INF PrmPkg/PrmLoaderDxe/PrmLoaderDxe.inf + + # EDK Core modules + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + !if $(SOURCE_DEBUG_ENABLE) + INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf + !endif + + # File System Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + !endif + + # Console + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2600GopDxe.inf + !endif + + INF AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoDynamicCommand.inf + INF AmdCpmPkg/Library/AmdAutoDynamicCommand/AmdAutoToolApp.inf + + INF AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf + INF AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/PspPlatformDriver/PspPlatform.inf + + # UEFI Shell + !if $(SHELL_BIN_PACKAGE) + INF ShellBinPkg/UefiShell/UefiShell.inf + !else + INF ShellPkg/Application/Shell/Shell.inf + !endif + + # AmdHiiConfigRouting + INF AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf + + # PCI + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # SATA + !if $(SATA_SUPPORT) + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + !endif + + # NVME + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(NVME_SUPPORT) == TRUE + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + !endif + + # USB + !if $(USB_SUPPORT) + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + !endif + + # SMBIOS + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + INF AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf + + # Board + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + INF MinPlatformPkg/Test/TestPointStubDxe/TestPointStubDxe.inf + + # Spi Flash Drivers + INF AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf + INF AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusDxe.inf + INF AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcDxe.inf + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(USE_EMULATED_VARIABLE_STORE) == FALSE + INF AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf + INF AmdPlatformPkg/Universal/Spi/BoardSpiBus/BoardSpiBusSmm.inf + INF AmdPlatformPkg/Universal/Spi/AmdSpiHc/AmdSpiHcSmm.inf + INF AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + INF MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + INF AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf + !else + INF AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + !endif + + # SMM Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == TRUE + # putting under conditional flag to avoid loading modules again(second time). + # MinPlatformPkg already has these modules included if + # gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + # in CoreOsBootInclude.fdf + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf + !endif + INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + + !if $(EMULATION) == TRUE + INF EmulationToolsPkg/EmuLinuxLoader/EmuLinuxLoader.inf + !endif + + !if $(USE_EMULATED_VARIABLE_STORE) == TRUE && gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + !endif + + # + # edk2 Redfish Foundation + # +!if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.fdf.inc +!endif + + # + # USB Network (Communication Device Class) drivers + # +!if $(USB_NETWORK_SUPPORT) == TRUE + INF MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + INF MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf +!endif +!if $(SIMNOW_SUPPORT) == FALSE && $(EMULATION) == FALSE + INF AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +!endif + +[FV.FvUefiBoot] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 5489442E-30C6-479F-9CA4-BAAAEE279A20 + + FILE FV_IMAGE = B5733BA8-C486-4B0F-889C-0815F483450A { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 48FD70BC-3389-4B90-A364-EF829F41DB70 + + !include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + INF RuleOverride = DRIVER_ACPITABLE $(PROCESSOR_PATH)/Universal/BoardAcpiDxe/BoardAcpiDxe.inf + INF AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + !endif + +[FV.FvLateSilicon] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = C3740903-41CC-4C7E-B9A1-7A4B59C0CEC2 + +[FV.FvOsBoot] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 7E097F4E-A40F-47D4-93FB-8802BB9051C0 + + FILE FV_IMAGE = B975908C-6ECF-4413-A87A-199DDA11AB37 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + FILE FV_IMAGE = 41077C2D-331A-4188-809A-E5278A534E51 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvLateSilicon + } + } + +[FV.FvSecurityPreMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 87E97057-5DEF-4EB3-ACC5-063AC68AA7B7 + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvSecurityPostMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = FBA1BC9C-66FD-4B05-887C-C00AB6DDEE1F + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + INF MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + +[FV.FvSecurityLate] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 79045073-CB0E-4E28-BC31-4AE00FBF4907 + + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + INF MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf + INF UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + !endif + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + INF AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf + + FILE FREEFORM = 85254ea7-4759-4fc4-82d4-5eed5fb0a4a0 { + SECTION RAW = SecurebootKeys/PK/PK.cer + } + + FILE FREEFORM = 6f64916e-9f7a-4c35-b952-cd041efb05a3 { + SECTION RAW = SecurebootKeys/KEK/MicCorKEKCA2011_2011-06-24.crt + } + + FILE FREEFORM = c491d352-7623-4843-accc-2791a7574421 { + SECTION RAW = SecurebootKeys/db/MicWinProPCA2011_2011-10-19.crt + SECTION RAW = SecurebootKeys/db/MicCorUEFCA2011_2011-06-27.crt + } + + FILE FREEFORM = 5740766a-718e-4dc0-9935-c36f7d3f884f { + SECTION RAW = SecurebootKeys/dbx/dbxupdate_x64.bin + } + + !endif + +[FV.FvSecurity] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 2D25F4E7-50AB-442C-B2AE-9C48F3116E62 + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE = FvSecurityPreMemory + } + !endif + + FILE FV_IMAGE = 7E21EF3C-D813-40C0-BE9E-A5F739CA88AC { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityPostMemory + } + } + +[FV.FvAdvancedSecurity] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 2FFD72AF-4917-4430-8A46-97BD74816264 + + FILE FV_IMAGE = B431E18D-A610-4A65-8D81-A4E482354EF8 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +[FV.FvAdvancedUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 9DC9F824-7D1E-4A81-A410-CE3CA6ABA779 + + # Enable Manageabilty modules, such as IPMI Driver + !include ManageabilityPkg/Include/PostMemory.fdf + + # + # Network Advanced Features + # + !if gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable == TRUE + !include Network/NetworkFeaturePkg/Include/PostMemory.fdf + !endif + + # LOGO + INF AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf + + # PCI HotPlug + !if gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport == TRUE + INF AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf + !endif + + # SPCR + !if gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable == TRUE + !include SpcrFeaturePkg/Include/PostMemory.fdf + !endif + +[FV.FvAdvanced] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = FC5D42FA-964F-47D5-9D53-35D997F1B83E + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedUncompact + } + } + +[FV.FvDxeMain] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = AF85B2E1-DC13-445A-AF0F-C7659E39BBAC + + INF MdeModulePkg/Core/Dxe/DxeMain.inf diff --git a/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c b/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c new file mode 100644 index 0000000000000000000000000000000000000000..17fd7c98f19a5e189d6b319cd9161e9804cf9852 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c @@ -0,0 +1,854 @@ +/** @file + Implements AMD Genoa Platform SoC Library. + Provides interface to Get/Set platform specific data. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_IOAPIC_NUM 0x20 + +/** + Obtains proximity domain for given PciAddress, + provided in BDF format. + + Calls AGESA fabric service to obtain domain information. + + @param[in] SocketID - SocketID of the provided PciAddress + @param[in] PciAddress - PCI Address of the device + + @retval SocketID, if fails to get data from fabric service, else + PXM value. +**/ +UINTN +GetPxmDomain ( + IN UINT8 SocketId, + IN PCI_ADDR PciAddress + ) +{ + FABRIC_NUMA_SERVICES2_PROTOCOL *FabricNumaServices; + EFI_STATUS Status; + PXM_DOMAIN_INFO PxmDomainInfo; + + Status = gBS->LocateProtocol (&gAmdFabricNumaServices2ProtocolGuid, NULL, (VOID **)&FabricNumaServices); + if (EFI_ERROR (Status)) { + return SocketId; + } + + ZeroMem ((VOID *)&PxmDomainInfo, sizeof (PxmDomainInfo)); + Status = FabricNumaServices->GetPxmDomainInfo (FabricNumaServices, PciAddress, &PxmDomainInfo); + if (EFI_ERROR (Status)) { + return SocketId; + } + + ASSERT (PxmDomainInfo.Count == 1); + return PxmDomainInfo.Domain[0]; +} + +/** + @brief Get the PCIe CXL2 Info object + + NOTE: Caller will need to free structure once finished. + + @param[in, out] CxlPortInfo The CXL port information + @param[in, out] CxlCount Number of CXL port present + + @retval EFI_SUCCESS Successfully retrieve the CXL port information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +GetPcieCxl2Info ( + IN OUT AMD_CXL_PORT_INFO **CxlPortInfo, + IN OUT UINTN *CxlCount + ) +{ + UINTN CxlRbSupportCount; + EFI_STATUS Status; + PCIE_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + AMD_CXL_PORT_INFO *LocalCxlPortInfoHead; + AMD_CXL_PORT_INFO *LocalCxlPortInfo; + + if ((CxlPortInfo == NULL) || (CxlCount == NULL)) { + return EFI_INVALID_PARAMETER; + } + + CxlRbSupportCount = 0; + LocalCxlPortInfoHead = NULL; + + // Collecting Pcie information from Hob + Status = PcieGetPcieDxe (&Pcie); + if (!EFI_ERROR (Status)) { + GnbHandle = NbioGetHandle (Pcie); + while (GnbHandle != NULL) { + if ((GnbHandle->Header.DescriptorFlags & SILICON_CXL_CAPABLE) == SILICON_CXL_CAPABLE) { + CxlRbSupportCount++; + } + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + if (CxlRbSupportCount > 0) { + LocalCxlPortInfoHead = AllocateZeroPool (sizeof (AMD_CXL_PORT_INFO) * CxlRbSupportCount); + if (LocalCxlPortInfoHead == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + GnbHandle = NbioGetHandle (Pcie); + // + // The code below will get all the root bridges with CXL 2.0 support + // We need to add the CXL ACPI method to all of them + // + LocalCxlPortInfo = LocalCxlPortInfoHead; + while (GnbHandle != NULL) { + if ((GnbHandle->Header.DescriptorFlags & SILICON_CXL_CAPABLE) == SILICON_CXL_CAPABLE) { + LocalCxlPortInfo->EndPointBDF.AddressValue = GnbHandle->Address.AddressValue; + LocalCxlPortInfo->IsCxl2 = TRUE; + LocalCxlPortInfo++; + } + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + } + + *CxlCount = CxlRbSupportCount; + *CxlPortInfo = LocalCxlPortInfoHead; + if (CxlRbSupportCount == 0) { + return EFI_NOT_FOUND; + } + } else { + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + @brief Get the Pcie Cxl Info object + + NOTE: Caller will need to free structure once finished. + + @param[in, out] CxlPortInfo The CXL port information + @param[in, out] CxlCount Number of CXL port present + + @retval EFI_SUCCESS Successfully retrieve the CXL port information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetPcieCxlInfo ( + IN OUT AMD_CXL_PORT_INFO **CxlPortInfo, + IN OUT UINTN *CxlCount + ) +{ + EFI_STATUS Status; + AMD_NBIO_CXL_SERVICES_PROTOCOL *AmdNbioCxlServicesProtocol; + UINT8 Index; + AMD_CXL_PORT_INFO *CxlPortInfoHead; + AMD_CXL_PORT_INFO *LocalCxlPortInfo; + AMD_CXL_PORT_INFO_STRUCT NbioPortInfo; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + + // Check for CXL 2.0 first + Status = GetPcieCxl2Info (CxlPortInfo, CxlCount); + if (!EFI_ERROR (Status) && (*CxlCount > 0)) { + return Status; + } + + AmdNbioCxlServicesProtocol = NULL; + + Status = gBS->LocateProtocol ( + &gAmdNbioCxlServicesProtocolGuid, + NULL, + (VOID **)&AmdNbioCxlServicesProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Failed to locate AmdNbioCxlServices Protocol: %r\n", __func__, Status)); + Status = EFI_SUCCESS; + return Status; + } + + CxlPortInfoHead = AllocateZeroPool (sizeof (AMD_CXL_PORT_INFO) * AmdNbioCxlServicesProtocol->CxlCount); + if (CxlPortInfoHead == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // + // Populate the data structure for the CXL devices in the system to add to + // the ACPI Table + // + for (Index = 0, LocalCxlPortInfo = CxlPortInfoHead; Index < AmdNbioCxlServicesProtocol->CxlCount; Index++, LocalCxlPortInfo++) { + Status = AmdNbioCxlServicesProtocol->CxlGetRootPortInformation ( + AmdNbioCxlServicesProtocol, + Index, + &NbioPortInfo + ); + if (Status != EFI_SUCCESS) { + break; + } + + LocalCxlPortInfo->EndPointBDF.AddressValue = NbioPortInfo.EndPointBDF.AddressValue; + if (NbioPortInfo.DsRcrb == 0) { + LocalCxlPortInfo->IsCxl2 = TRUE; + } else { + LocalCxlPortInfo->IsCxl2 = FALSE; + } + } + + *CxlPortInfo = CxlPortInfoHead; + *CxlCount = AmdNbioCxlServicesProtocol->CxlCount; + return EFI_SUCCESS; +} + +/** + Get the platform specific IOAPIC information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] IoApicInfo The IOAPIC information + @param[in, out] IoApicCount Number of IOAPIC present + + @retval EFI_SUCCESS Successfully retrieve the IOAPIC information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetIoApicInfo ( + IN OUT EFI_ACPI_6_5_IO_APIC_STRUCTURE **IoApicInfo, + IN OUT UINT8 *IoApicCount + ) +{ + EFI_STATUS Status; + DXE_AMD_NBIO_PCIE_SERVICES_PROTOCOL *PcieServicesProtocol; + PCIE_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + GNB_PCIE_INFORMATION_DATA_HOB *PciePlatformConfigHobData; + UINT32 Value32; + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApic; + UINT8 LocalIoApicCount; + IO_APIC_IDENTIFICATION_REGISTER IoApicIdentificationRegister; + UINT32 GlobalSystemInterruptBase; + IO_APIC_VERSION_REGISTER IoApicVersionRegister; + + if ((IoApicCount == NULL) || (IoApicInfo == NULL)) { + return EFI_INVALID_PARAMETER; + } + + IoApic = AllocateZeroPool (sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE) * MAX_IOAPIC_NUM); + if (IoApic == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a:%d Not enough memory to allocate EFI_ACPI_6_5_IO_APIC_STRUCTURE\n", + __func__, + __LINE__ + )); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // FCH IO APIC + GlobalSystemInterruptBase = 0; + MmioWrite8 ( + PcdGet32 (PcdIoApicAddress) + IOAPIC_INDEX_OFFSET, + IO_APIC_VERSION_REGISTER_INDEX + ); + IoApicVersionRegister.Uint32 = MmioRead32 (PcdGet32 (PcdIoApicAddress) + IOAPIC_DATA_OFFSET); + GlobalSystemInterruptBase += IoApicVersionRegister.Bits.MaximumRedirectionEntry + 1; + Status = gBS->LocateProtocol ( + &gAmdNbioPcieServicesProtocolGuid, + NULL, + (VOID **)&PcieServicesProtocol + ); + if (!EFI_ERROR (Status)) { + PcieServicesProtocol->PcieGetTopology (PcieServicesProtocol, (UINT32 **)&PciePlatformConfigHobData); + Pcie = &(PciePlatformConfigHobData->PciePlatformConfigHob); + GnbHandle = NbioGetHandle (Pcie); + LocalIoApicCount = 0; + IoApic[LocalIoApicCount].Type = EFI_ACPI_6_5_IO_APIC; + IoApic[LocalIoApicCount].Length = sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE); + IoApic[LocalIoApicCount].IoApicId = PcdGet8 (PcdIoApicId); + IoApic[LocalIoApicCount].Reserved = 0; + IoApic[LocalIoApicCount].IoApicAddress = PcdGet32 (PcdIoApicAddress); + IoApic[LocalIoApicCount].GlobalSystemInterruptBase = 0; + LocalIoApicCount++; + while (GnbHandle != NULL) { + // Fill the header + IoApic[LocalIoApicCount].Type = EFI_ACPI_6_5_IO_APIC; + IoApic[LocalIoApicCount].Length = sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE); + IoApic[LocalIoApicCount].Reserved = 0; + // Read IOAPIC Address + SmnRegisterReadS ( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + NBIO_SPACE (GnbHandle, SMN_IOHUB0NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS), + &Value32 + ); + IoApic[LocalIoApicCount].IoApicAddress = Value32 & IOAPIC_BASE_ADDR_LO_IOAPIC_BASE_ADDR_LO_MASK; + + // Set APIC ID + MmioWrite8 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_INDEX_OFFSET, + IO_APIC_IDENTIFICATION_REGISTER_INDEX + ); + IoApicIdentificationRegister.Uint32 = MmioRead32 (IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_DATA_OFFSET); + IoApic[LocalIoApicCount].IoApicId = (UINT8)IoApicIdentificationRegister.Bits.Identification; + + // Get Read the number of redirection entries in this IOAPIC + MmioWrite8 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_INDEX_OFFSET, + IO_APIC_VERSION_REGISTER_INDEX + ); + IoApicVersionRegister.Uint32 = MmioRead32 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_DATA_OFFSET + ); + // Set Global System Interrupt Base + IoApic[LocalIoApicCount].GlobalSystemInterruptBase = GlobalSystemInterruptBase; + GlobalSystemInterruptBase += IoApicVersionRegister.Bits.MaximumRedirectionEntry + 1; + + LocalIoApicCount++; + GnbHandle = GnbGetNextHandle (GnbHandle); + } + } + + *IoApicInfo = IoApic; + *IoApicCount = LocalIoApicCount; + return EFI_SUCCESS; +} + +/** + Get the platform PCIe configuration information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] RootBridge The root bridge information + @param[in, out] RootBridgeCount Number of root bridges present + + @retval EFI_SUCCESS Successfully retrieve the root bridge information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetPcieInfo ( + IN OUT AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE **RootBridge, + IN OUT UINTN *RootBridgeCount + ) +{ + EFI_STATUS Status; + UINTN NumberOfRootBridges; + UINTN RbIndex; + UINTN Index; + UINTN CxlIndex; + AMD_PCI_RESOURCES_PROTOCOL *AmdPciResources; + AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE *LocalRootBridgeArray; // do not free + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApicInfo; + UINT8 IoApicCount; + AMD_CXL_PORT_INFO *CxlPortInfoHead; + AMD_CXL_PORT_INFO *CxlPortInfo; + UINTN CxlCount; + PCI_ADDR PciAddr; + + IoApicInfo = NULL; + IoApicCount = 0; + Status = GetIoApicInfo (&IoApicInfo, &IoApicCount); + if (EFI_ERROR (Status) || (IoApicInfo == NULL) || (IoApicCount == 0)) { + DEBUG ((DEBUG_ERROR, "%a:%d Cannot obtain NBIO IOAPIC information.\n", __func__, __LINE__)); + return EFI_NOT_FOUND; + } + + Status = gBS->LocateProtocol ( + &gAmdPciResourceProtocolGuid, + NULL, + (VOID **)&AmdPciResources + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to locate AMD PCIe Resource Protocol: %r\n", + __func__, + Status + )); + return Status; + } + + Status = AmdPciResources->AmdPciResourcesGetNumberOfRootBridges ( + AmdPciResources, + &NumberOfRootBridges + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to get Number Of Root Bridges: %r\n", + __func__, + Status + )); + return Status; + } + + LocalRootBridgeArray = AllocateZeroPool (sizeof (AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE) * NumberOfRootBridges); + if (LocalRootBridgeArray == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // Collect CXL info + CxlPortInfoHead = NULL; + CxlCount = 0; + Status = GetPcieCxlInfo (&CxlPortInfoHead, &CxlCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "[INFO] Cannot find CXL device.\n")); + } + + // Collect Root Bridges to be sorted + for (RbIndex = 1; RbIndex <= NumberOfRootBridges; RbIndex++) { + Status = AmdPciResources->AmdPciResourcesGetRootBridgeInfo (AmdPciResources, RbIndex, (PCI_ROOT_BRIDGE_OBJECT **)&LocalRootBridgeArray[RbIndex - 1].Object); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to get Root Bridges information : %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + if (CxlPortInfoHead != NULL) { + FreePool (CxlPortInfoHead); + } + + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + + // Assign GSI values + LocalRootBridgeArray[RbIndex - 1].GlobalInterruptStart = IoApicInfo[RbIndex].GlobalSystemInterruptBase; + + // Get PXM info + ZeroMem ((VOID *)&PciAddr, sizeof (PciAddr)); + PciAddr.Address.Bus = (UINT32)LocalRootBridgeArray[RbIndex - 1].Object->BaseBusNumber; + PciAddr.Address.Segment = (UINT32)LocalRootBridgeArray[RbIndex - 1].Object->Segment; + LocalRootBridgeArray[RbIndex - 1].PxmDomain = GetPxmDomain (LocalRootBridgeArray[RbIndex - 1].Object->SocketId, PciAddr); + + // check for CXL port + if (CxlCount > 0) { + for (CxlIndex = 0, CxlPortInfo = CxlPortInfoHead; CxlIndex < CxlCount; CxlIndex++, CxlPortInfo++) { + if ((CxlPortInfo->EndPointBDF.Address.Segment == LocalRootBridgeArray[RbIndex - 1].Object->Segment) && + (CxlPortInfo->EndPointBDF.Address.Bus == LocalRootBridgeArray[RbIndex - 1].Object->BaseBusNumber)) + { + LocalRootBridgeArray[RbIndex - 1].CxlCount = 1; + LocalRootBridgeArray[RbIndex - 1].CxlPortInfo.IsCxl2 = CxlPortInfo->IsCxl2; + LocalRootBridgeArray[RbIndex - 1].CxlPortInfo.EndPointBDF.AddressValue = CxlPortInfo->EndPointBDF.AddressValue; + break; + } + } + } + + Status = AmdPciResources->AmdPciResourcesGetNumberOfRootPorts ( + AmdPciResources, + LocalRootBridgeArray[RbIndex - 1].Object->Index, + &LocalRootBridgeArray[RbIndex - 1].RootPortCount + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: GetNumberOfRootPorts Failed: %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + + for (Index = 1; Index <= LocalRootBridgeArray[RbIndex - 1].RootPortCount; Index++) { + Status = AmdPciResources->AmdPciResourcesGetRootPortInfo ( + AmdPciResources, + LocalRootBridgeArray[RbIndex - 1].Object->Index, + Index, + (PCI_ROOT_PORT_OBJECT **)&LocalRootBridgeArray[RbIndex - 1].RootPort[Index] + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: AmdPciResourcesGetRootPortInfo Failed: %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + } + } + + FreePool (IoApicInfo); + if (CxlPortInfoHead != NULL) { + FreePool (CxlPortInfoHead); + } + + *RootBridge = LocalRootBridgeArray; + *RootBridgeCount = NumberOfRootBridges; + return Status; +} + +/** + This function returns SBDF information for a given slot number. + + @param[in] SlotNumInfo Slot number to be provided. + @param[out] SegInfo Segment number. + @param[out] BusInfo Bus number. + @param[out] DevFunInfo Bits 0-2 corresponds to function number & bits 3-7 corresponds + to device number. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_INVALID_PARAMETER One or many parameters are invalid. + @retval EFI_NOT_FOUND SBDF information is not found for the given slot number. + +**/ +EFI_STATUS +SlotBdfInfo ( + IN UINT16 *SlotNumInfo, + OUT UINT16 *SegInfo, + OUT UINT8 *BusInfo, + OUT UINT8 *DevFunInfo + ) +{ + EFI_STATUS Status; + PCIE_PLATFORM_CONFIG *Pcie; + PCIE_COMPLEX_CONFIG *ComplexList; + PCIE_SILICON_CONFIG *SiliconList; + PCIE_WRAPPER_CONFIG *WrapperList; + PCIE_ENGINE_CONFIG *EngineList; + + if ((SlotNumInfo == NULL) || (SegInfo == NULL) || (BusInfo == NULL) || (DevFunInfo == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Pcie = NULL; + Status = PcieGetPcieDxe (&Pcie); + if (EFI_ERROR (Status)) { + return Status; + } + + ComplexList = (PCIE_COMPLEX_CONFIG *)PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + + while (ComplexList != NULL) { + SiliconList = PcieConfigGetChildSilicon (ComplexList); + while (SiliconList != NULL) { + WrapperList = PcieConfigGetChildWrapper (SiliconList); + while (WrapperList != NULL) { + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (EngineList->Type.Port.PortData.SlotNum == *SlotNumInfo) { + *SegInfo = EngineList->Type.Port.Address.Address.Segment & 0xFFFF; + *BusInfo = EngineList->Type.Port.Address.Address.Bus & 0xFF; + *DevFunInfo = (((EngineList->Type.Port.Address.Address.Device) & 0x1F) << 3) | + ((EngineList->Type.Port.Address.Address.Function) & 0x7); + return EFI_SUCCESS; + } + + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + + SiliconList = PcieLibGetNextDescriptor (SiliconList); + } + + if ((ComplexList->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_TOPOLOGY) == 0) { + ComplexList++; + } else { + ComplexList = NULL; + } + } + + return EFI_NOT_FOUND; +} + +/** + This function allocates and populate system slot smbios record (Type 9). + + @param DxioPortPtr Pointer to DXIO port descriptor. + @param SmbiosRecordPtr Pointer to smbios type 9 record. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_INVALID_PARAMETER One or many parameters are invalid. + @retval EFI_OUT_OF_RESOURCES Resource not available. + +**/ +EFI_STATUS +CreateSmbiosSystemSlotRecord ( + IN DXIO_PORT_DESCRIPTOR *DxioPortPtr, + IN OUT SMBIOS_TABLE_TYPE9 **SmbiosRecordPtr + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + UINT16 SlotNumInfo; + UINT16 SegInfo; + UINT8 BusInfo; + UINT8 DevFunInfo; + + Status = EFI_SUCCESS; + SegInfo = 0xFFFF; + BusInfo = 0xFF; + DevFunInfo = 0xFF; + + if ((DxioPortPtr == NULL) || (SmbiosRecordPtr == NULL)) { + return EFI_INVALID_PARAMETER; + } + + SmbiosRecord = NULL; + SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9)); + if (SmbiosRecord == NULL) { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } else { + // Currently only map PCIE slots in system slot table. + if (DxioPortPtr->EngineData.EngineType == DxioPcieEngine) { + switch (DxioPortPtr->Port.LinkSpeedCapability) { + case DxioGenMaxSupported: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + case DxioGen1: + SmbiosRecord->SlotType = SlotTypePciExpress; + break; + case DxioGen2: + SmbiosRecord->SlotType = SlotTypePciExpressGen2; + break; + case DxioGen3: + SmbiosRecord->SlotType = SlotTypePciExpressGen3; + break; + case DxioGen4: + SmbiosRecord->SlotType = SlotTypePciExpressGen4; + break; + case DxioGen5: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + default: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + } + } else { + SmbiosRecord->SlotType = SlotTypeOther; + } + + switch (DxioPortPtr->EngineData.DxioEndLane - + DxioPortPtr->EngineData.DxioStartLane) + { + case 15: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth16X; + SmbiosRecord->DataBusWidth = 16; + break; + case 7: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth8X; + SmbiosRecord->DataBusWidth = 8; + break; + case 3: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth4X; + SmbiosRecord->DataBusWidth = 4; + break; + case 1: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth2X; + SmbiosRecord->DataBusWidth = 2; + break; + default: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth1X; + SmbiosRecord->DataBusWidth = 1; + break; + } + + if (DxioPortPtr->Port.EndpointStatus == (DXIO_ENDPOINT_STATUS)EndpointDetect) { + SmbiosRecord->CurrentUsage = SlotUsageInUse; + } else if (DxioPortPtr->Port.EndpointStatus == (DXIO_ENDPOINT_STATUS)EndpointNotPresent) { + SmbiosRecord->CurrentUsage = SlotUsageAvailable; + } else { + SmbiosRecord->CurrentUsage = SlotUsageUnknown; + } + + SlotNumInfo = DxioPortPtr->Port.SlotNum; + Status = SlotBdfInfo ( + &SlotNumInfo, + &SegInfo, + &BusInfo, + &DevFunInfo + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Could not get SBDF information %r\n", Status)); + } + + SmbiosRecord->SlotLength = SlotLengthLong; + SmbiosRecord->SlotID = DxioPortPtr->Port.SlotNum; + SmbiosRecord->SegmentGroupNum = SegInfo; + SmbiosRecord->BusNum = BusInfo; + SmbiosRecord->DevFuncNum = DevFunInfo; + SmbiosRecord->PeerGroupingCount = 0; + + *SmbiosRecordPtr = SmbiosRecord; + } + + return Status; +} + +/** + Get the platform specific System Slot information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] SystemSlotInfo The System Slot information + @param[in, out] SystemSlotCount Number of System Slot present + + @retval EFI_UNSUPPORTED Platform do not support this function. +**/ +EFI_STATUS +EFIAPI +GetSystemSlotInfo ( + IN OUT SMBIOS_TABLE_TYPE9 **SystemSlotInfo, + IN OUT UINTN *SystemSlotCount + ) +{ + AMD_CPM_TABLE_PROTOCOL *CpmTableProtocolPtr; + AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTablePtr2[2]; + EFI_STATUS Status; + UINTN SocketIdx; + UINTN DxioPortIdx; + UINTN SlotCount; + SMBIOS_TABLE_TYPE9 *SlotInfo; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + + if ((SystemSlotInfo == NULL) || (SystemSlotCount == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = gBS->LocateProtocol ( + &gAmdCpmTableProtocolGuid, + NULL, + (VOID **)&CpmTableProtocolPtr + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to locate AmdCpmTableProtocol: %r\n", Status)); + return Status; + } + + DxioTopologyTablePtr2[0] = NULL; + DxioTopologyTablePtr2[0] = CpmTableProtocolPtr->CommonFunction.GetTablePtr2 ( + CpmTableProtocolPtr, + CPM_SIGNATURE_DXIO_TOPOLOGY + ); + + DxioTopologyTablePtr2[1] = NULL; + DxioTopologyTablePtr2[1] = CpmTableProtocolPtr->CommonFunction.GetTablePtr2 ( + CpmTableProtocolPtr, + CPM_SIGNATURE_DXIO_TOPOLOGY_S1 + ); + + // Add Smbios System Slot information for all sockets present. + SlotCount = 0; + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTablePtr2[SocketIdx] != NULL) { + for (DxioPortIdx = 0; DxioPortIdx < AMD_DXIO_PORT_DESCRIPTOR_SIZE; + DxioPortIdx++) + { + // Check if Slot is present + if ((DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Port.SlotNum > 0) && + (DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Port.PortPresent == 1)) + { + SlotCount++; + } + + // Terminate if last port found. + if ((DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Flags & 0x80000000)) { + break; + } + } + } + } + + if (SlotCount == 0) { + return EFI_NOT_FOUND; + } + + SlotInfo = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9) * SlotCount); + if (SlotInfo == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + SlotCount = 0; + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTablePtr2[SocketIdx] != NULL) { + for (DxioPortIdx = 0; DxioPortIdx < AMD_DXIO_PORT_DESCRIPTOR_SIZE; + DxioPortIdx++) + { + // Check if Slot is present + if ((DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Port.SlotNum > 0) && + (DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Port.PortPresent == 1)) + { + SmbiosRecord = NULL; + Status = CreateSmbiosSystemSlotRecord ( + &DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx], + &SmbiosRecord + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Slot (%d) information not found. Status = %r\n", + DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Port.SlotNum, + Status + )); + } else { + CopyMem (&SlotInfo[SlotCount], SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9)); + SlotCount++; + } + } + + // Terminate if last port found. + if ((DxioTopologyTablePtr2[SocketIdx]->Port[DxioPortIdx].Flags & 0x80000000)) { + break; + } + } + } + } + + *SystemSlotInfo = SlotInfo; + *SystemSlotCount = SlotCount; + return EFI_SUCCESS; +} diff --git a/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf b/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..4e7361747460a91d22d9b770741a5ad43597f4b9 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf @@ -0,0 +1,56 @@ +## @file +# INF file of AMD Platform SoC library +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = DxePlatformSocLib + MODULE_UNI_FILE = DxePlatformSocLib.uni + FILE_GUID = 16CB3571-F056-4486-87AB-E198AE479F63 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformSocLib + +[Sources] + DxePlatformSocLib.c + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModuleDfPkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + AgesaPkg/AgesaPkg.dec + AmdCpmPkg/AmdCpmPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + HobLib + NbioCommonDxeLib + NbioHandleLib + PcdLib + PcieConfigLib + SmnAccessLib + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket ## CONSUMES + +[Protocols] + gAmdFabricNumaServices2ProtocolGuid + gAmdNbioCxlServicesProtocolGuid + gAmdNbioPcieServicesProtocolGuid + gAmdPciResourceProtocolGuid + gAmdSocLogicalIdProtocolGuid + gAmdCpmTableProtocolGuid + +[Depex] + gAmdNbioPcieServicesProtocolGuid diff --git a/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni b/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni new file mode 100644 index 0000000000000000000000000000000000000000..ec26471a7abe6ea005f7ee5e41f8192a9bec5205 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni @@ -0,0 +1,12 @@ +## @file +# UNI file of AMD Genoa Platform SoC library +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +#string STR_MODULE_ABSTRACT #language en-US "AMD DXE Genoa SoC library instance." + +#string STR_MODULE_DESCRIPTION #language en-US "AMD DXE Genoa SoC library instance." + diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..a57389bf6dd7263350ba628d74524f52d5e34582 --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +#;***************************************************************************** +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"Default String" + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("069F7A75-1155-455F-81E9-2D778481D7EF")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"Default String" + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"Default String" + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"Default String" + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"Default String"} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"Default String"} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/OnyxBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..ba375cf28681dbd8d2c5e118aa2d51ab7d3f0bbb --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/Project.dsc @@ -0,0 +1,185 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Onyx +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 0b5350f0-7076-11eb-9439-0242ac130002 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "ONYX " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020202058594E4F # "ONYX " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|256 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|1 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|4 + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/OnyxBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..daf30856314c75e1832dff94b55bce9d422c1ea7 --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/Project.fdf @@ -0,0 +1,38 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..a64492c28bc3012fc634020b1bd6547176db610f --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,146 @@ +{ + "rs1oi": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1oi_simnow": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "INTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1oe": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1oe_simnow": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "EXTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1ois": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1ois_simnow": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "INTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1oes": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1oes_simnow": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "EXTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1oe_nocbs": { + "platform": "OnyxBoardPkg", + "sku": "1O", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Onyx", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..d1e24c2ef8017feb0c6d6993a0219a3531feb218 --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..227472ba3b204867934652cba9b8c322f59af44c --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Onyx' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..e0e05c9d74b021bdc8c1d83e9bbf3682392448b2 --- /dev/null +++ b/Platform/AMD/GenoaBoard/OnyxBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") diff --git a/Platform/AMD/GenoaBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c b/Platform/AMD/GenoaBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c new file mode 100644 index 0000000000000000000000000000000000000000..fb00356012e08d98fd8ddd300156150a1f076697 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c @@ -0,0 +1,1315 @@ +/** + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file +Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "TestPointInternal.h" + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GUID mTestPointSmmCommunciationGuid = TEST_POINT_SMM_COMMUNICATION_GUID; + +VOID +TestPointDumpGcd ( + OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR **GcdMemoryMap, OPTIONAL + OUT UINTN *GcdMemoryMapNumberOfDescriptors, OPTIONAL + OUT EFI_GCD_IO_SPACE_DESCRIPTOR **GcdIoMap, OPTIONAL + OUT UINTN *GcdIoMapNumberOfDescriptors, OPTIONAL + IN BOOLEAN DumpPrint + ); + +VOID +TestPointDumpUefiMemoryMap ( + OUT EFI_MEMORY_DESCRIPTOR **UefiMemoryMap, OPTIONAL + OUT UINTN *UefiMemoryMapSize, OPTIONAL + OUT UINTN *UefiDescriptorSize, OPTIONAL + IN BOOLEAN DumpPrint + ); + +EFI_STATUS +TestPointCheckUefiMemoryMap ( + VOID + ); + +EFI_STATUS +TestPointCheckUefiMemAttribute ( + VOID + ); + +EFI_STATUS +TestPointCheckPciResource ( + VOID + ); + +EFI_STATUS +TestPointCheckConsoleVariable ( + VOID + ); + +EFI_STATUS +TestPointCheckBootVariable ( + VOID + ); + +VOID +TestPointDumpDevicePath ( + VOID + ); + +EFI_STATUS +TestPointCheckMemoryTypeInformation ( + VOID + ); + +EFI_STATUS +TestPointCheckAcpi ( + VOID + ); + +EFI_STATUS +TestPointCheckAcpiGcdResource ( + VOID + ); + +EFI_STATUS +TestPointCheckHsti ( + VOID + ); + +VOID +TestPointDumpVariable ( + VOID + ); + +EFI_STATUS +TestPointCheckEsrt ( + VOID + ); + +EFI_STATUS +TestPointCheckSmmInfo ( + VOID + ); + +EFI_STATUS +TestPointCheckPciBusMaster ( + VOID + ); + +EFI_STATUS +TestPointCheckLoadedImage ( + VOID + ); + +EFI_STATUS +EFIAPI +TestPointCheckSmiHandlerInstrument ( + VOID + ); + +EFI_STATUS +TestPointCheckUefiSecureBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckPiSignedFvBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckTcgTrustedBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckTcgMor ( + VOID + ); + +EFI_STATUS +TestPointVtdEngine ( + VOID + ); + +VOID * +TestPointGetAcpi ( + IN UINT32 Signature + ); + +GLOBAL_REMOVE_IF_UNREFERENCED ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT mTestPointStruct = { + PLATFORM_TEST_POINT_VERSION, + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + {TEST_POINT_IMPLEMENTATION_ID_PLATFORM_DXE}, + TEST_POINT_FEATURE_SIZE, + {0}, // FeaturesImplemented + {0}, // FeaturesVerified + 0, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFeatureImplemented[TEST_POINT_FEATURE_SIZE]; + +/** + This service verifies bus master enable (BME) is disabled after PCI enumeration. + + Test subject: PCI device BME. + Test overview: Verify BME is cleared. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps results to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointPciEnumerationDonePciBusMasterDisabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciBusMasterDisabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPciBusMaster (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciBusMasterDisabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies PCI device resource assignment after PCI enumeration. + + Test subject: PCI device resources. + Test overview: Verify all PCI devices have been assigned proper resources. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps PCI resource assignments to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointPciEnumerationDonePciResourceAllocated ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciResourceAllocated - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPciResource (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciResourceAllocated - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the DMA ACPI table is reported at the end of DXE. + + Test subject: DMA protection. + Test overview: DMA ACPI table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the DMA ACPI table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeDmaAcpiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Acpi; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaAcpiTableFunctional - Enter\n")); + + Acpi = TestPointGetAcpi (EFI_ACPI_6_5_DMA_REMAPPING_TABLE_SIGNATURE); + if (Acpi == NULL) { + DEBUG ((DEBUG_ERROR, "No DMAR table\n")); + TestPointLibAppendErrorString ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL_ERROR_CODE \ + TEST_POINT_END_OF_DXE \ + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL_ERROR_STRING + ); + Status = EFI_INVALID_PARAMETER; + } else { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL + ); + Status = EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaAcpiTableFunctional - Exit\n")); + return Status; +} + +/** + This service verifies DMA protection configuration at the end of DXE. + + Test subject: DMA protection. + Test overview: DMA protection in DXE. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the DMA ACPI table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeDmaProtectionEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_DMA_PROTECTION_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaProtectionEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointVtdEngine (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_DMA_PROTECTION_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaProtectionEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies no 3rd party PCI option ROMs (OPROMs) were dispatched prior to the end of DXE. + + Test subject: 3rd party OPROMs. + Test overview: Verify no 3rd party PCI OPROMs were . + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps PCI resource assignments to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeNoThirdPartyPciOptionRom ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeNoThirdPartyPciOptionRom - Enter\n")); + + Result = TRUE; + Status = TestPointCheckLoadedImage (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeNoThirdPartyPciOptionRom - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of System Management RAM (SMRAM) alignment at SMM Ready To Lock. + + Test subject: SMRAM Information. + Test overview: SMRAM is aligned. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SMRAM region table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToLockSmramAligned ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockSmramAligned - Enter\n")); + + Result = TRUE; + Status = TestPointCheckSmmInfo (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockSmramAligned - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the Windows SMM Security Mitigation Table (WSMT) at SMM Ready To Lock. + + Test subject: Windows Security SMM Mitigation Table. + Test overview: The table is reported in compliance with the Windows SMM Security Mitigations Table + ACPI table specification. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the WSMT to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToLockWsmtTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Acpi; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockWsmtTableFunctional - Enter\n")); + + Acpi = TestPointGetAcpi (EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE); + if (Acpi == NULL) { + DEBUG ((DEBUG_ERROR, "No WSMT table\n")); + TestPointLibAppendErrorString ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_CODE \ + TEST_POINT_DXE_SMM_READY_TO_LOCK \ + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_STRING + ); + Status = EFI_INVALID_PARAMETER; + } else { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL + ); + Status = EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockWsmtTableFunctional - Exit\n")); + return Status; +} + +/** + This service verifies the validity of the SMM page table at Ready To Boot. + + Test subject: SMM page table. + Test overview: The SMM page table settings matches the SmmMemoryAttribute table. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Reports an error if verification fails. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToBootSmmPageProtection ( + VOID + ) +{ + EFI_MEMORY_DESCRIPTOR *UefiMemoryMap; + UINTN UefiMemoryMapSize; + UINTN UefiDescriptorSize; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMap; + EFI_GCD_IO_SPACE_DESCRIPTOR *GcdIoMap; + UINTN GcdMemoryMapNumberOfDescriptors; + UINTN GcdIoMapNumberOfDescriptors; + EFI_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable; + UINTN MemoryAttributesTableSize; + EFI_STATUS Status; + UINTN CommSize; + UINT64 LongCommSize; + UINT8 *CommBuffer; + EFI_SMM_COMMUNICATE_HEADER *CommHeader; + EFI_SMM_COMMUNICATION_PROTOCOL *SmmCommunication; + UINTN MinimalSizeNeeded; + EDKII_PI_SMM_COMMUNICATION_REGION_TABLE *PiSmmCommunicationRegionTable; + UINT32 Index; + EFI_MEMORY_DESCRIPTOR *Entry; + UINTN Size; + TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO *CommData; + + if ((mFeatureImplemented[6] & TEST_POINT_BYTE6_SMM_READY_TO_BOOT_SMM_PAGE_LEVEL_PROTECTION) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmmPageProtection - Enter\n")); + + TestPointDumpUefiMemoryMap (&UefiMemoryMap, &UefiMemoryMapSize, &UefiDescriptorSize, FALSE); + TestPointDumpGcd (&GcdMemoryMap, &GcdMemoryMapNumberOfDescriptors, &GcdIoMap, &GcdIoMapNumberOfDescriptors, FALSE); + + MemoryAttributesTable = NULL; + MemoryAttributesTableSize = 0; + Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); + if (!EFI_ERROR (Status)) { + MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries; + } + + Status = gBS->LocateProtocol(&gEfiSmmCommunicationProtocolGuid, NULL, (VOID **)&SmmCommunication); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: Locate SmmCommunication protocol - %r\n", Status)); + return EFI_SUCCESS; + } + + MinimalSizeNeeded = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) + + sizeof(TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO) + + UefiMemoryMapSize + + GcdMemoryMapNumberOfDescriptors * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR) + + GcdIoMapNumberOfDescriptors * sizeof(EFI_GCD_IO_SPACE_DESCRIPTOR) + + MemoryAttributesTableSize; + + Status = EfiGetSystemConfigurationTable( + &gEdkiiPiSmmCommunicationRegionTableGuid, + (VOID **)&PiSmmCommunicationRegionTable + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: Get PiSmmCommunicationRegionTable - %r\n", Status)); + return EFI_SUCCESS; + } + ASSERT(PiSmmCommunicationRegionTable != NULL); + Entry = (EFI_MEMORY_DESCRIPTOR *)(PiSmmCommunicationRegionTable + 1); + Size = 0; + for (Index = 0; Index < PiSmmCommunicationRegionTable->NumberOfEntries; Index++) { + if (Entry->Type == EfiConventionalMemory) { + Size = EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages); + if (Size >= MinimalSizeNeeded) { + break; + } + } + Entry = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)Entry + PiSmmCommunicationRegionTable->DescriptorSize); + } + // EDKII_BIOS_OVERRIDE START + // WA, REVISIT disable the assert + // ASSERT(Index < PiSmmCommunicationRegionTable->NumberOfEntries); + // EDKII_BIOS_OVERRIDE END + + CommBuffer = (UINT8 *)(UINTN)Entry->PhysicalStart; + + CommHeader = (EFI_SMM_COMMUNICATE_HEADER *)&CommBuffer[0]; + CopyMem(&CommHeader->HeaderGuid, &mTestPointSmmCommunciationGuid, sizeof(mTestPointSmmCommunciationGuid)); + CommHeader->MessageLength = MinimalSizeNeeded - OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data); + + CommData = (TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO *)&CommBuffer[OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data)]; + CommData->Header.Version = TEST_POINT_SMM_COMMUNICATION_VERSION; + CommData->Header.FuncId = TEST_POINT_SMM_COMMUNICATION_FUNC_ID_UEFI_GCD_MAP_INFO; + CommData->Header.Size = CommHeader->MessageLength; + CommData->UefiMemoryMapOffset = sizeof(TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO); + CommData->UefiMemoryMapSize = UefiMemoryMapSize; + CommData->GcdMemoryMapOffset = CommData->UefiMemoryMapOffset + CommData->UefiMemoryMapSize; + CommData->GcdMemoryMapSize = GcdMemoryMapNumberOfDescriptors * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR); + CommData->GcdIoMapOffset = CommData->GcdMemoryMapOffset + CommData->GcdMemoryMapSize; + CommData->GcdIoMapSize = GcdIoMapNumberOfDescriptors * sizeof(EFI_GCD_IO_SPACE_DESCRIPTOR); + CommData->UefiMemoryAttributeTableOffset = CommData->GcdIoMapOffset + CommData->GcdIoMapSize; + CommData->UefiMemoryAttributeTableSize = MemoryAttributesTableSize; + + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->UefiMemoryMapOffset), + UefiMemoryMap, + (UINTN)CommData->UefiMemoryMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->GcdMemoryMapOffset), + GcdMemoryMap, + (UINTN)CommData->GcdMemoryMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->GcdIoMapOffset), + GcdIoMap, + (UINTN)CommData->GcdIoMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->UefiMemoryAttributeTableOffset), + MemoryAttributesTable, + (UINTN)CommData->UefiMemoryAttributeTableSize + ); + + Status = SafeUint64Add (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, Data), CommHeader->MessageLength, &LongCommSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: LongCommSize calculation - %r\n", Status)); + return EFI_SUCCESS; + } + + Status = SafeUint64ToUintn (LongCommSize, &CommSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: CommSize conversion - %r\n", Status)); + return EFI_SUCCESS; + } + + Status = SmmCommunication->Communicate(SmmCommunication, CommBuffer, &CommSize); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: SmmCommunication - %r\n", Status)); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmmPageProtection - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies SMI handler profiling. + + Test subject: SMI handler profiling. + Test overview: + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SMI handler profile. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToBootSmiHandlerInstrument ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmiHandlerInstrument - Enter\n")); + + Result = TRUE; + Status = TestPointCheckSmiHandlerInstrument (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmiHandlerInstrument - Exit\n")); + return EFI_SUCCESS; +} + +/** + This services verifies the validity of installed ACPI tables at Ready To Boot. + + Test subject: ACPI tables. + Test overview: The ACPI table settings are valid. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the installed ACPI tables. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootAcpiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootAcpiTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckAcpi (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootAcpiTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This services verifies ACPI table resources are in the GCD. + + Test subject: ACPI memory resources. + Test overview: Memory resources are in both ACPI and GCD. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the installed ACPI tables and GCD. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootGcdResourceFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_GCD_RESOURCE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootGcdResourceFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckAcpiGcdResource (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_GCD_RESOURCE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootGcdResourceFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the memory type information settings. + + Test subject: Memory type information. + Test overview: Inspect an verify memory type information is correct. + Confirm no fragmentation exists in the ACPI/Reserved/Runtime regions. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the memory type information settings to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootMemoryTypeInformationFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootMemoryTypeInformationFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckMemoryTypeInformation (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + TestPointDumpUefiMemoryMap (NULL, NULL, NULL, TRUE); + Status = TestPointCheckUefiMemoryMap (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootMemoryTypeInformationFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the memory type information settings. + + Test subject: Memory type information. + Test overview: Inspect an verify memory type information is correct. + Confirm no fragmentation exists in the ACPI/Reserved/Runtime regions. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the memory type information settings to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiMemoryAttributeTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiMemoryAttributeTableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpUefiMemoryMap (NULL, NULL, NULL, TRUE); + TestPointDumpGcd (NULL, NULL, NULL, NULL, TRUE); + Status = TestPointCheckUefiMemAttribute (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiMemoryAttributeTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the UEFI memory attribute table. + + Test subject: UEFI memory attribute table. + Test overview: The UEFI memeory attribute table is reported. The image code/data is consistent with the table. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the UEFI image information and the UEFI memory attribute table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiBootVariableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiBootVariableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpDevicePath (); + TestPointDumpVariable (); + Status = TestPointCheckBootVariable (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiBootVariableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the consle variable information. + + Test subject: Console. + Test overview: Inspect and verify the console variable information is correct. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the console variable information. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiConsoleVariableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiConsoleVariableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpDevicePath (); + TestPointDumpVariable (); + Status = TestPointCheckConsoleVariable (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiConsoleVariableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the HSTI table. + + Test subject: HSTI table. + Test overview: Verify the HSTI table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the HSTI table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootHstiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[8] & TEST_POINT_BYTE8_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootHstiTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckHsti (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 8, + TEST_POINT_BYTE8_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootHstiTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the ESRT table. + + Test subject: ESRT table. + Test overview: Verify the ESRT table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the ESRT table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootEsrtTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[8] & TEST_POINT_BYTE8_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootEsrtTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckEsrt (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 8, + TEST_POINT_BYTE8_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootEsrtTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies UEFI Secure Boot is enabled. + + Test subject: UEFI Secure Boot. + Test overview: Verify the SecureBoot variable is set. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SecureBoot variable. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiSecureBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiSecureBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckUefiSecureBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiSecureBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies Platform Initialization (PI) Signed FV Boot is enabled. + + Test subject: PI Signed FV Boot. + Test overview: Verify PI signed FV boot is enabled. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootPiSignedFvBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootPiSignedFvBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPiSignedFvBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootPiSignedFvBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies TCG Trusted Boot is enabled. + + Test subject: TCG Trusted Boot. + Test overview: Verify the TCG protocol is installed. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the TCG protocol capability. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootTcgTrustedBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgTrustedBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckTcgTrustedBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgTrustedBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies TCG Memory Overwrite Request (MOR) is enabled. + + Test subject: TCG MOR. + Test overview: Verify the MOR UEFI variable is set. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the MOR UEFI variable. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootTcgMorEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_TCG_MOR_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgMorEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckTcgMor (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_TCG_MOR_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgMorEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the system state after Exit Boot Services is invoked. + + @retval EFI_SUCCESS The test point check was performed successfully. +**/ +EFI_STATUS +EFIAPI +TestPointExitBootServices ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "======== TestPointExitBootServices - Enter\n")); + + DEBUG ((DEBUG_INFO, "======== TestPointExitBootServices - Exit\n")); + + return EFI_SUCCESS; +} + +/** + Initialize feature data. + + @param[in] Role The test point role being requested. +**/ +VOID +InitData ( + IN UINT32 Role + ) +{ + EFI_STATUS Status; + + ASSERT (PcdGetSize(PcdTestPointIbvPlatformFeature) == sizeof(mFeatureImplemented)); + CopyMem (mFeatureImplemented, PcdGetPtr(PcdTestPointIbvPlatformFeature), sizeof(mFeatureImplemented)); + + mTestPointStruct.Role = Role; + CopyMem (mTestPointStruct.FeaturesImplemented, mFeatureImplemented, sizeof(mFeatureImplemented)); + Status = TestPointLibSetTable ( + &mTestPointStruct, + sizeof(mTestPointStruct) + ); + if (EFI_ERROR (Status)) { + if (Status != EFI_ALREADY_STARTED) { + ASSERT_EFI_ERROR (Status); + } + } +} + +/** + The library constructor. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +DxeTestPointCheckLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + InitData (PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/GenoaBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h b/Platform/AMD/GenoaBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h new file mode 100644 index 0000000000000000000000000000000000000000..178ba1e3ce3adf425f199e94794cbaabb05905e2 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h @@ -0,0 +1,194 @@ +/** + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file + Definition for the USB mass storage Bulk-Only Transport protocol, + based on the "Universal Serial Bus Mass Storage Class Bulk-Only + Transport" Revision 1.0, September 31, 1999. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_USBMASS_BOT_H_ +#define _EFI_USBMASS_BOT_H_ + +extern USB_MASS_TRANSPORT mUsbBotTransport; + +// +// Usb Bulk-Only class specific request +// +#define USB_BOT_RESET_REQUEST 0xFF ///< Bulk-Only Mass Storage Reset +#define USB_BOT_GETLUN_REQUEST 0xFE ///< Get Max Lun +#define USB_BOT_CBW_SIGNATURE 0x43425355 ///< dCBWSignature, tag the packet as CBW +#define USB_BOT_CSW_SIGNATURE 0x53425355 ///< dCSWSignature, tag the packet as CSW +#define USB_BOT_MAX_LUN 0x0F ///< Lun number is from 0 to 15 +#define USB_BOT_MAX_CMDLEN 16 ///< Maximum number of command from command set + +// +// Usb BOT command block status values +// +#define USB_BOT_COMMAND_OK 0x00 ///< Command passed, good status +#define USB_BOT_COMMAND_FAILED 0x01 ///< Command failed +#define USB_BOT_COMMAND_ERROR 0x02 ///< Phase error, need to reset the device + +// +// Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times] +// +#define USB_BOT_RECV_CSW_RETRY 3 + +// +// Usb Bot wait device reset complete, set by experience +// +// AMD_EDKII_OVERRIDE START +#define USB_BOT_RESET_DEVICE_STALL (60 * USB_MASS_1_SECOND) +// AMD_EDKII_OVERRIDE END + +// +// Usb Bot transport timeout, set by experience +// +#define USB_BOT_SEND_CBW_TIMEOUT (3 * USB_MASS_1_SECOND) +#define USB_BOT_RECV_CSW_TIMEOUT (3 * USB_MASS_1_SECOND) +#define USB_BOT_RESET_DEVICE_TIMEOUT (3 * USB_MASS_1_SECOND) + +#pragma pack(1) +/// +/// The CBW (Command Block Wrapper) structures used by the USB BOT protocol. +/// +typedef struct { + UINT32 Signature; + UINT32 Tag; + UINT32 DataLen; ///< Length of data between CBW and CSW + UINT8 Flag; ///< Bit 7, 0 ~ Data-Out, 1 ~ Data-In + UINT8 Lun; ///< Lun number. Bits 0~3 are used + UINT8 CmdLen; ///< Length of the command. Bits 0~4 are used + UINT8 CmdBlock[USB_BOT_MAX_CMDLEN]; +} USB_BOT_CBW; + +/// +/// The and CSW (Command Status Wrapper) structures used by the USB BOT protocol. +/// +typedef struct { + UINT32 Signature; + UINT32 Tag; + UINT32 DataResidue; + UINT8 CmdStatus; +} USB_BOT_CSW; +#pragma pack() + +typedef struct { + // + // Put Interface at the first field to make it easy to distinguish BOT/CBI Protocol instance + // + EFI_USB_INTERFACE_DESCRIPTOR Interface; + EFI_USB_ENDPOINT_DESCRIPTOR *BulkInEndpoint; + EFI_USB_ENDPOINT_DESCRIPTOR *BulkOutEndpoint; + UINT32 CbwTag; + EFI_USB_IO_PROTOCOL *UsbIo; +} USB_BOT_PROTOCOL; + +/** + Initializes USB BOT protocol. + + This function initializes the USB mass storage class BOT protocol. + It will save its context which is a USB_BOT_PROTOCOL structure + in the Context if Context isn't NULL. + + @param UsbIo The USB I/O Protocol instance + @param Context The buffer to save the context to + + @retval EFI_SUCCESS The device is successfully initialized. + @retval EFI_UNSUPPORTED The transport protocol doesn't support the device. + @retval Other The USB BOT initialization fails. + +**/ +EFI_STATUS +UsbBotInit ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + OUT VOID **Context OPTIONAL + ); + +/** + Call the USB Mass Storage Class BOT protocol to issue + the command/data/status circle to execute the commands. + + @param Context The context of the BOT protocol, that is, + USB_BOT_PROTOCOL + @param Cmd The high level command + @param CmdLen The command length + @param DataDir The direction of the data transfer + @param Data The buffer to hold data + @param DataLen The length of the data + @param Lun The number of logic unit + @param Timeout The time to wait command + @param CmdStatus The result of high level command execution + + @retval EFI_SUCCESS The command is executed successfully. + @retval Other Failed to execute command + +**/ +EFI_STATUS +UsbBotExecCommand ( + IN VOID *Context, + IN VOID *Cmd, + IN UINT8 CmdLen, + IN EFI_USB_DATA_DIRECTION DataDir, + IN VOID *Data, + IN UINT32 DataLen, + IN UINT8 Lun, + IN UINT32 Timeout, + OUT UINT32 *CmdStatus + ); + +/** + Reset the USB mass storage device by BOT protocol. + + @param Context The context of the BOT protocol, that is, + USB_BOT_PROTOCOL. + @param ExtendedVerification If FALSE, just issue Bulk-Only Mass Storage Reset request. + If TRUE, additionally reset parent hub port. + + @retval EFI_SUCCESS The device is reset. + @retval Others Failed to reset the device.. + +**/ +EFI_STATUS +UsbBotResetDevice ( + IN VOID *Context, + IN BOOLEAN ExtendedVerification + ); + +/** + Get the max LUN (Logical Unit Number) of USB mass storage device. + + @param Context The context of the BOT protocol, that is, USB_BOT_PROTOCOL + @param MaxLun Return pointer to the max number of LUN. (e.g. MaxLun=1 means LUN0 and + LUN1 in all.) + + @retval EFI_SUCCESS Max LUN is got successfully. + @retval Others Fail to execute this request. + +**/ +EFI_STATUS +UsbBotGetMaxLun ( + IN VOID *Context, + OUT UINT8 *MaxLun + ); + +/** + Clean up the resource used by this BOT protocol. + + @param Context The context of the BOT protocol, that is, USB_BOT_PROTOCOL. + + @retval EFI_SUCCESS The resource is cleaned up. + +**/ +EFI_STATUS +UsbBotCleanUp ( + IN VOID *Context + ); + +#endif diff --git a/Platform/AMD/GenoaBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c b/Platform/AMD/GenoaBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c new file mode 100644 index 0000000000000000000000000000000000000000..05b531e78441b4231ec431e149803c2862ca6ddc --- /dev/null +++ b/Platform/AMD/GenoaBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c @@ -0,0 +1,1137 @@ +/** + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file + USB Mass Storage Driver that manages USB Mass Storage Device and produces Block I/O Protocol. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsbMass.h" + +#define USB_MASS_TRANSPORT_COUNT 3 +// +// Array of USB transport interfaces. +// +USB_MASS_TRANSPORT *mUsbMassTransport[USB_MASS_TRANSPORT_COUNT] = { + &mUsbCbi0Transport, + &mUsbCbi1Transport, + &mUsbBotTransport, +}; + +EFI_DRIVER_BINDING_PROTOCOL gUSBMassDriverBinding = { + USBMassDriverBindingSupported, + USBMassDriverBindingStart, + USBMassDriverBindingStop, + 0x11, + NULL, + NULL +}; + +/** + Reset the block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.Reset(). + It resets the block device hardware. + ExtendedVerification is ignored in this implementation. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Indicates that the driver may perform a more exhaustive + verification operation of the device during reset. + + @retval EFI_SUCCESS The block device was reset. + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset. + +**/ +EFI_STATUS +EFIAPI +UsbMassReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_TPL OldTpl; + EFI_STATUS Status; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Status = UsbMass->Transport->Reset (UsbMass->Context, ExtendedVerification); + + gBS->RestoreTPL (OldTpl); + + return Status; +} + +/** + Reads the requested number of blocks from the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks(). + It reads the requested number of blocks from the device. + All the blocks are read, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the read request is for. + @param Lba The starting logical block address to read from on the device. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +UsbMassReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN TotalBlock; + + // AMD_EDKII_OVERRIDE START + INT8 ResetRetryCount; + VOID *OriginalBuffer; + EFI_LBA OriginalLba; + UINTN OriginalBufferSize; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Media = &UsbMass->BlockIoMedia; + + ResetRetryCount = 3; + OriginalBuffer = Buffer; + OriginalBufferSize = BufferSize; + OriginalLba = Lba; + + while (ResetRetryCount >= 0) { + + Buffer = OriginalBuffer; + Lba = OriginalLba; + BufferSize = OriginalBufferSize; + + // + // If it is a removable media, such as CD-Rom or Usb-Floppy, + // need to detect the media before each read/write. While some of + // Usb-Flash is marked as removable media. + // + if (Media->RemovableMedia) { + Status = UsbBootDetectMedia (UsbMass); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + } + + if (!(Media->MediaPresent)) { + Status = EFI_NO_MEDIA; + goto ON_EXIT; + } + + if (MediaId != Media->MediaId) { + Status = EFI_MEDIA_CHANGED; + goto ON_EXIT; + } + + if (BufferSize == 0) { + Status = EFI_SUCCESS; + goto ON_EXIT; + } + + if (Buffer == NULL) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // BufferSize must be a multiple of the intrinsic block size of the device. + // + if ((BufferSize % Media->BlockSize) != 0) { + Status = EFI_BAD_BUFFER_SIZE; + goto ON_EXIT; + } + + TotalBlock = BufferSize / Media->BlockSize; + + // + // Make sure the range to read is valid. + // + if (Lba + TotalBlock - 1 > Media->LastBlock) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + if (UsbMass->Cdb16Byte) { + Status = UsbBootReadWriteBlocks16 (UsbMass, FALSE, Lba, TotalBlock, Buffer); + } else { + Status = UsbBootReadWriteBlocks (UsbMass, FALSE, (UINT32)Lba, TotalBlock, Buffer); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassReadBlocks: UsbBootReadBlocks (%r) -> Reset\n", Status)); + UsbMassReset (This, TRUE); + ResetRetryCount--; + } + else { + break; + } + } + // AMD_EDKII_OVERRIDE END +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Writes a specified number of blocks to the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks(). + It writes a specified number of blocks to the device. + All blocks are written, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer Pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data were written correctly to the device. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +UsbMassWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN TotalBlock; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Media = &UsbMass->BlockIoMedia; + + // + // If it is a removable media, such as CD-Rom or Usb-Floppy, + // need to detect the media before each read/write. Some of + // USB Flash is marked as removable media. + // + if (Media->RemovableMedia) { + Status = UsbBootDetectMedia (UsbMass); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + } + + if (!(Media->MediaPresent)) { + Status = EFI_NO_MEDIA; + goto ON_EXIT; + } + + if (MediaId != Media->MediaId) { + Status = EFI_MEDIA_CHANGED; + goto ON_EXIT; + } + + if (BufferSize == 0) { + Status = EFI_SUCCESS; + goto ON_EXIT; + } + + if (Buffer == NULL) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // BufferSize must be a multiple of the intrinsic block size of the device. + // + if ((BufferSize % Media->BlockSize) != 0) { + Status = EFI_BAD_BUFFER_SIZE; + goto ON_EXIT; + } + + TotalBlock = BufferSize / Media->BlockSize; + + // + // Make sure the range to write is valid. + // + if (Lba + TotalBlock - 1 > Media->LastBlock) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // Try to write the data even the device is marked as ReadOnly, + // and clear the status should the write succeed. + // + if (UsbMass->Cdb16Byte) { + Status = UsbBootReadWriteBlocks16 (UsbMass, TRUE, Lba, TotalBlock, Buffer); + } else { + Status = UsbBootReadWriteBlocks (UsbMass, TRUE, (UINT32)Lba, TotalBlock, Buffer); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassWriteBlocks: UsbBootWriteBlocks (%r) -> Reset\n", Status)); + UsbMassReset (This, TRUE); + } + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Flushes all modified data to a physical block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.FlushBlocks(). + USB mass storage device doesn't support write cache, + so return EFI_SUCCESS directly. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data were written correctly to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data. + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +EFI_STATUS +EFIAPI +UsbMassFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + + @param UsbMass The USB mass storage device + + @retval EFI_SUCCESS The media parameters are updated successfully. + @retval Others Failed to get the media parameters. + +**/ +EFI_STATUS +UsbMassInitMedia ( + IN USB_MASS_DEVICE *UsbMass + ) +{ + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + + Media = &UsbMass->BlockIoMedia; + + // + // Fields of EFI_BLOCK_IO_MEDIA are defined in UEFI 2.0 spec, + // section for Block I/O Protocol. + // + Media->MediaPresent = FALSE; + Media->LogicalPartition = FALSE; + Media->ReadOnly = FALSE; + Media->WriteCaching = FALSE; + Media->IoAlign = 0; + Media->MediaId = 1; + + Status = UsbBootGetParams (UsbMass); + DEBUG ((DEBUG_INFO, "UsbMassInitMedia: UsbBootGetParams (%r)\n", Status)); + if (Status == EFI_MEDIA_CHANGED) { + // + // Some USB storage devices may report MEDIA_CHANGED sense key when hot-plugged. + // Treat it as SUCCESS + // + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Initialize the USB Mass Storage transport. + + This function tries to find the matching USB Mass Storage transport + protocol for USB device. If found, initializes the matching transport. + + @param This The USB mass driver's driver binding. + @param Controller The device to test. + @param Transport The pointer to pointer to USB_MASS_TRANSPORT. + @param Context The parameter for USB_MASS_DEVICE.Context. + @param MaxLun Get the MaxLun if is BOT dev. + + @retval EFI_SUCCESS The initialization is successful. + @retval EFI_UNSUPPORTED No matching transport protocol is found. + @retval Others Failed to initialize dev. + +**/ +EFI_STATUS +UsbMassInitTransport ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + OUT USB_MASS_TRANSPORT **Transport, + OUT VOID **Context, + OUT UINT8 *MaxLun + ) +{ + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_INTERFACE_DESCRIPTOR Interface; + UINT8 Index; + EFI_STATUS Status; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + Status = EFI_UNSUPPORTED; + + // + // Traverse the USB_MASS_TRANSPORT arrary and try to find the + // matching transport protocol. + // If not found, return EFI_UNSUPPORTED. + // If found, execute USB_MASS_TRANSPORT.Init() to initialize the transport context. + // + for (Index = 0; Index < USB_MASS_TRANSPORT_COUNT; Index++) { + *Transport = mUsbMassTransport[Index]; + + if (Interface.InterfaceProtocol == (*Transport)->Protocol) { + Status = (*Transport)->Init (UsbIo, Context); + break; + } + } + + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + // + // For BOT device, try to get its max LUN. + // If max LUN is 0, then it is a non-lun device. + // Otherwise, it is a multi-lun device. + // + if ((*Transport)->Protocol == USB_MASS_STORE_BOT) { + (*Transport)->GetMaxLun (*Context, MaxLun); + } + +ON_EXIT: + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + return Status; +} + +/** + Initialize data for device that supports multiple LUNSs. + + @param This The Driver Binding Protocol instance. + @param Controller The device to initialize. + @param Transport Pointer to USB_MASS_TRANSPORT. + @param Context Parameter for USB_MASS_DEVICE.Context. + @param DevicePath The remaining device path. + @param MaxLun The max LUN number. + + @retval EFI_SUCCESS At least one LUN is initialized successfully. + @retval EFI_NOT_FOUND Fail to initialize any of multiple LUNs. + +**/ +EFI_STATUS +UsbMassInitMultiLun ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN USB_MASS_TRANSPORT *Transport, + IN VOID *Context, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN UINT8 MaxLun + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + DEVICE_LOGICAL_UNIT_DEVICE_PATH LunNode; + UINT8 Index; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + ASSERT (MaxLun > 0); + ReturnStatus = EFI_NOT_FOUND; + + for (Index = 0; Index <= MaxLun; Index++) { + DEBUG ((DEBUG_INFO, "UsbMassInitMultiLun: Start to initialize No.%d logic unit\n", Index)); + + UsbIo = NULL; + UsbMass = AllocateZeroPool (sizeof (USB_MASS_DEVICE)); + ASSERT (UsbMass != NULL); + + UsbMass->Signature = USB_MASS_SIGNATURE; + UsbMass->UsbIo = UsbIo; + UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; + UsbMass->BlockIo.Reset = UsbMassReset; + UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; + UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; + UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; + UsbMass->OpticalStorage = FALSE; + UsbMass->Transport = Transport; + UsbMass->Context = Context; + UsbMass->Lun = Index; + + // + // Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + // + Status = UsbMassInitMedia (UsbMass); + if ((EFI_ERROR (Status)) && (Status != EFI_NO_MEDIA)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: UsbMassInitMedia (%r)\n", Status)); + FreePool (UsbMass); + continue; + } + + // + // Create a device path node for device logic unit, and append it. + // + LunNode.Header.Type = MESSAGING_DEVICE_PATH; + LunNode.Header.SubType = MSG_DEVICE_LOGICAL_UNIT_DP; + LunNode.Lun = UsbMass->Lun; + + SetDevicePathNodeLength (&LunNode.Header, sizeof (LunNode)); + + UsbMass->DevicePath = AppendDevicePathNode (DevicePath, &LunNode.Header); + + if (UsbMass->DevicePath == NULL) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: failed to create device logic unit device path\n")); + Status = EFI_OUT_OF_RESOURCES; + FreePool (UsbMass); + continue; + } + + InitializeDiskInfo (UsbMass); + + // + // Create a new handle for each LUN, and install Block I/O Protocol and Device Path Protocol. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &UsbMass->Controller, + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: InstallMultipleProtocolInterfaces (%r)\n", Status)); + FreePool (UsbMass->DevicePath); + FreePool (UsbMass); + continue; + } + + // + // Open USB I/O Protocol by child to setup a parent-child relationship. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + UsbMass->Controller, + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: OpenUsbIoProtocol By Child (%r)\n", Status)); + gBS->UninstallMultipleProtocolInterfaces ( + UsbMass->Controller, + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + FreePool (UsbMass->DevicePath); + FreePool (UsbMass); + continue; + } + + ReturnStatus = EFI_SUCCESS; + DEBUG ((DEBUG_INFO, "UsbMassInitMultiLun: Success to initialize No.%d logic unit\n", Index)); + } + + return ReturnStatus; +} + +/** + Initialize data for device that does not support multiple LUNSs. + + @param This The Driver Binding Protocol instance. + @param Controller The device to initialize. + @param Transport Pointer to USB_MASS_TRANSPORT. + @param Context Parameter for USB_MASS_DEVICE.Context. + + @retval EFI_SUCCESS Initialization succeeds. + @retval Other Initialization fails. + +**/ +EFI_STATUS +UsbMassInitNonLun ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN USB_MASS_TRANSPORT *Transport, + IN VOID *Context + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_STATUS Status; + + UsbIo = NULL; + UsbMass = AllocateZeroPool (sizeof (USB_MASS_DEVICE)); + ASSERT (UsbMass != NULL); + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitNonLun: OpenUsbIoProtocol By Driver (%r)\n", Status)); + goto ON_ERROR; + } + + UsbMass->Signature = USB_MASS_SIGNATURE; + UsbMass->Controller = Controller; + UsbMass->UsbIo = UsbIo; + UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; + UsbMass->BlockIo.Reset = UsbMassReset; + UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; + UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; + UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; + UsbMass->OpticalStorage = FALSE; + UsbMass->Transport = Transport; + UsbMass->Context = Context; + + // + // Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + // + Status = UsbMassInitMedia (UsbMass); + if ((EFI_ERROR (Status)) && (Status != EFI_NO_MEDIA)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitNonLun: UsbMassInitMedia (%r)\n", Status)); + goto ON_ERROR; + } + + InitializeDiskInfo (UsbMass); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Controller, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + return EFI_SUCCESS; + +ON_ERROR: + if (UsbMass != NULL) { + FreePool (UsbMass); + } + + if (UsbIo != NULL) { + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + return Status; +} + +/** + Check whether the controller is a supported USB mass storage. + + @param This The USB mass storage driver binding protocol. + @param Controller The controller handle to check. + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS The driver supports this controller. + @retval other This device isn't supported. + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_INTERFACE_DESCRIPTOR Interface; + USB_MASS_TRANSPORT *Transport; + EFI_STATUS Status; + UINTN Index; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Get the interface descriptor to check the USB class and find a transport + // protocol handler. + // + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + Status = EFI_UNSUPPORTED; + + if (Interface.InterfaceClass != USB_MASS_STORE_CLASS) { + goto ON_EXIT; + } + + // + // Traverse the USB_MASS_TRANSPORT arrary and try to find the + // matching transport method. + // If not found, return EFI_UNSUPPORTED. + // If found, execute USB_MASS_TRANSPORT.Init() to initialize the transport context. + // + for (Index = 0; Index < USB_MASS_TRANSPORT_COUNT; Index++) { + Transport = mUsbMassTransport[Index]; + if (Interface.InterfaceProtocol == Transport->Protocol) { + Status = Transport->Init (UsbIo, NULL); + break; + } + } + +ON_EXIT: + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + return Status; +} + +/** + Starts the USB mass storage device with this driver. + + This function consumes USB I/O Protocol, initializes USB mass storage device, + installs Block I/O Protocol, and submits Asynchronous Interrupt + Transfer to manage the USB mass storage device. + + @param This The USB mass storage driver binding protocol. + @param Controller The USB mass storage device to start on + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS This driver supports this device. + @retval EFI_UNSUPPORTED This driver does not support this device. + @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error. + @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources. + @retval EFI_ALREADY_STARTED This driver has been started. + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + USB_MASS_TRANSPORT *Transport; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + VOID *Context; + UINT8 MaxLun; + EFI_STATUS Status; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_TPL OldTpl; + + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + Transport = NULL; + Context = NULL; + MaxLun = 0; + + Status = UsbMassInitTransport (This, Controller, &Transport, &Context, &MaxLun); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitTransport (%r)\n", Status)); + goto Exit; + } + + if (MaxLun == 0) { + // + // Initialize data for device that does not support multiple LUNSs. + // + Status = UsbMassInitNonLun (This, Controller, Transport, Context); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitNonLun (%r)\n", Status)); + } + } else { + // + // Open device path to prepare for appending Device Logic Unit node. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID **)&DevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: OpenDevicePathProtocol By Driver (%r)\n", Status)); + goto Exit; + } + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: OpenUsbIoProtocol By Driver (%r)\n", Status)); + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + goto Exit; + } + + // + // Initialize data for device that supports multiple LUNs. + // EFI_SUCCESS is returned if at least 1 LUN is initialized successfully. + // + Status = UsbMassInitMultiLun (This, Controller, Transport, Context, DevicePath, MaxLun); + if (EFI_ERROR (Status)) { + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitMultiLun (%r) with Maxlun=%d\n", Status, MaxLun)); + } + } + +Exit: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Stop controlling the device. + + @param This The USB mass storage driver binding + @param Controller The device controller controlled by the driver. + @param NumberOfChildren The number of children of this device + @param ChildHandleBuffer The buffer of children handle. + + @retval EFI_SUCCESS The driver stopped from controlling the device. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error. + @retval EFI_UNSUPPORTED Block I/O Protocol is not installed on Controller. + @retval Others Failed to stop the driver + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status; + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_BLOCK_IO_PROTOCOL *BlockIo; + UINTN Index; + BOOLEAN AllChildrenStopped; + + // + // This is a bus driver stop function since multi-lun is supported. + // There are three kinds of device handles that might be passed: + // 1st is a handle with USB I/O & Block I/O installed (non-multi-lun) + // 2nd is a handle with Device Path & USB I/O installed (multi-lun root) + // 3rd is a handle with Device Path & USB I/O & Block I/O installed (multi-lun). + // + if (NumberOfChildren == 0) { + // + // A handle without any children, might be 1st and 2nd type. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiBlockIoProtocolGuid, + (VOID **)&BlockIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + // + // This is a 2nd type handle(multi-lun root), it needs to close devicepath + // and usbio protocol. + // + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + DEBUG ((DEBUG_INFO, "Success to stop multi-lun root handle\n")); + return EFI_SUCCESS; + } + + // + // This is a 1st type handle(non-multi-lun), which only needs to uninstall + // Block I/O Protocol, close USB I/O Protocol and free mass device. + // + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (BlockIo); + + // + // Uninstall Block I/O protocol from the device handle, + // then call the transport protocol to stop itself. + // + Status = gBS->UninstallMultipleProtocolInterfaces ( + Controller, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + UsbMass->Transport->CleanUp (UsbMass->Context); + FreePool (UsbMass); + + DEBUG ((DEBUG_INFO, "Success to stop non-multi-lun root handle\n")); + return EFI_SUCCESS; + } + + // + // This is a 3rd type handle(multi-lun), which needs uninstall + // Block I/O Protocol and Device Path Protocol, close USB I/O Protocol and + // free mass device for all children. + // + AllChildrenStopped = TRUE; + + for (Index = 0; Index < NumberOfChildren; Index++) { + Status = gBS->OpenProtocol ( + ChildHandleBuffer[Index], + &gEfiBlockIoProtocolGuid, + (VOID **)&BlockIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + AllChildrenStopped = FALSE; + DEBUG ((DEBUG_ERROR, "Fail to stop No.%d multi-lun child handle when opening blockio\n", (UINT32)Index)); + continue; + } + + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (BlockIo); + + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + ChildHandleBuffer[Index] + ); + + Status = gBS->UninstallMultipleProtocolInterfaces ( + ChildHandleBuffer[Index], + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + + if (EFI_ERROR (Status)) { + // + // Fail to uninstall Block I/O Protocol and Device Path Protocol, so re-open USB I/O Protocol by child. + // + AllChildrenStopped = FALSE; + DEBUG ((DEBUG_ERROR, "Fail to stop No.%d multi-lun child handle when uninstalling blockio and devicepath\n", (UINT32)Index)); + + gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + ChildHandleBuffer[Index], + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER + ); + } else { + // + // Succeed to stop this multi-lun handle, so go on with next child. + // + if (((Index + 1) == NumberOfChildren) && AllChildrenStopped) { + UsbMass->Transport->CleanUp (UsbMass->Context); + } + + FreePool (UsbMass); + } + } + + if (!AllChildrenStopped) { + return EFI_DEVICE_ERROR; + } + + DEBUG ((DEBUG_INFO, "Success to stop all %d multi-lun children handles\n", (UINT32)NumberOfChildren)); + return EFI_SUCCESS; +} + +/** + Entrypoint of USB Mass Storage Driver. + + This function is the entrypoint of USB Mass Storage Driver. It installs Driver Binding + Protocol together with Component Name Protocols. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +USBMassStorageEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Install driver binding protocol + // + Status = EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gUSBMassDriverBinding, + ImageHandle, + &gUsbMassStorageComponentName, + &gUsbMassStorageComponentName2 + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/GenoaBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf b/Platform/AMD/GenoaBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..425fec22ede0758017fbd84b90bdf4d191545ef4 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf @@ -0,0 +1,43 @@ +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# + +## @file +# Instance of PCI Express Library using the 256 MB PCI Express MMIO window. +# +# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform +# PCI Configuration cycles. Layers on top of an I/O Library instance. +# +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved. +# Portions copyright (c) 2016, American Megatrends, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmPciExpressLib + FILE_GUID = 00D24382-8231-4B18-A4F0-2D94D8FE2E81 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciExpressLib|DXE_SMM_DRIVER SMM_CORE + CONSTRUCTOR = SmmPciExpressLibConstructor + +[Sources] + PciExpressLib.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + PcdLib + DebugLib + IoLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..b777851fd2b8fde662f12f7c6e9d2ca53b340525 --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,244 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.IntDesignatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.ExtDesignatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.IntDesignatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.ExtDesignatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.IntDesignatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.ExtDesignatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.IntDesignatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/QuartzBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..998fc7353fad14f38485916534a96911cf01521e --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/Project.dsc @@ -0,0 +1,187 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Quartz +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 41f5897a-7076-11eb-9439-0242ac130002 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "QUARTZ " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20205A5452415551 # "QUARTZ " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|256 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|1 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|2 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|8 + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc + diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/QuartzBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..40bdb0043da878576921bb3170fd0e0cf75831ec --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/Project.fdf @@ -0,0 +1,37 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..cb5bd8cb7e57cfdd997da79667836e585857d788 --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,146 @@ +{ + "rs1qi": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qi_simnow": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "INTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qe": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qe_simnow": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "EXTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qis": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qis_simnow": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "INTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qes": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qes_simnow": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "EXTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1qe_nocbs": { + "platform": "QuartzBoardPkg", + "sku": "1Q", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Quartz", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..d1e24c2ef8017feb0c6d6993a0219a3531feb218 --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..f0e53ca15b917fdb683a086aaba7b71bc36aac47 --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Quartz QuartzRevA QuartzFR4' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..e0e05c9d74b021bdc8c1d83e9bbf3682392448b2 --- /dev/null +++ b/Platform/AMD/GenoaBoard/QuartzBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..c9c2c4ae21117aaf33162df5eb71d4eb0604bdd6 --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +#;***************************************************************************** +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"Default String" + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|{0} + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("4462C5BB-B061-4771-85D3-674849AB82E0")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"Default String" + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"Default String" + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"Default String" + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"Default String"} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"Default String"} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/RubyBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..77a3cef8bcd0686aaad09a54d7a4ee6d9771aa3a --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/Project.dsc @@ -0,0 +1,178 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Ruby +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = f9d2b0a3-f7a1-40db-b9c1-27c403d3a35d + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "RUBY " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020202059425552 # "RUBY " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|256 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|2 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|4 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/RubyBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..d81028ae5926d3ae7bb391375fcb32911de25aec --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/Project.fdf @@ -0,0 +1,37 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..156acbf2fbdb19ac92177e965225cdc8781278c4 --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,82 @@ +{ + "rs1ri": { + "platform": "RubyBoardPkg", + "sku": "1R", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Ruby", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1re": { + "platform": "RubyBoardPkg", + "sku": "1R", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Ruby", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1ris": { + "platform": "RubyBoardPkg", + "sku": "1R", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Ruby", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1res": { + "platform": "RubyBoardPkg", + "sku": "1R", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Ruby", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1re_nocbs": { + "platform": "RubyBoardPkg", + "sku": "1R", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Ruby", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..d1e24c2ef8017feb0c6d6993a0219a3531feb218 --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..80e09c18be110fb33ed83f35e0619e549ee9f432 --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Ruby' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/RubyBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..e0e05c9d74b021bdc8c1d83e9bbf3682392448b2 --- /dev/null +++ b/Platform/AMD/GenoaBoard/RubyBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..ea0e18fcf161ba7a0e25ff26cfc205182183d3d1 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf + !endif diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..aaf598d5ec7e510ff8a4f9c5b35dc94c34d50c16 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# CRB specific - External AGESA build. +# +## + # + # AMD AGESA Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.inc.dsc + !endif diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..1c410d4c93bbb2061c8446d7be5eaecba022c254 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf + !endif diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..1b35faccba0e6824567727af8459803ec1110867 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf @@ -0,0 +1,15 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.dxe.inc.fdf diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..d1b1fd9a09abaa1622c546fe355560a7a6cc27dc --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# CRB specific - Internal AGESA build. +# +## + # + # AMD AGESA Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !include AgesaModulePkg/AgesaIdsIntRs.inc.dsc + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.inc.dsc diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..959d51899b06aa9ca4c481bcdd2742019526996e --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf @@ -0,0 +1,15 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.pei.inc.fdf diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..d74dd51264464406f3671b683aedf961c02fda0b --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"Default String" + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("C3C04B5F-F675-470E-88B8-41760472D8C7")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"Default String" + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"Default String" + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"Default String" + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"Default String"} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"Default String"} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000000000000000000000000000000000..fde5f9d003b772d18c97a7cd100c15929ce873ee --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,159 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# GenoaShale reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +############################################################################## +# +# BIOS image layout +# +############################################################################## +# +===============================+ +# |Flash Device (FD) | +# |BaseAddress = 0xFF000000 | +# | ONLY 0xFF000000-0xFFFFFFFF | +# | Visible in MMIO < 4GB | +# |Size = 0x02000000 (32MB)| +# +===============================+ + DEFINE ROM2_FLASH_BASE = 0xFF000000 + DEFINE ROM2_FLASH_SIZE = 0x01000000 + DEFINE ROM3_FLASH_BASE = 0xFD02000000 + DEFINE ROM3_FLASH_SIZE = 0x02000000 + DEFINE SPI_BLOCK_SIZE = 0x1000 + DEFINE SPI_NUM_BLOCKS = 0x2000 + DEFINE ROM3_FLASH_ENABLE = TRUE +# +===============================+ +# Section FD Offset SPI Addr. RAM Addr +# +===============================+ 0x00000000 0xFF000000 +# |Unused Size=0x20000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0001FFFF 0xFF01FFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00020000 0xFF020000 +# |Embedded FW Sig Size=0x1000 | + DEFINE FV_FW_SIG_OFFSET = 0x00020000 + DEFINE FV_FW_SIG_SIZE = 0x00001000 +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00020FFF 0xFF020FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00021000 0xFF021000 +# |Unused Size=0x16000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00036FFF 0xFF036FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00037000 0xFF037000 +# |UEFI NVRAM Size=0x20000| + DEFINE NVRAM_AREA_VAR_OFFSET = 0x00037000 + DEFINE NVRAM_AREA_VAR_SIZE = 0x0000E000 + DEFINE NVRAM_AREA_SIZE = 0x00020000 + + DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE) + DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE) + + DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE) +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00056FFF 0xFF056FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00057000 0xFF057000 +# |Unused Size=0xb000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00061FFF 0xFF061FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00062000 0xFF062000 +# |PSP Dir1 Size=0x200000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x002C5FFF 0xFF2C5FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x002C6000 0xFF2C6000 +# |BIOS Dir1 Size=0x40000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00306FFF 0xFF306FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00307000 0xFF307000 +# |PSP Dir2 Size=0x234000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0053AFFF 0xFF53AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0053B000 0xFF53B000 +# |BIOS Dir2 Size=0x100000 | +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0063AFFF 0xFF63AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0063B000 0xFF63B000 +# |FV.FvAdvanced Size=0x90000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x006CAFFF 0xFF6CAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x006CB000 0xFF6CB000 +# |FV.FvAdvancedSecurity 0x40000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0070AFFF 0xFF70AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0070B000 0xFF70B000 +# |FV. FvOsBoot Size=0x100000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0080AFFF 0xFF80AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0080B000 0xFF80B000 +# |FV.FvUefiBoot Size=0x2C0000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00ACAFFF 0xFFACAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00ACB000 0xFFCAB000 +# |FV.FvSecurity Size=0x010000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00ADAFFF 0xFFADAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00ADB000 0xFFADB000 +# |FV.FvPostMemory Size=0x040000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00B1AFFF 0xFFB1AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00B1B000 0xFFB1B000 +# |FV.FvAdvancedPreMemory 0x1E5000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00CFFFFF 0xFFCFFFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00D00000 0xFFD00000 0x76D00000 +# |FV.FvPreMemory Size=0x300000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00FFFFFF 0xFFFFFFFF 0x76FFFFFF + DEFINE BOOT_FV_BASE = 0x76D00000 +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x01000000 +# |Unused Size=0x00100000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x010FFFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x01100000 +# |Unused Size=0x00F00000| +# +===============================+ 0x01FFFFFF + +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF800000 +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE) + +# FV offset and size assignment +# FvSecurity +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00ACB000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00010000 +# FvPostMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00040000 +# FvAdvancedPreMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x001E5000 +# FvPreMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00300000 + +# FvAdvanced +!if $(ROM3_FLASH_ENABLE) == TRUE + # if ROM3 is enabled then continue the offset update + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize) +!else + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x0063B000 +!endif +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00090000 +# FvAdvancedSecurity +SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) +SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = 0x00040000 +# FvOsBoot +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00100000 +# FvUefiBoot +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x002C0000 + +SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE) + +!if $(ROM3_FLASH_ENABLE) == TRUE + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +!endif diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..38414c160d373ce313820bd42c9d65f6bd6c6163 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Project.dsc @@ -0,0 +1,177 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Shale +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 0b5350f0-7076-11eb-9439-0242ac130002 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "SHALE " + + DEFINE SATA_OVERRIDE = FALSE + +!ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE +!else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE +!endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + + # Add platform includes AGESA, CPM etc + !include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + + # Board specific SMBIOS defines + !include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs + !include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x202020454C414853 # "SHALE " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|192 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|1 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|2 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|8 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..d81028ae5926d3ae7bb391375fcb32911de25aec --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/Project.fdf @@ -0,0 +1,37 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/PspDataRs.xml b/Platform/AMD/GenoaBoard/ShaleBoardPkg/PspDataRs.xml new file mode 100644 index 0000000000000000000000000000000000000000..58cde3c4e20175cb7e9968adced02bed81dbadb6 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/PspDataRs.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/PspDataRs_unencrypted.xml b/Platform/AMD/GenoaBoard/ShaleBoardPkg/PspDataRs_unencrypted.xml new file mode 100644 index 0000000000000000000000000000000000000000..f0777198330ccd2d029929522bb2b97222b24443 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/PspDataRs_unencrypted.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..1501feaf38f3febb02788fd9f2132f6e81d6e8c3 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,146 @@ +{ + "rs6hi": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6hi_simnow": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "INTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6he": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6he_simnow": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "EXTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6his": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6his_simnow": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "INTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6hes": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6hes_simnow": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "EXTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6he_nocbs": { + "platform": "ShaleBoardPkg", + "sku": "6H", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Shale", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..cc861d8ae79e7177d7fae6df342f7a7090ac2aac --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..1e7db19a67f1536e05d6a971b92ecef1aae210c1 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP6") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Shale' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..b9755ad915067be51b60d9bb7cbc2a9f4999dcf5 --- /dev/null +++ b/Platform/AMD/GenoaBoard/ShaleBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP6") diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..946eb983a6a674a681aefbc3d8011e0f2b53786a --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.dxe.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.dxe.inc.fdf + !endif \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..aaf598d5ec7e510ff8a4f9c5b35dc94c34d50c16 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.inc.dsc @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# CRB specific - External AGESA build. +# +## + # + # AMD AGESA Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.inc.dsc + !endif diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..1c410d4c93bbb2061c8446d7be5eaecba022c254 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaExt.pei.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - External + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !include AmdCbsPkg/Library/Family/0x19/RS/External/CbsStones.pei.inc.fdf + !endif diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..1b35faccba0e6824567727af8459803ec1110867 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.dxe.inc.fdf @@ -0,0 +1,15 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.dxe.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.dxe.inc.fdf diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..d1b1fd9a09abaa1622c546fe355560a7a6cc27dc --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.inc.dsc @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# CRB specific - Internal AGESA build. +# +## + # + # AMD AGESA Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.inc.dsc + !include AgesaModulePkg/AgesaIdsIntRs.inc.dsc + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.inc.dsc diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..959d51899b06aa9ca4c481bcdd2742019526996e --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/AgesaInc/AgesaInt.pei.inc.fdf @@ -0,0 +1,15 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - Internal + # + !include AgesaModulePkg/AgesaSp5RsModulePkg.pei.inc.fdf + !include AmdCbsPkg/Library/Family/0x19/RS/Internal/CbsStones.pei.inc.fdf diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..acececcf56c4c38bc09ae5053b8c42bdff6d287b --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"Default String" + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|{0} + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("B588BA40-ADBD-4D68-A4B1-B850515E0B20")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"Default String" + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"Default String" + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"Default String" + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"Default String"} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"Default String"} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000000000000000000000000000000000..ef62d45f44e88575435fb9902839939b7236d907 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,159 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# GenoaSunstone reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +############################################################################## +# +# BIOS image layout +# +############################################################################## +# +===============================+ +# |Flash Device (FD) | +# |BaseAddress = 0xFF000000 | +# | ONLY 0xFF000000-0xFFFFFFFF | +# | Visible in MMIO < 4GB | +# |Size = 0x02000000 (32MB)| +# +===============================+ + DEFINE ROM2_FLASH_BASE = 0xFF000000 + DEFINE ROM2_FLASH_SIZE = 0x01000000 + DEFINE ROM3_FLASH_BASE = 0xFD02000000 + DEFINE ROM3_FLASH_SIZE = 0x02000000 + DEFINE SPI_BLOCK_SIZE = 0x1000 + DEFINE SPI_NUM_BLOCKS = 0x2000 + DEFINE ROM3_FLASH_ENABLE = TRUE +# +===============================+ +# Section FD Offset SPI Addr. RAM Addr +# +===============================+ 0x00000000 0xFF000000 +# |Unused Size=0x20000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0001FFFF 0xFF01FFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00020000 0xFF020000 +# |Embedded FW Sig Size=0x1000 | + DEFINE FV_FW_SIG_OFFSET = 0x00020000 + DEFINE FV_FW_SIG_SIZE = 0x00001000 +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00020FFF 0xFF020FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00021000 0xFF021000 +# |Unused Size=0x16000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00036FFF 0xFF036FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00037000 0xFF037000 +# |UEFI NVRAM Size=0x20000| + DEFINE NVRAM_AREA_VAR_OFFSET = 0x00037000 + DEFINE NVRAM_AREA_VAR_SIZE = 0x0000E000 + DEFINE NVRAM_AREA_SIZE = 0x00020000 + + DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE) + DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE) + + DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE) +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00056FFF 0xFF056FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00057000 0xFF057000 +# |Unused Size=0xb000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00061FFF 0xFF061FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00062000 0xFF062000 +# |PSP Dir1 Size=0x200000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x002C5FFF 0xFF2C5FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x002C6000 0xFF2C6000 +# |BIOS Dir1 Size=0x40000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00306FFF 0xFF306FFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00307000 0xFF307000 +# |PSP Dir2 Size=0x234000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0053AFFF 0xFF53AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0053B000 0xFF53B000 +# |BIOS Dir2 Size=0x100000 | +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0063AFFF 0xFF63AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0063B000 0xFF63B000 +# |FV.FvAdvanced Size=0x90000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x006CAFFF 0xFF6CAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x006CB000 0xFF6CB000 +# |FV.FvAdvancedSecurity 0x40000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0070AFFF 0xFF70AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0070B000 0xFF70B000 +# |FV. FvOsBoot Size=0x100000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x0080AFFF 0xFF80AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x0080B000 0xFF80B000 +# |FV.FvUefiBoot Size=0x2C0000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00ACAFFF 0xFFACAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00ACB000 0xFFCAB000 +# |FV.FvSecurity Size=0x010000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00ADAFFF 0xFFADAFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00ADB000 0xFFADB000 +# |FV.FvPostMemory Size=0x040000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00B1AFFF 0xFFB1AFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00B1B000 0xFFB1B000 +# |FV.FvAdvancedPreMemory 0x1E5000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00CFFFFF 0xFFCFFFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x00D00000 0xFFD00000 0x76D00000 +# |FV.FvPreMemory Size=0x300000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x00FFFFFF 0xFFFFFFFF 0x76FFFFFF + DEFINE BOOT_FV_BASE = 0x76D00000 +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x01000000 +# |Unused Size=0x00100000| +# |^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^| 0x010FFFFF +# |vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv| 0x01100000 +# |Unused Size=0x00F00000| +# +===============================+ 0x01FFFFFF + +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF800000 +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE) + +# FV offset and size assignment +# FvSecurity +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00ACB000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00010000 +# FvPostMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00040000 +# FvAdvancedPreMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x001E5000 +# FvPreMemory +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00300000 + +# FvAdvanced +!if $(ROM3_FLASH_ENABLE) == TRUE + # if ROM3 is enabled then continue the offset update + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize) +!else + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x0063B000 +!endif +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00090000 +# FvAdvancedSecurity +SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) +SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = 0x00040000 +# FvOsBoot +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00100000 +# FvUefiBoot +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x002C0000 + +SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE) + +!if $(ROM3_FLASH_ENABLE) == TRUE + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +!endif diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..89299cdb3e51d11212b8c209f2fce552eeb8408d --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Project.dsc @@ -0,0 +1,175 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Sunstone +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 12DE9B28-76BE-454C-A337-297ECCB359B7 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "SUNSTONE" + + DEFINE SATA_OVERRIDE = FALSE + +!ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE +!else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE +!endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + + # Add platform includes AGESA, CPM etc + !include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + + # Board specific SMBIOS defines + !include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs + !include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x454E4F54534E5553 # "SUNSTONE" + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|96 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|192 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|2 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|1 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..d81028ae5926d3ae7bb391375fcb32911de25aec --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/Project.fdf @@ -0,0 +1,37 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/PspDataRs.xml b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/PspDataRs.xml new file mode 100644 index 0000000000000000000000000000000000000000..58cde3c4e20175cb7e9968adced02bed81dbadb6 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/PspDataRs.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/PspDataRs_unencrypted.xml b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/PspDataRs_unencrypted.xml new file mode 100644 index 0000000000000000000000000000000000000000..f0777198330ccd2d029929522bb2b97222b24443 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/PspDataRs_unencrypted.xml @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..9fefe5a108f6a203950b4a8eb497f4c900e187c4 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,146 @@ +{ + "rs6si": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6si_simnow": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "INTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6se": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6se_simnow": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "EXTERNAL", + "secure": "False", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6sis": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6sis_simnow": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "INTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6ses": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6ses_simnow": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "EXTERNAL", + "secure": "True", + "simnow": "True", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs6se_nocbs": { + "platform": "SunstoneBoardPkg", + "sku": "6S", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP6", + "board": "Sunstone", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} \ No newline at end of file diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..cc861d8ae79e7177d7fae6df342f7a7090ac2aac --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..708dd6e07320aa922388d10f9f019a49142643e4 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP6") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Sunstone' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..b9755ad915067be51b60d9bb7cbc2a9f4999dcf5 --- /dev/null +++ b/Platform/AMD/GenoaBoard/SunstoneBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP6") diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..00f1bf53936d05fe187d8e16924ee57dd34b3539 --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,171 @@ +#;***************************************************************************** +#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"Default String" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"Default String" + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|6 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J110" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J111" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J44" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J44" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J106" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"LAN" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|{0} + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("8dc4291c-f3ca-4858-8c53-6adc6713eb34")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"Default String" + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"Default String" + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"Default String" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"Default String" + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"Default String"} + + # SMBIOS Type 12 System Configuration Information + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"Default String"} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Project.dsc b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..baa916bf7209af65093291e302dba40df2bbe03f --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Project.dsc @@ -0,0 +1,179 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Genoa +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Titanite +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 7742fee3-af4d-4e51-8cce-993ca910de54 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "TITANITE" + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = FALSE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + # Console settings + # + # Background info: + # As per PPR vol7 17.4.10 UART Registers + # There are 4 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs + !include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"A0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"A1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4554494E41544954 # "TITANITE" + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|256 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|2 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxSocketSupportedV2|2 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|8 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Project.fdf b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..73dd53e45de85765214340186721527fa5d44447 --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/Project.fdf @@ -0,0 +1,37 @@ +#;***************************************************************************** +#; Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights reserved. +#; SPDX-License-Identifier: BSD-2-Clause-Patent +#; +#;***************************************************************************** + + +############################################################################## +# +# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0xFF + DEFINE EFS_ESPI_BYTE1 = 0x0E + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/SupportedBuilds.json b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/SupportedBuilds.json new file mode 100644 index 0000000000000000000000000000000000000000..86422da9b3725f361f22457f33c4f58be7fab215 --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/SupportedBuilds.json @@ -0,0 +1,82 @@ +{ + "rs1ti": { + "platform": "TitaniteBoardPkg", + "sku": "1T", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Titanite", + "build": "INTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1te": { + "platform": "TitaniteBoardPkg", + "sku": "1T", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Titanite", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1tis": { + "platform": "TitaniteBoardPkg", + "sku": "1T", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Titanite", + "build": "INTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1tes": { + "platform": "TitaniteBoardPkg", + "sku": "1T", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Titanite", + "build": "EXTERNAL", + "secure": "True", + "simnow": "False", + "emulation": "False", + "cbs": "True", + "dir": "GenoaOpenBoardPkg" + }, + "rs1te_nocbs": { + "platform": "TitaniteBoardPkg", + "sku": "1T", + "soc": "Genoa", + "soc2": "STONES", + "soc_family": "0x19", + "soc_sku": "RS", + "socket": "SP5", + "board": "Titanite", + "build": "EXTERNAL", + "secure": "False", + "simnow": "False", + "emulation": "False", + "cbs": "False", + "dir": "GenoaOpenBoardPkg" + } +} diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/__init__.py b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..cc861d8ae79e7177d7fae6df342f7a7090ac2aac --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/__init__.py @@ -0,0 +1,7 @@ +""" +******************************************************************************* + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/projectpostbuild.py b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/projectpostbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..f437a00b408e7c374db4a1492fbeaea02d58762e --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/projectpostbuild.py @@ -0,0 +1,31 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectpostbuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") + + workspace = os.environ['WORKSPACE'] + build_output = os.environ['BUILD_OUTPUT'] + + os.environ['APCB_TOOL_TEMP_PATH'] = os.path.normpath(os.path.join( + workspace, + 'AGESA/AgesaPkg/Addendum/Apcb/GenoaSp5Rdimm' + )) + os.environ['APCB_MULTI_BOARD_SUPPORT'] = '1' + os.environ['APCB_DATA_BOARD_DIR_LIST'] = 'GenoaCommon Titanite Titanite2P2G TitaniteRevC' + os.environ['CUSTOM_APCB_PATH'] = os.path.normpath(os.path.join( + build_output, + 'Apcb' + )) diff --git a/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/projectprebuild.py b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/projectprebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..e0e05c9d74b021bdc8c1d83e9bbf3682392448b2 --- /dev/null +++ b/Platform/AMD/GenoaBoard/TitaniteBoardPkg/support/projectprebuild.py @@ -0,0 +1,17 @@ +""" +******************************************************************************* + Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +******************************************************************************* +""" + +import os + +def projectprebuild(): + # These will be set elsewhere with dbuild.py and can be removed when it + # replaces dbuild.cmd + os.environ["SOC_FAMILY"] = os.environ.get("SOC_FAMILY", "0x19") + os.environ["SOC_SKU"] = os.environ.get("SOC_SKU", "RS") + os.environ["SOC2"] = os.environ.get("SOC2", "STONES") + os.environ["SOCKET"] = os.environ.get("SOCKET", "SP5") diff --git a/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..bed1d745486b5813becc76fba1d35f79ef40b322 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,235 @@ +/** + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file + This file implements BoardAcpiDxe driver. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param[in] Protocol The protocol to find. + @param[in] FfsGuid The FFS that contains the ACPI table. + @param[out] Instance Return pointer to the first instance of the protocol. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. +**/ +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + IN EFI_GUID *FfsGuid, + OUT VOID **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Size = 0; + FvStatus = 0; + Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *)(*Instance))->ReadFile ( + *Instance, + FfsGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + FreePool (HandleBuffer); + + return Status; +} + +/** + Publish ACPI table from FV. + + @param[in] FfsGuid The FFS that contains the ACPI table. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +PublishAcpiTablesFromFv ( + IN EFI_GUID *FfsGuid + ) +{ + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINT32 FvStatus; + UINTN Size; + UINTN TableHandle; + INTN Instance; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_ACPI_TABLE_VERSION Version; + + Instance = 0; + TableHandle = 0; + CurrentTable = NULL; + FwVol = NULL; + + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, " Looking for Platform ACPI table: %g\n", FfsGuid)); + + // + // Locate the firmware volume protocol + // + Status = LocateSupportProtocol ( + &gEfiFirmwareVolume2ProtocolGuid, + FfsGuid, + (VOID **)&FwVol + ); + ASSERT_EFI_ERROR (Status); + + // + // Read tables from the FV. + // + while (Status == EFI_SUCCESS) { + Status = FwVol->ReadSection ( + FwVol, + FfsGuid, + EFI_SECTION_RAW, + Instance, + (VOID **)&CurrentTable, + &Size, + &FvStatus + ); + if (!EFI_ERROR (Status)) { + BoardUpdateAcpiTable (CurrentTable, &Version); + // + // Add the table + // + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Failed to install ACPI table.\n")); + continue; + } + + Status = gBS->FreePool (CurrentTable); + CurrentTable = NULL; + // + // Increment the instance + // + Instance++; + } + } + + // + // Finished + // + return Status; +} + +/** + ACPI Platform driver installation function. + + @param[in] ImageHandle Handle for this drivers loaded image protocol. + @param[in] SystemTable EFI system table. + + @retval EFI_SUCCESS The driver installed without error. + @retval EFI_ABORTED The driver encountered an error and could not complete installation of + the ACPI tables. + +**/ +EFI_STATUS +EFIAPI +InstallAcpiBoard ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid); + if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) { + DEBUG ((DEBUG_ERROR, " Failed to publish platform ACPI table.\n")); + ASSERT (FALSE); + } + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..c9648cada4004720667c74f72bfc2fc11230bc0d --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,62 @@ +## @file +# BoardAcpiDxe friver to install common ACPI tables. +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = BoardAcpiDxe + FILE_GUID = ADA70EED-1CB6-4A69-B136-12E395ED2FC5 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallAcpiBoard + +[Sources.common] + BoardAcpiDxe.c + Dsdt/Dsdt.asl + Dsdt/PciSsdt.asl + Dsdt/AmdPci.asi + +[Packages] + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BoardAcpiTableLib + DebugLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart0Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart1Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart2Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart3Irq + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + +[Depex] + gEfiAcpiTableProtocolGuid AND + gEfiFirmwareVolume2ProtocolGuid + +[BuildOptions.common] + # + # Specify the addtinoal directories for IASL compiler to serach FchSongshanI2C_I3C.asl from either /AGESA/AgesaModulePkg or /edk2-platforms/Platform/AMD. + # /AGESA/AgesaModulePkg has the higher priority to search if this driver is built with AGESA PI release, otherwise the driver is build with opensource AGESA. + # + MSFT:*_*_*_ASL_FLAGS = -I$(WORKSPACE)/AGESA/AgesaModulePkg/Fch/Songshan/FchSongshanDxe -I$(WORKSPACE)/edk2-platforms/Platform/AMD/AgesaModulePkg/Fch/Songshan/FchSongshanDxe + GCC:*_*_*_ASL_FLAGS = -I$(WORKSPACE)/AGESA/AgesaModulePkg/Fch/Songshan/FchSongshanDxe -I$(WORKSPACE)/edk2-platforms/Platform/AMD/AgesaModulePkg/Fch/Songshan/FchSongshanDxe diff --git a/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi new file mode 100644 index 0000000000000000000000000000000000000000..f7e5f462cc885cea7c74f4445263c2e3853390d5 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi @@ -0,0 +1,411 @@ +/***************************************************************************** + * + * Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + *****************************************************************************/ +External (PCI0, DeviceObj) +External (\_SB.PCI0.RP71, DeviceObj) +External (PCI3, DeviceObj) +External (\_SB.PCI3.RP71, DeviceObj) +External (POSS, FieldUnitObj) +External (POSC, FieldUnitObj) + +Name (SS1, Zero) +Name (SS2, Zero) +Name (SS3, One) +Name (SS4, Zero) +Name (PRWP, Package (0x02) +{ + Zero, + Zero +}) +Method (GPRW, 2, NotSerialized) +{ + PRWP [Zero] = Arg0 + Local0 = (SS1 << One) + Local0 |= (SS2 << 0x02) + Local0 |= (SS3 << 0x03) + Local0 |= (SS4 << 0x04) + If (((One << Arg1) & Local0)) + { + PRWP [One] = Arg1 + } + Else + { + Local0 >>= One + FindSetRightBit (Local0, PRWP [One]) + } + + Return (PRWP) +} + +Scope (PCI0) { + Device (AL2A) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, "AL2AHB") + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadOnly, 0xFEDC0000, 0x00001000) + }) + OperationRegion (LUIE, SystemMemory, 0xFEDC0020, 0x4) + Field(LUIE, AnyAcc, NoLock, Preserve) { + IER0, 1, // IO_Enable_Range_0 + IER1, 1, // IO_Enable_Range_1 + IER2, 1, // IO_Enable_Range_2 + IER3, 1, // IO_Enable_Range_3 + LUR1, 4, // Reserved + WUR0, 2, // Which_UART_RANGE_0 + WUR1, 2, // Which_UART_RANGE_0 + WUR2, 2, // Which_UART_RANGE_0 + WUR3, 2, // Which_UART_RANGE_0 + LUR2, 16, // Reserved + } + // Return _STA Disable value if Legacy Resources Enabled + // Otherwise return _STA Enabled valude (0xF) + // ARG0 = UART number 0-3 + Method (USTA, 1) { + If (LAnd (LEqual(IER0, One), LEqual (WUR0, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER1, One), LEqual (WUR1, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER2, One), LEqual (WUR2, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER3, One), LEqual (WUR3, Arg0))) { + Return (Zero) + } + Else { + Return (0xF) + } + } + + // Return _STA Enable value (0xF) if COMx address is being decoded + // Else return _STA Disable value (0x0) + // ARG0 = COM port number 1-4 + Method (CSTA, 1) { + If (LAnd (LEqual (Arg0, 1), LEqual (IER3, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 2), LEqual (IER1, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 3), LEqual (IER2, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 4), LEqual (IER0, 1))) { + Return (0xF) + } + Else { + Return (Zero) + } + } + } + Device (URT0) { + Name (_HID, "AMDI0020") + Name (_UID, Zero) + Method (_STA) { + Store (^^AL2A.USTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDC9000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDC7000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart0Irq)} + }) + } + + Device (URT1) { + Name (_HID, "AMDI0020") + Name (_UID, One) + Method (_STA) { + Store (^^AL2A.USTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCA000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDC8000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart1Irq)} + }) + } + + // UART 2 always disabled + Device (URT2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Name (_STA, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCE000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDCC000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart2Irq)} + }) + } + + // UART 3 always disabled + Device (URT3) { + Name (_HID, "AMDI0020") + Name (_UID, 0x3) + Name (_STA, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCF000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDCD000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart3Irq)} + }) + } + + Device (LPC0) { + Name (_ADR, 0x140003) + + // UARTx -> COM1: I/O port 0x3F8, IRQ PcdFchUart1Irq + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM1") + Name (_UID, One) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03F8, 0x03F8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart1Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM1", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM2: I/O port 0x2F8, IRQ PcdFchUart0Irq + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM2") + Name (_UID, 2) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x02F8, 0x02F8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart0Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM2", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM3: I/O port 0x3E8, IRQ PcdFchUart2Irq + Device (COM3) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM3") + Name (_UID, 3) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03E8, 0x03E8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart2Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM3", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM4: I/O port 0x2E8, IRQ PcdFchUart3Irq + Device (COM4) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM4") + Name (_UID, 4) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x02E8, 0x02E8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart3Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM4", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + Device (DMAC) { + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0, 0x0, 0x1, 0x10) + IO (Decode16, 0x81, 0x81, 0x1, 0xF) + IO (Decode16, 0xC0, 0xC0, 0x1, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) {4} + }) + } // Device (DMAC) + + Device (RTC) { + Name (_HID, EISAID ("PNP0B00")) + Name (_FIX, Package () {EISAID ("PNP0B00")}) + Name (_CRS, ResourceTemplate () { + IO (Decode16,0x70,0x70,0x01,0x02) + IO (Decode16,0x72,0x72,0x01,0x02) + }) + } // Device (RTC) + + Device (SPKR) { + Name (_HID, EISAID ("PNP0800")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x61, 0x61, 0x1, 0x1) + }) + } // Device (SPKR) + + Device (TMR) { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x40, 0x40, 0x1, 0x4) + }) + } // Device (TMR) + + Device (SYSR) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x10, 0x10, 0x1, 0x10) + IO (Decode16, 0x20, 0x20, 0x1, 0x2) + IO (Decode16, 0xA0, 0xA0, 0x1, 0x2) + IO (Decode16, 0x72, 0x72, 0x1, 0x2) + IO (Decode16, 0x80, 0x80, 0x1, 0x1) + IO (Decode16, 0xB0, 0xB0, 0x1, 0x2) + IO (Decode16, 0x92, 0x92, 0x1, 0x1) + IO (Decode16, 0xF0, 0xF0, 0x1, 0x1) + IO (Decode16, 0x400, 0x400, 0x01,0xd0) + IO (Decode16, 0x4D0, 0x4D0, 0x1, 0x2) + IO (Decode16, 0x4D6, 0x4D6, 0x1, 0x1) + IO (Decode16, 0xC00, 0xC00, 0x1, 0x2) + IO (Decode16, 0xC14, 0xC14, 0x1, 0x1) + IO (Decode16, 0xC50, 0xC50, 0x1, 0x3) + IO (Decode16, 0xC6C, 0xC6C, 0x1, 0x1) + IO (Decode16, 0xC6F, 0xC6F, 0x1, 0x1) + IO (Decode16, 0xCD0, 0xCD0, 0x1, 0xc) + }) + } // Device (SYSR) + + Device (SPIR) { // SPI ROM + Name (_HID, EISAID ("PNP0C01")) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadOnly, + FixedPcdGet32 (PcdFlashAreaBaseAddress), + FixedPcdGet32 (PcdFlashAreaSize) + ) + }) + } // Device (SPIR) + +#if FixedPcdGet8 (PcdIpmiInterfaceType) != 0 + Device (IPMK) { // IPMI KCS Device + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, Unicode ("IPMI_KCS")) // _STR: Description String + Name (_UID, Zero) // _UID: Unique ID + Name (_IFT, One) // _IFT: IPMI Interface Type + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress), // Range Minimum + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress), // Range Maximum + 0x00, // Alignment + 0x02 // Length + ) + }) + Method (_SRV, 0, NotSerialized) { // _SRV: IPMI Spec Revision + Return (0x0200) + } + Method (_STA, 0, NotSerialized) { // _STA: Status + If (FixedPcdGet8 (PcdIpmiInterfaceType) == _IFT) { + Return (0x0F) + } + Else { + Return (Zero) + } + } // Method (_STA) + } // Device (IPMK) +#endif + + } // Device (LPC0) +} // Device (PCI0) + + Scope (\_SB.PCI0.RP71) { + Device (XHC0) + { + Name (_ADR, 0x00000004) + Method (_PRW, 0, NotSerialized) + { + Return (GPRW (0x0B, 0x04)) + } + } + } +Scope (\_SB.PCI3.RP71) { + Device (XHC0) + { + Name (_ADR, 0x00000004) + Method (_PRW, 0, NotSerialized) + { + Return (GPRW (0x0B, 0x04)) + } + } + } + + +Scope (_GPE) +{ + Method (_L0B, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.PCI0.RP71.XHC0, 0x02) // Device Wake + Notify (\_SB.PCI3.RP71.XHC0, 0x02) // Device Wake + } +} diff --git a/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl new file mode 100644 index 0000000000000000000000000000000000000000..cf6dca749be7b30e4c7c2c29a77ef1c6509c5931 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl @@ -0,0 +1,171 @@ +/***************************************************************************** + * + * Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + *****************************************************************************/ + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, + "AMD ", + "AmdTable", + 0x00 +) + +// BEGIN OF ASL SCOPE +{ + Name (\_S0, Package(4) { + 0x00, 0x00, 0x00, 0x00 // PM1a_CNT.SLP_TYP = 0, PM1b_CNT.SLP_TYP = 0 + }) + Name (\_S5, Package(4) { + 0x05, 0x00, 0x00, 0x00 // PM1a_CNT.SLP_TYP = 5, PM1b_CNT.SLP_TYP = 0 + }) + + External (POSS, FieldUnitObj) + External (POSC, FieldUnitObj) + External (SMIR, FieldUnitObj) + External (DSMI, FieldUnitObj) + External (DRPB, FieldUnitObj) + External (DRPA, FieldUnitObj) + External (DIDX, FieldUnitObj) + External (DFIN, FieldUnitObj) + External (DOUT, FieldUnitObj) + External (DRPN, FieldUnitObj) + External (OSMI, FieldUnitObj) + External (ORPB, FieldUnitObj) + External (ORPA, FieldUnitObj) + External (OAG1, FieldUnitObj) + + Scope (\_SB) { + Name (SUPP, 0) + Name (CTRL, 0) + Name (SUPC, Zero) + Name (CTRC, Zero) + NAME (BUF, Buffer() {0x00, 0x00}) + Method (OSCI, 4, NotSerialized) + { + CreateDWordField (Arg3, 0, CDW1) + // Check for proper UUID + If (LOr(LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")), + // The _OSC interface for a CXL Host Bridge UUID + (LEqual(Arg0, ToUUID("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3 ,CTRL) + // Only allow native hot plug control if OS supports: + // \* ASPM + // \* Clock PM + // \* MSI/MSI-X + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + If (LNotEqual (Arg1, One)) + { + // Unknown revision + Or (CDW1, 0x08, CDW1) + } + // Update CTRL (DWORD 3) from Platform RASD + And (CTRL, POSC, CTRL) + If (LNotEqual (CDW3, CTRL)) + { + // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + // Update to RASD oreration region. + Store (SUPP, POSS) //Store SUPP (DWORD 2) to Platform RASD + // If CXL Host Bridge + If (LEqual (Arg0, ToUUID ("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))) { + CreateDWordField (Arg3, 12, CDW4) // CXL Support Field: + CreateDWordField (Arg3, 16, CDW5) // CXL Control Field: + Store(CDW4,SUPC) + Store(CDW5,CTRC) + // + // The firmware clear bit 0 to deny control over CXL Memory CXL + // Error Reporting if bit 0 or 1 are not set + // + // Check bit 0 + // RCD and RCH Port Register Access Supported + // + If (LNotEqual (And (SUPC, 0x01), 0x01)) + { + And (CTRC, 0xFE, CTRC) + } + // + // Check bit 1 + // CXL VH Register Access Supported + // + If (LNotEqual (And (SUPC, 0x02), 0x01)) + { + And (CTRC, 0xFE, CTRC) + } + // Update DWORD5 in the buffer + Store (CTRC, CDW5) + } + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } + + Method (HDSM, 7, Serialized) { + CreateWordField(BUF, 0, SUPF) + Store(0, SUPF) + // check for GUID and revision match + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))) { + If (LEqual(Arg1, 0x05)) { + Store (Arg2, DIDX) + Store (0x00, DFIN) + If (LEqual(Arg2, 0x0C)) { + Store (ObjectType(Arg3), Local0) + If (LEqual (Local0, 4)) { // Arg3 is a package obj + Store (DeRefOf (Index (Arg3, 0)), Local1) + } Else { // Assume Arg3 is an Integer obj + Store (Arg3, Local1) + } + Store (Local1, DFIN) + Store (Arg6, DRPN) + } + Store (Arg4, DRPB) + Store (Arg5, DRPA) + // Trigger EDR DSM SMI + Store (DSMI, SMIR) + // Function 0 + If (LEqual(Arg2, 0)) { + Store(DOUT, SUPF) + Return(BUF) + } + // Functions 0x0C, 0x0D + Return(DOUT) + } + } + Return(BUF) // Failed + } // end HDSM + + Method (HOST, 4, Serialized) { + // OSPM calls this method after processing ErrorDisconnectRecover notification from firmware + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x0F) { // Error Disconnect Recover request + Store (Arg2, ORPB) + Store (Arg3, ORPA) + Store (Arg1, OAG1) + // Trigger EDR OST SMI + Store (OSMI, SMIR) + } // End Case(0xF) + } // End Switch + } // end HOST + + } + + Include ("FchSongshanI2C_I3C.asl") + +}// End of ASL File diff --git a/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl new file mode 100644 index 0000000000000000000000000000000000000000..37e9ed38ccc60220be4562444356f4ef5b66e440 --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl @@ -0,0 +1,29 @@ +/***************************************************************************** + * + * Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + *****************************************************************************/ + +/* + ACPI FCH device resources +*/ + +DefinitionBlock ( + "PciSsdt.aml", + "SSDT", + 0x02, // SSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // declared within the Definition Block are to be evaluated as 64-bit values + "AMD ", // OEM ID (6 byte string) + "AmdTable",// OEM table ID (8 byte string) + 0x00 // OEM version of SSDT table (4 byte Integer) +) + +// BEGIN OF ASL SCOPE +{ + Scope (\_SB) { + Include ("AmdPci.asi") + } +}// End of ASL File + diff --git a/Platform/AMD/GenoaBoard/Universal/DfResourcesPei/DfResourcesPei.c b/Platform/AMD/GenoaBoard/Universal/DfResourcesPei/DfResourcesPei.c new file mode 100644 index 0000000000000000000000000000000000000000..798aef170aa56c9c6325ae56a4f1d58af6a8bfbb --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/DfResourcesPei/DfResourcesPei.c @@ -0,0 +1,198 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Entry point for Data Fabric Resouces PEIM. + + @param FileHandle Pointer to the FFS file header. + @param PeiServices Pointer to the PEI services table. + + @retval EFI_STATUS EFI_SUCCESS + EFI_STATUS respective failure status. +**/ +EFI_STATUS +EFIAPI +PeiDfResourcesInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + FABRIC_RESOURCE_FOR_EACH_RB *FabricResourceForEachRb; + UINT8 SocPresent; + + DEBUG ((DEBUG_INFO, "Entered - %a\n", __func__)); + Status = (*PeiServices)->AllocatePool ( + PeiServices, + sizeof (FABRIC_RESOURCE_FOR_EACH_RB), + (VOID **)&FabricResourceForEachRb + ); + + if (!EFI_ERROR (Status)) { + SocPresent = (UINT8)FabricTopologyGetNumberOfProcessorsPresent (); + DEBUG ((DEBUG_INFO, "SoC count - %d\n", SocPresent)); + + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][0].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][1].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][2].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][3].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][0].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][1].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][2].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][3].Size = 0x0; + + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][0].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][1].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][2].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[0][3].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][0].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][1].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][2].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[1][3].Alignment = 1; + + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][0].Size = 0x8000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][1].Size = 0x8000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][2].Size = 0x8000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][3].Size = 0x10000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][0].Size = 0x8000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][1].Size = 0x8000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][2].Size = 0x8000000000; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][3].Size = 0x8000000000; + + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][0].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][1].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][2].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][3].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][0].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][1].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][2].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[1][3].Alignment = 0xffffff; + + if ( SocPresent == 2 ) { + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][1].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][3].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][0].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][1].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][2].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][3].Size = 0x2000000; + } else { + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][1].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][3].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][4].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][5].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][6].Size = 0x2000000; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][7].Size = 0x2000000; + } + + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][1].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][3].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][0].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][1].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][2].Alignment = 1; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][3].Alignment = 1; + + if ( SocPresent == 2 ) { + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][0].Size = 0x10000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][1].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][2].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][3].Size = 0x8000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][0].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][1].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][2].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][3].Size = 0x4000000; + } else { + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][0].Size = 0x10000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][1].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][2].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][3].Size = 0x8000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][4].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][5].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][6].Size = 0x4000000; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][7].Size = 0x4000000; + } + + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][0].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][1].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][2].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][3].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][0].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][1].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][2].Alignment = 0xffffff; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][3].Alignment = 0xffffff; + + FabricResourceForEachRb->PrimaryRbSecondNonPrefetchableMmioSizeBelow4G.Size = 0; + FabricResourceForEachRb->PrimaryRbSecondNonPrefetchableMmioSizeBelow4G.Alignment = 1; + FabricResourceForEachRb->PrimaryRbSecondPrefetchableMmioSizeBelow4G.Size = 1; + FabricResourceForEachRb->PrimaryRbSecondPrefetchableMmioSizeBelow4G.Alignment = 1; + + FabricResourceForEachRb->IO[0][0].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[0][1].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[0][2].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[0][3].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[1][0].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[1][1].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[1][2].Alignment = 0xFFFFF; + FabricResourceForEachRb->IO[1][3].Alignment = 0xFFFFF; + + if ( SocPresent == 2 ) { + FabricResourceForEachRb->IO[0][0].Size = 0x1000; + FabricResourceForEachRb->IO[0][1].Size = 0x1000; + FabricResourceForEachRb->IO[0][2].Size = 0x2000; + FabricResourceForEachRb->IO[0][3].Size = 0x1000; + FabricResourceForEachRb->IO[1][0].Size = 0x1000; + FabricResourceForEachRb->IO[1][1].Size = 0x1000; + FabricResourceForEachRb->IO[1][2].Size = 0x2000; + FabricResourceForEachRb->IO[1][3].Size = 0x1000; + } else { + FabricResourceForEachRb->IO[0][0].Size = 0x1000; + FabricResourceForEachRb->IO[0][1].Size = 0x1000; + FabricResourceForEachRb->IO[0][2].Size = 0x2000; + FabricResourceForEachRb->IO[0][3].Size = 0x1000; + FabricResourceForEachRb->IO[0][4].Size = 0x2000; + FabricResourceForEachRb->IO[0][5].Size = 0x1000; + FabricResourceForEachRb->IO[0][6].Size = 0x1000; + FabricResourceForEachRb->IO[0][7].Size = 0x1000; + } + + if ( SocPresent == 2 ) { + FabricResourceForEachRb->PciBusNumber[0][0] = 0x20; + FabricResourceForEachRb->PciBusNumber[0][1] = 0x20; + FabricResourceForEachRb->PciBusNumber[0][2] = 0x20; + FabricResourceForEachRb->PciBusNumber[0][3] = 0x20; + FabricResourceForEachRb->PciBusNumber[1][0] = 0x20; + FabricResourceForEachRb->PciBusNumber[1][1] = 0x20; + FabricResourceForEachRb->PciBusNumber[1][2] = 0x20; + FabricResourceForEachRb->PciBusNumber[1][3] = 0x20; + } else { + FabricResourceForEachRb->PciBusNumber[0][0] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][1] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][2] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][3] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][4] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][5] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][6] = 0x10; + FabricResourceForEachRb->PciBusNumber[0][7] = 0x10; + } + + PcdSet64S (PcdAmdFabricResourceDefaultSizePtr, (UINT64)(UINTN)FabricResourceForEachRb); + } + + return Status; +} diff --git a/Platform/AMD/GenoaBoard/Universal/DfResourcesPei/DfResourcesPei.inf b/Platform/AMD/GenoaBoard/Universal/DfResourcesPei/DfResourcesPei.inf new file mode 100644 index 0000000000000000000000000000000000000000..42267fc495fe87b8cc4e264a96d96f08db5ecfed --- /dev/null +++ b/Platform/AMD/GenoaBoard/Universal/DfResourcesPei/DfResourcesPei.inf @@ -0,0 +1,34 @@ +### @file +# Component information file for Pre-defined Data Fabric resources module. +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = DfResourcesPei + FILE_GUID = E215DB0C-CD25-450D-8A74-87D4CCB107A0 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeiDfResourcesInit + +[Sources] + DfResourcesPei.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + +[LibraryClasses] + BaseLib + BaseFabricTopologyLib + PcdLib + PeimEntryPoint + PeiServicesLib + +[Pcd] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFabricResourceDefaultSizePtr + +[Depex] + TRUE diff --git a/Platform/AMD/PlatformTools/Server/support/overrides.py b/Platform/AMD/PlatformTools/Server/support/overrides.py new file mode 100644 index 0000000000000000000000000000000000000000..556b04423486f32db13970565643214608ea06bd --- /dev/null +++ b/Platform/AMD/PlatformTools/Server/support/overrides.py @@ -0,0 +1,116 @@ +""" + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +""" +import os +import sys +import shutil + +excludeFolder = ["AgesaModulePkg", "AgesaPkg", "AmdCpmPkg", "AmdCbsPkg"] + +def isExcluded (file): + for folder in excludeFolder: + if folder in os.path.dirname(file): + return True + return False + +def _overrides(override=False): + """! + Override or restore Platfrom Override files + + @param overrides True = override files + False = restore files + @exception varies by failure + """ + if override: + mode = "Overrides" + else: + mode = "Restores" + print("\nAMD server platform tianocore source file override processing {}".format(mode)) + + # Get board folder + for arg in sys.argv[1:]: + if "Project.dsc" in arg: + boardName = arg.split(os.sep)[0] + if override: + print("Override files from " + boardName) + else: + print("Restore the files overrode by " + boardName) + + rel_platform_dir = os.path.join ( + "edk2-platforms", + "Platform", + "AMD", + boardName, + "Override" + ) + if sys.platform.startswith("linux"): + workspace ="WORKSPACE" + elif sys.platform.startswith("win"): + workspace ="Workspace" + + if workspace not in os.environ: + print("edk2 \"" + workspace + "\" environment variable is not set! Build process breaks...") + sys.exit() + + edk2Workspace = os.path.expanduser (os.environ.get(workspace)) + search_dir_tuple = [ + os.path.join( + edk2Workspace, + rel_platform_dir + )] + # Get environment variables exception if not located + for search_dir in search_dir_tuple: + print("\tSearching directory: " + search_dir) + for root, dirs, files in os.walk(search_dir): + for file in files: + src = os.path.join(root, file) + dst = os.path.join(edk2Workspace, src[len(search_dir) + 1 :]) + back = "{}.back".format(dst) + + if isExcluded (dst): + continue + + if override: + if os.path.exists(dst): + # Do not override back or dst if back already exists + # Leftover from failed build. A clean build will clean up + if not os.path.exists(back): + print('src: "{}"\n\tdst: "{}"\n\tback: "{}"'.format(src, dst, back)) + shutil.copy(dst, back) + # src must exist, no need to check + shutil.copy(src, dst) + else: + print('\tNo Override: Backup already exists: "{}"'.format(back)) + else: + # This is a new file, copy it to destination + print('src: "{}"\n\tdst: new file: "{}"\n\tback: no back file'.format(src, dst)) + if not os.path.exists(os.path.dirname(dst)): + os.makedirs(os.path.dirname(dst)) + shutil.copy(src, dst) + else: + if os.path.exists(back): + print('Restore to dst: "{}"\n\tsrc: "{}"\n'.format(dst, back)) + shutil.move(back, dst) + else: + if os.path.exists(dst): + print('No Restore: Remove the new source file:"{}"'.format(dst)) + os.remove(dst) + else: + print('No source file to remove:"{}"'.format(dst)) + + +def overrides(): + """! + Override Platfrom Override files + """ + _overrides(override=True) + + +def restore_overrides(): + """! + Restore Platfrom Override files + """ + _overrides(override=False) diff --git a/Platform/AMD/PlatformTools/Server/support/postbuild.py b/Platform/AMD/PlatformTools/Server/support/postbuild.py new file mode 100644 index 0000000000000000000000000000000000000000..24110a55e0b39a13844e4fc737c4fa297331b0af --- /dev/null +++ b/Platform/AMD/PlatformTools/Server/support/postbuild.py @@ -0,0 +1,28 @@ +""" + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +""" +import os +import sys +import overrides + +def postbuild(): + print('PostBuild') + print('Launched Python Version: {}.{}.{}'.format( + sys.version_info.major, + sys.version_info.minor, + sys.version_info.micro)) + overrides.restore_overrides() + +def main(): + """! + Execute PostBuild items + + Execute anything that needs to be completed after the EDKII BUILD + """ + postbuild() + +if __name__ == '__main__': + main() diff --git a/Platform/AMD/PlatformTools/Server/support/prebuild.py b/Platform/AMD/PlatformTools/Server/support/prebuild.py new file mode 100644 index 0000000000000000000000000000000000000000..3341fc3c8259850c21342003ad76540a0cbe1b0e --- /dev/null +++ b/Platform/AMD/PlatformTools/Server/support/prebuild.py @@ -0,0 +1,28 @@ +""" + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +""" +import os +import sys +import overrides + +def prebuild(): + print('PreBuild') + print('Launched Python Version: {}.{}.{}'.format( + sys.version_info.major, + sys.version_info.minor, + sys.version_info.micro)) + overrides.overrides() + +def main(): + """! + Execute PreBuild items + + Execute anything that needs to be completed before the EDKII BUILD + """ + prebuild() + +if __name__ == '__main__': + main() diff --git a/Platform/AMD/PlatformTools/Server/support/prepostbuild_launcher.py b/Platform/AMD/PlatformTools/Server/support/prepostbuild_launcher.py new file mode 100644 index 0000000000000000000000000000000000000000..8caba4e63127d45620a0d2a5897d93cfd741183d --- /dev/null +++ b/Platform/AMD/PlatformTools/Server/support/prepostbuild_launcher.py @@ -0,0 +1,103 @@ +""" + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +""" +import os +import sys +import subprocess +import argparse + +def parseargs(): + parser = argparse.ArgumentParser( + description = 'Launches the proper prebuild.py or postbuild.py script' + ) + parser.add_argument( + 'command', + choices=['prebuild', 'postbuild'], + help='Select between prebuild and postbuild execution' + ) + + args = parser.parse_known_args() + return args + +def main(): + """! + Find proper Python interpreter and launch post build processes + """ + print('PreBuild-PostBuild Launcher') + lmajor, lminor, lmicro, releaselevel, serial = sys.version_info + print('Launched Python Version: {}.{}.{}'.format( lmajor, lminor, lmicro)) + + args, unknown_args = parseargs() + module = __import__(args.command) + func = getattr(module, args.command) + + if 'PYTHON_HOME' in os.environ: + python_home = os.environ['PYTHON_HOME'].strip('"').strip("'") + python_home = os.path.normpath(python_home) + if ( + (os.path.normpath(os.path.dirname(sys.executable)) + == python_home) + and + (lmajor >= 3 and lminor >= 6) + ): + exit(func()) + else: + if sys.platform.startswith("linux"): + python_exe = "python3" + workspace ="WORKSPACE" + elif sys.platform.startswith("win"): + python_exe = "python.exe" + workspace ="Workspace" + python = os.path.normpath(os.path.join(python_home, python_exe)) + + if workspace not in os.environ: + print("edk2 \"" + workspace + "\" environment variable is not set! Build process breaks...") + sys.exit(1) + else: + edk2Workspace = os.environ.get(workspace) + prePostScriptPath = os.path.join ( + edk2Workspace, + "edk2-platforms", + "Platform", + "AMD", + "PlatformTools", + "Server", + "support" + ) + + sys.stdout.flush() + version = str(subprocess.check_output([python, '--version'])) + # Split apart Python version response + name, version = version.split() + major, minor, micro = version.split('.') + if int(major) >= 3 and int(minor) >= 6: + print('Launching using "{}"'.format(python)) + sys.stdout.flush() + command = [ + python, + os.path.join( + prePostScriptPath, + '{}.py'.format(args.command), + ) + ] + command.extend(sys.argv) + exit(subprocess.check_call(command)) + else: + print('ERROR: PYTHON_HOME not pointing to version 3.6 or later') + exit(1) + else: + if lmajor >= 3 and lminor >= 6: + print('Continuing with Launched Python') + exit(func()) + else: + print('Python 3.6 or greater required, exiting') + exit(1) + +if __name__ == '__main__': + main() + + + diff --git a/Platform/AMD/Readme.md b/Platform/AMD/Readme.md index d7835c2482777beb12bdc84621c955ce9cf21e10..f15c96bd8dd3139be254b023494695b6f681288c 100644 --- a/Platform/AMD/Readme.md +++ b/Platform/AMD/Readme.md @@ -1,117 +1,118 @@ -# AMD EDK2 Platform - -This is AMD folder that provides the edk2 modules to support AMD edk2 firmware -solution for the server, client (e.g., Notebook) and S3 (Strategic Silicon Solutions) -platforms. The board packages under this folder are the firmware reference code for -booting certain AMD platforms. The definition of sub-folders is described in below sections. - -## Term and Definitions - -* **AGESA** - - AMD Generic Encapsulated Software Architecture that are executed as part of a - host platform BIOS. - -* **AMD Platform** (platform in short) - - AMD platform refers to a platform that supports the particular AMD SoC (processor), such as - AMD EPYC Milan and Genoa processors. - -* **AMD Board** (board in short) - - AMD board is a generic terminology refers to a board that is designed based on a - specific AMD SoC architecture (also referred as AMD platform). More than one boards - are possibly designed to support an AMD platform with different configuration, such as - 1-processor socket or 2-processor sockets board. - -* **AMD edk2 Platform Package** (platform package in short) - - The folder has the AMD edk2 platform common modules. - -* **AMD edk2 Board Package** (board package in short) - - The folder has the edk2 meta files to build the necessary edk2 firmware modules - and generate the binary to run on a board. - -## Package Definition - -* **AgesaModulePkg** - - This package contains all of the private interfaces and build configuration files for the - AGESA support. - -* **AgesaPkg** - - This package contains all of the public interfaces and build configuration files - for the AGESA support. - -* **AmdCbsPkg** - - AMD Configurable BIOS Setting. Provides the edk2 formset following the UEFI HII - spec to configure BIOS settings. - -* **AmdCpmPkg** - - AMD Common Platform Module software is a BIOS procedure library designed to aid - AMD customers to quickly implement AMD platform technology into their products. - -* **AmdPlatformPkg** - - AMD platform edk2 package under this folder provides the common edk2 - modules that are leveraged by platforms. Usually those modules have no dependencies with - particular platforms. Modules under this scope can provide a common implementation - for all platforms, or may just provide a framework but the differences of implementation - could be configured through the PCDs declared in AmdPlatformPkg.dec, or the board level - library provided in the \Pkg. - -* **AmdMinBoardPkg** - - This package provides the common edk2 modules that can be leveraged across AMD boards using - the MinPlatform framework. - -* **\Board** - - This is the folder named by SoC and accommodates one or multiple board packages - that are designed based on the same SoC platform. Board folder may - contain edk2 package meta files directly or the sub-folders named by \Pkg for - a variety configurations of a platform. - -* **Pkg** - - This is the folder that contains edk2 package meta files for a board which is designed base - on a platform. Besides the edk2 meta files, Pkg may also provides edk2 modules - which are specifically to a board. - - ``` - e.g. GenoaBoard - |------Board1Pkg - |------Board2Pkg - ``` - - Below is the outline of folder structure under Platform/AMD - - ``` - Platform/AMD - |----AgesaModulePkg - |----AgesaPkg - |----AmdCbsPkg - |----AmdCpmPkg - |----AmdPlatformPkg - |----AmdMinBoardPkg - |----GenoaBoard - | |------Common Modules for Genoa boards - | |------Board1Pkg - | | |-------Board specific modules - | |------Board2Pkg - | - |----NextGenBoard - |------Common Modules for the next generation - platform boards - |------Board1Pkg - |------Board2Pkg - |-------Board specific modules - ``` - - -## Board Support -Under progress +# AMD EDK2 Platform + +This is AMD folder that provides the edk2 modules to support AMD edk2 firmware +solution for the server, client (e.g., Notebook) and S3 (Strategic Silicon Solutions) +platforms. The board packages under this folder are the firmware reference code for +booting certain AMD platforms. The definition of sub-folders is described in below sections. + +## Term and Definitions + +* **AGESA** + + AMD Generic Encapsulated Software Architecture that are executed as part of a + host platform BIOS. + +* **AMD Platform** (platform in short) + + AMD platform refers to a platform that supports the particular AMD SoC (processor), such as + AMD EPYC Milan and Genoa processors. + +* **AMD Board** (board in short) + + AMD board is a generic terminology refers to a board that is designed based on a + specific AMD SoC architecture (also referred as AMD platform). More than one boards + are possibly designed to support an AMD platform with different configuration, such as + 1-processor socket or 2-processor sockets board. + +* **AMD edk2 Platform Package** (platform package in short) + + The folder has the AMD edk2 platform common modules. + +* **AMD edk2 Board Package** (board package in short) + + The folder has the edk2 meta files to build the necessary edk2 firmware modules + and generate the binary to run on a board. + +## Package Definition + +* **AgesaModulePkg** + + This package contains all of the private interfaces and build configuration files for the + AGESA support. + +* **AgesaPkg** + + This package contains all of the public interfaces and build configuration files + for the AGESA support. + +* **AmdCbsPkg** + + AMD Configurable BIOS Setting. Provides the edk2 formset following the UEFI HII + spec to configure BIOS settings. + +* **AmdCpmPkg** + + AMD Common Platform Module software is a BIOS procedure library designed to aid + AMD customers to quickly implement AMD platform technology into their products. + +* **AmdPlatformPkg** + + AMD platform edk2 package under this folder provides the common edk2 + modules that are leveraged by platforms. Usually those modules have no dependencies with + particular platforms. Modules under this scope can provide a common implementation + for all platforms, or may just provide a framework but the differences of implementation + could be configured through the PCDs declared in AmdPlatformPkg.dec, or the board level + library provided in the \Pkg. + +* **AmdMinBoardPkg** + + This package provides the common edk2 modules that can be leveraged across AMD boards using + the MinPlatform framework. + +* **\Board** + + This is the folder named by SoC and accommodates one or multiple board packages + that are designed based on the same SoC platform. Board folder may + contain edk2 package meta files directly or the sub-folders named by \Pkg for + a variety configurations of a platform. + +* **Pkg** + + This is the folder that contains edk2 package meta files for a board which is designed base + on a platform. Besides the edk2 meta files, Pkg may also provides edk2 modules + which are specifically to a board. + + ``` + e.g. OverdriveBoard + e.g. GenoaBoard + |------Board1Pkg + |------Board2Pkg + ``` + + Below is the outline of folder structure under Platform/AMD + + ``` + Platform/AMD + |----AgesaModulePkg + |----AgesaPkg + |----AmdCbsPkg + |----AmdCpmPkg + |----AmdPlatformPkg + |----AmdMinBoardPkg + |----OverdriveBoard + |----TurinBoard + | |------Common Modules for Genoa boards + | |------VolcanoBoardPkg + | | |-------Board specific modules + | |------Board2Pkg + | + |----NextGenBoard + |------Common Modules for the next generation + platform boards + |------Board1Pkg + |------Board2Pkg + |-------Board specific modules + ``` + +## Board Support +### [Server Boards](./ServerBoard.md) diff --git a/Platform/AMD/ServerBoard.md b/Platform/AMD/ServerBoard.md new file mode 100644 index 0000000000000000000000000000000000000000..92e9612c1217cc5f638512205ee8688a113348c7 --- /dev/null +++ b/Platform/AMD/ServerBoard.md @@ -0,0 +1,117 @@ +### Server boards +### Turin + +| SoC | SoC Family | SoC SKU | SoC Name | Board | Package | +|-----------|------------|---------|-----------|----------|-----------------------------| +| Turin SP5 | 0x1A | BRH | Breithorn | Chalupa | TurinBoard/ChalupaBoardPkg | +| | | | | Galena | TurinBoard/GalenaBoardPkg | +| | | | | Onyx | TurinBoard/OnyxBoardPkg | +| | | | | Purico | TurinBoard/PuricoBoardPkg | +| | | | | Quartz | TurinBoard/QuartzBoardPkg | +| | | | | Ruby | TurinBoard/RubyBoardPkg | +| | | | | Titanite | TurinBoard/TitaniteBoardPkg | +| | | | | Volcano | TurinBoard/VolcanoBoardPkg | + +#### tianocore Code Base +| Code base | Revision | +|----------------|----------------------------------------------------| +| edk2 | edk2-stable202402 stable release | +| edk2-platforms | Commid ID 103c88ba5b0c6259fc674e6358c68a85e882e41b | +| edk2-non-osi | Commid ID f0bb00937ad6bfdf92d9c7fea9f7277c160d82e9 | + +#### Server boards edk2 build +AMD server SoC platform firmware reference code can be built using edk2 native build system. As of now the AGESA source code is released to customer in a different way, the AGESA source files under edk2-platforms/Platform/AMD are published to make sure the platform firmware reference code can be built without errors. Those AGESA modules are considered as the NULL instance of AGESA. Customers can request the release version of +AGESA from AMD, replace the NULL instance AGESA modules. +The open-sourced AGESA modules is still under development and will be upstream to edk2-platforms as the replacement of NULL instance AGESA. + +#### edk2 build steps +- Create an workspace (**[WorkSpace]**), e.g., "~/Turin" for Linux or "c:\Turin" for Windows. +- Clone the below repositories (DO NOT update submodule for edk2, [here is the reason](#)) from tianocore to under the **[WorkSpace]**. + + - edk2 + - edk2-platforms + - edk2-non-osi + +#### Check out the specific revision +Refer to [this table](#tianocore-code-base-table) for the tag or commit to check out.
+When checkout edk2 repository to edk2-stable202402, the git URL to subhook repository points to https://github.com/Zeex/subhook.git which is no longer exist. This issue has been resolved by using git URL to https://github.com/tianocore/edk2-subhook.git. That says when we checkout edk2-stable202402 tag on edk2 repository, we have to manually update the git URL of subhook in .gitmodules to the one on tianocore. Then git submodule update --recursive. + + +#### Configure edk2 **PACKAGE_PATH** for consuming the modules under particular edk2 packages under edk2,edk2-platform and edk2-non-osi , replace **[WorkSpace]** with yours. + +For Linux, +``` +export PACKAGES_PATH=[WorkSpace]:[WorkSpace]/edk2:[WorkSpace]/edk2-platforms:[WorkSpace]/edk2-platforms/Platform/AMD:[WorkSpace]/edk2-platforms/Platform/AMD/TurinBoard:[WorkSpace]/edk2-platforms/Features:[WorkSpace]/edk2-platforms/Platform/Intel:[WorkSpace]/edk2-platforms/Features/Intel:[WorkSpace]/edk2-platforms/Features/Intel/Network:[WorkSpace]/edk2-platforms/Features/Intel/OutOfBandManagement:[WorkSpace]/edk2-platforms/Features/Intel/Debugging:[WorkSpace]/edk2-platforms/Features/Intel/SystemInformation:[WorkSpace]/edk2-platforms/Features/Intel/PowerManagement:[WorkSpace]/edk2-platforms/Features/Intel/UserInterface:[WorkSpace]/edk2-platforms/Silicon/Intel:[WorkSpace]/edk2-non-osi +``` + +##### For Windows, +``` +set PACKAGES_PATH=[WorkSpace];[WorkSpace]\edk2;[WorkSpace]\edk2-platforms;[WorkSpace]\edk2-platforms\Platform\AMD;[WorkSpace]\edk2-platforms\Platform\AMD\TurinBoard;[WorkSpace]\edk2-platforms\Features;[WorkSpace]\edk2-platforms\Platform\Intel;[WorkSpace]\edk2-platforms\Features\Intel;[WorkSpace]\edk2-platforms\Features\Intel\Network;[WorkSpace]\edk2-platforms\Features\Intel\OutOfBandManagement;[WorkSpace]\edk2-platforms\Features\Intel\Debugging;[WorkSpace]\edk2-platforms\Features\Intel\SystemInformation;[WorkSpace]\edk2-platforms\Features\Intel\PowerManagement;[WorkSpace]\edk2-platforms\Features\Intel\UserInterface;[WorkSpace]\edk2-platforms\Silicon\Intel;[WorkSpace]\edk2-non-osi +``` + +#### Configure edk2 tools path. + +##### For Linux, +``` +export EDK_TOOLS_PATH=[WorkSpace]/edk2/BaseTools +``` + +##### For Windows, + +``` +set EDK_TOOLS_PATH=[WorkSpace]\edk2\BaseTools +``` + +#### Build edk2 base tools under **[WorkSpace]**. + +##### For Linux, +``` +make -C edk2/BaseTools +``` +##### For Windows, +``` +edksetup.bat Rebuild +``` + +#### Configure edk2 build environment, change the current working directory to **[WorkSpace]**, then execute edk2setup bash file. + +##### For Linux, +``` +. edksetup.sh +``` +##### For Windows, +``` +edksetup.bat +``` + +#### Change edk2 WORKSPACE to **[WorkSpace]** +##### For Linux, +``` + export WORKSPACE=[WorkSpace] +``` + +##### For Linux, +``` + set WORKSPACE=[WorkSpace] +``` + +#### Build server board Project.dsc
+The additional build environment variables are required for the build process, refer to [server board supporting table](#Server-boards) for the values. + +|Environment Variable |Value | +|------------------------|--------------| +|**SOC_FAMILY** | [SoC Family] | +|**SOC_SKU** | [SoC SKU] | +|**SOC2** | [SoC Name] | + +##### Building Turin SP5 Chalupa board on Linux, +``` +cd [WorkSpace] +build -a X64 -a IA32 -t GCC -DSOC_FAMILY=0x1A -DSOC_SKU=BRH -DSOC2=Breithorn -p TurinBoard/ChalupaBoardPkg/Project.dsc +``` + +##### Building Turin SP5 Chalupa board on Windows, +``` +cd [WorkSpace] +build -a X64 -a IA32 -t VS2017 -DSOC_FAMILY=0x1A -DSOC_SKU=BRH -DSOC2=Breithorn -p TurinBoard\ChalupaBoardPkg\Project.dsc +``` diff --git a/Platform/AMD/TurinBoard/Apcb/ApcbToken.h b/Platform/AMD/TurinBoard/Apcb/ApcbToken.h new file mode 100644 index 0000000000000000000000000000000000000000..5febe88356766f6aa293102b010822d24f366c8f --- /dev/null +++ b/Platform/AMD/TurinBoard/Apcb/ApcbToken.h @@ -0,0 +1,43 @@ +/** @file + + Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Add override tokens here + +#ifdef ESPI_UART +#ifdef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE + #undef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE +#endif +#define APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE 0 + +#ifdef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE + #undef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE +#endif +#define APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE 0 +#endif /// end of ESPI_UART + +#ifdef PCIE_MULTI_SEGMENT + #define APCB_TOKEN_UID_DF_PCI_MMIO_BASE_VALUE 0x0 + #define APCB_TOKEN_UID_DF_PCI_MMIO_HI_BASE_VALUE 0x3FFB +#endif /// end of PCIE_MULTI_SEGMENT + +#ifdef SATA_OVERRIDE + #define APCB_TOKEN_UID_FCH_SATA_0_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_1_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_2_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_3_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_4_ENABLE_VALUE 1 + #define APCB_TOKEN_UID_FCH_SATA_5_ENABLE_VALUE 1 + #define APCB_TOKEN_UID_FCH_SATA_6_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_7_ENABLE_VALUE 0 +#endif + +#ifdef ROM3_1TB_REMAP + #define APCB_TOKEN_UID_FCH_ROM3_BASE_HIGH_VALUE 0x3FFC +#else + #define APCB_TOKEN_UID_FCH_ROM3_BASE_HIGH_VALUE 0 +#endif diff --git a/Platform/AMD/TurinBoard/Binaries/EarlyVgaProg.bin b/Platform/AMD/TurinBoard/Binaries/EarlyVgaProg.bin new file mode 100644 index 0000000000000000000000000000000000000000..27535ee85aa0820783137771e2e7f7726ce378e7 Binary files /dev/null and b/Platform/AMD/TurinBoard/Binaries/EarlyVgaProg.bin differ diff --git a/Platform/AMD/TurinBoard/Binaries/earlyVgaProgOnly.bin b/Platform/AMD/TurinBoard/Binaries/earlyVgaProgOnly.bin new file mode 100644 index 0000000000000000000000000000000000000000..fbf4b4ef76ca7580f967a9d373f6e42e196ee26b Binary files /dev/null and b/Platform/AMD/TurinBoard/Binaries/earlyVgaProgOnly.bin differ diff --git a/Platform/AMD/TurinBoard/Binaries/epyc2_image.bin b/Platform/AMD/TurinBoard/Binaries/epyc2_image.bin new file mode 100644 index 0000000000000000000000000000000000000000..20c20491e3cb8b824310f023e2b9f2d8ddf5c5f1 Binary files /dev/null and b/Platform/AMD/TurinBoard/Binaries/epyc2_image.bin differ diff --git a/Platform/AMD/TurinBoard/ChalupaBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..047a9bb4eeec60495558f77fe446e08422b3223b --- /dev/null +++ b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("069F7A75-1155-455F-81E9-2D778481D7EF")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..29dd088c37f883c646a86750d4c2291c6164cda3 --- /dev/null +++ b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.dsc @@ -0,0 +1,203 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Chalupa +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 481A9339-68CD-4EBF-A656-857B3B9FE89B + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "CHALUPA " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204150554C414843 # "CHALUPA " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..4701cd93633b714fb52ffdd4b6a02aab36b59910 --- /dev/null +++ b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/EmulationBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/EmulationBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..80922a8dc86b2806c5429f85fcabe82a8028800c --- /dev/null +++ b/Platform/AMD/TurinBoard/EmulationBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,202 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("069F7A75-1155-455F-81E9-2D778481D7EF")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..e7daed9ac8fa76a4a07c63fc4e63f040c32b9fdc --- /dev/null +++ b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.dsc @@ -0,0 +1,202 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + # emulation is based on Chalupa including all PCDs and reference settings + PLATFORM_CRB = Chalupa +!endif + PLATFORM_NAME = EmulationBoardPkg + PLATFORM_GUID = C305E1F5-98FA-447D-846F-0863BBE8796A + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "EMULATE " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + # DRAM boot for emulation, set this flag to TRUE for pure Emulation environment + DEFINE DRAM_BOOT = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204151554C414843 # "CHALUPA " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdTransparentErrorLoggingEnable|TRUE + !if $(USB_SUPPORT) + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|FALSE + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..c065189b0a01bc17ad870127a94701472bb1e2df --- /dev/null +++ b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.fdf @@ -0,0 +1,49 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + + # Emulation BIOS can only be 16MB in size + DEFINE BUILD_16MB_IMAGE = TRUE + + !if $(BUILD_16MB_IMAGE) == TRUE + DEFINE SPI_NUM_BLOCKS = 0x1000 + !else + DEFINE SPI_NUM_BLOCKS = 0x2000 + !endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/GalenaBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/GalenaBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..1c3ad8dd0871e17c9c4d76870a6963ea4303576a --- /dev/null +++ b/Platform/AMD/TurinBoard/GalenaBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("3E35E28F-C98B-481B-BA7C-97C712982509")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..970dceee06f4734a4c4beb3178d1f53c3af9bcb7 --- /dev/null +++ b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.dsc @@ -0,0 +1,203 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Galena +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "GALENA " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020414E454C4147 # "GALENA " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..4701cd93633b714fb52ffdd4b6a02aab36b59910 --- /dev/null +++ b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..140859310cf68e33c77ffb4539253875af800c31 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf @@ -0,0 +1,19 @@ +## @file +# +# CRB specific - External AGESA DXE build. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # + # AMD AGESA DXE Includes - External + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/External/Cbs$(SOC2_2).dxe.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/External/Cbs$(SOC2).dxe.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.inc.dsc b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..dda6a6a7055308cc334c019a37dd40c37fd00704 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.inc.dsc @@ -0,0 +1,19 @@ +## @file +# +# CRB specific - External AGESA build. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # + # AMD AGESA Includes - External + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/External/Cbs$(SOC2_2).inc.dsc + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/External/Cbs$(SOC2).inc.dsc + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..f54b9868c41192b53a8c3c7ba2281d5cea282f40 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf @@ -0,0 +1,19 @@ +## @file +# +# CRB specific - External AGESA PEI build. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # + # AMD AGESA PEI Includes - External + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/External/Cbs$(SOC2_2).pei.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/External/Cbs$(SOC2).pei.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..db59e1f68c8b708efdb07761764f188591620279 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf @@ -0,0 +1,21 @@ +## @file +# +# CRB specific - Internal AGESA DXE build. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # + # AMD AGESA DXE Includes - Internal + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/Internal/Cbs$(SOC2_2).dxe.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/Internal/Cbs$(SOC2).dxe.inc.fdf + !else + !include AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.dxe.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.inc.dsc b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..260e6088c1fba50e45050d0585433a6fd9acdec8 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.inc.dsc @@ -0,0 +1,22 @@ +## @file +# +# CRB specific - Internal AGESA build. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # + # AMD AGESA Includes - Internal + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.inc.dsc + !include AgesaModulePkg/AgesaIdsIntBrh.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/Internal/Cbs$(SOC2_2).inc.dsc + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/Internal/Cbs$(SOC2).inc.dsc + !else + !include AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.inc.dsc + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..ce9b6ae7dc66f07c377bf3412bed370652ac707a --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf @@ -0,0 +1,21 @@ +## @file +# +# CRB specific - Internal AGESA PEI build. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # + # AMD AGESA PEI Includes - Internal + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/Internal/Cbs$(SOC2_2).pei.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/Internal/Cbs$(SOC2).pei.inc.fdf + !else + !include AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.pei.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/Dsc/Platform.inc.dsc b/Platform/AMD/TurinBoard/Include/Dsc/Platform.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..19edc864359bfd8f43d137fadd2951cabf593dd2 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Dsc/Platform.inc.dsc @@ -0,0 +1,20 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# CPM path +!ifndef CPM_DIR_PATH + CPM_DIR_PATH = $(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR) +!endif +!include AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(CPM_DIR_PATH)$(PLATFORM_CRB)Pkg.inc.dsc + +# AMD AGESA Include Path +!ifdef $(INTERNAL_IDS) + !include $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.inc.dsc +!else + !include $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.inc.dsc +!endif diff --git a/Platform/AMD/TurinBoard/Include/Dsc/PlatformCommonPcd.dsc.inc b/Platform/AMD/TurinBoard/Include/Dsc/PlatformCommonPcd.dsc.inc new file mode 100644 index 0000000000000000000000000000000000000000..94109e05d84a647380bd4f2697883a3e3ffa3999 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Dsc/PlatformCommonPcd.dsc.inc @@ -0,0 +1,725 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +!ifndef SECURE_BOOT_ENABLE + DEFINE SECURE_BOOT_ENABLE = TRUE +!endif +!ifndef PLATFORM_SECURE + DEFINE PLATFORM_SECURE = FALSE +!endif + DEFINE NETWORK_IP6_ENABLE = FALSE + + # + # Redfish support + # + DEFINE REDFISH_ENABLE = FALSE + + # + # Set Platform Redfish configuration + # +!if $(REDFISH_ENABLE) == TRUE + + # Enable BMC USB NIC as the Redfish transport interface + DEFINE USB_NETWORK_SUPPORT = TRUE + + # Allow HTTP connection for Redfish + DEFINE NETWORK_SNP_ENABLE = TRUE + DEFINE NETWORK_IP6_ENABLE = TRUE + DEFINE NETWORK_IP4_ENABLE = TRUE + DEFINE NETWORK_HTTP_ENABLE = TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE +!endif + +[Packages] + AmdCpmPkg/AmdCpmPkg.dec + AmdMinBoardPkg/AmdMinBoardPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + ManageabilityPkg/ManageabilityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + Network/NetworkFeaturePkg/NetworkFeaturePkg.dec + PcAtChipsetPkg/PcAtChipsetPkg.dec + SecurityPkg/SecurityPkg.dec + SpcrFeaturePkg/SpcrFeaturePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +# MinPlatformPkg includes +!include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc + +[PcdsFixedAtBuild] + # + # Key Boot Stage + # + # Please select the Boot Stage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiBertTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiHestTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiEinjTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + + # Set ROM Armor Selection + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspRomArmorSelection|1 + + # + # Set EFI Shell file description + # + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc|L"Internal UEFI Shell 2.2" + + # + # BSP Broadcast Method for the first-time wakeup of APs + # + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE + +[PcdsFeatureFlag] + # + # MinPlatformPkg Configuration + # + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|$(SECURE_BOOT_ENABLE) + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + !endif + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable|TRUE + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable|TRUE + !endif + +# Below include file should be here +# after PcdBootStage is set. +# and after respective features are enabled/disabled depends on PcdBootStage +!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + + # + # Below are Manageability feature knobs. + # + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiBmcAcpi|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiBmcElog|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiFrb|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiFru|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiOsWdt|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiSolStatus|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeMctpEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxePldmEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxePldmSmbiosTransferEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityPeiIpmiEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityPeiIpmiFrb|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilitySmmIpmiEnable|FALSE + # Enable IPMI feature for boot stage >=5 and only for real SoC + !if (gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5) && ($(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE) + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiEnable|TRUE + !endif + + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + !endif + + # MdeModulePkg + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Uefi Cpu Package + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|FALSE + + # ACPI + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + # Enable ROM Armor + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable|TRUE + +[PcdsFixedAtBuild.IA32] + # + # Temporary DRAM space for SEC->PEI transition (256KB) + # AMD_ENABLE_UEFI_STACK (Flat32.asm) divides: 1/2 Heap + 1/2 Stack + # + gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamBase|0x00100000 + gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamSize|0x00100000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x80000 + +[PcdsFixedAtBuild] + # Console/Uart settings + !if $(SERIAL_PORT) == "FCH_MMIO" + # MMIO based flow control UART0, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|0 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFEDC9000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|48000000 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0001 + !endif + + !if $(SERIAL_PORT) == "FCH_IO" + # Legacy based flow control UART0, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|0 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0100 + !endif + + !if $(SERIAL_PORT) == "BMC_SOL" + # MMIO based non-flow control UART1, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|1 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFEDCA000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|48000000 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|0xE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0002 + !endif + + !if $(SERIAL_PORT) == "BMC_SOL_IO" + # Legacy based non-flow control UART1, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|1 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|0xE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0200 + !endif + + !if $(SERIAL_PORT) == "BMC_ESPI" + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0000 + !endif + + # Indicates the receive FIFO depth of UART controller. + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|64 + + # Default Value of PlatformLangCodes Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + + ## The mask is used to control ReportStatusCodeLib behavior. + # BIT0 - Enable Progress Code. + # BIT1 - Enable Error Code. + # BIT2 - Enable Debug Code. + !ifdef $(INTERNAL_IDS) + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + !else + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x00 + !endif + + # + # Debug Masks + # + # // + # // Declare bits for PcdDebugPropertyMask + # // + # DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PROPERTY_DEBUG_PRINT_ENABLED 0x02 + # DEBUG_PROPERTY_DEBUG_CODE_ENABLED 0x04 + # DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED 0x08 + # DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED 0x10 + # DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED 0x20 + # // + # // Declare bits for PcdFixedDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint() + # // + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload message of manageability + # // related modules, such Redfish, IPMI, MCTP and etc. + # DEBUG_ERROR 0x80000000 // Error + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + !if $(DEBUG_DISPATCH_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x808000CF + !else + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x8080004F + !endif + + # + # AGESA Debug + # + !if ($(IDS_DEBUG_ENABLE) == TRUE) AND ($(SERIAL_PORT) != "NONE") + # IdsDebugPrint Filter. Refer to Library/IdsLib.h for details. + # 0x100401008A30042C (GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC | CPU_TRACE | MEM_FLOW | + # MEM_STATUS | MEM_PMU | FCH_TRACE | MAIN_FLOW | TEST_POINT | PSP_TRACE) + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintFilter|0x0000000300000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortDetectCableConnection|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPort|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + !else + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEnable|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortEnable|FALSE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80 + !else + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00 + !endif + + # + # Specifies the initial value for Register_D in RTC. + # Reason for change: + # PcRtc.c wants to see register D bit 7 (VRT) high almost immediately after writing the below value, + # which clears it with the default UEFI value of zero. The AMD FCH updates this bit only once per 4-1020ms (1020ms default). + # This causes function RtcWaitToUpdate to return an error. Preset VRT to 1 to avoid this. + # + gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x80 + + # + # SMBIOS + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosT16MaximumCapacity|0x80000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + + # + # PCIe Config-space MMIO (1MB per bus, 256MB) + # + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE + !endif + + !if $(PCIE_MULTI_SEGMENT) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x3FFB00000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow|0x0 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi|0x3FFB + !else + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow|0xE0000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi|0x0 + !endif + + # + # Boot + # + # PCDs to set the default size of the different UEFI memory types to promote + # contiguous UEFI memory allocation. These values are used by + # AmdCommon/Pei/PlatformInitPei/MemoryInitPei.c to reserve + # default chunks for each memory type when gEfiMemoryTypeInformationGuid + # variable is not set. These values can be updated to prevent reboot because + # MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c: + # BmSetMemoryTypeInformationVariable() sets gEfiMemoryTypeInformationGuid at + # the end of post to reserve more memory. Serial output from this code will + # display sizes required, which can then be updated in these PCDs. + # Memory Type 09 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize | 0x400 + # Memory Type 0A + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize | 0x400 + # Memory Type 00 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize | 0x5000 + # Memory Type 06 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize | 0x800 + # Memory Type 05 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize | 0x100 + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 + !if $(EMULATION) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + !endif + # 462CAA21-7614-4503-836E-8AB6F4662331 (UiApp FILE_GUID) + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ GUID("462CAA21-7614-4503-836E-8AB6F4662331") } + + # 1GB page support + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + + # + # ACPI + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemEnableAcpiSwSmi|0xA0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemDisableAcpiSwSmi|0xA1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"AMD " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20444D41 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x00000001 + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|4 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x0002052D + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdAcpiCpuSsdtProcessorScopeInSb|TRUE + + # NOTE, below PCD should match with gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgFchIoapicId + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x80 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|8 + # NOTE, below PCD should match with gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0xF0 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemEnableAcpiSwSmi + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemDisableAcpiSwSmi + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + !endif + + # Max Cpu constraints + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + + # + # EFI NV Storage + # + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0xA000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0xA000 + + # + # AGESA NBIO + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIommuMMIOAddressReservedEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicMMIOAddressReservedEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdPreDefineEn|TRUE #### Makes PEI assign IOAPIC IDs + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase|0xF0 + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCompliantEdkIIAcpiSdtProtocol|TRUE + + # AGESA FCH + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1EvtBlkAddr|0x800 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1CntBlkAddr|0x804 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr|0x808 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgCpuControlBlkAddr|0x810 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiGpe0BlkAddr|0x820 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemBeforePciRestoreSwSmi|0xB3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemAfterPciRestoreSwSmi|0xB4 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemSpiUnlockSwSmi|0xB7 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemSpiLockSwSmi|0xB8 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemCfgMaxPostPackageRepairEntries|0x3F + + # Disable S3 support + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE + + ## Toggle for whether the VariablePolicy engine should allow disabling. + # The engine is enabled at power-on, but the interface allows the platform to + # disable enforcement for servicing flexibility. If this PCD is disabled, it will block the ability to + # disable the enforcement and VariablePolicy enforcement will always be ON. + # TRUE - VariablePolicy can be disabled by request through the interface (until interface is locked) + # FALSE - VariablePolicy interface will not accept requests to disable and is ALWAYS ON + # @Prompt Allow VariablePolicy enforcement to be disabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdAllowVariablePolicyEnforcementDisable|TRUE + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE + + # TRUE - 5-Level Paging will be enabled. + # FALSE - 5-Level Paging will not be enabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable|FALSE + + # Specifies stack size in bytes for each processor in SMM. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x10000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdAcpiTableHeaderOemId|gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + !if $(EMULATION) == TRUE + # enable IDS prints for emulation to port80 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEmulationAutoDetect|$(IDS_DEBUG_ENABLE) + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdPspRecoveryFlagDetectEnable|FALSE + !endif + + # Secureboot + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE + !endif + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiGpe0BlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1CntBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1EvtBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockLength|0x8 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aEvtBlkAccessSize|0x2 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aCntBlkAccessSize|0x2 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize|0x03 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize|0x1 + + # + # The base address of temporary page table for accessing PCIE MMIO base address above 4G in PEI phase. + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPeiTempPageTableBaseAddress|0x60000000 + !if $(DRAM_BOOT) == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdShellFile|{GUID(68198A68-D249-4826-BC5E-45DF0CCA2A53)} + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc|L"Emulation Linux Loader" + !endif + + # To create MPDMA devices under RB named as PCIx + gAmdCpmPkgTokenSpaceGuid.UsePciXAslName|TRUE + + # + # edk2 Redfish foundation + # + !if $(REDFISH_ENABLE) == TRUE + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePathMatchMode|DEVICE_PATH_MATCH_MAC_NODE + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePathNum|1 + # + # Below is the MAC address of network adapter on EDK2 Emulator platform. + # You can use ifconfig under EFI shell to get the MAC address of network adapter on EDK2 Emulator platform. + # + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePath|{DEVICE_PATH("MAC(005056c00009,0x1)")} + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceAccessModeInBand|True + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishDiscoverAccessModeInBand|True + !endif + + # + # USB Network (Communication Device Class) drivers + # + !if $(USB_NETWORK_SUPPORT) == TRUE + # Set USB NIC Rate Limiting + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableUsbNetworkRateLimiting|TRUE + !endif + +[PcdsDynamicDefault.common] + # + # Set MMIO Above4GB at the 1TB boundary + # + !if $(PCIE_MULTI_SEGMENT) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMmioAbove4GLimit|0x3FFBFFFFFFFF + !else + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMmioAbove4GLimit|0x7FBFFFFFFFF + !endif + + # IO Resource padding in bytes, default 4KB, override to 0. + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIo|0x00 + + # + # Flash NV Storage + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0 + + # + # AGESA FCH + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdHpetEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdHpetMsiDis|FALSE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdNoneSioKbcSupport|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgFchIoapicId|gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + + # Tell AGESA how you want the UART configured for serial output + # FchRTDeviceEnableMap + # < BIT4 - LPC : PcdLpcEnable + # < BIT5 - I2C0 : FchRTDeviceEnableMap[BIT5] + # < BIT6 - I2C1 : FchRTDeviceEnableMap[BIT6] + # < BIT7 - I2C2 : FchRTDeviceEnableMap[BIT7] + # < BIT8 - I2C3 : FchRTDeviceEnableMap[BIT8] + # < BIT9 - I2C4 : FchRTDeviceEnableMap[BIT9] + # < BIT10 - I2C5 : FchRTDeviceEnableMap[BIT10] + # < BIT11 - UART0 : FchRTDeviceEnableMap[BIT11] + # < BIT12 - UART1 : FchRTDeviceEnableMap[BIT12] + # < BIT16 - UART2 : FchRTDeviceEnableMap[BIT13] + # < BIT18 - SD : PcdEmmcEnable and PcdEmmcType < 5 + # < BIT26 - UART3 : FchRTDeviceEnableMap[BIT26] + # < BIT27 - eSPI : PcdEspiEnable - read-only. + # < BIT28 - eMMC : PcdEmmcEnable - read-only. + gEfiAmdAgesaModulePkgTokenSpaceGuid.FchRTDeviceEnableMap|0x00001F60 + # FchUartLegacyEnable + # 0-disable, 1- 0x2E8/2EF, 2 - 0x2F8/2FF, 3 - 0x3E8/3EF, 4 - 0x3F8/3FF + !if $(SERIAL_PORT) == "FCH_IO" + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart0LegacyEnable|0x04 + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart1LegacyEnable|0x03 + !elseif $(SERIAL_PORT) == "BMC_SOL_IO" + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart0LegacyEnable|0x03 + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart1LegacyEnable|0x04 + !endif + + # + # AGESA APCB Recovery + # + # TO-DO: Temporarily disable Apcb Recovery, to suppress debug ASSERT. + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspApcbRecoveryEnable|FALSE + !endif + + # + # AGESA NBIO + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgGnbIoapicId|gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase + + # + # AGESA BMC (NBIO) + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkTraining|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkSocket|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkDie|0 + + !if $(USB_SUPPORT) + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|TRUE + ### USB 3.0 controller1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci1Enable|TRUE + ### USB3.0 controller0 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci2Enable|FALSE + ### USB3.0 controller1 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci3Enable|FALSE + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciSsid|0x00000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhciECCDedErrRptEn|FALSE + !else + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|FALSE + ### USB 3.0 controller1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci1Enable|FALSE + ### USB3.0 controller0 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci2Enable|FALSE + ### USB3.0 controller1 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci3Enable|FALSE + !endif + +!if $(SATA_SUPPORT) + ### @brief FCH-SATA enables + ### @details Select whether or not the FCH Sata controller is active. + ### @li TRUE - This option is active. + ### @li FALSE - This option is turned off. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataStaggeredSpinup|TRUE +!else + ### @brief FCH-SATA enables + ### @details Select whether or not the FCH Sata controller is active. + ### @li TRUE - This option is active. + ### @li FALSE - This option is turned off. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable|FALSE +!endif + + # NVDIMM feature + gEfiAmdAgesaPkgTokenSpaceGuid.PcdNvdimmEnable|FALSE + + # + # Firmware Revision + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(FIRMWARE_REVISION_NUM) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VERSION_STR)" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"$(RELEASE_DATE)" + + # MinPlatformPkg, 1's position enables respective ioapic + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFF + +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel + +[PcdsDynamicHii.X64.DEFAULT] + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x8|4|NV,BS + !endif + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCcxCfgPFEHEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLegacyFree|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCxlProtocolErrorReporting|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCxlComponentErrorReporting|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEgressPoisonSeverityLo|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEgressPoisonSeverityHi|0 + + !ifdef $(INTERNAL_IDS) + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdCcxSingleBitErrLogging|TRUE + !endif + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdS3LibTableSize|0x100000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspAntiRollbackLateSplFuse|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdUsbRSOemConfigurationTable|{0x0D,0x10,0xB1,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x01,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x01,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05} + + # Enable/Disable IOMMU (default TRUE) + # gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgIommuSupport|FALSE + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdIvInfoDmaReMap|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCStateIoBaseAddress|0x813 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdResetMode|0x07 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgSmiCmdPortAddr|0xB2 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdTelemetry_VddcrSocfull_Scale_Current|0x50 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdTelemetry_VddcrVddfull_Scale_Current|0xFF + + !if $(SIMNOW_SUPPORT) == TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdSmuFeatureControlDefines|0x00030000 + !endif + + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemPostPackageRepair|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemBootTimePostPackageRepair|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemRuntimePostPackageRepair|FALSE + !endif + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLpcEnable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{GUID({ 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } })} + gEfiSecurityPkgTokenSpaceGuid.PcdActiveTpmInterfaceType|0x00 + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x70060 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspSystemTpmConfig|0x00 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000 + + # Video resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|768 diff --git a/Platform/AMD/TurinBoard/Include/Dsc/ProjectCommon.inc.dsc b/Platform/AMD/TurinBoard/Include/Dsc/ProjectCommon.inc.dsc new file mode 100644 index 0000000000000000000000000000000000000000..0103df2d41096667a6d602cc8f1274651374e207 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Dsc/ProjectCommon.inc.dsc @@ -0,0 +1,549 @@ +## @file +# +# Copyright (C) 2023 -2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses] + # AML library + AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf + AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf + + # AMD AGESA + AmdCalloutLib|AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf + AmlGenerationLib|AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf + OemAgesaCcxPlatformLib|AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf + PciHostBridgeLib|AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + ResetSystemLib|AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf + !if $(SIMNOW_SUPPORT) == TRUE + AmdPostCodeLib|AgesaModulePkg/Library/AmdPostCodeEmuLib2/AmdPostCodeEmuLib.inf + !endif + + # EDKII Generic + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf + + # MinPlatformPkg + AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + BoardAcpiTableLib|MinPlatformPkg/Acpi/Library/BoardAcpiTableLibNull/BoardAcpiTableLibNull.inf + PlatformBootManagerLib|MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf + + # AMD Platform + PlatformSecLib|AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf + ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf + FchEspiCmdLib|AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf + + # Manageability + IpmiCommandLib|ManageabilityPkg/Library/IpmiCommandLib/IpmiCommandLib.inf + + # SPCR Device + SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf + + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + + !if $(SOURCE_DEBUG_ENABLE) + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + !else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + !endif + + !if $(SERIAL_PORT) == "NONE" + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + + !if $(SIMNOW_PORT80_DEBUG) == TRUE + SerialPortLib|AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf + !endif + + PlatformHookLib|AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf + +!if $(REDFISH_ENABLE) == TRUE + # + # edk2 Redfish foundation + # + !include RedfishPkg/RedfishLibs.dsc.inc + # + # edk2 Redfish foundation platform libraries + # + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceBmcUsbNicLib/PlatformHostInterfaceBmcUsbNicLib.inf + RedfishPlatformCredentialLib|RedfishPkg/Library/PlatformCredentialLibNull/PlatformCredentialLibNull.inf + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf +!endif + +[LibraryClasses.IA32.SEC] + # AGESA + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf + + # MinPlatformPkg + SetCacheMtrrLib|MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf + +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE] + # AGESA + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf + +[LibraryClasses.common.PEIM] + + # MinPlatformPkg + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf + !endif + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf + + # AMD Platform + SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM, LibraryClasses.common.PEI_CORE] + PciLib|MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf + PciSegmentLib|MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf + +[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf + +[LibraryClasses.Common.DXE_DRIVER] + PlatformSocLib|TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf + # MinPlatformPkg + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf + + !if gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable == TRUE + SpiHcPlatformLib|TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf + !else + SpiHcPlatformLib|AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf + !endif + + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf + !endif + + # IPMI Library for invoking IPMI protocol + IpmiLib|MdeModulePkg/Library/DxeIpmiLibIpmiProtocol/DxeIpmiLibIpmiProtocol.inf + +[LibraryClasses.Common.DXE_CORE, LibraryClasses.Common.DXE_DRIVER, LibraryClasses.Common.DXE_SMM_DRIVER] + # MinPlatformPkg + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf + BoardBdsHookLib|AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf + +[LibraryClasses.Common.DXE_SMM_DRIVER] + # EDKII Generic + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf + !endif + + # AMD Platform + AmdPspFlashAccLib|AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf + PlatformPspRomArmorWhitelistLib|AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf + + !if gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable == TRUE + SpiHcPlatformLib|TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf + !else + SpiHcPlatformLib|AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf + !endif +[LibraryClasses.Common.SMM_CORE] + # EDKII Generic + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + +[LibraryClasses.Common.DXE_RUNTIME_DRIVER] + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf + + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + +[Components.IA32] + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc + + # AGESA + AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf { + + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + + # AGESA FCH Platform initialization + !if $(EMULATION) == FALSE + TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf + !endif + + # EDKII Generic + # SEC Core + UefiCpuPkg/SecCore/SecCore.inf { + + SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + } + + # PEIM + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + } + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + + # MinPlatformPkg + MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + BoardInitLib|AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf + } + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf + } + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + + # AMD Platform + !if $(PREDEFINED_FABRIC_RESOURCES) == TRUE + $(PROCESSOR_PATH)/Universal/DfResourcesPei/DfResourcesPei.inf + !endif + +[Components.X64] + !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc + + # CPM + AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf + AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/PspPlatformDriver/PspPlatform.inf + + # MinPlatformPkg + MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { + + BoardInitLib|AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf + } + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf { + + NULL|AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.inf + } + MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf + MinPlatformPkg/Test/TestPointStubDxe/TestPointStubDxe.inf + + # EDKII Generic + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + !if $(SOURCE_DEBUG_ENABLE) + SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf { + + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + } + !endif + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # USB + !if $(USB_SUPPORT) + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + !endif + + # NVME + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(NVME_SUPPORT) == TRUE + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + !endif + + # SATA + !if $(SATA_SUPPORT) + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + !endif + + # SMM + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + !if $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf + !endif + + # + # Disable DEBUG_CACHE because SMI entry/exit may change MTRRs + # + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x801000C7 + } + + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf { + + # AMD Platform SMM Core hook + SmmCorePlatformHookLib|AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf + # SMM core hook for SPI host controller + NULL|AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf + } + + # File System Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + !endif + + # EFI Shell + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + ## NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000 + } + + # Security + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf { + + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf + } + UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf + MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + !endif + + !if $(USE_EMULATED_VARIABLE_STORE) == TRUE + # these modules are included in MinPlatformPkg in + # edk2-platforms\Platform\Intel\MinPlatformPkg\Include\Dsc\CoreDxeInclude.dsc + # removing these modules being loaded by adding depex condition which is + # always false + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + # emulation bios uses emulated variable store + # hence turning off the variable protection feature + AmdCpmPkg/Features/AmdVariableProtection/AmdVariableProtection.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !else + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + !endif + !endif + + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2600GopDxe.inf + !endif + + # ACPI + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + $(PROCESSOR_PATH)/Universal/BoardAcpiDxe/BoardAcpiDxe.inf + AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + !endif + + # SPI + MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf + MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf + AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(USE_EMULATED_VARIABLE_STORE) == FALSE + AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf + MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf + MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf + MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf + !else + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + !endif + + # HII + AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf + + # LOGO + AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf + + # PCI HotPlug + !if gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport == TRUE + AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf + AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf + !endif + + # Turn off post package repair for emulation + !if $(EMULATION) == TRUE + AgesaModulePkg/Mem/AmdMemPprSmmDriver/AmdMemPprSmmDriver.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + EmulationToolsPkg/EmuLinuxLoader/EmuLinuxLoader.inf + !endif + + !include ManageabilityPkg/Include/Manageability.dsc + ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf { + + ManageabilityTransportLib|ManageabilityPkg/Library/ManageabilityTransportKcsLib/Dxe/DxeManageabilityTransportKcs.inf + } + + # + # edk2 Redfish foundation + # +!if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/RedfishComponents.dsc.inc +!endif + + # + # USB Network (Communication Device Class) drivers + # +!if $(USB_NETWORK_SUPPORT) == TRUE + MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf +!endif + +!if $(SIMNOW_SUPPORT) == FALSE && $(EMULATION) == FALSE + AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +!endif + + # + ##For AMD PRM Feature Support## + # + + # + # PRM Libraries + # + PrmPkg/Library/DxePrmContextBufferLib/DxePrmContextBufferLib.inf + + # + # PRM Module Discovery Library + # + PrmPkg/Library/DxePrmModuleDiscoveryLib/DxePrmModuleDiscoveryLib.inf + + # + # PRM PE/COFF Library + # + PrmPkg/Library/DxePrmPeCoffLib/DxePrmPeCoffLib.inf + + # + # PRM Module Loader Driver + # + PrmPkg/PrmLoaderDxe/PrmLoaderDxe.inf + + # + # AMD DICE Protection Environment driver + # + AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf + + # Adds secure boot dependency to AmdVariableProtection feature + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == FALSE + AmdCpmPkg/Features/AmdVariableProtection/AmdVariableProtection.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !endif + +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + # + # PRM Package + # + PrmContextBufferLib|PrmPkg/Library/DxePrmContextBufferLib/DxePrmContextBufferLib.inf + PrmModuleDiscoveryLib|PrmPkg/Library/DxePrmModuleDiscoveryLib/DxePrmModuleDiscoveryLib.inf + PrmPeCoffLib|PrmPkg/Library/DxePrmPeCoffLib/DxePrmPeCoffLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER,LibraryClasses.common.SMM_CORE] + PciExpressLib|MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + MSFT:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + + GCC:*_*_*_CC_FLAGS = -D USE_EDKII_HEADER_FILE + + # Turn off DEBUG messages for Release Builds + GCC:RELEASE_*_*_CC_FLAGS = -D MDEPKG_NDEBUG + INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + + !ifdef $(INTERNAL_IDS) + GCC:*_*_*_CC_FLAGS = -DINTERNAL_IDS + INTEL:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_VFRPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLCC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_PP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_APP_FLAGS = /D INTERNAL_IDS + !endif + + !if $(EMULATION) == TRUE + GCC:*_*_*_CC_FLAGS = -D IDSOPT_PRESILICON_ENABLED=1 + INTEL:*_*_*_CC_FLAGS = /D IDSOPT_PRESILICON_ENABLED=1 + MSFT:*_*_*_CC_FLAGS = /D IDSOPT_PRESILICON_ENABLED=1 + !endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + #Force modules to 4K alignment + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER] + #Force modules to 4K alignment + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + diff --git a/Platform/AMD/TurinBoard/Include/Fdf/FlashMapInclude.fdf b/Platform/AMD/TurinBoard/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000000000000000000000000000000000..725d1880d11c0dfad0f66ef63443579e9831f11b --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,232 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +################################################################################ + +################################################################################ +# +# BIOS image layout +# +################################################################################ +### Flash layout, 16MB and 32MB iamge size with ROM3_FLASH_ENABLE = FALSE +################################################################################ +# Start End Size FV Name +################################################################################ +# 0x00000000 0x0001ffff 0x00020000 None Unused +# 0x00020000 0x00020fff 0x00001000 DATA EFS +# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM +# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW +# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved +# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory +# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory +# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory +# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory +# 0x00700000 0x007d7fff 0x000d8000 FV FVADVANCED +# 0x007d8000 0x0085ffff 0x00088000 FV FVADVANCEDSECURITY +# 0x00860000 0x0090dfff 0x000ae000 FV FVOSBOOT +# 0x0090e000 0x00bfbfff 0x002ee000 FV FVUEFIBOOT +# 0x00bfc000 0x00c27fff 0x0002c000 FV FVSECURITY +# 0x00c28000 0x00c37fff 0x00010000 FV FVPOSTMEMORY +# 0x00c38000 0x00c3ffff 0x00008000 FV FVADVANCEDPREMEMORY +# 0x00c40000 0x00ffffff 0x003c0000 FV FVPREMEMORY +################################################################################ +# Extra padding for 32MB image size +# 0x01000000 0x01ffffff 0x01000000 None unused +################################################################################ +### Flash layout, 32MB with ROM3_FLASH_ENABLE = TRUE +################################################################################ +# Start End Size FV Name +################################################################################ +# 0x00000000 0x0001ffff 0x00020000 None Unused +# 0x00020000 0x00020fff 0x00001000 DATA EFS +# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM +# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW +# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved +# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory +# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory +# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory +# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory +# 0x00bec000 0x00c17fff 0x0002c000 FV FVSECURITY +# 0x00c18000 0x00c37fff 0x00020000 FV FVPOSTMEMORY +# 0x00c38000 0x00c3ffff 0x00008000 FV FVADVANCEDPREMEMORY +# 0x00c40000 0x00ffffff 0x003c0000 FV FVPREMEMORY +# 0x01000000 0x010d7fff 0x000d8000 FV FVADVANCED +# 0x010d8000 0x0115ffff 0x00088000 FV FVADVANCEDSECURITY +# 0x01160000 0x0120dfff 0x000ae000 FV FVOSBOOT +# 0x0120e000 0x014fbfff 0x002ee000 FV FVUEFIBOOT +# 0x01fff000 0x01ffffff 0x00001000 None Unused +################################################################################ + + DEFINE ROM2_FLASH_BASE = 0xFF000000 + DEFINE ROM2_FLASH_SIZE = 0x01000000 + DEFINE ROM3_FLASH_SIZE = 0x02000000 + DEFINE SPI_BLOCK_SIZE = 0x1000 + + !ifndef BUILD_16MB_IMAGE + DEFINE BUILD_16MB_IMAGE = FALSE + !endif + !ifndef ROM3_FLASH_ENABLE + DEFINE ROM3_FLASH_ENABLE = FALSE + !endif + !ifndef ROM3_FLASH_BASE + DEFINE ROM3_FLASH_BASE = 0xFD02000000 + !endif + + !if $(BUILD_16MB_IMAGE) == TRUE + DEFINE SPI_NUM_BLOCKS = 0x1000 + !else + DEFINE SPI_NUM_BLOCKS = 0x2000 + !endif + !if ($(ROM3_FLASH_ENABLE) == TRUE) && ($(BUILD_16MB_IMAGE) == TRUE) + !error "ROM3 cannot be enabled on 16MB image" + !endif + + !ifndef FV_PRE_MEMORY_SIZE + # requires changes in PspData also + DEFINE FV_PRE_MEMORY_SIZE = 0x003C0000 + !endif + !ifndef FV_ADVANCED_PRE_MEMORY_SIZE + DEFINE FV_ADVANCED_PRE_MEMORY_SIZE = 0x00008000 + !endif + !ifndef FV_POST_MEMORY_SIZE + !if ($(ROM3_FLASH_ENABLE) == TRUE) + # Need extra space for DxeMain + DEFINE FV_POST_MEMORY_SIZE = 0x00020000 + !else + DEFINE FV_POST_MEMORY_SIZE = 0x00010000 + !endif + !endif + !ifndef FV_SECURITY_SIZE + DEFINE FV_SECURITY_SIZE = 0x0002C000 + !endif + !ifndef FV_UEFI_BOOT_SIZE + DEFINE FV_UEFI_BOOT_SIZE = 0x002EE000 + !endif + !ifndef FV_OS_BOOT_SIZE + DEFINE FV_OS_BOOT_SIZE = 0x000AE000 + !endif + !ifndef FV_ADVANCED_SECURITY_SIZE + DEFINE FV_ADVANCED_SECURITY_SIZE = 0x00088000 + !endif + !ifndef FV_ADVANCED_SIZE + DEFINE FV_ADVANCED_SIZE = 0x000D8000 + !endif + + DEFINE FV_FW_SIG_OFFSET = 0x00020000 + DEFINE FV_FW_SIG_SIZE = 0x00001000 + + DEFINE NVRAM_AREA_VAR_OFFSET = 0x00021000 + DEFINE NVRAM_AREA_VAR_SIZE = 0x0003E000 + DEFINE NVRAM_AREA_SIZE = 0x00080000 + + DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE) + DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE) + + DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE) +# NOTE: +# +# BOOT_FV_BASE value should match with the PspData.xml ResetImage address +# e.g. +# +# +# +# +# Also note that C40000 from 0x76C40000 came from PcdFlashFvPreMemoryOffset +# if PcdFlashFvPreMemoryOffset gets changed then the below value should also +# need to be change. +# +!ifndef BOOT_FV_BASE + DEFINE BOOT_FV_BASE = 0x76C40000 +!endif + +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000 +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE) + +# +# FV offset and size assignment +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = $(FV_PRE_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = ($(ROM2_FLASH_SIZE) - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = $(FV_ADVANCED_PRE_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = $(FV_POST_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = $(FV_SECURITY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + +!if $(ROM3_FLASH_ENABLE) == FALSE + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) + + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset - gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + # NOTE: + # for ROM3_FLASH_ENABLE disabled BIOS image max address (PcdFlashFvAdvancedSize + PcdFlashFvAdvancedOffset) + # should not overlap with BIOS DIR2 offset + size in PspData.xml + # e.g + # + # +!endif + +!if $(ROM3_FLASH_ENABLE) == TRUE + # if ROM3 is enabled then continue the offset update + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = $(ROM2_FLASH_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE) + + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE) + # NOTE: + # for ROM3_FLASH_ENABLE enabled BIOS image max address (PcdFlashFvSecuritySize + PcdFlashFvSecurityOffset) + # should not overlap with BIOS DIR2 offset + size in PspData.xml + # e.g + # +!endif + +SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE) + +!if $(ROM3_FLASH_ENABLE) == TRUE + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +!endif + + diff --git a/Platform/AMD/TurinBoard/Include/Fdf/Platform.inc.fdf b/Platform/AMD/TurinBoard/Include/Fdf/Platform.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..5fd2d48c510bd11cdcc2f9ee841a010656da90e4 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/Platform.inc.fdf @@ -0,0 +1,20 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +!ifdef $(INTERNAL_IDS) + DEFINE AGESA_PEI_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.pei.inc.fdf + DEFINE AGESA_DXE_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.dxe.inc.fdf +!else + DEFINE AGESA_PEI_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.pei.inc.fdf + DEFINE AGESA_DXE_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.dxe.inc.fdf +!endif +!ifndef CPM_DIR_PATH + CPM_DIR_PATH = $(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR) +!endif +DEFINE CPM_PEI_INC_FDF = AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(CPM_DIR_PATH)$(PLATFORM_CRB)Pkg.pei.inc.fdf +DEFINE CPM_DXE_INC_FDF = AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(CPM_DIR_PATH)$(PLATFORM_CRB)Pkg.dxe.inc.fdf diff --git a/Platform/AMD/TurinBoard/Include/Fdf/PlatformEfs.inc.fdf b/Platform/AMD/TurinBoard/Include/Fdf/PlatformEfs.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..0045bfcb2a5955c22e4f6bc8dc11428bf93f23c4 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/PlatformEfs.inc.fdf @@ -0,0 +1,8 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + diff --git a/Platform/AMD/TurinBoard/Include/Fdf/ProjectCommon.inc.fdf b/Platform/AMD/TurinBoard/Include/Fdf/ProjectCommon.inc.fdf new file mode 100644 index 0000000000000000000000000000000000000000..8e01c909d275af28fb849d3aeb83dfc2313c698e --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/ProjectCommon.inc.fdf @@ -0,0 +1,908 @@ +## @file +# +# Copyright (C) 2023 -2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# EFS multi gen is 32bit value +!ifndef EFS_MULTI_GEN_BYTE0 + DEFINE EFS_MULTI_GEN_BYTE0 = 0xE3 +!endif + +# EFS PSP address, 32-bit value, 0x000A1000 +!ifndef EFS_PSP_ADDR_BYTE0 + DEFINE EFS_PSP_ADDR_BYTE0 = 0x00 +!endif +!ifndef EFS_PSP_ADDR_BYTE1 + DEFINE EFS_PSP_ADDR_BYTE1 = 0x10 +!endif +!ifndef EFS_PSP_ADDR_BYTE2 + DEFINE EFS_PSP_ADDR_BYTE2 = 0x0A +!endif +!ifndef EFS_PSP_ADDR_BYTE3 + DEFINE EFS_PSP_ADDR_BYTE3 = 0x00 +!endif + +# EFS BIOS address, 32-bit value, 0x002E3000 +!ifndef EFS_BIOS_ADDR_BYTE0 + DEFINE EFS_BIOS_ADDR_BYTE0 = 0x00 +!endif +!ifndef EFS_BIOS_ADDR_BYTE1 + DEFINE EFS_BIOS_ADDR_BYTE1 = 0x30 +!endif +!ifndef EFS_BIOS_ADDR_BYTE2 + DEFINE EFS_BIOS_ADDR_BYTE2 = 0x2E +!endif +!ifndef EFS_BIOS_ADDR_BYTE3 + DEFINE EFS_BIOS_ADDR_BYTE3 = 0x00 +!endif + +# EFS ESPI defination +!ifndef EFS_ESPI_BYTE0 + DEFINE EFS_ESPI_BYTE0 = 0x0E +!endif +!ifndef EFS_ESPI_BYTE1 + DEFINE EFS_ESPI_BYTE1 = 0xFF +!endif + +[FD.Platform] + # Need ROM 2 flash base for calculated Addresses of FVs below 4GB + BaseAddress = $(ROM2_FLASH_BASE)|gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + # Need full flash size for FD Image size + !if $(BUILD_16MB_IMAGE) == TRUE + Size = $(ROM2_FLASH_SIZE) + !else + Size = $(ROM3_FLASH_SIZE) + !endif + ErasePolarity = 1 + BlockSize = $(SPI_BLOCK_SIZE) + NumBlocks = $(SPI_NUM_BLOCKS) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = $(ROM2_FLASH_SIZE) + SET gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaBase = $(ROM3_FLASH_BASE) + SET gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaSize = $(ROM3_FLASH_SIZE) + + # + # Embedded Firmware Signature + # + $(FV_FW_SIG_OFFSET)|$(FV_FW_SIG_SIZE) +!ifdef EMBEDDED_FIRMWARE_SIGNATURE + !include $(PROCESSOR_PATH)/Include/Fdf/PlatformEfs.inc.fdf +!else + DATA = { + 0xAA, 0x55, 0xAA, 0x55, # 0x00: Signature + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_PSP_ADDR_BYTE0), # + $(EFS_PSP_ADDR_BYTE1), # + $(EFS_PSP_ADDR_BYTE2), # + $(EFS_PSP_ADDR_BYTE3), # 0x14: PSP Dir1 + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_MULTI_GEN_BYTE0), # + 0xFF, 0xFF, 0xFF, # 0x24: BRH 4:0 as 00011b + $(EFS_BIOS_ADDR_BYTE0), # + $(EFS_BIOS_ADDR_BYTE1), # + $(EFS_BIOS_ADDR_BYTE2), # + $(EFS_BIOS_ADDR_BYTE3), # 0x28: BIOS Dir1 + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # 0x40 + 0xFF, 0xFF, 0xFF, 0xFF, # + 0xFF, 0xFF, 0xFF, 0xFF, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_ESPI_BYTE0), # + $(EFS_ESPI_BYTE1), # + 0xFF, 0xFF # 0x50: eSPI0 Configuration + # Default value = 0x0E (eSPI0, bus1, Alert mode, Port 80h, CLK1) + # + # bit[0]: eSPI PSP configuration valid bit. + # 0-Valid, 1-Not Valid + # bit[1]: enable 80h port. + # 0-disable, 1-enable + # bit[2]: Alert mode. + # 0-non-Alert, 1-dedicated Alert Pin. + # bit[3]: Data Bus, + # 0-bus0, 1-bus1. + # bit[4]: Clock pin. ignore for controller0 (always CLK0). + # for controller1, 0-CLK1, 1-CLK2 + # bit[7:5]: reserved + # 0x51: eSPI1 Configuration + # bit[0]: eSPI PSP configuration valid bit. + # 0-Valid, 1-Not Valid + # bit[1]: enable 80h port. + # 0-disable, 1-enable + # bit[2]: Alert mode. + # 0-non-Alert, 1-dedicated Alert Pin. + # bit[3]: Data Bus, + # 0-bus0, 1-bus1. + # bit[4]: Clock pin. ignore for controller0 (always CLK0). + # for controller1, 0-CLK1, 1-CLK2 + # bit[7:5]: reserved + } +!endif + # + # PSP NVRAM: NV Storage Area + # NV_VARIABLE_STORE + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x80 Blocks * 0x1000 Bytes / Block + 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End (null-terminated) + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + # Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + # Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + + # + # NV_FTW_WORKING + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, + # { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0x2C, 0xAF, 0x2C, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x1000(SPI_BLOCK_SIZE) - 0x20 (FTW_WORKING_HEADER) = 0x0FE0 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + + # + # NV_FTW_SPARE + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + + # Advance firmware volume where advance Board features are enabled. + !if $(ROM3_FLASH_ENABLE) == FALSE + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + FV = FvAdvancedSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + FV = FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + FV = FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize + FV = FvAdvancedPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + FV = FvPreMemory + + !if $(ROM3_FLASH_ENABLE) == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + FV = FvAdvancedSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + + # Fill unused space to create 32 MB FD image + $(ROM3_FLASH_SIZE) - 0x1000|0x1000 + + !elseif $(BUILD_16MB_IMAGE) == FALSE + # Fill unused space to create 32 MB FD image + 0x01000000|0x01000000 + !endif + +[FV.FvPreMemory] + FvNameGuid = 1BD2AB8A-BD04-4ee1-83B0-B05E5500121D + FvBaseAddress = $(BOOT_FV_BASE) + FvForceRebase = TRUE + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + + APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + } + + # SEC Core + INF UefiCpuPkg/SecCore/SecCore.inf + + # PEI Core + INF MdeModulePkg/Core/Pei/PeiMain.inf + + !include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf + INF AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf + + !if $(PREDEFINED_FABRIC_RESOURCES) == TRUE + INF $(PROCESSOR_PATH)/Universal/DfResourcesPei/DfResourcesPei.inf + !endif + + !if $(EMULATION) == FALSE + INF TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf + !endif + + # PEIM + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + # INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf + # INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf + + # AMD AGESA, CPM PEI Includes + !include $(CPM_PEI_INC_FDF) + !include $(AGESA_PEI_INC_FDF) + +[FV.FvAdvancedPreMemory] + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 87F76F65-4128-4B77-85D8-DE0F757B40F8 + + # !include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvPostMemoryUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 09F55EB9-7181-4919-8755-9185E3E35CA9 + + !include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf + + # Init Board Config PCD + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + +[FV.FvPostMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 3445B977-C771-4928-9851-2EFBD55CAACD + + FILE FV_IMAGE = F38D7A3E-35F1-4CE4-ACC8-AA059ABEA622{ + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvPostMemoryUncompact + } + } + !if $(ROM3_FLASH_ENABLE) == TRUE + FILE FV_IMAGE = 8DA879CE-D6D0-4687-8025-0EA967F506BD { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvDxeMain + } + } + !endif + +[FV.FvUefiBootUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = E889A6E3-385B-4DAF-A19A-E9B1D41EB046 + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + } + !include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf + + # AMD AGESA, CPM DXE Includes + !include $(CPM_DXE_INC_FDF) + !include $(AGESA_DXE_INC_FDF) + + + # AMD PRM feature support + INF PrmPkg/PrmLoaderDxe/PrmLoaderDxe.inf + + # EDK Core modules + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + !if $(SOURCE_DEBUG_ENABLE) + INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf + !endif + + # File System Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + !endif + + # Console + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2600GopDxe.inf + !endif + + INF AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf + INF AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf + + INF AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/PspPlatformDriver/PspPlatform.inf + + # UEFI Shell + !if $(SHELL_BIN_PACKAGE) + INF ShellBinPkg/UefiShell/UefiShell.inf + !else + INF ShellPkg/Application/Shell/Shell.inf + !endif + + # AmdHiiConfigRouting + INF AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf + + # PCI + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # SATA + !if $(SATA_SUPPORT) + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + !endif + + # NVME + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(NVME_SUPPORT) == TRUE + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + !endif + + # USB + !if $(USB_SUPPORT) + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + !endif + + # SMBIOS + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + INF AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf + + # Board + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + INF MinPlatformPkg/Test/TestPointStubDxe/TestPointStubDxe.inf + + # Spi Flash Drivers + INF AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf + INF MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf + INF MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(USE_EMULATED_VARIABLE_STORE) == FALSE + INF AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf + INF MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf + INF MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf + INF AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + INF MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + INF AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf + + !else + INF AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + !endif + + # SMM Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == TRUE + # putting under conditional flag to avoid loading modules again(second time). + # MinPlatformPkg already has these modules included if + # gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + # in CoreOsBootInclude.fdf + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf + !endif + INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + + !if $(EMULATION) == TRUE + INF EmulationToolsPkg/EmuLinuxLoader/EmuLinuxLoader.inf + !endif + + !if $(USE_EMULATED_VARIABLE_STORE) == TRUE && gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + !endif + + # + # edk2 Redfish Foundation + # +!if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.fdf.inc +!endif + + # + # USB Network (Communication Device Class) drivers + # +!if $(USB_NETWORK_SUPPORT) == TRUE + INF MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + INF MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf +!endif +!if $(SIMNOW_SUPPORT) == FALSE && $(EMULATION) == FALSE + INF AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +!endif + + # + # DICE Protection Environment driver + # + INF AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf + +[FV.FvUefiBoot] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 5489442E-30C6-479F-9CA4-BAAAEE279A20 + + FILE FV_IMAGE = B5733BA8-C486-4B0F-889C-0815F483450A { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 48FD70BC-3389-4B90-A364-EF829F41DB70 + + !include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + INF RuleOverride = DRIVER_ACPITABLE $(PROCESSOR_PATH)/Universal/BoardAcpiDxe/BoardAcpiDxe.inf + INF AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + !endif + +[FV.FvLateSilicon] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = C3740903-41CC-4C7E-B9A1-7A4B59C0CEC2 + +[FV.FvOsBoot] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 7E097F4E-A40F-47D4-93FB-8802BB9051C0 + + FILE FV_IMAGE = B975908C-6ECF-4413-A87A-199DDA11AB37 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + FILE FV_IMAGE = 41077C2D-331A-4188-809A-E5278A534E51 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvLateSilicon + } + } + +[FV.FvSecurityPreMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 87E97057-5DEF-4EB3-ACC5-063AC68AA7B7 + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvSecurityPostMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = FBA1BC9C-66FD-4B05-887C-C00AB6DDEE1F + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + INF MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + +[FV.FvSecurityLate] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 79045073-CB0E-4E28-BC31-4AE00FBF4907 + + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + INF MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf + INF UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + !endif + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + INF AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf + + FILE FREEFORM = 85254ea7-4759-4fc4-82d4-5eed5fb0a4a0 { + SECTION RAW = SecurebootKeys/PK/PK.cer + } + + FILE FREEFORM = 6f64916e-9f7a-4c35-b952-cd041efb05a3 { + SECTION RAW = SecurebootKeys/KEK/MicCorKEKCA2011_2011-06-24.crt + } + + FILE FREEFORM = c491d352-7623-4843-accc-2791a7574421 { + SECTION RAW = SecurebootKeys/db/MicWinProPCA2011_2011-10-19.crt + SECTION RAW = SecurebootKeys/db/MicCorUEFCA2011_2011-06-27.crt + } + + FILE FREEFORM = 5740766a-718e-4dc0-9935-c36f7d3f884f { + SECTION RAW = SecurebootKeys/dbx/dbxupdate_x64.bin + } + + !endif + +[FV.FvSecurity] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 2D25F4E7-50AB-442C-B2AE-9C48F3116E62 + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE = FvSecurityPreMemory + } + !endif + + FILE FV_IMAGE = 7E21EF3C-D813-40C0-BE9E-A5F739CA88AC { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityPostMemory + } + } + +[FV.FvAdvancedSecurity] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 2FFD72AF-4917-4430-8A46-97BD74816264 + + FILE FV_IMAGE = B431E18D-A610-4A65-8D81-A4E482354EF8 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +[FV.FvAdvancedUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 9DC9F824-7D1E-4A81-A410-CE3CA6ABA779 + + # Enable Manageabilty modules, such as IPMI Driver + !include ManageabilityPkg/Include/PostMemory.fdf + + # + # Network Advanced Features + # + !if gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable == TRUE + !include Network/NetworkFeaturePkg/Include/PostMemory.fdf + !endif + + # LOGO + INF AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf + + # PCI HotPlug + !if gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport == TRUE + INF AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf + INF AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf + !endif + + # SPCR + !if gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable == TRUE + !include SpcrFeaturePkg/Include/PostMemory.fdf + !endif + +[FV.FvAdvanced] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = FC5D42FA-964F-47D5-9D53-35D997F1B83E + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedUncompact + } + } + +[FV.FvDxeMain] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = AF85B2E1-DC13-445A-AF0F-C7659E39BBAC + + INF MdeModulePkg/Core/Dxe/DxeMain.inf diff --git a/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c new file mode 100644 index 0000000000000000000000000000000000000000..7ae3ca5e8c2ca48de29bc641457c6fcac6658521 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c @@ -0,0 +1,940 @@ +/** @file + + Implements AMD Turin Platform SoC Library. + Provides interface to Get Set platform specific data. + + Copyright (C) 2023 -2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_IOAPIC_NUM 0x20 + +/** + Obtains proximity domain for given PciAddress, + provided in BDF format. + + Calls AGESA fabric service to obtain domain information. + + @param[in] SocketID - SocketID of the provided PciAddress + @param[in] PciAddress - PCI Address of the device + + @retval SocketID, if fails to get data from fabric service, else + PXM value. +**/ +UINTN +GetPxmDomain ( + IN UINT8 SocketId, + IN PCI_ADDR PciAddress + ) +{ + FABRIC_NUMA_SERVICES2_PROTOCOL *FabricNumaServices; + EFI_STATUS Status; + PXM_DOMAIN_INFO PxmDomainInfo; + + Status = gBS->LocateProtocol (&gAmdFabricNumaServices2ProtocolGuid, NULL, (VOID **)&FabricNumaServices); + if (EFI_ERROR (Status)) { + return SocketId; + } + + ZeroMem ((VOID *)&PxmDomainInfo, sizeof (PxmDomainInfo)); + Status = FabricNumaServices->GetPxmDomainInfo (FabricNumaServices, PciAddress, &PxmDomainInfo); + if (EFI_ERROR (Status)) { + return SocketId; + } + + ASSERT (PxmDomainInfo.Count == 1); + return PxmDomainInfo.Domain[0]; +} + +/** + @brief Get the PCIe CXL2 Info object + + NOTE: Caller will need to free structure once finished. + + @param[in, out] CxlPortInfo The CXL port information + @param[in, out] CxlCount Number of CXL port present + + @retval EFI_SUCCESS Successfully retrieve the CXL port information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +GetPcieCxl2Info ( + IN OUT AMD_CXL_PORT_INFO **CxlPortInfo, + IN OUT UINTN *CxlCount + ) +{ + UINTN CxlRbSupportCount; + EFI_STATUS Status; + PCIE_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + AMD_CXL_PORT_INFO *LocalCxlPortInfoHead; + AMD_CXL_PORT_INFO *LocalCxlPortInfo; + + if ((CxlPortInfo == NULL) || (CxlCount == NULL)) { + return EFI_INVALID_PARAMETER; + } + + CxlRbSupportCount = 0; + LocalCxlPortInfoHead = NULL; + + // Collecting Pcie information from Hob + Status = PcieGetPcieDxe (&Pcie); + if (!EFI_ERROR (Status)) { + GnbHandle = NbioGetHandle (Pcie); + while (GnbHandle != NULL) { + if ((GnbHandle->Header.DescriptorFlags & SILICON_CXL_CAPABLE) == SILICON_CXL_CAPABLE) { + CxlRbSupportCount++; + } + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + if (CxlRbSupportCount > 0) { + LocalCxlPortInfoHead = AllocateZeroPool (sizeof (AMD_CXL_PORT_INFO) * CxlRbSupportCount); + if (LocalCxlPortInfoHead == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + GnbHandle = NbioGetHandle (Pcie); + // + // The code below will get all the root bridges with CXL 2.0 support + // We need to add the CXL ACPI method to all of them + // + LocalCxlPortInfo = LocalCxlPortInfoHead; + while (GnbHandle != NULL) { + if ((GnbHandle->Header.DescriptorFlags & SILICON_CXL_CAPABLE) == SILICON_CXL_CAPABLE) { + LocalCxlPortInfo->EndPointBDF.AddressValue = GnbHandle->Address.AddressValue; + LocalCxlPortInfo->IsCxl2 = TRUE; + LocalCxlPortInfo++; + } + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + } + + *CxlCount = CxlRbSupportCount; + *CxlPortInfo = LocalCxlPortInfoHead; + if (CxlRbSupportCount == 0) { + return EFI_NOT_FOUND; + } + } else { + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + @brief Get the Pcie Cxl Info object + + NOTE: Caller will need to free structure once finished. + + @param[in, out] CxlPortInfo The CXL port information + @param[in, out] CxlCount Number of CXL port present + + @retval EFI_SUCCESS Successfully retrieve the CXL port information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetPcieCxlInfo ( + IN OUT AMD_CXL_PORT_INFO **CxlPortInfo, + IN OUT UINTN *CxlCount + ) +{ + EFI_STATUS Status; + AMD_NBIO_CXL_SERVICES_PROTOCOL *AmdNbioCxlServicesProtocol; + UINT8 Index; + AMD_CXL_PORT_INFO *CxlPortInfoHead; + AMD_CXL_PORT_INFO *LocalCxlPortInfo; + AMD_CXL_PORT_INFO_STRUCT NbioPortInfo; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + + // Check for CXL 2.0 first + Status = GetPcieCxl2Info (CxlPortInfo, CxlCount); + if (!EFI_ERROR (Status) && (*CxlCount > 0)) { + return Status; + } + + AmdNbioCxlServicesProtocol = NULL; + + Status = gBS->LocateProtocol ( + &gAmdNbioCxlServicesProtocolGuid, + NULL, + (VOID **)&AmdNbioCxlServicesProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Failed to locate AmdNbioCxlServices Protocol: %r\n", __func__, Status)); + Status = EFI_SUCCESS; + return Status; + } + + CxlPortInfoHead = AllocateZeroPool (sizeof (AMD_CXL_PORT_INFO) * AmdNbioCxlServicesProtocol->CxlCount); + if (CxlPortInfoHead == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // + // Populate the data structure for the CXL devices in the system to add to + // the ACPI Table + // + for (Index = 0, LocalCxlPortInfo = CxlPortInfoHead; Index < AmdNbioCxlServicesProtocol->CxlCount; Index++, LocalCxlPortInfo++) { + Status = AmdNbioCxlServicesProtocol->CxlGetRootPortInformation ( + AmdNbioCxlServicesProtocol, + Index, + &NbioPortInfo + ); + if (Status != EFI_SUCCESS) { + break; + } + + LocalCxlPortInfo->EndPointBDF.AddressValue = NbioPortInfo.EndPointBDF.AddressValue; + if (NbioPortInfo.DsRcrb == 0) { + LocalCxlPortInfo->IsCxl2 = TRUE; + } else { + LocalCxlPortInfo->IsCxl2 = FALSE; + } + } + + *CxlPortInfo = CxlPortInfoHead; + *CxlCount = AmdNbioCxlServicesProtocol->CxlCount; + return EFI_SUCCESS; +} + +/** + Get the platform specific IOAPIC information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] IoApicInfo The IOAPIC information + @param[in, out] IoApicCount Number of IOAPIC present + + @retval EFI_SUCCESS Successfully retrieve the IOAPIC information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetIoApicInfo ( + IN OUT EFI_ACPI_6_5_IO_APIC_STRUCTURE **IoApicInfo, + IN OUT UINT8 *IoApicCount + ) +{ + EFI_STATUS Status; + DXE_AMD_NBIO_PCIE_SERVICES_PROTOCOL *PcieServicesProtocol; + PCIE_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + GNB_PCIE_INFORMATION_DATA_HOB *PciePlatformConfigHobData; + UINT32 Value32; + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApic; + UINT8 LocalIoApicCount; + IO_APIC_IDENTIFICATION_REGISTER IoApicIdentificationRegister; + UINT32 GlobalSystemInterruptBase; + IO_APIC_VERSION_REGISTER IoApicVersionRegister; + + if ((IoApicCount == NULL) || (IoApicInfo == NULL)) { + return EFI_INVALID_PARAMETER; + } + + IoApic = AllocateZeroPool (sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE) * MAX_IOAPIC_NUM); + if (IoApic == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a:%d Not enough memory to allocate EFI_ACPI_6_5_IO_APIC_STRUCTURE\n", + __func__, + __LINE__ + )); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // FCH IO APIC + GlobalSystemInterruptBase = 0; + MmioWrite8 ( + PcdGet32 (PcdIoApicAddress) + IOAPIC_INDEX_OFFSET, + IO_APIC_VERSION_REGISTER_INDEX + ); + IoApicVersionRegister.Uint32 = MmioRead32 (PcdGet32 (PcdIoApicAddress) + IOAPIC_DATA_OFFSET); + GlobalSystemInterruptBase += IoApicVersionRegister.Bits.MaximumRedirectionEntry + 1; + Status = gBS->LocateProtocol ( + &gAmdNbioPcieServicesProtocolGuid, + NULL, + (VOID **)&PcieServicesProtocol + ); + if (!EFI_ERROR (Status)) { + PcieServicesProtocol->PcieGetTopology (PcieServicesProtocol, (UINT32 **)&PciePlatformConfigHobData); + Pcie = &(PciePlatformConfigHobData->PciePlatformConfigHob); + GnbHandle = NbioGetHandle (Pcie); + LocalIoApicCount = 0; + IoApic[LocalIoApicCount].Type = EFI_ACPI_6_5_IO_APIC; + IoApic[LocalIoApicCount].Length = sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE); + IoApic[LocalIoApicCount].IoApicId = PcdGet8 (PcdIoApicId); + IoApic[LocalIoApicCount].Reserved = 0; + IoApic[LocalIoApicCount].IoApicAddress = PcdGet32 (PcdIoApicAddress); + IoApic[LocalIoApicCount].GlobalSystemInterruptBase = 0; + LocalIoApicCount++; + while (GnbHandle != NULL) { + // Fill the header + IoApic[LocalIoApicCount].Type = EFI_ACPI_6_5_IO_APIC; + IoApic[LocalIoApicCount].Length = sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE); + IoApic[LocalIoApicCount].Reserved = 0; + // Read IOAPIC Address + if (GnbHandle->RBIndex < 4) { + SmnRegisterReadS ( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + NBIO_SPACE (GnbHandle, SMN_IOHUB0NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS), + &Value32 + ); + } else { + SmnRegisterReadS ( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + NBIO_SPACE (GnbHandle, SMN_IOHUB1NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS), + &Value32 + ); + } + + IoApic[LocalIoApicCount].IoApicAddress = Value32 & IOAPIC_BASE_ADDR_LO_IOAPIC_BASE_ADDR_LO_MASK; + + // Set APIC ID + MmioWrite8 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_INDEX_OFFSET, + IO_APIC_IDENTIFICATION_REGISTER_INDEX + ); + IoApicIdentificationRegister.Uint32 = MmioRead32 (IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_DATA_OFFSET); + IoApic[LocalIoApicCount].IoApicId = (UINT8)IoApicIdentificationRegister.Bits.Identification; + + // Get Read the number of redirection entries in this IOAPIC + MmioWrite8 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_INDEX_OFFSET, + IO_APIC_VERSION_REGISTER_INDEX + ); + IoApicVersionRegister.Uint32 = MmioRead32 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_DATA_OFFSET + ); + // Set Global System Interrupt Base + IoApic[LocalIoApicCount].GlobalSystemInterruptBase = GlobalSystemInterruptBase; + GlobalSystemInterruptBase += IoApicVersionRegister.Bits.MaximumRedirectionEntry + 1; + + LocalIoApicCount++; + GnbHandle = GnbGetNextHandle (GnbHandle); + } + } + + *IoApicInfo = IoApic; + *IoApicCount = LocalIoApicCount; + return EFI_SUCCESS; +} + +/** + Get the platform PCIe configuration information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] RootBridge The root bridge information + @param[in, out] RootBridgeCount Number of root bridges present + + @retval EFI_SUCCESS Successfully retrieve the root bridge information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetPcieInfo ( + IN OUT AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE **RootBridge, + IN OUT UINTN *RootBridgeCount + ) +{ + EFI_STATUS Status; + UINTN NumberOfRootBridges; + UINTN RbIndex; + UINTN Index; + UINTN CxlIndex; + AMD_PCI_RESOURCES_PROTOCOL *AmdPciResources; + AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE *LocalRootBridgeArray; // do not free + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApicInfo; + UINT8 IoApicCount; + AMD_CXL_PORT_INFO *CxlPortInfoHead; + AMD_CXL_PORT_INFO *CxlPortInfo; + UINTN CxlCount; + PCI_ADDR PciAddr; + + IoApicInfo = NULL; + IoApicCount = 0; + Status = GetIoApicInfo (&IoApicInfo, &IoApicCount); + if (EFI_ERROR (Status) || (IoApicInfo == NULL) || (IoApicCount == 0)) { + DEBUG ((DEBUG_ERROR, "%a:%d Cannot obtain NBIO IOAPIC information.\n", __func__, __LINE__)); + return EFI_NOT_FOUND; + } + + Status = gBS->LocateProtocol ( + &gAmdPciResourceProtocolGuid, + NULL, + (VOID **)&AmdPciResources + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to locate AMD PCIe Resource Protocol: %r\n", + __func__, + Status + )); + return Status; + } + + Status = AmdPciResources->AmdPciResourcesGetNumberOfRootBridges ( + AmdPciResources, + &NumberOfRootBridges + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to get Number Of Root Bridges: %r\n", + __func__, + Status + )); + return Status; + } + + LocalRootBridgeArray = AllocateZeroPool (sizeof (AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE) * NumberOfRootBridges); + if (LocalRootBridgeArray == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // Collect CXL info + CxlPortInfoHead = NULL; + CxlCount = 0; + Status = GetPcieCxlInfo (&CxlPortInfoHead, &CxlCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "[INFO] Cannot find CXL device.\n")); + } + + // Collect Root Bridges to be sorted + for (RbIndex = 1; RbIndex <= NumberOfRootBridges; RbIndex++) { + Status = AmdPciResources->AmdPciResourcesGetRootBridgeInfo (AmdPciResources, RbIndex, (PCI_ROOT_BRIDGE_OBJECT **)&LocalRootBridgeArray[RbIndex - 1].Object); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to get Root Bridges information : %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + if (CxlPortInfoHead != NULL) { + FreePool (CxlPortInfoHead); + } + + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + + // Assign GSI values + LocalRootBridgeArray[RbIndex - 1].GlobalInterruptStart = IoApicInfo[RbIndex].GlobalSystemInterruptBase; + + // Get PXM info + ZeroMem ((VOID *)&PciAddr, sizeof (PciAddr)); + PciAddr.Address.Bus = (UINT32)LocalRootBridgeArray[RbIndex - 1].Object->BaseBusNumber; + PciAddr.Address.Segment = (UINT32)LocalRootBridgeArray[RbIndex - 1].Object->Segment; + LocalRootBridgeArray[RbIndex - 1].PxmDomain = GetPxmDomain (LocalRootBridgeArray[RbIndex - 1].Object->SocketId, PciAddr); + + // check for CXL port + if (CxlCount > 0) { + for (CxlIndex = 0, CxlPortInfo = CxlPortInfoHead; CxlIndex < CxlCount; CxlIndex++, CxlPortInfo++) { + if ((CxlPortInfo->EndPointBDF.Address.Segment == LocalRootBridgeArray[RbIndex - 1].Object->Segment) && + (CxlPortInfo->EndPointBDF.Address.Bus == LocalRootBridgeArray[RbIndex - 1].Object->BaseBusNumber)) + { + LocalRootBridgeArray[RbIndex - 1].CxlCount = 1; + LocalRootBridgeArray[RbIndex - 1].CxlPortInfo.IsCxl2 = CxlPortInfo->IsCxl2; + LocalRootBridgeArray[RbIndex - 1].CxlPortInfo.EndPointBDF.AddressValue = CxlPortInfo->EndPointBDF.AddressValue; + break; + } + } + } + + Status = AmdPciResources->AmdPciResourcesGetNumberOfRootPorts ( + AmdPciResources, + LocalRootBridgeArray[RbIndex - 1].Object->Index, + &LocalRootBridgeArray[RbIndex - 1].RootPortCount + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: GetNumberOfRootPorts Failed: %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + + for (Index = 1; Index <= LocalRootBridgeArray[RbIndex - 1].RootPortCount; Index++) { + Status = AmdPciResources->AmdPciResourcesGetRootPortInfo ( + AmdPciResources, + LocalRootBridgeArray[RbIndex - 1].Object->Index, + Index, + (PCI_ROOT_PORT_OBJECT **)&LocalRootBridgeArray[RbIndex - 1].RootPort[Index] + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: AmdPciResourcesGetRootPortInfo Failed: %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + } + } + + FreePool (IoApicInfo); + if (CxlPortInfoHead != NULL) { + FreePool (CxlPortInfoHead); + } + + *RootBridge = LocalRootBridgeArray; + *RootBridgeCount = NumberOfRootBridges; + return Status; +} + +/** + This function returns SBDF information for a given slot number. + + @param[in] SlotNumInfo Slot number to be provided. + @param[out] SegInfo Segment number. + @param[out] BusInfo Bus number. + @param[out] DevFunInfo Bits 0-2 corresponds to function number & bits 3-7 corresponds + to device number. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_INVALID_PARAMETER One or many parameters are invalid. + @retval EFI_NOT_FOUND SBDF information is not found for the given slot number. + +**/ +EFI_STATUS +SlotBdfInfo ( + IN UINT16 *SlotNumInfo, + OUT UINT16 *SegInfo, + OUT UINT8 *BusInfo, + OUT UINT8 *DevFunInfo + ) +{ + EFI_STATUS Status; + PCIE_PLATFORM_CONFIG *Pcie; + PCIE_COMPLEX_CONFIG *ComplexList; + PCIE_SILICON_CONFIG *SiliconList; + PCIE_WRAPPER_CONFIG *WrapperList; + PCIE_ENGINE_CONFIG *EngineList; + + if ((SlotNumInfo == NULL) || (SegInfo == NULL) || (BusInfo == NULL) || (DevFunInfo == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Pcie = NULL; + Status = PcieGetPcieDxe (&Pcie); + if (EFI_ERROR (Status)) { + return Status; + } + + ComplexList = (PCIE_COMPLEX_CONFIG *)PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + + while (ComplexList != NULL) { + SiliconList = PcieConfigGetChildSilicon (ComplexList); + while (SiliconList != NULL) { + WrapperList = PcieConfigGetChildWrapper (SiliconList); + while (WrapperList != NULL) { + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (EngineList->Type.Port.PortData.SlotNum == *SlotNumInfo) { + *SegInfo = EngineList->Type.Port.Address.Address.Segment & 0xFFFF; + *BusInfo = EngineList->Type.Port.Address.Address.Bus & 0xFF; + *DevFunInfo = (((EngineList->Type.Port.Address.Address.Device) & 0x1F) << 3) | + ((EngineList->Type.Port.Address.Address.Function) & 0x7); + return EFI_SUCCESS; + } + + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + + SiliconList = PcieLibGetNextDescriptor (SiliconList); + } + + if ((ComplexList->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_TOPOLOGY) == 0) { + ComplexList++; + } else { + ComplexList = NULL; + } + } + + return EFI_NOT_FOUND; +} + +/** + This function allocates and populate system slot smbios record (Type 9). + + @param DxioPortPtr Pointer to DXIO port descriptor. + @param SmbiosRecordPtr Pointer to smbios type 9 record. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_INVALID_PARAMETER One or many parameters are invalid. + @retval EFI_OUT_OF_RESOURCES Resource not available. + +**/ +EFI_STATUS +CreateSmbiosSystemSlotRecord ( + IN DXIO_PORT_DESCRIPTOR *DxioPortPtr, + IN OUT SMBIOS_TABLE_TYPE9 **SmbiosRecordPtr + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + UINT16 SlotNumInfo; + UINT16 SegInfo; + UINT8 BusInfo; + UINT8 DevFunInfo; + UINT8 PortWidth; + + Status = EFI_SUCCESS; + SegInfo = 0xFFFF; + BusInfo = 0xFF; + DevFunInfo = 0xFF; + + if ((DxioPortPtr == NULL) || (SmbiosRecordPtr == NULL)) { + return EFI_INVALID_PARAMETER; + } + + SmbiosRecord = NULL; + SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9)); + if (SmbiosRecord == NULL) { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } else { + // Currently only map PCIE slots in system slot table. + if (DxioPortPtr->EngineData.EngineType == DxioPcieEngine) { + switch (DxioPortPtr->Port.LinkSpeedCapability) { + case DxioGenMaxSupported: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + case DxioGen1: + SmbiosRecord->SlotType = SlotTypePciExpress; + break; + case DxioGen2: + SmbiosRecord->SlotType = SlotTypePciExpressGen2; + break; + case DxioGen3: + SmbiosRecord->SlotType = SlotTypePciExpressGen3; + break; + case DxioGen4: + SmbiosRecord->SlotType = SlotTypePciExpressGen4; + break; + case DxioGen5: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + default: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + } + } else { + SmbiosRecord->SlotType = SlotTypeOther; + } + + if (DxioPortPtr->EngineData.EndLane >= DxioPortPtr->EngineData.StartLane) { + PortWidth = DxioPortPtr->EngineData.EndLane - DxioPortPtr->EngineData.StartLane + 1; + } else { + PortWidth = DxioPortPtr->EngineData.StartLane - DxioPortPtr->EngineData.EndLane + 1; + } + + switch (PortWidth) + { + case 16: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth16X; + SmbiosRecord->DataBusWidth = 16; + break; + case 8: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth8X; + SmbiosRecord->DataBusWidth = 8; + break; + case 4: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth4X; + SmbiosRecord->DataBusWidth = 4; + break; + case 2: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth2X; + SmbiosRecord->DataBusWidth = 2; + break; + default: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth1X; + SmbiosRecord->DataBusWidth = 1; + break; + } + + if (DxioPortPtr->Port.EndpointStatus == (DXIO_ENDPOINT_STATUS)EndpointDetect) { + SmbiosRecord->CurrentUsage = SlotUsageInUse; + } else if (DxioPortPtr->Port.EndpointStatus == (DXIO_ENDPOINT_STATUS)EndpointNotPresent) { + SmbiosRecord->CurrentUsage = SlotUsageAvailable; + } else { + SmbiosRecord->CurrentUsage = SlotUsageUnknown; + } + + SlotNumInfo = DxioPortPtr->Port.SlotNum; + Status = SlotBdfInfo ( + &SlotNumInfo, + &SegInfo, + &BusInfo, + &DevFunInfo + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Could not get SBDF information %r\n", Status)); + } + + SmbiosRecord->SlotLength = SlotLengthLong; + SmbiosRecord->SlotID = DxioPortPtr->Port.SlotNum; + SmbiosRecord->SegmentGroupNum = SegInfo; + SmbiosRecord->BusNum = BusInfo; + SmbiosRecord->DevFuncNum = DevFunInfo; + SmbiosRecord->PeerGroupingCount = 0; + + *SmbiosRecordPtr = SmbiosRecord; + } + + return Status; +} + +/** + Parse the port parameters and update their slot numbers + + @param[in, out] PortDescriptor Port descriptor to update + + @retval VOID +**/ +VOID +GetSlotNumber ( + IN OUT DXIO_PORT_DESCRIPTOR *PortDescriptor + ) +{ + PORT_PARAM *PortParam; + + PortParam = (PORT_PARAM *) &(PortDescriptor->PortParams); + while (PortParam != NULL && PortParam->ParamType != 0) { + if (PortParam->ParamType == PP_SLOT_NUM) { + PortDescriptor->Port.SlotNum = PortParam->ParamValue; + } + PortParam++; + } +} + +/** + Parse the DXIO topology table for PcieEngine's and update + their slot number + + @param[in, out] DxioTopologyTablePtr DXIO Topology Table pointer + + @retval VOID +**/ +VOID +UpdateSlotNum ( + IN OUT AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTablePtr + ) +{ + UINTN Count; + + for (Count = 0; Count < AMD_DXIO_PORT_DESCRIPTOR_SIZE; Count++) { + if (DxioTopologyTablePtr->Port[Count].Flags == DESCRIPTOR_TERMINATE_LIST) { + break; + } + if (!(DxioTopologyTablePtr->Port[Count].EngineData.EngineType == DxioPcieEngine && + DxioTopologyTablePtr->Port[Count].Port.PortPresent != DxioPortDisabled)) { + continue; + } + GetSlotNumber (&DxioTopologyTablePtr->Port[Count]); + } +} + +/** + Get the platform specific System Slot information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] SystemSlotInfo The System Slot information + @param[in, out] SystemSlotCount Number of System Slot present + + @retval EFI_UNSUPPORTED Platform do not support this function. +**/ +EFI_STATUS +EFIAPI +GetSystemSlotInfo ( + IN OUT SMBIOS_TABLE_TYPE9 **SystemSlotInfo, + IN OUT UINTN *SystemSlotCount + ) +{ + AMD_CPM_TABLE_PROTOCOL *CpmTableProtocolPtr; + AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTablePtr2[2]; + AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTableCopyPtr[2]; + EFI_STATUS Status; + UINTN SocketIdx; + UINTN DxioPortIdx; + UINTN SlotCount; + SMBIOS_TABLE_TYPE9 *SlotInfo; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + + if ((SystemSlotInfo == NULL) || (SystemSlotCount == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = gBS->LocateProtocol ( + &gAmdCpmTableProtocolGuid, + NULL, + (VOID **)&CpmTableProtocolPtr + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to locate AmdCpmTableProtocol: %r\n", Status)); + return Status; + } + + DxioTopologyTablePtr2[0] = NULL; + DxioTopologyTablePtr2[0] = CpmTableProtocolPtr->CommonFunction.GetTablePtr2 ( + CpmTableProtocolPtr, + CPM_SIGNATURE_DXIO_TOPOLOGY + ); + + DxioTopologyTablePtr2[1] = NULL; + DxioTopologyTablePtr2[1] = CpmTableProtocolPtr->CommonFunction.GetTablePtr2 ( + CpmTableProtocolPtr, + CPM_SIGNATURE_DXIO_TOPOLOGY_S1 + ); + + //Shouldn't modify CPM table, so make a copy that we can edit + DxioTopologyTableCopyPtr[0] = AllocateZeroPool (sizeof(AMD_CPM_DXIO_TOPOLOGY_TABLE)); + DxioTopologyTableCopyPtr[1] = AllocateZeroPool (sizeof(AMD_CPM_DXIO_TOPOLOGY_TABLE)); + + CopyMem (DxioTopologyTableCopyPtr[0], (VOID*) DxioTopologyTablePtr2[0], sizeof (AMD_CPM_DXIO_TOPOLOGY_TABLE)); + CopyMem (DxioTopologyTableCopyPtr[1], (VOID*) DxioTopologyTablePtr2[1], sizeof (AMD_CPM_DXIO_TOPOLOGY_TABLE)); + + //Update Slot Numbers from port params + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTableCopyPtr[SocketIdx] != NULL) { + UpdateSlotNum (DxioTopologyTableCopyPtr[SocketIdx]); + } + } + + // Add Smbios System Slot information for all sockets present. + SlotCount = 0; + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTableCopyPtr[SocketIdx] != NULL) { + for (DxioPortIdx = 0; DxioPortIdx < AMD_DXIO_PORT_DESCRIPTOR_SIZE; + DxioPortIdx++) + { + // Check if Slot is present + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.SlotNum > 0) && + (DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.PortPresent == 1)) + { + SlotCount++; + } + + // Terminate if last port found. + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Flags & DESCRIPTOR_TERMINATE_LIST)) { + break; + } + } + } + } + + if (SlotCount == 0) { + return EFI_NOT_FOUND; + } + + SlotInfo = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9) * SlotCount); + if (SlotInfo == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + SlotCount = 0; + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTableCopyPtr[SocketIdx] != NULL) { + for (DxioPortIdx = 0; DxioPortIdx < AMD_DXIO_PORT_DESCRIPTOR_SIZE; + DxioPortIdx++) + { + // Check if Slot is present + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.SlotNum > 0) && + (DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.PortPresent == 1)) + { + SmbiosRecord = NULL; + Status = CreateSmbiosSystemSlotRecord ( + &DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx], + &SmbiosRecord + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Slot (%d) information not found. Status = %r\n", + DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.SlotNum, + Status + )); + } else { + CopyMem (&SlotInfo[SlotCount], SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9)); + SlotCount++; + } + } + + // Terminate if last port found. + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Flags & 0x80000000)) { + break; + } + } + } + } + + FreePool (DxioTopologyTableCopyPtr[0]); + FreePool (DxioTopologyTableCopyPtr[1]); + + *SystemSlotInfo = SlotInfo; + *SystemSlotCount = SlotCount; + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..9edfaad64eb5fd5c105d9a66cc30004b81126a7c --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf @@ -0,0 +1,58 @@ +## @file +# +# INF file of AMD Platform SoC library +# +# Copyright (C) 2023 -2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = DxePlatformSocLib + MODULE_UNI_FILE = DxePlatformSocLib.uni + FILE_GUID = 27F805CC-7724-48CE-935F-6FBBC7B17BCE + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformSocLib + +[Sources] + DxePlatformSocLib.c + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModuleDfPkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + AgesaPkg/AgesaPkg.dec + AmdCpmPkg/AmdCpmPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + HobLib + NbioCommonDxeLib + NbioHandleLib + PcdLib + PcieConfigLib + SmnAccessLib + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket ## CONSUMES + +[Protocols] + gAmdFabricNumaServices2ProtocolGuid + gAmdNbioCxlServicesProtocolGuid + gAmdNbioPcieServicesProtocolGuid + gAmdPciResourceProtocolGuid + gAmdSocLogicalIdProtocolGuid + gAmdCpmTableProtocolGuid + +[Depex] + gAmdNbioPcieServicesProtocolGuid diff --git a/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni new file mode 100644 index 0000000000000000000000000000000000000000..dcb169fbafd0d6536450cb727e77e53783af336a --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni @@ -0,0 +1,14 @@ +## @file +# +# UNI file of AMD Turin Platform SoC library +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +#string STR_MODULE_ABSTRACT #language en-US "AMD DXE Turin SoC library instance." + +#string STR_MODULE_DESCRIPTION #language en-US "AMD DXE Turin SoC library instance." + diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.c new file mode 100644 index 0000000000000000000000000000000000000000..b58ac4b6e63607671f44d473e51b039faa394d99 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.c @@ -0,0 +1,301 @@ +/** @file + + Internal functions used by platform SPI HC library that includes ROM armor + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" + +extern BOOLEAN mPspMailboxSpiMode; +extern SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +extern EFI_PHYSICAL_ADDRESS mHcAddress; + +/** + Check that SPI Conroller is Not Busy + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiControllerNotBusy ( + ) +{ + UINT32 SpiReg00; + UINT32 LpcDmaStatus; + UINT32 RetryCount; + UINTN DelayMicroseconds; + + if (mPspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + + DelayMicroseconds = FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + SpiReg00 = FCH_SPI_BUSY; + RetryCount = FixedPcdGet32 (PcdAmdSpiRetryCount); + do { + SpiReg00 = MmioRead32 (mHcAddress + FCH_SPI_MMIO_REG4C_SPISTATUS); + LpcDmaStatus = PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0x00, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REGB8 + ) + ); + if ( ((SpiReg00 & FCH_SPI_BUSY) == 0) + && ((LpcDmaStatus & FCH_LPC_DMA_SPI_BUSY) == 0)) + { + break; + } + + MicroSecondDelay (DelayMicroseconds); + RetryCount--; + } while (RetryCount > 0); + + if (RetryCount == 0) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Check for SPI transaction failure(s) + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiTransactionCheckFailure ( + ) +{ + EFI_STATUS Status; + UINT32 Data; + + if (mPspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + Data = MmioRead32 (mHcAddress + FCH_SPI_MMIO_REG00); + if ((Data & FCH_SPI_FIFO_PTR_CRL) != 0) { + Status = EFI_ACCESS_DENIED; + } + } + + return Status; +} + +/** + If SPI controller is not busy, execute SPI command. Then wait until SPI + controller is not busy. + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiExecute ( + ) +{ + EFI_STATUS Status; + + if (mPspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + MmioOr8 (mHcAddress + FCH_SPI_MMIO_REG47_CMDTRIGGER, BIT7); + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + Status = FchSpiTransactionCheckFailure (); + } + } + + return Status; +} + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiBlockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + BOOLEAN OpcodeBlocked; + UINTN RestrictedCmd; + UINT8 Data; + + Status = EFI_OUT_OF_RESOURCES; + OpcodeBlocked = FALSE; + + // Allow only one copy of Opcode in RestrictedCmd register + for (RestrictedCmd = 0; RestrictedCmd <= 3; RestrictedCmd++) { + Data = MmioRead8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd); + + if ((Data == Opcode) && (OpcodeBlocked == FALSE)) { + OpcodeBlocked = TRUE; + } else if ((Data == Opcode) && (OpcodeBlocked == TRUE)) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, 0x00); + } else if ((Data == 0x00) && (OpcodeBlocked == FALSE)) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, Opcode); + OpcodeBlocked = TRUE; + } + } + + if (OpcodeBlocked) { + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ) +{ + UINTN RestrictedCmd; + + // Unblock any copies of the Opcode + for (RestrictedCmd = 0; RestrictedCmd <= 3; RestrictedCmd++) { + if (MmioRead8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd) == Opcode) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, 0x00); + } + } + + return EFI_SUCCESS; +} + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockAllOpcodes ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioWrite32 (HcAddress + FCH_SPI_MMIO_REG04, 0x00); + return EFI_SUCCESS; +} + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiLockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioBitFieldAnd32 ( + HcAddress + FCH_SPI_MMIO_REG00, + 22, + 23, + 0x0 + ); + if (MmioBitFieldRead32 (HcAddress + FCH_SPI_MMIO_REG00, 22, 23) + == 0x0) + { + return EFI_SUCCESS; + } + + return EFI_DEVICE_ERROR; +} + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnlockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioBitFieldOr32 ( + HcAddress + FCH_SPI_MMIO_REG00, + 22, + 23, + BIT0 | BIT1 + ); + if (MmioBitFieldRead32 (HcAddress + FCH_SPI_MMIO_REG00, 22, 23) + == (BIT0 | BIT1)) + { + return EFI_SUCCESS; + } + + return EFI_DEVICE_ERROR; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.h b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.h new file mode 100644 index 0000000000000000000000000000000000000000..e70fc5840e7e81c18e6940fdbd6f4833b10c20bb --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.h @@ -0,0 +1,129 @@ +/** @file + + Internal functions used by platform SPI HC library + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef AMD_SPI_HC_INTERNAL_H_ +#define AMD_SPI_HC_INTERNAL_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define FCH_LPC_DMA_SPI_BUSY BIT0 +#define FCH_SPI_MMIO_REG04 0x04// SPI_RestrictedCmd +#define FCH_SPI_FRAME_SIZE_SUPPORT_MASK (1 << (8 - 1)) +#define FCH_SPI_LOCK_CONTROLLER 0x00 +#define FCH_SPI_UNLOCK_CONTROLLER BIT0 | BIT1 + +/** + Check that SPI Conroller is Not Busy + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiControllerNotBusy ( + ); + +/** + Execute SPI command + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiExecute ( + ); + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiBlockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ); + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ); + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockAllOpcodes ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiLockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnlockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +#endif // __AMD_SPI_HC_INTERNAL_H__ diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.c new file mode 100644 index 0000000000000000000000000000000000000000..fd67d3f7dc8c916920e44b83af071c772400a2cf --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.c @@ -0,0 +1,367 @@ +/** @file + + SPI HC SMM state registration function definitions + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcSmmState.h" +#include "AmdSpiHcInternal.h" + +extern BOOLEAN mPspMailboxSpiMode; +extern EFI_PHYSICAL_ADDRESS mHcAddress; +extern BOOLEAN mSmmAlreadySavedState; +extern VOID *mState; +extern UINT32 mStateSize; +extern UINT32 mStateRecordCount; + +CONST struct SpiHcRegisterState mSpiHcState[] = { + // {Register, Size, Count} + { 0x04, 0x4, 0x1 }, // SPI_RestrictedCmd + { 0x08, 0x4, 0x1 }, // SPI_RestrictedCmd2 + { 0x0D, 0x1, 0x1 }, // SPI_Cntrl1[15:8] + { 0x0E, 0x2, 0x1 }, // SPI_Cntrl1[31:16] + { 0x10, 0x4, 0x1 }, // SPI_CmdValue0 + { 0x14, 0x4, 0x1 }, // SPI_CmdValue1 + { 0x18, 0x4, 0x1 }, // SPI_CmdValue2 + { 0x1D, 0x1, 0x1 }, // Alt_SPI_CS + { 0x20, 0x1, 0x1 }, // SPI100 Enable + { 0x22, 0x2, 0x1 }, // SPI100 Speed Config + { 0x24, 0x4, 0x1 }, // SPI100 Clock Config + { 0x32, 0x2, 0x1 }, // SPI100 Dummy Cycle Config + { 0x34, 0x2, 0x1 }, // SPI100 RX Timing Config 1 + { 0x44, 0x1, 0x1 }, // ModeByte + { 0x45, 0x1, 0x1 }, // CmdCode + { 0x48, 0x1, 0x1 }, // TxByteCount + { 0x4B, 0x1, 0x1 }, // RxByteCount + { 0x80, 0x1, 70 }, // FIFO [70:0] + { 0x00, 0x4, 0x1 } // SpiCntrl0 ** Save last so restore last ** +}; + +/** + Allocate the save state space and update the instance structure + + @retval EFI_SUCCESS The Save State space was allocated + @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate +**/ +EFI_STATUS +EFIAPI +AllocateState ( + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + + NumRecords = sizeof (mSpiHcState) / sizeof (struct SpiHcRegisterState); + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + // calculate space needed + mStateSize = 0; + for (Record = 0; Record < NumRecords; Record++) { + mStateSize += mSpiHcState[Record].Size + * mSpiHcState[Record].Count; + } + + mStateRecordCount = NumRecords; + mState = AllocateZeroPool (mStateSize); + if (mState == NULL) { + mStateRecordCount = 0; + Status = EFI_OUT_OF_RESOURCES; + } else { + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Save the Host controler state to restore after transaction is complete + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +SaveState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + UINT32 Count; + UINT8 *State; + + Status = EFI_SUCCESS; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return Status; + } + + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + State = mState; + NumRecords = mStateRecordCount; + if (!mSmmAlreadySavedState) { + for (Record = 0; Record < NumRecords; Record++) { + switch (mSpiHcState[Record].Size) { + case 0x1: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT8 *)State = MmioRead8 ( + mHcAddress + + mSpiHcState[Record].Register + ); + State += 1; + } + + break; + case 0x2: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT16 *)State = MmioRead16 ( + mHcAddress + + mSpiHcState[Record].Register + ); + State += 2; + } + + break; + case 0x4: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT32 *)State = MmioRead32 ( + mHcAddress + + mSpiHcState[Record].Register + ); + State += 4; + } + + break; + } + } + + mSmmAlreadySavedState = TRUE; + } + } + + return Status; +} + +/** + Restore the Host Controller state + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +RestoreState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + UINT32 Count; + UINT8 *State; + + Status = EFI_SUCCESS; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return Status; + } + + State = mState; + NumRecords = mStateRecordCount; + if (mSmmAlreadySavedState) { + for (Record = 0; Record < NumRecords; Record++) { + switch (mSpiHcState[Record].Size) { + case 0x1: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite8 ( + mHcAddress + mSpiHcState[Record].Register, + *(UINT8 *)State + ); + State += 1; + } + + break; + case 0x2: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite16 ( + mHcAddress + mSpiHcState[Record].Register, + *(UINT16 *)State + ); + State += 2; + } + + break; + case 0x4: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite32 ( + mHcAddress + mSpiHcState[Record].Register, + *(UINT32 *)State + ); + State += 4; + } + + break; + } + } + + mSmmAlreadySavedState = FALSE; + } + + return Status; +} + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiBlockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiBlockOpcode (mHcAddress, Opcode); + return Status; +} + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnblockOpcode (mHcAddress, Opcode); + return Status; +} + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockAllOpcodes ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnblockAllOpcodes (mHcAddress); + return Status; +} + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiLockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiLockSpiHostControllerRegisters (mHcAddress); + return Status; +} + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnlockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnlockSpiHostControllerRegisters (mHcAddress); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.h b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.h new file mode 100644 index 0000000000000000000000000000000000000000..2d7ff32bf70fa98b7a2be5d5d6bd9cabb437ff91 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.h @@ -0,0 +1,143 @@ +/** @file + + SPI HC SMM state registration function declarations + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef AMD_SPI_HC_SMM_STATE_H_ +#define AMD_SPI_HC_SMM_STATE_H_ + +#include +#include +#include +#include "AmdSpiHcInternal.h" + +struct SpiHcRegisterState { + UINT32 Register; + UINT8 Size; // Size in Bytes + UINT8 Count; // Number of contiguous registers to store +}; + +/** + Allocate the save state space and update the instance structure + + @retval EFI_SUCCESS The Save State space was allocated + @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate +**/ +EFI_STATUS +EFIAPI +AllocateState ( + ); + +/** + Save the Host Controller state to restore after transaction is complete + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +SaveState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Restore the Host Controller state + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +RestoreState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiBlockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ); + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ); + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockAllOpcodes ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiLockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnlockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +#endif // __AMD_SPI_HC_SMM_STATE_H__ diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.c new file mode 100644 index 0000000000000000000000000000000000000000..5ac22be8e62989be64103f6ef5516dd18c129e99 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.c @@ -0,0 +1,364 @@ +/** @file + + SPI HC platform library implementation. This code touches the SPI controllers and performs + the hardware transaction + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" +#include +#include + +extern BOOLEAN mPspMailboxSpiMode; +extern SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +extern EFI_PHYSICAL_ADDRESS mHcAddress; + +/** + This function reports the device path of SPI host controller. This is needed in order for the SpiBus + to match the correct SPI_BUS to the SPI host controller + + @param[out] DevicePath The device path for this SPI HC is returned in this variable + + @retval EFI_SUCCESS +*/ +EFI_STATUS +EFIAPI +GetSpiHcDevicePath ( + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mFchDevicePath; + return EFI_SUCCESS; +} + +/** + This is the platform specific Spi Chip select function. + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSelect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ) +{ + EFI_STATUS Status; + CHIP_SELECT_PARAMETERS *ChipSelectParameter; + + Status = EFI_DEVICE_ERROR; + ChipSelectParameter = SpiPeripheral->ChipSelectParameter; + + if (ChipSelectParameter->OrValue <= 1) { + if (!mPspMailboxSpiMode) { + MmioAndThenOr8 ( + mHcAddress + FCH_SPI_MMIO_REG1D, + ChipSelectParameter->AndValue, + ChipSelectParameter->OrValue + ); + Status = EFI_SUCCESS; + } else { + mSpiCommunicationBuffer.SpiCommand[0].ChipSelect = + ChipSelectParameter->OrValue + 1; + Status = EFI_SUCCESS; + } + } else { + Status = EFI_INVALID_PARAMETER; + } + + return Status; +} + +/** + This function is the platform specific SPI clock function. + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcClock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ) +{ + EFI_STATUS Status; + UINT32 InternalClockHz; + UINT16 InternalClockValue; + + Status = EFI_SUCCESS; + InternalClockHz = *ClockHz; + InternalClockValue = 0x00; + if ((SpiPeripheral->MaxClockHz != 0) && + (SpiPeripheral->MaxClockHz < InternalClockHz)) + { + InternalClockHz = SpiPeripheral->MaxClockHz; + } + + if ((SpiPeripheral->SpiPart->MaxClockHz != 0) && + (SpiPeripheral->SpiPart->MaxClockHz < InternalClockHz)) + { + InternalClockHz = SpiPeripheral->SpiPart->MaxClockHz; + } + + if ((SpiPeripheral->SpiPart->MinClockHz != 0) && + (SpiPeripheral->SpiPart->MinClockHz > InternalClockHz)) + { + Status = EFI_UNSUPPORTED; + } + + if (!EFI_ERROR (Status)) { + if (InternalClockHz >= MHz (100)) { + InternalClockValue = 0x4; + } else if (InternalClockHz >= MHz (66)) { + InternalClockValue = 0x0; + } else if (InternalClockHz >= MHz (33)) { + InternalClockValue = 0x1; + } else if (InternalClockHz >= MHz (22)) { + InternalClockValue = 0x2; + } else if (InternalClockHz >= MHz (16)) { + InternalClockValue = 0x3; + } else if (InternalClockHz >= KHz (800)) { + InternalClockValue = 0x5; + } else { + Status = EFI_UNSUPPORTED; + } + + if (!EFI_ERROR (Status)) { + if (!mPspMailboxSpiMode) { + // Enable UseSpi100 + MmioOr8 ( + mHcAddress + FCH_SPI_MMIO_REG20, + BIT0 + ); + // Set the Value for NormSpeed and FastSpeed + InternalClockValue = InternalClockValue << 12 | InternalClockValue << 8; + MmioAndThenOr16 ( + mHcAddress + FCH_SPI_MMIO_REG22, + 0x00FF, + InternalClockValue + ); + } else { + mSpiCommunicationBuffer.SpiCommand[0].Frequency = + (UINT8)InternalClockValue; + } + } + } + + return Status; +} + +/** + This function is the platform specific SPI transaction function + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + @retval EFI_DEVICE_ERROR SPI Host Controller failed transaction + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcTransaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ) +{ + EFI_STATUS Status; + UINT8 Opcode; + UINT32 WriteBytes; + UINT8 *WriteBuffer; + UINT32 ReadBytes; + UINT8 *ReadBuffer; + EFI_PHYSICAL_ADDRESS HcAddress; + + WriteBytes = BusTransaction->WriteBytes; + WriteBuffer = BusTransaction->WriteBuffer; + + ReadBytes = BusTransaction->ReadBytes; + ReadBuffer = BusTransaction->ReadBuffer; + + if ( (WriteBytes > This->MaximumTransferBytes + 6) + || (ReadBytes > (This->MaximumTransferBytes + 6 - WriteBytes)) + || ((WriteBytes != 0) && (WriteBuffer == NULL)) + || ((ReadBytes != 0) && (ReadBuffer == NULL))) + { + return EFI_BAD_BUFFER_SIZE; + } + + Opcode = 0; + if (WriteBytes >= 1) { + Opcode = WriteBuffer[0]; + // Skip Opcode + WriteBytes -= 1; + WriteBuffer += 1; + } + + Status = EFI_SUCCESS; + HcAddress = mHcAddress; + + if (!mPspMailboxSpiMode) { + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG48_TX_BYTECOUNT, + (UINT8)WriteBytes + ); + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG4B_RXBYTECOUNT, + (UINT8)ReadBytes + ); + + // Fill in Write Data including Address + if (WriteBytes != 0) { + MmioWriteBuffer8 ( + HcAddress + FCH_SPI_MMIO_REG80_FIFO, + WriteBytes, + WriteBuffer + ); + } + + // Set Opcode + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG45_CMDCODE, + Opcode + ); + + // Execute the Transaction + Status = FchSpiExecute (); + if (!EFI_ERROR (Status)) { + if (ReadBytes != 0) { + MmioReadBuffer8 ( + HcAddress + + FCH_SPI_MMIO_REG80_FIFO + + WriteBytes, + ReadBytes, + ReadBuffer + ); + } + } + } + } else { + // Execute SPI transaction through PSP Mailbox + mSpiCommunicationBuffer.SpiCommand[0].OpCode = Opcode; + mSpiCommunicationBuffer.SpiCommand[0].BytesToTx = (UINT8)WriteBytes; + if (WriteBytes != 0) { + CopyMem ( + &mSpiCommunicationBuffer.SpiCommand[0].Buffer, + WriteBuffer, + WriteBytes + ); + } + + mSpiCommunicationBuffer.SpiCommand[0].BytesToRx = (UINT8)ReadBytes; + mSpiCommunicationBuffer.CommandCount = 1; + mSpiCommunicationBuffer.SpiCommunicationResult.Value = 0x0; + mSpiCommunicationBuffer.ReadyToRun = TRUE; + Status = PspExecuteSpiCommand (); + if (!EFI_ERROR (Status)) { + if (mSpiCommunicationBuffer.SpiCommunicationResult.Value == 0x1000) { + Status = EFI_INVALID_PARAMETER; + } else { + switch (mSpiCommunicationBuffer.SpiCommunicationResult.Field.Command0Result) { + case SPI_COMMAND_MALFORMED: + Status = EFI_INVALID_PARAMETER; + break; + case SPI_COMMAND_COMPLETED: + Status = EFI_SUCCESS; + if (ReadBytes > 0) { + CopyMem ( + ReadBuffer, + &mSpiCommunicationBuffer.SpiCommand[0].Buffer[0] + WriteBytes, + ReadBytes + ); + } + + break; + case SPI_COMMAND_NOT_ALLOWED: + Status = EFI_WRITE_PROTECTED; + break; + default: + Status = EFI_DEVICE_ERROR; + break; + } + } + } + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.uni b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.uni new file mode 100644 index 0000000000000000000000000000000000000000..0d82be9b54238eeb890e3259f9289c0bdb90cf55 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.uni @@ -0,0 +1,10 @@ +/** @file + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "AMD SPI Host controller library" diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..ff09b92ba16921a7c1ad1bd02747e40bca6a6bdb --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.c @@ -0,0 +1,65 @@ +/** @file + + Implementation of SpiHcPlatformLibrary for DXE + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" +#include +#include + +#define SPI_HC_MAXIMUM_TRANSFER_BYTES 64 + +// Global variables to manage the platform-dependent SPI host controller +BOOLEAN mPspMailboxSpiMode; +SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +EFI_PHYSICAL_ADDRESS mHcAddress; + +/** + This function reports the details of the SPI Host Controller to the SpiHc driver. + + @param[out] Attributes The suported attributes of the SPI host controller + @param[out] FrameSizeSupportMask The suported FrameSizeSupportMask of the SPI host controller + @param[out] MaximumTransferBytes The suported MaximumTransferBytes of the SPI host controller + + @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly + @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated +*/ +EFI_STATUS +EFIAPI +GetPlatformSpiHcDetails ( + OUT UINT32 *Attributes, + OUT UINT32 *FrameSizeSupportMask, + OUT UINT32 *MaximumTransferBytes + ) +{ + // Fill in the SPI Host Controller Protocol + *Attributes = HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS | + HC_SUPPORTS_READ_ONLY_OPERATIONS | + HC_SUPPORTS_WRITE_ONLY_OPERATIONS; + *FrameSizeSupportMask = FCH_SPI_FRAME_SIZE_SUPPORT_MASK; + *MaximumTransferBytes = SPI_HC_MAXIMUM_TRANSFER_BYTES; + + // fill in Platform specific global variables + mHcAddress = ( + PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS (0x00, FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0) + ) + ) & 0xFFFFFF00; + mPspMailboxSpiMode = TRUE; + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..0023f95584da15cb47dc0822bb8a3374a6c8b32e --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf @@ -0,0 +1,61 @@ +## @file +# +# SpiHcPlatformLibrary DXE_DRIVER inf +# +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SpiHcPlatformLibDxe + FILE_GUID = 3C230948-6DF5-4802-8177-967A190579CF + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + LIBRARY_CLASS = SpiHcPlatformLib + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + AmdPspRomArmorLib + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + PcdLib + PciSegmentLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Sources] + SpiHcPlatformLibDxe.c + SpiHcPlatformLib.c + AmdSpiHcInternal.h + AmdSpiHcInternal.c + +[Protocols] + gEfiSpiHcProtocolGuid + +[FeaturePcd] + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SpiHcPlatformLib.uni diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..703c26e17f17d70753ae224795d0df1a561abc8f --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.c @@ -0,0 +1,184 @@ +/** @file + + Implementation of SpiHcPlatformLibrary for SMM + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" +#include "AmdSpiHcSmmState.h" + +#define SPI_HC_MAXIMUM_TRANSFER_BYTES 64 + +EFI_HANDLE mSpiStateHandle = 0; + +// Global variables to manage the platform-dependent SPI host controller when in DXE or SMM +BOOLEAN mPspMailboxSpiMode; +SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +VOID *mRegistration; +EFI_PHYSICAL_ADDRESS mHcAddress; + +// SMM specific global variables to manage the platform-dependent SPI host controller +SMM_EFI_SPI_HC_STATE_PROTOCOL mStateProtocol; +BOOLEAN mSmmAlreadySavedState; +VOID *mState; +UINT32 mStateSize; +UINT32 mStateRecordCount; + +/** + SPI host controller event notify callback to lock down the SPI chipset + + @param + @param + + @retval +**/ +EFI_STATUS +EFIAPI +AmdSpiHcEventNotify ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_SPI_HC_PROTOCOL *SpiHc; + SPI_WHITE_LIST *SpiWhitelist; + SMM_EFI_SPI_HC_STATE_PROTOCOL *SpiStateProtocol; + + // There can only be one SPI host controller driver in SMM + Status = gMmst->MmLocateProtocol ( + &gEfiSpiSmmHcProtocolGuid, + NULL, + (VOID **)&SpiHc + ); + + // Call PSP MailBox to change to PSP SPI mode + Status = gMmst->MmLocateProtocol ( + &gAmdSpiHcStateProtocolGuid, + NULL, + (VOID **)&SpiStateProtocol + ); + + SpiStateProtocol->Lock (SpiStateProtocol); + Status = PspEnterSmmOnlyMode (&mSpiCommunicationBuffer); + + if (!EFI_ERROR (Status)) { + mPspMailboxSpiMode = TRUE; + } else { + return EFI_DEVICE_ERROR; + } + + if (FeaturePcdGet (PcdRomArmorWhitelistEnable)) { + // Retrieve allocated Whitelist table + Status = GetPspRomArmorWhitelist (&SpiWhitelist); + if (EFI_ERROR (Status)) { + if (SpiWhitelist != NULL) { + FreePool (SpiWhitelist); + } + + return Status; + } + + // Send Whitelist to PSP + Status = PspEnforceWhitelist (SpiWhitelist); + if (SpiWhitelist != NULL) { + FreePool (SpiWhitelist); + } + } + + return Status; +} + +/** + This function reports the details of the SPI Host Controller to the SpiHc driver. + + @param[out] Attributes The suported attributes of the SPI host controller + @param[out] FrameSizeSupportMask The suported FrameSizeSupportMask of the SPI host controller + @param[out] MaximumTransferBytes The suported MaximumTransferBytes of the SPI host controller + + @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly + @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated +*/ +EFI_STATUS +EFIAPI +GetPlatformSpiHcDetails ( + OUT UINT32 *Attributes, + OUT UINT32 *FrameSizeSupportMask, + OUT UINT32 *MaximumTransferBytes + ) +{ + EFI_STATUS Status; + + // Fill in the SPI Host Controller Protocol + *Attributes = HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS | + HC_SUPPORTS_READ_ONLY_OPERATIONS | + HC_SUPPORTS_WRITE_ONLY_OPERATIONS; + *FrameSizeSupportMask = FCH_SPI_FRAME_SIZE_SUPPORT_MASK; + *MaximumTransferBytes = SPI_HC_MAXIMUM_TRANSFER_BYTES; + + // Set platform specific global variables + mPspMailboxSpiMode = FALSE; // not supported in SMM + mHcAddress = ( + PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS (0x00, FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0) + ) + ) & 0xFFFFFF00; + + // Allocate Host Controller save state space + Status = AllocateState (); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + // Fill in the SPI HC Save State Protocol + mStateProtocol.SaveState = SaveState; + mStateProtocol.RestoreState = RestoreState; + mStateProtocol.Lock = FchSpiLockSpiHostControllerRegisters; + mStateProtocol.Unlock = FchSpiUnlockSpiHostControllerRegisters; + mStateProtocol.BlockOpcode = FchSpiBlockOpcode; + mStateProtocol.UnblockOpcode = FchSpiUnblockOpcode; + mStateProtocol.UnblockAllOpcodes = FchSpiUnblockAllOpcodes; + + Status = gMmst->MmInstallProtocolInterface ( + &mSpiStateHandle, + &gAmdSpiHcStateProtocolGuid, + EFI_NATIVE_INTERFACE, + &mStateProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error installing gAmdSpiHcStateProtocolGuid\n")); + } + + Status = gMmst->MmRegisterProtocolNotify ( + &gEfiMmReadyToLockProtocolGuid, + AmdSpiHcEventNotify, + &mRegistration + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error registering gEfiMmReadyToLockProtocolGuid\n")); + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..9eda400c725a4f5b544b79745a43c2d1bbb8744e --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf @@ -0,0 +1,66 @@ +## @file +# +# SpiHcPlatformLibrary DXE_SMM_DRIVER inf +# +# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SpiHcPlatformLibSmm + FILE_GUID = 6D856A06-B502-49D5-80D5-10A0BA4EDB4D + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + LIBRARY_CLASS = SpiHcPlatformLib + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + AmdPspRomArmorLib + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + MmServicesTableLib + PcdLib + PciSegmentLib + PlatformPspRomArmorWhitelistLib + TimerLib + UefiDriverEntryPoint + +[Sources] + SpiHcPlatformLibSmm.c + SpiHcPlatformLib.c + AmdSpiHcInternal.h + AmdSpiHcInternal.c + AmdSpiHcSmmState.h + AmdSpiHcSmmState.c + +[Protocols] + gEfiSmmVariableProtocolGuid + gEfiSpiSmmHcProtocolGuid + gAmdSpiHcStateProtocolGuid + gEfiMmReadyToLockProtocolGuid + +[FeaturePcd] + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorWhitelistEnable + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SpiHcPlatformLib.uni diff --git a/Platform/AMD/TurinBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..58a82f1c4421239d41d9061fbf5c1380d43ecbc9 --- /dev/null +++ b/Platform/AMD/TurinBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("3E35E28F-C98B-481B-BA7C-97C712982509")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf{ + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..2274b45cfed3df17d8f6ffd8739ba0046465b4c7 --- /dev/null +++ b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.dsc @@ -0,0 +1,204 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Onyx +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "ONYX " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020202058594E4F # "ONYX " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc + diff --git a/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..4701cd93633b714fb52ffdd4b6a02aab36b59910 --- /dev/null +++ b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/Override/AGESA/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi b/Platform/AMD/TurinBoard/Override/AGESA/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi new file mode 100644 index 0000000000000000000000000000000000000000..93be0e33ab696bcee886bd9b2f1256678a7aac13 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/AGESA/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi @@ -0,0 +1,924 @@ +/** @file + + Fch Return I2C I3C Interrupt + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB) { + +Name (TSOS, 0x75) + +If(CondRefOf(\_OSI)) +{ + If(\_OSI("Windows 2009")) + { + Store(0x50, TSOS) + } + If(\_OSI("Windows 2015")) + { + Store(0x70, TSOS) + } +} + +OperationRegion(ECMC, SystemIo, 0x72, 0x02) +Field(ECMC, AnyAcc, NoLock, Preserve) +{ + ECMI, 8, + ECMD, 8, +} +IndexField(ECMI, ECMD, ByteAcc, NoLock, Preserve) { + Offset (0x08), + FRTB, 32, +} +OperationRegion(FRTP, SystemMemory, FRTB, 0x100) +Field(FRTP, AnyAcc, NoLock, Preserve) +{ + PEBA, 64, + Offset (0x08), + , 4, + LPCE, 1, //LPC , 4 + IC0E, 1, //I2C0, 5 + IC1E, 1, //I2C1, 6 + IC2E, 1, //I2C2, 7 + IC3E, 1, //I2C3, 8 + IC4E, 1, //I2C3, 9 + IC5E, 1, //I2C3, 10 + UT0E, 1, //UART0, 11 + UT1E, 1, //UART1, 12 + I31E, 1, //I3C1 13 + I32E, 1, //I3C2, 14 + I33E, 1, //I3C3, 15 + UT2E, 1, //UART2, 16 + , 1, + EMMD, 2, //18-19, EMMC Driver type, 0:AMD eMMC Driver (AMDI0040) 1:MS SD Driver (PNP0D40) 2:0:MS eMMC Driver (AMDI0040) + , 1, //UART4, 20 + I30E, 1, //I3C0, 21 + , 1, + XHCE, 1, //XCHI, 23 + , 1, //24 + , 1, + UT3E, 1, //UART3, 26 + ESPI, 1, //ESPI 27 + EMME, 1, //EMMC 28 + Offset (0x0C), + PCEF, 1, // Post Code Enable Flag + , 4, + IC0D, 1, //I2C0, 5 + IC1D, 1, + IC2D, 1, + IC3D, 1, //I2C3, 8 + IC4D, 1, //I2C3, 9 + IC5D, 1, //I2C3, 10 + UT0D, 1, //UART0, 11 + UT1D, 1, //UART1, 12 + , 1, //, 13 + , 1, //, 14 + ST_D, 1, //SATA, 15 + UT2D, 1, //UART2, 16 + , 1, + EHCD, 1, //EHCI, 18 + , 4, + XHCD, 1, //XCHI, 23 + SD_D, 1, //SD, 24 + , 1, + UT3D, 1, //UART1, 26 + , 1, + EMD3, 1, //EMMC D3 28 + , 2, + S03D, 1, //S0I3 flag, 31 + Offset (0x10), + FW00, 16, + FW01, 32, + FW02, 16, + FW03, 32, + SDS0, 8, //SataDevSlpPort0S5Pin + SDS1, 8, //SataDevSlpPort1S5Pin + Offset (0x2A), + I30M, 1, //I3C 0 Mode + I31M, 1, //I3C 1 Mode + I32M, 1, //I3C 2 Mode + I33M, 1, //I3C 3 Mode + Offset (0x2E), + UT0I, 1, // UART0 Invisible 0 + UT1I, 1, // UART1 Invisible 1 + UT2I, 1, // UART2 Invisible 2 + UT3I, 1, // UART3 Invisible 3 + UT4I, 1, // UART4 Invisible 4 + , 3, + UL0I, 1, // UART0 Legacy IO Invisible 8 + UL1I, 1, // UART1 Legacy IO Invisible 9 + UL2I, 1, // UART2 Legacy IO Invisible 10 + UL3I, 1, // UART3 Legacy IO Invisible 11 + Offset (0x30), + I20I, 1, // I2C0 Invisidble 0 + I21I, 1, // I2C1 Invisidble 1 + I22I, 1, // I2C2 Invisidble 2 + I23I, 1, // I2C3 Invisidble 3 + I24I, 1, // I2C4 Invisidble 4 + I25I, 1, // I2C5 Invisidble 5 + I30I, 1, // I3C0 Invisidble 6 + I31I, 1, // I3C1 Invisidble 7 + I32I, 1, // I3C2 Invisidble 8 + I33I, 1, // I3C3 Invisidble 9 + Offset (0x32), + IDPC, 8, // Identify Dimms per channel - Offset (0x32) +} +OperationRegion(FCFG, SystemMemory, PEBA, 0x01000000) +Field(FCFG, DwordAcc, NoLock, Preserve) +{ + Offset(0x000A3044), + IPDE, 32, //IO Port Decode Enable + Offset(0x000A3048), + IMPE, 32, //IO Memory Port decode Enable + Offset(0x000A3078), + , 2, + LDQ0, 1, // + Offset(0x000A30CB), + , 7, + AUSS, 1, //AutoSizeStart +} +OperationRegion(IOMX, SystemMemory, 0xFED80D00, 0x100) +Field(IOMX, AnyAcc, NoLock, Preserve) +{ + Offset (0x15), + IM15, 8, // + Offset (0x16), + IM16, 8, // + Offset (0x1F), + IM1F, 8, // + Offset (0x20), + IM20, 8, // + Offset (0x44), + IM44, 8, // + Offset (0x46), + IM46, 8, // + Offset (0x4A), + IM4A, 8, // + Offset (0x4B), + IM4B, 8, // + Offset (0x57), + IM57, 8, // + Offset (0x58), + IM58, 8, // + Offset (0x68), + IM68, 8, // + Offset (0x69), + IM69, 8, // + Offset (0x6A), + IM6A, 8, // + Offset (0x6B), + IM6B, 8, // + Offset (0x6D), + IM6D, 8, // +} +OperationRegion(FACR, SystemMemory, 0xFED81E00, 0x100) //Fch AoaC Register +Field(FACR, AnyAcc, NoLock, Preserve) +{ + Offset (0x80), + ,28, + RD28, 1, //Request of Device 28, MAP + , 1, + RQTY, 1, //ReQuestTYpe + Offset (0x84), + ,28, + SD28, 1, //Status of Device 28, MAP + , 1, + Offset (0xA0), //AOACx0000A0 [PwrGood Control] (PwrGoodCtl) + PG1A, 1, +} + + +OperationRegion(LUIE, SystemMemory, 0xFEDC0020, 0x4) //Legacy Uart Io Enable +Field(LUIE, AnyAcc, NoLock, Preserve) +{ + IER0, 1, //2E8 + IER1, 1, //2F8 + IER2, 1, //3E8 + IER3, 1, //3F8 + RESV, 4, //Reserved + WUR0, 2, // 0=Uart0, 1=Uart1, 2=Uart2, 3=Uart3 + WUR1, 2, // + WUR2, 2, // + WUR3, 2, // +} + +// Fch Return I2C/I3C Interrupt +Method (FRII, 1, Serialized) { + if (LEqual (Arg0, 0)) { + return (IIC0) + } elseif (LEqual (Arg0, 1)) { + return (IIC1) + } elseif (LEqual (Arg0, 2)) { + return (IIC2) + } elseif (LEqual (Arg0, 3)) { + return (IIC3) + } elseif (LEqual (Arg0, 4)) { + return (IIC4) + } elseif (LEqual (Arg0, 5)) { + return (IIC5) + } else { + // Return IRQ10 should never be run, it avoids ASL compiler warning. + return (10) + } +} // End of Method (FRII, 1, Serialized) + +// Fch Return Uart Interrupt +Method (FRUI, 1, Serialized) { + if (LEqual (Arg0, 0)) { + return (IUA0) + } elseif (LEqual (Arg0, 1)) { + return (IUA1) + } elseif (LEqual (Arg0, 2)) { + return (IUA2) + } elseif (LEqual (Arg0, 3)) { + return (IUA3) + } else { + // Return IRQ3 should never be run, it avoids ASL compiler warning. + return (3) + } +} // End of Method (FRUI + +Method(SRAD,2, Serialized) //SoftResetAoacDevice, Arg0:Device ID, Arg1:reset period in micro seconds +{ + ShiftLeft(Arg0, 1, Local0) + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + store (one, ADIS) // IsSwControl = 1 + store (zero, ADSR) // SwRstB = 0 + stall (Arg1) + store (one, ADSR) // SwRstB = 1 + store (zero, ADIS) // IsSwControl = 0 + stall (Arg1) +} +Method(DSAD,2, Serialized) //DxSequenceAoacDevice, Arg0:Device ID, Arg1:3=D3, 0=D0 +{ + ShiftLeft(Arg0, 1, Local0) + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + if (LNotEqual(Arg0, ADTD)) { + if (LEqual(Arg1, 0)) { + //D0 + store(0x00, ADTD) + store(one, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x7)) {store(ADDS, Local0)} + } + if (LEqual(Arg1, 3)) { + //D3 + store(zero, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x0)) {store(ADDS, Local0)} + store(0x03, ADTD) + } + } +} +Method(HSAD,2, Serialized) //Hardware dx Sequence Aoac Device, Arg0:Device ID, Arg1:3=D3, 0=D0 +{ + //ShiftLeft(1, Arg0, Local3) //caculate bit map location + ShiftLeft(Arg0, 1, Local0) //Caculate device register location + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + if (LNotEqual(Arg1, ADTD)) { + if (LEqual(Arg1, 0)) { + store (One, PG1A) //power up + //D0 + store(0x00, ADTD) + store(one, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x7)) {store(ADDS, Local0)} + //Do hareware restore now + // Set RequestType to restore + store (one, RQTY) + store (one, RD28) + // Wait for restore complete + store (SD28, Local0) + while (LNot(Local0)) {store (SD28, Local0)} + } + if (LEqual(Arg1, 3)) { + //Do hareware save first + store (zero, RQTY) + store (one, RD28) + store (SD28, Local0) + while (Local0) {store (SD28, Local0)} + //D3 + store(zero, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x0)) {store(ADDS, Local0)} + store(0x03, ADTD) + store (Zero, PG1A) //power down + } + } +} +OperationRegion(FPIC, SystemIo, 0xc00, 0x02)//Fch Pci Interrupt Connector +Field(FPIC, AnyAcc, NoLock, Preserve) +{ + FPII, 8, + FPID, 8, +} +IndexField(FPII, FPID, ByteAcc, NoLock, Preserve) { + Offset (0xF0), //Interrupt for I2C/I3C/UART + IIC0, 8, + IIC1, 8, + IIC2, 8, + IIC3, 8, + IUA0, 8, + IUA1, 8, + IIC4, 8, + IIC5, 8, + IUA2, 8, + IUA3, 8, +} + +Method(CKUL,1, Serialized) +{ + //Check if legacy UART is enabled. Return 1: enabled, 0:no legacy UART enabled. + if (LAnd (LEqual (IER0, 1), LEqual (WUR0, Arg0))) {Return (1)} + elseif (LAnd (LEqual (IER1, 1), LEqual (WUR1, Arg0))) {Return (1)} + elseif (LAnd (LEqual (IER2, 1), LEqual (WUR2, Arg0))) {Return (1)} + elseif (LAnd (LEqual (IER3, 1), LEqual (WUR3, Arg0))) {Return (1)} + else {Return (0)} +} + + Device(GPIO) { + Name (_HID, "AMDI0030") + Name (_CID, "AMDI0030") + Name(_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // + // Interrupt resource. In this example, banks 0 & 1 share the same + // interrupt to the parent controller and similarly banks 2 & 3. + // + // N.B. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform + // + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + + // + // Memory resource. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform. + // + Memory32Fixed(ReadWrite, 0xFED81500, 0x400) + //for 11 remote GPIO ( GPIO256~GPIO266) + Memory32Fixed(ReadWrite, 0xFED81200, 0x2C) + }) + + Return (RBUF) + } + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } // End Device GPIO + + + Device(FUR0) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID00") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {3} + Memory32Fixed(ReadWrite, 0xFEDC9000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDC7000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA0, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT0E, one)) { + if (LEqual(CKUL(0), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT0I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR0 + + Device(FUR1) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID01") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {14} + Memory32Fixed(ReadWrite, 0xFEDCA000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDC8000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA1, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT1E, one)) { + if (LEqual(CKUL(1), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT1I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR1 + + Device(FUR2) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID02") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {5} + Memory32Fixed(ReadWrite, 0xFEDCE000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDCC000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA2, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT2E, one)) { + if (LEqual(CKUL(2), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT2I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR2 + + Device(FUR3) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,"ID03") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {15} + Memory32Fixed(ReadWrite, 0xFEDCF000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDCD000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IUA3, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT3E, one)) { + if (LEqual(CKUL(3), one) ) {Return (0)} //if legacy uart enabled ,hide it. + if (LEqual(UT3I, one) ) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR3 + + Device(I2CA) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x0) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC0, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC0E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I20I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (5, 200)} + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, one) || LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CA + + Device(I2CB) + { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x1) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC1, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC1E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I21I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (6, 200)} + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, one) || LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CB + + Device(I2CC) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x2) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC2, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC2E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I22I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (7, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CC + + Device(I2CD) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x3) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC3, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC3E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I23I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + Method(RSET,0) { SRAD (8, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + if (LEqual(IDPC, 2)) { + Return(Buffer(One){0x01}) + } Else { + Return(Buffer(One){0x00}) + } + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CD + + Device(I2CE) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x4) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {22} + Memory32Fixed(ReadWrite, 0xFEDC6000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC4, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC4E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I24I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (9, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + Return(Buffer(One){0x00}) + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CE + + Device(I2CF) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x5) + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {23} + Memory32Fixed(ReadWrite, 0xFEDCB000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC5, IRQW) + Return(BUF0) // return the result + }// end _CRS method + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(IC5E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I25I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (10, 200)} + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("48DFFC9D-B5A5-48B0-8BA8-28D4E674B25A"))) + { + Return(Buffer(One){0x00}) + } Else { + Return(Buffer(One){0x00}) + } + } + } // End Device I2CF + + + Device(I3CA) { + Name(_UID,0x0) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDD2000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC0, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I30E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I30I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (21, 200)} + +} // End Device I3C0 + + + Device(I3CB) { + Name(_UID,0x1) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDD3000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC1, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I31E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I31I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (13, 200)} + +} // End Device I3C1 + + + Device(I3CC) { + Name(_UID,0x2) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDD4000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC2, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I32E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I32I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (14, 200)} + +} // End Device I3C2 + + + Device(I3CD) { + Name(_UID,0x3) + // I3C DisCo Definition + Name(_HID, "AMDI0015") + Method(_CRS, 0, Serialized) { + Name(BUF0, ResourceTemplate(){ + Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDD6000, 0x1000) + }) + // Create pointers to the specific byte + CreateWordField (BUF0, 0x05, IRQW) + //Modify the IRQ + Store (IIC3, IRQW) + Return(BUF0) // return the result + }// end _CRS method + + Method(_STA, 0, NotSerialized) { + Store (0x0, Local0) + If (LGreaterEqual(TSOS, 0x70)) { + If (LEqual(I33E, one)) { + Store (0x0F, Local0) + } + } + If (LEqual (I33I, One)) { + Store (0x0, Local0) + } + Return (Local0) + } + + Method(RSET,0) { SRAD (15, 200)} + +} // End Device I3C3 + + + + +} // End of Scope(\_SB) + diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/BoardModulePkg.dec b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/BoardModulePkg.dec new file mode 100644 index 0000000000000000000000000000000000000000..f2c7f61696fc07e577798970286ef42b5f57b99a --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/BoardModulePkg.dec @@ -0,0 +1,73 @@ +## @file +# This package provides the modules that build for a full feature platform. +# This BoardModulePkg should only depend on EDKII Core packages and MinPlatformPkg. +# +# The DEC files are used by the utilities that parse DSC and +# INF files to generate AutoGen.c and AutoGen.h files +# for the build infrastructure. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + DEC_SPECIFICATION = 0x00010017 + PACKAGE_NAME = BoardModulePkg + PACKAGE_VERSION = 0.1 + PACKAGE_GUID = 30EEB750-574D-45AA-8895-D77161019BC7 + + +[Includes] + Include + +[LibraryClasses] + ## @libraryclass Provide services to access CMOS area. + CmosAccessLib|Include/Library/CmosAccessLib.h + + ## @libraryclass Provide platform relevant services to access CMOS area. + PlatformCmosAccessLib|Include/Library/PlatformCmosAccessLib.h + + ## @libraryclass Provide services to get BIOS ID information. + BiosIdLib|Include/Library/BiosIdLib.h + + ## @libraryclass Provides a service to determine the firmware boot media device. + FirmwareBootMediaInfoLib|Include/Library/FirmwareBootMediaInfoLib.h + +[Guids] + ## Include Include/Guid/BiosId.h + gBiosIdGuid = { 0xC3E36D09, 0x8294, 0x4b97, { 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 } } + + ## GUID to publish BIOS information HOB + gBiosInfoGuid = { 0x09d0d15c, 0xe9f0, 0x4dfc, {0x9e, 0x0b, 0x39, 0x33, 0x1f, 0xca, 0x66, 0x85} } + + ## {7F4EE1A3-C1F3-43E4-BA1A-39DCDE46C343} + gBoardModulePkgTokenSpaceGuid = { 0x7f4ee1a3, 0xc1f3, 0x43e4, { 0xba, 0x1a, 0x39, 0xdc, 0xde, 0x46, 0xc3, 0x43 } } + +[Protocols] + gBoardBdsBootFromDevicePathProtocolGuid = { 0x446a068f, 0xa755, 0x425a, { 0xba, 0x2a, 0x1f, 0x67, 0xd3, 0xd6, 0xce, 0xe2 } } + +[PcdsFixedAtBuild] + ## PcdPs2KbMsEnable 0x0:Disable, 0x1:Enable + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|0x00|UINT8|0x00000001 + + ## SuperIo Pci ISA Bridge info. It is an array that contains the Segment, Bus, Device and Function + # information describing the PCI Device Info. The first byte is the segment number, + # the second is the bus number, third byte is the device number, the fourth byte + # is the Function. + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000002 + + ## PcdUart1Enable 0x0:Disable, 0x1:Enable + gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x00|UINT8|0x00000003 + gBoardModulePkgTokenSpaceGuid.PcdUart1IrqMask|0x0010|UINT16|0x00000004 + gBoardModulePkgTokenSpaceGuid.PcdUart1IoPort|0x03F8|UINT16|0x00000005 + gBoardModulePkgTokenSpaceGuid.PcdUart1Length|0x08|UINT8|0x00000006 + + ## PcdUart2Enable 0x0:Disable, 0x1:Enable + gBoardModulePkgTokenSpaceGuid.PcdUart2Enable|0x00|UINT8|0x00000007 + gBoardModulePkgTokenSpaceGuid.PcdUart2IrqMask|0x0008|UINT16|0x00000008 + gBoardModulePkgTokenSpaceGuid.PcdUart2IoPort|0x02F8|UINT16|0x00000009 + gBoardModulePkgTokenSpaceGuid.PcdUart2Length|0x08|UINT8|0x0000000A diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Include/Library/BoardBdsHookLib.h b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Include/Library/BoardBdsHookLib.h new file mode 100644 index 0000000000000000000000000000000000000000..db3e787e03edb6b3b2312646ac4ba0da22281a7c --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Include/Library/BoardBdsHookLib.h @@ -0,0 +1,113 @@ +/** @file +Header file for BDS Hook Library + +Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BOARD_BDS_HOOK_LIB_H_ +#define _BOARD_BDS_HOOK_LIB_H_ + +#include +#include + +#define BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL_GUID \ + { 0x446a068f, 0xa755, 0x425a, \ + { 0xba, 0x2a, 0x1f, 0x67, 0xd3, 0xd6, 0xce, 0xe2 }} + +struct _BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL { + UINT8 IpmiBootDeviceSelectorType; + EFI_DEVICE_PATH_PROTOCOL *Device; +}; + +typedef struct _BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL; + +extern EFI_GUID gBoardBdsBootFromDevicePathProtocolGuid; +/** + This is the callback function for Bds Ready To Boot event. + + @param Event Pointer to this event + @param Context Event hanlder private data + + @retval None. +**/ +VOID +EFIAPI +BdsReadyToBootCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + This is the callback function for Smm Ready To Lock event. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsSmmReadyToLockCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + This is the callback function for PCI ENUMERATION COMPLETE. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsPciEnumCompleteCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + Before console after trusted console event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsBeforeConsoleAfterTrustedConsoleCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + Before console before end of DXE event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsBeforeConsoleBeforeEndOfDxeGuidCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + After console ready before boot option event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsAfterConsoleReadyBeforeBootOptionCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h new file mode 100644 index 0000000000000000000000000000000000000000..8a064c01656c160047f09a62aa1290b611fd6fc4 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h @@ -0,0 +1,273 @@ +/** @file + Header file for BDS Hook Library + +Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BOARD_BDS_HOOK_H_ +#define _BOARD_BDS_HOOK_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/// +/// For boot order override. +/// +#define IPMI_BOOT_OVERRIDE_VAR_NAME L"IpmiBootOverride" +#define IS_FIRST_BOOT_VAR_NAME L"IsFirstBoot" + +/// +/// ConnectType +/// +#define CONSOLE_OUT 0x00000001 +#define STD_ERROR 0x00000002 +#define CONSOLE_IN 0x00000004 +#define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) + +extern EFI_GUID gUefiShellFileGuid; +extern EFI_BOOT_MODE gBootMode; + +#define gPciRootBridge \ + { \ + { \ + ACPI_DEVICE_PATH, \ + ACPI_DP, \ + { \ + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ + }, \ + }, \ + EISA_PNP_ID (0x0A03), \ + 0 \ + } + +#define gEndEntire \ + { \ + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \ + } + +typedef struct { + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINTN ConnectType; +} BDS_CONSOLE_CONNECT_ENTRY; + +// +// Platform Root Bridge +// +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_ROOT_BRIDGE_DEVICE_PATH; + +// +// Below is the platform console device path +// +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH IsaBridge; + ACPI_HID_DEVICE_PATH Keyboard; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_KEYBOARD_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciDevice; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_ONBOARD_CONTROLLER_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH Pci0Device; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_PEG_ROOT_CONTROLLER_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciBridge; + PCI_DEVICE_PATH PciDevice; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_PCI_CONTROLLER_DEVICE_PATH; + +// +// Below is the boot option device path +// + +#define CLASS_HID 3 +#define SUBCLASS_BOOT 1 +#define PROTOCOL_KEYBOARD 1 + +typedef struct { + USB_CLASS_DEVICE_PATH UsbClass; + EFI_DEVICE_PATH_PROTOCOL End; +} USB_CLASS_FORMAT_DEVICE_PATH; + +extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath; + +// +// Platform BDS Functions +// + + +/** + Perform the memory test base on the memory test intensive level, + and update the memory resource. + + @param Level The memory test intensive level. + + @retval EFI_STATUS Success test all the system memory and update + the memory resource + +**/ +EFI_STATUS +MemoryTest ( + IN EXTENDMEM_COVERAGE_LEVEL Level + ); + +/** + Connect with predeined platform connect sequence, + the OEM/IBV can customize with their own connect sequence. + + @param[in] BootMode Boot mode of this boot. +**/ +VOID +ConnectSequence ( + IN EFI_BOOT_MODE BootMode + ); + + +/** + Compares boot priorities of two boot options + + @param Left The left boot option + @param Right The right boot option + + @return The difference between the Left and Right + boot options + **/ +INTN +EFIAPI +CompareBootOption ( + CONST VOID *Left, + CONST VOID *Right + ); + +/** + Compares boot priorities of two boot options, while giving PXE the highest priority + + @param Left The left boot option + @param Right The right boot option + + @return The difference between the Left and Right + boot options +**/ +INTN +EFIAPI +CompareBootOptionPxePriority ( + CONST VOID *Left, + CONST VOID *Right + ); + +/** + Compares boot priorities of two boot options, while giving HDD the highest priority + + @param Left The left boot option + @param Right The right boot option + + @return The difference between the Left and Right + boot options +**/ +INTN +EFIAPI +CompareBootOptionHddPriority ( + CONST VOID *Left, + CONST VOID *Right + ); + +/** + This function is called after all the boot options are enumerated and ordered properly. +**/ +VOID +RegisterStaticHotkey ( + VOID + ); + +/** + Registers/Unregisters boot option hotkey + + @param OptionNumber The boot option number for the key option. + @param Key The the key input + @param Add Flag to indicate to add or remove a key +**/ +VOID +RegisterDefaultBootOption ( + VOID + ); + +/** + Add console variable device paths + + @param ConsoleType ConIn or ConOut + @param ConsoleDevicePath Device path to be added +**/ +VOID +AddConsoleVariable ( + IN CONSOLE_TYPE ConsoleType, + IN EFI_DEVICE_PATH *ConsoleDevicePath + ); + +/** + Returns the boot option type of a device + + @param DevicePath The path of device whose boot option type + to be returned + @retval -1 Device type not found + @retval > -1 Device type found +**/ +UINT8 +BootOptionType ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); +#endif diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c new file mode 100644 index 0000000000000000000000000000000000000000..8836b7d3c44a625924e76a710becdd981665f215 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c @@ -0,0 +1,1646 @@ +/** @file + This library registers Bds callbacks. It is a default library + implementation instance of the BDS hook library + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "BoardBdsHook.h" + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE gBootMode; +BOOLEAN gPPRequireUIConfirm; +extern UINTN mBootMenuOptionNumber; + + +GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = { + { + { + MESSAGING_DEVICE_PATH, + MSG_USB_CLASS_DP, + { + (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), + (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) + } + }, + 0xffff, // VendorId + 0xffff, // ProductId + CLASS_HID, // DeviceClass + SUBCLASS_BOOT, // DeviceSubClass + PROTOCOL_KEYBOARD // DeviceProtocol + }, + gEndEntire +}; + + +// +// BDS Platform Functions +// +BOOLEAN +IsMorBitSet ( + VOID + ) +{ + UINTN MorControl; + EFI_STATUS Status; + UINTN DataSize; + + // + // Check if the MOR bit is set. + // + DataSize = sizeof (MorControl); + Status = gRT->GetVariable ( + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + NULL, + &DataSize, + &MorControl + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, " gEfiMemoryOverwriteControlDataGuid doesn't exist!!***\n")); + MorControl = 0; + } else { + DEBUG ((DEBUG_INFO, " Get the gEfiMemoryOverwriteControlDataGuid = %x!!***\n", MorControl)); + } + + return (BOOLEAN) (MorControl & 0x01); +} + + +/** + Prints device paths. + @param Name The device name. + @param DevicePath The device path to be printed +**/ +VOID +EFIAPI +DumpDevicePath ( + IN CHAR16 *Name, + IN EFI_DEVICE_PATH *DevicePath + ) +{ + CHAR16 *Str; + Str = ConvertDevicePathToText (DevicePath, TRUE, TRUE); + DEBUG ((DEBUG_INFO, "%s: %s\n", Name, Str)); + if (Str != NULL) { + FreePool (Str); + } +} + +/** + Return whether the device is trusted console. + + @param Device The device to be tested. + + @retval TRUE The device can be trusted. + @retval FALSE The device cannot be trusted. +**/ +BOOLEAN +IsTrustedConsole ( + IN CONSOLE_TYPE ConsoleType, + IN EFI_DEVICE_PATH_PROTOCOL *Device + ) +{ + VOID *TrustedConsoleDevicepath; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *Instance; + UINTN Size; + EFI_DEVICE_PATH_PROTOCOL *ConsoleDevice; + + if (Device == NULL) { + return FALSE; + } + + ConsoleDevice = DuplicateDevicePath (Device); + + TrustedConsoleDevicepath = NULL; + + switch (ConsoleType) { + case ConIn: + TrustedConsoleDevicepath = DuplicateDevicePath (PcdGetPtr (PcdTrustedConsoleInputDevicePath)); + break; + case ConOut: + // + // Check GOP and remove last node + // + TempDevicePath = ConsoleDevice; + while (!IsDevicePathEndType (TempDevicePath)) { + if (DevicePathType (TempDevicePath) == ACPI_DEVICE_PATH && + DevicePathSubType (TempDevicePath) == ACPI_ADR_DP) { + SetDevicePathEndNode (TempDevicePath); + break; + } + TempDevicePath = NextDevicePathNode (TempDevicePath); + } + + TrustedConsoleDevicepath = DuplicateDevicePath (PcdGetPtr (PcdTrustedConsoleOutputDevicePath)); + break; + default: + ASSERT (FALSE); + break; + } + + TempDevicePath = TrustedConsoleDevicepath; + do { + Instance = GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance == NULL) { + break; + } + + if (CompareMem (ConsoleDevice, Instance, Size - END_DEVICE_PATH_LENGTH) == 0) { + FreePool (Instance); + FreePool (ConsoleDevice); + if (TempDevicePath != NULL) { + FreePool (TempDevicePath); + } + return TRUE; + } + + FreePool (Instance); + } while (TempDevicePath != NULL); + + FreePool (ConsoleDevice); + if (TempDevicePath != NULL) { + FreePool (TempDevicePath); + } + return FALSE; +} + + +/** + Return whether the USB device path is in a short form. + + @param DevicePath The device path to be tested. + + @retval TRUE The device path is in short form. + @retval FALSE The device path is not in short form. +**/ +BOOLEAN +IsUsbShortForm ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + if ((DevicePathType (DevicePath) == MESSAGING_DEVICE_PATH) && + ((DevicePathSubType (DevicePath) == MSG_USB_CLASS_DP) || + (DevicePathSubType (DevicePath) == MSG_USB_WWID_DP)) ) { + return TRUE; + } + + return FALSE; +} + +/** + Connect the USB short form device path. + + @param DevicePath USB short form device path + + @retval EFI_SUCCESS Successfully connected the USB device + @retval EFI_NOT_FOUND Cannot connect the USB device + @retval EFI_INVALID_PARAMETER The device path is invalid. +**/ +EFI_STATUS +ConnectUsbShortFormDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN HandleCount; + UINTN Index; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 Class[3]; + BOOLEAN AtLeastOneConnected; + + // + // Check the passed in parameters + // + if (DevicePath == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (!IsUsbShortForm (DevicePath)) { + return EFI_INVALID_PARAMETER; + } + + // + // Find the usb host controller firstly, then connect with the remaining device path + // + AtLeastOneConnected = FALSE; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + for (Index = 0; Index < HandleCount; Index++) { + Status = gBS->HandleProtocol ( + Handles[Index], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + if (!EFI_ERROR (Status)) { + // + // Check whether the Pci device is the wanted usb host controller + // + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class); + if (!EFI_ERROR (Status) && + ((PCI_CLASS_SERIAL == Class[2]) && (PCI_CLASS_SERIAL_USB == Class[1]))) { + Status = gBS->ConnectController ( + Handles[Index], + NULL, + DevicePath, + FALSE + ); + if (!EFI_ERROR(Status)) { + AtLeastOneConnected = TRUE; + } + } + } + } + + return AtLeastOneConnected ? EFI_SUCCESS : EFI_NOT_FOUND; +} + + +/** + Return whether the Handle is a vga handle. + + @param Handle The handle to be tested. + + @retval TRUE The handle is a vga handle. + @retval FALSE The handle is not a vga handle.. +**/ +BOOLEAN +IsVgaHandle ( + IN EFI_HANDLE Handle + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + EFI_STATUS Status; + + Status = gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (!EFI_ERROR (Status)) { + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0, + sizeof (Pci) / sizeof (UINT32), + &Pci + ); + if (!EFI_ERROR (Status)) { + if (IS_PCI_VGA (&Pci) || IS_PCI_OLD_VGA (&Pci)) { + return TRUE; + } + } + } + return FALSE; +} + + +/** + Return whether the device path points to a video controller. + + @param DevicePath The device path to be tested. + + @retval TRUE The device path points to a video controller. + @retval FALSE The device path does not point to a video controller. +**/ +EFI_HANDLE +IsVideoController ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *DupDevicePath; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + + DupDevicePath = DuplicateDevicePath (DevicePath); + ASSERT (DupDevicePath != NULL); + if (DupDevicePath == NULL) { + return NULL; + } + + TempDevicePath = DupDevicePath; + Status = gBS->LocateDevicePath ( + &gEfiDevicePathProtocolGuid, + &TempDevicePath, + &DeviceHandle + ); + FreePool (DupDevicePath); + if (EFI_ERROR (Status)) { + return NULL; + } + + if (IsVgaHandle (DeviceHandle)) { + return DeviceHandle; + } else { + return NULL; + } +} + + +/** + Return whether the device path is a GOP device path. + + @param DevicePath The device path to be tested. + + @retval TRUE The device path is a GOP device path. + @retval FALSE The device on the device path is not a GOP device path. +**/ +BOOLEAN +IsGopDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + while (!IsDevicePathEndType (DevicePath)) { + if (DevicePathType (DevicePath) == ACPI_DEVICE_PATH && + DevicePathSubType (DevicePath) == ACPI_ADR_DP) { + return TRUE; + } + DevicePath = NextDevicePathNode (DevicePath); + } + return FALSE; +} + + +/** + Remove all GOP device path instance from DevicePath and add the Gop to the DevicePath. + + @param DevicePath The device path to be removed + @param Gop The device path to be added. + + @retval Return The updated device path. +**/ +EFI_DEVICE_PATH_PROTOCOL * +UpdateGopDevicePath ( + EFI_DEVICE_PATH_PROTOCOL *DevicePath, + EFI_DEVICE_PATH_PROTOCOL *Gop + ) +{ + UINTN Size; + UINTN GopSize; + EFI_DEVICE_PATH_PROTOCOL *Temp; + EFI_DEVICE_PATH_PROTOCOL *Return; + EFI_DEVICE_PATH_PROTOCOL *Instance; + BOOLEAN Exist; + + Exist = FALSE; + Return = NULL; + GopSize = GetDevicePathSize (Gop); + do { + Instance = GetNextDevicePathInstance (&DevicePath, &Size); + if (Instance == NULL) { + break; + } + if (!IsGopDevicePath (Instance) || + (Size == GopSize && CompareMem (Instance, Gop, GopSize) == 0) + ) { + if (Size == GopSize && CompareMem (Instance, Gop, GopSize) == 0) { + Exist = TRUE; + } + Temp = Return; + Return = AppendDevicePathInstance (Return, Instance); + if (Temp != NULL) { + FreePool (Temp); + } + } + FreePool (Instance); + } while (DevicePath != NULL); + + if (!Exist) { + Temp = Return; + Return = AppendDevicePathInstance (Return, Gop); + if (Temp != NULL) { + FreePool (Temp); + } + } + return Return; +} + +/** + Get Graphics Controller Handle. VgaDevices needs to be freed by caller. + + @param NeedTrustedConsole The flag to determine if trusted console + or non trusted console should be returned + + @retval EFI ERROR No VGA capable devices found + @retval EFI_SUCCESS At least one VGA device found +**/ +EFI_STATUS +EFIAPI +GetGraphicsController ( + IN BOOLEAN NeedTrustedConsole, + IN OUT EFI_HANDLE **VgaDevices, + IN OUT UINTN *VgaDevicesCount + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_HANDLE *PciHandles; + UINTN PciHandlesSize; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINT32 NumDevices; + + if (VgaDevicesCount == NULL || VgaDevices == NULL) { + return EFI_INVALID_PARAMETER; + } + + NumDevices = 0; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &PciHandlesSize, + &PciHandles + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *VgaDevices = AllocateZeroPool (sizeof (EFI_HANDLE) * PciHandlesSize); + if (VgaDevices == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index = 0; Index < PciHandlesSize; Index++) { + Status = gBS->HandleProtocol ( + PciHandles[Index], + &gEfiDevicePathProtocolGuid, + (VOID **) &DevicePath + ); + if (EFI_ERROR(Status)) { + continue; + } + if (!IsVgaHandle (PciHandles[Index])) { + continue; + } + if ((NeedTrustedConsole && IsTrustedConsole (ConOut, DevicePath)) || + ((!NeedTrustedConsole) && (!IsTrustedConsole (ConOut, DevicePath)))) { + VgaDevices[0][NumDevices] = PciHandles[Index]; + NumDevices++; + } + } + *VgaDevicesCount = NumDevices; + if (NumDevices > 0) { + return EFI_SUCCESS; + } + else { + return EFI_NOT_FOUND; + } +} + +/** + Updates Graphic ConOut variable. This function searches for all VGA capable output devices and + adds them to the ConOut variable. + + @param NeedTrustedConsole The flag that determines if trusted console + or non trusted console should be returned +**/ +VOID +UpdateGraphicConOut ( + IN BOOLEAN NeedTrustedConsole + ) +{ + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath; + EFI_DEVICE_PATH_PROTOCOL *ConOutDevicePath; + EFI_DEVICE_PATH_PROTOCOL *UpdatedConOutDevicePath; + EFI_HANDLE *VgaDevices; + UINTN VgaDevicesCount; + UINTN Count; + EFI_STATUS Status; + + Count = 0; + VgaDevicesCount = 0; + + // + // Update ConOut variable + // + Status = GetGraphicsController (NeedTrustedConsole, &VgaDevices, &VgaDevicesCount); + if (Status == EFI_SUCCESS) { + GetEfiGlobalVariable2 (L"ConOut", (VOID **)&ConOutDevicePath, NULL); + if (ConOutDevicePath != NULL) { + DumpDevicePath (L"Original ConOut variable", ConOutDevicePath); + FreePool (ConOutDevicePath); + } + + //Add VGA devices to ConOut + for (Count = 0; Count < VgaDevicesCount; Count++) { + // + // Connect the GOP driver + // + gBS->ConnectController (VgaDevices[Count], NULL, NULL, TRUE); + // + // Get the GOP device path + // NOTE: We may get a device path that contains Controller node in it. + // + GopDevicePath = EfiBootManagerGetGopDevicePath (VgaDevices[Count]); + if (GopDevicePath != NULL) { + GetEfiGlobalVariable2 (L"ConOut", (VOID **)&ConOutDevicePath, NULL); + if (ConOutDevicePath != NULL) { + UpdatedConOutDevicePath = UpdateGopDevicePath (ConOutDevicePath, GopDevicePath); + if (UpdatedConOutDevicePath != NULL) { + gRT->SetVariable ( + L"ConOut", + &gEfiGlobalVariableGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS, + GetDevicePathSize (UpdatedConOutDevicePath), + UpdatedConOutDevicePath + ); + FreePool (UpdatedConOutDevicePath); + } + FreePool (ConOutDevicePath); + } + FreePool (GopDevicePath); + } + } + FreePool (VgaDevices); + } + GetEfiGlobalVariable2 (L"ConOut", (VOID **)&ConOutDevicePath, NULL); + if (ConOutDevicePath != NULL) { + DumpDevicePath (L"Final ConOut variable", ConOutDevicePath); + FreePool (ConOutDevicePath); + } +} + +/** + The function connects the trusted consoles. +**/ +VOID +ConnectTrustedConsole ( + VOID + ) +{ + EFI_DEVICE_PATH_PROTOCOL *Consoles; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *Instance; + EFI_DEVICE_PATH_PROTOCOL *Next; + UINTN Size; + UINTN Index; + EFI_HANDLE Handle; + EFI_STATUS Status; + CHAR16 *ConsoleVar[] = {L"ConIn", L"ConOut"}; + VOID *TrustedConsoleDevicepath; + + TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleInputDevicePath); + DumpDevicePath (L"TrustedConsoleIn", TrustedConsoleDevicepath); + TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleOutputDevicePath); + DumpDevicePath (L"TrustedConsoleOut", TrustedConsoleDevicepath); + + for (Index = 0; Index < sizeof (ConsoleVar) / sizeof (ConsoleVar[0]); Index++) { + + GetEfiGlobalVariable2 (ConsoleVar[Index], (VOID **)&Consoles, NULL); + + TempDevicePath = Consoles; + do { + Instance = GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance == NULL) { + break; + } + if (IsTrustedConsole (Index, Instance)) { + if (IsUsbShortForm (Instance)) { + ConnectUsbShortFormDevicePath (Instance); + } else { + for (Next = Instance; !IsDevicePathEnd (Next); Next = NextDevicePathNode (Next)) { + if (DevicePathType (Next) == ACPI_DEVICE_PATH && DevicePathSubType (Next) == ACPI_ADR_DP) { + break; + } else if (DevicePathType (Next) == HARDWARE_DEVICE_PATH && + DevicePathSubType (Next) == HW_CONTROLLER_DP && + DevicePathType (NextDevicePathNode (Next)) == ACPI_DEVICE_PATH && + DevicePathSubType (NextDevicePathNode (Next)) == ACPI_ADR_DP + ) { + break; + } + } + if (!IsDevicePathEnd (Next)) { + SetDevicePathEndNode (Next); + Status = EfiBootManagerConnectDevicePath (Instance, &Handle); + if (!EFI_ERROR (Status)) { + gBS->ConnectController (Handle, NULL, NULL, TRUE); + } + } else { + EfiBootManagerConnectDevicePath (Instance, NULL); + } + } + } + FreePool (Instance); + } while (TempDevicePath != NULL); + + if (Consoles != NULL) { + FreePool (Consoles); + } + } +} + + +/** + The function connects the trusted Storages. +**/ +VOID +ConnectTrustedStorage ( + VOID + ) +{ + VOID *TrustedStorageDevicepath; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *Instance; + UINTN Size; + EFI_DEVICE_PATH_PROTOCOL *TempStorageDevicePath; + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + + TrustedStorageDevicepath = DuplicateDevicePath (PcdGetPtr (PcdTrustedStorageDevicePath)); + DumpDevicePath (L"TrustedStorage", TrustedStorageDevicepath); + + TempDevicePath = TrustedStorageDevicepath; + do { + Instance = GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance == NULL) { + break; + } + + EfiBootManagerConnectDevicePath (Instance, NULL); + + TempStorageDevicePath = Instance; + + Status = gBS->LocateDevicePath ( + &gEfiDevicePathProtocolGuid, + &TempStorageDevicePath, + &DeviceHandle + ); + if (!EFI_ERROR (Status)) { + gBS->ConnectController (DeviceHandle, NULL, NULL, FALSE); + } + + FreePool (Instance); + } while (TempDevicePath != NULL); + + if (TempDevicePath != NULL) { + FreePool (TempDevicePath); + } +} + + +/** + Check if current BootCurrent variable is internal shell boot option. + + @retval TRUE BootCurrent is internal shell. + @retval FALSE BootCurrent is not internal shell. +**/ +BOOLEAN +BootCurrentIsInternalShell ( + VOID + ) +{ + UINTN VarSize; + UINT16 BootCurrent; + CHAR16 BootOptionName[16]; + UINT8 *BootOption; + UINT8 *Ptr; + BOOLEAN Result; + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; + EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode; + EFI_GUID *GuidPoint; + + BootOption = NULL; + Result = FALSE; + + // + // Get BootCurrent variable + // + VarSize = sizeof (UINT16); + Status = gRT->GetVariable ( + L"BootCurrent", + &gEfiGlobalVariableGuid, + NULL, + &VarSize, + &BootCurrent + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + // + // Create boot option Bootxxxx from BootCurrent + // + UnicodeSPrint (BootOptionName, sizeof(BootOptionName), L"Boot%04X", BootCurrent); + + GetEfiGlobalVariable2 (BootOptionName, (VOID **) &BootOption, &VarSize); + if (BootOption == NULL || VarSize == 0) { + return FALSE; + } + + Ptr = BootOption; + Ptr += sizeof (UINT32); + Ptr += sizeof (UINT16); + Ptr += StrSize ((CHAR16 *) Ptr); + TempDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr; + LastDeviceNode = TempDevicePath; + while (!IsDevicePathEnd (TempDevicePath)) { + LastDeviceNode = TempDevicePath; + TempDevicePath = NextDevicePathNode (TempDevicePath); + } + GuidPoint = EfiGetNameGuidFromFwVolDevicePathNode ( + (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode + ); + if ((GuidPoint != NULL) && + ((CompareGuid (GuidPoint, &gUefiShellFileGuid)))) { + // + // if this option is internal shell, return TRUE + // + Result = TRUE; + } + + if (BootOption != NULL) { + FreePool (BootOption); + BootOption = NULL; + } + + return Result; +} + +/** + This function will change video resolution and text mode + for internl shell when internal shell is launched. + + @param None. + + @retval EFI_SUCCESS Mode is changed successfully. + @retval Others Mode failed to changed. +**/ +EFI_STATUS +EFIAPI +ChangeModeForInternalShell ( + VOID + ) +{ + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; + EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *SimpleTextOut; + UINTN SizeOfInfo; + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info; + UINT32 MaxGopMode; + UINT32 MaxTextMode; + UINT32 ModeNumber; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN Index; + UINTN CurrentColumn; + UINTN CurrentRow; + + // + // Internal shell mode + // + UINT32 mShellModeColumn; + UINT32 mShellModeRow; + UINT32 mShellHorizontalResolution; + UINT32 mShellVerticalResolution; + + + // + // Get user defined text mode for internal shell only once. + // + mShellHorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution); + mShellVerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution); + mShellModeColumn = PcdGet32 (PcdSetupConOutColumn); + mShellModeRow = PcdGet32 (PcdSetupConOutRow); + + + Status = gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiGraphicsOutputProtocolGuid, + (VOID**)&GraphicsOutput + ); + if (EFI_ERROR (Status)) { + GraphicsOutput = NULL; + } + + Status = gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiSimpleTextOutProtocolGuid, + (VOID**)&SimpleTextOut + ); + if (EFI_ERROR (Status)) { + SimpleTextOut = NULL; + } + + if ((GraphicsOutput == NULL) || (SimpleTextOut == NULL)) { + return EFI_UNSUPPORTED; + } + + MaxGopMode = GraphicsOutput->Mode->MaxMode; + MaxTextMode = SimpleTextOut->Mode->MaxMode; + + // + // 1. If current video resolution is same with new video resolution, + // video resolution need not be changed. + // 1.1. If current text mode is same with new text mode, text mode need not be change. + // 1.2. If current text mode is different with new text mode, text mode need be change to new text mode. + // 2. If current video resolution is different with new video resolution, we need restart whole console drivers. + // + for (ModeNumber = 0; ModeNumber < MaxGopMode; ModeNumber++) { + Status = GraphicsOutput->QueryMode ( + GraphicsOutput, + ModeNumber, + &SizeOfInfo, + &Info + ); + if (!EFI_ERROR (Status)) { + if ((Info->HorizontalResolution == mShellHorizontalResolution) && + (Info->VerticalResolution == mShellVerticalResolution)) { + if ((GraphicsOutput->Mode->Info->HorizontalResolution == mShellHorizontalResolution) && + (GraphicsOutput->Mode->Info->VerticalResolution == mShellVerticalResolution)) { + // + // If current video resolution is same with new resolution, + // then check if current text mode is same with new text mode. + // + Status = SimpleTextOut->QueryMode (SimpleTextOut, SimpleTextOut->Mode->Mode, &CurrentColumn, &CurrentRow); + ASSERT_EFI_ERROR (Status); + if (CurrentColumn == mShellModeColumn && CurrentRow == mShellModeRow) { + // + // Current text mode is same with new text mode, text mode need not be change. + // + FreePool (Info); + return EFI_SUCCESS; + } else { + // + // Current text mode is different with new text mode, text mode need be change to new text mode. + // + for (Index = 0; Index < MaxTextMode; Index++) { + Status = SimpleTextOut->QueryMode (SimpleTextOut, Index, &CurrentColumn, &CurrentRow); + if (!EFI_ERROR(Status)) { + if ((CurrentColumn == mShellModeColumn) && (CurrentRow == mShellModeRow)) { + // + // New text mode is supported, set it. + // + Status = SimpleTextOut->SetMode (SimpleTextOut, Index); + ASSERT_EFI_ERROR (Status); + // + // Update text mode PCD. + // + Status = PcdSet32S (PcdConOutColumn, mShellModeColumn); + ASSERT_EFI_ERROR (Status); + + Status = PcdSet32S (PcdConOutRow, mShellModeRow); + ASSERT_EFI_ERROR (Status); + + FreePool (Info); + return EFI_SUCCESS; + } + } + } + if (Index == MaxTextMode) { + // + // If new text mode is not supported, return error. + // + FreePool (Info); + return EFI_UNSUPPORTED; + } + } + } else { + FreePool (Info); + // + // If current video resolution is not same with the new one, set new video resolution. + // In this case, the driver which produces simple text out need be restarted. + // + Status = GraphicsOutput->SetMode (GraphicsOutput, ModeNumber); + if (!EFI_ERROR (Status)) { + // + // Set PCD to restart GraphicsConsole and Consplitter to change video resolution + // and produce new text mode based on new resolution. + // + Status = PcdSet32S (PcdVideoHorizontalResolution, mShellHorizontalResolution); + ASSERT_EFI_ERROR (Status); + + Status = PcdSet32S (PcdVideoVerticalResolution, mShellVerticalResolution); + ASSERT_EFI_ERROR (Status); + + Status = PcdSet32S (PcdConOutColumn, mShellModeColumn); + ASSERT_EFI_ERROR (Status); + + Status = PcdSet32S (PcdConOutRow, mShellModeRow); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSimpleTextOutProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < HandleCount; Index++) { + gBS->DisconnectController (HandleBuffer[Index], NULL, NULL); + } + for (Index = 0; Index < HandleCount; Index++) { + gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE); + } + if (HandleBuffer != NULL) { + FreePool (HandleBuffer); + } + break; + } + } + } + } + FreePool (Info); + } + } + + if (ModeNumber == MaxGopMode) { + // + // If the new resolution is not supported, return error. + // + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + + +/** + The function connects the trusted consoles and then call the PP processing library interface. +**/ +VOID +ProcessTcgPp ( + VOID + ) +{ + gPPRequireUIConfirm |= Tcg2PhysicalPresenceLibNeedUserConfirm(); + + if (gPPRequireUIConfirm) { + ConnectTrustedConsole (); + } + + Tcg2PhysicalPresenceLibProcessRequest (NULL); +} + + +/** + The function connects the trusted storage to perform TPerReset. +**/ +VOID +ProcessTcgMor ( + VOID + ) +{ + if (IsMorBitSet ()) { + ConnectTrustedConsole(); + ConnectTrustedStorage(); + } +} + + +/** + Update the ConIn variable with USB Keyboard device path,if its not already exists in ConIn +**/ +VOID +EnumUsbKeyboard ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "[EnumUsbKeyboard]\n")); + EfiBootManagerUpdateConsoleVariable (ConIn, (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, NULL); + // + // Append Usb Keyboard short form DevicePath into "ConInDev" + // + EfiBootManagerUpdateConsoleVariable (ConInDev, (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, NULL); +} + + +/** + Connect with predeined platform connect sequence, + the OEM/IBV can customize with their own connect sequence. + + @param[in] BootMode Boot mode of this boot. +**/ +VOID +ConnectSequence ( + IN EFI_BOOT_MODE BootMode + ) +{ + EfiBootManagerConnectAll (); +} + +/** + Connects Root Bridge + **/ +VOID +ConnectRootBridge ( + BOOLEAN Recursive + ) +{ + UINTN RootBridgeHandleCount; + EFI_HANDLE *RootBridgeHandleBuffer; + UINTN RootBridgeIndex; + + RootBridgeHandleCount = 0; + gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &RootBridgeHandleCount, + &RootBridgeHandleBuffer + ); + for (RootBridgeIndex = 0; RootBridgeIndex < RootBridgeHandleCount; RootBridgeIndex++) { + gBS->ConnectController (RootBridgeHandleBuffer[RootBridgeIndex], NULL, NULL, Recursive); + } +} +/** + Add console variable device paths + + @param ConsoleType ConIn or ConOut + @param ConsoleDevicePath Device path to be added +**/ +VOID +AddConsoleVariable ( + IN CONSOLE_TYPE ConsoleType, + IN EFI_DEVICE_PATH *ConsoleDevicePath + ) +{ + EFI_DEVICE_PATH *TempDevicePath; + EFI_DEVICE_PATH *Instance; + UINTN Size; + EFI_HANDLE GraphicsControllerHandle; + EFI_DEVICE_PATH *GopDevicePath; + + TempDevicePath = DuplicateDevicePath (ConsoleDevicePath); + do { + Instance = GetNextDevicePathInstance (&TempDevicePath, &Size); + if (Instance == NULL) { + break; + } + + switch (ConsoleType) { + case ConIn: + if (IsUsbShortForm (Instance)) { + // + // Append Usb Keyboard short form DevicePath into "ConInDev" + // + EfiBootManagerUpdateConsoleVariable (ConInDev, Instance, NULL); + } + EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL); + break; + case ConOut: + GraphicsControllerHandle = IsVideoController (Instance); + if (GraphicsControllerHandle == NULL) { + EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL); + } else { + // + // Connect the GOP driver + // + gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE); + // + // Get the GOP device path + // NOTE: We may get a device path that contains Controller node in it. + // + GopDevicePath = EfiBootManagerGetGopDevicePath (GraphicsControllerHandle); + if (GopDevicePath != NULL) { + EfiBootManagerUpdateConsoleVariable (ConsoleType, GopDevicePath, NULL); + } + } + break; + default: + ASSERT(FALSE); + break; + } + + FreePool (Instance); + } while (TempDevicePath != NULL); + + if (TempDevicePath != NULL) { + FreePool (TempDevicePath); + } +} + + +/** + This is the callback function for PCI ENUMERATION COMPLETE. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsPciEnumCompleteCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *ProtocolPointer; + EFI_DEVICE_PATH_PROTOCOL *VarConOut; + EFI_DEVICE_PATH_PROTOCOL *VarConIn; + + Status = EFI_SUCCESS; + + // + // Check if this is first time called by EfiCreateProtocolNotifyEvent() or not, + // if it is, we will skip it until real event is triggered + // + Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **) &ProtocolPointer); + if (EFI_SUCCESS != Status) { + return; + } + //gBS->CloseEvent (Event); + + + DEBUG ((DEBUG_INFO, "Event BdsPciEnumCompleteCallback callback starts\n")); + + gBootMode = GetBootModeHob (); + + // + // Fill ConIn/ConOut in Full Configuration boot mode + // + DEBUG ((DEBUG_INFO, "PlatformBootManagerInit - %x\n", gBootMode)); + + + if (gBootMode == BOOT_WITH_FULL_CONFIGURATION || + gBootMode == BOOT_WITH_DEFAULT_SETTINGS || + gBootMode == BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS || + gBootMode == BOOT_IN_RECOVERY_MODE) { + + GetEfiGlobalVariable2 (L"ConOut", (VOID **)&VarConOut, NULL); + if (VarConOut != NULL) { + FreePool (VarConOut); + } + + GetEfiGlobalVariable2 (L"ConIn", (VOID **)&VarConIn, NULL); + if (VarConIn != NULL) { + FreePool (VarConIn); + } + + // + // Only fill ConIn/ConOut when ConIn/ConOut is empty because we may drop to Full Configuration boot mode in non-first boot + // + if (VarConOut == NULL || VarConIn == NULL) { + if (PcdGetSize (PcdTrustedConsoleOutputDevicePath) >= sizeof(EFI_DEVICE_PATH_PROTOCOL)) { + AddConsoleVariable (ConOut, PcdGetPtr (PcdTrustedConsoleOutputDevicePath)); + } + if (PcdGetSize (PcdTrustedConsoleInputDevicePath) >= sizeof(EFI_DEVICE_PATH_PROTOCOL)) { + AddConsoleVariable (ConIn, PcdGetPtr (PcdTrustedConsoleInputDevicePath)); + } + } + } + + // + // Enumerate USB keyboard + // + EnumUsbKeyboard (); + + // + // For trusted console it must be handled here. + // + UpdateGraphicConOut (TRUE); + + // + // Register Boot Options + // + RegisterDefaultBootOption (); + + // + // Register Static Hot keys + // + RegisterStaticHotkey (); + + // + // Process Physical Preo + // + PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7010); + if (PcdGetBool (PcdTpm2Enable)) { + ProcessTcgPp (); + ProcessTcgMor (); + } + PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7011); + + // + // Perform memory test + // We should make all UEFI memory and GCD information populated before ExitPmAuth. + // SMM may consume these information. + // + MemoryTest((EXTENDMEM_COVERAGE_LEVEL) PcdGet32 (PcdPlatformMemoryCheckLevel)); +} + +/** + This is the callback function for Smm Ready To Lock. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsSmmReadyToLockCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + VOID *ProtocolPointer; + EFI_STATUS Status; + // + // Check if this is first time called by EfiCreateProtocolNotifyEvent() or not, + // if it is, we will skip it until real event is triggered + // + Status = gBS->LocateProtocol (&gEfiDxeSmmReadyToLockProtocolGuid, NULL, (VOID **) &ProtocolPointer); + if (EFI_SUCCESS != Status) { + return; + } + + DEBUG ((DEBUG_INFO, "Event gEfiDxeSmmReadyToLockProtocolGuid callback starts\n")); + + // + // Dispatch the deferred 3rd party images. + // + EfiBootManagerDispatchDeferredImages (); + + // + // For non-trusted console it must be handled here. + // + UpdateGraphicConOut (FALSE); +} + +/** + ReadyToBoot callback to set video and text mode for internal shell boot. + That will not connect USB controller while CSM and FastBoot are disabled, we need to connect them + before booting to Shell for showing USB devices in Shell. + + When FastBoot is enabled and Windows Console is the chosen Console behavior, input devices will not be connected + by default. Hence, when booting to EFI shell, connecting input consoles are required. + + @param Event Pointer to this event + @param Context Event hanlder private data + + @retval None. +**/ +VOID +EFIAPI +BdsReadyToBootCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + DEBUG ((DEBUG_INFO, "BdsReadyToBootCallback\n")); + + if (BootCurrentIsInternalShell ()) { + + ChangeModeForInternalShell (); + EfiBootManagerConnectAllDefaultConsoles (); + gDS->Dispatch (); + } +} + + +/** + Before console after trusted console event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsBeforeConsoleAfterTrustedConsoleCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + DEBUG ((DEBUG_INFO, "Event gBdsEventBeforeConsoleBeforeEndOfDxeGuid callback starts\n")); + + // + // Connect Root Bridge to make PCI BAR resource allocated and all PciIo created + // + ConnectRootBridge (FALSE); +} + + +/** + Before console before end of DXE event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsBeforeConsoleBeforeEndOfDxeGuidCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + DEBUG ((DEBUG_INFO, "Event gBdsBeforeConsoleBeforeEndOfDxeGuid callback starts\n")); +} + +/** + Compares two device paths to see if FullDevicePath starts with PartialDevicePath. + + @param[in] PartialDevicePath Partial device path pointer. + @param[in] FullDevicePath Complete device path pointer + + @retval TRUE PartialDevicePath was found in FullDevicePath. + @retval FALSE PartialDevicePath was not found in FullDevicePath. + +**/ +BOOLEAN +StartsWithDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *PartialDevicePath, + IN EFI_DEVICE_PATH_PROTOCOL *FullDevicePath + ) +{ + INTN PartialSize; + INTN FullSize; + + //Size includes end of device path node, don't want this to be included in comparison + PartialSize = (INTN)GetDevicePathSize (PartialDevicePath) - sizeof(EFI_DEVICE_PATH_PROTOCOL); + FullSize = (INTN)GetDevicePathSize (FullDevicePath) - sizeof(EFI_DEVICE_PATH_PROTOCOL); + + if (PartialSize <= 0 || FullSize <= 0) { + return FALSE; + } + + if (CompareMem (PartialDevicePath, FullDevicePath, PartialSize) != 0) { + return FALSE; + } + + return TRUE; +} + + +/** + Handle possible IPMI boot overrides by modifying the LoadOptions variable. + + @retval EFI_SUCCESS Boot override successful, or not necessary. + @retval EFI_NOT_FOUND Attempted to override boot to an unsupported boot option. +**/ +EFI_STATUS +HandleIpmiBootOverride ( + ) +{ + UINT8 NvIpmiBootOverride; + UINT8 Index; + UINT8 CurrentIpmiBootOverride; + UINT8 *GetBootOptionsBuffer; + UINT8 *SetBootOptionsBuffer; + UINTN BootOptionCount; + UINTN DataSize; + IPMI_GET_BOOT_OPTIONS_REQUEST BootOptionsRequest; + IPMI_GET_BOOT_OPTIONS_RESPONSE *BootOptionsResponse; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 *BootOptionsParameterData; + IPMI_SET_BOOT_OPTIONS_REQUEST *SetBootOptionsRequest; + IPMI_SET_BOOT_OPTIONS_RESPONSE SetBootOptionsResponse; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 *SetBootOptionsParameterData; + EFI_BOOT_MANAGER_LOAD_OPTION *LoadOptionToManipulate; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + EFI_STATUS Status; + EFI_STATUS BootDevicePathStatus; + BOARD_BDS_BOOT_FROM_DEVICE_PATH_PROTOCOL *BootDevicePathProtocol; + + ZeroMem (&BootOptionsRequest, sizeof (IPMI_GET_BOOT_OPTIONS_REQUEST)); + ZeroMem (&SetBootOptionsResponse, sizeof (IPMI_SET_BOOT_OPTIONS_RESPONSE)); + + LoadOptionToManipulate = NULL; + Status = EFI_SUCCESS; + + // setup buffers + GetBootOptionsBuffer = (UINT8 *)AllocateZeroPool (sizeof (BootOptionsResponse) + sizeof (IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5)); + SetBootOptionsBuffer = (UINT8 *)AllocateZeroPool (sizeof (SetBootOptionsRequest) + sizeof (IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5)); + + // setup parameter dataa + BootOptionsRequest.ParameterSelector.Bits.ParameterSelector = IPMI_BOOT_OPTIONS_PARAMETER_BOOT_FLAGS; + BootOptionsResponse = (IPMI_GET_BOOT_OPTIONS_RESPONSE *)&GetBootOptionsBuffer[0]; + Status = IpmiGetSystemBootOptions (&BootOptionsRequest, BootOptionsResponse); + BootOptionsParameterData = (IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 *)BootOptionsResponse->ParameterData; + + if (EFI_ERROR (Status)) { + Status = EFI_UNSUPPORTED; + goto end; + } + + // setup SetBootOptions parameter data + SetBootOptionsRequest = (IPMI_SET_BOOT_OPTIONS_REQUEST *)&SetBootOptionsBuffer[0]; + SetBootOptionsParameterData = (IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 *)SetBootOptionsRequest->ParameterData; + + BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot); + + // if received valid IPMI data, then override boot option + if (!BootOptionsResponse->ParameterValid.Bits.ParameterValid && BootOptionsParameterData->Data1.Bits.BootFlagValid) { + // get non volatile IpmiBootOverride variable + DataSize = sizeof (UINT8); + Status = gRT->GetVariable ( + IPMI_BOOT_OVERRIDE_VAR_NAME, + &gEfiCallerIdGuid, + NULL, + &DataSize, + &NvIpmiBootOverride + ); + if (EFI_ERROR (Status)) { + NvIpmiBootOverride = IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE; + } + + CurrentIpmiBootOverride = BootOptionsParameterData->Data2.Bits.BootDeviceSelector; + + + BootDevicePathStatus = gBS->LocateProtocol(&gBoardBdsBootFromDevicePathProtocolGuid, + NULL, + (VOID**)&BootDevicePathProtocol); + + DumpDevicePath (L"\t Found override boot device path: ", BootDevicePathProtocol->Device); + + DEBUG((DEBUG_INFO, "Status after locating gBoardBdsBootFromDevicePathProtocolGuid - %r\n", BootDevicePathStatus)); + if (CurrentIpmiBootOverride == IPMI_BOOT_DEVICE_SELECTOR_BIOS_SETUP) { + DEBUG ((DEBUG_INFO, "[Bds]BiosSetup option override detected via IPMI\n")); + // need to find boot option corresponding to BiosSetup + for (Index = 0; Index < BootOptionCount; Index++) { + if ((StrCmp (BootOptions[Index].Description, L"Enter Setup") == 0) && (BootOptions[Index].Attributes == (LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN))) { + LoadOptionToManipulate = &BootOptions[Index]; + } else if (StrCmp (BootOptions[Index].Description, L"Enter Setup") == 0) { + // delete duplicate BiosSetup Menu option + EfiBootManagerDeleteLoadOptionVariable (BootOptions[Index].OptionNumber, LoadOptionTypeBoot); + } + } + + if (LoadOptionToManipulate == NULL) { + Status = EFI_UNSUPPORTED; + goto end; + } + + // have Load option for bios setup, now update loadoptions + Status = EfiBootManagerDeleteLoadOptionVariable (LoadOptionToManipulate->OptionNumber, LoadOptionTypeBoot); + LoadOptionToManipulate->Attributes &= LOAD_OPTION_CATEGORY_BOOT; + LoadOptionToManipulate->Attributes |= (LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN); + Status = EfiBootManagerAddLoadOptionVariable (LoadOptionToManipulate, 0); // add back in loadoptions in 0th index (first option) + } + else if (CurrentIpmiBootOverride == IPMI_BOOT_DEVICE_SELECTOR_PXE) { + DEBUG((DEBUG_INFO, "[Bds]Pxe option override detected via IPMI\n")); + EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOptionPxePriority); + BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot); + + if(BootDevicePathStatus == EFI_SUCCESS && BootDevicePathProtocol->IpmiBootDeviceSelectorType == IPMI_BOOT_DEVICE_SELECTOR_PXE) { + //find where the DevicePath override boot option is + for (Index = 0; Index < BootOptionCount; Index++) { + if (StartsWithDevicePath(BootDevicePathProtocol->Device, BootOptions[Index].FilePath) && BootOptionType (BootOptions[Index].FilePath) == MSG_IPv4_DP) { + if (Index == 0) { + break; + } + LoadOptionToManipulate = &BootOptions[Index]; + Status = EfiBootManagerDeleteLoadOptionVariable (LoadOptionToManipulate->OptionNumber, LoadOptionTypeBoot); + Status = EfiBootManagerAddLoadOptionVariable (LoadOptionToManipulate, 0); // add back in loadoptions in 0th index (first option) + break; + } + } + } + } + else if (CurrentIpmiBootOverride == IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE) { + EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOptionHddPriority); + } + else if ((CurrentIpmiBootOverride == IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE) && (CurrentIpmiBootOverride != NvIpmiBootOverride)) { + // delete BiosSetup option corresponding to the override + Status = EfiBootManagerDeleteLoadOptionVariable (BootOptions[0].OptionNumber, LoadOptionTypeBoot); + // re sort boot options + EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption); + } + + // if Ipmi override not persistent, reset boot option to None and persistent to true + if (!BootOptionsParameterData->Data1.Bits.PersistentOptions) { + SetBootOptionsRequest->ParameterValid.Bits.ParameterSelector = IPMI_BOOT_OPTIONS_PARAMETER_BOOT_FLAGS; + CopyMem (SetBootOptionsParameterData, BootOptionsParameterData, sizeof (IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5)); + SetBootOptionsParameterData->Data1.Bits.PersistentOptions = 1; // persistent + SetBootOptionsParameterData->Data2.Bits.BootDeviceSelector = IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE; // revert to no override + Status = IpmiSetSystemBootOptions (SetBootOptionsRequest, &SetBootOptionsResponse); + } + + Status = gRT->SetVariable ( + IPMI_BOOT_OVERRIDE_VAR_NAME, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (UINT8), + &CurrentIpmiBootOverride + ); + } + +end: + // Free buffers + FreePool (GetBootOptionsBuffer); + FreePool (SetBootOptionsBuffer); + return Status; +} + + + +/** + After console ready before boot option event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Event. +**/ +VOID +EFIAPI +BdsAfterConsoleReadyBeforeBootOptionCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_BOOT_MODE LocalBootMode; + EFI_STATUS Status; + BOOLEAN IsFirstBoot; + UINTN DataSize; + DEBUG ((DEBUG_INFO, "Event gBdsAfterConsoleReadyBeforeBootOptionEvent callback starts\n")); + // + // Get current Boot Mode + // + LocalBootMode = gBootMode; + DEBUG ((DEBUG_INFO, "Current local bootmode - %x\n", LocalBootMode)); + + // + // Go the different platform policy with different boot mode + // Notes: this part code can be change with the table policy + // + switch (LocalBootMode) { + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES: + case BOOT_WITH_MINIMAL_CONFIGURATION: + case BOOT_ON_S4_RESUME: + // + // Perform some platform specific connect sequence + // + PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7050); + ConnectSequence (LocalBootMode); + PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7051); + + break; + + case BOOT_WITH_FULL_CONFIGURATION: + case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS: + case BOOT_WITH_DEFAULT_SETTINGS: + default: + // + // Perform some platform specific connect sequence + // + ConnectSequence (LocalBootMode); + + // + // Only in Full Configuration boot mode we do the enumeration of boot device + // + // + // Dispatch all but Storage Oprom explicitly, because we assume Int13Thunk driver is there. + // + + // + // PXE boot option may appear after boot option enumeration + // + + EfiBootManagerRefreshAllBootOption (); + DataSize = sizeof (BOOLEAN); + Status = gRT->GetVariable ( + IS_FIRST_BOOT_VAR_NAME, + &gEfiCallerIdGuid, + NULL, + &DataSize, + &IsFirstBoot + ); + if (EFI_ERROR (Status)) { + // + // If can't find the variable, see it as the first boot + // + IsFirstBoot = TRUE; + } + + if (IsFirstBoot) { + // + // In the first boot, sort the boot option + // + EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption); + IsFirstBoot = FALSE; + Status = gRT->SetVariable ( + IS_FIRST_BOOT_VAR_NAME, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (BOOLEAN), + &IsFirstBoot + ); + } + + break; + } + + HandleIpmiBootOverride (); + + Print (L"Press F2 for Setup, or F7 for BootMenu!\n"); +} diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..27092e21b1e9359c8b534991e02a459267d08e88 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf @@ -0,0 +1,102 @@ +### @file +# Module Information file for the Bds Hook Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BoardBdsHookLib + FILE_GUID = 649A7502-7301-4E3A-A99B-EA91AD6DD7A8 + VERSION_STRING = 1.0 + MODULE_TYPE = DXE_DRIVER + LIBRARY_CLASS = BoardBdsHookLib|DXE_DRIVER + +[LibraryClasses] + BaseLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + DebugLib + PcdLib + PrintLib + DevicePathLib + UefiLib + HobLib + DxeServicesLib + DxeServicesTableLib + HiiLib + UefiBootManagerLib + PerformanceLib + TimerLib + Tcg2PhysicalPresenceLib + IpmiLib + IpmiCommandLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + BoardModulePkg/BoardModulePkg.dec + ManageabilityPkg/ManageabilityPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand ## PRODUCES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformMemoryCheckLevel ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdTrustedStorageDevicePath ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdShellFile ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc ## CONSUMES + +[Sources] + BoardBdsHook.h + BoardBdsHookLib.c + BoardMemoryTest.c + BoardBootOption.c + +[Protocols] + gEfiPciRootBridgeIoProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + gEfiCpuIo2ProtocolGuid ## CONSUMES + gEfiDxeSmmReadyToLockProtocolGuid ## PRODUCES + gEfiGenericMemTestProtocolGuid ## CONSUMES + gEfiDiskInfoProtocolGuid ## CONSUMES + gEfiDevicePathToTextProtocolGuid ## CONSUMES + gEfiSimpleTextInputExProtocolGuid ## CONSUMES + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gEfiFormBrowser2ProtocolGuid ## CONSUMES + gEfiGenericMemTestProtocolGuid ## CONSUMES + gBoardBdsBootFromDevicePathProtocolGuid ## CONSUMES + gEfiDxeSmmReadyToLockProtocolGuid + +[Guids] + gEfiGlobalVariableGuid ## PRODUCES + gEfiMemoryOverwriteControlDataGuid ## PRODUCES + gEfiEndOfDxeEventGroupGuid ## CONSUMES + gBdsEventBeforeConsoleAfterTrustedConsoleGuid + gBdsEventBeforeConsoleBeforeEndOfDxeGuid + gBdsEventAfterConsoleReadyBeforeBootOptionGuid + +[Depex.common.DXE_DRIVER] + gEfiVariableArchProtocolGuid + +[Depex] + TRUE diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c new file mode 100644 index 0000000000000000000000000000000000000000..20734ca6a6fe47bf5ec51d38aa045723c548edb2 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c @@ -0,0 +1,736 @@ +/** @file + Driver for Platform Boot Options support. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BoardBdsHook.h" + +EFI_GUID gUefiShellFileGuid = {0}; +#define UEFI_HARD_DRIVE_NAME L"UEFI Hard Drive" +EFI_GUID mUiFile = { + 0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, 0x31 } +}; +EFI_GUID mBootMenuFile = { + 0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, 0x1D } +}; + +BOOLEAN mContinueBoot = FALSE; +BOOLEAN mBootMenuBoot = FALSE; +BOOLEAN mPxeBoot = FALSE; +BOOLEAN mHotKeypressed = FALSE; +EFI_EVENT HotKeyEvent = NULL; + +UINTN mBootMenuOptionNumber; +UINTN mSetupOptionNumber; + + +/** + This function will create a SHELL BootOption to boot. + + @return Shell Device path for booting. +**/ +EFI_DEVICE_PATH_PROTOCOL * +BdsCreateShellDevicePath ( + VOID + ) +{ + UINTN FvHandleCount; + EFI_HANDLE *FvHandleBuffer; + UINTN Index; + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINTN Size; + UINT32 AuthenticationStatus; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + VOID *Buffer; + + DevicePath = NULL; + Status = EFI_SUCCESS; + + DEBUG ((DEBUG_INFO, "BdsCreateShellDevicePath\n")); + gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &FvHandleCount, + &FvHandleBuffer + ); + + for (Index = 0; Index < FvHandleCount; Index++) { + gBS->HandleProtocol ( + FvHandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + + Buffer = NULL; + Size = 0; + Status = Fv->ReadSection ( + Fv, + &gUefiShellFileGuid, + EFI_SECTION_PE32, + 0, + &Buffer, + &Size, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + // + // Skip if no shell file in the FV + // + continue; + } else { + // + // Found the shell + // + break; + } + } + + if (EFI_ERROR (Status)) { + // + // No shell present + // + if (FvHandleCount) { + FreePool (FvHandleBuffer); + } + return NULL; + } + // + // Build the shell boot option + // + DevicePath = DevicePathFromHandle (FvHandleBuffer[Index]); + + if (FvHandleCount) { + FreePool (FvHandleBuffer); + } + + return DevicePath; +} + + +EFI_STATUS +CreateFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + EFI_BOOT_MANAGER_LOAD_OPTION *BootOption, + UINT32 Attributes, + UINT8 *OptionalData, OPTIONAL + UINT32 OptionalDataSize + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINT32 AuthenticationStatus; + VOID *Buffer; + UINTN Size; + + if ((BootOption == NULL) || (FileGuid == NULL) || (Description == NULL)) { + return EFI_INVALID_PARAMETER; + } + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + + if (!CompareGuid (&gUefiShellFileGuid, FileGuid)) { + Status = gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **) &LoadedImage + ); + if (!EFI_ERROR (Status)) { + Status = gBS->HandleProtocol ( + LoadedImage->DeviceHandle, + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + if (!EFI_ERROR (Status)) { + Buffer = NULL; + Size = 0; + Status = Fv->ReadSection ( + Fv, + FileGuid, + EFI_SECTION_PE32, + 0, + &Buffer, + &Size, + &AuthenticationStatus + ); + if (Buffer != NULL) { + FreePool (Buffer); + } + } + } + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + DevicePath = AppendDevicePathNode ( + DevicePathFromHandle (LoadedImage->DeviceHandle), + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + } else { + DevicePath = AppendDevicePathNode ( + BdsCreateShellDevicePath (), + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + } + + Status = EfiBootManagerInitializeLoadOption ( + BootOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + OptionalData, + OptionalDataSize + ); + FreePool (DevicePath); + return Status; +} + +/** + Return the index of the load option in the load option array. + + The function consider two load options are equal when the + OptionType, Attributes, Description, FilePath and OptionalData are equal. + + @param Key Pointer to the load option to be found. + @param Array Pointer to the array of load options to be found. + @param Count Number of entries in the Array. + + @retval -1 Key wasn't found in the Array. + @retval 0 ~ Count-1 The index of the Key in the Array. +**/ +INTN +PlatformFindLoadOption ( + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key, + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array, + IN UINTN Count + ) +{ + UINTN Index; + + for (Index = 0; Index < Count; Index++) { + if ((Key->OptionType == Array[Index].OptionType) && + (Key->Attributes == Array[Index].Attributes) && + (StrCmp (Key->Description, Array[Index].Description) == 0) && + (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) && + (Key->OptionalDataSize == Array[Index].OptionalDataSize) && + (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) { + return (INTN) Index; + } + } + + return -1; +} + + +/** + Registers a boot option + + @param FileGuid Boot file GUID + @param Description Boot option discription + @param Position Position of the new load option to put in the ****Order variable. + @param Attributes Boot option attributes + @param OptionalData Optional data of the boot option. + @param OptionalDataSize Size of the optional data of the boot option + + @return boot option number +**/ +UINTN +RegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINTN Position, + UINT32 Attributes, + UINT8 *OptionalData, OPTIONAL + UINT32 OptionalDataSize + ) +{ + EFI_STATUS Status; + UINTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + + NewOption.OptionNumber = LoadOptionNumberUnassigned; + Status = CreateFvBootOption (FileGuid, Description, &NewOption, Attributes, OptionalData, OptionalDataSize); + if (!EFI_ERROR (Status)) { + BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot); + + OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount); + + if (OptionIndex == -1) { + Status = EfiBootManagerAddLoadOptionVariable (&NewOption, Position); + ASSERT_EFI_ERROR (Status); + } else { + NewOption.OptionNumber = BootOptions[OptionIndex].OptionNumber; + } + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); + } + + return NewOption.OptionNumber; +} + + +/** + Boot manager wait callback + + @param TimeoutRemain The remaingin timeout period +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_STATUS Status; + EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *TxtInEx; + EFI_KEY_DATA KeyData; + BOOLEAN PausePressed; + + // + // Pause on PAUSE key + // + Status = gBS->HandleProtocol (gST->ConsoleInHandle, &gEfiSimpleTextInputExProtocolGuid, (VOID **) &TxtInEx); + ASSERT_EFI_ERROR (Status); + + PausePressed = FALSE; + + while (TRUE) { + Status = TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData); + if (EFI_ERROR (Status)) { + break; + } + + if (KeyData.Key.ScanCode == SCAN_PAUSE) { + PausePressed = TRUE; + break; + } + } + + // + // Loop until non-PAUSE key pressed + // + while (PausePressed) { + Status = TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData); + if (!EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, "[PauseCallback] %x/%x %x/%x\n", + KeyData.Key.ScanCode, KeyData.Key.UnicodeChar, + KeyData.KeyState.KeyShiftState, KeyData.KeyState.KeyToggleState + )); + PausePressed = (BOOLEAN) (KeyData.Key.ScanCode == SCAN_PAUSE); + } + } +} + + +/** + Registers default boot option +**/ + +VOID +RegisterDefaultBootOption ( + VOID + ) +{ + UINT16 *ShellData; + UINT32 ShellDataSize; + + ShellData = NULL; + ShellDataSize = 0; + CopyMem (&gUefiShellFileGuid, PcdGetPtr (PcdShellFile), sizeof (GUID)); + RegisterFvBootOption (&gUefiShellFileGuid, (CHAR16 *) PcdGetPtr (PcdShellFileDesc), (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize); + + // + // Boot Menu + // + mBootMenuOptionNumber = RegisterFvBootOption (&mBootMenuFile, L"Boot Device List", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0); + + if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) { + DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned)); + } + + // + // Boot Manager Menu + // + mSetupOptionNumber = RegisterFvBootOption (&mUiFile, L"Enter Setup", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0); +} + +/** + Registers/Unregisters boot option hotkey + + @param OptionNumber The boot option number for the key option. + @param Key The the key input + @param Add Flag to indicate to add or remove a key +**/ +VOID +RegisterBootOptionHotkey ( + UINT16 OptionNumber, + EFI_INPUT_KEY *Key, + BOOLEAN Add + ) +{ + EFI_STATUS Status; + + if (!Add) { + // + // No enter hotkey when force to setup or there is no boot option + // + Status = EfiBootManagerDeleteKeyOptionVariable (NULL, 0, Key, NULL); + ASSERT (Status == EFI_SUCCESS || Status == EFI_NOT_FOUND); + } else { + // + // Register enter hotkey for the first boot option + // + Status = EfiBootManagerAddKeyOptionVariable (NULL, OptionNumber, 0, Key,NULL); + ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED); + } +} + + +/** + Detect key press callback + + @param The key data + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +DetectKeypressCallback ( + IN EFI_KEY_DATA *KeyData +) +{ + mHotKeypressed = TRUE; + + if (HotKeyEvent != NULL) { + gBS->SignalEvent(HotKeyEvent); + } + + return EFI_SUCCESS; +} + +/** + This function is called after all the boot options are enumerated and ordered properly. +**/ +VOID +RegisterStaticHotkey ( + VOID + ) +{ + + EFI_INPUT_KEY Enter; + EFI_KEY_DATA F2; + EFI_KEY_DATA F7; + BOOLEAN EnterSetup; + + EnterSetup = FALSE; + + // + // [Enter] + // + mContinueBoot = !EnterSetup; + if (mContinueBoot) { + Enter.ScanCode = SCAN_NULL; + Enter.UnicodeChar = CHAR_CARRIAGE_RETURN; + EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); + } + + + // + // [F2] + // + if (mSetupOptionNumber != LoadOptionNumberUnassigned) { + F2.Key.ScanCode = SCAN_F2; + F2.Key.UnicodeChar = CHAR_NULL; + F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID; + F2.KeyState.KeyToggleState = 0; + RegisterBootOptionHotkey ((UINT16) mSetupOptionNumber, &F2.Key, TRUE); + } + + // + // Register [F7] only when the mBootMenuOptionNumber is valid + // + if (mBootMenuOptionNumber != LoadOptionNumberUnassigned) { + F7.Key.ScanCode = SCAN_F7; + F7.Key.UnicodeChar = CHAR_NULL; + F7.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID; + F7.KeyState.KeyToggleState = 0; + mBootMenuBoot = !EnterSetup; + RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBootMenuBoot); + } +} + + + +/** + Returns the boot option type of a device + + @param DevicePath The path of device whose boot option type + to be returned + @retval -1 Device type not found + @retval > -1 Device type found +**/ +UINT8 +BootOptionType ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *Node; + EFI_DEVICE_PATH_PROTOCOL *NextNode; + + for (Node = DevicePath; !IsDevicePathEndType (Node); Node = NextDevicePathNode (Node)) { + if (DevicePathType (Node) == MESSAGING_DEVICE_PATH) { + // + // Make sure the device path points to the driver device. + // + NextNode = NextDevicePathNode (Node); + if (DevicePathSubType(NextNode) == MSG_DEVICE_LOGICAL_UNIT_DP) { + // + // if the next node type is Device Logical Unit, which specify the Logical Unit Number (LUN), + // skip it + // + NextNode = NextDevicePathNode (NextNode); + } + if (IsDevicePathEndType (NextNode)) { + if ((DevicePathType (Node) == MESSAGING_DEVICE_PATH)) { + return DevicePathSubType (Node); + } else { + return MSG_SATA_DP; + } + } + } + } + + return (UINT8) -1; +} + +/** + Returns the priority number. + OptionType EFI + ------------------------------------ + PXE 2 + DVD 4 + USB 6 + NVME 7 + HDD 8 + EFI Shell 9 + Others 100 + + @param BootOption +**/ +UINTN +BootOptionPriority ( + CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption + ) +{ + // + // EFI boot options + // + switch (BootOptionType (BootOption->FilePath)) { + case MSG_MAC_ADDR_DP: + case MSG_VLAN_DP: + case MSG_IPv4_DP: + case MSG_IPv6_DP: + return 2; + + case MSG_SATA_DP: + case MSG_ATAPI_DP: + case MSG_UFS_DP: + case MSG_NVME_NAMESPACE_DP: + return 4; + + case MSG_USB_DP: + return 6; + + } + if (StrCmp (BootOption->Description, (CHAR16 *) PcdGetPtr (PcdShellFileDesc)) == 0) { + if (PcdGetBool (PcdBootToShellOnly)) { + return 0; + } + return 9; + } + if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) { + return 8; + } + return 100; +} + + +/** + Returns the priority number. + + @param BootOption + @retval + OptionType EFI + ------------------------------------ + PXE 2 + DVD 4 + USB 6 + NVME 7 + HDD 8 + EFI Shell 9 + Others 100 +**/ +UINTN +PxeBootOptionPriority ( + CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption + ) +{ + // + // EFI boot options + // + switch (BootOptionType (BootOption->FilePath)) { + case MSG_MAC_ADDR_DP: + case MSG_VLAN_DP: + case MSG_IPv4_DP: + case MSG_IPv6_DP: + return 2; + + case MSG_SATA_DP: + case MSG_ATAPI_DP: + case MSG_UFS_DP: + case MSG_NVME_NAMESPACE_DP: + return 4; + + case MSG_USB_DP: + return 6; + + } + if (StrCmp (BootOption->Description, (CHAR16 *) PcdGetPtr (PcdShellFileDesc)) == 0) { + if (PcdGetBool (PcdBootToShellOnly)) { + return 0; + } + return 9; + } + if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) { + return 8; + } + return 100; +} + +/** + Returns the priority number. + + @param BootOption + @retval + OptionType EFI + ------------------------------------ + NVME, DVD, HDD 2 + PXE 4 + USB 6 + HDD 8 + EFI Shell 9 + Others 100 +**/ +UINTN +HddBootOptionPriority ( + CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption + ) +{ + // + // EFI boot options + // + switch (BootOptionType (BootOption->FilePath)) { + case MSG_SATA_DP: + case MSG_UFS_DP: + case MSG_NVME_NAMESPACE_DP: + return 2; + + case MSG_ATAPI_DP: + return 3; + + case MSG_MAC_ADDR_DP: + case MSG_VLAN_DP: + case MSG_IPv4_DP: + case MSG_IPv6_DP: + return 4; + + case MSG_USB_DP: + return 6; + + } + if (StrCmp (BootOption->Description, (CHAR16 *) PcdGetPtr (PcdShellFileDesc)) == 0) { + if (PcdGetBool (PcdBootToShellOnly)) { + return 0; + } + return 9; + } + if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) { + return 2; + } + return 100; +} + +/** + Compares boot priorities of two boot options + + @param Left The left boot option + @param Right The right boot option + + @return The difference between the Left and Right + boot options + **/ +INTN +EFIAPI +CompareBootOption ( + CONST VOID *Left, + CONST VOID *Right + ) +{ + + return BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Left) - + BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Right); +} + +/** + Compares boot priorities of two boot options, while giving PXE the highest priority + + @param Left The left boot option + @param Right The right boot option + + @return The difference between the Left and Right + boot options + **/ +INTN +EFIAPI +CompareBootOptionPxePriority ( + CONST VOID *Left, + CONST VOID *Right + ) +{ + return PxeBootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Left) - + PxeBootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Right); +} + +/** + Compares boot priorities of two boot options, while giving HDD the highest priority + + @param Left The left boot option + @param Right The right boot option + + @return The difference between the Left and Right + boot options + **/ +INTN +EFIAPI +CompareBootOptionHddPriority ( + CONST VOID *Left, + CONST VOID *Right + ) +{ + return HddBootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Left) - + HddBootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Right); +} \ No newline at end of file diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.c b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.c new file mode 100644 index 0000000000000000000000000000000000000000..cd1b5615c04323fe5c8736aad8fccd5b694a7eb2 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.c @@ -0,0 +1,78 @@ +/** @file + Source code file for Report Firmware Volume (FV) PEI module + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback +}; + +/** + Install Firmware Volume Hob's once there is main memory + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] NotifyDescriptor Notify that this module published. + @param[in] Ppi PPI that was installed. + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + ReportPostMemFv (); + + TestPointMemoryDiscoveredFvInfoFunctional (); + + return EFI_SUCCESS; +} + +/** + Platform Init before memory PEI module entry point + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to every PEIM. + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database +**/ +EFI_STATUS +EFIAPI +ReportFvEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + ReportPreMemFv (); + + /// + /// After code reorangized, memorycallback will run because the PPI is already + /// installed when code run to here, it is supposed that the InstallEfiMemory is + /// done before. + /// + Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); + + return Status; +} \ No newline at end of file diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf new file mode 100644 index 0000000000000000000000000000000000000000..518954b0a0efa2f882b4873f1038d0e50cec5d05 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf @@ -0,0 +1,37 @@ +### @file +# Component information file for the Report Firmware Volume (FV) PEI module. +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = ReportFvPei + FILE_GUID = 3FECFD95-7CB2-4A6E-8FAC-DEFD9947E35E + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + ENTRY_POINT = ReportFvEntryPoint + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + ReportFvLib + TestPointCheckLib + IoLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[Sources] + ReportFvPei.c + +[Ppis] + gEfiPeiMemoryDiscoveredPpiGuid + +[Depex] + TRUE \ No newline at end of file diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeCheckAcpiMadt.c b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeCheckAcpiMadt.c new file mode 100644 index 0000000000000000000000000000000000000000..fb7588f96a7c34e62d6a65c608412fcfcca0566a --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeCheckAcpiMadt.c @@ -0,0 +1,334 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +DumpCharArray ( + IN CHAR8 *Ch, + IN UINTN Size + ); + +VOID +DumpAcpiTableHeader ( + IN EFI_ACPI_DESCRIPTION_HEADER *Table + ); + +BOOLEAN +IsMmioExit ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN BOOLEAN CheckAllocated + ); + +typedef struct { + UINT8 Type; + UINT8 Length; +} APIC_STRUCT_HEADER; + +CHAR8 *mMadtTypeString[] = { + "APIC ", + "IO_APIC ", + "INT_SRC_OR", + "NNI_SRC ", + "APIC_NMI ", + "APIC_OR ", + "IO_SAPIC ", + "SAPIC ", + "PL_INT_SRC", + "X2APIC ", + "X2APIC_NMI", +}; + +STATIC CHAR8 mUnknownStr[11]; + +CHAR8 * +ShortNameOfMadtType( + IN UINT8 Type + ) +{ + if (Type < sizeof(mMadtTypeString) / sizeof(mMadtTypeString[0])) { + return mMadtTypeString[Type]; + } else { + AsciiSPrint(mUnknownStr, sizeof(mUnknownStr), "[%02x] ", Type); + return mUnknownStr; + } +} + +VOID +DumpAcpiMadt ( + IN EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt + ) +{ + APIC_STRUCT_HEADER *ApicStructHeader; + INTN MadtLen; + EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE *ProcessorLocalApic; + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IOApic; + EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *InterruptSourceOverride; + EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *NonMaskableInterruptSource; + EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE *LocalApicNMI; + EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *LocalApicAddressOverride; + EFI_ACPI_6_5_IO_SAPIC_STRUCTURE *IOSapic; + EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE *ProcessorLocalSapic; + EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE *PlatformInterruptSource; + EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE *ProcessorLocalX2Apic; + EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE *LocalX2ApicNmi; + + DumpAcpiTableHeader (&Madt->Header); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " LocalApicAddress=0x%08x\n", Madt->LocalApicAddress)); + + // + // Sub table + // + MadtLen = Madt->Header.Length - sizeof(EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); + ApicStructHeader = (APIC_STRUCT_HEADER *)(Madt + 1); + while (MadtLen > 0) { + switch (ApicStructHeader->Type) { + case EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC: + ProcessorLocalApic = (EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " ID=0x%02x", ProcessorLocalApic->AcpiProcessorUid)); + DEBUG ((DEBUG_INFO, " ApicId=0x%02x", ProcessorLocalApic->ApicId)); + if ((ProcessorLocalApic->Flags & EFI_ACPI_6_5_LOCAL_APIC_ENABLED) != 0) { + DEBUG ((DEBUG_INFO, " (Enabled)")); + } + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_IO_APIC: + IOApic = (EFI_ACPI_6_5_IO_APIC_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " IoApicId=0x%02x", IOApic->IoApicId)); + DEBUG ((DEBUG_INFO, " Address=0x%08x", IOApic->IoApicAddress)); + DEBUG ((DEBUG_INFO, " InterruptBase=0x%08x", IOApic->GlobalSystemInterruptBase)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE: + InterruptSourceOverride = (EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " Bus=0x%02x", InterruptSourceOverride->Bus)); + DEBUG ((DEBUG_INFO, " Source=0x%02x", InterruptSourceOverride->Source)); + DEBUG ((DEBUG_INFO, " Interrupt=0x%08x", InterruptSourceOverride->GlobalSystemInterrupt)); + DEBUG ((DEBUG_INFO, " Flags=0x%04x", InterruptSourceOverride->Flags)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE: + NonMaskableInterruptSource = (EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " Interrupt=0x%08x", NonMaskableInterruptSource->GlobalSystemInterrupt)); + DEBUG ((DEBUG_INFO, " Flags=0x%04x", NonMaskableInterruptSource->Flags)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_LOCAL_APIC_NMI: + LocalApicNMI = (EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " ID=0x%02x", LocalApicNMI->AcpiProcessorUid)); + DEBUG ((DEBUG_INFO, " Lint=0x%02x", LocalApicNMI->LocalApicLint)); + DEBUG ((DEBUG_INFO, " Flags=0x%04x", LocalApicNMI->Flags)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE: + LocalApicAddressOverride = (EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " LocalApicAddress=0x%016lx", LocalApicAddressOverride->LocalApicAddress)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_IO_SAPIC: + IOSapic = (EFI_ACPI_6_5_IO_SAPIC_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " IoApicId=0x%02x", IOSapic->IoApicId)); + DEBUG ((DEBUG_INFO, " InterruptBase=0x%08x", IOSapic->GlobalSystemInterruptBase)); + DEBUG ((DEBUG_INFO, " IoSapicAddress=0x%016lx", IOSapic->IoSapicAddress)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_LOCAL_SAPIC: + ProcessorLocalSapic = (EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " ID=0x%02x", ProcessorLocalSapic->AcpiProcessorId)); + DEBUG ((DEBUG_INFO, " LocalSapicId=0x%02x", ProcessorLocalSapic->LocalSapicId)); + DEBUG ((DEBUG_INFO, " LocalSapicEid=0x%02x", ProcessorLocalSapic->LocalSapicEid)); + DEBUG ((DEBUG_INFO, " UID=0x%08x", ProcessorLocalSapic->ACPIProcessorUIDValue)); + if ((ProcessorLocalSapic->Flags & EFI_ACPI_6_5_LOCAL_APIC_ENABLED) != 0) { + DEBUG ((DEBUG_INFO, " (Enabled)")); + } + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES: + PlatformInterruptSource = (EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " Type=0x%02x", PlatformInterruptSource->InterruptType)); + DEBUG ((DEBUG_INFO, " ID=0x%02x", PlatformInterruptSource->ProcessorId)); + DEBUG ((DEBUG_INFO, " EID=0x%02x", PlatformInterruptSource->ProcessorEid)); + DEBUG ((DEBUG_INFO, " IoSapicVector=0x%02x", PlatformInterruptSource->IoSapicVector)); + DEBUG ((DEBUG_INFO, " Interrupt=0x%08x", PlatformInterruptSource->GlobalSystemInterrupt)); + DEBUG ((DEBUG_INFO, " SourceFlags=0x%08x", PlatformInterruptSource->PlatformInterruptSourceFlags)); + DEBUG ((DEBUG_INFO, " Flags=0x%04x", PlatformInterruptSource->Flags)); + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC: + ProcessorLocalX2Apic = (EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " X2ApicId=0x%08x", ProcessorLocalX2Apic->X2ApicId)); + DEBUG ((DEBUG_INFO, " UID=0x%08x", ProcessorLocalX2Apic->AcpiProcessorUid)); + if ((ProcessorLocalX2Apic->Flags & EFI_ACPI_6_5_LOCAL_APIC_ENABLED) != 0) { + DEBUG ((DEBUG_INFO, " (Enabled)")); + } + DEBUG ((DEBUG_INFO, "\n")); + break; + case EFI_ACPI_6_5_LOCAL_X2APIC_NMI: + LocalX2ApicNmi = (EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE *) ApicStructHeader; + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, ": [0x%02x]", ApicStructHeader->Type)); + DEBUG ((DEBUG_INFO, " UID=0x%08x", LocalX2ApicNmi->AcpiProcessorUid)); + DEBUG ((DEBUG_INFO, " Lint=0x%02x", LocalX2ApicNmi->LocalX2ApicLint)); + DEBUG ((DEBUG_INFO, " Flags=0x%04x", LocalX2ApicNmi->Flags)); + DEBUG ((DEBUG_INFO, "\n")); + break; + default: + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, " ")); + DEBUG ((DEBUG_INFO, ShortNameOfMadtType(ApicStructHeader->Type))); + DEBUG ((DEBUG_INFO, "\n")); + break; + } + // Update MadtLen first to avoid the dead loop and system hang + MadtLen -= ApicStructHeader->Length; + ApicStructHeader = (APIC_STRUCT_HEADER *)((UINT8 *)ApicStructHeader + ApicStructHeader->Length); + } +} + +EFI_STATUS +CheckAcpiMadt ( + IN EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt + ) +{ + + APIC_STRUCT_HEADER *ApicStructHeader; + INTN MadtLen; + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IOApic; + EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *LocalApicAddressOverride; + EFI_ACPI_6_5_IO_SAPIC_STRUCTURE *IOSapic; +#if 0 + EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE *ProcessorLocalApic; + EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *InterruptSourceOverride; + EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *NonMaskableInterruptSource; + EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE *LocalApicNMI; + EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE *ProcessorLocalSapic; + EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE *PlatformInterruptSource; + EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE *ProcessorLocalX2Apic; + EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE *LocalX2ApicNmi; +#endif + + if (!IsMmioExit (Madt->LocalApicAddress, SIZE_4KB, TRUE)) { + DEBUG ((DEBUG_ERROR, "MADT resource (0x%x) is not reported correctly.\n", Madt->LocalApicAddress)); + return EFI_NOT_STARTED; + } + + // + // Sub table + // + MadtLen = Madt->Header.Length - sizeof(EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); + ApicStructHeader = (APIC_STRUCT_HEADER *)(Madt + 1); + while (MadtLen > 0) { + switch (ApicStructHeader->Type) { + case EFI_ACPI_6_5_IO_APIC: + IOApic = (EFI_ACPI_6_5_IO_APIC_STRUCTURE *) ApicStructHeader; + if (!IsMmioExit (IOApic->IoApicAddress, SIZE_4KB, TRUE)) { + DEBUG ((DEBUG_ERROR, "MADT.IOAPIC resource (0x%x) is not reported correctly.\n", IOApic->IoApicAddress)); + return EFI_NOT_STARTED; + } + break; + case EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE: + LocalApicAddressOverride = (EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *) ApicStructHeader; + if (!IsMmioExit (LocalApicAddressOverride->LocalApicAddress, SIZE_4KB, TRUE)) { + DEBUG ((DEBUG_ERROR, "MADT.LocalApicOverride resource (0x%x) is not reported correctly.\n", LocalApicAddressOverride->LocalApicAddress)); + return EFI_NOT_STARTED; + } + break; + case EFI_ACPI_6_5_IO_SAPIC: + IOSapic = (EFI_ACPI_6_5_IO_SAPIC_STRUCTURE *) ApicStructHeader; + if (!IsMmioExit (IOSapic->IoSapicAddress, SIZE_4KB, TRUE)) { + DEBUG ((DEBUG_ERROR, "MADT.IOSAPIC resource (0x%x) is not reported correctly.\n", IOSapic->IoSapicAddress)); + return EFI_NOT_STARTED; + } + break; +#if 0 + case EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC: + ProcessorLocalApic = (EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE: + InterruptSourceOverride = (EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE: + NonMaskableInterruptSource = (EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_LOCAL_APIC_NMI: + LocalApicNMI = (EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_LOCAL_SAPIC: + ProcessorLocalSapic = (EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES: + PlatformInterruptSource = (EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC: + ProcessorLocalX2Apic = (EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE *) ApicStructHeader; + break; + case EFI_ACPI_6_5_LOCAL_X2APIC_NMI: + LocalX2ApicNmi = (EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE *) ApicStructHeader; + break; +#endif + default: + break; + } + // Update MadtLen first to avoid the dead loop and system hang + MadtLen -= ApicStructHeader->Length; + ApicStructHeader = (APIC_STRUCT_HEADER *)((UINT8 *)ApicStructHeader + ApicStructHeader->Length); + } + return EFI_SUCCESS; +} \ No newline at end of file diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c new file mode 100644 index 0000000000000000000000000000000000000000..1646b48aa2043118a54820067aa5088f225d1bb0 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c @@ -0,0 +1,1320 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** @file +Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "TestPointInternal.h" + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GUID mTestPointSmmCommunciationGuid = TEST_POINT_SMM_COMMUNICATION_GUID; + +VOID +TestPointDumpGcd ( + OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR **GcdMemoryMap, OPTIONAL + OUT UINTN *GcdMemoryMapNumberOfDescriptors, OPTIONAL + OUT EFI_GCD_IO_SPACE_DESCRIPTOR **GcdIoMap, OPTIONAL + OUT UINTN *GcdIoMapNumberOfDescriptors, OPTIONAL + IN BOOLEAN DumpPrint + ); + +VOID +TestPointDumpUefiMemoryMap ( + OUT EFI_MEMORY_DESCRIPTOR **UefiMemoryMap, OPTIONAL + OUT UINTN *UefiMemoryMapSize, OPTIONAL + OUT UINTN *UefiDescriptorSize, OPTIONAL + IN BOOLEAN DumpPrint + ); + +EFI_STATUS +TestPointCheckUefiMemoryMap ( + VOID + ); + +EFI_STATUS +TestPointCheckUefiMemAttribute ( + VOID + ); + +EFI_STATUS +TestPointCheckPciResource ( + VOID + ); + +EFI_STATUS +TestPointCheckConsoleVariable ( + VOID + ); + +EFI_STATUS +TestPointCheckBootVariable ( + VOID + ); + +VOID +TestPointDumpDevicePath ( + VOID + ); + +EFI_STATUS +TestPointCheckMemoryTypeInformation ( + VOID + ); + +EFI_STATUS +TestPointCheckAcpi ( + VOID + ); + +EFI_STATUS +TestPointCheckAcpiGcdResource ( + VOID + ); + +EFI_STATUS +TestPointCheckHsti ( + VOID + ); + +VOID +TestPointDumpVariable ( + VOID + ); + +EFI_STATUS +TestPointCheckEsrt ( + VOID + ); + +EFI_STATUS +TestPointCheckSmmInfo ( + VOID + ); + +EFI_STATUS +TestPointCheckPciBusMaster ( + VOID + ); + +EFI_STATUS +TestPointCheckLoadedImage ( + VOID + ); + +EFI_STATUS +EFIAPI +TestPointCheckSmiHandlerInstrument ( + VOID + ); + +EFI_STATUS +TestPointCheckUefiSecureBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckPiSignedFvBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckTcgTrustedBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckTcgMor ( + VOID + ); + +EFI_STATUS +TestPointVtdEngine ( + VOID + ); + +VOID * +TestPointGetAcpi ( + IN UINT32 Signature + ); + +GLOBAL_REMOVE_IF_UNREFERENCED ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT mTestPointStruct = { + PLATFORM_TEST_POINT_VERSION, + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + {TEST_POINT_IMPLEMENTATION_ID_PLATFORM_DXE}, + TEST_POINT_FEATURE_SIZE, + {0}, // FeaturesImplemented + {0}, // FeaturesVerified + 0, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFeatureImplemented[TEST_POINT_FEATURE_SIZE]; + +/** + This service verifies bus master enable (BME) is disabled after PCI enumeration. + + Test subject: PCI device BME. + Test overview: Verify BME is cleared. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps results to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointPciEnumerationDonePciBusMasterDisabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciBusMasterDisabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPciBusMaster (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciBusMasterDisabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies PCI device resource assignment after PCI enumeration. + + Test subject: PCI device resources. + Test overview: Verify all PCI devices have been assigned proper resources. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps PCI resource assignments to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointPciEnumerationDonePciResourceAllocated ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciResourceAllocated - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPciResource (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciResourceAllocated - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the DMA ACPI table is reported at the end of DXE. + + Test subject: DMA protection. + Test overview: DMA ACPI table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the DMA ACPI table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeDmaAcpiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Acpi; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaAcpiTableFunctional - Enter\n")); + + Acpi = TestPointGetAcpi (EFI_ACPI_6_5_DMA_REMAPPING_TABLE_SIGNATURE); + if (Acpi == NULL) { + DEBUG ((DEBUG_ERROR, "No DMAR table\n")); + TestPointLibAppendErrorString ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL_ERROR_CODE \ + TEST_POINT_END_OF_DXE \ + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL_ERROR_STRING + ); + Status = EFI_INVALID_PARAMETER; + } else { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL + ); + Status = EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaAcpiTableFunctional - Exit\n")); + return Status; +} + +/** + This service verifies DMA protection configuration at the end of DXE. + + Test subject: DMA protection. + Test overview: DMA protection in DXE. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the DMA ACPI table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeDmaProtectionEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_DMA_PROTECTION_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaProtectionEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointVtdEngine (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_DMA_PROTECTION_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaProtectionEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies no 3rd party PCI option ROMs (OPROMs) were dispatched prior to the end of DXE. + + Test subject: 3rd party OPROMs. + Test overview: Verify no 3rd party PCI OPROMs were . + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps PCI resource assignments to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeNoThirdPartyPciOptionRom ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeNoThirdPartyPciOptionRom - Enter\n")); + + Result = TRUE; + Status = TestPointCheckLoadedImage (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeNoThirdPartyPciOptionRom - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of System Management RAM (SMRAM) alignment at SMM Ready To Lock. + + Test subject: SMRAM Information. + Test overview: SMRAM is aligned. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SMRAM region table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToLockSmramAligned ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockSmramAligned - Enter\n")); + + Result = TRUE; + Status = TestPointCheckSmmInfo (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockSmramAligned - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the Windows SMM Security Mitigation Table (WSMT) at SMM Ready To Lock. + + Test subject: Windows Security SMM Mitigation Table. + Test overview: The table is reported in compliance with the Windows SMM Security Mitigations Table + ACPI table specification. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the WSMT to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToLockWsmtTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Acpi; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockWsmtTableFunctional - Enter\n")); + + Acpi = TestPointGetAcpi (EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE); + if (Acpi == NULL) { + DEBUG ((DEBUG_ERROR, "No WSMT table\n")); + TestPointLibAppendErrorString ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_CODE \ + TEST_POINT_DXE_SMM_READY_TO_LOCK \ + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_STRING + ); + Status = EFI_INVALID_PARAMETER; + } else { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL + ); + Status = EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockWsmtTableFunctional - Exit\n")); + return Status; +} + +/** + This service verifies the validity of the SMM page table at Ready To Boot. + + Test subject: SMM page table. + Test overview: The SMM page table settings matches the SmmMemoryAttribute table. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Reports an error if verification fails. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToBootSmmPageProtection ( + VOID + ) +{ + EFI_MEMORY_DESCRIPTOR *UefiMemoryMap; + UINTN UefiMemoryMapSize; + UINTN UefiDescriptorSize; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMap; + EFI_GCD_IO_SPACE_DESCRIPTOR *GcdIoMap; + UINTN GcdMemoryMapNumberOfDescriptors; + UINTN GcdIoMapNumberOfDescriptors; + EFI_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable; + UINTN MemoryAttributesTableSize; + EFI_STATUS Status; + UINTN CommSize; + UINT64 LongCommSize; + UINT8 *CommBuffer; + EFI_SMM_COMMUNICATE_HEADER *CommHeader; + EFI_SMM_COMMUNICATION_PROTOCOL *SmmCommunication; + UINTN MinimalSizeNeeded; + EDKII_PI_SMM_COMMUNICATION_REGION_TABLE *PiSmmCommunicationRegionTable; + UINT32 Index; + EFI_MEMORY_DESCRIPTOR *Entry; + UINTN Size; + TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO *CommData; + + if ((mFeatureImplemented[6] & TEST_POINT_BYTE6_SMM_READY_TO_BOOT_SMM_PAGE_LEVEL_PROTECTION) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmmPageProtection - Enter\n")); + + TestPointDumpUefiMemoryMap (&UefiMemoryMap, &UefiMemoryMapSize, &UefiDescriptorSize, FALSE); + TestPointDumpGcd (&GcdMemoryMap, &GcdMemoryMapNumberOfDescriptors, &GcdIoMap, &GcdIoMapNumberOfDescriptors, FALSE); + + MemoryAttributesTable = NULL; + MemoryAttributesTableSize = 0; + Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); + if (!EFI_ERROR (Status)) { + MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries; + } + + Status = gBS->LocateProtocol(&gEfiSmmCommunicationProtocolGuid, NULL, (VOID **)&SmmCommunication); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: Locate SmmCommunication protocol - %r\n", Status)); + return EFI_SUCCESS; + } + + MinimalSizeNeeded = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) + + sizeof(TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO) + + UefiMemoryMapSize + + GcdMemoryMapNumberOfDescriptors * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR) + + GcdIoMapNumberOfDescriptors * sizeof(EFI_GCD_IO_SPACE_DESCRIPTOR) + + MemoryAttributesTableSize; + + Status = EfiGetSystemConfigurationTable( + &gEdkiiPiSmmCommunicationRegionTableGuid, + (VOID **)&PiSmmCommunicationRegionTable + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: Get PiSmmCommunicationRegionTable - %r\n", Status)); + return EFI_SUCCESS; + } + ASSERT(PiSmmCommunicationRegionTable != NULL); + Entry = (EFI_MEMORY_DESCRIPTOR *)(PiSmmCommunicationRegionTable + 1); + Size = 0; + for (Index = 0; Index < PiSmmCommunicationRegionTable->NumberOfEntries; Index++) { + if (Entry->Type == EfiConventionalMemory) { + Size = EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages); + if (Size >= MinimalSizeNeeded) { + break; + } + } + Entry = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)Entry + PiSmmCommunicationRegionTable->DescriptorSize); + } + // EDKII_BIOS_OVERRIDE START + // WA, REVISIT disable the assert + // ASSERT(Index < PiSmmCommunicationRegionTable->NumberOfEntries); + // EDKII_BIOS_OVERRIDE END + + CommBuffer = (UINT8 *)(UINTN)Entry->PhysicalStart; + + CommHeader = (EFI_SMM_COMMUNICATE_HEADER *)&CommBuffer[0]; + CopyMem(&CommHeader->HeaderGuid, &mTestPointSmmCommunciationGuid, sizeof(mTestPointSmmCommunciationGuid)); + CommHeader->MessageLength = MinimalSizeNeeded - OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data); + + CommData = (TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO *)&CommBuffer[OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data)]; + CommData->Header.Version = TEST_POINT_SMM_COMMUNICATION_VERSION; + CommData->Header.FuncId = TEST_POINT_SMM_COMMUNICATION_FUNC_ID_UEFI_GCD_MAP_INFO; + CommData->Header.Size = CommHeader->MessageLength; + CommData->UefiMemoryMapOffset = sizeof(TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO); + CommData->UefiMemoryMapSize = UefiMemoryMapSize; + CommData->GcdMemoryMapOffset = CommData->UefiMemoryMapOffset + CommData->UefiMemoryMapSize; + CommData->GcdMemoryMapSize = GcdMemoryMapNumberOfDescriptors * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR); + CommData->GcdIoMapOffset = CommData->GcdMemoryMapOffset + CommData->GcdMemoryMapSize; + CommData->GcdIoMapSize = GcdIoMapNumberOfDescriptors * sizeof(EFI_GCD_IO_SPACE_DESCRIPTOR); + CommData->UefiMemoryAttributeTableOffset = CommData->GcdIoMapOffset + CommData->GcdIoMapSize; + CommData->UefiMemoryAttributeTableSize = MemoryAttributesTableSize; + + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->UefiMemoryMapOffset), + UefiMemoryMap, + (UINTN)CommData->UefiMemoryMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->GcdMemoryMapOffset), + GcdMemoryMap, + (UINTN)CommData->GcdMemoryMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->GcdIoMapOffset), + GcdIoMap, + (UINTN)CommData->GcdIoMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->UefiMemoryAttributeTableOffset), + MemoryAttributesTable, + (UINTN)CommData->UefiMemoryAttributeTableSize + ); + + Status = SafeUint64Add (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, Data), CommHeader->MessageLength, &LongCommSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: LongCommSize calculation - %r\n", Status)); + return EFI_SUCCESS; + } + + Status = SafeUint64ToUintn (LongCommSize, &CommSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: CommSize conversion - %r\n", Status)); + return EFI_SUCCESS; + } + + Status = SmmCommunication->Communicate(SmmCommunication, CommBuffer, &CommSize); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: SmmCommunication - %r\n", Status)); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmmPageProtection - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies SMI handler profiling. + + Test subject: SMI handler profiling. + Test overview: + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SMI handler profile. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToBootSmiHandlerInstrument ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmiHandlerInstrument - Enter\n")); + + Result = TRUE; + Status = TestPointCheckSmiHandlerInstrument (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmiHandlerInstrument - Exit\n")); + return EFI_SUCCESS; +} + +/** + This services verifies the validity of installed ACPI tables at Ready To Boot. + + Test subject: ACPI tables. + Test overview: The ACPI table settings are valid. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the installed ACPI tables. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootAcpiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootAcpiTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckAcpi (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootAcpiTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This services verifies ACPI table resources are in the GCD. + + Test subject: ACPI memory resources. + Test overview: Memory resources are in both ACPI and GCD. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the installed ACPI tables and GCD. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootGcdResourceFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_GCD_RESOURCE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootGcdResourceFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckAcpiGcdResource (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_GCD_RESOURCE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootGcdResourceFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the memory type information settings. + + Test subject: Memory type information. + Test overview: Inspect an verify memory type information is correct. + Confirm no fragmentation exists in the ACPI/Reserved/Runtime regions. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the memory type information settings to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootMemoryTypeInformationFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootMemoryTypeInformationFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckMemoryTypeInformation (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + TestPointDumpUefiMemoryMap (NULL, NULL, NULL, TRUE); + Status = TestPointCheckUefiMemoryMap (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootMemoryTypeInformationFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the memory type information settings. + + Test subject: Memory type information. + Test overview: Inspect an verify memory type information is correct. + Confirm no fragmentation exists in the ACPI/Reserved/Runtime regions. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the memory type information settings to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiMemoryAttributeTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiMemoryAttributeTableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpUefiMemoryMap (NULL, NULL, NULL, TRUE); + TestPointDumpGcd (NULL, NULL, NULL, NULL, TRUE); + Status = TestPointCheckUefiMemAttribute (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiMemoryAttributeTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the UEFI memory attribute table. + + Test subject: UEFI memory attribute table. + Test overview: The UEFI memeory attribute table is reported. The image code/data is consistent with the table. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the UEFI image information and the UEFI memory attribute table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiBootVariableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiBootVariableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpDevicePath (); + TestPointDumpVariable (); + Status = TestPointCheckBootVariable (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiBootVariableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the consle variable information. + + Test subject: Console. + Test overview: Inspect and verify the console variable information is correct. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the console variable information. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiConsoleVariableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiConsoleVariableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpDevicePath (); + TestPointDumpVariable (); + Status = TestPointCheckConsoleVariable (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiConsoleVariableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the HSTI table. + + Test subject: HSTI table. + Test overview: Verify the HSTI table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the HSTI table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootHstiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[8] & TEST_POINT_BYTE8_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootHstiTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckHsti (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 8, + TEST_POINT_BYTE8_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootHstiTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the ESRT table. + + Test subject: ESRT table. + Test overview: Verify the ESRT table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the ESRT table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootEsrtTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[8] & TEST_POINT_BYTE8_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootEsrtTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckEsrt (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 8, + TEST_POINT_BYTE8_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootEsrtTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies UEFI Secure Boot is enabled. + + Test subject: UEFI Secure Boot. + Test overview: Verify the SecureBoot variable is set. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SecureBoot variable. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiSecureBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiSecureBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckUefiSecureBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiSecureBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies Platform Initialization (PI) Signed FV Boot is enabled. + + Test subject: PI Signed FV Boot. + Test overview: Verify PI signed FV boot is enabled. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootPiSignedFvBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootPiSignedFvBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPiSignedFvBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootPiSignedFvBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies TCG Trusted Boot is enabled. + + Test subject: TCG Trusted Boot. + Test overview: Verify the TCG protocol is installed. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the TCG protocol capability. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootTcgTrustedBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgTrustedBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckTcgTrustedBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgTrustedBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies TCG Memory Overwrite Request (MOR) is enabled. + + Test subject: TCG MOR. + Test overview: Verify the MOR UEFI variable is set. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the MOR UEFI variable. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootTcgMorEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_TCG_MOR_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgMorEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckTcgMor (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_TCG_MOR_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgMorEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the system state after Exit Boot Services is invoked. + + @retval EFI_SUCCESS The test point check was performed successfully. +**/ +EFI_STATUS +EFIAPI +TestPointExitBootServices ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "======== TestPointExitBootServices - Enter\n")); + + DEBUG ((DEBUG_INFO, "======== TestPointExitBootServices - Exit\n")); + + return EFI_SUCCESS; +} + +/** + Initialize feature data. + + @param[in] Role The test point role being requested. +**/ +VOID +InitData ( + IN UINT32 Role + ) +{ + EFI_STATUS Status; + + ASSERT (PcdGetSize(PcdTestPointIbvPlatformFeature) == sizeof(mFeatureImplemented)); + CopyMem (mFeatureImplemented, PcdGetPtr(PcdTestPointIbvPlatformFeature), sizeof(mFeatureImplemented)); + + mTestPointStruct.Role = Role; + CopyMem (mTestPointStruct.FeaturesImplemented, mFeatureImplemented, sizeof(mFeatureImplemented)); + Status = TestPointLibSetTable ( + &mTestPointStruct, + sizeof(mTestPointStruct) + ); + if (EFI_ERROR (Status)) { + if (Status != EFI_ALREADY_STARTED) { + ASSERT_EFI_ERROR (Status); + } + } +} + +/** + The library constructor. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +DxeTestPointCheckLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + InitData (PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/Platform/AMD/TurinBoard/Override/edk2/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h new file mode 100644 index 0000000000000000000000000000000000000000..d3ac293ba612b0ee44719fa53bf24f87baa9692c --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h @@ -0,0 +1,1940 @@ +/** @file + AML Lib. + + Copyright (c) 2019 - 2023, Arm Limited. All rights reserved.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef AML_LIB_H_ +#define AML_LIB_H_ + +/** + @mainpage Dynamic AML Generation + @{ + @par Summary + @{ + ACPI tables are categorized as data tables and definition block + tables. Dynamic Tables Framework currently supports generation of ACPI + data tables. Generation of definition block tables is difficult as these + tables are encoded in ACPI Machine Language (AML), which has a complex + grammar. + + Dynamic AML Generation is an extension to the Dynamic tables Framework. + One of the techniques used to simplify definition block generation is to + fixup a template SSDT table. + + Dynamic AML aims to provide a framework that allows fixing up of an ACPI + SSDT template with appropriate information about the hardware. + + This framework consists of an: + - AMLLib core that implements a rich set of interfaces to parse, traverse + and update AML data. + - AMLLib library APIs that provides interfaces to search and updates nodes + in the AML namespace. + @} + @} +*/ + +#include +#include + +#ifndef AML_HANDLE + +/** Node handle. +*/ +typedef void *AML_NODE_HANDLE; + +/** Root Node handle. +*/ +typedef void *AML_ROOT_NODE_HANDLE; + +/** Object Node handle. +*/ +typedef void *AML_OBJECT_NODE_HANDLE; + +/** Data Node handle. +*/ +typedef void *AML_DATA_NODE_HANDLE; + +#endif // AML_HANDLE + +/** Memory attributes, _MEM (2 bits) + + Possible values are: + 0-The memory is non-cacheable + 1-The memory is cacheable (DEPRECATED) + 2-The memory is cacheable and supports + write combining (DEPRECATED) + 3-The memory is cacheable and prefetchable + + @par Reference(s): + - ACPI 6.5, s6.4.3.5.5 "Resource Type Specific Flags" + +**/ +typedef enum { + AmlMemoryNonCacheable = 0, + AmlMemoryCacheable = 1, + AmlMemoryCacheableWriteCombine = 2, + AmlMemoryCacheablePrefetch = 3, + AmlMemoryCacheablityMax = 4 +} AML_MEMORY_ATTRIBUTES_MEM; + +/** Memory attributes, _MTP (2 bits) + + Possible values are: + 0-AddressRangeMemory + 1-AddressRangeReserved + 2-AddressRangeACPI + 3-AddressRangeNVS + + @par Reference(s): + - ACPI 6.5, s6.4.3.5.5 "Resource Type Specific Flags" + +**/ +typedef enum { + AmlAddressRangeMemory = 0, + AmlAddressRangeReserved = 1, + AmlAddressRangeACPI = 2, + AmlAddressRangeNVS = 3, + AmlAddressRangeMax = 4 +} AML_MEMORY_ATTRIBUTES_MTP; + +/** Method parameter types + + Possible values are: + 0 - AmlMethodParamTypeInteger + 1 - AmlMethodParamTypeString + 2 - AmlMethodParamTypeArg + 3 - AmlMethodParamTypeLocal + + @par Reference(s) + - ACPI 6.5, s20.2.5 "Term Objects Encoding" + +**/ +typedef enum { + AmlMethodParamTypeInteger = 0, + AmlMethodParamTypeString = 1, + AmlMethodParamTypeArg = 2, + AmlMethodParamTypeLocal = 3 +} AML_METHOD_PARAM_TYPE; + +/** AML Method parameter data + holds the AML method parameter data. +**/ +typedef union { + UINT8 Arg; + UINT8 Local; + UINT64 Integer; + VOID *Buffer; +} AML_METHOD_PARAM_DATA; + +/** structure to hold AML method parameter types + Type - Type of parameter + Data - holds data of parameter + if Type is AmlMethodParamTypeInteger + then Data is of type Integer to hold integer value. + if Type is AmlMethodParamTypeString + then Data contains null terminated string. + If Type is AmlMethodParamTypeArg + then Data contains the Argument number, + 0 to 6 are supported value. + If Type is AmlMethodParamTypeLocal + then Data contains the Local variable number, + 0 to 7 are supported value. + DataSize - for future use +**/ +typedef struct { + AML_METHOD_PARAM_TYPE Type; + AML_METHOD_PARAM_DATA Data; + UINTN DataSize; +} AML_METHOD_PARAM; + +/** Parse the definition block. + + The function parses the whole AML blob. It starts with the ACPI DSDT/SSDT + header and then parses the AML bytestream. + A tree structure is returned via the RootPtr. + The tree must be deleted with the AmlDeleteTree function. + + @ingroup UserApis + + @param [in] DefinitionBlock Pointer to the definition block. + @param [out] RootPtr Pointer to the root node of the AML tree. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_BUFFER_TOO_SMALL No space left in the buffer. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlParseDefinitionBlock ( + IN CONST EFI_ACPI_DESCRIPTION_HEADER *DefinitionBlock, + OUT AML_ROOT_NODE_HANDLE *RootPtr + ); + +/** Serialize an AML definition block. + + This functions allocates memory with the "AllocateZeroPool ()" + function. This memory is used to serialize the AML tree and is + returned in the Table. + + @ingroup UserApis + + @param [in] RootNode Root node of the tree. + @param [out] Table On return, hold the serialized + definition block. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlSerializeDefinitionBlock ( + IN AML_ROOT_NODE_HANDLE RootNode, + OUT EFI_ACPI_DESCRIPTION_HEADER **Table + ); + +/** Clone a node and its children (clone a tree branch). + + The cloned branch returned is not attached to any tree. + + @ingroup UserApis + + @param [in] Node Pointer to a node. + Node is the head of the branch to clone. + @param [out] ClonedNode Pointer holding the head of the created cloned + branch. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCloneTree ( + IN AML_NODE_HANDLE Node, + OUT AML_NODE_HANDLE *ClonedNode + ); + +/** Delete a Node and its children. + + The Node must be removed from the tree first, + or must be the root node. + + @ingroup UserApis + + @param [in] Node Pointer to the node to delete. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlDeleteTree ( + IN AML_NODE_HANDLE Node + ); + +/** Detach the Node from the tree. + + The function will fail if the Node is in its parent's fixed + argument list. + The Node is not deleted. The deletion is done separately + from the removal. + + @ingroup UserApis + + @param [in] Node Pointer to a Node. + Must be a data node or an object node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlDetachNode ( + IN AML_NODE_HANDLE Node + ); + +/** Attach a node in an AML tree. + + The node will be added as the last statement of the ParentNode. + E.g.: + ASL code corresponding to NewNode: + Name (_UID, 0) + + ASL code corresponding to ParentNode: + Device (PCI0) { + Name(_HID, EISAID("PNP0A08")) + } + + "AmlAttachNode (ParentNode, NewNode)" will result in: + ASL code: + Device (PCI0) { + Name(_HID, EISAID("PNP0A08")) + Name (_UID, 0) + } + + @param [in] ParentNode Pointer to the parent node. + Must be a root or an object node. + @param [in] NewNode Pointer to the node to add. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlAttachNode ( + IN AML_NODE_HANDLE ParentNode, + IN AML_NODE_HANDLE NewNode + ); + +/** Find a node in the AML namespace, given an ASL path and a reference Node. + + - The AslPath can be an absolute path, or a relative path from the + reference Node; + - Node must be a root node or a namespace node; + - A root node is expected to be at the top of the tree. + + E.g.: + For the following AML namespace, with the ReferenceNode being the node with + the name "AAAA": + - the node with the name "BBBB" can be found by looking for the ASL + path "BBBB"; + - the root node can be found by looking for the ASL relative path "^", + or the absolute path "\\". + + AML namespace: + \ + \-AAAA <- ReferenceNode + \-BBBB + + @ingroup NameSpaceApis + + @param [in] ReferenceNode Reference node. + If a relative path is given, the + search is done from this node. If + an absolute path is given, the + search is done from the root node. + Must be a root node or an object + node which is part of the + namespace. + @param [in] AslPath ASL path to the searched node in + the namespace. An ASL path name is + NULL terminated. Can be a relative + or absolute path. + E.g.: "\\_SB.CLU0.CPU0" or "^CPU0" + @param [out] OutNode Pointer to the found node. + Contains NULL if not found. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_BUFFER_TOO_SMALL No space left in the buffer. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Out of memory. +**/ +EFI_STATUS +EFIAPI +AmlFindNode ( + IN AML_NODE_HANDLE ReferenceNode, + IN CHAR8 *AslPath, + OUT AML_NODE_HANDLE *OutNode + ); + +/** + @defgroup UserApis User APIs + @{ + User APIs are implemented to ease most common actions that might be done + using the AmlLib. They allow to find specific objects like "_UID" or + "_CRS" and to update their value. It also shows what can be done using + AmlLib functions. + @} +*/ + +/** Update the name of a DeviceOp object node. + + @ingroup UserApis + + @param [in] DeviceOpNode Object node representing a Device. + Must have an OpCode=AML_NAME_OP, SubOpCode=0. + OpCode/SubOpCode. + DeviceOp object nodes are defined in ASL + using the "Device ()" function. + @param [in] NewNameString The new Device's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlDeviceOpUpdateName ( + IN AML_OBJECT_NODE_HANDLE DeviceOpNode, + IN CHAR8 *NewNameString + ); + +/** Update an integer value defined by a NameOp object node. + + For compatibility reasons, the NameOpNode must initially + contain an integer. + + @ingroup UserApis + + @param [in] NameOpNode NameOp object node. + Must have an OpCode=AML_NAME_OP, SubOpCode=0. + NameOp object nodes are defined in ASL + using the "Name ()" function. + @param [in] NewInt New Integer value to assign. + Must be a UINT64. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlNameOpUpdateInteger ( + IN AML_OBJECT_NODE_HANDLE NameOpNode, + IN UINT64 NewInt + ); + +/** Update a string value defined by a NameOp object node. + + The NameOpNode must initially contain a string. + The EISAID ASL macro converts a string to an integer. This, it is + not accepted. + + @ingroup UserApis + + @param [in] NameOpNode NameOp object node. + Must have an OpCode=AML_NAME_OP, SubOpCode=0. + NameOp object nodes are defined in ASL + using the "Name ()" function. + @param [in] NewName New NULL terminated string to assign to + the NameOpNode. + The input string is copied. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlNameOpUpdateString ( + IN AML_OBJECT_NODE_HANDLE NameOpNode, + IN CONST CHAR8 *NewName + ); + +/** Get the first Resource Data element contained in a named object. + + In the following ASL code, the function will return the Resource Data + node corresponding to the "QWordMemory ()" ASL macro. + Name (_CRS, ResourceTemplate() { + QWordMemory (...) {...}, + Interrupt (...) {...} + } + ) + + Note: + "_CRS" names defined as methods are not handled by this function. + They must be defined as names, using the "Name ()" statement. + + @ingroup UserApis + + @param [in] NameOpNode NameOp object node defining a named object. + Must have an OpCode=AML_NAME_OP, SubOpCode=0. + NameOp object nodes are defined in ASL + using the "Name ()" function. + @param [out] OutRdNode Pointer to the first Resource Data element of + the named object. A Resource Data element + is stored in a data node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlNameOpGetFirstRdNode ( + IN AML_OBJECT_NODE_HANDLE NameOpNode, + OUT AML_DATA_NODE_HANDLE *OutRdNode + ); + +/** Get the Resource Data element following the CurrRdNode Resource Data. + + In the following ASL code, if CurrRdNode corresponds to the first + "QWordMemory ()" ASL macro, the function will return the Resource Data + node corresponding to the "Interrupt ()" ASL macro. + Name (_CRS, ResourceTemplate() { + QwordMemory (...) {...}, + Interrupt (...) {...} + } + ) + + Note: + "_CRS" names defined as methods are not handled by this function. + They must be defined as names, using the "Name ()" statement. + + @ingroup UserApis + + @param [in] CurrRdNode Pointer to the current Resource Data element of + the named object. + @param [out] OutRdNode Pointer to the Resource Data element following + the CurrRdNode. + Contain a NULL pointer if CurrRdNode is the + last Resource Data element in the list. + The "End Tag" is not considered as a resource + data element and is not returned. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +EFI_STATUS +EFIAPI +AmlNameOpGetNextRdNode ( + IN AML_DATA_NODE_HANDLE CurrRdNode, + OUT AML_DATA_NODE_HANDLE *OutRdNode + ); + +/** Update the first interrupt of an Interrupt resource data node. + + The flags of the Interrupt resource data are left unchanged. + + The InterruptRdNode corresponds to the Resource Data created by the + "Interrupt ()" ASL macro. It is an Extended Interrupt Resource Data. + See ACPI 6.3 specification, s6.4.3.6 "Extended Interrupt Descriptor" + for more information about Extended Interrupt Resource Data. + + @ingroup UserApis + + @param [in] InterruptRdNode Pointer to the an extended interrupt + resource data node. + @param [in] Irq Interrupt value to update. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Out of resources. +**/ +EFI_STATUS +EFIAPI +AmlUpdateRdInterrupt ( + IN AML_DATA_NODE_HANDLE InterruptRdNode, + IN UINT32 Irq + ); + +/** Update the base address and length of a QWord resource data node. + + @ingroup UserApis + + @param [in] QWordRdNode Pointer a QWord resource data + node. + @param [in] BaseAddress Base address. + @param [in] BaseAddressLength Base address length. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Out of resources. +**/ +EFI_STATUS +EFIAPI +AmlUpdateRdQWord ( + IN AML_DATA_NODE_HANDLE QWordRdNode, + IN UINT64 BaseAddress, + IN UINT64 BaseAddressLength + ); + +/** Code generation for the "DWordIO ()" ASL function. + + The Resource Data effectively created is a DWord Address Space Resource + Data. Cf ACPI 6.4: + - s6.4.3.5.2 "DWord Address Space Descriptor". + - s19.6.34 "DWordIO". + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + See ACPI 6.4 spec, s19.6.34 for more. + + @param [in] IsResourceConsumer ResourceUsage parameter. + @param [in] IsMinFixed Minimum address is fixed. + @param [in] IsMaxFixed Maximum address is fixed. + @param [in] IsPosDecode Decode parameter + @param [in] IsaRanges Possible values are: + 0-Reserved + 1-NonISAOnly + 2-ISAOnly + 3-EntireRange + @param [in] AddressGranularity Address granularity. + @param [in] AddressMinimum Minimum address. + @param [in] AddressMaximum Maximum address. + @param [in] AddressTranslation Address translation. + @param [in] RangeLength Range length. + @param [in] ResourceSourceIndex Resource Source index. + Not supported. Must be 0. + @param [in] ResourceSource Resource Source. + Not supported. Must be NULL. + @param [in] IsDenseTranslation TranslationDensity parameter. + @param [in] IsTypeStatic TranslationType parameter. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdDWordIo ( + IN BOOLEAN IsResourceConsumer, + IN BOOLEAN IsMinFixed, + IN BOOLEAN IsMaxFixed, + IN BOOLEAN IsPosDecode, + IN UINT8 IsaRanges, + IN UINT32 AddressGranularity, + IN UINT32 AddressMinimum, + IN UINT32 AddressMaximum, + IN UINT32 AddressTranslation, + IN UINT32 RangeLength, + IN UINT8 ResourceSourceIndex, + IN CONST CHAR8 *ResourceSource, + IN BOOLEAN IsDenseTranslation, + IN BOOLEAN IsTypeStatic, + IN AML_OBJECT_NODE_HANDLE NameOpNode, OPTIONAL + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** Code generation for the "DWordMemory ()" ASL function. + + The Resource Data effectively created is a DWord Address Space Resource + Data. Cf ACPI 6.4: + - s6.4.3.5.2 "DWord Address Space Descriptor". + - s19.6.35 "DWordMemory". + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + See ACPI 6.4 spec, s19.6.35 for more. + + @param [in] IsResourceConsumer ResourceUsage parameter. + @param [in] IsPosDecode Decode parameter + @param [in] IsMinFixed Minimum address is fixed. + @param [in] IsMaxFixed Maximum address is fixed. + @param [in] Cacheable Possible values are: + 0-The memory is non-cacheable + 1-The memory is cacheable + 2-The memory is cacheable and supports + write combining + 3-The memory is cacheable and prefetchable + @param [in] IsReadWrite ReadAndWrite parameter. + @param [in] AddressGranularity Address granularity. + @param [in] AddressMinimum Minimum address. + @param [in] AddressMaximum Maximum address. + @param [in] AddressTranslation Address translation. + @param [in] RangeLength Range length. + @param [in] ResourceSourceIndex Resource Source index. + Not supported. Must be 0. + @param [in] ResourceSource Resource Source. + Not supported. Must be NULL. + @param [in] MemoryRangeType Possible values are: + 0-AddressRangeMemory + 1-AddressRangeReserved + 2-AddressRangeACPI + 3-AddressRangeNVS + @param [in] IsTypeStatic TranslationType parameter. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdDWordMemory ( + IN BOOLEAN IsResourceConsumer, + IN BOOLEAN IsPosDecode, + IN BOOLEAN IsMinFixed, + IN BOOLEAN IsMaxFixed, + IN AML_MEMORY_ATTRIBUTES_MEM Cacheable, + IN BOOLEAN IsReadWrite, + IN UINT32 AddressGranularity, + IN UINT32 AddressMinimum, + IN UINT32 AddressMaximum, + IN UINT32 AddressTranslation, + IN UINT32 RangeLength, + IN UINT8 ResourceSourceIndex, + IN CONST CHAR8 *ResourceSource, + IN AML_MEMORY_ATTRIBUTES_MTP MemoryRangeType, + IN BOOLEAN IsTypeStatic, + IN AML_OBJECT_NODE_HANDLE NameOpNode, OPTIONAL + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** Code generation for the "Memory32Fixed ()" ASL macro. + + The Resource Data effectively created is a 32-bit Memory Resource + Data. Cf ACPI 6.4: + - s19.6.83 "Memory Resource Descriptor Macro". + - s19.2.8 "Memory32FixedTerm". + + See ACPI 6.4 spec, s19.2.8 for more. + + @param [in] IsReadWrite ReadAndWrite parameter. + @param [in] Address AddressBase parameter. + @param [in] RangeLength Range length. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewMemNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdMemory32Fixed ( + BOOLEAN IsReadWrite, + UINT32 Address, + UINT32 RangeLength, + AML_OBJECT_NODE_HANDLE NameOpNode, + AML_DATA_NODE_HANDLE *NewMemNode + ); + +/** Code generation for the "WordBusNumber ()" ASL function. + + The Resource Data effectively created is a Word Address Space Resource + Data. Cf ACPI 6.4: + - s6.4.3.5.3 "Word Address Space Descriptor". + - s19.6.149 "WordBusNumber". + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + See ACPI 6.4 spec, s19.6.149 for more. + + @param [in] IsResourceConsumer ResourceUsage parameter. + @param [in] IsMinFixed Minimum address is fixed. + @param [in] IsMaxFixed Maximum address is fixed. + @param [in] IsPosDecode Decode parameter + @param [in] AddressGranularity Address granularity. + @param [in] AddressMinimum Minimum address. + @param [in] AddressMaximum Maximum address. + @param [in] AddressTranslation Address translation. + @param [in] RangeLength Range length. + @param [in] ResourceSourceIndex Resource Source index. + Not supported. Must be 0. + @param [in] ResourceSource Resource Source. + Not supported. Must be NULL. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdWordBusNumber ( + IN BOOLEAN IsResourceConsumer, + IN BOOLEAN IsMinFixed, + IN BOOLEAN IsMaxFixed, + IN BOOLEAN IsPosDecode, + IN UINT16 AddressGranularity, + IN UINT16 AddressMinimum, + IN UINT16 AddressMaximum, + IN UINT16 AddressTranslation, + IN UINT16 RangeLength, + IN UINT8 ResourceSourceIndex, + IN CONST CHAR8 *ResourceSource, + IN AML_OBJECT_NODE_HANDLE NameOpNode, OPTIONAL + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** Code generation for the "WordIO ()" ASL function. + + The Resource Data effectively created is a Word Address Space Resource + Data. Cf ACPI 6.5: + - s6.4.3.5.3 "Word Address Space Descriptor". + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + @param [in] IsResourceConsumer ResourceUsage parameter. + @param [in] IsMinFixed Minimum address is fixed. + @param [in] IsMaxFixed Maximum address is fixed. + @param [in] IsPosDecode Decode parameter + @param [in] IsaRanges Possible values are: + 0-Reserved + 1-NonISAOnly + 2-ISAOnly + 3-EntireRange + @param [in] AddressGranularity Address granularity. + @param [in] AddressMinimum Minimum address. + @param [in] AddressMaximum Maximum address. + @param [in] AddressTranslation Address translation. + @param [in] RangeLength Range length. + @param [in] ResourceSourceIndex Resource Source index. + Not supported. Must be 0. + @param [in] ResourceSource Resource Source. + Not supported. Must be NULL. + @param [in] IsDenseTranslation TranslationDensity parameter. + @param [in] IsTypeStatic TranslationType parameter. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdWordIo ( + IN BOOLEAN IsResourceConsumer, + IN BOOLEAN IsMinFixed, + IN BOOLEAN IsMaxFixed, + IN BOOLEAN IsPosDecode, + IN UINT8 IsaRanges, + IN UINT16 AddressGranularity, + IN UINT16 AddressMinimum, + IN UINT16 AddressMaximum, + IN UINT16 AddressTranslation, + IN UINT16 RangeLength, + IN UINT8 ResourceSourceIndex, + IN CONST CHAR8 *ResourceSource, + IN BOOLEAN IsDenseTranslation, + IN BOOLEAN IsTypeStatic, + IN AML_OBJECT_NODE_HANDLE NameOpNode, OPTIONAL + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** Code generation for the "QWordIO ()" ASL function. + + The Resource Data effectively created is a QWord Address Space Resource + Data. Cf ACPI 6.4: + - s6.4.3.5.1 "QWord Address Space Descriptor". + - s19.6.109 "QWordIO". + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + See ACPI 6.4 spec, s19.6.109 for more. + + @param [in] IsResourceConsumer ResourceUsage parameter. + @param [in] IsMinFixed Minimum address is fixed. + @param [in] IsMaxFixed Maximum address is fixed. + @param [in] IsPosDecode Decode parameter + @param [in] IsaRanges Possible values are: + 0-Reserved + 1-NonISAOnly + 2-ISAOnly + 3-EntireRange + @param [in] AddressGranularity Address granularity. + @param [in] AddressMinimum Minimum address. + @param [in] AddressMaximum Maximum address. + @param [in] AddressTranslation Address translation. + @param [in] RangeLength Range length. + @param [in] ResourceSourceIndex Resource Source index. + Unused. Must be 0. + @param [in] ResourceSource Resource Source. + Unused. Must be NULL. + @param [in] IsDenseTranslation TranslationDensity parameter. + @param [in] IsTypeStatic TranslationType parameter. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdQWordIo ( + IN BOOLEAN IsResourceConsumer, + IN BOOLEAN IsMinFixed, + IN BOOLEAN IsMaxFixed, + IN BOOLEAN IsPosDecode, + IN UINT8 IsaRanges, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 AddressTranslation, + IN UINT64 RangeLength, + IN UINT8 ResourceSourceIndex, + IN CONST CHAR8 *ResourceSource, + IN BOOLEAN IsDenseTranslation, + IN BOOLEAN IsTypeStatic, + IN AML_OBJECT_NODE_HANDLE NameOpNode, OPTIONAL + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** Code generation for the "QWordMemory ()" ASL function. + + The Resource Data effectively created is a QWord Address Space Resource + Data. Cf ACPI 6.4: + - s6.4.3.5.1 "QWord Address Space Descriptor". + - s19.6.110 "QWordMemory". + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + See ACPI 6.4 spec, s19.6.110 for more. + + @param [in] IsResourceConsumer ResourceUsage parameter. + @param [in] IsPosDecode Decode parameter. + @param [in] IsMinFixed Minimum address is fixed. + @param [in] IsMaxFixed Maximum address is fixed. + @param [in] Cacheable Possible values are: + 0-The memory is non-cacheable + 1-The memory is cacheable + 2-The memory is cacheable and supports + write combining + 3-The memory is cacheable and prefetchable + @param [in] IsReadWrite ReadAndWrite parameter. + @param [in] AddressGranularity Address granularity. + @param [in] AddressMinimum Minimum address. + @param [in] AddressMaximum Maximum address. + @param [in] AddressTranslation Address translation. + @param [in] RangeLength Range length. + @param [in] ResourceSourceIndex Resource Source index. + Not supported. Must be 0. + @param [in] ResourceSource Resource Source. + Not supported. Must be NULL. + @param [in] MemoryRangeType Possible values are: + 0-AddressRangeMemory + 1-AddressRangeReserved + 2-AddressRangeACPI + 3-AddressRangeNVS + @param [in] IsTypeStatic TranslationType parameter. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data + node to the list of resource data elements + of this node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdQWordMemory ( + IN BOOLEAN IsResourceConsumer, + IN BOOLEAN IsPosDecode, + IN BOOLEAN IsMinFixed, + IN BOOLEAN IsMaxFixed, + IN AML_MEMORY_ATTRIBUTES_MEM Cacheable, + IN BOOLEAN IsReadWrite, + IN UINT64 AddressGranularity, + IN UINT64 AddressMinimum, + IN UINT64 AddressMaximum, + IN UINT64 AddressTranslation, + IN UINT64 RangeLength, + IN UINT8 ResourceSourceIndex, + IN CONST CHAR8 *ResourceSource, + IN AML_MEMORY_ATTRIBUTES_MTP MemoryRangeType, + IN BOOLEAN IsTypeStatic, + IN AML_OBJECT_NODE_HANDLE NameOpNode, OPTIONAL + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** Code generation for the "Interrupt ()" ASL function. + + The Resource Data effectively created is an Extended Interrupt Resource + Data. Cf ACPI 6.4: + - s6.4.3.6 "Extended Interrupt Descriptor" + - s19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)" + + The created resource data node can be: + - appended to the list of resource data elements of the NameOpNode. + In such case NameOpNode must be defined by a the "Name ()" ASL statement + and initially contain a "ResourceTemplate ()". + - returned through the NewRdNode parameter. + + @ingroup CodeGenApis + + @param [in] ResourceConsumer The device consumes the specified interrupt + or produces it for use by a child device. + @param [in] EdgeTriggered The interrupt is edge triggered or + level triggered. + @param [in] ActiveLow The interrupt is active-high or active-low. + @param [in] Shared The interrupt can be shared with other + devices or not (Exclusive). + @param [in] IrqList Interrupt list. Must be non-NULL. + @param [in] IrqCount Interrupt count. Must be non-zero. + @param [in] NameOpNode NameOp object node defining a named object. + If provided, append the new resource data node + to the list of resource data elements of this + node. + @param [out] NewRdNode If provided and success, + contain the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenRdInterrupt ( + IN BOOLEAN ResourceConsumer, + IN BOOLEAN EdgeTriggered, + IN BOOLEAN ActiveLow, + IN BOOLEAN Shared, + IN UINT32 *IrqList, + IN UINT8 IrqCount, + IN AML_OBJECT_NODE_HANDLE NameOpNode OPTIONAL, + OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL + ); + +/** AML code generation for DefinitionBlock. + + Create a Root Node handle. + It is the caller's responsibility to free the allocated memory + with the AmlDeleteTree function. + + AmlCodeGenDefinitionBlock (TableSignature, OemId, TableID, OEMRevision) is + equivalent to the following ASL code: + DefinitionBlock (AMLFileName, TableSignature, ComplianceRevision, + OemId, TableID, OEMRevision) {} + with the ComplianceRevision set to 2 and the AMLFileName is ignored. + + @ingroup CodeGenApis + + @param[in] TableSignature 4-character ACPI signature. + Must be 'DSDT' or 'SSDT'. + @param[in] OemId 6-character string OEM identifier. + @param[in] OemTableId 8-character string OEM table identifier. + @param[in] OemRevision OEM revision number. + @param[out] DefinitionBlockTerm The ASL Term handle representing a + Definition Block. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenDefinitionBlock ( + IN CONST CHAR8 *TableSignature, + IN CONST CHAR8 *OemId, + IN CONST CHAR8 *OemTableId, + IN UINT32 OemRevision, + OUT AML_ROOT_NODE_HANDLE *NewRootNode + ); + +/** AML code generation for a Name object node, containing a String. + + AmlCodeGenNameString ("_HID", "HID0000", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(_HID, "HID0000") + + @ingroup CodeGenApis + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] String NULL terminated String to associate to the + NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameString ( + IN CONST CHAR8 *NameString, + IN CHAR8 *String, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a Name object node, containing an Integer. + + AmlCodeGenNameInteger ("_UID", 1, ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(_UID, One) + + @ingroup CodeGenApis + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] Integer Integer to associate to the NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameInteger ( + IN CONST CHAR8 *NameString, + IN UINT64 Integer, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a Name object node, containing a Package. + + AmlCodeGenNamePackage ("PKG0", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(PKG0, Package () {}) + + @ingroup CodeGenApis + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNamePackage ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HANDLE ParentNode, OPTIONAL + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a Name object node, containing a ResourceTemplate. + + AmlCodeGenNameResourceTemplate ("PRS0", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(PRS0, ResourceTemplate () {}) + + @ingroup CodeGenApis + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameResourceTemplate ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HANDLE ParentNode, OPTIONAL + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a Name object node, containing a String. + + AmlCodeGenNameUnicodeString ("_STR", L"String", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(_STR, Unicode ("String")) + + @ingroup CodeGenApis + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] String NULL terminated Unicode String to associate to the + NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameUnicodeString ( + IN CONST CHAR8 *NameString, + IN CHAR16 *String, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** Add a _PRT entry. + + AmlCodeGenPrtEntry (0x0FFFF, 0, "LNKA", 0, PrtNameNode) is + equivalent of the following ASL code: + Package (4) { + 0x0FFFF, // Address: Device address (([Device Id] << 16) | 0xFFFF). + 0, // Pin: PCI pin number of the device (0-INTA, ...). + LNKA // Source: Name of the device that allocates the interrupt + // to which the above pin is connected. + 0 // Source Index: Source is assumed to only describe one + // interrupt, so let it to index 0. + } + + The package is added at the tail of the list of the input _PRT node + name: + Name (_PRT, Package () { + [Pre-existing _PRT entries], + [Newly created _PRT entry] + }) + + Cf. ACPI 6.4, s6.2.13 "_PRT (PCI Routing Table)" + + @ingroup CodeGenApis + + @param [in] Address Address. Cf ACPI 6.4 specification, Table 6.2: + "ADR Object Address Encodings": + High word-Device #, Low word-Function #. (for + example, device 3, function 2 is 0x00030002). + To refer to all the functions on a device #, + use a function number of FFFF). + @param [in] Pin PCI pin number of the device (0-INTA ... 3-INTD). + Must be between 0-3. + @param [in] LinkName Link Name, i.e. device in the AML NameSpace + describing the interrupt used. + The input string is copied. + @param [in] SourceIndex Source index or GSIV. + @param [in] PrtNameNode Prt Named node to add the object to .... + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddPrtEntry ( + IN UINT32 Address, + IN UINT8 Pin, + IN CONST CHAR8 *LinkName, + IN UINT32 SourceIndex, + IN AML_OBJECT_NODE_HANDLE PrtNameNode + ); + +/** AML code generation for a Device object node. + + AmlCodeGenDevice ("COM0", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Device(COM0) {} + + @ingroup CodeGenApis + + @param [in] NameString The new Device's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenDevice ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a ThermalZone object node. + + AmlCodeGenThermalZone ("TZ00", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + ThermalZone(TZ00) {} + + @ingroup CodeGenApis + + @param [in] NameString The new ThermalZone's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenThermalZone ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a Scope object node. + + AmlCodeGenScope ("_SB", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Scope(_SB) {} + + @ingroup CodeGenApis + + @param [in] NameString The new Scope's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenScope ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a method returning a NameString. + + AmlCodeGenMethodRetNameString ( + "MET0", "_CRS", 1, TRUE, 3, ParentNode, NewObjectNode + ); + is equivalent of the following ASL code: + Method(MET0, 1, Serialized, 3) { + Return (_CRS) + } + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @ingroup CodeGenApis + + @param [in] MethodNameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] ReturnedNameString The name of the object returned by the + method. Optional parameter, can be: + - NULL (ignored). + - A NULL-terminated ASL NameString. + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenMethodRetNameString ( + IN CONST CHAR8 *MethodNameString, + IN CONST CHAR8 *ReturnedNameString OPTIONAL, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a method returning an Integer. + + AmlCodeGenMethodRetInteger ( + "_CBA", 0, 1, TRUE, 3, ParentNode, NewObjectNode + ); + is equivalent of the following ASL code: + Method(_CBA, 1, Serialized, 3) { + Return (0) + } + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @param [in] MethodNameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] ReturnedInteger The value of the integer returned by the + method. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenMethodRetInteger ( + IN CONST CHAR8 *MethodNameString, + IN UINT64 ReturnedInteger, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** AML code generation for a method returning a NameString that takes an + integer argument. + + AmlCodeGenMethodRetNameStringIntegerArgument ( + "MET0", "MET1", 1, TRUE, 3, 5, ParentNode, NewObjectNode + ); + is equivalent of the following ASL code: + Method(MET0, 1, Serialized, 3) { + Return (MET1 (5)) + } + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @param [in] MethodNameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] ReturnedNameString The name of the object returned by the + method. Optional parameter, can be: + - NULL (ignored). + - A NULL-terminated ASL NameString. + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] IntegerArgument Argument to pass to the NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenMethodRetNameStringIntegerArgument ( + IN CONST CHAR8 *MethodNameString, + IN CONST CHAR8 *ReturnedNameString OPTIONAL, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN UINT64 IntegerArgument, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ); + +/** Create a _LPI name. + + AmlCreateLpiNode ("_LPI", 0, 1, ParentNode, &LpiNode) is + equivalent of the following ASL code: + Name (_LPI, Package ( + 0, // Revision + 1, // LevelId + 0 // Count + )) + + This function doesn't define any LPI state. As shown above, the count + of _LPI state is set to 0. + The AmlAddLpiState () function must be used to add LPI states. + + Cf ACPI 6.3 specification, s8.4.4 "Lower Power Idle States". + + @ingroup CodeGenApis + + @param [in] LpiNameString The new LPI 's object name. + Must be a NULL-terminated ASL NameString + e.g.: "_LPI", "DEV0.PLPI", etc. + The input string is copied. + @param [in] Revision Revision number of the _LPI states. + @param [in] LevelId A platform defined number that identifies the + level of hierarchy of the processor node to + which the LPI states apply. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewLpiNode If success, contains the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCreateLpiNode ( + IN CONST CHAR8 *LpiNameString, + IN UINT16 Revision, + IN UINT64 LevelId, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewLpiNode OPTIONAL + ); + +/** Add an _LPI state to a LPI node created using AmlCreateLpiNode (). + + AmlAddLpiState () increments the Count of LPI states in the LPI node by one, + and adds the following package: + Package() { + MinResidency, + WorstCaseWakeLatency, + Flags, + ArchFlags, + ResCntFreq, + EnableParentState, + (GenericRegisterDescriptor != NULL) ? // Entry method. If a + ResourceTemplate(GenericRegisterDescriptor) : // Register is given, + Integer, // use it. Use the + // Integer otherwise. + ResourceTemplate() { // NULL Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // NULL Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "" // NULL State Name + }, + + Cf ACPI 6.3 specification, s8.4.4 "Lower Power Idle States". + + @ingroup CodeGenApis + + @param [in] MinResidency Minimum Residency. + @param [in] WorstCaseWakeLatency Worst case wake-up latency. + @param [in] Flags Flags. + @param [in] ArchFlags Architectural flags. + @param [in] ResCntFreq Residency Counter Frequency. + @param [in] EnableParentState Enabled Parent State. + @param [in] GenericRegisterDescriptor Entry Method. + If not NULL, use this Register to + describe the entry method address. + @param [in] Integer Entry Method. + If GenericRegisterDescriptor is NULL, + take this value. + @param [in] ResidencyCounterRegister If not NULL, use it to populate the + residency counter register. + @param [in] UsageCounterRegister If not NULL, use it to populate the + usage counter register. + @param [in] StateName If not NULL, use it to populate the + state name. + @param [in] LpiNode Lpi node created with the function + AmlCreateLpiNode to which the new LPI + state is appended. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddLpiState ( + IN UINT32 MinResidency, + IN UINT32 WorstCaseWakeLatency, + IN UINT32 Flags, + IN UINT32 ArchFlags, + IN UINT32 ResCntFreq, + IN UINT32 EnableParentState, + IN EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE *GenericRegisterDescriptor OPTIONAL, + IN UINT64 Integer OPTIONAL, + IN EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE *ResidencyCounterRegister OPTIONAL, + IN EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE *UsageCounterRegister OPTIONAL, + IN CHAR8 *StateName OPTIONAL, + IN AML_OBJECT_NODE_HANDLE LpiNode + ); + +/** AML code generation for a _DSD device data object. + + AmlAddDeviceDataDescriptorPackage (Uuid, DsdNode, PackageNode) is + equivalent of the following ASL code: + ToUUID(Uuid), + Package () {} + + Cf ACPI 6.4 specification, s6.2.5 "_DSD (Device Specific Data)". + + _DSD (Device Specific Data) Implementation Guide + https://github.com/UEFI/DSD-Guide + Per s3. "'Well-Known _DSD UUIDs and Data Structure Formats'" + If creating a Device Properties data then UUID daffd814-6eba-4d8c-8a91-bc9bbf4aa301 should be used. + + @param [in] Uuid The Uuid of the descriptor to be created + @param [in] DsdNode Node of the DSD Package. + @param [out] PackageNode If success, contains the created package node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddDeviceDataDescriptorPackage ( + IN CONST EFI_GUID *Uuid, + IN AML_OBJECT_NODE_HANDLE DsdNode, + OUT AML_OBJECT_NODE_HANDLE *PackageNode + ); + +/** AML code generation to add a package with a name and value, + to a parent package. + This is useful to build the _DSD package but can be used in other cases. + + AmlAddNameIntegerPackage ("Name", Value, PackageNode) is + equivalent of the following ASL code: + Package (2) {"Name", Value} + + Cf ACPI 6.4 specification, s6.2.5 "_DSD (Device Specific Data)". + + @param [in] Name String to place in first entry of package + @param [in] Value Integer to place in second entry of package + @param [in] PackageNode Package to add new sub package to. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddNameIntegerPackage ( + IN CHAR8 *Name, + IN UINT64 Value, + IN AML_OBJECT_NODE_HANDLE PackageNode + ); + +/** Create a _CPC node. + + Creates and optionally adds the following node + Name(_CPC, Package() + { + NumEntries, // Integer + Revision, // Integer + HighestPerformance, // Integer or Buffer (Resource Descriptor) + NominalPerformance, // Integer or Buffer (Resource Descriptor) + LowestNonlinearPerformance, // Integer or Buffer (Resource Descriptor) + LowestPerformance, // Integer or Buffer (Resource Descriptor) + GuaranteedPerformanceRegister, // Buffer (Resource Descriptor) + DesiredPerformanceRegister , // Buffer (Resource Descriptor) + MinimumPerformanceRegister , // Buffer (Resource Descriptor) + MaximumPerformanceRegister , // Buffer (Resource Descriptor) + PerformanceReductionToleranceRegister, // Buffer (Resource Descriptor) + TimeWindowRegister, // Buffer (Resource Descriptor) + CounterWraparoundTime, // Integer or Buffer (Resource Descriptor) + ReferencePerformanceCounterRegister, // Buffer (Resource Descriptor) + DeliveredPerformanceCounterRegister, // Buffer (Resource Descriptor) + PerformanceLimitedRegister, // Buffer (Resource Descriptor) + CPPCEnableRegister // Buffer (Resource Descriptor) + AutonomousSelectionEnable, // Integer or Buffer (Resource Descriptor) + AutonomousActivityWindowRegister, // Buffer (Resource Descriptor) + EnergyPerformancePreferenceRegister, // Buffer (Resource Descriptor) + ReferencePerformance // Integer or Buffer (Resource Descriptor) + LowestFrequency, // Integer or Buffer (Resource Descriptor) + NominalFrequency // Integer or Buffer (Resource Descriptor) + }) + + If resource buffer is NULL then integer will be used. + + Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control) + + @ingroup CodeGenApis + + @param [in] CpcInfo CpcInfo object + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewCpcNode If success and provided, contains the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCreateCpcNode ( + IN AML_CPC_INFO *CpcInfo, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewCpcNode OPTIONAL + ); + +/** AML code generation to add a NameString to the package in a named node. + + + @param [in] NameString NameString to add + @param [in] NamedNode Node to add the string to the included package. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddNameStringToNamedPackage ( + IN CHAR8 *NameString, + IN AML_OBJECT_NODE_HANDLE NamedNode + ); + +/** AML code generation to invoke/call another method. + + This method is a subset implementation of MethodInvocation + defined in the ACPI specification 6.5, + section 20.2.5 "Term Objects Encoding". + Added integer, string, ArgObj and LocalObj support. + + Example 1: + AmlCodeGenInvokeMethod ("MET0", 0, NULL, ParentNode); + is equivalent to the following ASL code: + MET0 (); + + Example 2: + AML_METHOD_PARAM Param[4]; + Param[0].Data.Integer = 0x100; + Param[0].Type = AmlMethodParamTypeInteger; + Param[1].Data.Buffer = "TEST"; + Param[1].Type = AmlMethodParamTypeString; + Param[2].Data.Arg = 0; + Param[2].Type = AmlMethodParamTypeArg; + Param[3].Data.Local = 2; + Param[3].Type = AmlMethodParamTypeLocal; + AmlCodeGenInvokeMethod ("MET0", 4, Param, ParentNode); + + is equivalent to the following ASL code: + MET0 (0x100, "TEST", Arg0, Local2); + + Example 3: + AML_METHOD_PARAM Param[2]; + Param[0].Data.Arg = 0; + Param[0].Type = AmlMethodParamTypeArg; + Param[1].Data.Integer = 0x100; + Param[1].Type = AmlMethodParamTypeInteger; + AmlCodeGenMethodRetNameString ("MET2", NULL, 2, TRUE, 0, ParentNode, &MethodNode); + AmlCodeGenInvokeMethod ("MET3", 2, Param, MethodNode); + + is equivalent to the following ASL code: + Method (MET2, 2, Serialized) + { + MET3 (Arg0, 0x0100) + } + + @param [in] MethodNameString The method name to be called or invoked. + @param [in] NumArgs Number of arguments to be passed, + 0 to 7 are permissible values. + @param [in] Parameters Contains the parameter data. + @param [in] ParentNode The parent node to which the method invocation + nodes are attached. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. + **/ +EFI_STATUS +EFIAPI +AmlCodeGenInvokeMethod ( + IN CONST CHAR8 *MethodNameString, + IN UINT8 NumArgs, + IN AML_METHOD_PARAM *Parameters OPTIONAL, + IN AML_NODE_HANDLE ParentNode + ); + +/** Create a _PSD node. + + Creates and optionally adds the following node + Name(_PSD, Package() + { + NumEntries, // Integer + Revision, // Integer + Domain, // Integer + CoordType, // Integer + NumProc, // Integer + }) + + Cf. ACPI 6.5, s8.4.5.5 _PSD (P-State Dependency) + + @ingroup CodeGenApis + + @param [in] PsdInfo PsdInfo object + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewPsdNode If success and provided, contains the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCreatePsdNode ( + IN AML_PSD_INFO *PsdInfo, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewPsdNode OPTIONAL + ); + +/** Create a _OST method for AMD platform. + + Method (_OST, 3, Serialized) + { + \_SB.host (Arg0, Arg1, BRB, _ADR) + } + + @ingroup CodeGenApis + + @param [in] DeviceNode DeviceNode object + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_STATUS Other failure +**/ +EFI_STATUS +EFIAPI +AmdAmlCodeGenMethodInvokeMethodOst ( + IN OUT AML_OBJECT_NODE_HANDLE DeviceNode + ); + +/** Create a _DSM method for AMD platform. + + Method (_DSM, 4, Serialized) + { + \_SB.HDSM (Arg0, Arg1, Arg2, Arg3, BRB, _ADR, RSTR) + } + + @ingroup CodeGenApis + + @param [in] DeviceNode DeviceNode object + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_STATUS Other failure +**/ +EFI_STATUS +EFIAPI +AmdAmlCodeGenMethodInvokeMethodDsm ( + IN OUT AML_OBJECT_NODE_HANDLE DeviceNode + ); + +/** Create a _OSC method for AMD platform. + + Method (_OSC, 4, NotSerialized, 4) // _OSC: Operating System Capabilities + { + Return (\_SB.OSCI (Arg0, Arg1, Arg2, Arg3)) + } + + @ingroup CodeGenApis + + @param [in] DeviceNode DeviceNode object + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_STATUS Other failure +**/ +EFI_STATUS +EFIAPI +AmdAmlCodeGenMethodInvokeMethodOsc ( + IN OUT AML_OBJECT_NODE_HANDLE DeviceNode + ); + +/** Add an integer value to Package node. + + AmlCodeGenNamePackage ("_CID", NULL, &PackageNode); + AmlGetEisaIdFromString ("PNP0A03", &EisaId); + AmlAddIntegerPackageEntry (EisaId, PackageNameNode); + AmlGetEisaIdFromString ("PNP0A08", &EisaId); + AmlAddIntegerPackageEntry (EisaId, PackageNameNode); + + equivalent of the following ASL code: + Name (_CID, Package (0x02) // _CID: Compatible ID + { + EisaId ("PNP0A03"), + EisaId ("PNP0A08") + }) + + The package is added at the tail of the list of the input package node + name: + Name ("NamePackageNode", Package () { + [Pre-existing package entries], + [Newly created integer entry] + }) + + + @ingroup CodeGenApis + + @param [in] Integer Integer value that need to be added to package node. + @param [in] PackageNameNode Prt Named node to add the object to .... + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddIntegerPackageEntry ( + IN UINT64 Integer, + IN AML_OBJECT_NODE_HANDLE PackageNameNode + ); + +#endif // AML_LIB_H_ diff --git a/Platform/AMD/TurinBoard/Override/edk2/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c b/Platform/AMD/TurinBoard/Override/edk2/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c new file mode 100644 index 0000000000000000000000000000000000000000..27b11e604a360a4585e232f9e151e7d3e1c69941 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c @@ -0,0 +1,5072 @@ +/** @file + AML Code Generation. + + Copyright (c) 2020 - 2023, Arm Limited. All rights reserved.
+ Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** Utility function to link a node when returning from a CodeGen function. + + @param [in] Node Newly created node. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If not NULL: + - and Success, contains the created Node. + - and Error, reset to NULL. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +STATIC +EFI_STATUS +EFIAPI +LinkNode ( + IN AML_OBJECT_NODE *Node, + IN AML_NODE_HEADER *ParentNode, + OUT AML_OBJECT_NODE **NewObjectNode + ) +{ + EFI_STATUS Status; + + if (NewObjectNode != NULL) { + *NewObjectNode = NULL; + } + + // Add RdNode as the last element. + if (ParentNode != NULL) { + Status = AmlVarListAddTail (ParentNode, (AML_NODE_HEADER *)Node); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + } + + if (NewObjectNode != NULL) { + *NewObjectNode = Node; + } + + return EFI_SUCCESS; +} + +/** AML code generation for DefinitionBlock. + + Create a Root Node handle. + It is the caller's responsibility to free the allocated memory + with the AmlDeleteTree function. + + AmlCodeGenDefinitionBlock (TableSignature, OemID, TableID, OEMRevision) is + equivalent to the following ASL code: + DefinitionBlock (AMLFileName, TableSignature, ComplianceRevision, + OemID, TableID, OEMRevision) {} + with the ComplianceRevision set to 2 and the AMLFileName is ignored. + + @param[in] TableSignature 4-character ACPI signature. + Must be 'DSDT' or 'SSDT'. + @param[in] OemId 6-character string OEM identifier. + @param[in] OemTableId 8-character string OEM table identifier. + @param[in] OemRevision OEM revision number. + @param[out] NewRootNode Pointer to the root node representing a + Definition Block. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenDefinitionBlock ( + IN CONST CHAR8 *TableSignature, + IN CONST CHAR8 *OemId, + IN CONST CHAR8 *OemTableId, + IN UINT32 OemRevision, + OUT AML_ROOT_NODE **NewRootNode + ) +{ + EFI_STATUS Status; + EFI_ACPI_DESCRIPTION_HEADER AcpiHeader; + + if ((TableSignature == NULL) || + (OemId == NULL) || + (OemTableId == NULL) || + (NewRootNode == NULL)) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + CopyMem (&AcpiHeader.Signature, TableSignature, 4); + AcpiHeader.Length = sizeof (EFI_ACPI_DESCRIPTION_HEADER); + AcpiHeader.Revision = 2; + CopyMem (&AcpiHeader.OemId, OemId, 6); + CopyMem (&AcpiHeader.OemTableId, OemTableId, 8); + AcpiHeader.OemRevision = OemRevision; + AcpiHeader.CreatorId = TABLE_GENERATOR_CREATOR_ID_ARM; + AcpiHeader.CreatorRevision = CREATE_REVISION (1, 0); + + Status = AmlCreateRootNode (&AcpiHeader, NewRootNode); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** AML code generation for a String object node. + + @param [in] String Pointer to a NULL terminated string. + @param [out] NewObjectNode If success, contains the created + String object node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenString ( + IN CHAR8 *String, + OUT AML_OBJECT_NODE **NewObjectNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + + if ((String == NULL) || + (NewObjectNode == NULL)) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + DataNode = NULL; + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_STRING_PREFIX, 0), + 0, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeString, + (UINT8 *)String, + (UINT32)AsciiStrLen (String) + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + goto error_handler; + } + + *NewObjectNode = ObjectNode; + return Status; + +error_handler: + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + return Status; +} + +/** AML code generation for an Integer object node. + + @param [in] Integer Integer of the Integer object node. + @param [out] NewObjectNode If success, contains the created + Integer object node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenInteger ( + IN UINT64 Integer, + OUT AML_OBJECT_NODE **NewObjectNode + ) +{ + EFI_STATUS Status; + INT8 ValueWidthDiff; + + if (NewObjectNode == NULL) { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // Create an object node containing Zero. + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_ZERO_OP, 0), + 0, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // Update the object node with integer value. + Status = AmlNodeSetIntegerValue (*NewObjectNode, Integer, &ValueWidthDiff); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)*NewObjectNode); + } + + return Status; +} + +/** AML code generation for a Package object node. + + The package generated is empty. New elements can be added via its + list of variable arguments. + + @param [out] NewObjectNode If success, contains the created + Package object node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenPackage ( + OUT AML_OBJECT_NODE **NewObjectNode + ) +{ + EFI_STATUS Status; + AML_DATA_NODE *DataNode; + UINT8 NodeCount; + + if (NewObjectNode == NULL) { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + NodeCount = 0; + + // Create an object node. + // PkgLen is 2: + // - one byte to store the PkgLength + // - one byte for the NumElements. + // Cf ACPI6.3, s20.2.5 "Term Objects Encoding" + // DefPackage := PackageOp PkgLength NumElements PackageElementList + // NumElements := ByteData + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_PACKAGE_OP, 0), + 2, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // NumElements is a ByteData. + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + &NodeCount, + sizeof (NodeCount), + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlSetFixedArgument ( + *NewObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + AmlDeleteTree ((AML_NODE_HEADER *)*NewObjectNode); + if (DataNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + } + + return Status; +} + +/** AML code generation for a Buffer object node. + + To create a Buffer object node with an empty buffer, + call the function with (Buffer=NULL, BufferSize=0). + + @param [in] Buffer Buffer to set for the created Buffer + object node. The Buffer's content is copied. + NULL if there is no buffer to set for + the Buffer node. + @param [in] BufferSize Size of the Buffer. + 0 if there is no buffer to set for + the Buffer node. + @param [out] NewObjectNode If success, contains the created + Buffer object node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenBuffer ( + IN CONST UINT8 *Buffer OPTIONAL, + IN UINT32 BufferSize OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *BufferNode; + AML_OBJECT_NODE *BufferSizeNode; + UINT32 BufferSizeNodeSize; + AML_DATA_NODE *DataNode; + UINT32 PkgLen; + + // Buffer and BufferSize must be either both set, or both clear. + if ((NewObjectNode == NULL) || + ((Buffer == NULL) != (BufferSize == 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + BufferNode = NULL; + DataNode = NULL; + + // Cf ACPI 6.3 specification, s20.2.5.4 "Type 2 Opcodes Encoding" + // DefBuffer := BufferOp PkgLength BufferSize ByteList + // BufferOp := 0x11 + // BufferSize := TermArg => Integer + + Status = AmlCodeGenInteger (BufferSize, &BufferSizeNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // Get the number of bytes required to encode the BufferSizeNode. + Status = AmlComputeSize ( + (AML_NODE_HEADER *)BufferSizeNode, + &BufferSizeNodeSize + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + // Compute the size to write in the PkgLen. + Status = AmlComputePkgLength (BufferSizeNodeSize + BufferSize, &PkgLen); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + // Create an object node for the buffer. + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_BUFFER_OP, 0), + PkgLen, + &BufferNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + // Set the BufferSizeNode as a fixed argument of the BufferNode. + Status = AmlSetFixedArgument ( + BufferNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)BufferSizeNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + // BufferSizeNode is now attached. + BufferSizeNode = NULL; + + // If there is a buffer, create a DataNode and attach it to the BufferNode. + if (Buffer != NULL) { + Status = AmlCreateDataNode ( + EAmlNodeDataTypeRaw, + Buffer, + BufferSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)BufferNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + } + + *NewObjectNode = BufferNode; + return Status; + +error_handler: + if (BufferSizeNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)BufferSizeNode); + } + + if (BufferNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)BufferNode); + } + + if (DataNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + } + + return Status; +} + +/** AML code generation for a ResourceTemplate. + + "ResourceTemplate" is a macro defined in ACPI 6.3, s19.3.3 + "ASL Resource Templates". It allows to store resource data elements. + + In AML, a ResourceTemplate is implemented as a Buffer storing resource + data elements. An EndTag resource data descriptor must be at the end + of the list of resource data elements. + This function generates a Buffer node with an EndTag resource data + descriptor. It can be seen as an empty list of resource data elements. + + @param [out] NewObjectNode If success, contains the created + ResourceTemplate object node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenResourceTemplate ( + OUT AML_OBJECT_NODE **NewObjectNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *BufferNode; + + if (NewObjectNode == NULL) { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // Create a BufferNode with an empty buffer. + Status = AmlCodeGenBuffer (NULL, 0, &BufferNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // Create an EndTag resource data element and attach it to the Buffer. + Status = AmlCodeGenEndTag (0, BufferNode, NULL); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)BufferNode); + return Status; + } + + *NewObjectNode = BufferNode; + return Status; +} + +/** AML code generation for a Name object node. + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + This input string is copied. + @param [in] Object Object associated to the NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenName ( + IN CONST CHAR8 *NameString, + IN AML_OBJECT_NODE *Object, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + if ((NameString == NULL) || + (Object == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + ObjectNode = NULL; + DataNode = NULL; + AmlNameString = NULL; + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_NAME_OP, 0), + 0, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + goto error_handler2; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm1, + (AML_NODE_HEADER *)Object + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + Status = LinkNode ( + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // Free AmlNameString before returning as it is copied + // in the call to AmlCreateDataNode(). + goto error_handler1; + +error_handler2: + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + +error_handler1: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a Name object node, containing a String. + + AmlCodeGenNameString ("_HID", "HID0000", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(_HID, "HID0000") + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] String NULL terminated String to associate to the + NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameString ( + IN CONST CHAR8 *NameString, + IN CHAR8 *String, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + + if ((NameString == NULL) || + (String == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCodeGenString (String, &ObjectNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenName ( + NameString, + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + + return Status; +} + +/** AML code generation for a Name object node, containing an Integer. + + AmlCodeGenNameInteger ("_UID", 1, ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(_UID, One) + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] Integer Integer to associate to the NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameInteger ( + IN CONST CHAR8 *NameString, + IN UINT64 Integer, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + + if ((NameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCodeGenInteger (Integer, &ObjectNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenName ( + NameString, + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + + return Status; +} + +/** AML code generation for a Name object node, containing a Package. + + AmlCodeGenNamePackage ("PKG0", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(PKG0, Package () {}) + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNamePackage ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HEADER *ParentNode, OPTIONAL + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *PackageNode; + + if ((NameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCodeGenPackage (&PackageNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenName ( + NameString, + PackageNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)PackageNode); + } + + return Status; +} + +/** AML code generation for a Name object node, containing a ResourceTemplate. + + AmlCodeGenNameResourceTemplate ("PRS0", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(PRS0, ResourceTemplate () {}) + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameResourceTemplate ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HEADER *ParentNode, OPTIONAL + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ResourceTemplateNode; + + if ((NameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCodeGenResourceTemplate (&ResourceTemplateNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenName ( + NameString, + ResourceTemplateNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)ResourceTemplateNode); + } + + return Status; +} + +/** AML code generation for a Name object node, containing a String. + + AmlCodeGenNameUnicodeString ("_STR", L"String", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Name(_STR, Unicode ("String")) + + @ingroup CodeGenApis + + @param [in] NameString The new variable name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] String NULL terminated Unicode String to associate to the + NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenNameUnicodeString ( + IN CONST CHAR8 *NameString, + IN CHAR16 *String, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + + if ((NameString == NULL) || + (String == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCodeGenBuffer (NULL, 0, &ObjectNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeRaw, + (CONST UINT8 *)String, + (UINT32)StrSize (String), + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + return Status; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)ObjectNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + AmlDeleteTree ((AML_NODE_HANDLE)DataNode); + return Status; + } + + Status = AmlCodeGenName ( + NameString, + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + + return Status; +} + +/** Add a _PRT entry. + + AmlCodeGenPrtEntry (0x0FFFF, 0, "LNKA", 0, PrtNameNode) is + equivalent of the following ASL code: + Package (4) { + 0x0FFFF, // Address: Device address (([Device Id] << 16) | 0xFFFF). + 0, // Pin: PCI pin number of the device (0-INTA, ...). + LNKA // Source: Name of the device that allocates the interrupt + // to which the above pin is connected. + 0 // Source Index: Source is assumed to only describe one + // interrupt, so let it to index 0. + } + + The 2 models described in ACPI 6.4, s6.2.13 "_PRT (PCI Routing Table)" can + be generated by this function. The example above matches the first model. + + The package is added at the tail of the list of the input _PRT node + name: + Name (_PRT, Package () { + [Pre-existing _PRT entries], + [Newly created _PRT entry] + }) + + Cf. ACPI 6.4 specification: + - s6.2.13 "_PRT (PCI Routing Table)" + - s6.1.1 "_ADR (Address)" + + @param [in] Address Address. Cf ACPI 6.4 specification, Table 6.2: + "ADR Object Address Encodings": + High word-Device #, Low word-Function #. (for + example, device 3, function 2 is 0x00030002). + To refer to all the functions on a device #, + use a function number of FFFF). + @param [in] Pin PCI pin number of the device (0-INTA ... 3-INTD). + Must be between 0-3. + @param [in] LinkName Link Name, i.e. device in the AML NameSpace + describing the interrupt used. The input string + is copied. + If NULL, generate 0 in the 'Source' field (cf. + second model, using GSIV). + @param [in] SourceIndex Source index or GSIV. + @param [in] PrtNameNode Prt Named node to add the object to .... + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddPrtEntry ( + IN UINT32 Address, + IN UINT8 Pin, + IN CONST CHAR8 *LinkName, + IN UINT32 SourceIndex, + IN AML_OBJECT_NODE_HANDLE PrtNameNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *PrtEntryList; + AML_OBJECT_NODE *PackageNode; + AML_OBJECT_NODE *NewElementNode; + + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + AML_DATA_NODE *DataNode; + + if ((Pin > 3) || + (PrtNameNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PrtNameNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PrtNameNode, AML_NAME_OP, 0)) || + !AmlNameOpCompareName (PrtNameNode, "_PRT")) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + NewElementNode = NULL; + AmlNameString = NULL; + DataNode = NULL; + + // Get the Package object node of the _PRT node, + // which is the 2nd fixed argument (i.e. index 1). + PrtEntryList = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + PrtNameNode, + EAmlParseIndexTerm1 + ); + if ((PrtEntryList == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PrtEntryList) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PrtEntryList, AML_PACKAGE_OP, 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // The new _PRT entry. + Status = AmlCodeGenPackage (&PackageNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenInteger (Address, &NewElementNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)NewElementNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + NewElementNode = NULL; + + Status = AmlCodeGenInteger (Pin, &NewElementNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)NewElementNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + NewElementNode = NULL; + + if (LinkName != NULL) { + Status = ConvertAslNameToAmlName (LinkName, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + // AmlNameString will be freed be fore returning. + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + DataNode = NULL; + } else { + Status = AmlCodeGenInteger (0, &NewElementNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)NewElementNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + } + + Status = AmlCodeGenInteger (SourceIndex, &NewElementNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)NewElementNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + // Append to the list of _PRT entries. + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PrtEntryList, + (AML_NODE_HANDLE)PackageNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + // Free AmlNameString before returning as it is copied + // in the call to AmlCreateDataNode(). + goto exit_handler; + +error_handler: + AmlDeleteTree ((AML_NODE_HANDLE)PackageNode); + if (NewElementNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)NewElementNode); + } + + if (DataNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)DataNode); + } + +exit_handler: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a Device object node. + + AmlCodeGenDevice ("COM0", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Device(COM0) {} + + @param [in] NameString The new Device's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenDevice ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + if ((NameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + ObjectNode = NULL; + DataNode = NULL; + AmlNameString = NULL; + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_EXT_OP, AML_EXT_DEVICE_OP), + AmlNameStringSize + AmlComputePkgLengthWidth (AmlNameStringSize), + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + goto error_handler2; + } + + Status = LinkNode ( + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // Free AmlNameString before returning as it is copied + // in the call to AmlCreateDataNode(). + goto error_handler1; + +error_handler2: + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + +error_handler1: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a ThermalZone object node. + + AmlCodeGenThermalZone ("TZ00", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + ThermalZone(TZ00) {} + + @ingroup CodeGenApis + + @param [in] NameString The new ThermalZone's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenThermalZone ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + if ((NameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + ObjectNode = NULL; + DataNode = NULL; + AmlNameString = NULL; + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_EXT_OP, AML_EXT_THERMAL_ZONE_OP), + AmlNameStringSize + AmlComputePkgLengthWidth (AmlNameStringSize), + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + goto error_handler2; + } + + Status = LinkNode ( + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // Free AmlNameString before returning as it is copied + // in the call to AmlCreateDataNode(). + goto error_handler1; + +error_handler2: + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + +error_handler1: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a Scope object node. + + AmlCodeGenScope ("_SB", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Scope(_SB) {} + + @param [in] NameString The new Scope's name. + Must be a NULL-terminated ASL NameString + e.g.: "DEV0", "DV15.DEV0", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenScope ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + if ((NameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + ObjectNode = NULL; + DataNode = NULL; + AmlNameString = NULL; + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_SCOPE_OP, 0), + AmlNameStringSize + AmlComputePkgLengthWidth (AmlNameStringSize), + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + goto error_handler2; + } + + Status = LinkNode ( + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // Free AmlNameString before returning as it is copied + // in the call to AmlCreateDataNode(). + goto error_handler1; + +error_handler2: + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + +error_handler1: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a Method object node. + + AmlCodeGenMethod ("MET0", 1, TRUE, 3, ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Method(MET0, 1, Serialized, 3) {} + + ACPI 6.4, s20.2.5.2 "Named Objects Encoding": + DefMethod := MethodOp PkgLength NameString MethodFlags TermList + MethodOp := 0x14 + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @param [in] NameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenMethod ( + IN CONST CHAR8 *NameString, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + UINT32 PkgLen; + UINT8 Flags; + AML_OBJECT_NODE *ObjectNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + if ((NameString == NULL) || + (NumArgs > 6) || + (SyncLevel > 15) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + ObjectNode = NULL; + DataNode = NULL; + + // ACPI 6.4, s20.2.5.2 "Named Objects Encoding": + // DefMethod := MethodOp PkgLength NameString MethodFlags TermList + // MethodOp := 0x14 + // So: + // 1- Create the NameString + // 2- Compute the size to write in the PkgLen + // 3- Create nodes for the NameString and Method object node + // 4- Set the NameString DataNode as a fixed argument + // 5- Create and link the MethodFlags node + + // 1- Create the NameString + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + // 2- Compute the size to write in the PkgLen + // Add 1 byte (ByteData) for MethodFlags. + Status = AmlComputePkgLength (AmlNameStringSize + 1, &PkgLen); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + // 3- Create nodes for the NameString and Method object node + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_METHOD_OP, 0), + PkgLen, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler1; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // 4- Set the NameString DataNode as a fixed argument + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + DataNode = NULL; + + // 5- Create and link the MethodFlags node + Flags = NumArgs | + (IsSerialized ? BIT3 : 0) | + (SyncLevel << 4); + + Status = AmlCreateDataNode (EAmlNodeDataTypeUInt, &Flags, 1, &DataNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm1, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // Data node is attached so set the pointer to + // NULL to ensure correct error handling. + DataNode = NULL; + + Status = LinkNode ( + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler2; + } + + // Free AmlNameString before returning as it is copied + // in the call to AmlCreateDataNode(). + goto error_handler1; + +error_handler2: + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + + if (DataNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)DataNode); + } + +error_handler1: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a Return object node. + + AmlCodeGenReturn (ReturnNode, ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Return([Content of the ReturnNode]) + + The ACPI 6.3 specification, s20.2.5.3 "Type 1 Opcodes Encoding" states: + DefReturn := ReturnOp ArgObject + ReturnOp := 0xA4 + ArgObject := TermArg => DataRefObject + + Thus, the ReturnNode must be evaluated as a DataRefObject. It can + be a NameString referencing an object. As this CodeGen Api doesn't + do semantic checking, it is strongly advised to check the AML bytecode + generated by this function against an ASL compiler. + + The ReturnNode must be generated inside a Method body scope. + + @param [in] ReturnNode The object returned by the Return ASL statement. + This node is deleted if an error occurs. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + Must be a MethodOp node. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenReturn ( + IN AML_NODE_HEADER *ReturnNode, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + + if ((ReturnNode == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL)) || + ((ParentNode != NULL) && + !AmlNodeCompareOpCode ( + (AML_OBJECT_NODE *)ParentNode, + AML_METHOD_OP, + 0 + ))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode (AML_RETURN_OP, 0), + 0, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = AmlSetFixedArgument ( + ObjectNode, + EAmlParseIndexTerm0, + ReturnNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + ReturnNode = NULL; + + Status = LinkNode ( + ObjectNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + if (ReturnNode != NULL) { + AmlDeleteTree (ReturnNode); + } + + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HEADER *)ObjectNode); + } + + return Status; +} + +/** AML code generation for a Return object node, + returning the object as an input NameString. + + AmlCodeGenReturn ("NAM1", ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Return(NAM1) + + The ACPI 6.3 specification, s20.2.5.3 "Type 1 Opcodes Encoding" states: + DefReturn := ReturnOp ArgObject + ReturnOp := 0xA4 + ArgObject := TermArg => DataRefObject + + Thus, the ReturnNode must be evaluated as a DataRefObject. It can + be a NameString referencing an object. As this CodeGen Api doesn't + do semantic checking, it is strongly advised to check the AML bytecode + generated by this function against an ASL compiler. + + The ReturnNode must be generated inside a Method body scope. + + @param [in] NameString The object referenced by this NameString + is returned by the Return ASL statement. + Must be a NULL-terminated ASL NameString + e.g.: "NAM1", "_SB.NAM1", etc. + The input string is copied. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + Must be a MethodOp node. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenReturnNameString ( + IN CONST CHAR8 *NameString, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + DataNode = NULL; + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler; + } + + // AmlCodeGenReturn() deletes DataNode if error. + Status = AmlCodeGenReturn ( + (AML_NODE_HEADER *)DataNode, + ParentNode, + NewObjectNode + ); + ASSERT_EFI_ERROR (Status); + +exit_handler: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a Return object node, + returning an Integer. + + AmlCodeGenReturn (0), ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Return (0) + + The ACPI 6.3 specification, 20.2.8 "Statement Opcodes Encoding" states: + DefReturn := ReturnOp ArgObject + ReturnOp := 0xA4 + ArgObject := TermArg => DataRefObject + + Thus, the ReturnNode must be evaluated as a DataRefObject. + + The ReturnNode must be generated inside a Method body scope. + + @param [in] Integer The integer is returned by the Return + ASL statement. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + Must be a MethodOp node. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenReturnInteger ( + IN UINT64 Integer, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *IntNode; + + IntNode = NULL; + + Status = AmlCodeGenInteger (Integer, &IntNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // AmlCodeGenReturn() deletes DataNode if error. + Status = AmlCodeGenReturn ( + (AML_NODE_HEADER *)IntNode, + ParentNode, + NewObjectNode + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** AML code generation for a Return object node, + returning the object as an input NameString with a integer argument. + + AmlCodeGenReturn ("NAM1", 6, ParentNode, NewObjectNode) is + equivalent of the following ASL code: + Return(NAM1 (6)) + + The ACPI 6.3 specification, s20.2.5.3 "Type 1 Opcodes Encoding" states: + DefReturn := ReturnOp ArgObject + ReturnOp := 0xA4 + ArgObject := TermArg => DataRefObject + + Thus, the ReturnNode must be evaluated as a DataRefObject. It can + be a NameString referencing an object. As this CodeGen Api doesn't + do semantic checking, it is strongly advised to check the AML bytecode + generated by this function against an ASL compiler. + + The ReturnNode must be generated inside a Method body scope. + + @param [in] NameString The object referenced by this NameString + is returned by the Return ASL statement. + Must be a NULL-terminated ASL NameString + e.g.: "NAM1", "_SB.NAM1", etc. + The input string is copied. + @param [in] Integer Argument to pass to the NameString + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + Must be a MethodOp node. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlCodeGenReturnNameStringIntegerArgument ( + IN CONST CHAR8 *NameString, + IN UINT64 Integer, + IN AML_NODE_HEADER *ParentNode OPTIONAL, + OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_DATA_NODE *DataNode; + AML_OBJECT_NODE *IntNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + AML_OBJECT_NODE *ObjectNode; + + DataNode = NULL; + IntNode = NULL; + ObjectNode = NULL; + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler; + } + + Status = AmlCodeGenInteger (Integer, &IntNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler1; + } + + // AmlCodeGenReturn() deletes DataNode if error. + Status = AmlCodeGenReturn ( + (AML_NODE_HEADER *)DataNode, + ParentNode, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler1; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)ObjectNode, + (AML_NODE_HANDLE)IntNode + ); + if (EFI_ERROR (Status)) { + // ObjectNode is already attached to ParentNode in AmlCodeGenReturn(), + // so no need to free it here, it will be deleted when deleting the + // ParentNode tree + ASSERT (0); + goto exit_handler1; + } + + if (NewObjectNode != 0) { + *NewObjectNode = ObjectNode; + } + + goto exit_handler; + +exit_handler1: + if (IntNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)IntNode); + } + +exit_handler: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation for a method returning a NameString. + + AmlCodeGenMethodRetNameString ( + "MET0", "_CRS", 1, TRUE, 3, ParentNode, NewObjectNode + ); + is equivalent of the following ASL code: + Method(MET0, 1, Serialized, 3) { + Return (_CRS) + } + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @param [in] MethodNameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] ReturnedNameString The name of the object returned by the + method. Optional parameter, can be: + - NULL (ignored). + - A NULL-terminated ASL NameString. + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenMethodRetNameString ( + IN CONST CHAR8 *MethodNameString, + IN CONST CHAR8 *ReturnedNameString OPTIONAL, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE MethodNode; + + if ((MethodNameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // Create a Method named MethodNameString. + Status = AmlCodeGenMethod ( + MethodNameString, + NumArgs, + IsSerialized, + SyncLevel, + NULL, + &MethodNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // Return ReturnedNameString if provided. + if (ReturnedNameString != NULL) { + Status = AmlCodeGenReturnNameString ( + ReturnedNameString, + (AML_NODE_HANDLE)MethodNode, + NULL + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + } + + Status = LinkNode ( + MethodNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + if (MethodNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)MethodNode); + } + + return Status; +} + +/** AML code generation for a method returning a NameString that takes an + integer argument. + + AmlCodeGenMethodRetNameStringIntegerArgument ( + "MET0", "MET1", 1, TRUE, 3, 5, ParentNode, NewObjectNode + ); + is equivalent of the following ASL code: + Method(MET0, 1, Serialized, 3) { + Return (MET1 (5)) + } + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @param [in] MethodNameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] ReturnedNameString The name of the object returned by the + method. Optional parameter, can be: + - NULL (ignored). + - A NULL-terminated ASL NameString. + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] IntegerArgument Argument to pass to the NameString. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenMethodRetNameStringIntegerArgument ( + IN CONST CHAR8 *MethodNameString, + IN CONST CHAR8 *ReturnedNameString OPTIONAL, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN UINT64 IntegerArgument, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE MethodNode; + + if ((MethodNameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // Create a Method named MethodNameString. + Status = AmlCodeGenMethod ( + MethodNameString, + NumArgs, + IsSerialized, + SyncLevel, + NULL, + &MethodNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // Return ReturnedNameString if provided. + if (ReturnedNameString != NULL) { + Status = AmlCodeGenReturnNameStringIntegerArgument ( + ReturnedNameString, + IntegerArgument, + (AML_NODE_HANDLE)MethodNode, + NULL + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + } + + Status = LinkNode ( + MethodNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + if (MethodNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)MethodNode); + } + + return Status; +} + +/** AML code generation for a method returning an Integer. + + AmlCodeGenMethodRetInteger ( + "_CBA", 0, 1, TRUE, 3, ParentNode, NewObjectNode + ); + is equivalent of the following ASL code: + Method(_CBA, 1, Serialized, 3) { + Return (0) + } + + The ASL parameters "ReturnType" and "ParameterTypes" are not asked + in this function. They are optional parameters in ASL. + + @param [in] MethodNameString The new Method's name. + Must be a NULL-terminated ASL NameString + e.g.: "MET0", "_SB.MET0", etc. + The input string is copied. + @param [in] ReturnedInteger The value of the integer returned by the + method. + @param [in] NumArgs Number of arguments. + Must be 0 <= NumArgs <= 6. + @param [in] IsSerialized TRUE is equivalent to Serialized. + FALSE is equivalent to NotSerialized. + Default is NotSerialized in ASL spec. + @param [in] SyncLevel Synchronization level for the method. + Must be 0 <= SyncLevel <= 15. + Default is 0 in ASL. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewObjectNode If success, contains the created node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCodeGenMethodRetInteger ( + IN CONST CHAR8 *MethodNameString, + IN UINT64 ReturnedInteger, + IN UINT8 NumArgs, + IN BOOLEAN IsSerialized, + IN UINT8 SyncLevel, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE MethodNode; + + if ((MethodNameString == NULL) || + ((ParentNode == NULL) && (NewObjectNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // Create a Method named MethodNameString. + Status = AmlCodeGenMethod ( + MethodNameString, + NumArgs, + IsSerialized, + SyncLevel, + NULL, + &MethodNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenReturnInteger ( + ReturnedInteger, + (AML_NODE_HANDLE)MethodNode, + NULL + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + Status = LinkNode ( + MethodNode, + ParentNode, + NewObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + if (MethodNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)MethodNode); + } + + return Status; +} + +/** Create a _LPI name. + + AmlCreateLpiNode ("_LPI", 0, 1, ParentNode, &LpiNode) is + equivalent of the following ASL code: + Name (_LPI, Package ( + 0, // Revision + 1, // LevelId + 0 // Count + )) + + This function doesn't define any LPI state. As shown above, the count + of _LPI state is set to 0. + The AmlAddLpiState () function allows to add LPI states. + + Cf ACPI 6.3 specification, s8.4.4 "Lower Power Idle States". + + @param [in] LpiNameString The new LPI 's object name. + Must be a NULL-terminated ASL NameString + e.g.: "_LPI", "DEV0.PLPI", etc. + The input string is copied. + @param [in] Revision Revision number of the _LPI states. + @param [in] LevelId A platform defined number that identifies the + level of hierarchy of the processor node to + which the LPI states apply. + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewLpiNode If success, contains the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCreateLpiNode ( + IN CONST CHAR8 *LpiNameString, + IN UINT16 Revision, + IN UINT64 LevelId, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewLpiNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE PackageNode; + AML_OBJECT_NODE_HANDLE IntegerNode; + + if ((LpiNameString == NULL) || + ((ParentNode == NULL) && (NewLpiNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + IntegerNode = NULL; + + Status = AmlCodeGenPackage (&PackageNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // Create and attach Revision + Status = AmlCodeGenInteger (Revision, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // Create and attach LevelId + Status = AmlCodeGenInteger (LevelId, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // Create and attach Count. No LPI state is added, so 0. + Status = AmlCodeGenInteger (0, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + Status = AmlCodeGenName (LpiNameString, PackageNode, ParentNode, NewLpiNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + AmlDeleteTree ((AML_NODE_HANDLE)PackageNode); + if (IntegerNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)IntegerNode); + } + + return Status; +} + +/** Add an _LPI state to a LPI node created using AmlCreateLpiNode. + + AmlAddLpiState increments the Count of LPI states in the LPI node by one, + and adds the following package: + Package() { + MinResidency, + WorstCaseWakeLatency, + Flags, + ArchFlags, + ResCntFreq, + EnableParentState, + (GenericRegisterDescriptor != NULL) ? // Entry method. If a + ResourceTemplate(GenericRegisterDescriptor) : // Register is given, + Integer, // use it. Use the + // Integer otherwise. + ResourceTemplate() { // NULL Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // NULL Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "" // NULL State Name + }, + + Cf ACPI 6.3 specification, s8.4.4 "Lower Power Idle States". + + @param [in] MinResidency Minimum Residency. + @param [in] WorstCaseWakeLatency Worst case wake-up latency. + @param [in] Flags Flags. + @param [in] ArchFlags Architectural flags. + @param [in] ResCntFreq Residency Counter Frequency. + @param [in] EnableParentState Enabled Parent State. + @param [in] GenericRegisterDescriptor Entry Method. + If not NULL, use this Register to + describe the entry method address. + @param [in] Integer Entry Method. + If GenericRegisterDescriptor is NULL, + take this value. + @param [in] ResidencyCounterRegister If not NULL, use it to populate the + residency counter register. + @param [in] UsageCounterRegister If not NULL, use it to populate the + usage counter register. + @param [in] StateName If not NULL, use it to populate the + state name. + @param [in] LpiNode Lpi node created with the function + AmlCreateLpiNode to which the new LPI + state is appended. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddLpiState ( + IN UINT32 MinResidency, + IN UINT32 WorstCaseWakeLatency, + IN UINT32 Flags, + IN UINT32 ArchFlags, + IN UINT32 ResCntFreq, + IN UINT32 EnableParentState, + IN EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE *GenericRegisterDescriptor OPTIONAL, + IN UINT64 Integer OPTIONAL, + IN EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE *ResidencyCounterRegister OPTIONAL, + IN EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE *UsageCounterRegister OPTIONAL, + IN CHAR8 *StateName OPTIONAL, + IN AML_OBJECT_NODE_HANDLE LpiNode + ) +{ + EFI_STATUS Status; + AML_DATA_NODE_HANDLE RdNode; + AML_OBJECT_NODE_HANDLE PackageNode; + AML_OBJECT_NODE_HANDLE IntegerNode; + AML_OBJECT_NODE_HANDLE StringNode; + AML_OBJECT_NODE_HANDLE NewLpiPackageNode; + AML_OBJECT_NODE_HANDLE ResourceTemplateNode; + + UINT32 Index; + AML_OBJECT_NODE_HANDLE CountNode; + UINT64 Count; + + if ((LpiNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)LpiNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (LpiNode, AML_NAME_OP, 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + RdNode = 0; + StringNode = NULL; + IntegerNode = NULL; + ResourceTemplateNode = NULL; + + // AmlCreateLpiNode () created a LPI container such as: + // Name (_LPI, Package ( + // 0, // Revision + // 1, // LevelId + // 0 // Count + // )) + // Get the LPI container, a PackageOp object node stored as the 2nd fixed + // argument (i.e. index 1) of LpiNode. + PackageNode = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + LpiNode, + EAmlParseIndexTerm1 + ); + if ((PackageNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PackageNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PackageNode, AML_PACKAGE_OP, 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + CountNode = NULL; + // The third variable argument is the LPI Count node. + for (Index = 0; Index < 3; Index++) { + CountNode = (AML_OBJECT_NODE_HANDLE)AmlGetNextVariableArgument ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)CountNode + ); + if (CountNode == NULL) { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + } + + Status = AmlNodeGetIntegerValue (CountNode, &Count); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlUpdateInteger (CountNode, Count + 1); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlCodeGenPackage (&NewLpiPackageNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + // MinResidency + Status = AmlCodeGenInteger (MinResidency, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // WorstCaseWakeLatency + Status = AmlCodeGenInteger (WorstCaseWakeLatency, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // Flags + Status = AmlCodeGenInteger (Flags, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // ArchFlags + Status = AmlCodeGenInteger (ArchFlags, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // ResCntFreq + Status = AmlCodeGenInteger (ResCntFreq, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // EnableParentState + Status = AmlCodeGenInteger (EnableParentState, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + + // Entry Method + if (GenericRegisterDescriptor != NULL) { + // Entry Method: As a Register resource data + Status = AmlCodeGenResourceTemplate (&ResourceTemplateNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + ResourceTemplateNode = NULL; + goto error_handler; + } + + Status = AmlCodeGenRdRegister ( + GenericRegisterDescriptor->AddressSpaceId, + GenericRegisterDescriptor->RegisterBitWidth, + GenericRegisterDescriptor->RegisterBitOffset, + GenericRegisterDescriptor->Address, + GenericRegisterDescriptor->AccessSize, + NULL, + &RdNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + RdNode = NULL; + goto error_handler; + } + + Status = AmlAppendRdNode (ResourceTemplateNode, RdNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + RdNode = NULL; + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)ResourceTemplateNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + ResourceTemplateNode = NULL; + } else { + // Entry Method: As an integer + Status = AmlCodeGenInteger (Integer, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + IntegerNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + IntegerNode = NULL; + } + + // Residency Counter Register. + Status = AmlCodeGenResourceTemplate (&ResourceTemplateNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + ResourceTemplateNode = NULL; + goto error_handler; + } + + if (ResidencyCounterRegister != NULL) { + Status = AmlCodeGenRdRegister ( + ResidencyCounterRegister->AddressSpaceId, + ResidencyCounterRegister->RegisterBitWidth, + ResidencyCounterRegister->RegisterBitOffset, + ResidencyCounterRegister->Address, + ResidencyCounterRegister->AccessSize, + NULL, + &RdNode + ); + } else { + Status = AmlCodeGenRdRegister ( + EFI_ACPI_6_4_SYSTEM_MEMORY, + 0, + 0, + 0, + 0, + NULL, + &RdNode + ); + } + + if (EFI_ERROR (Status)) { + ASSERT (0); + RdNode = NULL; + goto error_handler; + } + + Status = AmlAppendRdNode (ResourceTemplateNode, RdNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + RdNode = NULL; + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)ResourceTemplateNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + ResourceTemplateNode = NULL; + + // Usage Counter Register. + Status = AmlCodeGenResourceTemplate (&ResourceTemplateNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + ResourceTemplateNode = NULL; + goto error_handler; + } + + if (UsageCounterRegister != NULL) { + Status = AmlCodeGenRdRegister ( + UsageCounterRegister->AddressSpaceId, + UsageCounterRegister->RegisterBitWidth, + UsageCounterRegister->RegisterBitOffset, + UsageCounterRegister->Address, + UsageCounterRegister->AccessSize, + NULL, + &RdNode + ); + } else { + Status = AmlCodeGenRdRegister ( + EFI_ACPI_6_4_SYSTEM_MEMORY, + 0, + 0, + 0, + 0, + NULL, + &RdNode + ); + } + + if (EFI_ERROR (Status)) { + ASSERT (0); + RdNode = NULL; + goto error_handler; + } + + Status = AmlAppendRdNode (ResourceTemplateNode, RdNode); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + RdNode = NULL; + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)ResourceTemplateNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + ResourceTemplateNode = NULL; + + // State name. + if (UsageCounterRegister != NULL) { + Status = AmlCodeGenString (StateName, &StringNode); + } else { + Status = AmlCodeGenString ("", &StringNode); + } + + if (EFI_ERROR (Status)) { + ASSERT (0); + StringNode = NULL; + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewLpiPackageNode, + (AML_NODE_HANDLE)StringNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + StringNode = NULL; + + // Add the new LPI state to the LpiNode. + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)NewLpiPackageNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto error_handler; + } + + return Status; + +error_handler: + if (RdNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)RdNode); + } + + if (NewLpiPackageNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)NewLpiPackageNode); + } + + if (StringNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)StringNode); + } + + if (IntegerNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)IntegerNode); + } + + if (ResourceTemplateNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)ResourceTemplateNode); + } + + return Status; +} + +/** AML code generation for a _DSD device data object. + + AmlAddDeviceDataDescriptorPackage (Uuid, DsdNode, PackageNode) is + equivalent of the following ASL code: + ToUUID(Uuid), + Package () {} + + Cf ACPI 6.4 specification, s6.2.5 "_DSD (Device Specific Data)". + + _DSD (Device Specific Data) Implementation Guide + https://github.com/UEFI/DSD-Guide + Per s3. "'Well-Known _DSD UUIDs and Data Structure Formats'" + If creating a Device Properties data then UUID daffd814-6eba-4d8c-8a91-bc9bbf4aa301 should be used. + + @param [in] Uuid The Uuid of the descriptor to be created + @param [in] DsdNode Node of the DSD Package. + @param [out] PackageNode If success, contains the created package node. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddDeviceDataDescriptorPackage ( + IN CONST EFI_GUID *Uuid, + IN AML_OBJECT_NODE_HANDLE DsdNode, + OUT AML_OBJECT_NODE_HANDLE *PackageNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *UuidNode; + AML_DATA_NODE *UuidDataNode; + AML_OBJECT_NODE_HANDLE DsdEntryList; + + if ((Uuid == NULL) || + (PackageNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)DsdNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (DsdNode, AML_NAME_OP, 0)) || + !AmlNameOpCompareName (DsdNode, "_DSD")) + { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return EFI_INVALID_PARAMETER; + } + + // Get the Package object node of the _DSD node, + // which is the 2nd fixed argument (i.e. index 1). + DsdEntryList = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + DsdNode, + EAmlParseIndexTerm1 + ); + if ((DsdEntryList == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)DsdEntryList) != EAmlNodeObject) || + (!AmlNodeHasOpCode (DsdEntryList, AML_PACKAGE_OP, 0))) + { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return EFI_INVALID_PARAMETER; + } + + *PackageNode = NULL; + UuidDataNode = NULL; + + Status = AmlCodeGenBuffer (NULL, 0, &UuidNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeRaw, + (CONST UINT8 *)Uuid, + sizeof (EFI_GUID), + &UuidDataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)UuidNode, + (AML_NODE_HEADER *)UuidDataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + UuidDataNode = NULL; + + // Append to the list of _DSD entries. + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)DsdEntryList, + (AML_NODE_HANDLE)UuidNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlCodeGenPackage (PackageNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler_detach; + } + + // Append to the list of _DSD entries. + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)DsdEntryList, + (AML_NODE_HANDLE)*PackageNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler_detach; + } + + return Status; + +error_handler_detach: + if (UuidNode != NULL) { + AmlDetachNode ((AML_NODE_HANDLE)UuidNode); + } + +error_handler: + if (UuidNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)UuidNode); + } + + if (*PackageNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)*PackageNode); + *PackageNode = NULL; + } + + if (UuidDataNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)UuidDataNode); + } + + return Status; +} + +/** AML code generation to add a package with a name and value, + to a parent package. + This is useful to build the _DSD package but can be used in other cases. + + AmlAddNameIntegerPackage ("Name", Value, PackageNode) is + equivalent of the following ASL code: + Package (2) {"Name", Value} + + Cf ACPI 6.4 specification, s6.2.5 "_DSD (Device Specific Data)". + + @param [in] Name String to place in first entry of package + @param [in] Value Integer to place in second entry of package + @param [in] PackageNode Package to add new sub package to. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddNameIntegerPackage ( + IN CHAR8 *Name, + IN UINT64 Value, + IN AML_OBJECT_NODE_HANDLE PackageNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *NameNode; + AML_OBJECT_NODE *ValueNode; + AML_OBJECT_NODE *NewPackageNode; + + if ((Name == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PackageNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PackageNode, AML_PACKAGE_OP, 0))) + { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return EFI_INVALID_PARAMETER; + } + + NameNode = NULL; + ValueNode = NULL; + + // The new package entry. + Status = AmlCodeGenPackage (&NewPackageNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlCodeGenString (Name, &NameNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewPackageNode, + (AML_NODE_HANDLE)NameNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + NameNode = NULL; + + Status = AmlCodeGenInteger (Value, &ValueNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)NewPackageNode, + (AML_NODE_HANDLE)ValueNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + ValueNode = NULL; + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)NewPackageNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + return Status; + +error_handler: + if (NewPackageNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)NewPackageNode); + } + + if (NameNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)NameNode); + } + + if (ValueNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)ValueNode); + } + + return Status; +} + +/** Adds a register to the package + + @ingroup CodeGenApis + + @param [in] Register If provided, register that will be added to package. + otherwise NULL register will be added + @param [in] PackageNode Package to add value to + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlAddRegisterToPackage ( + IN EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE *Register OPTIONAL, + IN AML_OBJECT_NODE_HANDLE PackageNode + ) +{ + EFI_STATUS Status; + AML_DATA_NODE_HANDLE RdNode; + AML_OBJECT_NODE_HANDLE ResourceTemplateNode; + + RdNode = NULL; + + Status = AmlCodeGenResourceTemplate (&ResourceTemplateNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (Register != NULL) { + Status = AmlCodeGenRdRegister ( + Register->AddressSpaceId, + Register->RegisterBitWidth, + Register->RegisterBitOffset, + Register->Address, + Register->AccessSize, + NULL, + &RdNode + ); + } else { + Status = AmlCodeGenRdRegister ( + EFI_ACPI_6_4_SYSTEM_MEMORY, + 0, + 0, + 0, + 0, + NULL, + &RdNode + ); + } + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAppendRdNode (ResourceTemplateNode, RdNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + RdNode = NULL; + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)ResourceTemplateNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + return Status; + +error_handler: + if (RdNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)RdNode); + } + + if (ResourceTemplateNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)ResourceTemplateNode); + } + + return Status; +} + +/** Utility function to check if generic address points to NULL + + @param [in] Address Pointer to the Generic address + + @retval TRUE Address is system memory with an Address of 0. + @retval FALSE Address does not point to NULL. +**/ +STATIC +BOOLEAN +EFIAPI +IsNullGenericAddress ( + IN EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE *Address + ) +{ + if ((Address == NULL) || + ((Address->AddressSpaceId == EFI_ACPI_6_4_SYSTEM_MEMORY) && + (Address->Address == 0x0))) + { + return TRUE; + } + + return FALSE; +} + +/** Adds an integer or register to the package + + @ingroup CodeGenApis + + @param [in] Register If provided, register that will be added to package + @param [in] Integer If Register is NULL, integer that will be added to the package + @param [in] PackageNode Package to add value to + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +STATIC +EFI_STATUS +EFIAPI +AmlAddRegisterOrIntegerToPackage ( + IN EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE *Register OPTIONAL, + IN UINT32 Integer, + IN AML_OBJECT_NODE_HANDLE PackageNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE IntegerNode; + + IntegerNode = NULL; + + if (!IsNullGenericAddress (Register)) { + Status = AmlAddRegisterToPackage (Register, PackageNode); + } else { + Status = AmlCodeGenInteger (Integer, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)IntegerNode + ); + } + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + if (IntegerNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)IntegerNode); + } + } + + return Status; +} + +/** Create a _CPC node. + + Creates and optionally adds the following node + Name(_CPC, Package() + { + NumEntries, // Integer + Revision, // Integer + HighestPerformance, // Integer or Buffer (Resource Descriptor) + NominalPerformance, // Integer or Buffer (Resource Descriptor) + LowestNonlinearPerformance, // Integer or Buffer (Resource Descriptor) + LowestPerformance, // Integer or Buffer (Resource Descriptor) + GuaranteedPerformanceRegister, // Buffer (Resource Descriptor) + DesiredPerformanceRegister , // Buffer (Resource Descriptor) + MinimumPerformanceRegister , // Buffer (Resource Descriptor) + MaximumPerformanceRegister , // Buffer (Resource Descriptor) + PerformanceReductionToleranceRegister, // Buffer (Resource Descriptor) + TimeWindowRegister, // Buffer (Resource Descriptor) + CounterWraparoundTime, // Integer or Buffer (Resource Descriptor) + ReferencePerformanceCounterRegister, // Buffer (Resource Descriptor) + DeliveredPerformanceCounterRegister, // Buffer (Resource Descriptor) + PerformanceLimitedRegister, // Buffer (Resource Descriptor) + CPPCEnableRegister // Buffer (Resource Descriptor) + AutonomousSelectionEnable, // Integer or Buffer (Resource Descriptor) + AutonomousActivityWindowRegister, // Buffer (Resource Descriptor) + EnergyPerformancePreferenceRegister, // Buffer (Resource Descriptor) + ReferencePerformance // Integer or Buffer (Resource Descriptor) + LowestFrequency, // Integer or Buffer (Resource Descriptor) + NominalFrequency // Integer or Buffer (Resource Descriptor) + }) + + If resource buffer is NULL then integer will be used. + + Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control) + + @ingroup CodeGenApis + + @param [in] CpcInfo CpcInfo object + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewCpcNode If success and provided, contains the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCreateCpcNode ( + IN AML_CPC_INFO *CpcInfo, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewCpcNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE CpcNode; + AML_OBJECT_NODE_HANDLE CpcPackage; + UINT32 NumberOfEntries; + + if ((CpcInfo == NULL) || + ((ParentNode == NULL) && (NewCpcNode == NULL))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + // Revision 3 per ACPI 6.4 specification + if (CpcInfo->Revision == EFI_ACPI_6_5_AML_CPC_REVISION) { + // NumEntries 23 per ACPI 6.4 specification + NumberOfEntries = 23; + } else { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + /// The following fields are theoretically mandatory, but not supported + /// by some platforms. + /// - PerformanceLimitedRegister + /// - ReferencePerformanceCounterRegister + /// - DeliveredPerformanceCounterRegister + /// Warn if BIT0 in PcdDevelopmentPlatformRelaxations is set, otherwise + /// return an error. + if (IsNullGenericAddress (&CpcInfo->PerformanceLimitedRegister) || + IsNullGenericAddress (&CpcInfo->ReferencePerformanceCounterRegister) || + IsNullGenericAddress (&CpcInfo->DeliveredPerformanceCounterRegister)) + { + if ((PcdGet64 (PcdDevelopmentPlatformRelaxations) & BIT0) != 0) { + DEBUG (( + DEBUG_WARN, + "Missing PerformanceLimited|ReferencePerformanceCounter|" + "DeliveredPerformanceCounter field in _CPC object\n" + )); + } else { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + } + + if ((IsNullGenericAddress (&CpcInfo->HighestPerformanceBuffer) && + (CpcInfo->HighestPerformanceInteger == 0)) || + (IsNullGenericAddress (&CpcInfo->NominalPerformanceBuffer) && + (CpcInfo->NominalPerformanceInteger == 0)) || + (IsNullGenericAddress (&CpcInfo->LowestNonlinearPerformanceBuffer) && + (CpcInfo->LowestNonlinearPerformanceInteger == 0)) || + (IsNullGenericAddress (&CpcInfo->LowestPerformanceBuffer) && + (CpcInfo->LowestPerformanceInteger == 0)) || + IsNullGenericAddress (&CpcInfo->DesiredPerformanceRegister)) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + CpcPackage = NULL; + + Status = AmlCodeGenNamePackage ("_CPC", NULL, &CpcNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Get the Package object node of the _CPC node, + // which is the 2nd fixed argument (i.e. index 1). + CpcPackage = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + CpcNode, + EAmlParseIndexTerm1 + ); + if ((CpcPackage == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)CpcPackage) != EAmlNodeObject) || + (!AmlNodeHasOpCode (CpcPackage, AML_PACKAGE_OP, 0))) + { + ASSERT (0); + Status = EFI_INVALID_PARAMETER; + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + NULL, + NumberOfEntries, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + NULL, + CpcInfo->Revision, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->HighestPerformanceBuffer, + CpcInfo->HighestPerformanceInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->NominalPerformanceBuffer, + CpcInfo->NominalPerformanceInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->LowestNonlinearPerformanceBuffer, + CpcInfo->LowestNonlinearPerformanceInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->LowestPerformanceBuffer, + CpcInfo->LowestPerformanceInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->GuaranteedPerformanceRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->DesiredPerformanceRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->MinimumPerformanceRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->MaximumPerformanceRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->PerformanceReductionToleranceRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->TimeWindowRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->CounterWraparoundTimeBuffer, + CpcInfo->CounterWraparoundTimeInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->ReferencePerformanceCounterRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->DeliveredPerformanceCounterRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->PerformanceLimitedRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->CPPCEnableRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->AutonomousSelectionEnableBuffer, + CpcInfo->AutonomousSelectionEnableInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->AutonomousActivityWindowRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterToPackage (&CpcInfo->EnergyPerformancePreferenceRegister, CpcPackage); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->ReferencePerformanceBuffer, + CpcInfo->ReferencePerformanceInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->LowestFrequencyBuffer, + CpcInfo->LowestFrequencyInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlAddRegisterOrIntegerToPackage ( + &CpcInfo->NominalFrequencyBuffer, + CpcInfo->NominalFrequencyInteger, + CpcPackage + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = LinkNode (CpcNode, ParentNode, NewCpcNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + return Status; + +error_handler: + AmlDeleteTree ((AML_NODE_HANDLE)CpcNode); + return Status; +} + +/** AML code generation to add a NameString to the package in a named node. + + + @param [in] NameString NameString to add + @param [in] NamedNode Node to add the string to the included package. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddNameStringToNamedPackage ( + IN CHAR8 *NameString, + IN AML_OBJECT_NODE_HANDLE NamedNode + ) +{ + EFI_STATUS Status; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + AML_OBJECT_NODE_HANDLE PackageNode; + + DataNode = NULL; + + if ((NamedNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)NamedNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (NamedNode, AML_NAME_OP, 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + PackageNode = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + NamedNode, + EAmlParseIndexTerm1 + ); + if ((PackageNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PackageNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PackageNode, AML_PACKAGE_OP, 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + Status = ConvertAslNameToAmlName (NameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT (0); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT (0); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageNode, + (AML_NODE_HANDLE)DataNode + ); + if (EFI_ERROR (Status)) { + AmlDeleteTree ((AML_NODE_HANDLE)DataNode); + } + +exit_handler: + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** AML code generation to invoke/call another method. + + This method is a subset implementation of MethodInvocation + defined in the ACPI specification 6.5, + section 20.2.5 "Term Objects Encoding". + Added integer, string, ArgObj and LocalObj support. + + Example 1: + AmlCodeGenInvokeMethod ("MET0", 0, NULL, ParentNode); + is equivalent to the following ASL code: + MET0 (); + + Example 2: + AML_METHOD_PARAM Param[4]; + Param[0].Data.Integer = 0x100; + Param[0].Type = AmlMethodParamTypeInteger; + Param[1].Data.Buffer = "TEST"; + Param[1].Type = AmlMethodParamTypeString; + Param[2].Data.Arg = 0; + Param[2].Type = AmlMethodParamTypeArg; + Param[3].Data.Local = 2; + Param[3].Type = AmlMethodParamTypeLocal; + AmlCodeGenInvokeMethod ("MET0", 4, Param, ParentNode); + + is equivalent to the following ASL code: + MET0 (0x100, "TEST", Arg0, Local2); + + Example 3: + AML_METHOD_PARAM Param[2]; + Param[0].Data.Arg = 0; + Param[0].Type = AmlMethodParamTypeArg; + Param[1].Data.Integer = 0x100; + Param[1].Type = AmlMethodParamTypeInteger; + AmlCodeGenMethodRetNameString ("MET2", NULL, 2, TRUE, 0, + ParentNode, &MethodNode); + AmlCodeGenInvokeMethod ("MET3", 2, Param, MethodNode); + + is equivalent to the following ASL code: + Method (MET2, 2, Serialized) + { + MET3 (Arg0, 0x0100) + } + + @param [in] MethodNameString The method name to be called or invoked. + @param [in] NumArgs Number of arguments to be passed, + 0 to 7 are permissible values. + @param [in] Parameters Contains the parameter data. + @param [in] ParentNode The parent node to which the method invocation + nodes are attached. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. + **/ +EFI_STATUS +EFIAPI +AmlCodeGenInvokeMethod ( + IN CONST CHAR8 *MethodNameString, + IN UINT8 NumArgs, + IN AML_METHOD_PARAM *Parameters OPTIONAL, + IN AML_NODE_HANDLE ParentNode + ) +{ + EFI_STATUS Status; + UINT8 Index; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + AML_DATA_NODE *DataNode; + AML_OBJECT_NODE *ObjectNode; + AML_NODE_HANDLE *NodeStream; + + if ((MethodNameString == NULL) || (ParentNode == NULL)) { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + if ((NumArgs > 7) || + ((Parameters == NULL) && (NumArgs > 0))) + { + ASSERT (0); + return EFI_INVALID_PARAMETER; + } + + /// Allocate space to store methodname, object, data node pointers + NodeStream = AllocateZeroPool (sizeof (AML_NODE_HANDLE) * (NumArgs + 1)); + if (NodeStream == NULL) { + ASSERT (0); + return EFI_OUT_OF_RESOURCES; + } + + /// Create a called or invoked method name string. + Status = ConvertAslNameToAmlName (MethodNameString, &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + FreePool (AmlNameString); + goto exit_handler; + } + + DataNode = NULL; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + FreePool (AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + NodeStream[0] = (AML_NODE_HANDLE)DataNode; + + if (Parameters != NULL) { + /// Validate and convert the Parameters to the stream of nodes. + for (Index = 0; Index < NumArgs; Index++) { + ObjectNode = NULL; + switch (Parameters[Index].Type) { + case AmlMethodParamTypeInteger: + Status = AmlCodeGenInteger ( + Parameters[Index].Data.Integer, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + break; + case AmlMethodParamTypeString: + if (Parameters[Index].Data.Buffer == NULL) { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + Status = EFI_INVALID_PARAMETER; + goto exit_handler; + } + + Status = AmlCodeGenString ( + Parameters[Index].Data.Buffer, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + break; + case AmlMethodParamTypeArg: + if (Parameters[Index].Data.Arg > (UINT8)(AML_ARG6 - AML_ARG0)) { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + Status = EFI_INVALID_PARAMETER; + goto exit_handler; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode ( + AML_ARG0 + Parameters[Index].Data.Arg, + 0 + ), + 0, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + break; + case AmlMethodParamTypeLocal: + if (Parameters[Index].Data.Local > (UINT8)(AML_LOCAL7 - AML_LOCAL0)) { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + Status = EFI_INVALID_PARAMETER; + goto exit_handler; + } + + Status = AmlCreateObjectNode ( + AmlGetByteEncodingByOpCode ( + AML_LOCAL0 + Parameters[Index].Data.Local, + 0 + ), + 0, + &ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + break; + default: + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + Status = EFI_INVALID_PARAMETER; + goto exit_handler; + } // switch + + // Link the Object Node in the Node Stream. + NodeStream[Index + 1] = (AML_NODE_HANDLE)ObjectNode; + } // for + } + + /// Index <= NumArgs, because an additional method name was added. + for (Index = 0; Index <= NumArgs; Index++) { + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)ParentNode, + (AML_NODE_HANDLE)NodeStream[Index] + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler_detach; + } + } + + FreePool (NodeStream); + return Status; + +exit_handler_detach: + /// The index contains the last successful node attached. + for ( ; Index > 0; Index--) { + /// Index contains the node number that is failed for AmlVarListAddTail(). + /// Hence, start detaching from the last successful + AmlDetachNode (NodeStream[Index-1]); + } + +exit_handler: + /// Index <= NumArgs, because an additional method name was added. + for (Index = 0; Index <= NumArgs; Index++) { + if (NodeStream[Index] != 0) { + AmlDeleteTree (NodeStream[Index]); + } + } + + FreePool (NodeStream); + return Status; +} + +/** Create a _PSD node. + + Creates and optionally adds the following node + Name(_PSD, Package() + { + NumEntries, // Integer + Revision, // Integer + Domain, // Integer + CoordType, // Integer + NumProc, // Integer + }) + + Cf. ACPI 6.5, s8.4.5.5 _PSD (P-State Dependency) + + @ingroup CodeGenApis + + @param [in] PsdInfo PsdInfo object + @param [in] ParentNode If provided, set ParentNode as the parent + of the node created. + @param [out] NewPsdNode If success and provided, contains the created node. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlCreatePsdNode ( + IN AML_PSD_INFO *PsdInfo, + IN AML_NODE_HANDLE ParentNode OPTIONAL, + OUT AML_OBJECT_NODE_HANDLE *NewPsdNode OPTIONAL + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE PsdNode; + AML_OBJECT_NODE_HANDLE PsdPackage; + AML_OBJECT_NODE_HANDLE IntegerNode; + UINT32 NumberOfEntries; + + if ((PsdInfo == NULL) || + ((ParentNode == NULL) && (NewPsdNode == NULL))) + { + Status = EFI_INVALID_PARAMETER; + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Revision 3 per ACPI 6.5 specification + if (PsdInfo->Revision == EFI_ACPI_6_5_AML_PSD_REVISION) { + // NumEntries 5 per ACPI 6.5 specification + NumberOfEntries = 5; + } else { + Status = EFI_INVALID_PARAMETER; + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (((PsdInfo->CoordType != ACPI_AML_COORD_TYPE_SW_ALL) && + (PsdInfo->CoordType != ACPI_AML_COORD_TYPE_SW_ANY) && + (PsdInfo->CoordType != ACPI_AML_COORD_TYPE_HW_ALL)) || + (PsdInfo->NumProc == 0)) + { + Status = EFI_INVALID_PARAMETER; + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlCodeGenNamePackage ("_PSD", NULL, &PsdNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Get the Package object node of the _PSD node, + // which is the 2nd fixed argument (i.e. index 1). + PsdPackage = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + PsdNode, + EAmlParseIndexTerm1 + ); + if ((PsdPackage == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PsdPackage) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PsdPackage, AML_PACKAGE_OP, 0))) + { + Status = EFI_INVALID_PARAMETER; + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + // NumEntries + Status = AmlCodeGenInteger (NumberOfEntries, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PsdPackage, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + FreePool (IntegerNode); + goto error_handler; + } + + // Revision + Status = AmlCodeGenInteger (PsdInfo->Revision, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PsdPackage, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + FreePool (IntegerNode); + goto error_handler; + } + + // Domain + Status = AmlCodeGenInteger (PsdInfo->Domain, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PsdPackage, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + FreePool (IntegerNode); + goto error_handler; + } + + // CoordType + Status = AmlCodeGenInteger (PsdInfo->CoordType, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PsdPackage, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + FreePool (IntegerNode); + goto error_handler; + } + + // Num Processors + Status = AmlCodeGenInteger (PsdInfo->NumProc, &IntegerNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PsdPackage, + (AML_NODE_HANDLE)IntegerNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + FreePool (IntegerNode); + goto error_handler; + } + + Status = LinkNode (PsdNode, ParentNode, NewPsdNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + + return Status; + +error_handler: + AmlDeleteTree ((AML_NODE_HANDLE)PsdNode); + return Status; +} + +/** Create a _OST method for AMD platform. + + Method (_OST, 3, Serialized) + { + \_SB.host (Arg0, Arg1, BRB, _ADR) + } + + @ingroup CodeGenApis + + @param [in] DeviceNode DeviceNode object + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_STATUS Other failure +**/ +EFI_STATUS +EFIAPI +AmdAmlCodeGenMethodInvokeMethodOst ( + IN OUT AML_OBJECT_NODE_HANDLE DeviceNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE MethodNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + // Create a Method named MethodNameString + Status = AmlCodeGenMethod ( + "_OST", + 3, + TRUE, + 0, + NULL, + &MethodNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DataNode = NULL; + + Status = ConvertAslNameToAmlName ("\\_SB.HOST", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG0; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG1; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + Status = ConvertAslNameToAmlName ("BRB", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + Status = ConvertAslNameToAmlName ("_ADR", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + Status = AmlVarListAddTail ((AML_NODE_HEADER *)DeviceNode, (AML_NODE_HEADER *)MethodNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + return Status; + +exit_handler: + if (MethodNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)MethodNode); + } + + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** Create a _DSM method for AMD platform. + + Method (_DSM, 4, Serialized) + { + \_SB.HDSM (Arg0, Arg1, Arg2, Arg3, BRB, _ADR, RSTR) + } + + @ingroup CodeGenApis + + @param [in] DeviceNode DeviceNode object + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_STATUS Other failure +**/ +EFI_STATUS +EFIAPI +AmdAmlCodeGenMethodInvokeMethodDsm ( + IN OUT AML_OBJECT_NODE_HANDLE DeviceNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE MethodNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + // Create a Method named MethodNameString + Status = AmlCodeGenMethod ( + "_DSM", + 4, + TRUE, + 0, + NULL, + &MethodNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DataNode = NULL; + + Status = ConvertAslNameToAmlName ("\\_SB.HDSM", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG0; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG1; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG2; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG3; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + Status = ConvertAslNameToAmlName ("BRB", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + Status = ConvertAslNameToAmlName ("_ADR", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + Status = ConvertAslNameToAmlName ("RSTR", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + Status = AmlVarListAddTail ((AML_NODE_HEADER *)DeviceNode, (AML_NODE_HEADER *)MethodNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + return Status; + +exit_handler: + if (MethodNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)MethodNode); + } + + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** Create a _OSC method for AMD platform. + + Method (_OSC, 4, NotSerialized, 4) // _OSC: Operating System Capabilities + { + Return (\_SB.OSCI (Arg0, Arg1, Arg2, Arg3)) + } + + @ingroup CodeGenApis + + @param [in] DeviceNode DeviceNode object + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_STATUS Other failure +**/ +EFI_STATUS +EFIAPI +AmdAmlCodeGenMethodInvokeMethodOsc ( + IN OUT AML_OBJECT_NODE_HANDLE DeviceNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE_HANDLE MethodNode; + AML_DATA_NODE *DataNode; + CHAR8 *AmlNameString; + UINT32 AmlNameStringSize; + + // Create a Method named MethodNameString + Status = AmlCodeGenMethod ( + "_OSC", + 4, + FALSE, + 4, + NULL, + &MethodNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DataNode = NULL; + + Status = ConvertAslNameToAmlName ("\\_SB.OSCI", &AmlNameString); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlGetNameStringSize (AmlNameString, &AmlNameStringSize); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlCreateDataNode ( + EAmlNodeDataTypeNameString, + (UINT8 *)AmlNameString, + AmlNameStringSize, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG0; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG1; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG2; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + DataNode = NULL; + + AmlNameStringSize = AML_ARG3; + Status = AmlCreateDataNode ( + EAmlNodeDataTypeUInt, + (UINT8 *)&AmlNameStringSize, + 1, + &DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HEADER *)MethodNode, + (AML_NODE_HEADER *)DataNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + Status = AmlVarListAddTail ((AML_NODE_HEADER *)DeviceNode, (AML_NODE_HEADER *)MethodNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + + return Status; + +exit_handler: + if (MethodNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)MethodNode); + } + + if (AmlNameString != NULL) { + FreePool (AmlNameString); + } + + return Status; +} + +/** Add an integer value to Package node. + + AmlCodeGenNamePackage ("_CID", NULL, &PackageNode); + AmlGetEisaIdFromString ("PNP0A03", &EisaId); + AmlAddIntegerPackageEntry (EisaId, PackageNameNode); + AmlGetEisaIdFromString ("PNP0A08", &EisaId); + AmlAddIntegerPackageEntry (EisaId, PackageNameNode); + + equivalent of the following ASL code: + Name (_CID, Package (0x02) // _CID: Compatible ID + { + EisaId ("PNP0A03"), + EisaId ("PNP0A08") + }) + + The package is added at the tail of the list of the input package node + name: + Name ("NamePackageNode", Package () { + [Pre-existing package entries], + [Newly created integer entry] + }) + + + @ingroup CodeGenApis + + @param [in] Integer Integer value that need to be added to package node. + @param [in] PackageNameNode Prt Named node to add the object to .... + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_OUT_OF_RESOURCES Failed to allocate memory. +**/ +EFI_STATUS +EFIAPI +AmlAddIntegerPackageEntry ( + IN UINT64 Integer, + IN AML_OBJECT_NODE_HANDLE PackageNameNode + ) +{ + EFI_STATUS Status; + AML_OBJECT_NODE *ObjectNode; + AML_OBJECT_NODE *PackageEntryList; + + if (PackageNameNode == NULL) + { + ASSERT_EFI_ERROR (FALSE); + return EFI_INVALID_PARAMETER; + } + + if ((PackageNameNode == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PackageNameNode) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PackageNameNode, AML_NAME_OP, 0))) + { + ASSERT_EFI_ERROR (FALSE); + return EFI_INVALID_PARAMETER; + } + + PackageEntryList = (AML_OBJECT_NODE_HANDLE)AmlGetFixedArgument ( + PackageNameNode, + EAmlParseIndexTerm1 + ); + if ((PackageEntryList == NULL) || + (AmlGetNodeType ((AML_NODE_HANDLE)PackageEntryList) != EAmlNodeObject) || + (!AmlNodeHasOpCode (PackageEntryList, AML_PACKAGE_OP, 0))) + { + ASSERT_EFI_ERROR (FALSE); + return EFI_INVALID_PARAMETER; + } + + Status = AmlCodeGenInteger (Integer, &ObjectNode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = AmlVarListAddTail ( + (AML_NODE_HANDLE)PackageEntryList, + (AML_NODE_HANDLE)ObjectNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + goto error_handler; + } + return Status; + +error_handler: + if (ObjectNode != NULL) { + AmlDeleteTree ((AML_NODE_HANDLE)ObjectNode); + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.c new file mode 100644 index 0000000000000000000000000000000000000000..ef5be95d91358b17f0a91fca42551e191a58ff2b --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.c @@ -0,0 +1,434 @@ +/** @file + + SpiBus driver + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include "SpiBus.h" + +/** + Checks if two device paths are the same + + @param DevicePath1 First device path to compare + @param DevicePath2 Second device path to compare + + @retval TRUE The device paths share the same nodes and values + @retval FALSE The device paths differ +**/ +BOOLEAN +EFIAPI +DevicePathsAreEqual ( + IN const EFI_DEVICE_PATH_PROTOCOL *DevicePath1, + IN const EFI_DEVICE_PATH_PROTOCOL *DevicePath2 + ) +{ + UINTN Size1; + UINTN Size2; + + Size1 = GetDevicePathSize (DevicePath1); + Size2 = GetDevicePathSize (DevicePath2); + + if (Size1 != Size2) { + return FALSE; + } + + if (CompareMem (DevicePath1, DevicePath2, Size1) != 0) { + return FALSE; + } + + return TRUE; +} + +/** + Calls the SpiPeripherals ChipSelect if it is not null, otherwise + calls the Host Controllers ChipSelect function + + @param SpiChip The SpiChip to place on the bus via asserting its chip select + @param PinValue Value to place on the chip select pin + + @retval EFI_SUCCESS Chip select pin was placed at requested level + @retval EFI_INVALID_PARAMETER Invalid parameters passed into ChipSelect function +**/ +EFI_STATUS +EFIAPI +SpiChipSelect ( + IN CONST SPI_IO_CHIP *SpiChip, + IN BOOLEAN PinValue + ) +{ + EFI_STATUS Status; + + // Check which chip select function to use + if (SpiChip->Protocol.SpiPeripheral->ChipSelect != NULL) { + Status = SpiChip->Protocol.SpiPeripheral->ChipSelect ( + SpiChip->BusTransaction.SpiPeripheral, + PinValue + ); + } else { + Status = SpiChip->SpiHc->ChipSelect ( + SpiChip->SpiHc, + SpiChip->BusTransaction.SpiPeripheral, + PinValue + ); + } + + return Status; +} + +/** + Checks the SpiChip's BusTransaction attributes to ensure its a valid SPI transaction + + @param SpiChip The SpiChip to place on the bus via asserting its chip select + @param PinValue Value to place on the chip select pin + + @retval EFI_SUCCESS This is a valid SPI bus transaction + @retval EFI_BAD_BUFFER_SIZE The WriteBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support +**/ +EFI_STATUS +EFIAPI +IsValidSpiTransaction ( + IN SPI_IO_CHIP *SpiChip + ) +{ + // Error checking + if (SpiChip->BusTransaction.TransactionType > SPI_TRANSACTION_WRITE_THEN_READ) { + return EFI_INVALID_PARAMETER; + } + + if (((SpiChip->BusTransaction.BusWidth != 1) && (SpiChip->BusTransaction.BusWidth != 2) && (SpiChip->BusTransaction.BusWidth != 4) && + (SpiChip->BusTransaction.BusWidth != 8)) || (SpiChip->BusTransaction.FrameSize == 0)) + { + return EFI_INVALID_PARAMETER; + } + + if ((SpiChip->BusTransaction.BusWidth == 8) && (((SpiChip->Protocol.Attributes & SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH) != SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH) || + ((SpiChip->BusTransaction.SpiPeripheral->Attributes & SPl_PART_SUPPORTS_8_B1T_DATA_BUS_WIDTH) != SPl_PART_SUPPORTS_8_B1T_DATA_BUS_WIDTH))) + { + return EFI_INVALID_PARAMETER; + } else if ((SpiChip->BusTransaction.BusWidth == 4) && (((SpiChip->Protocol.Attributes & SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH) != SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH) || + ((SpiChip->BusTransaction.SpiPeripheral->Attributes & SPl_PART_SUPPORTS_4_B1T_DATA_BUS_WIDTH) != SPl_PART_SUPPORTS_4_B1T_DATA_BUS_WIDTH))) + { + return EFI_INVALID_PARAMETER; + } else if ((SpiChip->BusTransaction.BusWidth == 2) && (((SpiChip->Protocol.Attributes & SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH) != SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH) || + ((SpiChip->BusTransaction.SpiPeripheral->Attributes & SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH) != SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH))) + { + return EFI_INVALID_PARAMETER; + } + + if (((SpiChip->BusTransaction.WriteBytes > 0) && (SpiChip->BusTransaction.WriteBuffer == NULL)) || ((SpiChip->BusTransaction.ReadBytes > 0) && (SpiChip->BusTransaction.ReadBuffer == NULL))) { + return EFI_INVALID_PARAMETER; + } + + if ((SpiChip->BusTransaction.TransactionType == SPI_TRANSACTION_FULL_DUPLEX) && (SpiChip->BusTransaction.ReadBytes != SpiChip->BusTransaction.WriteBytes)) { + return EFI_INVALID_PARAMETER; + } + + // Check frame size, passed parameter is in bits + if ((SpiChip->Protocol.FrameSizeSupportMask & (1<<(SpiChip->BusTransaction.FrameSize-1))) == 0) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Initiate a SPI transaction between the host and a SPI peripheral. + + This routine must be called at or below TPL_NOTIFY. + This routine works with the SPI bus layer to pass the SPI transaction to the + SPI controller for execution on the SPI bus. There are four types of + supported transactions supported by this routine: + * Full Duplex: WriteBuffer and ReadBuffer are the same size. + * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0 + * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0 + * Write Then Read: WriteBuffer contains control data to write to SPI + peripheral before data is placed into the ReadBuffer. + Both WriteBytes and ReadBytes must be non-zero. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] TransactionType Type of SPI transaction. + @param[in] DebugTransaction Set TRUE only when debugging is desired. + Debugging may be turned on for a single SPI + transaction. Only this transaction will display + debugging messages. All other transactions with + this value set to FALSE will not display any + debugging messages. + @param[in] ClockHz Specify the ClockHz value as zero (0) to use + the maximum clock frequency supported by the + SPI controller and part. Specify a non-zero + value only when a specific SPI transaction + requires a reduced clock rate. + @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4 + @param[in] FrameSize Frame size in bits, range: 1 - 32 + @param[in] WriteBytes The length of the WriteBuffer in bytes. + Specify zero for read-only operations. + @param[in] WriteBuffer The buffer containing data to be sent from the + host to the SPI chip. Specify NULL for read + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The transmit frame is in the least + significant N bits. + @param[in] ReadBytes The length of the ReadBuffer in bytes. + Specify zero for write-only operations. + @param[out] ReadBuffer The buffer to receeive data from the SPI chip + during the transaction. Specify NULL for write + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The received frame is in the least + significant N bits. + + @retval EFI_SUCCESS The SPI transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The WriteBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN EFI_SPI_TRANSACTION_TYPE TransactionType, + IN BOOLEAN DebugTransaction, + IN UINT32 ClockHz OPTIONAL, + IN UINT32 BusWidth, + IN UINT32 FrameSize, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT32 ReadBytes, + OUT UINT8 *ReadBuffer + ) +{ + EFI_STATUS Status; + SPI_IO_CHIP *SpiChip; + UINT32 MaxClockHz; + UINT8 *DummyReadBuffer; + UINT8 *DummyWriteBuffer; + + SpiChip = SPI_IO_CHIP_FROM_THIS (This); + SpiChip->BusTransaction.SpiPeripheral = + (EFI_SPI_PERIPHERAL *)SpiChip->Protocol.SpiPeripheral; + SpiChip->BusTransaction.TransactionType = TransactionType; + SpiChip->BusTransaction.DebugTransaction = DebugTransaction; + SpiChip->BusTransaction.BusWidth = BusWidth; + SpiChip->BusTransaction.FrameSize = FrameSize; + SpiChip->BusTransaction.WriteBytes = WriteBytes; + SpiChip->BusTransaction.WriteBuffer = WriteBuffer; + SpiChip->BusTransaction.ReadBytes = ReadBytes; + SpiChip->BusTransaction.ReadBuffer = ReadBuffer; + + // Ensure valid spi transaction parameters + Status = IsValidSpiTransaction (SpiChip); + if (EFI_ERROR (Status)) { + return Status; + } + + // Setup the proper clock frequency + if (SpiChip->BusTransaction.SpiPeripheral->MaxClockHz != 0) { + MaxClockHz = SpiChip->BusTransaction.SpiPeripheral->MaxClockHz; + } else { + MaxClockHz = SpiChip->BusTransaction.SpiPeripheral->SpiPart->MaxClockHz; + } + + // Call proper clock function + if (SpiChip->Protocol.SpiPeripheral->SpiBus->Clock != NULL) { + Status = SpiChip->Protocol.SpiPeripheral->SpiBus->Clock ( + SpiChip->BusTransaction.SpiPeripheral, + &MaxClockHz + ); + } else { + Status = SpiChip->SpiHc->Clock ( + SpiChip->SpiHc, + SpiChip->BusTransaction.SpiPeripheral, + &MaxClockHz + ); + } + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = SpiChipSelect (SpiChip, SpiChip->BusTransaction.SpiPeripheral->SpiPart->ChipSelectPolarity); + + if (EFI_ERROR (Status)) { + return Status; + } + + // Check transaction types and match to HC capabilities + if ((TransactionType == SPI_TRANSACTION_WRITE_ONLY) && + ((SpiChip->SpiHc->Attributes & HC_SUPPORTS_WRITE_ONLY_OPERATIONS) != HC_SUPPORTS_WRITE_ONLY_OPERATIONS)) + { + // Convert to full duplex transaction + SpiChip->BusTransaction.ReadBytes = SpiChip->BusTransaction.WriteBytes; + SpiChip->BusTransaction.ReadBuffer = AllocateZeroPool (SpiChip->BusTransaction.ReadBytes); + + Status = SpiChip->SpiHc->Transaction ( + SpiChip->SpiHc, + &SpiChip->BusTransaction + ); + + SpiChip->BusTransaction.ReadBytes = ReadBytes; // assign to passed parameter + FreePool (SpiChip->BusTransaction.ReadBuffer); // Free temporary buffer + } else if ((TransactionType == SPI_TRANSACTION_READ_ONLY) && + ((SpiChip->SpiHc->Attributes & HC_SUPPORTS_READ_ONLY_OPERATIONS) != HC_SUPPORTS_READ_ONLY_OPERATIONS)) + { + // Convert to full duplex transaction + SpiChip->BusTransaction.WriteBytes = SpiChip->BusTransaction.WriteBytes; + SpiChip->BusTransaction.WriteBuffer = AllocateZeroPool (SpiChip->BusTransaction.WriteBytes); + + Status = SpiChip->SpiHc->Transaction ( + SpiChip->SpiHc, + &SpiChip->BusTransaction + ); + + SpiChip->BusTransaction.WriteBytes = WriteBytes; + FreePool (SpiChip->BusTransaction.WriteBuffer); + } else if ((TransactionType == SPI_TRANSACTION_WRITE_THEN_READ) && + ((SpiChip->SpiHc->Attributes & HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS) != HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS)) + { + // Convert to full duplex transaction + DummyReadBuffer = AllocateZeroPool (WriteBytes); + DummyWriteBuffer = AllocateZeroPool (ReadBytes); + SpiChip->BusTransaction.ReadBuffer = DummyReadBuffer; + SpiChip->BusTransaction.ReadBytes = WriteBytes; + + Status = SpiChip->SpiHc->Transaction ( + SpiChip->SpiHc, + &SpiChip->BusTransaction + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + // Write is done, now need to read, restore passed in read buffer info + SpiChip->BusTransaction.ReadBuffer = ReadBuffer; + SpiChip->BusTransaction.ReadBytes = ReadBytes; + + SpiChip->BusTransaction.WriteBuffer = DummyWriteBuffer; + SpiChip->BusTransaction.WriteBytes = ReadBytes; + + Status = SpiChip->SpiHc->Transaction ( + SpiChip->SpiHc, + &SpiChip->BusTransaction + ); + // Restore write data + SpiChip->BusTransaction.WriteBuffer = WriteBuffer; + SpiChip->BusTransaction.WriteBytes = WriteBytes; + + FreePool (DummyReadBuffer); + FreePool (DummyWriteBuffer); + } else { + // Supported transaction type, just pass info the SPI HC Protocol Transaction + Status = SpiChip->SpiHc->Transaction ( + SpiChip->SpiHc, + &SpiChip->BusTransaction + ); + } + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = SpiChipSelect (SpiChip, !SpiChip->BusTransaction.SpiPeripheral->SpiPart->ChipSelectPolarity); + + return Status; +} + +/** + Update the SPI peripheral associated with this SPI 10 SpiChip. + + Support socketed SPI parts by allowing the SPI peripheral driver to replace + the SPI peripheral after the connection is made. An example use is socketed + SPI NOR flash parts, where the size and parameters change depending upon + device is in the socket. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure. + + @retval EFI_SUCCESS The SPI peripheral was updated successfully + @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL, + or the SpiPeripheral->SpiBus is NULL, + or the SpiPeripheral->SpiBus pointing at + wrong bus, or the SpiPeripheral->SpiPart is NULL +**/ +EFI_STATUS +EFIAPI +UpdateSpiPeripheral ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral + ) +{ + EFI_STATUS Status; + SPI_IO_CHIP *SpiChip; + + DEBUG ((DEBUG_VERBOSE, "%a: SPI Bus - Entry\n", __func__)); + + SpiChip = SPI_IO_CHIP_FROM_THIS (This); + + if ((SpiPeripheral == NULL) || (SpiPeripheral->SpiBus == NULL) || + (SpiPeripheral->SpiPart == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + // EFI_INVALID_PARAMETER if SpiPeripheral->SpiBus is pointing at wrong bus + if (!DevicePathsAreEqual (SpiPeripheral->SpiBus->ControllerPath, SpiChip->SpiBus->ControllerPath)) { + return EFI_INVALID_PARAMETER; + } + + SpiChip->Protocol.OriginalSpiPeripheral = SpiChip->Protocol.SpiPeripheral; + SpiChip->Protocol.SpiPeripheral = SpiPeripheral; + + Status = EFI_SUCCESS; + DEBUG (( + DEBUG_VERBOSE, + "%a: SPI Bus - Exit Status=%r\n", + __func__, + Status + )); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.h new file mode 100644 index 0000000000000000000000000000000000000000..8d1a72742feff54bd845e9973fff4a484e2430f4 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.h @@ -0,0 +1,167 @@ +/** @file + + SPI bus driver + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_BUS_H_ +#define SPI_BUS_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPI_IO_SIGNATURE SIGNATURE_32 ('s', 'i', 'o', 'c') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SPI_IO_PROTOCOL Protocol; + EFI_SPI_BUS_TRANSACTION BusTransaction; + EFI_SPI_CONFIGURATION_PROTOCOL *SpiConfig; + EFI_SPI_HC_PROTOCOL *SpiHc; + EFI_SPI_BUS *SpiBus; +} SPI_IO_CHIP; + +#define SPI_IO_CHIP_FROM_THIS(a) \ + CR (a, SPI_IO_CHIP, Protocol, \ + SPI_IO_SIGNATURE) + +/** + Checks if two device paths are the same + + @param DevicePath1 First device path to compare + @param DevicePath2 Second device path to compare + + @retval TRUE The device paths share the same nodes and values + @retval FALSE The device paths differ +**/ +BOOLEAN +EFIAPI +DevicePathsAreEqual ( + IN const EFI_DEVICE_PATH_PROTOCOL *DevicePath1, + IN const EFI_DEVICE_PATH_PROTOCOL *DevicePath2 + ); + +/** + Initiate a SPI transaction between the host and a SPI peripheral. + + This routine must be called at or below TPL_NOTIFY. + This routine works with the SPI bus layer to pass the SPI transaction to the + SPI controller for execution on the SPI bus. There are four types of + supported transactions supported by this routine: + * Full Duplex: WriteBuffer and ReadBuffer are the same size. + * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0 + * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0 + * Write Then Read: WriteBuffer contains control data to write to SPI + peripheral before data is placed into the ReadBuffer. + Both WriteBytes and ReadBytes must be non-zero. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] TransactionType Type of SPI transaction. + @param[in] DebugTransaction Set TRUE only when debugging is desired. + Debugging may be turned on for a single SPI + transaction. Only this transaction will display + debugging messages. All other transactions with + this value set to FALSE will not display any + debugging messages. + @param[in] ClockHz Specify the ClockHz value as zero (0) to use + the maximum clock frequency supported by the + SPI controller and part. Specify a non-zero + value only when a specific SPI transaction + requires a reduced clock rate. + @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4 + @param[in] FrameSize Frame size in bits, range: 1 - 32 + @param[in] WriteBytes The length of the WriteBuffer in bytes. + Specify zero for read-only operations. + @param[in] WriteBuffer The buffer containing data to be sent from the + host to the SPI chip. Specify NULL for read + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The transmit frame is in the least + significant N bits. + @param[in] ReadBytes The length of the ReadBuffer in bytes. + Specify zero for write-only operations. + @param[out] ReadBuffer The buffer to receeive data from the SPI chip + during the transaction. Specify NULL for write + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The received frame is in the least + significant N bits. + + @retval EFI_SUCCESS The SPI transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The writeBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN EFI_SPI_TRANSACTION_TYPE TransactionType, + IN BOOLEAN DebugTransaction, + IN UINT32 ClockHz OPTIONAL, + IN UINT32 BusWidth, + IN UINT32 FrameSize, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT32 ReadBytes, + OUT UINT8 *ReadBuffer + ); + +/** + Update the SPI peripheral associated with this SPI 10 instance. + + Support socketed SPI parts by allowing the SPI peripheral driver to replace + the SPI peripheral after the connection is made. An example use is socketed + SPI NOR flash parts, where the size and parameters change depending upon + device is in the socket. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure. + + @retval EFI_SUCCESS The SPI peripheral was updated successfully + @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL, + or the SpiPeripheral->SpiBus is NULL, + or the SpiPeripheral->SpiBus pointing at + wrong bus, or the SpiPeripheral->SpiPart is NULL + +**/ +EFI_STATUS +EFIAPI +UpdateSpiPeripheral ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral + ); + +#endif //SPI_BUS_H_ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.uni b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.uni new file mode 100644 index 0000000000000000000000000000000000000000..e508bb2ec1b3f35dbfdf88f1d5503a020c531b3f --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBus.uni @@ -0,0 +1,10 @@ +// /** @file +// +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "SPI Bus driver" diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..8a2b4076a44dd1007128d1b5d6a8f8c99b5c3164 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.c @@ -0,0 +1,197 @@ +/** @file + + SPI bus DXE driver + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiBus.h" + +/** + Entry point of the Spi Bus layer + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_DEVICE_ERROR Fail to install EFI_SPI_HC_PROTOCOL protocol. + @retval EFI_NOT_FOUND fail to locate SpiHcProtocol or SpiIoConfigurationProtocol +**/ +EFI_STATUS +EFIAPI +SpiBusEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SPI_IO_CHIP *SpiChip; + EFI_SPI_HC_PROTOCOL *SpiHc; + EFI_SPI_CONFIGURATION_PROTOCOL *SpiConfiguration; + EFI_SPI_PERIPHERAL *SpiPeripheral; + EFI_SPI_BUS *Bus; + UINTN BusIndex; + UINTN HcIndex; + EFI_HANDLE *SpiHcHandles; + UINTN HandleCount; + EFI_DEVICE_PATH_PROTOCOL *SpiHcDevicePath; + + DEBUG ((DEBUG_VERBOSE, "%a - ENTRY\n", __func__)); + + // Get all SPI HC protocols, could be multiple SPI HC's on a single platform + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSpiHcProtocolGuid, + NULL, + &HandleCount, + &SpiHcHandles + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "No SpiHcProtocol is found\n")); + Status = EFI_NOT_FOUND; + goto Exit; + } + + // Locate the SPI Configuration Protocol + Status = gBS->LocateProtocol ( + &gEfiSpiConfigurationProtocolGuid, + NULL, + (VOID **)&SpiConfiguration + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "No SpiConfigurationProtocol is found\n")); + Status = EFI_NOT_FOUND; + goto Exit; + } + + // Parse through Hc protocols, find correct device path + for (HcIndex = 0; HcIndex < HandleCount; HcIndex++) { + Status = gBS->HandleProtocol ( + SpiHcHandles[HcIndex], + &gEfiDevicePathProtocolGuid, + (VOID **)&SpiHcDevicePath + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error locating EFI device path for this SPI controller, status=%r \n", Status)); + continue; // Continue searching + } + + // Parse through SpiConfiguration's SpiBuses, find matching devicepath for SpiHc + for (BusIndex = 0; BusIndex < SpiConfiguration->BusCount; BusIndex++) { + Bus = (EFI_SPI_BUS *)SpiConfiguration->Buslist[BusIndex]; + if (!DevicePathsAreEqual (SpiHcDevicePath, Bus->ControllerPath)) { + DEBUG ((DEBUG_VERBOSE, "SpiHc and SpiConfig device paths dont match, continue parsing\n")); + continue; + } + + DEBUG (( + DEBUG_VERBOSE, + "%a: Found matching device paths, Enumerating SPI BUS: %s with DevicePath: %s\n", + __func__, + Bus->FriendlyName, + ConvertDevicePathToText (SpiHcDevicePath, FALSE, FALSE) + )); + + // Get SpiHc from the SpiHcHandles + Status = gBS->HandleProtocol ( + SpiHcHandles[HcIndex], + &gEfiDevicePathProtocolGuid, + (VOID **)&SpiHc + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "%a - Error getting SpiHc from Handle\n", __func__)); + goto Exit; + } + + SpiPeripheral = (EFI_SPI_PERIPHERAL *)Bus->Peripherallist; + if (SpiPeripheral != NULL) { + do { + DEBUG (( + DEBUG_VERBOSE, + "%a: Installing SPI IO protocol for %s, by %s, PN=%s\n", + __func__, + SpiPeripheral->FriendlyName, + SpiPeripheral->SpiPart->Vendor, + SpiPeripheral->SpiPart->PartNumber + )); + // Allocate the SPI IO Device + SpiChip = AllocateZeroPool (sizeof (SPI_IO_CHIP)); + ASSERT (SpiChip != NULL); + if (SpiChip != NULL) { + // Fill in the SpiChip + SpiChip->Signature = SPI_IO_SIGNATURE; + SpiChip->SpiConfig = SpiConfiguration; + SpiChip->SpiHc = SpiHc; + SpiChip->SpiBus = Bus; + SpiChip->Protocol.SpiPeripheral = SpiPeripheral; + SpiChip->Protocol.OriginalSpiPeripheral = SpiPeripheral; + SpiChip->Protocol.FrameSizeSupportMask = SpiHc->FrameSizeSupportMask; + SpiChip->Protocol.MaximumTransferBytes = SpiHc->MaximumTransferBytes; + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_ADDRESS) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS; + } + + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_OPCODE) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE; + } + + if ((SpiHc->Attributes & HC_SUPPORTS_8_BIT_DATA_BUS_WIDTH) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH; + } + + if ((SpiHc->Attributes & HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH; + } + + if ((SpiHc->Attributes & HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH; + } + + SpiChip->Protocol.Transaction = Transaction; + SpiChip->Protocol.UpdateSpiPeripheral = UpdateSpiPeripheral; + // Install the SPI IO Protocol + Status = gBS->InstallProtocolInterface ( + &SpiChip->Handle, + (GUID *)SpiPeripheral->SpiPeripheralDriverGuid, + EFI_NATIVE_INTERFACE, + &SpiChip->Protocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "%a - Error installing SpiIoProtocol\n", __func__)); + continue; + } + } else { + Status = EFI_OUT_OF_RESOURCES; + DEBUG (( + DEBUG_ERROR, + "%a: Out of Memory resources\n", + __func__ + )); + break; + } + + SpiPeripheral = (EFI_SPI_PERIPHERAL *)SpiPeripheral->NextSpiPeripheral; + } while (SpiPeripheral != NULL); + } else { + Status = EFI_DEVICE_ERROR; + } + } + } + +Exit: + DEBUG ((DEBUG_VERBOSE, "%a - EXIT (Status = %r)\n", __func__, Status)); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..84dec6bc59f31b8e77c7d1358ee2cf2af4b8ec6b --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf @@ -0,0 +1,42 @@ +#/** @file +# +# Component description for the SPI BUS DXE module +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 1.27 + BASE_NAME = SpiBusDxe + FILE_GUID = 25CE038C-5C3A-4A9B-A111-90DF5897E058 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = SpiBusEntry + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Sources] + SpiBusDxe.c + SpiBus.c + SpiBus.h + +[Protocols] + gEfiSpiConfigurationProtocolGuid ## CONSUMES + gEfiSpiHcProtocolGuid ## CONSUMES + +[Depex] + gEfiSpiConfigurationProtocolGuid AND + gEfiSpiHcProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + SpiBus.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..2d614cba67dd448d268ecc7280fba3e31fc1b53c --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.c @@ -0,0 +1,161 @@ +/** @file + + SPI bus SMM driver + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiBus.h" + +/** + Entry point of the Spi Bus layer + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_DEVICE_ERROR Fail to install EFI_SPI_HC_PROTOCOL protocol. + @retval EFI_NOT_FOUND fail to locate SpiHcProtocol or SpiIoConfigurationProtocol +**/ +EFI_STATUS +EFIAPI +SpiBusEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SPI_IO_CHIP *SpiChip; + EFI_SPI_HC_PROTOCOL *SpiHc; + EFI_SPI_CONFIGURATION_PROTOCOL *SpiConfiguration; + EFI_SPI_PERIPHERAL *SpiPeripheral; + EFI_SPI_BUS *Bus; + + DEBUG ((DEBUG_VERBOSE, "%a - ENTRY\n", __func__)); + + // Only a single Spi HC protocol in SMM + Status = gMmst->MmLocateProtocol ( + &gEfiSpiSmmHcProtocolGuid, + NULL, + (VOID **)&SpiHc + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "No SpiHcProtocol is found\n")); + Status = EFI_NOT_FOUND; + goto Exit; + } + + // Locate the SPI Configuration Protocol + Status = gMmst->MmLocateProtocol ( + &gEfiSpiSmmConfigurationProtocolGuid, + NULL, + (VOID **)&SpiConfiguration + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "No SpiConfigurationProtocol is found\n")); + Status = EFI_NOT_FOUND; + goto Exit; + } + + // Only one SpiBus supported in SMM + if (SpiConfiguration->BusCount != 1) { + DEBUG ((DEBUG_VERBOSE, "Only one SPI Bus supported in SMM\n")); + Status = EFI_UNSUPPORTED; + goto Exit; + } + + Bus = (EFI_SPI_BUS *)SpiConfiguration->Buslist[0]; + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "%a - Error getting SpiHc from Handle\n", __func__)); + goto Exit; + } + + SpiPeripheral = (EFI_SPI_PERIPHERAL *)Bus->Peripherallist; + if (SpiPeripheral != NULL) { + do { + DEBUG (( + DEBUG_VERBOSE, + "%a: Installing SPI IO protocol for %s, by %s, PN=%s\n", + __func__, + SpiPeripheral->FriendlyName, + SpiPeripheral->SpiPart->Vendor, + SpiPeripheral->SpiPart->PartNumber + )); + // Allocate the SPI IO Device + SpiChip = AllocateZeroPool (sizeof (SPI_IO_CHIP)); + ASSERT (SpiChip != NULL); + if (SpiChip != NULL) { + // Fill in the SpiChip + SpiChip->Signature = SPI_IO_SIGNATURE; + SpiChip->SpiConfig = SpiConfiguration; + SpiChip->SpiHc = SpiHc; + SpiChip->SpiBus = Bus; + SpiChip->Protocol.SpiPeripheral = SpiPeripheral; + SpiChip->Protocol.OriginalSpiPeripheral = SpiPeripheral; + SpiChip->Protocol.FrameSizeSupportMask = SpiHc->FrameSizeSupportMask; + SpiChip->Protocol.MaximumTransferBytes = SpiHc->MaximumTransferBytes; + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_ADDRESS) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS; + } + + if ((SpiHc->Attributes & HC_TRANSFER_SIZE_INCLUDES_OPCODE) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE; + } + + if ((SpiHc->Attributes & HC_SUPPORTS_8_BIT_DATA_BUS_WIDTH) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH; + } + + if ((SpiHc->Attributes & HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH; + } + + if ((SpiHc->Attributes & HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH) != 0) { + SpiChip->Protocol.Attributes |= SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH; + } + + SpiChip->Protocol.Transaction = Transaction; + SpiChip->Protocol.UpdateSpiPeripheral = UpdateSpiPeripheral; + // Install the SPI IO Protocol + Status = gMmst->MmInstallProtocolInterface ( + &SpiChip->Handle, + (GUID *)SpiPeripheral->SpiPeripheralDriverGuid, + EFI_NATIVE_INTERFACE, + &SpiChip->Protocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "%a - Error installing SpiIoProtocol\n", __func__)); + continue; + } + } else { + Status = EFI_OUT_OF_RESOURCES; + DEBUG (( + DEBUG_ERROR, + "%a: Out of Memory resources\n", + __func__ + )); + break; + } + + SpiPeripheral = (EFI_SPI_PERIPHERAL *)SpiPeripheral->NextSpiPeripheral; + } while (SpiPeripheral != NULL); + } else { + Status = EFI_DEVICE_ERROR; + } + +Exit: + DEBUG ((DEBUG_VERBOSE, "%a - EXIT (Status = %r)\n", __func__, Status)); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..694c425eb6f6ed4aee65a20cf97a8de1ff2094aa --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf @@ -0,0 +1,42 @@ +#/** @file +# +# Component description for the SPI BUS SMM module +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 1.27 + BASE_NAME = SpiBusSmm + FILE_GUID = 5DBB52E1-3D78-4C9C-A9D7-A43E79E93AC0 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = SpiBusEntry + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + MmServicesTableLib + UefiDriverEntryPoint + +[Sources] + SpiBus.h + SpiBus.c + SpiBusSmm.c + +[Protocols] + gEfiSpiSmmConfigurationProtocolGuid ## CONSUMES + gEfiSpiSmmHcProtocolGuid ## CONSUMES + +[Depex] + gEfiSpiSmmConfigurationProtocolGuid AND + gEfiSpiSmmHcProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + SpiBus.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.c new file mode 100644 index 0000000000000000000000000000000000000000..fdda2c5ab17224c9a5c557f2f3827722555e6d29 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.c @@ -0,0 +1,115 @@ +/** @file + + SPI Host Controller shell implementation, as host controller code is platform + specfic. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "SpiHc.h" + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +ChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ) +{ + return PlatformSpiHcChipSelect (This, SpiPeripheral, PinValue); +} + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +Clock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ) +{ + return PlatformSpiHcClock (This, SpiPeripheral, ClockHz); +} + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + @retval EFI_DEVICE_ERROR SPI Host Controller failed transaction + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ) +{ + return PlatformSpiHcTransaction (This, BusTransaction); +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.h new file mode 100644 index 0000000000000000000000000000000000000000..f4d03c4c00847e0dd41b63f859e93298a7279e38 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.h @@ -0,0 +1,111 @@ +/** @file + + SPI Host Controller function declarations + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +ChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +Clock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + @retval EFI_DEVICE_ERROR SPI Host Controller failed transaction + +**/ +EFI_STATUS +EFIAPI +Transaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ); diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.uni b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.uni new file mode 100644 index 0000000000000000000000000000000000000000..7d8d375e225663910d49462ef0f4f5fff9490192 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHc.uni @@ -0,0 +1,10 @@ +// /** @file +// +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "SPI host controller driver" diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..d8453be98c08a61aa0e880b8ca6d773350177114 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.c @@ -0,0 +1,101 @@ +/** @file + + SPI Host controller entry point for DXE + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiHc.h" + +EFI_HANDLE mSpiHcHandle = 0; + +/** + Entry point of the SPI Host Controller driver. Installs the EFI_SPI_HC_PROTOCOL on mSpiHcHandle. + Also installs the EFI_DEVICE_PATH_PROTOCOL corresponding to the SPI Host controller on the same + mSpiHcHandle. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_RESOURCES If the system has run out of memory +**/ +EFI_STATUS +EFIAPI +SpiHcProtocolEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SPI_HC_PROTOCOL *HcProtocol; + EFI_DEVICE_PATH_PROTOCOL *HcDevicePath; + + DEBUG ((DEBUG_VERBOSE, "%a - ENTRY\n", __func__)); + + // Allocate the SPI Host Controller protocol + HcProtocol = AllocateZeroPool (sizeof (EFI_SPI_HC_PROTOCOL)); + ASSERT (HcProtocol != NULL); + if (HcProtocol == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // Fill in the SPI Host Controller Protocol + Status = GetPlatformSpiHcDetails ( + &HcProtocol->Attributes, + &HcProtocol->FrameSizeSupportMask, + &HcProtocol->MaximumTransferBytes + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error, no Platform SPI HC details\n")); + return Status; + } + + HcProtocol->ChipSelect = ChipSelect; + HcProtocol->Clock = Clock; + HcProtocol->Transaction = Transaction; + + // Install Host Controller protocol + Status = gBS->InstallProtocolInterface ( + &mSpiHcHandle, + &gEfiSpiHcProtocolGuid, + EFI_NATIVE_INTERFACE, + HcProtocol + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error installing gEfiSpiHcProtocolGuid\n")); + return Status; + } + + Status = GetSpiHcDevicePath (&HcDevicePath); + + // Install HC device path here on this handle as well + Status = gBS->InstallProtocolInterface ( + &mSpiHcHandle, + &gEfiDevicePathProtocolGuid, + EFI_NATIVE_INTERFACE, + HcDevicePath + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error installing gEfiDevicePathProtocolGuid\n")); + } + + DEBUG ((DEBUG_VERBOSE, "%a - EXIT Status=%r\n", __func__, Status)); + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..b3c101c1ff196ab7f656805b9dac225484d3cb9d --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf @@ -0,0 +1,46 @@ +#/** @file +# +# Component description file for SPI Host Controller Module +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 1.27 + BASE_NAME = SpiHcDxe + FILE_GUID = 95D148FF-5A23-43B9-9FC4-80AE0DD48D32 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = SpiHcProtocolEntry + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + SpiHcPlatformLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Sources] + SpiHc.h + SpiHc.c + SpiHcDxe.c + +[Protocols] + gEfiSpiHcProtocolGuid + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SpiHc.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..961d174a248bfb8da54a97f77523f88fd2667e56 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.c @@ -0,0 +1,79 @@ +/** @file + + SPI Host controller entry point for SMM + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiHc.h" + +EFI_HANDLE mSpiHcHandle = 0; + +/** + Entry point of the SPI Host Controller driver. Installs the EFI_SPI_HC_PROTOCOL on mSpiHcHandle. + Also installs the EFI_DEVICE_PATH_PROTOCOL corresponding to the SPI Host controller on the same + mSpiHcHandle. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_RESOURCES If the system has run out of memory +**/ +EFI_STATUS +EFIAPI +SpiHcProtocolEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SPI_HC_PROTOCOL *HcProtocol; + + DEBUG ((DEBUG_VERBOSE, "%a - ENTRY\n", __func__)); + + // Allocate the SPI Host Controller protocol + HcProtocol = AllocateZeroPool (sizeof (EFI_SPI_HC_PROTOCOL)); + ASSERT (HcProtocol != NULL); + if (HcProtocol == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // Fill in the SPI Host Controller Protocol + Status = GetPlatformSpiHcDetails ( + &HcProtocol->Attributes, + &HcProtocol->FrameSizeSupportMask, + &HcProtocol->MaximumTransferBytes + ); + + HcProtocol->ChipSelect = ChipSelect; + HcProtocol->Clock = Clock; + HcProtocol->Transaction = Transaction; + + Status = gMmst->MmInstallProtocolInterface ( + &mSpiHcHandle, + &gEfiSpiSmmHcProtocolGuid, + EFI_NATIVE_INTERFACE, + HcProtocol + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error installing gEfiSpiSmmHcProtocolGuid\n")); + } + + DEBUG ((DEBUG_VERBOSE, "%a - EXIT Status=%r\n", __func__, Status)); + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..c47cc96f54f5eaab1c1c3d89069a8d3b4a5dd978 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Component description file for SPI Host Controller Module +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ +[Defines] + INF_VERSION = 1.27 + BASE_NAME = SpiHcSmm + FILE_GUID = 0CDAE298-CB3B-480A-BDC4-A6840FFE1F5E + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = SpiHcProtocolEntry + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + MemoryAllocationLib + MmServicesTableLib + SpiHcPlatformLib + UefiDriverEntryPoint + UefiLib + +[Sources] + SpiHc.h + SpiHc.c + SpiHcSmm.c + +[Protocols] + gEfiSpiSmmHcProtocolGuid + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SpiHc.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlash.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlash.c new file mode 100644 index 0000000000000000000000000000000000000000..767e818c52a15b65d57b8140f3995482a55727f0 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlash.c @@ -0,0 +1,1136 @@ +/** @file + SPI NOR Flash operation functions. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiNorFlash.h" + +/** + Fill Write Buffer with Opcode, Address, Dummy Bytes, and Data + + @param[in] Opcode - Opcode for transaction + @param[in] Address - SPI Offset Start Address + @param[in] WriteBytes - Number of bytes to write to SPI device + @param[in] WriteBuffer - Buffer containing bytes to write to SPI device + + @retval Size of Data in Buffer +**/ +UINT32 +FillWriteBuffer ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN UINT8 Opcode, + IN UINT32 DummyBytes, + IN UINT8 AddressBytesSupported, + IN BOOLEAN UseAddress, + IN UINT32 Address, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer + ) +{ + UINT32 AddressSize; + UINT32 BigEndianAddress; + UINT32 Index; + UINT8 SfdpAddressBytes; + + SfdpAddressBytes = (UINT8)Instance->SfdpBasicFlash->AddressBytes; + + // Copy Opcode into Write Buffer + Instance->SpiTransactionWriteBuffer[0] = Opcode; + Index = 1; + if (UseAddress == TRUE) { + if (AddressBytesSupported == SPI_ADDR_3BYTE_ONLY) { + if (SfdpAddressBytes != 0) { + // Check if the supported address length is already initiated. + if ((SfdpAddressBytes != SPI_ADDR_3BYTE_ONLY) && (SfdpAddressBytes != SPI_ADDR_3OR4BYTE)) { + DEBUG ((DEBUG_ERROR, "%a: Unsupported Address Bytes: 0x%x, SFDP is: 0x%x\n", __func__, AddressBytesSupported, SfdpAddressBytes)); + ASSERT (FALSE); + } + } + + AddressSize = 3; + } else if (AddressBytesSupported == SPI_ADDR_4BYTE_ONLY) { + if (SfdpAddressBytes != 0) { + // Check if the supported address length is already initiated. + if ((SfdpAddressBytes != SPI_ADDR_4BYTE_ONLY) && (SfdpAddressBytes != SPI_ADDR_3OR4BYTE)) { + DEBUG ((DEBUG_ERROR, "%a: Unsupported Address Bytes: 0x%x, SFDP is: 0x%x\n", __func__, AddressBytesSupported, SfdpAddressBytes)); + ASSERT (FALSE); + } + } + + AddressSize = 4; + } else if (AddressBytesSupported == SPI_ADDR_3OR4BYTE) { + if (SfdpAddressBytes != 0) { + // Check if the supported address length is already initiated. + if (SfdpAddressBytes != SPI_ADDR_3OR4BYTE) { + DEBUG ((DEBUG_ERROR, "%a: Unsupported Address Bytes: 0x%x, SFDP is: 0x%x\n", __func__, AddressBytesSupported, SfdpAddressBytes)); + ASSERT (FALSE); + } + } + + if (Instance->Protocol.FlashSize <= SIZE_16MB) { + AddressSize = 3; + } else { + // SPI part is > 16MB use 4-byte addressing. + AddressSize = 4; + } + } else { + DEBUG ((DEBUG_ERROR, "%a: Invalid Address Bytes\n", __func__)); + ASSERT (FALSE); + } + + BigEndianAddress = SwapBytes32 ((UINT32)Address); + BigEndianAddress >>= ((sizeof (UINT32) - AddressSize) * 8); + CopyMem ( + &Instance->SpiTransactionWriteBuffer[Index], + &BigEndianAddress, + AddressSize + ); + Index += AddressSize; + } + + if (SfdpAddressBytes == SPI_ADDR_3OR4BYTE) { + // + // TODO: + // We may need to enter/exit 4-Byte mode if SPI flash + // device is currently operated in 3-Bytes mode. + // + } + + // Fill DummyBytes + if (DummyBytes != 0) { + SetMem ( + &Instance->SpiTransactionWriteBuffer[Index], + DummyBytes, + 0 + ); + Index += DummyBytes; + } + + // Fill Data + if (WriteBytes > 0) { + CopyMem ( + &Instance->SpiTransactionWriteBuffer[Index], + WriteBuffer, + WriteBytes + ); + Index += WriteBytes; + } + + return Index; +} + +/** + Internal Read the flash status register. + + This routine reads the flash part status register. + + @param[in] Instance SPI_NOR_FLASH_INSTANCE + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +EFI_STATUS +EFIAPI +InternalReadStatus ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + + // Read Status register + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSR, + SPI_FLASH_RDSR_DUMMY, + SPI_FLASH_RDSR_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 1, + FlashStatus + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + Set Write Enable Latch + + @param[in] Instance SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS SPI Write Enable succeeded + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +SetWel ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + + TransactionBufferLength = FillWriteBuffer ( + Instance, + Instance->WriteEnableLatchCommand, + SPI_FLASH_WREN_DUMMY, + SPI_FLASH_WREN_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Set WEL fail.\n", __func__)); + ASSERT (FALSE); + } + + return Status; +} + +/** + Check for not device write in progress + + @param[in] Instance SPI NOR instance with all protocols, etc. + @param[in] Timeout Timeout in microsecond + @param[in] RetryCount The retry count + + @retval EFI_SUCCESS Device does not have a write in progress + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +WaitNotWip ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT32 Timeout, + IN UINT32 RetryCount + ) +{ + EFI_STATUS Status; + UINT8 DeviceStatus; + UINT32 AlreadyDelayedInMicroseconds; + + if (Timeout == 0) { + return EFI_SUCCESS; + } + + if (RetryCount == 0) { + RetryCount = 1; + } + + do { + AlreadyDelayedInMicroseconds = 0; + while (AlreadyDelayedInMicroseconds < Timeout) { + Status = InternalReadStatus (SpiNorFlashInstance, 1, &DeviceStatus); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Read status error\n", __FUNCTION__)); + ASSERT (FALSE); + return Status; + } + + if ((DeviceStatus & SPI_FLASH_SR_WIP) == SPI_FLASH_SR_NOT_WIP) { + return Status; + } + + MicroSecondDelay (FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds)); + AlreadyDelayedInMicroseconds += FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + } + + RetryCount--; + } while (RetryCount > 0); + + DEBUG ((DEBUG_ERROR, "%a: Timeout error\n", __FUNCTION__)); + return EFI_DEVICE_ERROR; +} + +/** + Check for write enable latch set and not device write in progress + + @param[in] Instance SPI NOR instance with all protocols, etc. + @param[in] Timeout Timeout in microsecond + @param[in] RetryCount The retry count + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +WaitWelNotWip ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT32 Timeout, + IN UINT32 RetryCount + ) +{ + EFI_STATUS Status; + UINT8 DeviceStatus; + UINT32 AlreadyDelayedInMicroseconds; + + if (Timeout == 0) { + return EFI_SUCCESS; + } + + if (RetryCount == 0) { + RetryCount = 1; + } + + do { + AlreadyDelayedInMicroseconds = 0; + while (AlreadyDelayedInMicroseconds < Timeout) { + Status = InternalReadStatus (SpiNorFlashInstance, 1, &DeviceStatus); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to read WEL.\n", __FUNCTION__)); + ASSERT_EFI_ERROR (Status); + return Status; + } + + if ((DeviceStatus & (SPI_FLASH_SR_WIP | SPI_FLASH_SR_WEL)) == SPI_FLASH_SR_WEL) { + return Status; + } + + MicroSecondDelay (FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds)); + AlreadyDelayedInMicroseconds += FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + } + + RetryCount--; + } while (RetryCount > 0); + + DEBUG ((DEBUG_ERROR, "%a: Timeout error\n", __FUNCTION__)); + return EFI_DEVICE_ERROR; +} + +/** + Check for not write enable latch set and not device write in progress + + @param[in] Instance SPI NOR instance with all protocols, etc. + @param[in] Timeout Timeout in microsecond + @param[in] RetryCount The retry count + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is not set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +WaitNotWelNotWip ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT32 Timeout, + IN UINT32 RetryCount + ) +{ + EFI_STATUS Status; + UINT8 DeviceStatus; + UINT32 AlreadyDelayedInMicroseconds; + + if (Timeout == 0) { + return EFI_SUCCESS; + } + + if (RetryCount == 0) { + RetryCount = 1; + } + + do { + AlreadyDelayedInMicroseconds = 0; + while (AlreadyDelayedInMicroseconds < Timeout) { + Status = InternalReadStatus (SpiNorFlashInstance, 1, &DeviceStatus); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status) || + ((DeviceStatus & (SPI_FLASH_SR_WIP | SPI_FLASH_SR_WEL)) == SPI_FLASH_SR_NOT_WIP)) + { + return Status; + } + + MicroSecondDelay (FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds)); + AlreadyDelayedInMicroseconds += FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + } + + RetryCount--; + } while (RetryCount > 0); + + DEBUG ((DEBUG_ERROR, "SpiNorFlash:%a: Timeout error\n", __FUNCTION__)); + return EFI_DEVICE_ERROR; +} + +/** + Read the 3 byte manufacture and device ID from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the 3 byte manufacture and device ID from the flash part + filling the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure. + @param[out] Buffer Pointer to a 3 byte buffer to receive the manufacture and + device ID. + + @retval EFI_SUCCESS The manufacture and device ID was read + successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +GetFlashId ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + UINT32 TransactionBufferLength; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + Instance = SPI_NOR_FLASH_FROM_THIS (This); + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDID, + SPI_FLASH_RDID_DUMMY, + SPI_FLASH_RDID_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 3, + Buffer + ); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + Read data from the SPI flash at not fast speed + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +LfReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT8 *CurrentBuffer; + UINT32 Length; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + + Status = EFI_DEVICE_ERROR; + if ((Buffer == NULL) || + (FlashAddress >= This->FlashSize) || + (LengthInBytes > This->FlashSize - FlashAddress)) + { + return EFI_INVALID_PARAMETER; + } + + Instance = SPI_NOR_FLASH_FROM_THIS (This); + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + + CurrentBuffer = Buffer; + Length = 0; + for (ByteCounter = 0; ByteCounter < LengthInBytes;) { + CurrentAddress = FlashAddress + ByteCounter; + CurrentBuffer = Buffer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_READ, + SPI_FLASH_READ_DUMMY, + SPI_FLASH_READ_ADDR_BYTES, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + Length, + CurrentBuffer + ); + ASSERT_EFI_ERROR (Status); + ByteCounter += Length; + } + + return Status; +} + +/** + Read data from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +ReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT8 *CurrentBuffer; + UINT32 Length; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + UINT8 FastReadInstruction; + UINT8 FastReadWaitStateDummyClocks; + UINT8 FastReadModeClock; + + DEBUG ((DEBUG_INFO, "%a: Entry, Read address = 0x%08x, Length = 0x%08x\n", __func__, FlashAddress, LengthInBytes)); + + Status = EFI_DEVICE_ERROR; + if ((Buffer == NULL) || + (FlashAddress >= This->FlashSize) || + (LengthInBytes > This->FlashSize - FlashAddress)) + { + return EFI_INVALID_PARAMETER; + } + + Instance = SPI_NOR_FLASH_FROM_THIS (This); + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + + // + // Initial the default read operation parameters. + // + FastReadInstruction = SPI_FLASH_FAST_READ; + FastReadWaitStateDummyClocks = SPI_FLASH_FAST_READ_DUMMY * 8; + FastReadModeClock = 0; + // + // Override by the Fast Read capabiity table. + // + // Get the first supported fast read comamnd. + // This will be the standard fast read command (0x0b), + // which is the first fast read command added to the + // supported list. + // TODO: The mechanism to choose the advanced fast read + // is not determined yet in this version of + // SpiNorFlash driver. + Status = GetFastReadParameter ( + Instance, + &FastReadInstruction, + &FastReadModeClock, + &FastReadWaitStateDummyClocks + ); + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, " Use below Fast Read mode:\n")); + } else { + DEBUG ((DEBUG_VERBOSE, " Use the default Fast Read mode:\n")); + } + + DEBUG ((DEBUG_VERBOSE, " Instruction : 0x%x\n", FastReadInstruction)); + DEBUG ((DEBUG_VERBOSE, " Mode Clock : 0x%x\n", FastReadModeClock)); + DEBUG ((DEBUG_VERBOSE, " Wait States (Dummy Clocks) in clock: 0x%x\n", FastReadWaitStateDummyClocks)); + DEBUG ((DEBUG_VERBOSE, " Supported erase address bytes by device: 0x%02x.\n", Instance->SfdpBasicFlash->AddressBytes)); + DEBUG ((DEBUG_VERBOSE, " (00: 3-Byte, 01: 3 or 4-Byte. 10: 4-Byte)\n")); + + CurrentBuffer = Buffer; + Length = 0; + for (ByteCounter = 0; ByteCounter < LengthInBytes;) { + CurrentAddress = FlashAddress + ByteCounter; + CurrentBuffer = Buffer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + + TransactionBufferLength = FillWriteBuffer ( + Instance, + FastReadInstruction, + FastReadWaitStateDummyClocks / 8, + (UINT8)Instance->SfdpBasicFlash->AddressBytes, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + Length, + CurrentBuffer + ); + ASSERT_EFI_ERROR (Status); + ByteCounter += Length; + } + + return Status; +} + +/** + Read the flash status register. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +EFI_STATUS +EFIAPI +ReadStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + + if (LengthInBytes != 1) { + return EFI_INVALID_PARAMETER; + } + + Instance = SPI_NOR_FLASH_FROM_THIS (This); + + Status = InternalReadStatus (Instance, LengthInBytes, FlashStatus); + + return Status; +} + +/** + Write the flash status register. + + This routine must be called at or below TPL_N OTIFY. + This routine writes the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to write. + @param[in] FlashStatus Pointer to a buffer containing the new status. + + @retval EFI_SUCCESS The status write was successful. + @retval EFI_OUT_OF_RESOURCES Failed to allocate the write buffer. + +**/ +EFI_STATUS +EFIAPI +WriteStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + IN UINT8 *FlashStatus + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + UINT32 TransactionBufferLength; + + if (LengthInBytes != 1) { + return EFI_INVALID_PARAMETER; + } + + Instance = SPI_NOR_FLASH_FROM_THIS (This); + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + + // Set Write Enable + if (!EFI_ERROR (Status)) { + if (Instance->WriteEnableLatchRequired) { + Status = SetWel (Instance); + DEBUG ((DEBUG_ERROR, "%a: set Write Enable Error.\n", __func__)); + ASSERT_EFI_ERROR (Status); + // Check not WIP & WEL enabled + Status = WaitWelNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + } + + // Write the Status Register + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_WRSR, + SPI_FLASH_WRSR_DUMMY, + SPI_FLASH_WRSR_ADDR_BYTES, + FALSE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + } + } + + return Status; +} + +/** + Write data to the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine breaks up the write operation as necessary to write the data to + the SPI part. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start writing + @param[in] LengthInBytes Write length in bytes + @param[in] Buffer Address of a buffer containing the data + + @retval EFI_SUCCESS The data was written successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + @retval EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer. + +**/ +EFI_STATUS +EFIAPI +WriteData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT32 Length; + UINT32 BytesUntilBoundary; + UINT8 *CurrentBuffer; + UINT32 TransactionBufferLength; + UINT32 MaximumTransferBytes; + UINT32 SpiFlashPageSize; + + DEBUG ((DEBUG_INFO, "%a: Entry: Write address = 0x%08x, Length = 0x%08x\n", __func__, FlashAddress, LengthInBytes)); + + Status = EFI_DEVICE_ERROR; + if ((Buffer == NULL) || + (LengthInBytes == 0) || + (FlashAddress >= This->FlashSize) || + (LengthInBytes > This->FlashSize - FlashAddress)) + { + return EFI_INVALID_PARAMETER; + } + + Instance = SPI_NOR_FLASH_FROM_THIS (This); + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + if (Instance->SfdpBasicFlashByteCount >= 11 * 4) { + // JESD216C spec DWORD 11 + SpiFlashPageSize = 1 << Instance->SfdpBasicFlash->PageSize; + } else { + SpiFlashPageSize = 256; + } + + CurrentBuffer = Buffer; + Length = 0; + for (ByteCounter = 0; ByteCounter < LengthInBytes;) { + CurrentAddress = FlashAddress + ByteCounter; + CurrentBuffer = Buffer + ByteCounter; + Length = LengthInBytes - ByteCounter; + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Cannot cross SpiFlashPageSize boundary + BytesUntilBoundary = SpiFlashPageSize + - (CurrentAddress % SpiFlashPageSize); + if ((BytesUntilBoundary != 0) && (Length > BytesUntilBoundary)) { + Length = BytesUntilBoundary; + } + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + + if (Instance->WriteEnableLatchRequired) { + // Set Write Enable + Status = SetWel (Instance); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + break; + } + + // Check not WIP & WEL enabled + Status = WaitWelNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + } + + // Write Data + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_PP, + SPI_FLASH_PP_DUMMY, + SPI_FLASH_PP_ADDR_BYTES, + TRUE, + CurrentAddress, + Length, + CurrentBuffer + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + break; + } + + if (Instance->WriteEnableLatchRequired) { + // Check not WIP & not WEL + Status = WaitNotWelNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + } else { + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + } + + ByteCounter += Length; + } + + return Status; +} + +/** + Efficiently erases blocks in the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine may use the combination of variable earse sizes to erase the + specified area accroding to the flash region. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address to start erasing + @param[in] BlockCount Number of blocks to erase. The block size is indicated + in EraseBlockBytes in EFI_SPI_NOR_FLASH_PROTOCOL. + + @retval EFI_SUCCESS The erase was completed successfully. + @retval EFI_DEVICE_ERROR The flash devices has problems. + @retval EFI_INVALID_PARAMETER The given FlashAddress and/or BlockCount + is invalid. + +**/ +EFI_STATUS +EFIAPI +Erase ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 BlockCount + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + UINT8 Opcode; + UINT32 Dummy; + UINT32 ByteCounter; + UINT32 EraseLength; + UINT32 TotalEraseLength; + UINT32 CurrentAddress; + UINT32 TransactionBufferLength; + UINT32 BlockCountToErase; + UINT32 BlockSizeToErase; + UINT8 BlockEraseCommand; + UINT32 TypicalEraseTime; + UINT64 MaximumEraseTimeout; + SFDP_SECTOR_REGION_RECORD *FlashRegion; + + DEBUG ((DEBUG_INFO, "%a: Entry: Erase address = 0x%08x, Block count = 0x%x\n", __func__, FlashAddress, BlockCount)); + + Status = EFI_DEVICE_ERROR; + Instance = SPI_NOR_FLASH_FROM_THIS (This); + + // Get the region of this flash address. + Status = GetRegionByFlashAddress (Instance, FlashAddress, &FlashRegion); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Failed to get the flash region of this flash address.\n")); + ASSERT (FALSE); + return Status; + } + + CurrentAddress = FlashAddress; + BlockCountToErase = BlockCount; + BlockSizeToErase = FlashRegion->SectorSize; // This is also the minimum block erase size. + TotalEraseLength = BlockCountToErase * FlashRegion->SectorSize; + if ((FlashAddress + TotalEraseLength) > (FlashRegion->RegionAddress + FlashRegion->RegionTotalSize)) { + DEBUG ((DEBUG_ERROR, " The blocks to erase exceeds the region boundary.\n")); + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_VERBOSE, " Region starting address: 0x%08x.\n", FlashRegion->RegionAddress)); + DEBUG ((DEBUG_VERBOSE, " Region size : 0x%08x.\n", FlashRegion->RegionTotalSize)); + DEBUG ((DEBUG_VERBOSE, " Region sector size : 0x%08x.\n", FlashRegion->SectorSize)); + DEBUG ((DEBUG_VERBOSE, " Supported erase address bytes by device: 0x%02x.\n", Instance->SfdpBasicFlash->AddressBytes)); + DEBUG ((DEBUG_VERBOSE, " (00: 3-Byte, 01: 3 or 4-Byte. 10: 4-Byte)\n")); + + // Loop until all blocks are erased. + ByteCounter = 0; + while (ByteCounter < TotalEraseLength) { + CurrentAddress = FlashAddress + ByteCounter; + + // Is this the whole device erase. + if (TotalEraseLength == This->FlashSize) { + Opcode = SPI_FLASH_CE; + Dummy = SPI_FLASH_CE_DUMMY; + EraseLength = TotalEraseLength; + DEBUG ((DEBUG_VERBOSE, " This is the chip erase.\n")); + } else { + // + // Get the erase block attributes. + // + Status = GetEraseBlockAttribute ( + Instance, + FlashRegion, + CurrentAddress, + TotalEraseLength - ByteCounter, + &BlockSizeToErase, + &BlockCountToErase, + &BlockEraseCommand, + &TypicalEraseTime, + &MaximumEraseTimeout + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Failed to get erase block attribute.\n")); + ASSERT (FALSE); + } + + Opcode = BlockEraseCommand; + Dummy = SPI_FLASH_BE_DUMMY; + EraseLength = BlockCountToErase * BlockSizeToErase; + DEBUG (( + DEBUG_VERBOSE, + " Erase command 0x%02x at adddress 0x%08x for length 0x%08x.\n", + BlockEraseCommand, + CurrentAddress, + EraseLength + )); + } + + // + // Process the erase command. + // + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + + if (Instance->WriteEnableLatchRequired) { + // Set Write Enable + Status = SetWel (Instance); + if (EFI_ERROR (Status)) { + break; + } + + // Check not WIP & WEL enabled + Status = WaitWelNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + } + + // Erase Block + TransactionBufferLength = FillWriteBuffer ( + Instance, + Opcode, + Dummy, + (UINT8)Instance->SfdpBasicFlash->AddressBytes, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_ONLY, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 0, + NULL + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + break; + } else { + DEBUG ((DEBUG_VERBOSE, "Erase command sucessfully.\n")); + } + + if (Instance->WriteEnableLatchRequired) { + // + // Check not WIP & not WEL + // Use the timeout value calculated by SPI NOR flash SFDP. + // + Status = WaitNotWelNotWip (Instance, (UINT32)MaximumEraseTimeout * 1000, FixedPcdGet32 (PcdSpiNorFlashOperationRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + } else { + // + // Use the timeout value calculated by SPI NOR flash SFDP. + // + Status = WaitNotWip (Instance, (UINT32)MaximumEraseTimeout * 1000, FixedPcdGet32 (PcdSpiNorFlashOperationRetryCount)); + if (EFI_ERROR (Status)) { + break; + } + } + + ByteCounter += EraseLength; + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlash.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlash.h new file mode 100644 index 0000000000000000000000000000000000000000..1dce0353d56dcdd20bb784d372291be103047382 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlash.h @@ -0,0 +1,285 @@ +/** @file + Definitions of SPI NOR flash operation functions. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_NOR_FLASH_H_ +#define SPI_NOR_FLASH_H_ + +#include +#include +#include +#include "SpiNorFlashJedecSfdpInternal.h" + +/** + Fill Write Buffer with Opcode, Address, Dummy Bytes, and Data + + @param[in] Opcode - Opcode for transaction + @param[in] Address - SPI Offset Start Address + @param[in] WriteBytes - Number of bytes to write to SPI device + @param[in] WriteBuffer - Buffer containing bytes to write to SPI device + + @retval Size of Data in Buffer +**/ +UINT32 +FillWriteBuffer ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT8 Opcode, + IN UINT32 DummyBytes, + IN UINT8 AddressBytesSupported, + IN BOOLEAN UseAddress, + IN UINT32 Address, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer + ); + +/** + Set Write Enable Latch + + @param[in] Instance SPI NOR instance with all protocols, etc. + + @retval EFI_SUCCESS SPI Write Enable succeeded + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +SetWel ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance + ); + +/** + Check for not device write in progress + + @param[in] Instance SPI NOR instance with all protocols, etc. + @param[in] Timeout Timeout in microsecond + @param[in] RetryCount The retry count + + @retval EFI_SUCCESS Device does not have a write in progress + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +WaitNotWip ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT32 Timeout, + IN UINT32 RetryCount + ); + +/** + Check for write enable latch set and not device write in progress + + @param[in] Instance SPI NOR instance with all protocols, etc. + @param[in] Timeout Timeout in microsecond + @param[in] RetryCount The retry count + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +WaitWelNotWip ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT32 Timeout, + IN UINT32 RetryCount + ); + +/** + Check for not write enable latch set and not device write in progress + + @param[in] Instance SPI NOR instance with all protocols, etc. + @param[in] Timeout Timeout in microsecond + @param[in] RetryCount The retry count + + @retval EFI_SUCCESS Device does not have a write in progress and + write enable latch is not set + @retval EFI_DEVICE_ERROR SPI Flash part did not respond properly +**/ +EFI_STATUS +WaitNotWelNotWip ( + IN SPI_NOR_FLASH_INSTANCE *SpiNorFlashInstance, + IN UINT32 Timeout, + IN UINT32 RetryCount + ); + +/** + Read the 3 byte manufacture and device ID from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the 3 byte manufacture and device ID from the flash part + filling the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure. + @param[out] Buffer Pointer to a 3 byte buffer to receive the manufacture and + device ID. + + + + @retval EFI_SUCCESS The manufacture and device ID was read + successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +GetFlashId ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + OUT UINT8 *Buffer + ); + +/** + Read data from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +ReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ); + +/** + Read data from the SPI flash at not fast speed + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +LfReadData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ); + +/** + Read the flash status register. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +EFI_STATUS +EFIAPI +ReadStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ); + +/** + Write the flash status register. + + This routine must be called at or below TPL_N OTIFY. + This routine writes the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to write. + @param[in] FlashStatus Pointer to a buffer containing the new status. + + @retval EFI_SUCCESS The status write was successful. + @retval EFI_OUT_OF_RESOURCES Failed to allocate the write buffer. + +**/ +EFI_STATUS +EFIAPI +WriteStatus ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + IN UINT8 *FlashStatus + ); + +/** + Write data to the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine breaks up the write operation as necessary to write the data to + the SPI part. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start writing + @param[in] LengthInBytes Write length in bytes + @param[in] Buffer Address of a buffer containing the data + + @retval EFI_SUCCESS The data was written successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + @retval EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer. + +**/ +EFI_STATUS +EFIAPI +WriteData ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + IN UINT8 *Buffer + ); + +/** + Efficiently erases one or more 4KiB regions in the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine uses a combination of 4 KiB and larger blocks to erase the + specified area. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address within a 4 KiB block to start erasing + @param[in] BlockCount Number of 4 KiB blocks to erase + + @retval EFI_SUCCESS The erase was completed successfully. + @retval EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize, or + BlockCount * 4 KiB + > This->FlashSize - FlashAddress + +**/ +EFI_STATUS +EFIAPI +Erase ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 BlockCount + ); + +#endif // SPI_NOR_FLASH_H_ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdp.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdp.c new file mode 100644 index 0000000000000000000000000000000000000000..480ea018e0d5abcf61f7e3099fc344cb37fa1015 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdp.c @@ -0,0 +1,1781 @@ +/** @file + SPI NOR Flash JEDEC Serial Flash Discoverable Parameters (SFDP) + common functions. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - JEDEC Standard, JESD216F.02 + https://www.jedec.org/document_search?search_api_views_fulltext=JESD216 + + @par Glossary: + - SFDP - Serial Flash Discoverable Parameters + - PTP - Parameter Table Pointer +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiNorFlash.h" +#include "SpiNorFlashJedecSfdpInternal.h" + +/** + Build up the Fast Read capability entry and link it to + the linked list. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + @param[in] FastReadInstruction The string of fast read instruction. + @param[in] FastReadModeClk The string of fast read mode clock. + @param[in] FastReadDummyClk The string of fast read dummy clock. + +**/ +VOID +CreateSpiFastReadTableEntry ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN UINT32 FastReadInstruction, + IN UINT32 FastReadModeClk, + IN UINT32 FastReadDummyClk + ) +{ + SFPD_FAST_READ_CAPBILITY_RECORD *CapabilityEntry; + + CapabilityEntry = AllocateZeroPool (sizeof (SFPD_FAST_READ_CAPBILITY_RECORD)); + if (CapabilityEntry == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Failed to create fast read table\n", __func__)); + ASSERT (FALSE); + return; + } + + InitializeListHead (&CapabilityEntry->NextFastReadCap); + CapabilityEntry->FastReadInstruction = (UINT8)FastReadInstruction; + CapabilityEntry->ModeClocks = (UINT8)FastReadModeClk; + CapabilityEntry->WaitStates = (UINT8)FastReadDummyClk; + InsertTailList (&Instance->FastReadTableList, &CapabilityEntry->NextFastReadCap); + DEBUG ((DEBUG_VERBOSE, "%a: Create and link table.\n", __func__)); + DEBUG ((DEBUG_VERBOSE, " Instruction : 0x%x\n", FastReadInstruction)); + DEBUG ((DEBUG_VERBOSE, " Mode bits : 0x%x\n", FastReadModeClk)); + DEBUG ((DEBUG_VERBOSE, " Wait States (Dummy Clocks): 0x%x\n", FastReadDummyClk)); +} + +/** + Calculate erase type typical time. + + @param[in] SfdpEraseTypicalTime Erase type typical time indicated in + Basic Flash Parameter Table. + EraseTypicalTime [0:4] - Count + EraseTypicalTime [5:6] - Unit + 00b: 1ms + 01b: 16ms + 10b: 128ms + 11b: 1s + @param[in] SfdpEraseTimeMultiplier Multiplier from erase typical time. + @param[out] EraseTypicalTime Pointer to receive Erase typical time in milliseconds. + @param[out] EraseTimeout Pointer to receive Erase timeout in milliseconds. + + @retval Erase time in milliseconds. +**/ +VOID +CalculateEraseTiming ( + IN UINT32 SfdpEraseTypicalTime, + IN UINT32 SfdpEraseTimeMultiplier, + OUT UINT32 *EraseTypicalTime, + OUT UINT64 *EraseTimeout + ) +{ + UINT32 UnitInMs; + + UnitInMs = (SfdpEraseTypicalTime & ERASE_TYPICAL_TIME_UNITS_MASK) >> ERASE_TYPICAL_TIME_BIT_POSITION; + switch (UnitInMs) { + case ERASE_TYPICAL_TIME_UNIT_1_MS_BITMAP: + UnitInMs = ERASE_TYPICAL_TIME_UNIT_1_MS; + break; + + case ERASE_TYPICAL_TIME_UNIT_16_MS_BITMAP: + UnitInMs = ERASE_TYPICAL_TIME_UNIT_16_MS; + break; + + case ERASE_TYPICAL_TIME_UNIT_128_MS_BITMAP: + UnitInMs = ERASE_TYPICAL_TIME_UNIT_128_MS; + break; + + case ERASE_TYPICAL_TIME_UNIT_1000_MS_BITMAP: + UnitInMs = ERASE_TYPICAL_TIME_UNIT_1000_MS; + break; + default: + DEBUG ((DEBUG_ERROR, "%a: Unsupported Erase Typical time.\n", __func__)); + ASSERT (FALSE); + } + + *EraseTypicalTime = UnitInMs * ((SfdpEraseTypicalTime & ERASE_TYPICAL_TIME_COUNT_MASK) + 1); + *EraseTimeout = 2 * (SfdpEraseTimeMultiplier + 1) * *EraseTypicalTime; + return; +} + +/** + Print out the erase type information. + + @param[in] SupportedEraseType Pointer to SFDP_SUPPORTED_ERASE_TYPE_RECORD. +**/ +VOID +DebugPrintEraseType ( + IN SFDP_SUPPORTED_ERASE_TYPE_RECORD *SupportedEraseType + ) +{ + DEBUG ((DEBUG_VERBOSE, " Erase Type %d\n", SupportedEraseType->EraseType)); + DEBUG ((DEBUG_VERBOSE, " Erase Type instruction: 0x%x\n", SupportedEraseType->EraseInstruction)); + DEBUG ((DEBUG_VERBOSE, " Erase size: 0x%x bytes\n", SupportedEraseType->EraseSizeInByte)); + DEBUG ((DEBUG_VERBOSE, " Erase time: %d Milliseconds\n", SupportedEraseType->EraseTypicalTime)); + DEBUG ((DEBUG_VERBOSE, " Erase timeout: %d Milliseconds:\n", SupportedEraseType->EraseTimeout)); +} + +/** + Insert supported erase type entry. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + @param[in] SupportedEraseType Pointer to SFDP_SUPPORTED_ERASE_TYPE_RECORD. +**/ +VOID +CreateEraseTypeEntry ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_SUPPORTED_ERASE_TYPE_RECORD *SupportedEraseType + ) +{ + InitializeListHead (&SupportedEraseType->NextEraseType); + InsertTailList (&Instance->SupportedEraseTypes, &SupportedEraseType->NextEraseType); + + DEBUG ((DEBUG_VERBOSE, "%a: Erase Type 0x%x is supported:\n", __func__, SupportedEraseType->EraseType)); + DebugPrintEraseType (SupportedEraseType); +} + +/** + Build up the erase type tables. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + +**/ +VOID +BuildUpEraseTypeTable ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + SFDP_SUPPORTED_ERASE_TYPE_RECORD *SupportedEraseType; + + // Build up erase type 1 entry. + if (Instance->SfdpBasicFlash->Erase1Size != 0) { + SupportedEraseType = AllocateZeroPool (sizeof (SFDP_SUPPORTED_ERASE_TYPE_RECORD)); + if (SupportedEraseType != NULL) { + SupportedEraseType->EraseType = SFDP_ERASE_TYPE_1; + SupportedEraseType->EraseInstruction = (UINT8)Instance->SfdpBasicFlash->Erase1Instr; + SupportedEraseType->EraseSizeInByte = (UINT32)1 << Instance->SfdpBasicFlash->Erase1Size; + CalculateEraseTiming ( + Instance->SfdpBasicFlash->Erase1Time, + Instance->SfdpBasicFlash->EraseMultiplier, + &SupportedEraseType->EraseTypicalTime, + &SupportedEraseType->EraseTimeout + ); + CreateEraseTypeEntry (Instance, SupportedEraseType); + } else { + DEBUG ((DEBUG_ERROR, "%a: Memory allocated failed for SFDP_SUPPORTED_ERASE_TYPE_RECORD (Type 1).\n", __func__)); + ASSERT (FALSE); + } + } + + // Build up erase type 2 entry. + if (Instance->SfdpBasicFlash->Erase2Size != 0) { + SupportedEraseType = AllocateZeroPool (sizeof (SFDP_SUPPORTED_ERASE_TYPE_RECORD)); + if (SupportedEraseType != NULL) { + SupportedEraseType->EraseType = SFDP_ERASE_TYPE_2; + SupportedEraseType->EraseInstruction = (UINT8)Instance->SfdpBasicFlash->Erase2Instr; + SupportedEraseType->EraseSizeInByte = (UINT32)1 << Instance->SfdpBasicFlash->Erase2Size; + CalculateEraseTiming ( + Instance->SfdpBasicFlash->Erase2Time, + Instance->SfdpBasicFlash->EraseMultiplier, + &SupportedEraseType->EraseTypicalTime, + &SupportedEraseType->EraseTimeout + ); + CreateEraseTypeEntry (Instance, SupportedEraseType); + } else { + DEBUG ((DEBUG_ERROR, "%a: Memory allocated failed for SFDP_SUPPORTED_ERASE_TYPE_RECORD (Type 2).\n", __func__)); + ASSERT (FALSE); + } + } + + // Build up erase type 3 entry. + if (Instance->SfdpBasicFlash->Erase3Size != 0) { + SupportedEraseType = AllocateZeroPool (sizeof (SFDP_SUPPORTED_ERASE_TYPE_RECORD)); + if (SupportedEraseType != NULL) { + SupportedEraseType->EraseType = SFDP_ERASE_TYPE_3; + SupportedEraseType->EraseInstruction = (UINT8)Instance->SfdpBasicFlash->Erase3Instr; + SupportedEraseType->EraseSizeInByte = (UINT32)1 << Instance->SfdpBasicFlash->Erase3Size; + CalculateEraseTiming ( + Instance->SfdpBasicFlash->Erase3Time, + Instance->SfdpBasicFlash->EraseMultiplier, + &SupportedEraseType->EraseTypicalTime, + &SupportedEraseType->EraseTimeout + ); + CreateEraseTypeEntry (Instance, SupportedEraseType); + } else { + DEBUG ((DEBUG_ERROR, "%a: Memory allocated failed for SFDP_SUPPORTED_ERASE_TYPE_RECORD (Type 3).\n", __func__)); + ASSERT (FALSE); + } + } + + // Build up erase type 4 entry. + if (Instance->SfdpBasicFlash->Erase4Size != 0) { + SupportedEraseType = AllocateZeroPool (sizeof (SFDP_SUPPORTED_ERASE_TYPE_RECORD)); + if (SupportedEraseType != NULL) { + SupportedEraseType->EraseType = SFDP_ERASE_TYPE_4; + SupportedEraseType->EraseInstruction = (UINT8)Instance->SfdpBasicFlash->Erase4Instr; + SupportedEraseType->EraseSizeInByte = (UINT32)1 << Instance->SfdpBasicFlash->Erase4Size; + CalculateEraseTiming ( + Instance->SfdpBasicFlash->Erase4Time, + Instance->SfdpBasicFlash->EraseMultiplier, + &SupportedEraseType->EraseTypicalTime, + &SupportedEraseType->EraseTimeout + ); + CreateEraseTypeEntry (Instance, SupportedEraseType); + } else { + DEBUG ((DEBUG_ERROR, "%a: Memory allocated failed for SFDP_SUPPORTED_ERASE_TYPE_RECORD (Type 4).\n", __func__)); + ASSERT (FALSE); + } + } +} + +/** + This function check if the erase type is one of the target erase types. + + @param[in] EraseType The erase type. + @param[in] TargetTypeNum Number of target search types. + @param[in] TargetTypes Target types. + + + @retval TRUE Yes, this is the target erase type. + @retval FALSE No, this is not the target erase type. + +**/ +BOOLEAN +IsTargetEraseType ( + IN UINT16 EraseType, + IN UINT8 TargetTypeNum, + IN UINT8 *TargetTypes + ) +{ + UINT8 Index; + + for (Index = 0; Index < TargetTypeNum; Index++) { + if (EraseType == *(TargetTypes + Index)) { + return TRUE; + } + } + + return FALSE; +} + +/** + Search the erase type record according to the given search type and value. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + @param[in] SearchType Search type. + @param[in] SearchValue The value of according to search type. + - For SearchEraseTypeByCommand: + SearchValue is the erase instruction. + - For SearchEraseTypeBySize: + SearchValue is the erase block size. + - For SearchEraseTypeBySmallestSize: + SearchValue is not used. + - For SearchEraseTypeByBiggestSize: + SearchValue is not used. + @param[in] SupportedTypeTargetNum Only search the specific erase types. + @param[in] SupportedTypeTarget Pointer to SupportedTypeTargetNum of + supported erase types. + @param[out] EraseTypeRecord Pointer to receive the erase type record. + + @retval EFI_SUCCESS Pointer to erase type record is returned. + EFI_INVALID_PARAMETER Invalid SearchType. + EFI_NOT_FOUND Erase type not found. +**/ +EFI_STATUS +GetEraseTypeRecord ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_SEARCH_ERASE_TYPE SearchType, + IN UINT32 SearchValue, + IN UINT8 SupportedTypeTargetNum, + IN UINT8 *SupportedTypeTarget OPTIONAL, + OUT SFDP_SUPPORTED_ERASE_TYPE_RECORD **EraseTypeRecord + ) +{ + SFDP_SUPPORTED_ERASE_TYPE_RECORD *EraseType; + UINT32 ValueToCompare; + BOOLEAN ExitSearching; + + if (IsListEmpty (&Instance->SupportedEraseTypes)) { + return EFI_NOT_FOUND; + } + + *EraseTypeRecord = NULL; + + // + // Initial the comapre value. + // + switch (SearchType) { + case SearchEraseTypeByType: + case SearchEraseTypeByCommand: + case SearchEraseTypeBySize: + break; + case SearchEraseTypeBySmallestSize: + ValueToCompare = (UINT32)-1; + break; + case SearchEraseTypeByBiggestSize: + ValueToCompare = 0; + break; + default: + return EFI_INVALID_PARAMETER; + } + + ExitSearching = FALSE; + EraseType = (SFDP_SUPPORTED_ERASE_TYPE_RECORD *)GetFirstNode (&Instance->SupportedEraseTypes); + while (TRUE) { + if ((SupportedTypeTarget == NULL) || IsTargetEraseType (EraseType->EraseType, SupportedTypeTargetNum, SupportedTypeTarget)) { + switch (SearchType) { + case SearchEraseTypeByType: + if (EraseType->EraseType == SearchValue) { + *EraseTypeRecord = EraseType; + ExitSearching = TRUE; + } + + break; + + case SearchEraseTypeBySize: + if (EraseType->EraseSizeInByte == SearchValue) { + *EraseTypeRecord = EraseType; + ExitSearching = TRUE; + } + + break; + + case SearchEraseTypeByCommand: + if (EraseType->EraseInstruction == (UINT8)SearchValue) { + *EraseTypeRecord = EraseType; + ExitSearching = TRUE; + } + + break; + + case SearchEraseTypeBySmallestSize: + if (EraseType->EraseSizeInByte < ValueToCompare) { + ValueToCompare = EraseType->EraseSizeInByte; + *EraseTypeRecord = EraseType; + } + + break; + + case SearchEraseTypeByBiggestSize: + if (EraseType->EraseSizeInByte > ValueToCompare) { + ValueToCompare = EraseType->EraseSizeInByte; + *EraseTypeRecord = EraseType; + } + + break; + + default: + return EFI_INVALID_PARAMETER; + } + } + + if (IsNodeAtEnd (&Instance->SupportedEraseTypes, &EraseType->NextEraseType) || ExitSearching) { + break; + } + + EraseType = (SFDP_SUPPORTED_ERASE_TYPE_RECORD *)GetNextNode (&Instance->SupportedEraseTypes, &EraseType->NextEraseType); + } + + if (*EraseTypeRecord == NULL) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Get the erase block attribute for the target address. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] FlashRegion The region the flash address belong. + @param[in] FlashAddress The target flash address. + @param[in] RemainingSize Remaining size to erase. + @param[in, out] BlockSizeToErase Input - The block erase size for this continious blocks. + Output - The determined block size for erasing. + @param[in, out] BlockCountToErase Input - The expected blocks to erase. + Output - The determined number of blocks to erase. + @param[out] BlockEraseCommand The erase command used for this continious blocks. + @param[out] TypicalTime Pointer to receive the typical time in millisecond + to erase this erase type size. + @param[out] MaximumTimeout Pointer to receive the maximum timeout in millisecond + to erase this erase type size. + + @retval EFI_SUCCESS The erase block attribute is returned. + @retval EFI_DEVICE_ERROR No valid SFDP discovered. + @retval EFI_NOT_FOUND No valud erase block attribute found. + +**/ +EFI_STATUS +GetEraseBlockAttribute ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_SECTOR_REGION_RECORD *FlashRegion, + IN UINT32 FlashAddress, + IN UINT32 RemainingSize, + IN OUT UINT32 *BlockSizeToErase, + IN OUT UINT32 *BlockCountToErase, + OUT UINT8 *BlockEraseCommand, + OUT UINT32 *TypicalTime, + OUT UINT64 *MaximumTimeout + ) +{ + EFI_STATUS Status; + SFDP_SUPPORTED_ERASE_TYPE_RECORD *EraseType; + UINT32 EraseSize; + + DEBUG ((DEBUG_VERBOSE, "%a: Entry\n", __func__)); + + for (EraseSize = SIZE_2GB; EraseSize != 0; EraseSize = EraseSize >> 1) { + Status = GetEraseTypeRecord (Instance, SearchEraseTypeBySize, EraseSize, 0, NULL, &EraseType); + if (!EFI_ERROR (Status)) { + // Validate this erase type. + if (((FlashAddress & (EraseType->EraseSizeInByte - 1)) == 0) && + (RemainingSize >= EraseType->EraseSizeInByte)) + { + *BlockSizeToErase = EraseType->EraseSizeInByte; + *BlockCountToErase = 1; + *BlockEraseCommand = EraseType->EraseInstruction; + *TypicalTime = EraseType->EraseTypicalTime; + *MaximumTimeout = EraseType->EraseTimeout; + Status = EFI_SUCCESS; + break; + } + } + } + + if (EraseType == NULL) { + return EFI_DEVICE_ERROR; + } + + DEBUG ((DEBUG_VERBOSE, " Erase address at 0x%08x.\n", FlashAddress)); + DEBUG ((DEBUG_VERBOSE, " - Erase block size : 0x%08x.\n", *BlockSizeToErase)); + DEBUG ((DEBUG_VERBOSE, " - Erase block count : 0x%08x.\n", *BlockCountToErase)); + DEBUG ((DEBUG_VERBOSE, " - Erase block command: 0x%02x.\n", *BlockEraseCommand)); + DEBUG ((DEBUG_VERBOSE, " - Remaining size to erase: 0x%08x.\n", RemainingSize)); + DEBUG ((DEBUG_VERBOSE, " - Erase typical time: %d milliseconds.\n", *TypicalTime)); + DEBUG ((DEBUG_VERBOSE, " - Erase timeout: %d milliseconds.\n", *MaximumTimeout)); + return EFI_SUCCESS; +} + +/** + Get the erase block attribute for the target address. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] FlashAddress The target flash address. + @param[out] FlashRegion The target flash address. + + @retval EFI_SUCCESS The region is returned. + @retval EFI_INVALID_PARAMETER FlashAddress is not belong to any region. + @retval Otherwise Other errors. + +**/ +EFI_STATUS +GetRegionByFlashAddress ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN UINT32 FlashAddress, + OUT SFDP_SECTOR_REGION_RECORD **FlashRegion + ) +{ + SFDP_SECTOR_MAP_RECORD *SectorMapRecord; + SFDP_SECTOR_REGION_RECORD *RegionRecord; + + DEBUG ((DEBUG_VERBOSE, "%a: Entry\n", __func__)); + + SectorMapRecord = Instance->CurrentSectorMap; + if (SectorMapRecord == NULL) { + return EFI_DEVICE_ERROR; + } + + RegionRecord = (SFDP_SECTOR_REGION_RECORD *)GetFirstNode (&SectorMapRecord->RegionList); + while (TRUE) { + if ((FlashAddress >= RegionRecord->RegionAddress) && + (FlashAddress < RegionRecord->RegionAddress + RegionRecord->RegionTotalSize)) + { + *FlashRegion = RegionRecord; + return EFI_SUCCESS; + } + + if (IsNodeAtEnd (&SectorMapRecord->RegionList, &RegionRecord->NextRegion)) { + break; + } + + RegionRecord = (SFDP_SECTOR_REGION_RECORD *)GetNextNode (&SectorMapRecord->RegionList, &RegionRecord->NextRegion); + } + + return EFI_INVALID_PARAMETER; +} + +/** + Build up the Fast Read capability tables. The earlier linked table + in the linked list has the faster transfer. + NOTE: 1. The Quad input instructions mentioned in 21th DWOWRD + are not considered yet. + 2. Maximum speed options for certain Fast Read modes are + not considered yet. (e.g., 8D-8D-8D or 4S-4D-4D) + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + +**/ +VOID +BuildUpFastReadTable ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + // Build up the standard Fast Read + // This will be first picked for the ReadData. + // TODO: The mechanism to choose the advance fast read + // is not determined yet in this version of + // SpiNorFlash driver. + CreateSpiFastReadTableEntry ( + Instance, + SPI_FLASH_FAST_READ, + 0, + SPI_FLASH_FAST_READ_DUMMY * 8 + ); + + // Build up Fast Read table 1S-1S-4S + if (Instance->SfdpBasicFlash->FastRead114 != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead114Instr, + Instance->SfdpBasicFlash->FastRead114ModeClk, + Instance->SfdpBasicFlash->FastRead114Dummy + ); + } + + // Build up Fast Read table 1S-2S-2S + if (Instance->SfdpBasicFlash->FastRead122 != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead122Instr, + Instance->SfdpBasicFlash->FastRead122ModeClk, + Instance->SfdpBasicFlash->FastRead122Dummy + ); + } + + // Build up Fast Read table 2S-2S-2S + if (Instance->SfdpBasicFlash->FastRead222 != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead222Instr, + Instance->SfdpBasicFlash->FastRead222ModeClk, + Instance->SfdpBasicFlash->FastRead222Dummy + ); + } + + // Build up Fast Read table 1S-4S-4S + if (Instance->SfdpBasicFlash->FastRead144 != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead144Instr, + Instance->SfdpBasicFlash->FastRead144ModeClk, + Instance->SfdpBasicFlash->FastRead144Dummy + ); + } + + // Build up Fast Read table 4S-4S-4S + if (Instance->SfdpBasicFlash->FastRead444 != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead444Instr, + Instance->SfdpBasicFlash->FastRead444ModeClk, + Instance->SfdpBasicFlash->FastRead444Dummy + ); + } + + // Build up Fast Read table 1S-1S-8S + if (Instance->SfdpBasicFlash->FastRead118Instr != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead118Instr, + Instance->SfdpBasicFlash->FastRead118ModeClk, + Instance->SfdpBasicFlash->FastRead118Dummy + ); + } + + // Build up Fast Read table 1S-8S-8S + if (Instance->SfdpBasicFlash->FastRead188Instr != 0) { + CreateSpiFastReadTableEntry ( + Instance, + Instance->SfdpBasicFlash->FastRead188Instr, + Instance->SfdpBasicFlash->FastRead188ModeClk, + Instance->SfdpBasicFlash->FastRead188Dummy + ); + } +} + +/** + This function sets up the erase types supported + by this region. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + @param[in] RegionRecord Pointer to SFDP_SECTOR_REGION_RECORD of this + regions. + @retval EFI_SUCCESS Current sector map configuration is determined. + EFI_DEVICE_ERROR Current sector map configuration is not found. + +**/ +EFI_STATUS +SetupRegionEraseInfo ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_SECTOR_REGION_RECORD *RegionRecord + ) +{ + SFDP_SUPPORTED_ERASE_TYPE_RECORD *SupportedEraseType; + UINT32 MinimumEraseSize; + + if (IsListEmpty (&Instance->SupportedEraseTypes)) { + DEBUG ((DEBUG_ERROR, "%a: No erase type suppoted on the flash device.\n", __func__)); + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + MinimumEraseSize = (UINT32)-1; + SupportedEraseType = (SFDP_SUPPORTED_ERASE_TYPE_RECORD *)GetFirstNode (&Instance->SupportedEraseTypes); + while (TRUE) { + RegionRecord->SupportedEraseType[RegionRecord->SupportedEraseTypeNum] = (UINT8)SupportedEraseType->EraseType; + RegionRecord->SupportedEraseTypeNum++; + RegionRecord->EraseTypeBySizeBitmap |= SupportedEraseType->EraseSizeInByte; + if (MinimumEraseSize > SupportedEraseType->EraseSizeInByte) { + MinimumEraseSize = SupportedEraseType->EraseSizeInByte; + } + + if (IsNodeAtEnd (&Instance->SupportedEraseTypes, &SupportedEraseType->NextEraseType)) { + break; + } + + SupportedEraseType = (SFDP_SUPPORTED_ERASE_TYPE_RECORD *)GetNextNode (&Instance->SupportedEraseTypes, &SupportedEraseType->NextEraseType); + } + + RegionRecord->SectorSize = MinimumEraseSize; + RegionRecord->RegionTotalSize = Instance->FlashDeviceSize; + RegionRecord->RegionSectors = RegionRecord->RegionTotalSize / RegionRecord->SectorSize; + return EFI_SUCCESS; +} + +/** + Create a single flash sector map. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + @retval EFI_SUCCESS Current sector map configuration is determined. + EFI_DEVICE_ERROR Current sector map configuration is not found. + +**/ +EFI_STATUS +CreateSingleFlashSectorMap ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + SFDP_SECTOR_MAP_RECORD *SectorMapRecord; + SFDP_SECTOR_REGION_RECORD *RegionRecord; + UINTN EraseIndex; + + DEBUG ((DEBUG_VERBOSE, "%a: Entry:\n", __func__)); + SectorMapRecord = (SFDP_SECTOR_MAP_RECORD *)AllocateZeroPool (sizeof (SFDP_SECTOR_MAP_RECORD)); + if (SectorMapRecord == NULL) { + DEBUG ((DEBUG_ERROR, "%a: No memory resource for SFDP_SECTOR_MAP_DETECTION_RECORD.\n", __func__)); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + // Create SFDP_SECTOR_MAP_RECORD. + InitializeListHead (&SectorMapRecord->NextDescriptor); + InitializeListHead (&SectorMapRecord->RegionList); + SectorMapRecord->ConfigurationId = 0; + SectorMapRecord->RegionCount = 1; + InsertTailList (&Instance->ConfigurationMapList, &SectorMapRecord->NextDescriptor); + DEBUG ((DEBUG_VERBOSE, " Sector map configurations ID : 0x%x\n", SectorMapRecord->ConfigurationId)); + DEBUG ((DEBUG_VERBOSE, " Sector map configurations regions: %d\n", SectorMapRecord->RegionCount)); + + // Create SFDP_SECTOR_MAP_RECORD region record. + RegionRecord = (SFDP_SECTOR_REGION_RECORD *)AllocateZeroPool (sizeof (SFDP_SECTOR_REGION_RECORD)); + if (RegionRecord == NULL) { + DEBUG ((DEBUG_ERROR, "%a: No memory resource for SFDP_SECTOR_REGION_RECORD.\n", __func__)); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + InitializeListHead (&RegionRecord->NextRegion); + + RegionRecord->RegionAddress = 0; + // + // Setup erase information in the region record. + // + SetupRegionEraseInfo (Instance, RegionRecord); + + InsertTailList (&SectorMapRecord->RegionList, &RegionRecord->NextRegion); + + Instance->CurrentSectorMap = SectorMapRecord; + + DEBUG ((DEBUG_VERBOSE, " Region totoal size : 0x%x\n", RegionRecord->RegionTotalSize)); + DEBUG ((DEBUG_VERBOSE, " Region sector size : 0x%x\n", RegionRecord->SectorSize)); + DEBUG ((DEBUG_VERBOSE, " Region sectors : 0x%x\n", RegionRecord->RegionSectors)); + + for (EraseIndex = 0; EraseIndex < RegionRecord->SupportedEraseTypeNum; EraseIndex++) { + DEBUG ((DEBUG_VERBOSE, " Region erase type supported: 0x%x\n", RegionRecord->SupportedEraseType[EraseIndex])); + } + + return EFI_SUCCESS; +} + +/** + Set EraseBlockBytes in SPI NOR Flash Protocol + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The erase block size is returned. + @retval Otherwise Failed to get erase block size. + +**/ +EFI_STATUS +SetSectorEraseBlockSize ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + SFDP_SUPPORTED_ERASE_TYPE_RECORD *EraseTypeRecord; + + // Use the smallest size for the sector erase. + Status = GetEraseTypeRecord (Instance, SearchEraseTypeBySmallestSize, 0, 0, NULL, &EraseTypeRecord); + if (!EFI_ERROR (Status)) { + Instance->Protocol.EraseBlockBytes = EraseTypeRecord->EraseSizeInByte; + DEBUG ((DEBUG_VERBOSE, " Erase block size = 0x%08x\n", EraseTypeRecord->EraseSizeInByte)); + } + + return Status; +} + +/** + Get the current sector map configuration. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + + @retval EFI_SUCCESS Current sector map configuration is determined. + EFI_DEVICE_ERROR Current sector map configuration is not found. + +**/ +EFI_STATUS +GetCurrentSectorMapConfiguration ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + UINT8 AddressLength; + BOOLEAN UseAddress; + UINT32 DummyBytes; + UINT8 ReturnByte; + UINT8 ConfigurationId; + SFDP_SECTOR_MAP_RECORD *SectorMap; + SFDP_SECTOR_MAP_DETECTION_RECORD *CommandEntry; + + Instance->CurrentSectorMap = NULL; + if (!Instance->ConfigurationCommandsNeeded) { + // No command needed measn only one configuration for the flash device sector map. + Instance->CurrentSectorMap = (SFDP_SECTOR_MAP_RECORD *)GetFirstNode (&Instance->ConfigurationMapList); + return EFI_SUCCESS; + } + + // + // Send the command to collect interest bit. + // + ConfigurationId = 0; + CommandEntry = (SFDP_SECTOR_MAP_DETECTION_RECORD *)GetFirstNode (&Instance->ConfigurationCommandList); + while (TRUE) { + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + + // Read configuration byte. + AddressLength = SPI_ADDR_3BYTE_ONLY; + DummyBytes = 1; + if (CommandEntry->CommandAddressLength == SpdfConfigurationCommandAddress4Byte) { + AddressLength = SPI_ADDR_4BYTE_ONLY; + DummyBytes = 0; + } + + UseAddress = TRUE; + if (CommandEntry->CommandAddress == SpdfConfigurationCommandAddressNone) { + UseAddress = FALSE; + } + + TransactionBufferLength = FillWriteBuffer ( + Instance, + CommandEntry->CommandInstruction, + DummyBytes, + AddressLength, + UseAddress, + CommandEntry->CommandAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + 1, + &ReturnByte + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to read the configuration byte.\n", __func__)); + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + // + // Retrieve the interest bit. + // + if ((ReturnByte & CommandEntry->ConfigurationBitMask) != 0) { + ConfigurationId |= 0x01; + } + + if (IsNodeAtEnd (&Instance->ConfigurationCommandList, &CommandEntry->NextCommand)) { + break; + } + + CommandEntry = (SFDP_SECTOR_MAP_DETECTION_RECORD *)GetNextNode (&Instance->ConfigurationCommandList, &CommandEntry->NextCommand); + ConfigurationId = ConfigurationId << 1; + } + + // + // Now we have current activated configuration ID in ConfigurationId. + // Walk through ConfigurationMapList to record the activated flash sector + // map configuration. + // + SectorMap = (SFDP_SECTOR_MAP_RECORD *)GetFirstNode (&Instance->ConfigurationMapList); + while (TRUE) { + if (SectorMap->ConfigurationId == ConfigurationId) { + Instance->CurrentSectorMap = SectorMap; + break; + } + + if (IsNodeAtEnd (&Instance->ConfigurationMapList, &SectorMap->NextDescriptor)) { + break; + } + + SectorMap = (SFDP_SECTOR_MAP_RECORD *)GetNextNode (&Instance->ConfigurationMapList, &SectorMap->NextDescriptor); + } + + if (Instance->CurrentSectorMap == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Activated flash sector map is not found!\n", __func__)); + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Build sector map configurations. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + + @retval EFI_SUCCESS Records of sector map configuration command and map + descriptor are built up successfully. + EFI_OUT_OF_RESOURCES Not enough memory resource. + EFI_DEVICE_ERROR SFDP Sector Map Parameter is not + constructed correctly. + +**/ +EFI_STATUS +BuildSectorMapCommandAndMap ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + SFDP_SECTOR_MAP_TABLE *SfdpSectorMapTable; + SFDP_SECTOR_CONFIGURATION_COMMAND *SfdpDetectionCommand; + SFDP_SECTOR_MAP_DETECTION_RECORD *CommandEntry; + SFDP_SECTOR_CONFIGURATION_MAP *SfdpConfigurationMap; + SFDP_SECTOR_MAP_RECORD *SectorMapRecord; + SFDP_SECTOR_REGION *SpdfSectorRegion; + SFDP_SECTOR_REGION_RECORD *RegionRecord; + SFDP_SUPPORTED_ERASE_TYPE_RECORD *SupportedEraseType; + UINT8 RegionCount; + UINT8 EraseTypeCount; + UINT32 MinimumEraseSize; + UINT32 RegionAddress; + + SfdpSectorMapTable = Instance->SfdpFlashSectorMap; + SfdpConfigurationMap = &SfdpSectorMapTable->ConfigurationMap; + SfdpDetectionCommand = &SfdpSectorMapTable->ConfigurationCommand; + + if (SfdpSectorMapTable->GenericHeader.DescriptorType == SFDP_SECTOR_MAP_TABLE_ENTRY_TYPE_MAP) { + // No configuration detection commands are needs. + Instance->ConfigurationCommandsNeeded = FALSE; + } else { + DEBUG ((DEBUG_VERBOSE, "%a: Sector map configuration detection command is needed\n", __func__)); + Instance->ConfigurationCommandsNeeded = TRUE; + + // Go through the section map detection commands. + while (TRUE) { + CommandEntry = (SFDP_SECTOR_MAP_DETECTION_RECORD *)AllocateZeroPool (sizeof (SFDP_SECTOR_MAP_DETECTION_RECORD)); + if (CommandEntry == NULL) { + DEBUG ((DEBUG_ERROR, "%a: No memory resource for SFDP_SECTOR_MAP_DETECTION_RECORD.\n", __func__)); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + InitializeListHead (&CommandEntry->NextCommand); + CommandEntry->CommandAddress = SfdpDetectionCommand->CommandAddress; + CommandEntry->CommandAddressLength = (SPDF_CONFIGURATION_COMMAND_ADDR_LENGTH)SfdpDetectionCommand->DetectionCommandAddressLen; + CommandEntry->CommandInstruction = (UINT8)SfdpDetectionCommand->DetectionInstruction; + CommandEntry->ConfigurationBitMask = (UINT8)SfdpDetectionCommand->ReadDataMask; + CommandEntry->LatencyInClock = (UINT8)SfdpDetectionCommand->DetectionLatency; + InsertTailList (&Instance->ConfigurationCommandList, &CommandEntry->NextCommand); + DEBUG ((DEBUG_VERBOSE, " Command instruction : 0x%x\n", CommandEntry->CommandInstruction)); + DEBUG ((DEBUG_VERBOSE, " Bit selection : 0x%x\n", CommandEntry->ConfigurationBitMask)); + DEBUG ((DEBUG_VERBOSE, " Command address : 0x%x\n", CommandEntry->CommandAddress)); + DEBUG ((DEBUG_VERBOSE, " Command address length: %d\n", CommandEntry->CommandAddressLength)); + DEBUG ((DEBUG_VERBOSE, " Command latency clocks: %d\n\n", CommandEntry->LatencyInClock)); + if (SfdpDetectionCommand->DescriptorEnd == SFDP_SECTOR_MAP_TABLE_ENTRY_LAST) { + break; + } + + SfdpDetectionCommand++; + } + + SfdpConfigurationMap = (SFDP_SECTOR_CONFIGURATION_MAP *)SfdpDetectionCommand++; + } + + // + // Go through the region table pointed in SfdpConfigurationMap. + // + if (SfdpConfigurationMap->DescriptorType != SFDP_SECTOR_MAP_TABLE_ENTRY_TYPE_MAP) { + DEBUG ((DEBUG_ERROR, "%a: Incorrect format of Sector Map Parameter.\n", __func__)); + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + while (TRUE) { + DEBUG ((DEBUG_VERBOSE, "%a: Sector map configurations:\n", __func__)); + SectorMapRecord = (SFDP_SECTOR_MAP_RECORD *)AllocateZeroPool (sizeof (SFDP_SECTOR_MAP_RECORD)); + if (SectorMapRecord == NULL) { + DEBUG ((DEBUG_ERROR, "%a: No memory resource for SFDP_SECTOR_MAP_DETECTION_RECORD.\n", __func__)); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + InitializeListHead (&SectorMapRecord->NextDescriptor); + InitializeListHead (&SectorMapRecord->RegionList); + SectorMapRecord->ConfigurationId = (UINT8)SfdpConfigurationMap->ConfigurationID; + SectorMapRecord->RegionCount = (UINT8)SfdpConfigurationMap->RegionCount; + InsertTailList (&Instance->ConfigurationMapList, &SectorMapRecord->NextDescriptor); + DEBUG ((DEBUG_VERBOSE, " Sector map configurations ID : 0x%x\n", SectorMapRecord->ConfigurationId)); + DEBUG ((DEBUG_VERBOSE, " Sector map configurations regions: %d\n", SectorMapRecord->RegionCount)); + SpdfSectorRegion = (SFDP_SECTOR_REGION *)SfdpConfigurationMap + 1; + RegionAddress = 0; + for (RegionCount = 0; RegionCount < SectorMapRecord->RegionCount; RegionCount++) { + RegionRecord = (SFDP_SECTOR_REGION_RECORD *)AllocateZeroPool (sizeof (SFDP_SECTOR_REGION_RECORD)); + if (RegionRecord == NULL) { + DEBUG ((DEBUG_ERROR, "%a: No memory resource for SFDP_SECTOR_MAP_DETECTION_RECORD.\n", __func__)); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + InitializeListHead (&RegionRecord->NextRegion); + RegionRecord->RegionTotalSize = (SpdfSectorRegion->RegionSize + 1) * SFDP_SECTOR_REGION_SIZE_UNIT; + // + // Construct erase type supported for this region. + // + if (SpdfSectorRegion->EraseType1 != 0) { + RegionRecord->SupportedEraseType[RegionRecord->SupportedEraseTypeNum] = SFDP_ERASE_TYPE_1; + RegionRecord->SupportedEraseTypeNum++; + } + + if (SpdfSectorRegion->EraseType2 != 0) { + RegionRecord->SupportedEraseType[RegionRecord->SupportedEraseTypeNum] = SFDP_ERASE_TYPE_2; + RegionRecord->SupportedEraseTypeNum++; + } + + if (SpdfSectorRegion->EraseType3 != 0) { + RegionRecord->SupportedEraseType[RegionRecord->SupportedEraseTypeNum] = SFDP_ERASE_TYPE_3; + RegionRecord->SupportedEraseTypeNum++; + } + + if (SpdfSectorRegion->EraseType4 != 0) { + RegionRecord->SupportedEraseType[RegionRecord->SupportedEraseTypeNum] = SFDP_ERASE_TYPE_4; + RegionRecord->SupportedEraseTypeNum++; + } + + // + // Calculate the sector size and total sectors. + // + if (IsListEmpty (&Instance->SupportedEraseTypes)) { + DEBUG ((DEBUG_ERROR, "%a: No erase type suppoted on the flash device.\n", __func__)); + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + MinimumEraseSize = (UINT32)-1; + for (EraseTypeCount = 0; EraseTypeCount < RegionRecord->SupportedEraseTypeNum++; EraseTypeCount++) { + // + // Walk through Instance->SupportedEraseTypes to find the matching erase type and + // Use the minimum erase size as the sector size; + // + SupportedEraseType = (SFDP_SUPPORTED_ERASE_TYPE_RECORD *)GetFirstNode (&Instance->SupportedEraseTypes); + while (TRUE) { + if (RegionRecord->SupportedEraseType[EraseTypeCount] == SupportedEraseType->EraseType) { + // Set erase size bitmap. + RegionRecord->EraseTypeBySizeBitmap |= SupportedEraseType->EraseSizeInByte; + + if (MinimumEraseSize > SupportedEraseType->EraseSizeInByte) { + MinimumEraseSize = SupportedEraseType->EraseSizeInByte; + break; + } + } + + if (IsNodeAtEnd (&Instance->SupportedEraseTypes, &SupportedEraseType->NextEraseType)) { + break; + } + + SupportedEraseType = (SFDP_SUPPORTED_ERASE_TYPE_RECORD *)GetNextNode (&Instance->SupportedEraseTypes, &SupportedEraseType->NextEraseType); + } + } + + RegionRecord->SectorSize = MinimumEraseSize; + RegionRecord->RegionSectors = RegionRecord->RegionTotalSize / RegionRecord->SectorSize; + RegionRecord->RegionAddress = RegionAddress; + + // Insert to link. + InsertTailList (&SectorMapRecord->RegionList, &RegionRecord->NextRegion); + DEBUG ((DEBUG_VERBOSE, " Region: %d\n", RegionCount)); + DEBUG ((DEBUG_VERBOSE, " Region totoal size: 0x%x\n", RegionRecord->RegionTotalSize)); + DEBUG ((DEBUG_VERBOSE, " Region sector size: 0x%x\n", RegionRecord->SectorSize)); + DEBUG ((DEBUG_VERBOSE, " Region sectors : 0x%x\n", RegionRecord->RegionSectors)); + DEBUG ((DEBUG_VERBOSE, " Region erase supported bitmap: 0x%x\n", RegionRecord->EraseTypeBySizeBitmap)); + + SpdfSectorRegion++; + RegionAddress += RegionRecord->RegionTotalSize; + } + + if (SfdpConfigurationMap->DescriptorEnd == SFDP_SECTOR_MAP_TABLE_ENTRY_LAST) { + break; + } + + SfdpConfigurationMap = (SFDP_SECTOR_CONFIGURATION_MAP *)SpdfSectorRegion; + } + + return EFI_SUCCESS; +} + +/** + This routine get Write Enable latch command. + + @param[in] Instance SPI Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + +**/ +VOID +GetWriteEnableCommand ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + // + // Set Wrtie Enable command. + // + Instance->WriteEnableLatchRequired = TRUE; + Instance->WriteEnableLatchCommand = SPI_FLASH_WREN; + if (Instance->SfdpBasicFlash->VolatileStatusBlockProtect == 1) { + if (Instance->SfdpBasicFlash->WriteEnableVolatileStatus == 0) { + Instance->WriteEnableLatchCommand = SPI_FLASH_WREN_50H; + } + } + + DEBUG ((DEBUG_ERROR, "%a: Use Write Enable Command 0x%x.\n", __func__, Instance->WriteEnableLatchCommand)); +} + +/** + This routine returns the desired Fast Read mode. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in,out] FastReadInstruction Fast Read instruction, the input is + the default value. + @param[in,out] FastReadModeBits The operational mode bits. + @param[in,out] FastReadDummyClocks Fast Read wait state (Dummy clocks), the + input is the default value. + @param[out] FastReadStr Pointer to retrieve the human readable string + of fast read mode. + @retval EFI_SUCCESS The parameters are updated. + @retval EFI_NOT_FOUND No desired Fas Read mode found. + +**/ +EFI_STATUS +GetFastReadParameter ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN OUT UINT8 *FastReadInstruction, + IN OUT UINT8 *FastReadModeBits, + IN OUT UINT8 *FastReadDummyClocks + ) +{ + SFPD_FAST_READ_CAPBILITY_RECORD *FastReadEntry; + + if (IsListEmpty (&Instance->FastReadTableList)) { + return EFI_NOT_FOUND; + } + + FastReadEntry = (SFPD_FAST_READ_CAPBILITY_RECORD *)GetFirstNode (&Instance->FastReadTableList); + *FastReadInstruction = FastReadEntry->FastReadInstruction; + *FastReadDummyClocks = FastReadEntry->WaitStates; + *FastReadModeBits = FastReadEntry->ModeClocks; + + // + // *FastReadOperationClock may be replaced by 8D-8D-8D or 4S-4D-4D Fast Read + // mode clock operation mode. Which is not cosidered in the implementation yet. + // + return EFI_SUCCESS; +} + +/** + Return the flash device size from SFDP Basic Flash Parameter Table DWORD 2 + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + + @retval UINT32 Flash device size in byte, zero indicates error. + +**/ +UINT32 +SfdpGetFlashSize ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + if (Instance == NULL) { + return 0; + } + + if ((Instance->SfdpBasicFlash->Density & SFDP_FLASH_MEMORY_DENSITY_4GBIT) == 0) { + // + // The flash device size is <= 256MB. + // + return (Instance->SfdpBasicFlash->Density + 1) / 8; + } + + // + // The flash deivce size is >= 512MB. + // Bit [0:30] defines 'N' where the density is computed as 2^N bits. + // N must be >=32 according to the SFDP specification. + // + if ((Instance->SfdpBasicFlash->Density & ~SFDP_FLASH_MEMORY_DENSITY_4GBIT) < 32) { + return 0; + } + + return (UINT32)RShiftU64 (LShiftU64 (1, Instance->SfdpBasicFlash->Density & ~SFDP_FLASH_MEMORY_DENSITY_4GBIT), 3); +} + +/** + Read SFDP Header + + This routine reads the JEDEC SPI Flash Discoverable Parameter header from the + SPI chip. Fails if Major Revision is not = 1 + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS Header is filled in + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +EFIAPI +ReadSfdpHeader ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + UINT32 TransactionBufferLength; + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + + // Read SFDP Header + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSFDP, + SPI_FLASH_RDSFDP_DUMMY, + SPI_FLASH_RDSFDP_ADDR_BYTES, + TRUE, + 0, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + sizeof (SFDP_HEADER), + (UINT8 *)&Instance->SfdpHeader + ); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + // Read Basic Flash Parameter Header + if ((Instance->SfdpHeader.Signature != SFDP_HEADER_SIGNATURE) || + (Instance->SfdpHeader.MajorRev != SFDP_SUPPORTED_MAJOR_REVISION)) + { + Status = EFI_DEVICE_ERROR; + } else { + DEBUG ((DEBUG_VERBOSE, "Total %d parameter headers\n", Instance->SfdpHeader.NumParameterHeaders + 1)); + } + } + + return Status; +} + +/** + Read SFDP + This routine reads the JEDEC SPI Flash Discoverable Parameters. We just + read the necessary tables in this routine. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS Header is filled in + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +ReadSfdp ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + SFDP_SUPPORTED_ERASE_TYPE_RECORD *EraseTypeRecord; + + InitializeListHead (&Instance->FastReadTableList); + InitializeListHead (&Instance->SupportedEraseTypes); + InitializeListHead (&Instance->ConfigurationCommandList); + InitializeListHead (&Instance->ConfigurationMapList); + + DEBUG ((DEBUG_VERBOSE, "%a: Entry\n", __func__)); + + Status = ReadSfdpHeader (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read SFDP header\n", __func__)); + ASSERT (FALSE); + return Status; + } + + Status = ReadSfdpBasicParameterTable (Instance); + if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read SFDP Basic Parameter Table\n", __func__)); + ASSERT (FALSE); + return Status; + } + + Instance->FlashDeviceSize = SfdpGetFlashSize (Instance); + DEBUG ((DEBUG_VERBOSE, "%a: Flash Size=0x%X\n", __func__, Instance->FlashDeviceSize)); + if (Instance->FlashDeviceSize == 0) { + ASSERT (FALSE); + return Status; + } + + Status = ReadSfdpSectorMapParameterTable (Instance); + if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read SFDP Sector Map Parameter Table\n", __func__)); + ASSERT (FALSE); + } else if (Status == EFI_NOT_FOUND) { + DEBUG ((DEBUG_VERBOSE, "%a: The SPI NOR flash device doesn't have SFDP Sector Map Parameter Table implemented:\n", __func__)); + + // + // No SFDP Sector Map Parameter Table exist. + // Check if device support the uniform 4K erase size. + // + Instance->Uniform4KEraseSupported = FALSE; + if (Instance->SfdpBasicFlash->EraseSizes == SPI_UNIFORM_4K_ERASE_SUPPORTED) { + DEBUG ((DEBUG_VERBOSE, "%a: The SPI NOR flash device supports uniform 4K erase.\n", __func__)); + + // Check if 4K erase type supported? + Status = GetEraseTypeRecord (Instance, SearchEraseTypeBySize, SIZE_4KB, 0, NULL, &EraseTypeRecord); + if (Status == EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR, "However, no corresponding 4K size erase type found.\n", __func__)); + ASSERT (FALSE); + } + + Instance->Uniform4KEraseSupported = TRUE; + } else { + // Uniform 4K erase unsupported, get the smallest erase block size. + DEBUG ((DEBUG_VERBOSE, "%a: The SPI NOR flash device doesn't support uniform 4K erase.\n", __func__)); + } + + // + // Build flash map + // Instance->ConfigurationMapList is an empty list because no FDP Sector Map Parameter Table. + // + CreateSingleFlashSectorMap (Instance); + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Read SFDP Specific Parameter Header + + This routine reads the JEDEC SPI Flash Discoverable Parameter header from the + SPI chip. Fails if Major Revision is not = SFDP_SUPPORTED_MAJOR_REVISION. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] SfdpHeader SFDP Header Buffer Pointer + @param[in] ParameterIdMsb Most significant byte of parameter ID. + @param[in] ParameterIdLsb Lowest significant byte of parameter ID. + + @retval EFI_SUCCESS Header is filled in + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + @retval EFI_NOT_FOUND Unsupported Parameter Header. + +**/ +EFI_STATUS +EFIAPI +ReadSfdpParameterHeader ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_PARAMETER_HEADER *SfdpParameterHeader, + IN UINT8 ParameterIdMsb, + IN UINT8 ParameterIdLsb + ) +{ + EFI_STATUS Status; + UINT32 Index; + SFDP_PARAMETER_HEADER LocalSfdpParameterHeader; + UINT32 TransactionBufferLength; + + DEBUG ((DEBUG_VERBOSE, "%a: Entry\n", __func__)); + DEBUG ((DEBUG_VERBOSE, " Looking for Parameter Header %02x:%02x\n", ParameterIdMsb, ParameterIdLsb)); + + // + // Parse Parameter Headers Starting at size eof SFDP_HEADER. + // SfdpHeader.NumParameterHeaders is zero based, 0 means 1 parameter header. + // + ZeroMem (SfdpParameterHeader, sizeof (SFDP_PARAMETER_HEADER)); + for (Index = 0; Index < Instance->SfdpHeader.NumParameterHeaders + 1; Index++) { + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSFDP, + SPI_FLASH_RDSFDP_DUMMY, + SPI_FLASH_RDSFDP_ADDR_BYTES, + TRUE, + sizeof (SFDP_HEADER) + Index * 8, // Parameter Header Index + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + sizeof (LocalSfdpParameterHeader), + (UINT8 *)&LocalSfdpParameterHeader + ); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + // Break if SfdParamHeader is Type 0, Basic SPI Protocol Parameters + DEBUG (( + DEBUG_VERBOSE, + " #%d Parameter Header: %02x:%02x, revision: %d.%d\n", + Index, + LocalSfdpParameterHeader.IdMsb, + LocalSfdpParameterHeader.IdLsb, + LocalSfdpParameterHeader.MajorRev, + LocalSfdpParameterHeader.MinorRev >= SfdpParameterHeader->MinorRev + )); + if ((LocalSfdpParameterHeader.IdLsb == ParameterIdLsb) && + (LocalSfdpParameterHeader.IdMsb == ParameterIdMsb) && + (LocalSfdpParameterHeader.MajorRev == (UINT32)SFDP_SUPPORTED_MAJOR_REVISION) && + (LocalSfdpParameterHeader.MinorRev >= SfdpParameterHeader->MinorRev)) + { + CopyMem ( + (VOID **)SfdpParameterHeader, + (VOID **)&LocalSfdpParameterHeader, + sizeof (SFDP_PARAMETER_HEADER) + ); + } + } else { + break; + } + } else { + break; + } + } + + if (Status != EFI_DEVICE_ERROR) { + if ((SfdpParameterHeader->IdLsb != ParameterIdLsb) || + (SfdpParameterHeader->IdMsb != ParameterIdMsb)) + { + DEBUG ((DEBUG_ERROR, " Parameter Header: %02x:%02x is not found.\n", ParameterIdMsb, ParameterIdLsb)); + Status = EFI_NOT_FOUND; + } + } + + return Status; +} + +/** + Read from SFDP table pointer + + This routine sends SPI_FLASH_RDSFDP command and reads parameter from the + given TablePointer. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] TablePointer Pointer to read data from SFDP. + @param[in] DestBuffer Destination buffer. + @param[in] LengthInBytes Length to read. + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + @retval Other errors + +**/ +EFI_STATUS +EFIAPI +SpiReadSfdpPtp ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN UINT32 TablePointer, + IN VOID *DestBuffer, + IN UINT32 LengthInBytes + ) +{ + EFI_STATUS Status; + UINT32 Length; + UINT8 *CurrentBuffer; + UINT32 ByteCounter; + UINT32 CurrentAddress; + UINT32 MaximumTransferBytes; + UINT32 TransactionBufferLength; + + Length = 0; + MaximumTransferBytes = Instance->SpiIo->MaximumTransferBytes; + CurrentBuffer = (UINT8 *)DestBuffer; + for (ByteCounter = 0; ByteCounter < LengthInBytes; ByteCounter += Length) { + CurrentAddress = TablePointer + ByteCounter; + Length = LengthInBytes - ByteCounter; + + // Length must be MaximumTransferBytes or less + if (Length > MaximumTransferBytes) { + Length = MaximumTransferBytes; + } + + // Check not WIP + Status = WaitNotWip (Instance, FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds), FixedPcdGet32 (PcdSpiNorFlashFixedTimeoutRetryCount)); + + // Read Data + if (!EFI_ERROR (Status)) { + TransactionBufferLength = FillWriteBuffer ( + Instance, + SPI_FLASH_RDSFDP, + SPI_FLASH_RDSFDP_DUMMY, + SPI_FLASH_RDSFDP_ADDR_BYTES, + TRUE, + CurrentAddress, + 0, + NULL + ); + Status = Instance->SpiIo->Transaction ( + Instance->SpiIo, + SPI_TRANSACTION_WRITE_THEN_READ, + FALSE, + 0, + 1, + 8, + TransactionBufferLength, + Instance->SpiTransactionWriteBuffer, + Length, + CurrentBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to read SFDP parameter.\n", __func__)); + ASSERT_EFI_ERROR (Status); + } + + CurrentBuffer += Length; + } else { + break; + } + } + + return Status; +} + +/** + Read SFDP Sector Map Parameter into buffer + + This routine reads the JEDEC SPI Flash Discoverable Parameters from the SPI + chip. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +ReadSfdpSectorMapParameterTable ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + SFDP_PARAMETER_HEADER SfdpParamHeader; + + Status = ReadSfdpParameterHeader ( + Instance, + &SfdpParamHeader, + SFDP_SECTOR_MAP_PARAMETER_ID_MSB, + SFDP_SECTOR_MAP_PARAMETER_ID_LSB + ); + if (!EFI_ERROR (Status)) { + // Read Sector Map Parameters. Already know it is MajorRev = SFDP_SUPPORTED_MAJOR_REVISION + Instance->SfdpSectorMapByteCount = SfdpParamHeader.Length * sizeof (UINT32); + Instance->SfdpFlashSectorMap = AllocateZeroPool (Instance->SfdpSectorMapByteCount); + if (Instance->SfdpFlashSectorMap != NULL) { + // Read from SFDP Parameter Table Pointer (PTP). + Status = SpiReadSfdpPtp ( + Instance, + SfdpParamHeader.TablePointer, + (VOID *)Instance->SfdpFlashSectorMap, + Instance->SfdpSectorMapByteCount + ); + if (!EFI_ERROR (Status)) { + Status = BuildSectorMapCommandAndMap (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to build sector map command and descriptor.\n", __func__)); + ASSERT (FALSE); + Status = GetCurrentSectorMapConfiguration (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to get current sector map configuration.\n", __func__)); + ASSERT (FALSE); + } + } + } else { + FreePool (Instance->SfdpFlashSectorMap); + Instance->SfdpFlashSectorMap = NULL; + DEBUG ((DEBUG_ERROR, "%a: Fails to read SFDP Sector Map Parameter.\n", __func__)); + ASSERT (FALSE); + } + } else { + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to allocate memory for reading SFDP Sector Map Parameter.\n", __func__)); + ASSERT (FALSE); + } + } + } + + return Status; +} + +/** + Read SFDP Basic Parameters into buffer + + This routine reads the JEDEC SPI Flash Discoverable Parameters from the SPI + chip. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + @retval EFI_NOT_FOUND Parameter header is not found. + +**/ +EFI_STATUS +ReadSfdpBasicParameterTable ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + SFDP_PARAMETER_HEADER SfdpBasicFlashParamHeader; + + Status = ReadSfdpParameterHeader ( + Instance, + &SfdpBasicFlashParamHeader, + SFDP_BASIC_PARAMETER_ID_MSB, + SFDP_BASIC_PARAMETER_ID_LSB + ); + if (!EFI_ERROR (Status)) { + // Read Basic Flash Parameters. Already know it is MajorRev = SFDP_SUPPORTED_MAJOR_REVISION + Instance->SfdpBasicFlashByteCount = SfdpBasicFlashParamHeader.Length * sizeof (UINT32); + Instance->SfdpBasicFlash = AllocateZeroPool (Instance->SfdpBasicFlashByteCount); + if (Instance->SfdpBasicFlash != NULL) { + // Read from SFDP Parameter Table Pointer (PTP). + Status = SpiReadSfdpPtp ( + Instance, + SfdpBasicFlashParamHeader.TablePointer, + (VOID *)Instance->SfdpBasicFlash, + Instance->SfdpBasicFlashByteCount + ); + if (!EFI_ERROR (Status)) { + GetWriteEnableCommand (Instance); + // + // Build the Fast Read capability table according to + // the Basic Flash Parameter Table. + // + BuildUpFastReadTable (Instance); + BuildUpEraseTypeTable (Instance); // Build up erase type and size. + + // Set current address bytes to 3-Bytes. + Instance->CurrentAddressBytes = 3; + } else { + FreePool (Instance->SfdpBasicFlash); + Instance->SfdpBasicFlash = NULL; + DEBUG ((DEBUG_ERROR, "%a: Fails to read SFDP Basic Parameter.\n", __func__)); + ASSERT (FALSE); + } + } else { + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to allocate memory for reading SFDP Basic Parameter.\n", __func__)); + ASSERT (FALSE); + } + } + } + + return Status; +} + +/** + Initial SPI_NOR_FLASH_INSTANCE structure. + + @param[in] Instance Pointer to SPI_NOR_FLASH_INSTANCE. + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS SPI_NOR_FLASH_INSTANCE is initialized according to + SPI NOR Flash SFDP specification. + @retval EFI_INVALID_PARAMETER Instance = NULL or + Instance->SpiIo == NULL or + Instance->SpiIo->SpiPeripheral == NULL or + Instance->SpiIo->SpiPeripheral->SpiBus == NULL or + Instance->SpiIo->SpiPeripheral->SpiBus->ControllerPath. + @retval Otherwise Failed to initial SPI_NOR_FLASH_INSTANCE structure. + +**/ +EFI_STATUS +InitialSpiNorFlashSfdpInstance ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + EFI_SPI_NOR_FLASH_PROTOCOL *Protocol; + + if (Instance == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Instance is NULL.\n", __func__)); + return EFI_INVALID_PARAMETER; + } + + if ((Instance->SpiIo == NULL) || + (Instance->SpiIo->SpiPeripheral == NULL) || + (Instance->SpiIo->SpiPeripheral->SpiBus == NULL) + ) + { + DEBUG ((DEBUG_ERROR, "%a: One of SpiIo, SpiPeripheral and SpiBus is NULL.\n", __func__)); + return EFI_INVALID_PARAMETER; + } + + Instance->Signature = SPI_NOR_FLASH_SIGNATURE; + + // Allocate write buffer for SPI IO transactions with extra room for Opcode + // and Address with 10 bytes extra room. + Instance->SpiTransactionWriteBuffer = + AllocatePool (Instance->SpiIo->MaximumTransferBytes + 10); + + Protocol = &Instance->Protocol; + Protocol->SpiPeripheral = Instance->SpiIo->SpiPeripheral; + Protocol->GetFlashid = GetFlashId; + Protocol->ReadData = ReadData; // Fast Read transfer + Protocol->LfReadData = LfReadData; // Normal Read transfer + Protocol->ReadStatus = ReadStatus; + Protocol->WriteStatus = WriteStatus; + Protocol->WriteData = WriteData; + Protocol->Erase = Erase; + Status = Protocol->GetFlashid (Protocol, (UINT8 *)&Protocol->Deviceid); + ASSERT_EFI_ERROR (Status); + DEBUG (( + DEBUG_VERBOSE, + "%a: Flash ID: Manufacturer=0x%02X, Device=0x%02X%02X\n", + __func__, + Protocol->Deviceid[0], + Protocol->Deviceid[1], + Protocol->Deviceid[2] + ) + ); + + Status = ReadSfdp (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to Read SFDP\n", __func__)); + ASSERT (FALSE); + } + + // Get flash deivce size from SFDP. + Protocol->FlashSize = SfdpGetFlashSize (Instance); + DEBUG ((DEBUG_VERBOSE, "%a: Flash Size=0x%X\n", __func__, Protocol->FlashSize)); + if (Protocol->FlashSize == 0) { + ASSERT_EFI_ERROR (Status); + } + + // Set flash erase block size. + Status = SetSectorEraseBlockSize (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fails to get the smallest erase block size.\n", __func__)); + ASSERT (FALSE); + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..77ceaa481ecaf77bd10ac51019398827119994b0 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.c @@ -0,0 +1,260 @@ +/** @file + SPI NOR Flash JEDEC Serial Flash Discoverable Parameters (SFDP) + DXE driver. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - JEDEC Standard, JESD216F.02 + https://www.jedec.org/document_search?search_api_views_fulltext=JESD216 + + @par Glossary: + - SFDP - Serial Flash Discoverable Parameters + - PTP - Parameter Table Pointer +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiNorFlash.h" +#include "SpiNorFlashJedecSfdpInternal.h" + +/** + Function to create SPI_NOR_FLASH_INSTANCE for this SPI part. + + @param[in] SpiIoHandle The handle with SPI I/O protocol installed. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_OF_RESOURCES Not enough resource to create SPI_NOR_FLASH_INSTANCE. + @retval otherwise Fail to create SPI NOR Flash SFDP Instance +**/ +EFI_STATUS +CreateSpiNorFlashSfdpInstance ( + IN EFI_HANDLE SpiIoHandle + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + + // Allocate SPI_NOR_FLASH_INSTANCE Instance. + Instance = AllocateZeroPool (sizeof (SPI_NOR_FLASH_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // Locate the SPI IO Protocol + Status = gBS->HandleProtocol ( + SpiIoHandle, + &gEdk2JedecSfdpSpiDxeDriverGuid, + (VOID **)&Instance->SpiIo + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to locate SPI I/O protocol\n", __func__)); + FreePool (Instance); + } else { + Status = InitialSpiNorFlashSfdpInstance (Instance); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to initial SPI_NOR_FLASH_INSTANCE.\n", __func__)); + FreePool (Instance); + } else { + // Install SPI NOR Flash Protocol. + Status = gBS->InstallProtocolInterface ( + &Instance->Handle, + &gEfiSpiNorFlashProtocolGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to Install gEfiSpiNorFlashProtocolGuid protocol.\n", __func__)); + FreePool (Instance); + } + } + } + + return Status; +} + +/** + Callback function executed when the EFI_SPI_IO_PROTOCOL + protocol interface is installed. + + @param[in] Event Event whose notification function is being invoked. + @param[out] Context Pointer to SPI I/O protocol GUID. + +**/ +VOID +EFIAPI +SpiIoProtocolInstalledCallback ( + IN EFI_EVENT Event, + OUT VOID *Context + ) +{ + EFI_STATUS Status; + UINTN InstanceBufferSize; + EFI_HANDLE InstanceBuffer; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __func__)); + InstanceBufferSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle ( + ByRegisterNotify, + (EFI_GUID *)Context, + NULL, + &InstanceBufferSize, + &InstanceBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Can't locate SPI I/O protocol.\n", __func__)); + DEBUG ((DEBUG_INFO, "%a: Exit.\n", __func__)); + return; + } + + CreateSpiNorFlashSfdpInstance (InstanceBuffer); + DEBUG ((DEBUG_INFO, "%a: Exit.\n", __func__)); + return; +} + +/** + Register for the later installed SPI I/O protocol notification. + + @retval EFI_SUCCESS Succeed. + @retval otherwise Fail to register SPI I/O protocol installed + notification. +**/ +EFI_STATUS +RegisterSpioProtocolNotification ( + VOID + ) +{ + EFI_EVENT Event; + EFI_STATUS Status; + VOID *Registration; + + Status = gBS->CreateEvent ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SpiIoProtocolInstalledCallback, + NULL, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to create event for the SPI I/O Protocol installation.", __func__)); + return Status; + } + + Status = gBS->RegisterProtocolNotify ( + &gEdk2JedecSfdpSpiDxeDriverGuid, + Event, + &Registration + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to register event for the SPI I/O Protocol installation.", __func__)); + } else { + DEBUG ((DEBUG_INFO, "%a: Notification for SPI I/O Protocol installation was registered.", __func__)); + } + + return Status; +} + +/** + Entry point of the Macronix SPI NOR Flash driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND No gEdk2JedecSfdpSpiSmmDriverGuid installed on + system yet. + @retval EFI_OUT_OF_RESOURCES Not enough resource for SPI NOR Flash JEDEC SFDP + initialization. + @retval Otherwise Other errors. +**/ +EFI_STATUS +EFIAPI +SpiNorFlashJedecSfdpDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE *InstanceBuffer; + UINTN InstanceIndex; + UINTN InstanceBufferSize; + + DEBUG ((DEBUG_INFO, "%a - ENTRY\n", __func__)); + + // + // Register notification for the later SPI I/O protocol installation. + // + RegisterSpioProtocolNotification (); + DEBUG ((DEBUG_INFO, "Check if there were already some gEdk2JedecSfdpSpiDxeDriverGuid handles installed.\n")); + + // + // Check if there were already some gEdk2JedecSfdpSpiDxeDriverGuid + // handles installed. + // + // Locate the SPI I/O Protocol for the SPI flash part + // that supports JEDEC SFDP specification. + // + InstanceBufferSize = 0; + InstanceBuffer = NULL; + Status = gBS->LocateHandle ( + ByProtocol, + &gEdk2JedecSfdpSpiDxeDriverGuid, + NULL, + &InstanceBufferSize, + InstanceBuffer + ); + if (Status == EFI_NOT_FOUND) { + DEBUG (( + DEBUG_INFO, + "No gEdk2JedecSfdpSpiSmmDriverGuid handles found at the moment, wait for the notification of SPI I/O protocol installation.\n" + )); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return EFI_SUCCESS; + } else if (Status == EFI_BUFFER_TOO_SMALL) { + InstanceBuffer = (EFI_HANDLE *)AllocateZeroPool (InstanceBufferSize); + ASSERT (InstanceBuffer != NULL); + if (InstanceBuffer == NULL) { + DEBUG ((DEBUG_ERROR, "Not enough resource for gEdk2JedecSfdpSpiDxeDriverGuid handles.\n")); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return EFI_OUT_OF_RESOURCES; + } + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error to locate gEdk2JedecSfdpSpiDxeDriverGuid - Status = %r.\n", Status)); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return Status; + } + + Status = gBS->LocateHandle ( + ByProtocol, + &gEdk2JedecSfdpSpiDxeDriverGuid, + NULL, + &InstanceBufferSize, + InstanceBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to locate all gEdk2JedecSfdpSpiDxeDriverGuid handles.\n")); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return Status; + } + + DEBUG ((DEBUG_INFO, "%d of gEdk2JedecSfdpSpiDxeDriverGuid are found.\n", InstanceBufferSize / sizeof (EFI_HANDLE))); + for (InstanceIndex = 0; InstanceIndex < InstanceBufferSize / sizeof (EFI_HANDLE); InstanceIndex++) { + Status = CreateSpiNorFlashSfdpInstance (*(InstanceBuffer + InstanceIndex)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to create SPI NOR Flash SFDP instance #%d.\n", InstanceIndex)); + } + } + + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..5f30cf8a107f44c3d3eba55f8d3fb5ae0f479dae --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.inf @@ -0,0 +1,63 @@ +## @file +# The SPI NOR Flash JEDEC Serial Flash Discoverable Parameters (SFDP) +# DXE driver INF file. +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Revision Reference: +# - JEDEC Standard, JESD216F.02 +# https://www.jedec.org/document_search?search_api_views_fulltext=JESD216 +# +# @par Glossary: +# - SFDP - Serial Flash Discoverable Parameters +# - PTP - Parameter Table Pointer +## + +[Defines] + INF_VERSION = 1.25 + BASE_NAME = SpiNorFlashJedecSfdpDxe + FILE_GUID = 0DC9C2C7-D450-41BA-9CF7-D2090C35A797 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 1.10 + ENTRY_POINT = SpiNorFlashJedecSfdpDxeEntry + MODULE_UNI_FILE = SpiNorFlashJedecSfdpDxe.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + TimerLib + UefiDriverEntryPoint + UefiBootServicesTableLib + +[Sources] + SpiNorFlashJedecSfdpDxe.c + SpiNorFlash.c + SpiNorFlashJedecSfdp.c + SpiNorFlashJedecSfdpInternal.h + SpiNorFlash.h + +[Protocols] + gEfiSpiNorFlashProtocolGuid ## PROCUDES + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashFixedTimeoutRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Guids] + gEdk2JedecSfdpSpiDxeDriverGuid + +[Depex] + gEdk2JedecSfdpSpiDxeDriverGuid + +[UserExtensions.TianoCore."ExtraFiles"] + SpiNorFlashJedecSfdpExtra.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.uni b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.uni new file mode 100644 index 0000000000000000000000000000000000000000..544d56daf6cba94edf45308998beeda0dd277a78 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.uni @@ -0,0 +1,12 @@ +// /** @file +// SPI NOR Flash SFDP Localized Strings and Content. +// +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "EDK2 SPI NOR FLASH SFDP DXE driver" + +#string STR_MODULE_DESCRIPTION #language en-US "This driver provides SPI NOR FLASH Serial Flash Discoverable Parameter (SFDP) compatible flash device capability discovery." + diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpExtra.uni b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..dbf4c0d551255a800cc3abb74c193e1222a9b551 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpExtra.uni @@ -0,0 +1,10 @@ +// /** @file +// SPI NOR Flash SFDP Localized Strings and Content. +// +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "SPI NOR Flash driver for JEDEC Serial Flash Discoverable Parameters (SFDP) compliant SPI Flash Memory" diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpInternal.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpInternal.h new file mode 100644 index 0000000000000000000000000000000000000000..803bb48be050e9f0c1e63bf4d64d200d5974d247 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpInternal.h @@ -0,0 +1,298 @@ +/** @file + SPI NOR flash driver internal definitions. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_NOR_FLASH_INSTANCE_H_ +#define SPI_NOR_FLASH_INSTANCE_H_ + +#include +#include +#include +#include + +#define SPI_NOR_FLASH_SIGNATURE SIGNATURE_32 ('s', 'n', 'f', 'm') + +#define SPI_NOR_FLASH_FROM_THIS(a) CR (a, SPI_NOR_FLASH_INSTANCE, Protocol, SPI_NOR_FLASH_SIGNATURE) + +typedef struct { + LIST_ENTRY NextFastReadCap; ///< Link list to next Fast read capability + UINT8 FastReadInstruction; ///< Fast read instruction. + UINT8 ModeClocks; ///< Fast read clock. + UINT8 WaitStates; ///< Fast read wait dummy clocks +} SFPD_FAST_READ_CAPBILITY_RECORD; + +typedef struct { + LIST_ENTRY NextEraseType; ///< Link list to next erase type. + UINT16 EraseType; ///< Erase type this flash device supports. + UINT8 EraseInstruction; ///< Erase instruction + UINT32 EraseSizeInByte; ///< The size of byte in 2^EraseSize the erase type command + ///< can erase. + UINT32 EraseTypicalTime; ///< Time the device typically takes to erase this type + ///< size. + UINT64 EraseTimeout; ///< Maximum typical erase timeout. +} SFDP_SUPPORTED_ERASE_TYPE_RECORD; + +typedef enum { + SearchEraseTypeByType = 1, + SearchEraseTypeByCommand, + SearchEraseTypeBySize, + SearchEraseTypeBySmallestSize, + SearchEraseTypeByBiggestSize +} SFDP_SEARCH_ERASE_TYPE; + +typedef struct { + LIST_ENTRY NextCommand; ///< Link list to next detection command. + UINT32 CommandAddress; ///< Address to issue the command. + UINT8 CommandInstruction; ///< Detection command instruction. + UINT8 LatencyInClock; ///< Command latency in clocks. + SPDF_CONFIGURATION_COMMAND_ADDR_LENGTH CommandAddressLength; ///< Adddress length of detection command. + UINT8 ConfigurationBitMask; ///< The interest bit of the byte data retunred + ///< after sending the detection command. +} SFDP_SECTOR_MAP_DETECTION_RECORD; + +typedef struct { + LIST_ENTRY NextRegion; ///< Link list to the next region. + UINT32 RegionAddress; ///< Region starting address. + UINT32 RegionTotalSize; ///< Region total size in bytes. + UINT32 RegionSectors; ///< Sectors in this region. + UINT32 SectorSize; ///< Sector size in byte (Minimum blcok erase size) + UINT8 SupportedEraseTypeNum; ///< Number of erase type supported. + UINT8 SupportedEraseType[SFDP_ERASE_TYPES_NUMBER]; ///< Erase types supported. + UINT32 EraseTypeBySizeBitmap; ///< The bitmap of supoprted srase block sizes. + ///< from big to small. +} SFDP_SECTOR_REGION_RECORD; + +typedef struct { + LIST_ENTRY NextDescriptor; ///< Link list to next flash map descriptor. + UINT8 ConfigurationId; ///< The ID of this configuration. + UINT8 RegionCount; ///< The regions of this sector map configuration. + LIST_ENTRY RegionList; ///< The linked list of the regions. +} SFDP_SECTOR_MAP_RECORD; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SPI_NOR_FLASH_PROTOCOL Protocol; + EFI_SPI_IO_PROTOCOL *SpiIo; + UINT32 SfdpBasicFlashByteCount; + UINT32 SfdpSectorMapByteCount; + SFDP_BASIC_FLASH_PARAMETER *SfdpBasicFlash; + SFDP_SECTOR_MAP_TABLE *SfdpFlashSectorMap; + UINT8 *SpiTransactionWriteBuffer; + UINT32 SpiTransactionWriteBufferIndex; + // + // SFDP information. + // + SFDP_HEADER SfdpHeader; ///< SFDP header. + UINT32 FlashDeviceSize; ///< The total size of this flash device. + UINT8 CurrentAddressBytes; ///< The current address bytes. + + // + // This is a linked list in which the Fast Read capability tables + // are linked from the low performance transfer to higher performance + // transfer. The SPI read would use the first Fast Read entry for + // SPI read operation. + // + LIST_ENTRY FastReadTableList; + + LIST_ENTRY SupportedEraseTypes; ///< The linked list of supported erase types. + BOOLEAN Uniform4KEraseSupported; ///< The flash device supoprts uniform 4K erase. + BOOLEAN WriteEnableLatchRequired; ///< Wether Write Enable Latch is supported. + UINT8 WriteEnableLatchCommand; ///< Write Enable Latch command. + // + // Below is the linked list of flash device sector + // map configuration detection command and map descriptors. + // + BOOLEAN ConfigurationCommandsNeeded; ///< Indicates whether sector map + ///< configuration detection is + ///< required. + LIST_ENTRY ConfigurationCommandList; ///< The linked list of configuration + ///< detection command sequence. + LIST_ENTRY ConfigurationMapList; ///< The linked list of configuration + ///< map descriptors. + SFDP_SECTOR_MAP_RECORD *CurrentSectorMap; ///< The current activated flash device + ///< sector map. +} SPI_NOR_FLASH_INSTANCE; + +/** + This routine returns the desired Fast Read mode. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in,out] FastReadInstruction Fast Read instruction, the input is + the default value. + @param[in,out] FastReadOperationClock Fast Read operation clock, the input is + the default value. + @param[in,out] FastReadDummyClocks Fast Read wait state (Dummy clocks), the + input is the default value. + @retval EFI_SUCCESS The parameters are updated. + @retval EFI_NOT_FOUND No desired Fas Read mode found. + +**/ +EFI_STATUS +GetFastReadParameter ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN OUT UINT8 *FastReadInstruction, + IN OUT UINT8 *FastReadOperationClock, + IN OUT UINT8 *FastReadDummyClocks + ); + +/** + Read SFDP parameters into buffer + + This routine reads the JEDEC SPI Flash Discoverable Parameters from the SPI + chip. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +ReadSfdpBasicParameterTable ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ); + +/** + Read SFDP Sector Map Parameter into buffer + + This routine reads the JEDEC SPI Flash Discoverable Parameters from the SPI + chip. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The SPI part size is filled. + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +ReadSfdpSectorMapParameterTable ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ); + +/** + Return flash device size from SFDP Basic Flash Parameter Table DWORD 2 + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and + EFI_SPI_IO_PROTOCOL. + +* @retval UINT32 Flash device size in byte, zero indicates error. + +**/ +UINT32 +SfdpGetFlashSize ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ); + +/** + Read SFDP + This routine reads the JEDEC SPI Flash Discoverable Parameters. We just + read the necessary tables in this routine. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS Header is filled in + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +EFI_STATUS +ReadSfdp ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ); + +/** + Set EraseBlockBytes in SPI NOR Flash Protocol + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS The erase block size is returned. + @retval Otherwise Failed to get erase block size. + +**/ +EFI_STATUS +SetSectorEraseBlockSize ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ); + +/** + Get the erase block attribute for the target address. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] FlashRegion The region the flash address belong. + @param[in] FlashAddress The target flash address. + @param[in] RemainingSize Remaining size to erase. + @param[in, out] BlockSizeToErase Input - The block erase size for this continious blocks. + Output - The determined block size for erasing. + @param[in, out] BlockCountToErase Input - The expected blocks to erase. + Output - The determined number of blocks to erase. + @param[out] BlockEraseCommand The erase command used for this continious blocks. + @param[out] TypicalTime Pointer to receive the typical time in millisecond + to erase this erase type size. + @param[out] MaximumTimeout Pointer to receive the maximum timeout in millisecond + to erase this erase type size. + @retval EFI_SUCCESS The erase block attribute is returned. + @retval EFI_DEVICE_ERROR No valid SFDP discovered. + @retval EFI_NOT_FOUND No valud erase block attribute found. + +**/ +EFI_STATUS +GetEraseBlockAttribute ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN SFDP_SECTOR_REGION_RECORD *FlashRegion, + IN UINT32 FlashAddress, + IN UINT32 RemainingSize, + IN OUT UINT32 *BlockSizeToErase, + IN OUT UINT32 *BlockCountToErase, + OUT UINT8 *BlockEraseCommand, + OUT UINT32 *TypicalTime, + OUT UINT64 *MaximumTimeout + ); + +/** + Get the erase block attribute for the target address. + + @param[in] Instance Spi Nor Flash Instance data with pointer to + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + @param[in] FlashAddress The target flash address. + @param[out] FlashRegion The target flash address. + + @retval EFI_SUCCESS The region is returned. + @retval EFI_INVALID_PARAMETER FlashAddress is not belong to any region. + @retval EFI_INVALID_PARAMETER Other errors. + +**/ +EFI_STATUS +GetRegionByFlashAddress ( + IN SPI_NOR_FLASH_INSTANCE *Instance, + IN UINT32 FlashAddress, + OUT SFDP_SECTOR_REGION_RECORD **FlashRegion + ); + +/** + Initial SPI_NOR_FLASH_INSTANCE structure. + + @param[in] Instance Pointer to SPI_NOR_FLASH_INSTANCE. + EFI_SPI_NOR_FLASH_PROTOCOL and EFI_SPI_IO_PROTOCOL + + @retval EFI_SUCCESS SPI_NOR_FLASH_INSTANCE is initialized according to + SPI NOR Flash SFDP specification. + @retval Otherwisw Failed to initial SPI_NOR_FLASH_INSTANCE structure. + +**/ +EFI_STATUS +InitialSpiNorFlashSfdpInstance ( + IN SPI_NOR_FLASH_INSTANCE *Instance + ); + +#endif // SPI_NOR_FLASH_INSTANCE_H_ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..68ab4c8f09403edc0fa6c6fcffead2afbf5b715d --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.c @@ -0,0 +1,233 @@ +/** @file + SPI NOR Flash JEDEC Serial Flash Discoverable Parameters (SFDP) + SMM driver. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - JEDEC Standard, JESD216F.02 + https://www.jedec.org/document_search?search_api_views_fulltext=JESD216 + + @par Glossary: + - SFDP - Serial Flash Discoverable Parameters + - PTP - Parameter Table Pointer +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "SpiNorFlash.h" +#include "SpiNorFlashJedecSfdpInternal.h" + +/** + Function to create SPI_NOR_FLASH_INSTANCE for this SPI part. + + @param[in] SpiIoHandle The handle with SPI I/O protocol installed. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_OF_RESOURCES Not enough resource to create SPI_NOR_FLASH_INSTANCE. + @retval otherwise Fail to create SPI NOR Flash SFDP Instance +**/ +EFI_STATUS +CreateSpiNorFlashSfdpInstance ( + IN EFI_HANDLE SpiIoHandle + ) +{ + EFI_STATUS Status; + SPI_NOR_FLASH_INSTANCE *Instance; + + // Allocate SPI_NOR_FLASH_INSTANCE Instance. + Instance = AllocateZeroPool (sizeof (SPI_NOR_FLASH_INSTANCE)); + ASSERT (Instance != NULL); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // Locate the SPI IO Protocol. + Status = gSmst->SmmHandleProtocol ( + SpiIoHandle, + &gEdk2JedecSfdpSpiSmmDriverGuid, + (VOID **)&Instance->SpiIo + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to locate SPI I/O protocol.\n", __func__)); + FreePool (Instance); + } else { + Status = InitialSpiNorFlashSfdpInstance (Instance); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to initial SPI_NOR_FLASH_INSTANCE.\n", __func__)); + FreePool (Instance); + } else { + // Install SPI NOR Flash Protocol. + Status = gSmst->SmmInstallProtocolInterface ( + &Instance->Handle, + &gEfiSpiSmmNorFlashProtocolGuid, + EFI_NATIVE_INTERFACE, + &Instance->Protocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to Install gEfiSpiSmmNorFlashProtocolGuid protocol.\n", __func__)); + FreePool (Instance); + } + } + } + + return Status; +} + +/** + Callback function executed when the EFI_SPI_IO_PROTOCOL + protocol interface is installed. + + @param[in] Protocol Points to the protocol's unique identifier. + @param[in] Interface Points to the interface instance. + @param[in] Handle The handle on which the interface was installed. + + @return Status Code + +**/ +EFI_STATUS +EFIAPI +SpiIoProtocolInstalledCallback ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __func__)); + Status = CreateSpiNorFlashSfdpInstance (Handle); + return Status; +} + +/** + Register notification for the later installed SPI I/O protocol. + + @retval EFI_SUCCESS Succeed. + @retval otherwise Fail to register the notification of + SPI I/O protocol installation. + +**/ +EFI_STATUS +RegisterSpioProtocolNotification ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Registration; + + Status = gSmst->SmmRegisterProtocolNotify ( + &gEdk2JedecSfdpSpiSmmDriverGuid, + SpiIoProtocolInstalledCallback, + &Registration + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to register event for the SPI I/O Protocol installation.", __func__)); + } else { + DEBUG ((DEBUG_INFO, "%a: Notification for SPI I/O Protocol installation was registered.", __func__)); + } + + return Status; +} + +/** + Entry point of the SPI NOR Flash SFDP SMM driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND No gEdk2JedecSfdpSpiSmmDriverGuid installed on + system yet. + @retval EFI_OUT_OF_RESOURCES Not enough resource for SPI NOR Flash JEDEC SFDP + initialization. + @retval Otherwise Other errors. +**/ +EFI_STATUS +EFIAPI +SpiNorFlashJedecSfdpSmmEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE *InstanceBuffer; + UINTN InstanceIndex; + UINTN InstanceBufferSize; + + DEBUG ((DEBUG_INFO, "%a - ENTRY.\n", __func__)); + + // + // Register notification for the later SPI I/O protocol installation. + // + RegisterSpioProtocolNotification (); + DEBUG ((DEBUG_INFO, "Check if there were already some gEdk2JedecSfdpSpiSmmDriverGuid handles installed.\n")); + // + // Check if there were already some gEdk2JedecSfdpSpiSmmDriverGuid + // handles installed. + // + // Locate the SPI I/O Protocol for the SPI flash part + // that supports JEDEC SFDP specification. + // + InstanceBufferSize = 0; + InstanceBuffer = NULL; + Status = gSmst->SmmLocateHandle ( + ByProtocol, + &gEdk2JedecSfdpSpiSmmDriverGuid, + NULL, + &InstanceBufferSize, + InstanceBuffer + ); + if (Status == EFI_NOT_FOUND) { + DEBUG (( + DEBUG_INFO, + "No gEdk2JedecSfdpSpiSmmDriverGuid handles found at the moment, wait for the notification of SPI I/O protocol installation.\n" + )); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return EFI_SUCCESS; + } else if (Status == EFI_BUFFER_TOO_SMALL) { + InstanceBuffer = (EFI_HANDLE *)AllocateZeroPool (InstanceBufferSize); + ASSERT (InstanceBuffer != NULL); + if (InstanceBuffer == NULL) { + DEBUG ((DEBUG_ERROR, "Not enough resource for gEdk2JedecSfdpSpiSmmDriverGuid handles.\n")); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return EFI_OUT_OF_RESOURCES; + } + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error to locate gEdk2JedecSfdpSpiSmmDriverGuid - Status = %r.\n", Status)); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return Status; + } + + Status = gSmst->SmmLocateHandle ( + ByProtocol, + &gEdk2JedecSfdpSpiSmmDriverGuid, + NULL, + &InstanceBufferSize, + InstanceBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to locate all gEdk2JedecSfdpSpiSmmDriverGuid handles.\n")); + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return Status; + } + + DEBUG ((DEBUG_INFO, "%d of gEdk2JedecSfdpSpiSmmDriverGuid handles are found.\n", InstanceBufferSize / sizeof (EFI_HANDLE))); + for (InstanceIndex = 0; InstanceIndex < InstanceBufferSize / sizeof (EFI_HANDLE); InstanceIndex++) { + Status = CreateSpiNorFlashSfdpInstance (*(InstanceBuffer + InstanceIndex)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to create SPI NOR Flash SFDP instance #%d.\n", InstanceIndex)); + } + } + + DEBUG ((DEBUG_INFO, "%a: EXIT - Status=%r\n", __func__, Status)); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..c14d698853994e5888187b1623ad6f30b87d7e56 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf @@ -0,0 +1,63 @@ +## @file +# The SPI NOR Flash JEDEC Serial Flash Discoverable Parameters (SFDP) +# SMM driver INF file. +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Revision Reference: +# - JEDEC Standard, JESD216F.02 +# https://www.jedec.org/document_search?search_api_views_fulltext=JESD216 +# +# @par Glossary: +# - SFDP - Serial Flash Discoverable Parameters +# - PTP - Parameter Table Pointer +## + +[Defines] + INF_VERSION = 1.25 + BASE_NAME = SpiNorFlashJedecSfdpSmm + FILE_GUID = AC7884C7-35A2-40AC-B9E0-AD67298E3BBA + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 1.10 + ENTRY_POINT = SpiNorFlashJedecSfdpSmmEntry + MODULE_UNI_FILE = SpiNorFlashJedecSfdpSmm.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + SmmServicesTableLib + TimerLib + UefiDriverEntryPoint + +[Sources] + SpiNorFlashJedecSfdpSmm.c + SpiNorFlash.c + SpiNorFlashJedecSfdp.c + SpiNorFlashJedecSfdpInternal.h + SpiNorFlash.h + +[Protocols] + gEfiSpiSmmNorFlashProtocolGuid ## PROCUDES + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashFixedTimeoutRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Guids] + gEdk2JedecSfdpSpiSmmDriverGuid + +[Depex] + gEdk2JedecSfdpSpiSmmDriverGuid + +[UserExtensions.TianoCore."ExtraFiles"] + SpiNorFlashJedecSfdpExtra.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.uni b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.uni new file mode 100644 index 0000000000000000000000000000000000000000..5e298301b8559eec092a5d1a649b091152f0b6cd --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.uni @@ -0,0 +1,12 @@ +// /** @file +// SPI NOR Flash SFDP Localized Strings and Content. +// +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "EDK2 SPI NOR FLASH SFDP SMM driver" + +#string STR_MODULE_DESCRIPTION #language en-US "This driver provides SPI NOR FLASH Serial Flash Discoverable Parameter (SFDP) compatible flash device capability discovery." + diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c new file mode 100644 index 0000000000000000000000000000000000000000..fa415cc2fc870befb8920cba427ffa91dd94672c --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c @@ -0,0 +1,1571 @@ +/** @file + + Usb Bus Driver Binding and Bus IO Protocol. + +Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsbBus.h" + +EFI_USB_IO_PROTOCOL mUsbIoProtocol = { + UsbIoControlTransfer, + UsbIoBulkTransfer, + UsbIoAsyncInterruptTransfer, + UsbIoSyncInterruptTransfer, + UsbIoIsochronousTransfer, + UsbIoAsyncIsochronousTransfer, + UsbIoGetDeviceDescriptor, + UsbIoGetActiveConfigDescriptor, + UsbIoGetInterfaceDescriptor, + UsbIoGetEndpointDescriptor, + UsbIoGetStringDescriptor, + UsbIoGetSupportedLanguages, + UsbIoPortReset +}; + +EFI_DRIVER_BINDING_PROTOCOL mUsbBusDriverBinding = { + UsbBusControllerDriverSupported, + UsbBusControllerDriverStart, + UsbBusControllerDriverStop, + 0xa, + NULL, + NULL +}; + +/** + USB_IO function to execute a control transfer. This + function will execute the USB transfer. If transfer + successes, it will sync the internal state of USB bus + with device state. + + @param This The USB_IO instance + @param Request The control transfer request + @param Direction Direction for data stage + @param Timeout The time to wait before timeout + @param Data The buffer holding the data + @param DataLength Then length of the data + @param UsbStatus USB result + + @retval EFI_INVALID_PARAMETER The parameters are invalid + @retval EFI_SUCCESS The control transfer succeeded. + @retval Others Failed to execute the transfer + +**/ +EFI_STATUS +EFIAPI +UsbIoControlTransfer ( + IN EFI_USB_IO_PROTOCOL *This, + IN EFI_USB_DEVICE_REQUEST *Request, + IN EFI_USB_DATA_DIRECTION Direction, + IN UINT32 Timeout, + IN OUT VOID *Data OPTIONAL, + IN UINTN DataLength OPTIONAL, + OUT UINT32 *UsbStatus + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + USB_ENDPOINT_DESC *EpDesc; + EFI_TPL OldTpl; + EFI_STATUS Status; + UINTN RequestedDataLength; + + if (UsbStatus == NULL) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + RequestedDataLength = DataLength; + Status = UsbHcControlTransfer ( + Dev->Bus, + Dev->Address, + Dev->Speed, + Dev->MaxPacket0, + Request, + Direction, + Data, + &DataLength, + (UINTN)Timeout, + &Dev->Translator, + UsbStatus + ); + // + // If the request completed successfully and the Direction of the request is + // EfiUsbDataIn or EfiUsbDataOut, then make sure the actual number of bytes + // transferred is the same as the number of bytes requested. If a different + // number of bytes were transferred, then return EFI_DEVICE_ERROR. + // + if (!EFI_ERROR (Status)) { + if ((Direction != EfiUsbNoData) && (DataLength != RequestedDataLength)) { + Status = EFI_DEVICE_ERROR; + goto ON_EXIT; + } + } + + if (EFI_ERROR (Status) || (*UsbStatus != EFI_USB_NOERROR)) { + // + // Clear TT buffer when CTRL/BULK split transaction failes + // Clear the TRANSLATOR TT buffer, not parent's buffer + // + ASSERT (Dev->Translator.TranslatorHubAddress < Dev->Bus->MaxDevices); + if (Dev->Translator.TranslatorHubAddress != 0) { + UsbHubCtrlClearTTBuffer ( + Dev->Bus->Devices[Dev->Translator.TranslatorHubAddress], + Dev->Translator.TranslatorPortNumber, + Dev->Address, + 0, + USB_ENDPOINT_CONTROL + ); + } + + goto ON_EXIT; + } + + // + // Some control transfer will change the device's internal + // status, such as Set_Configuration and Set_Interface. + // We must synchronize the bus driver's status with that in + // device. We ignore the Set_Descriptor request because it's + // hardly used by any device, especially in pre-boot environment + // + + // + // Reset the endpoint toggle when endpoint stall is cleared + // + if ((Request->Request == USB_REQ_CLEAR_FEATURE) && + (Request->RequestType == USB_REQUEST_TYPE ( + EfiUsbNoData, + USB_REQ_TYPE_STANDARD, + USB_TARGET_ENDPOINT + )) && + (Request->Value == USB_FEATURE_ENDPOINT_HALT)) + { + EpDesc = UsbGetEndpointDesc (UsbIf, (UINT8)Request->Index); + + if (EpDesc != NULL) { + EpDesc->Toggle = 0; + } + } + + // + // Select a new configuration. This is a dangerous action. Upper driver + // should stop use its current UsbIo after calling this driver. The old + // UsbIo will be uninstalled and new UsbIo be installed. We can't use + // ReinstallProtocol since interfaces in different configuration may be + // completely irrelevant. + // + if ((Request->Request == USB_REQ_SET_CONFIG) && + (Request->RequestType == USB_REQUEST_TYPE ( + EfiUsbNoData, + USB_REQ_TYPE_STANDARD, + USB_TARGET_DEVICE + ))) + { + // + // Don't re-create the USB interfaces if configuration isn't changed. + // + if ((Dev->ActiveConfig != NULL) && + (Request->Value == Dev->ActiveConfig->Desc.ConfigurationValue)) + { + goto ON_EXIT; + } + + DEBUG ((DEBUG_INFO, "UsbIoControlTransfer: configure changed!!! Do NOT use old UsbIo!!!\n")); + + if (Dev->ActiveConfig != NULL) { + UsbRemoveConfig (Dev); + } + + if (Request->Value != 0) { + Status = UsbSelectConfig (Dev, (UINT8)Request->Value); + } + + // + // Exit now, Old USB_IO is invalid now + // + goto ON_EXIT; + } + + // + // A new alternative setting is selected for the interface. + // No need to reinstall UsbIo in this case because only + // underlying communication endpoints are changed. Functionality + // should remains the same. + // + if ((Request->Request == USB_REQ_SET_INTERFACE) && + (Request->RequestType == USB_REQUEST_TYPE ( + EfiUsbNoData, + USB_REQ_TYPE_STANDARD, + USB_TARGET_INTERFACE + )) && + (Request->Index == UsbIf->IfSetting->Desc.InterfaceNumber)) + { + Status = UsbSelectSetting (UsbIf->IfDesc, (UINT8)Request->Value); + + if (!EFI_ERROR (Status)) { + ASSERT (UsbIf->IfDesc->ActiveIndex < USB_MAX_INTERFACE_SETTING); + UsbIf->IfSetting = UsbIf->IfDesc->Settings[UsbIf->IfDesc->ActiveIndex]; + } + } + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Execute a bulk transfer to the device endpoint. + + @param This The USB IO instance. + @param Endpoint The device endpoint. + @param Data The data to transfer. + @param DataLength The length of the data to transfer. + @param Timeout Time to wait before timeout. + @param UsbStatus The result of USB transfer. + + @retval EFI_SUCCESS The bulk transfer is OK. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval Others Failed to execute transfer, reason returned in + UsbStatus. + +**/ +EFI_STATUS +EFIAPI +UsbIoBulkTransfer ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 Endpoint, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN UINTN Timeout, + OUT UINT32 *UsbStatus + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + USB_ENDPOINT_DESC *EpDesc; + UINT8 BufNum; + UINT8 Toggle; + EFI_TPL OldTpl; + EFI_STATUS Status; + + if ((USB_ENDPOINT_ADDR (Endpoint) == 0) || (USB_ENDPOINT_ADDR (Endpoint) > 15) || + (UsbStatus == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + EpDesc = UsbGetEndpointDesc (UsbIf, Endpoint); + + if ((EpDesc == NULL) || (USB_ENDPOINT_TYPE (&EpDesc->Desc) != USB_ENDPOINT_BULK)) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + BufNum = 1; + Toggle = EpDesc->Toggle; + Status = UsbHcBulkTransfer ( + Dev->Bus, + Dev->Address, + Endpoint, + Dev->Speed, + EpDesc->Desc.MaxPacketSize, + BufNum, + &Data, + DataLength, + &Toggle, + Timeout, + &Dev->Translator, + UsbStatus + ); + + EpDesc->Toggle = Toggle; + + if (EFI_ERROR (Status) || (*UsbStatus != EFI_USB_NOERROR)) { + // + // Clear TT buffer when CTRL/BULK split transaction failes. + // Clear the TRANSLATOR TT buffer, not parent's buffer + // + ASSERT (Dev->Translator.TranslatorHubAddress < Dev->Bus->MaxDevices); + if (Dev->Translator.TranslatorHubAddress != 0) { + UsbHubCtrlClearTTBuffer ( + Dev->Bus->Devices[Dev->Translator.TranslatorHubAddress], + Dev->Translator.TranslatorPortNumber, + Dev->Address, + 0, + USB_ENDPOINT_BULK + ); + } + } + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Execute a synchronous interrupt transfer. + + @param This The USB IO instance. + @param Endpoint The device endpoint. + @param Data The data to transfer. + @param DataLength The length of the data to transfer. + @param Timeout Time to wait before timeout. + @param UsbStatus The result of USB transfer. + + @retval EFI_SUCCESS The synchronous interrupt transfer is OK. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval Others Failed to execute transfer, reason returned in + UsbStatus. + +**/ +EFI_STATUS +EFIAPI +UsbIoSyncInterruptTransfer ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 Endpoint, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN UINTN Timeout, + OUT UINT32 *UsbStatus + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + USB_ENDPOINT_DESC *EpDesc; + EFI_TPL OldTpl; + UINT8 Toggle; + EFI_STATUS Status; + + if ((USB_ENDPOINT_ADDR (Endpoint) == 0) || (USB_ENDPOINT_ADDR (Endpoint) > 15) || + (UsbStatus == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + EpDesc = UsbGetEndpointDesc (UsbIf, Endpoint); + + if ((EpDesc == NULL) || (USB_ENDPOINT_TYPE (&EpDesc->Desc) != USB_ENDPOINT_INTERRUPT)) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + Toggle = EpDesc->Toggle; + Status = UsbHcSyncInterruptTransfer ( + Dev->Bus, + Dev->Address, + Endpoint, + Dev->Speed, + EpDesc->Desc.MaxPacketSize, + Data, + DataLength, + &Toggle, + Timeout, + &Dev->Translator, + UsbStatus + ); + + EpDesc->Toggle = Toggle; + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Queue a new asynchronous interrupt transfer, or remove the old + request if (IsNewTransfer == FALSE). + + @param This The USB_IO instance. + @param Endpoint The device endpoint. + @param IsNewTransfer Whether this is a new request, if it's old, remove + the request. + @param PollInterval The interval to poll the transfer result, (in ms). + @param DataLength The length of perodic data transfer. + @param Callback The function to call periodically when transfer is + ready. + @param Context The context to the callback. + + @retval EFI_SUCCESS New transfer is queued or old request is removed. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval Others Failed to queue the new request or remove the old + request. + +**/ +EFI_STATUS +EFIAPI +UsbIoAsyncInterruptTransfer ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 Endpoint, + IN BOOLEAN IsNewTransfer, + IN UINTN PollInterval OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback OPTIONAL, + IN VOID *Context OPTIONAL + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + USB_ENDPOINT_DESC *EpDesc; + EFI_TPL OldTpl; + UINT8 Toggle; + EFI_STATUS Status; + + if ((USB_ENDPOINT_ADDR (Endpoint) == 0) || (USB_ENDPOINT_ADDR (Endpoint) > 15)) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + EpDesc = UsbGetEndpointDesc (UsbIf, Endpoint); + + if ((EpDesc == NULL) || (USB_ENDPOINT_TYPE (&EpDesc->Desc) != USB_ENDPOINT_INTERRUPT)) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + Toggle = EpDesc->Toggle; + Status = UsbHcAsyncInterruptTransfer ( + Dev->Bus, + Dev->Address, + Endpoint, + Dev->Speed, + EpDesc->Desc.MaxPacketSize, + IsNewTransfer, + &Toggle, + PollInterval, + DataLength, + &Dev->Translator, + Callback, + Context + ); + + EpDesc->Toggle = Toggle; + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Execute a synchronous isochronous transfer. + + @param This The USB IO instance. + @param DeviceEndpoint The device endpoint. + @param Data The data to transfer. + @param DataLength The length of the data to transfer. + @param UsbStatus The result of USB transfer. + + @retval EFI_UNSUPPORTED Currently isochronous transfer isn't supported. + +**/ +EFI_STATUS +EFIAPI +UsbIoIsochronousTransfer ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN OUT VOID *Data, + IN UINTN DataLength, + OUT UINT32 *Status + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Queue an asynchronous isochronous transfer. + + @param This The USB_IO instance. + @param DeviceEndpoint The device endpoint. + @param Data The data to transfer. + @param DataLength The length of perodic data transfer. + @param IsochronousCallBack The function to call periodically when transfer is + ready. + @param Context The context to the callback. + + @retval EFI_UNSUPPORTED Currently isochronous transfer isn't supported. + +**/ +EFI_STATUS +EFIAPI +UsbIoAsyncIsochronousTransfer ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN OUT VOID *Data, + IN UINTN DataLength, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack, + IN VOID *Context OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Retrieve the device descriptor of the device. + + @param This The USB IO instance. + @param Descriptor The variable to receive the device descriptor. + + @retval EFI_SUCCESS The device descriptor is returned. + @retval EFI_INVALID_PARAMETER The parameter is invalid. + +**/ +EFI_STATUS +EFIAPI +UsbIoGetDeviceDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + OUT EFI_USB_DEVICE_DESCRIPTOR *Descriptor + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + EFI_TPL OldTpl; + + if (Descriptor == NULL) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + CopyMem (Descriptor, &Dev->DevDesc->Desc, sizeof (EFI_USB_DEVICE_DESCRIPTOR)); + + gBS->RestoreTPL (OldTpl); + return EFI_SUCCESS; +} + +/** + Return the configuration descriptor of the current active configuration. + + @param This The USB IO instance. + @param Descriptor The USB configuration descriptor. + + @retval EFI_SUCCESS The active configuration descriptor is returned. + @retval EFI_INVALID_PARAMETER Some parameter is invalid. + @retval EFI_NOT_FOUND Currently no active configuration is selected. + +**/ +EFI_STATUS +EFIAPI +UsbIoGetActiveConfigDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + OUT EFI_USB_CONFIG_DESCRIPTOR *Descriptor + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + EFI_STATUS Status; + EFI_TPL OldTpl; + + if (Descriptor == NULL) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_SUCCESS; + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + if (Dev->ActiveConfig == NULL) { + Status = EFI_NOT_FOUND; + goto ON_EXIT; + } + + CopyMem (Descriptor, &(Dev->ActiveConfig->Desc), sizeof (EFI_USB_CONFIG_DESCRIPTOR)); + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Retrieve the active interface setting descriptor for this USB IO instance. + + @param This The USB IO instance. + @param Descriptor The variable to receive active interface setting. + + @retval EFI_SUCCESS The active interface setting is returned. + @retval EFI_INVALID_PARAMETER Some parameter is invalid. + +**/ +EFI_STATUS +EFIAPI +UsbIoGetInterfaceDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + OUT EFI_USB_INTERFACE_DESCRIPTOR *Descriptor + ) +{ + USB_INTERFACE *UsbIf; + EFI_TPL OldTpl; + + if (Descriptor == NULL) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + CopyMem (Descriptor, &(UsbIf->IfSetting->Desc), sizeof (EFI_USB_INTERFACE_DESCRIPTOR)); + + gBS->RestoreTPL (OldTpl); + return EFI_SUCCESS; +} + +/** + Retrieve the endpoint descriptor from this interface setting. + + @param This The USB IO instance. + @param Index The index (start from zero) of the endpoint to + retrieve. + @param Descriptor The variable to receive the descriptor. + + @retval EFI_SUCCESS The endpoint descriptor is returned. + @retval EFI_INVALID_PARAMETER Some parameter is invalid. + +**/ +EFI_STATUS +EFIAPI +UsbIoGetEndpointDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 Index, + OUT EFI_USB_ENDPOINT_DESCRIPTOR *Descriptor + ) +{ + USB_INTERFACE *UsbIf; + EFI_TPL OldTpl; + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + + if ((Descriptor == NULL) || (Index > 15)) { + gBS->RestoreTPL (OldTpl); + return EFI_INVALID_PARAMETER; + } + + if (Index >= UsbIf->IfSetting->Desc.NumEndpoints) { + gBS->RestoreTPL (OldTpl); + return EFI_NOT_FOUND; + } + + CopyMem ( + Descriptor, + &(UsbIf->IfSetting->Endpoints[Index]->Desc), + sizeof (EFI_USB_ENDPOINT_DESCRIPTOR) + ); + + gBS->RestoreTPL (OldTpl); + return EFI_SUCCESS; +} + +/** + Retrieve the supported language ID table from the device. + + @param This The USB IO instance. + @param LangIDTable The table to return the language IDs. + @param TableSize The size, in bytes, of the table LangIDTable. + + @retval EFI_SUCCESS The language ID is return. + +**/ +EFI_STATUS +EFIAPI +UsbIoGetSupportedLanguages ( + IN EFI_USB_IO_PROTOCOL *This, + OUT UINT16 **LangIDTable, + OUT UINT16 *TableSize + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + EFI_TPL OldTpl; + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + *LangIDTable = Dev->LangId; + *TableSize = (UINT16)(Dev->TotalLangId * sizeof (UINT16)); + + gBS->RestoreTPL (OldTpl); + return EFI_SUCCESS; +} + +/** + Retrieve an indexed string in the language of LangID. + + @param This The USB IO instance. + @param LangID The language ID of the string to retrieve. + @param StringIndex The index of the string. + @param String The variable to receive the string. + + @retval EFI_SUCCESS The string is returned. + @retval EFI_NOT_FOUND No such string existed. + +**/ +EFI_STATUS +EFIAPI +UsbIoGetStringDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT16 LangID, + IN UINT8 StringIndex, + OUT CHAR16 **String + ) +{ + USB_DEVICE *Dev; + USB_INTERFACE *UsbIf; + EFI_USB_STRING_DESCRIPTOR *StrDesc; + EFI_TPL OldTpl; + UINT8 *Buf; + UINT8 Index; + EFI_STATUS Status; + + if ((StringIndex == 0) || (LangID == 0)) { + return EFI_NOT_FOUND; + } + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + // + // Check whether language ID is supported + // + Status = EFI_NOT_FOUND; + + for (Index = 0; Index < Dev->TotalLangId; Index++) { + ASSERT (Index < USB_MAX_LANG_ID); + if (Dev->LangId[Index] == LangID) { + break; + } + } + + if (Index == Dev->TotalLangId) { + goto ON_EXIT; + } + + // + // Retrieve the string descriptor then allocate a buffer + // to hold the string itself. + // + StrDesc = UsbGetOneString (Dev, StringIndex, LangID); + + if (StrDesc == NULL) { + goto ON_EXIT; + } + + if (StrDesc->Length <= 2) { + goto FREE_STR; + } + + Buf = AllocateZeroPool (StrDesc->Length); + + if (Buf == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto FREE_STR; + } + + CopyMem (Buf, StrDesc->String, StrDesc->Length - 2); + *String = (CHAR16 *)Buf; + Status = EFI_SUCCESS; + +FREE_STR: + gBS->FreePool (StrDesc); + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Reset the device, then if that succeeds, reconfigure the + device with its address and current active configuration. + + @param This The USB IO instance. + + @retval EFI_SUCCESS The device is reset and configured. + @retval Others Failed to reset the device. + +**/ +EFI_STATUS +EFIAPI +UsbIoPortReset ( + IN EFI_USB_IO_PROTOCOL *This + ) +{ + USB_INTERFACE *UsbIf; + USB_INTERFACE *HubIf; + USB_DEVICE *Dev; + EFI_TPL OldTpl; + EFI_STATUS Status; + UINT8 DevAddress; + UINT8 Config; + + OldTpl = gBS->RaiseTPL (USB_BUS_TPL); + + UsbIf = USB_INTERFACE_FROM_USBIO (This); + Dev = UsbIf->Device; + + if (UsbIf->IsHub) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + HubIf = Dev->ParentIf; + Status = HubIf->HubApi->ResetPort (HubIf, Dev->ParentPort); + + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "UsbIoPortReset: failed to reset hub port %d@hub %d - %r\n", + Dev->ParentPort, + Dev->ParentAddr, + Status + )); + + goto ON_EXIT; + } + + HubIf->HubApi->ClearPortChange (HubIf, Dev->ParentPort); + + // + // Reset the device to its current address. The device now has an address + // of ZERO after port reset, so need to set Dev->Address to the device again for + // host to communicate with it. + // + DevAddress = Dev->Address; + Dev->Address = 0; + Status = UsbSetAddress (Dev, DevAddress); + Dev->Address = DevAddress; + + gBS->Stall (USB_SET_DEVICE_ADDRESS_STALL); + + if (EFI_ERROR (Status)) { + // + // It may fail due to device disconnection or other reasons. + // + DEBUG (( + DEBUG_ERROR, + "UsbIoPortReset: failed to set address for device %d - %r\n", + Dev->Address, + Status + )); + + goto ON_EXIT; + } + + DEBUG ((DEBUG_INFO, "UsbIoPortReset: device is now ADDRESSED at %d\n", Dev->Address)); + + // + // Reset the current active configure, after this device + // is in CONFIGURED state. + // + if (Dev->ActiveConfig != NULL) { + UsbFreeDevDesc (Dev->DevDesc); + + Status = UsbRemoveConfig (Dev); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbIoPortReset: Failed to remove configuration - %r\n", Status)); + } + + Status = UsbGetMaxPacketSize0 (Dev); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbIoPortReset: Failed to get max packet size - %r\n", Status)); + } + + Status = UsbBuildDescTable (Dev); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbIoPortReset: Failed to build descriptor table - %r\n", Status)); + } + + Config = Dev->DevDesc->Configs[0]->Desc.ConfigurationValue; + + Status = UsbSetConfig (Dev, Config); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "UsbIoPortReset: failed to set configure for device %d - %r\n", + Dev->Address, + Status + )); + } + + Status = UsbSelectConfig (Dev, Config); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbIoPortReset: Failed to set configuration - %r\n", Status)); + } + } + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Install Usb Bus Protocol on host controller, and start the Usb bus. + + @param This The USB bus driver binding instance. + @param Controller The controller to check. + @param RemainingDevicePath The remaining device patch. + + @retval EFI_SUCCESS The controller is controlled by the usb bus. + @retval EFI_ALREADY_STARTED The controller is already controlled by the usb bus. + @retval EFI_OUT_OF_RESOURCES Failed to allocate resources. + +**/ +EFI_STATUS +EFIAPI +UsbBusBuildProtocol ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + USB_BUS *UsbBus; + USB_DEVICE *RootHub; + USB_INTERFACE *RootIf; + EFI_STATUS Status; + EFI_STATUS Status2; + + UsbBus = AllocateZeroPool (sizeof (USB_BUS)); + + if (UsbBus == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + UsbBus->Signature = USB_BUS_SIGNATURE; + UsbBus->HostHandle = Controller; + UsbBus->MaxDevices = USB_MAX_DEVICES; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID **)&UsbBus->DevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbBusStart: Failed to open device path - %r\n", Status)); + + FreePool (UsbBus); + return Status; + } + + // + // Get USB_HC2/USB_HC host controller protocol (EHCI/UHCI). + // This is for backward compatibility with EFI 1.x. In UEFI + // 2.x, USB_HC2 replaces USB_HC. We will open both USB_HC2 + // and USB_HC because EHCI driver will install both protocols + // (for the same reason). If we don't consume both of them, + // the unconsumed one may be opened by others. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsb2HcProtocolGuid, + (VOID **)&(UsbBus->Usb2Hc), + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + Status2 = gBS->OpenProtocol ( + Controller, + &gEfiUsbHcProtocolGuid, + (VOID **)&(UsbBus->UsbHc), + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status) && EFI_ERROR (Status2)) { + DEBUG ((DEBUG_ERROR, "UsbBusStart: Failed to open USB_HC/USB2_HC - %r\n", Status)); + + Status = EFI_DEVICE_ERROR; + goto CLOSE_HC; + } + + if (!EFI_ERROR (Status)) { + // + // The EFI_USB2_HC_PROTOCOL is produced for XHCI support. + // Then its max supported devices are 256. Otherwise it's 128. + // + ASSERT (UsbBus->Usb2Hc != NULL); + if (UsbBus->Usb2Hc->MajorRevision == 0x3) { + UsbBus->MaxDevices = 256; + } + } + + // + // Install an EFI_USB_BUS_PROTOCOL to host controller to identify it. + // + Status = gBS->InstallProtocolInterface ( + &Controller, + &gEfiCallerIdGuid, + EFI_NATIVE_INTERFACE, + &UsbBus->BusId + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbBusStart: Failed to install bus protocol - %r\n", Status)); + goto CLOSE_HC; + } + + // + // Initial the wanted child device path list, and add first RemainingDevicePath + // + InitializeListHead (&UsbBus->WantedUsbIoDPList); + Status = UsbBusAddWantedUsbIoDP (&UsbBus->BusId, RemainingDevicePath); + ASSERT (!EFI_ERROR (Status)); + // + // Create a fake usb device for root hub + // + RootHub = AllocateZeroPool (sizeof (USB_DEVICE)); + + if (RootHub == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto UNINSTALL_USBBUS; + } + + RootIf = AllocateZeroPool (sizeof (USB_INTERFACE)); + + if (RootIf == NULL) { + FreePool (RootHub); + Status = EFI_OUT_OF_RESOURCES; + goto FREE_ROOTHUB; + } + + RootHub->Bus = UsbBus; + RootHub->NumOfInterface = 1; + RootHub->Interfaces[0] = RootIf; + RootHub->Tier = 0; + RootIf->Signature = USB_INTERFACE_SIGNATURE; + RootIf->Device = RootHub; + RootIf->DevicePath = UsbBus->DevicePath; + + // + // Report Status Code here since we will enumerate the USB devices + // + REPORT_STATUS_CODE_WITH_DEVICE_PATH ( + EFI_PROGRESS_CODE, + (EFI_IO_BUS_USB | EFI_IOB_PC_DETECT), + UsbBus->DevicePath + ); + + Status = mUsbRootHubApi.Init (RootIf); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbBusStart: Failed to init root hub - %r\n", Status)); + goto FREE_ROOTHUB; + } + + UsbBus->Devices[0] = RootHub; + + DEBUG ((DEBUG_INFO, "UsbBusStart: usb bus started on %p, root hub %p\n", Controller, RootIf)); + return EFI_SUCCESS; + +FREE_ROOTHUB: + if (RootIf != NULL) { + FreePool (RootIf); + } + + if (RootHub != NULL) { + FreePool (RootHub); + } + +UNINSTALL_USBBUS: + gBS->UninstallProtocolInterface (Controller, &gEfiCallerIdGuid, &UsbBus->BusId); + +CLOSE_HC: + if (UsbBus->Usb2Hc != NULL) { + gBS->CloseProtocol ( + Controller, + &gEfiUsb2HcProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + if (UsbBus->UsbHc != NULL) { + gBS->CloseProtocol ( + Controller, + &gEfiUsbHcProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + FreePool (UsbBus); + + DEBUG ((DEBUG_ERROR, "UsbBusStart: Failed to start bus driver - %r\n", Status)); + return Status; +} + +/** + The USB bus driver entry pointer. + + @param ImageHandle The driver image handle. + @param SystemTable The system table. + + @return EFI_SUCCESS The component name protocol is installed. + @return Others Failed to init the usb driver. + +**/ +EFI_STATUS +EFIAPI +UsbBusDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &mUsbBusDriverBinding, + ImageHandle, + &mUsbBusComponentName, + &mUsbBusComponentName2 + ); +} + +/** + Check whether USB bus driver support this device. + + @param This The USB bus driver binding protocol. + @param Controller The controller handle to check. + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS The bus supports this controller. + @retval EFI_UNSUPPORTED This device isn't supported. + +**/ +EFI_STATUS +EFIAPI +UsbBusControllerDriverSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_DEV_PATH_PTR DevicePathNode; + EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; + EFI_USB2_HC_PROTOCOL *Usb2Hc; + EFI_USB_HC_PROTOCOL *UsbHc; + EFI_STATUS Status; + + // + // Check whether device path is valid + // + if (RemainingDevicePath != NULL) { + // + // Check if RemainingDevicePath is the End of Device Path Node, + // if yes, go on checking other conditions + // + if (!IsDevicePathEnd (RemainingDevicePath)) { + // + // If RemainingDevicePath isn't the End of Device Path Node, + // check its validation + // + DevicePathNode.DevPath = RemainingDevicePath; + + if ((DevicePathNode.DevPath->Type != MESSAGING_DEVICE_PATH) || + ( (DevicePathNode.DevPath->SubType != MSG_USB_DP) && + (DevicePathNode.DevPath->SubType != MSG_USB_CLASS_DP) + && (DevicePathNode.DevPath->SubType != MSG_USB_WWID_DP) + )) + { + return EFI_UNSUPPORTED; + } + } + } + + // + // Check whether USB_HC2 protocol is installed + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsb2HcProtocolGuid, + (VOID **)&Usb2Hc, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (Status == EFI_ALREADY_STARTED) { + return EFI_SUCCESS; + } + + if (EFI_ERROR (Status)) { + // + // If failed to open USB_HC2, fall back to USB_HC + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbHcProtocolGuid, + (VOID **)&UsbHc, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (Status == EFI_ALREADY_STARTED) { + return EFI_SUCCESS; + } + + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Close the USB_HC used to perform the supported test + // + gBS->CloseProtocol ( + Controller, + &gEfiUsbHcProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } else { + // + // Close the USB_HC2 used to perform the supported test + // + gBS->CloseProtocol ( + Controller, + &gEfiUsb2HcProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + // + // Open the EFI Device Path protocol needed to perform the supported test + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID **)&ParentDevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (Status == EFI_ALREADY_STARTED) { + return EFI_SUCCESS; + } + + if (!EFI_ERROR (Status)) { + // + // Close protocol, don't use device path protocol in the Support() function + // + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + return EFI_SUCCESS; + } + + return Status; +} + +/** + Start to process the controller. + + @param This The USB bus driver binding instance. + @param Controller The controller to check. + @param RemainingDevicePath The remaining device patch. + + @retval EFI_SUCCESS The controller is controlled by the usb bus. + @retval EFI_ALREADY_STARTED The controller is already controlled by the usb + bus. + @retval EFI_OUT_OF_RESOURCES Failed to allocate resources. + +**/ +EFI_STATUS +EFIAPI +UsbBusControllerDriverStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_USB_BUS_PROTOCOL *UsbBusId; + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID **)&ParentDevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + ASSERT_EFI_ERROR (Status); + + // + // Report Status Code here since we will initialize the host controller + // + REPORT_STATUS_CODE_WITH_DEVICE_PATH ( + EFI_PROGRESS_CODE, + (EFI_IO_BUS_USB | EFI_IOB_PC_INIT), + ParentDevicePath + ); + + // + // Locate the USB bus protocol, if it is found, USB bus + // is already started on this controller. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiCallerIdGuid, + (VOID **)&UsbBusId, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + // + // If first start, build the bus execute environment and install bus protocol + // + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_IO_BUS_USB | EFI_P_PC_ENABLE)); + Status = UsbBusBuildProtocol (This, Controller, RemainingDevicePath); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Try get the Usb Bus protocol interface again + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiCallerIdGuid, + (VOID **)&UsbBusId, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + ASSERT (!EFI_ERROR (Status)); + } else { + // + // USB Bus driver need to control the recursive connect policy of the bus, only those wanted + // usb child device will be recursively connected. + // The RemainingDevicePath indicate the child usb device which user want to fully recursively connecte this time. + // All wanted usb child devices will be remembered by the usb bus driver itself. + // If RemainingDevicePath == NULL, all the usb child devices in the usb bus are wanted devices. + // + // Save the passed in RemainingDevicePath this time + // + if (RemainingDevicePath != NULL) { + if (IsDevicePathEnd (RemainingDevicePath)) { + // + // If RemainingDevicePath is the End of Device Path Node, + // skip enumerate any device and return EFI_SUCCESS + // + return EFI_SUCCESS; + } + } + + Status = UsbBusAddWantedUsbIoDP (UsbBusId, RemainingDevicePath); + ASSERT (!EFI_ERROR (Status)); + // + // Ensure all wanted child usb devices are fully recursively connected + // + Status = UsbBusRecursivelyConnectWantedUsbIo (UsbBusId); + ASSERT (!EFI_ERROR (Status)); + } + + return EFI_SUCCESS; +} + +/** + Stop handle the controller by this USB bus driver. + + @param This The USB bus driver binding protocol. + @param Controller The controller to release. + @param NumberOfChildren The child of USB bus that opened controller + BY_CHILD. + @param ChildHandleBuffer The array of child handle. + + @retval EFI_SUCCESS The controller or children are stopped. + @retval EFI_DEVICE_ERROR Failed to stop the driver. + +**/ +EFI_STATUS +EFIAPI +UsbBusControllerDriverStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + USB_BUS *Bus; + USB_DEVICE *RootHub; + USB_DEVICE *UsbDev; + USB_INTERFACE *RootIf; + USB_INTERFACE *UsbIf; + EFI_USB_BUS_PROTOCOL *BusId; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_TPL OldTpl; + UINTN Index; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + Status = EFI_SUCCESS; + + if (NumberOfChildren > 0) { + // + // BugBug: Raise TPL to callback level instead of USB_BUS_TPL to avoid TPL conflict + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + ReturnStatus = EFI_SUCCESS; + for (Index = 0; Index < NumberOfChildren; Index++) { + Status = gBS->OpenProtocol ( + ChildHandleBuffer[Index], + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + // + // It is possible that the child has already been released: + // 1. For combo device, free one device will release others. + // 2. If a hub is released, all devices on its down facing + // ports are released also. + // + continue; + } + + UsbIf = USB_INTERFACE_FROM_USBIO (UsbIo); + UsbDev = UsbIf->Device; + + ReturnStatus = UsbRemoveDevice (UsbDev); + } + + gBS->RestoreTPL (OldTpl); + return ReturnStatus; + } + + DEBUG ((DEBUG_INFO, "UsbBusStop: usb bus stopped on %p\n", Controller)); + + // + // Locate USB_BUS for the current host controller + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiCallerIdGuid, + (VOID **)&BusId, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Bus = USB_BUS_FROM_THIS (BusId); + + // + // Stop the root hub, then free all the devices + // + // BugBug: Raise TPL to callback level instead of USB_BUS_TPL to avoid TPL conflict + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + RootHub = Bus->Devices[0]; + RootIf = RootHub->Interfaces[0]; + + ASSERT (Bus->MaxDevices <= 256); + ReturnStatus = EFI_SUCCESS; + for (Index = 1; Index < Bus->MaxDevices; Index++) { + if (Bus->Devices[Index] != NULL) { + Status = UsbRemoveDevice (Bus->Devices[Index]); + if (EFI_ERROR (Status)) { + ReturnStatus = Status; + } + } + } + + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR (ReturnStatus)) { + mUsbRootHubApi.Release (RootIf); + gBS->FreePool (RootIf); + gBS->FreePool (RootHub); + + Status = UsbBusFreeUsbDPList (&Bus->WantedUsbIoDPList); + ASSERT (!EFI_ERROR (Status)); + + // + // Uninstall the bus identifier and close USB_HC/USB2_HC protocols + // + gBS->UninstallProtocolInterface (Controller, &gEfiCallerIdGuid, &Bus->BusId); + + if (Bus->Usb2Hc != NULL) { + Status = gBS->CloseProtocol ( + Controller, + &gEfiUsb2HcProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + if (Bus->UsbHc != NULL) { + Status = gBS->CloseProtocol ( + Controller, + &gEfiUsbHcProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + if (!EFI_ERROR (Status)) { + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + gBS->FreePool (Bus); + } + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h new file mode 100644 index 0000000000000000000000000000000000000000..58f645d9a577254a1d3ab12153b3c8d1faa5858f --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h @@ -0,0 +1,191 @@ +/** @file + Definition for the USB mass storage Bulk-Only Transport protocol, + based on the "Universal Serial Bus Mass Storage Class Bulk-Only + Transport" Revision 1.0, September 31, 1999. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_USBMASS_BOT_H_ +#define _EFI_USBMASS_BOT_H_ + +extern USB_MASS_TRANSPORT mUsbBotTransport; + +// +// Usb Bulk-Only class specific request +// +#define USB_BOT_RESET_REQUEST 0xFF ///< Bulk-Only Mass Storage Reset +#define USB_BOT_GETLUN_REQUEST 0xFE ///< Get Max Lun +#define USB_BOT_CBW_SIGNATURE 0x43425355 ///< dCBWSignature, tag the packet as CBW +#define USB_BOT_CSW_SIGNATURE 0x53425355 ///< dCSWSignature, tag the packet as CSW +#define USB_BOT_MAX_LUN 0x0F ///< Lun number is from 0 to 15 +#define USB_BOT_MAX_CMDLEN 16 ///< Maximum number of command from command set + +// +// Usb BOT command block status values +// +#define USB_BOT_COMMAND_OK 0x00 ///< Command passed, good status +#define USB_BOT_COMMAND_FAILED 0x01 ///< Command failed +#define USB_BOT_COMMAND_ERROR 0x02 ///< Phase error, need to reset the device + +// +// Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times] +// +#define USB_BOT_RECV_CSW_RETRY 3 + +// +// Usb Bot wait device reset complete, set by experience +// +// AMD_EDKII_OVERRIDE START +#define USB_BOT_RESET_DEVICE_STALL (60 * USB_MASS_1_SECOND) +// AMD_EDKII_OVERRIDE END + +// +// Usb Bot transport timeout, set by experience +// +#define USB_BOT_SEND_CBW_TIMEOUT (3 * USB_MASS_1_SECOND) +#define USB_BOT_RECV_CSW_TIMEOUT (3 * USB_MASS_1_SECOND) +#define USB_BOT_RESET_DEVICE_TIMEOUT (3 * USB_MASS_1_SECOND) + +#pragma pack(1) +/// +/// The CBW (Command Block Wrapper) structures used by the USB BOT protocol. +/// +typedef struct { + UINT32 Signature; + UINT32 Tag; + UINT32 DataLen; ///< Length of data between CBW and CSW + UINT8 Flag; ///< Bit 7, 0 ~ Data-Out, 1 ~ Data-In + UINT8 Lun; ///< Lun number. Bits 0~3 are used + UINT8 CmdLen; ///< Length of the command. Bits 0~4 are used + UINT8 CmdBlock[USB_BOT_MAX_CMDLEN]; +} USB_BOT_CBW; + +/// +/// The and CSW (Command Status Wrapper) structures used by the USB BOT protocol. +/// +typedef struct { + UINT32 Signature; + UINT32 Tag; + UINT32 DataResidue; + UINT8 CmdStatus; +} USB_BOT_CSW; +#pragma pack() + +typedef struct { + // + // Put Interface at the first field to make it easy to distinguish BOT/CBI Protocol instance + // + EFI_USB_INTERFACE_DESCRIPTOR Interface; + EFI_USB_ENDPOINT_DESCRIPTOR *BulkInEndpoint; + EFI_USB_ENDPOINT_DESCRIPTOR *BulkOutEndpoint; + UINT32 CbwTag; + EFI_USB_IO_PROTOCOL *UsbIo; +} USB_BOT_PROTOCOL; + +/** + Initializes USB BOT protocol. + + This function initializes the USB mass storage class BOT protocol. + It will save its context which is a USB_BOT_PROTOCOL structure + in the Context if Context isn't NULL. + + @param UsbIo The USB I/O Protocol instance + @param Context The buffer to save the context to + + @retval EFI_SUCCESS The device is successfully initialized. + @retval EFI_UNSUPPORTED The transport protocol doesn't support the device. + @retval Other The USB BOT initialization fails. + +**/ +EFI_STATUS +UsbBotInit ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + OUT VOID **Context OPTIONAL + ); + +/** + Call the USB Mass Storage Class BOT protocol to issue + the command/data/status circle to execute the commands. + + @param Context The context of the BOT protocol, that is, + USB_BOT_PROTOCOL + @param Cmd The high level command + @param CmdLen The command length + @param DataDir The direction of the data transfer + @param Data The buffer to hold data + @param DataLen The length of the data + @param Lun The number of logic unit + @param Timeout The time to wait command + @param CmdStatus The result of high level command execution + + @retval EFI_SUCCESS The command is executed successfully. + @retval Other Failed to execute command + +**/ +EFI_STATUS +UsbBotExecCommand ( + IN VOID *Context, + IN VOID *Cmd, + IN UINT8 CmdLen, + IN EFI_USB_DATA_DIRECTION DataDir, + IN VOID *Data, + IN UINT32 DataLen, + IN UINT8 Lun, + IN UINT32 Timeout, + OUT UINT32 *CmdStatus + ); + +/** + Reset the USB mass storage device by BOT protocol. + + @param Context The context of the BOT protocol, that is, + USB_BOT_PROTOCOL. + @param ExtendedVerification If FALSE, just issue Bulk-Only Mass Storage Reset request. + If TRUE, additionally reset parent hub port. + + @retval EFI_SUCCESS The device is reset. + @retval Others Failed to reset the device.. + +**/ +EFI_STATUS +UsbBotResetDevice ( + IN VOID *Context, + IN BOOLEAN ExtendedVerification + ); + +/** + Get the max LUN (Logical Unit Number) of USB mass storage device. + + @param Context The context of the BOT protocol, that is, USB_BOT_PROTOCOL + @param MaxLun Return pointer to the max number of LUN. (e.g. MaxLun=1 means LUN0 and + LUN1 in all.) + + @retval EFI_SUCCESS Max LUN is got successfully. + @retval Others Fail to execute this request. + +**/ +EFI_STATUS +UsbBotGetMaxLun ( + IN VOID *Context, + OUT UINT8 *MaxLun + ); + +/** + Clean up the resource used by this BOT protocol. + + @param Context The context of the BOT protocol, that is, USB_BOT_PROTOCOL. + + @retval EFI_SUCCESS The resource is cleaned up. + +**/ +EFI_STATUS +UsbBotCleanUp ( + IN VOID *Context + ); + +#endif diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c new file mode 100644 index 0000000000000000000000000000000000000000..ad24b3c44cf250f11dec3e470188a213a6d79167 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c @@ -0,0 +1,1141 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** @file + USB Mass Storage Driver that manages USB Mass Storage Device and produces Block I/O Protocol. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsbMass.h" + +#define USB_MASS_TRANSPORT_COUNT 3 +// +// Array of USB transport interfaces. +// +USB_MASS_TRANSPORT *mUsbMassTransport[USB_MASS_TRANSPORT_COUNT] = { + &mUsbCbi0Transport, + &mUsbCbi1Transport, + &mUsbBotTransport, +}; + +EFI_DRIVER_BINDING_PROTOCOL gUSBMassDriverBinding = { + USBMassDriverBindingSupported, + USBMassDriverBindingStart, + USBMassDriverBindingStop, + 0x11, + NULL, + NULL +}; + +/** + Reset the block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.Reset(). + It resets the block device hardware. + ExtendedVerification is ignored in this implementation. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Indicates that the driver may perform a more exhaustive + verification operation of the device during reset. + + @retval EFI_SUCCESS The block device was reset. + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset. + +**/ +EFI_STATUS +EFIAPI +UsbMassReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_TPL OldTpl; + EFI_STATUS Status; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Status = UsbMass->Transport->Reset (UsbMass->Context, ExtendedVerification); + + gBS->RestoreTPL (OldTpl); + + return Status; +} + +/** + Reads the requested number of blocks from the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks(). + It reads the requested number of blocks from the device. + All the blocks are read, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the read request is for. + @param Lba The starting logical block address to read from on the device. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +UsbMassReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN TotalBlock; + + // AMD_EDKII_OVERRIDE START + INT8 ResetRetryCount; + VOID *OriginalBuffer; + EFI_LBA OriginalLba; + UINTN OriginalBufferSize; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Media = &UsbMass->BlockIoMedia; + + ResetRetryCount = 3; + OriginalBuffer = Buffer; + OriginalBufferSize = BufferSize; + OriginalLba = Lba; + + while (ResetRetryCount >= 0) { + + Buffer = OriginalBuffer; + Lba = OriginalLba; + BufferSize = OriginalBufferSize; + + // + // If it is a removable media, such as CD-Rom or Usb-Floppy, + // need to detect the media before each read/write. While some of + // Usb-Flash is marked as removable media. + // + if (Media->RemovableMedia) { + Status = UsbBootDetectMedia (UsbMass); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + } + + if (!(Media->MediaPresent)) { + Status = EFI_NO_MEDIA; + goto ON_EXIT; + } + + if (MediaId != Media->MediaId) { + Status = EFI_MEDIA_CHANGED; + goto ON_EXIT; + } + + if (BufferSize == 0) { + Status = EFI_SUCCESS; + goto ON_EXIT; + } + + if (Buffer == NULL) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // BufferSize must be a multiple of the intrinsic block size of the device. + // + if ((BufferSize % Media->BlockSize) != 0) { + Status = EFI_BAD_BUFFER_SIZE; + goto ON_EXIT; + } + + TotalBlock = BufferSize / Media->BlockSize; + + // + // Make sure the range to read is valid. + // + if (Lba + TotalBlock - 1 > Media->LastBlock) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + if (UsbMass->Cdb16Byte) { + Status = UsbBootReadWriteBlocks16 (UsbMass, FALSE, Lba, TotalBlock, Buffer); + } else { + Status = UsbBootReadWriteBlocks (UsbMass, FALSE, (UINT32)Lba, TotalBlock, Buffer); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassReadBlocks: UsbBootReadBlocks (%r) -> Reset\n", Status)); + UsbMassReset (This, TRUE); + ResetRetryCount--; + } + else { + break; + } + } + // AMD_EDKII_OVERRIDE END +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Writes a specified number of blocks to the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks(). + It writes a specified number of blocks to the device. + All blocks are written, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer Pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data were written correctly to the device. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +UsbMassWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN TotalBlock; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Media = &UsbMass->BlockIoMedia; + + // + // If it is a removable media, such as CD-Rom or Usb-Floppy, + // need to detect the media before each read/write. Some of + // USB Flash is marked as removable media. + // + if (Media->RemovableMedia) { + Status = UsbBootDetectMedia (UsbMass); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + } + + if (!(Media->MediaPresent)) { + Status = EFI_NO_MEDIA; + goto ON_EXIT; + } + + if (MediaId != Media->MediaId) { + Status = EFI_MEDIA_CHANGED; + goto ON_EXIT; + } + + if (BufferSize == 0) { + Status = EFI_SUCCESS; + goto ON_EXIT; + } + + if (Buffer == NULL) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // BufferSize must be a multiple of the intrinsic block size of the device. + // + if ((BufferSize % Media->BlockSize) != 0) { + Status = EFI_BAD_BUFFER_SIZE; + goto ON_EXIT; + } + + TotalBlock = BufferSize / Media->BlockSize; + + // + // Make sure the range to write is valid. + // + if (Lba + TotalBlock - 1 > Media->LastBlock) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // Try to write the data even the device is marked as ReadOnly, + // and clear the status should the write succeed. + // + if (UsbMass->Cdb16Byte) { + Status = UsbBootReadWriteBlocks16 (UsbMass, TRUE, Lba, TotalBlock, Buffer); + } else { + Status = UsbBootReadWriteBlocks (UsbMass, TRUE, (UINT32)Lba, TotalBlock, Buffer); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassWriteBlocks: UsbBootWriteBlocks (%r) -> Reset\n", Status)); + UsbMassReset (This, TRUE); + } + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Flushes all modified data to a physical block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.FlushBlocks(). + USB mass storage device doesn't support write cache, + so return EFI_SUCCESS directly. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data were written correctly to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data. + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +EFI_STATUS +EFIAPI +UsbMassFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + + @param UsbMass The USB mass storage device + + @retval EFI_SUCCESS The media parameters are updated successfully. + @retval Others Failed to get the media parameters. + +**/ +EFI_STATUS +UsbMassInitMedia ( + IN USB_MASS_DEVICE *UsbMass + ) +{ + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + + Media = &UsbMass->BlockIoMedia; + + // + // Fields of EFI_BLOCK_IO_MEDIA are defined in UEFI 2.0 spec, + // section for Block I/O Protocol. + // + Media->MediaPresent = FALSE; + Media->LogicalPartition = FALSE; + Media->ReadOnly = FALSE; + Media->WriteCaching = FALSE; + Media->IoAlign = 0; + Media->MediaId = 1; + + Status = UsbBootGetParams (UsbMass); + DEBUG ((DEBUG_INFO, "UsbMassInitMedia: UsbBootGetParams (%r)\n", Status)); + if (Status == EFI_MEDIA_CHANGED) { + // + // Some USB storage devices may report MEDIA_CHANGED sense key when hot-plugged. + // Treat it as SUCCESS + // + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Initialize the USB Mass Storage transport. + + This function tries to find the matching USB Mass Storage transport + protocol for USB device. If found, initializes the matching transport. + + @param This The USB mass driver's driver binding. + @param Controller The device to test. + @param Transport The pointer to pointer to USB_MASS_TRANSPORT. + @param Context The parameter for USB_MASS_DEVICE.Context. + @param MaxLun Get the MaxLun if is BOT dev. + + @retval EFI_SUCCESS The initialization is successful. + @retval EFI_UNSUPPORTED No matching transport protocol is found. + @retval Others Failed to initialize dev. + +**/ +EFI_STATUS +UsbMassInitTransport ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + OUT USB_MASS_TRANSPORT **Transport, + OUT VOID **Context, + OUT UINT8 *MaxLun + ) +{ + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_INTERFACE_DESCRIPTOR Interface; + UINT8 Index; + EFI_STATUS Status; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + Status = EFI_UNSUPPORTED; + + // + // Traverse the USB_MASS_TRANSPORT arrary and try to find the + // matching transport protocol. + // If not found, return EFI_UNSUPPORTED. + // If found, execute USB_MASS_TRANSPORT.Init() to initialize the transport context. + // + for (Index = 0; Index < USB_MASS_TRANSPORT_COUNT; Index++) { + *Transport = mUsbMassTransport[Index]; + + if (Interface.InterfaceProtocol == (*Transport)->Protocol) { + Status = (*Transport)->Init (UsbIo, Context); + break; + } + } + + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + // + // For BOT device, try to get its max LUN. + // If max LUN is 0, then it is a non-lun device. + // Otherwise, it is a multi-lun device. + // + if ((*Transport)->Protocol == USB_MASS_STORE_BOT) { + (*Transport)->GetMaxLun (*Context, MaxLun); + } + +ON_EXIT: + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + return Status; +} + +/** + Initialize data for device that supports multiple LUNSs. + + @param This The Driver Binding Protocol instance. + @param Controller The device to initialize. + @param Transport Pointer to USB_MASS_TRANSPORT. + @param Context Parameter for USB_MASS_DEVICE.Context. + @param DevicePath The remaining device path. + @param MaxLun The max LUN number. + + @retval EFI_SUCCESS At least one LUN is initialized successfully. + @retval EFI_NOT_FOUND Fail to initialize any of multiple LUNs. + +**/ +EFI_STATUS +UsbMassInitMultiLun ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN USB_MASS_TRANSPORT *Transport, + IN VOID *Context, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN UINT8 MaxLun + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + DEVICE_LOGICAL_UNIT_DEVICE_PATH LunNode; + UINT8 Index; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + ASSERT (MaxLun > 0); + ReturnStatus = EFI_NOT_FOUND; + + for (Index = 0; Index <= MaxLun; Index++) { + DEBUG ((DEBUG_INFO, "UsbMassInitMultiLun: Start to initialize No.%d logic unit\n", Index)); + + UsbIo = NULL; + UsbMass = AllocateZeroPool (sizeof (USB_MASS_DEVICE)); + ASSERT (UsbMass != NULL); + + UsbMass->Signature = USB_MASS_SIGNATURE; + UsbMass->UsbIo = UsbIo; + UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; + UsbMass->BlockIo.Reset = UsbMassReset; + UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; + UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; + UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; + UsbMass->OpticalStorage = FALSE; + UsbMass->Transport = Transport; + UsbMass->Context = Context; + UsbMass->Lun = Index; + + // + // Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + // + Status = UsbMassInitMedia (UsbMass); + if ((EFI_ERROR (Status)) && (Status != EFI_NO_MEDIA)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: UsbMassInitMedia (%r)\n", Status)); + FreePool (UsbMass); + continue; + } + + // + // Create a device path node for device logic unit, and append it. + // + LunNode.Header.Type = MESSAGING_DEVICE_PATH; + LunNode.Header.SubType = MSG_DEVICE_LOGICAL_UNIT_DP; + LunNode.Lun = UsbMass->Lun; + + SetDevicePathNodeLength (&LunNode.Header, sizeof (LunNode)); + + UsbMass->DevicePath = AppendDevicePathNode (DevicePath, &LunNode.Header); + + if (UsbMass->DevicePath == NULL) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: failed to create device logic unit device path\n")); + Status = EFI_OUT_OF_RESOURCES; + FreePool (UsbMass); + continue; + } + + InitializeDiskInfo (UsbMass); + + // + // Create a new handle for each LUN, and install Block I/O Protocol and Device Path Protocol. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &UsbMass->Controller, + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: InstallMultipleProtocolInterfaces (%r)\n", Status)); + FreePool (UsbMass->DevicePath); + FreePool (UsbMass); + continue; + } + + // + // Open USB I/O Protocol by child to setup a parent-child relationship. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + UsbMass->Controller, + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: OpenUsbIoProtocol By Child (%r)\n", Status)); + gBS->UninstallMultipleProtocolInterfaces ( + UsbMass->Controller, + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + FreePool (UsbMass->DevicePath); + FreePool (UsbMass); + continue; + } + + ReturnStatus = EFI_SUCCESS; + DEBUG ((DEBUG_INFO, "UsbMassInitMultiLun: Success to initialize No.%d logic unit\n", Index)); + } + + return ReturnStatus; +} + +/** + Initialize data for device that does not support multiple LUNSs. + + @param This The Driver Binding Protocol instance. + @param Controller The device to initialize. + @param Transport Pointer to USB_MASS_TRANSPORT. + @param Context Parameter for USB_MASS_DEVICE.Context. + + @retval EFI_SUCCESS Initialization succeeds. + @retval Other Initialization fails. + +**/ +EFI_STATUS +UsbMassInitNonLun ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN USB_MASS_TRANSPORT *Transport, + IN VOID *Context + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_STATUS Status; + + UsbIo = NULL; + UsbMass = AllocateZeroPool (sizeof (USB_MASS_DEVICE)); + ASSERT (UsbMass != NULL); + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitNonLun: OpenUsbIoProtocol By Driver (%r)\n", Status)); + goto ON_ERROR; + } + + UsbMass->Signature = USB_MASS_SIGNATURE; + UsbMass->Controller = Controller; + UsbMass->UsbIo = UsbIo; + UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; + UsbMass->BlockIo.Reset = UsbMassReset; + UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; + UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; + UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; + UsbMass->OpticalStorage = FALSE; + UsbMass->Transport = Transport; + UsbMass->Context = Context; + + // + // Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + // + Status = UsbMassInitMedia (UsbMass); + if ((EFI_ERROR (Status)) && (Status != EFI_NO_MEDIA)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitNonLun: UsbMassInitMedia (%r)\n", Status)); + goto ON_ERROR; + } + + InitializeDiskInfo (UsbMass); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Controller, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + return EFI_SUCCESS; + +ON_ERROR: + if (UsbMass != NULL) { + FreePool (UsbMass); + } + + if (UsbIo != NULL) { + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + return Status; +} + +/** + Check whether the controller is a supported USB mass storage. + + @param This The USB mass storage driver binding protocol. + @param Controller The controller handle to check. + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS The driver supports this controller. + @retval other This device isn't supported. + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_INTERFACE_DESCRIPTOR Interface; + USB_MASS_TRANSPORT *Transport; + EFI_STATUS Status; + UINTN Index; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Get the interface descriptor to check the USB class and find a transport + // protocol handler. + // + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + Status = EFI_UNSUPPORTED; + + if (Interface.InterfaceClass != USB_MASS_STORE_CLASS) { + goto ON_EXIT; + } + + // + // Traverse the USB_MASS_TRANSPORT arrary and try to find the + // matching transport method. + // If not found, return EFI_UNSUPPORTED. + // If found, execute USB_MASS_TRANSPORT.Init() to initialize the transport context. + // + for (Index = 0; Index < USB_MASS_TRANSPORT_COUNT; Index++) { + Transport = mUsbMassTransport[Index]; + if (Interface.InterfaceProtocol == Transport->Protocol) { + Status = Transport->Init (UsbIo, NULL); + break; + } + } + +ON_EXIT: + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + return Status; +} + +/** + Starts the USB mass storage device with this driver. + + This function consumes USB I/O Protocol, initializes USB mass storage device, + installs Block I/O Protocol, and submits Asynchronous Interrupt + Transfer to manage the USB mass storage device. + + @param This The USB mass storage driver binding protocol. + @param Controller The USB mass storage device to start on + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS This driver supports this device. + @retval EFI_UNSUPPORTED This driver does not support this device. + @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error. + @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources. + @retval EFI_ALREADY_STARTED This driver has been started. + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + USB_MASS_TRANSPORT *Transport; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + VOID *Context; + UINT8 MaxLun; + EFI_STATUS Status; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_TPL OldTpl; + + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + Transport = NULL; + Context = NULL; + MaxLun = 0; + + Status = UsbMassInitTransport (This, Controller, &Transport, &Context, &MaxLun); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitTransport (%r)\n", Status)); + goto Exit; + } + + if (MaxLun == 0) { + // + // Initialize data for device that does not support multiple LUNSs. + // + Status = UsbMassInitNonLun (This, Controller, Transport, Context); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitNonLun (%r)\n", Status)); + } + } else { + // + // Open device path to prepare for appending Device Logic Unit node. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID **)&DevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: OpenDevicePathProtocol By Driver (%r)\n", Status)); + goto Exit; + } + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: OpenUsbIoProtocol By Driver (%r)\n", Status)); + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + goto Exit; + } + + // + // Initialize data for device that supports multiple LUNs. + // EFI_SUCCESS is returned if at least 1 LUN is initialized successfully. + // + Status = UsbMassInitMultiLun (This, Controller, Transport, Context, DevicePath, MaxLun); + if (EFI_ERROR (Status)) { + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitMultiLun (%r) with Maxlun=%d\n", Status, MaxLun)); + } + } + +Exit: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Stop controlling the device. + + @param This The USB mass storage driver binding + @param Controller The device controller controlled by the driver. + @param NumberOfChildren The number of children of this device + @param ChildHandleBuffer The buffer of children handle. + + @retval EFI_SUCCESS The driver stopped from controlling the device. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error. + @retval EFI_UNSUPPORTED Block I/O Protocol is not installed on Controller. + @retval Others Failed to stop the driver + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status; + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_BLOCK_IO_PROTOCOL *BlockIo; + UINTN Index; + BOOLEAN AllChildrenStopped; + + // + // This is a bus driver stop function since multi-lun is supported. + // There are three kinds of device handles that might be passed: + // 1st is a handle with USB I/O & Block I/O installed (non-multi-lun) + // 2nd is a handle with Device Path & USB I/O installed (multi-lun root) + // 3rd is a handle with Device Path & USB I/O & Block I/O installed (multi-lun). + // + if (NumberOfChildren == 0) { + // + // A handle without any children, might be 1st and 2nd type. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiBlockIoProtocolGuid, + (VOID **)&BlockIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + // + // This is a 2nd type handle(multi-lun root), it needs to close devicepath + // and usbio protocol. + // + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + DEBUG ((DEBUG_INFO, "Success to stop multi-lun root handle\n")); + return EFI_SUCCESS; + } + + // + // This is a 1st type handle(non-multi-lun), which only needs to uninstall + // Block I/O Protocol, close USB I/O Protocol and free mass device. + // + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (BlockIo); + + // + // Uninstall Block I/O protocol from the device handle, + // then call the transport protocol to stop itself. + // + Status = gBS->UninstallMultipleProtocolInterfaces ( + Controller, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + UsbMass->Transport->CleanUp (UsbMass->Context); + FreePool (UsbMass); + + DEBUG ((DEBUG_INFO, "Success to stop non-multi-lun root handle\n")); + return EFI_SUCCESS; + } + + // + // This is a 3rd type handle(multi-lun), which needs uninstall + // Block I/O Protocol and Device Path Protocol, close USB I/O Protocol and + // free mass device for all children. + // + AllChildrenStopped = TRUE; + + for (Index = 0; Index < NumberOfChildren; Index++) { + Status = gBS->OpenProtocol ( + ChildHandleBuffer[Index], + &gEfiBlockIoProtocolGuid, + (VOID **)&BlockIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + AllChildrenStopped = FALSE; + DEBUG ((DEBUG_ERROR, "Fail to stop No.%d multi-lun child handle when opening blockio\n", (UINT32)Index)); + continue; + } + + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (BlockIo); + + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + ChildHandleBuffer[Index] + ); + + Status = gBS->UninstallMultipleProtocolInterfaces ( + ChildHandleBuffer[Index], + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + + if (EFI_ERROR (Status)) { + // + // Fail to uninstall Block I/O Protocol and Device Path Protocol, so re-open USB I/O Protocol by child. + // + AllChildrenStopped = FALSE; + DEBUG ((DEBUG_ERROR, "Fail to stop No.%d multi-lun child handle when uninstalling blockio and devicepath\n", (UINT32)Index)); + + gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + ChildHandleBuffer[Index], + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER + ); + } else { + // + // Succeed to stop this multi-lun handle, so go on with next child. + // + if (((Index + 1) == NumberOfChildren) && AllChildrenStopped) { + UsbMass->Transport->CleanUp (UsbMass->Context); + } + + FreePool (UsbMass); + } + } + + if (!AllChildrenStopped) { + return EFI_DEVICE_ERROR; + } + + DEBUG ((DEBUG_INFO, "Success to stop all %d multi-lun children handles\n", (UINT32)NumberOfChildren)); + return EFI_SUCCESS; +} + +/** + Entrypoint of USB Mass Storage Driver. + + This function is the entrypoint of USB Mass Storage Driver. It installs Driver Binding + Protocol together with Component Name Protocols. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +USBMassStorageEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Install driver binding protocol + // + Status = EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gUSBMassDriverBinding, + ImageHandle, + &gUsbMassStorageComponentName, + &gUsbMassStorageComponentName2 + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Include/Library/SpiHcPlatformLib.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Include/Library/SpiHcPlatformLib.h new file mode 100644 index 0000000000000000000000000000000000000000..1b369d8b993aab6584f5788a13dcbd29ddb2d4e3 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Include/Library/SpiHcPlatformLib.h @@ -0,0 +1,148 @@ +/** @file + + Function declarations for SpiHcPlatformLib + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PLATFORM_SPI_HC_H_ +#define PLATFORM_SPI_HC_H_ + +#include +#include +#include +#include +#include + +/** + This function reports the details of the SPI Host Controller to the SpiHc driver. + + @param[out] Attributes The suported attributes of the SPI host controller + @param[out] FrameSizeSupportMask The suported FrameSizeSupportMask of the SPI host controller + @param[out] MaximumTransferBytes The suported MaximumTransferBytes of the SPI host controller + + @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly + @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated +*/ +EFI_STATUS +EFIAPI +GetPlatformSpiHcDetails ( + OUT UINT32 *Attributes, + OUT UINT32 *FrameSizeSupportMask, + OUT UINT32 *MaximumTransferBytes + ); + +/** + This function reports the device path of SPI host controller. This is needed in order for the SpiBus + to match the correct SPI_BUS to the SPI host controller + + @param[out] DevicePath The device path for this SPI HC is returned in this variable + + @retval EFI_SUCCESS +*/ +EFI_STATUS +EFIAPI +GetSpiHcDevicePath ( + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + This is the platform specific Spi Chip select function. + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + This function is the platform specific SPI clock function. + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcClock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/** + This function is the platform specific SPI transaction function + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcTransaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ); + +#endif // PLATFORM_SPI_HC_SMM_PROTOCOL_H_ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.c new file mode 100644 index 0000000000000000000000000000000000000000..0acb5b2b9068efc972dd7b52da10e4d1b94d2de6 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.c @@ -0,0 +1,146 @@ +/** @file + + Null implementation of SpiHcPlatformLib + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include + +/** + This function reports the details of the SPI Host Controller to the SpiHc driver. + + @param[in, out] Protocol The EFI_SPI_HC_PROTOCOL created in the SpiHc driver. + @param[out] Attributes The suported attributes of the SPI host controller + @param[out] FrameSizeSupportMask The suported FrameSizeSupportMask of the SPI host controller + @param[out] MaximumTransferBytes The suported MaximumTransferBytes of the SPI host controller + + @retval EFI_UNSUPPORTED +*/ +EFI_STATUS +EFIAPI +GetPlatformSpiHcDetails ( + OUT UINT32 *Attributes, + OUT UINT32 *FrameSizeSupportMask, + OUT UINT32 *MaximumTransferBytes + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function reports the device path of SPI host controller. This is needed in order for the SpiBus + to match the correct SPI_BUS to the SPI host controller + + @param[out] DevicePath The device path for this SPI HC is returned in this variable + + @retval EFI_UNSUPPORTED +*/ +EFI_STATUS +EFIAPI +GetSpiHcDevicePath ( + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This is the platform specific Spi Chip select function. + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_UNSUPPORTED + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function is the platform specific SPI clock function. + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_UNSUPPORTED + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcClock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function is the platform specific SPI transaction function + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_UNSUPPORTED + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcTransaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.inf b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.inf new file mode 100644 index 0000000000000000000000000000000000000000..96dff0e97a0024b44ee86bc72d686f8b8282badc --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.inf @@ -0,0 +1,34 @@ +#/** @file +# +# NULL library for platform SPI Host controller, which should be provided +# by the OEM. +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +#**/ +[Defines] + INF_VERSION = 1.27 + BASE_NAME = BaseSpiHcPlatformLibNull + FILE_GUID = 3C230948-6DF5-4802-8177-967A190579CF + MODULE_TYPE = BASE + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + LIBRARY_CLASS = SpiHcPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + DevicePathLib + UefiLib + +[Sources] + BaseSpiHcPlatformLibNull.c + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + BaseSpiHcPlatformLibNull.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.uni b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.uni new file mode 100644 index 0000000000000000000000000000000000000000..f3d54d71ea7c8f2cf26b484905c748b0792f9c85 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.uni @@ -0,0 +1,10 @@ +// /** @file +// +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "Null SPI Host controller library" diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.c new file mode 100644 index 0000000000000000000000000000000000000000..eaba59a59c2003d36aaf56c62901209d59ba4f53 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.c @@ -0,0 +1,1147 @@ +/** @file + + Provides definitions and functionality for manipulating IMAGE_PROPERTIES_RECORD. + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#define PREVIOUS_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \ + ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) - (Size))) + +#define NEXT_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \ + ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) + (Size))) + +/** + Converts a number of pages to a size in bytes. + + NOTE: Do not use EFI_PAGES_TO_SIZE because it handles UINTN only. + + @param[in] Pages The number of EFI_PAGES. + + @retval The number of bytes associated with the input number of pages. +**/ +STATIC +UINT64 +EfiPagesToSize ( + IN UINT64 Pages + ) +{ + return LShiftU64 (Pages, EFI_PAGE_SHIFT); +} + +/** + Converts a size, in bytes, to a number of EFI_PAGESs. + + NOTE: Do not use EFI_SIZE_TO_PAGES because it handles UINTN only. + + @param[in] Size A size in bytes. + + @retval The number of pages associated with the input number of bytes. + +**/ +STATIC +UINT64 +EfiSizeToPages ( + IN UINT64 Size + ) +{ + return RShiftU64 (Size, EFI_PAGE_SHIFT) + ((((UINTN)Size) & EFI_PAGE_MASK) ? 1 : 0); +} + +/** + Sort memory map entries based upon PhysicalStart from low to high. + + @param[in, out] MemoryMap A pointer to the buffer in which firmware places + the current memory map. + @param[in] MemoryMapSize Size, in bytes, of the MemoryMap buffer. + @param[in] DescriptorSize Size, in bytes, of an individual EFI_MEMORY_DESCRIPTOR. +**/ +STATIC +VOID +SortMemoryMap ( + IN OUT EFI_MEMORY_DESCRIPTOR *MemoryMap, + IN UINTN MemoryMapSize, + IN UINTN DescriptorSize + ) +{ + EFI_MEMORY_DESCRIPTOR *MemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *MemoryMapEnd; + EFI_MEMORY_DESCRIPTOR TempMemoryMap; + + MemoryMapEntry = MemoryMap; + NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + MemoryMapSize); + while (MemoryMapEntry < MemoryMapEnd) { + while (NextMemoryMapEntry < MemoryMapEnd) { + if (MemoryMapEntry->PhysicalStart > NextMemoryMapEntry->PhysicalStart) { + CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); + CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); + CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof (EFI_MEMORY_DESCRIPTOR)); + } + + NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NextMemoryMapEntry, DescriptorSize); + } + + MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + } + + return; +} + +/** + Return the first image record, whose [ImageBase, ImageSize] covered by [Buffer, Length]. + + @param[in] Buffer Starting Address + @param[in] Length Length to check + @param[in] ImageRecordList A list of IMAGE_PROPERTIES_RECORD entries to check against + the memory range Buffer -> Buffer + Length + + @retval The first image record covered by [Buffer, Length] +**/ +STATIC +IMAGE_PROPERTIES_RECORD * +GetImageRecordByAddress ( + IN EFI_PHYSICAL_ADDRESS Buffer, + IN UINT64 Length, + IN LIST_ENTRY *ImageRecordList + ) +{ + IMAGE_PROPERTIES_RECORD *ImageRecord; + LIST_ENTRY *ImageRecordLink; + + for (ImageRecordLink = ImageRecordList->ForwardLink; + ImageRecordLink != ImageRecordList; + ImageRecordLink = ImageRecordLink->ForwardLink) + { + ImageRecord = CR ( + ImageRecordLink, + IMAGE_PROPERTIES_RECORD, + Link, + IMAGE_PROPERTIES_RECORD_SIGNATURE + ); + + if ((Buffer <= ImageRecord->ImageBase) && + (Buffer + Length >= ImageRecord->ImageBase + ImageRecord->ImageSize)) + { + return ImageRecord; + } + } + + return NULL; +} + +/** + Break up the input OldRecord into multiple new records based on the code + and data sections in the input ImageRecord. + + @param[in] ImageRecord An IMAGE_PROPERTIES_RECORD whose ImageBase and + ImageSize is covered by by OldRecord. + @param[in, out] NewRecord A pointer to several new memory map entries. + The caller gurantee the buffer size be 1 + + (SplitRecordCount * DescriptorSize) calculated + below. + @param[in] OldRecord A pointer to one old memory map entry. + @param[in] DescriptorSize The size, in bytes, of an individual EFI_MEMORY_DESCRIPTOR. + + @retval The number of new descriptors created. +**/ +STATIC +UINTN +SetNewRecord ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord, + IN OUT EFI_MEMORY_DESCRIPTOR *NewRecord, + IN EFI_MEMORY_DESCRIPTOR *OldRecord, + IN UINTN DescriptorSize + ) +{ + EFI_MEMORY_DESCRIPTOR TempRecord; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + LIST_ENTRY *ImageRecordCodeSectionLink; + LIST_ENTRY *ImageRecordCodeSectionEndLink; + LIST_ENTRY *ImageRecordCodeSectionList; + UINTN NewRecordCount; + UINT64 PhysicalEnd; + UINT64 ImageEnd; + + CopyMem (&TempRecord, OldRecord, sizeof (EFI_MEMORY_DESCRIPTOR)); + PhysicalEnd = TempRecord.PhysicalStart + EfiPagesToSize (TempRecord.NumberOfPages); + NewRecordCount = 0; + + ImageRecordCodeSectionList = &ImageRecord->CodeSegmentList; + + ImageRecordCodeSectionLink = ImageRecordCodeSectionList->ForwardLink; + ImageRecordCodeSectionEndLink = ImageRecordCodeSectionList; + while (ImageRecordCodeSectionLink != ImageRecordCodeSectionEndLink) { + ImageRecordCodeSection = CR ( + ImageRecordCodeSectionLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE + ); + ImageRecordCodeSectionLink = ImageRecordCodeSectionLink->ForwardLink; + + if (TempRecord.PhysicalStart <= ImageRecordCodeSection->CodeSegmentBase) { + // + // DATA + // + NewRecord->Type = TempRecord.Type; + NewRecord->PhysicalStart = TempRecord.PhysicalStart; + NewRecord->VirtualStart = 0; + NewRecord->NumberOfPages = EfiSizeToPages (ImageRecordCodeSection->CodeSegmentBase - NewRecord->PhysicalStart); + NewRecord->Attribute = TempRecord.Attribute | EFI_MEMORY_XP; + if (NewRecord->NumberOfPages != 0) { + NewRecord = NEXT_MEMORY_DESCRIPTOR (NewRecord, DescriptorSize); + NewRecordCount++; + } + + // + // CODE + // + NewRecord->Type = TempRecord.Type; + NewRecord->PhysicalStart = ImageRecordCodeSection->CodeSegmentBase; + NewRecord->VirtualStart = 0; + NewRecord->NumberOfPages = EfiSizeToPages (ImageRecordCodeSection->CodeSegmentSize); + NewRecord->Attribute = (TempRecord.Attribute & (~EFI_MEMORY_XP)) | EFI_MEMORY_RO; + if (NewRecord->NumberOfPages != 0) { + NewRecord = NEXT_MEMORY_DESCRIPTOR (NewRecord, DescriptorSize); + NewRecordCount++; + } + + TempRecord.PhysicalStart = ImageRecordCodeSection->CodeSegmentBase + EfiPagesToSize (EfiSizeToPages (ImageRecordCodeSection->CodeSegmentSize)); + TempRecord.NumberOfPages = EfiSizeToPages (PhysicalEnd - TempRecord.PhysicalStart); + if (TempRecord.NumberOfPages == 0) { + break; + } + } + } + + ImageEnd = ImageRecord->ImageBase + ImageRecord->ImageSize; + + // + // Final DATA + // + if (TempRecord.PhysicalStart < ImageEnd) { + NewRecord->Type = TempRecord.Type; + NewRecord->PhysicalStart = TempRecord.PhysicalStart; + NewRecord->VirtualStart = 0; + NewRecord->NumberOfPages = EfiSizeToPages (ImageEnd - TempRecord.PhysicalStart); + NewRecord->Attribute = TempRecord.Attribute | EFI_MEMORY_XP; + NewRecordCount++; + } + + return NewRecordCount; +} + +/** + Return the maximum number of new entries required to describe the code and data sections + of all images covered by the input OldRecord. + + @param[in] OldRecord A pointer to one old memory map entry. + @param[in] ImageRecordList A list of IMAGE_PROPERTIES_RECORD entries used when searching + for an image record contained by the memory range described by + OldRecord + + @retval The maximum number of new descriptors required to describe the code and data sections + of all images covered by OldRecord. +**/ +STATIC +UINTN +GetMaxSplitRecordCount ( + IN EFI_MEMORY_DESCRIPTOR *OldRecord, + IN LIST_ENTRY *ImageRecordList + ) +{ + IMAGE_PROPERTIES_RECORD *ImageRecord; + UINTN SplitRecordCount; + UINT64 PhysicalStart; + UINT64 PhysicalEnd; + + SplitRecordCount = 0; + PhysicalStart = OldRecord->PhysicalStart; + PhysicalEnd = OldRecord->PhysicalStart + EfiPagesToSize (OldRecord->NumberOfPages); + + do { + ImageRecord = GetImageRecordByAddress (PhysicalStart, PhysicalEnd - PhysicalStart, ImageRecordList); + if (ImageRecord == NULL) { + break; + } + + SplitRecordCount += (2 * ImageRecord->CodeSegmentCount + 3); + PhysicalStart = ImageRecord->ImageBase + ImageRecord->ImageSize; + } while ((ImageRecord != NULL) && (PhysicalStart < PhysicalEnd)); + + if (SplitRecordCount != 0) { + SplitRecordCount--; + } + + return SplitRecordCount; +} + +/** + Split the memory map into new entries based upon the PE code and data sections + in ImageRecordList covered by the input OldRecord. + + @param[in] OldRecord A pointer to one old memory map entry. + @param[in, out] NewRecord A pointer to several new memory map entries. + The caller gurantee the buffer size be + (SplitRecordCount * DescriptorSize). + @param[in] MaxSplitRecordCount The maximum number of entries post-split. + @param[in] DescriptorSize The size, in bytes, of an individual EFI_MEMORY_DESCRIPTOR. + @param[in] ImageRecordList A list of IMAGE_PROPERTIES_RECORD entries used when searching + for an image record contained by the memory range described in + the existing EFI memory map descriptor OldRecord + + @retval The number of split entries. +**/ +STATIC +UINTN +SplitRecord ( + IN EFI_MEMORY_DESCRIPTOR *OldRecord, + IN OUT EFI_MEMORY_DESCRIPTOR *NewRecord, + IN UINTN MaxSplitRecordCount, + IN UINTN DescriptorSize, + IN LIST_ENTRY *ImageRecordList + ) +{ + EFI_MEMORY_DESCRIPTOR TempRecord; + IMAGE_PROPERTIES_RECORD *ImageRecord; + IMAGE_PROPERTIES_RECORD *NewImageRecord; + UINT64 PhysicalStart; + UINT64 PhysicalEnd; + UINTN NewRecordCount; + UINTN TotalNewRecordCount; + BOOLEAN IsLastRecordData; + + if (MaxSplitRecordCount == 0) { + CopyMem (NewRecord, OldRecord, DescriptorSize); + return 0; + } + + TotalNewRecordCount = 0; + + // + // Override previous record + // + CopyMem (&TempRecord, OldRecord, sizeof (EFI_MEMORY_DESCRIPTOR)); + PhysicalStart = TempRecord.PhysicalStart; + PhysicalEnd = TempRecord.PhysicalStart + EfiPagesToSize (TempRecord.NumberOfPages); + + ImageRecord = NULL; + do { + NewImageRecord = GetImageRecordByAddress (PhysicalStart, PhysicalEnd - PhysicalStart, ImageRecordList); + if (NewImageRecord == NULL) { + // + // No more image covered by this range, stop + // + if ((PhysicalEnd > PhysicalStart) && (ImageRecord != NULL)) { + // + // If this is still address in this record, need record. + // + NewRecord = PREVIOUS_MEMORY_DESCRIPTOR (NewRecord, DescriptorSize); + IsLastRecordData = FALSE; + if ((NewRecord->Attribute & EFI_MEMORY_XP) != 0) { + IsLastRecordData = TRUE; + } + + if (IsLastRecordData) { + // + // Last record is DATA, just merge it. + // + NewRecord->NumberOfPages = EfiSizeToPages (PhysicalEnd - NewRecord->PhysicalStart); + } else { + // + // Last record is CODE, create a new DATA entry. + // + NewRecord = NEXT_MEMORY_DESCRIPTOR (NewRecord, DescriptorSize); + NewRecord->Type = TempRecord.Type; + NewRecord->PhysicalStart = TempRecord.PhysicalStart; + NewRecord->VirtualStart = 0; + NewRecord->NumberOfPages = TempRecord.NumberOfPages; + NewRecord->Attribute = TempRecord.Attribute | EFI_MEMORY_XP; + TotalNewRecordCount++; + } + } + + break; + } + + ImageRecord = NewImageRecord; + + // + // Set new record + // + NewRecordCount = SetNewRecord (ImageRecord, NewRecord, &TempRecord, DescriptorSize); + TotalNewRecordCount += NewRecordCount; + NewRecord = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)NewRecord + NewRecordCount * DescriptorSize); + + // + // Update PhysicalStart, in order to exclude the image buffer already splitted. + // + PhysicalStart = ImageRecord->ImageBase + ImageRecord->ImageSize; + TempRecord.PhysicalStart = PhysicalStart; + TempRecord.NumberOfPages = EfiSizeToPages (PhysicalEnd - PhysicalStart); + } while ((ImageRecord != NULL) && (PhysicalStart < PhysicalEnd)); + + // + // The logic in function SplitTable() ensures that TotalNewRecordCount will not be zero if the + // code reaches here. + // + ASSERT (TotalNewRecordCount != 0); + return TotalNewRecordCount - 1; +} + +/** + Split the original memory map and add more entries to describe PE code + and data sections for each image in the input ImageRecordList. + + NOTE: This function assumes PE code/data section are page aligned. + NOTE: This function assumes there are enough entries for the new memory map. + + | | | | | | | | + | 4K PAGE | DATA | CODE | DATA | CODE | DATA | 4K PAGE | + | | | | | | | | + Assume the above memory region is the result of one split memory map descriptor. It's unlikely + that a linker will orient an image this way, but the caller must assume the worst case scenario. + This image layout example contains code sections oriented in a way that maximizes the number of + descriptors which would be required to describe each section. To ensure we have enough space + for every descriptor of the broken up memory map, the caller must assume that every image will + have the maximum number of code sections oriented in a way which maximizes the number of data + sections with unrelated memory regions flanking each image within a single descriptor. + + Given an image record list, the caller should use the following formula when allocating extra descriptors: + NumberOfAdditionalDescriptors = (MemoryMapSize / DescriptorSize) + + ((2 * + 3) * ) + + @param[in, out] MemoryMapSize IN: The size, in bytes, of the old memory map before the split. + OUT: The size, in bytes, of the used descriptors of the split + memory map + @param[in, out] MemoryMap IN: A pointer to the buffer containing the current memory map. + This buffer must have enough space to accomodate the "worst case" + scenario where every image in ImageRecordList needs a new descriptor + to describe its code and data sections. + OUT: A pointer to the updated memory map with separated image section + descriptors. + @param[in] DescriptorSize The size, in bytes, of an individual EFI_MEMORY_DESCRIPTOR. + @param[in] ImageRecordList A list of IMAGE_PROPERTIES_RECORD entries used when searching + for an image record contained by the memory range described in + EFI memory map descriptors. + @param[in] NumberOfAdditionalDescriptors The number of unused descriptors at the end of the input MemoryMap. + The formula in the description should be used to calculate this value. + + @retval EFI_SUCCESS The memory map was successfully split. + @retval EFI_INVALID_PARAMETER MemoryMapSize, MemoryMap, or ImageRecordList was NULL. +**/ +EFI_STATUS +EFIAPI +SplitTable ( + IN OUT UINTN *MemoryMapSize, + IN OUT EFI_MEMORY_DESCRIPTOR *MemoryMap, + IN UINTN DescriptorSize, + IN LIST_ENTRY *ImageRecordList, + IN UINTN NumberOfAdditionalDescriptors + ) +{ + INTN IndexOld; + INTN IndexNew; + INTN IndexNewStarting; + UINTN MaxSplitRecordCount; + UINTN RealSplitRecordCount; + UINTN TotalSkippedRecords; + + if ((MemoryMapSize == NULL) || (MemoryMap == NULL) || (ImageRecordList == NULL)) { + return EFI_INVALID_PARAMETER; + } + + TotalSkippedRecords = 0; + // + // Let old record point to end of valid MemoryMap buffer. + // + IndexOld = ((*MemoryMapSize) / DescriptorSize) - 1; + // + // Let new record point to end of full MemoryMap buffer. + // + IndexNew = ((*MemoryMapSize) / DescriptorSize) - 1 + NumberOfAdditionalDescriptors; + IndexNewStarting = IndexNew; + for ( ; IndexOld >= 0; IndexOld--) { + MaxSplitRecordCount = GetMaxSplitRecordCount ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + IndexOld * DescriptorSize), ImageRecordList); + // + // Split this MemoryMap record + // + IndexNew -= MaxSplitRecordCount; + RealSplitRecordCount = SplitRecord ( + (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + IndexOld * DescriptorSize), + (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + IndexNew * DescriptorSize), + MaxSplitRecordCount, + DescriptorSize, + ImageRecordList + ); + + // If we didn't utilize all the extra allocated descriptor slots, set the physical address of the unused slots + // to MAX_ADDRESS so they are moved to the bottom of the list when sorting. + for ( ; RealSplitRecordCount < MaxSplitRecordCount; RealSplitRecordCount++) { + ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + ((IndexNew + RealSplitRecordCount + 1) * DescriptorSize)))->PhysicalStart = MAX_ADDRESS; + TotalSkippedRecords++; + } + + IndexNew--; + } + + // + // Move all records to the beginning. + // + CopyMem ( + MemoryMap, + (UINT8 *)MemoryMap + ((IndexNew + 1) * DescriptorSize), + (IndexNewStarting - IndexNew) * DescriptorSize + ); + + // + // Sort from low to high to filter out the MAX_ADDRESS records. + // + SortMemoryMap (MemoryMap, (IndexNewStarting - IndexNew) * DescriptorSize, DescriptorSize); + + *MemoryMapSize = (IndexNewStarting - IndexNew - TotalSkippedRecords) * DescriptorSize; + + return EFI_SUCCESS; +} + +/** + Swap two code sections in a single IMAGE_PROPERTIES_RECORD. + + @param[in] FirstImageRecordCodeSection The first code section + @param[in] SecondImageRecordCodeSection The second code section + + @retval EFI_SUCCESS The code sections were swapped successfully + @retval EFI_INVALID_PARAMETER FirstImageRecordCodeSection or SecondImageRecordCodeSection is NULL +**/ +EFI_STATUS +EFIAPI +SwapImageRecordCodeSection ( + IN IMAGE_PROPERTIES_RECORD_CODE_SECTION *FirstImageRecordCodeSection, + IN IMAGE_PROPERTIES_RECORD_CODE_SECTION *SecondImageRecordCodeSection + ) +{ + IMAGE_PROPERTIES_RECORD_CODE_SECTION TempImageRecordCodeSection; + + if ((FirstImageRecordCodeSection == NULL) || (SecondImageRecordCodeSection == NULL)) { + return EFI_INVALID_PARAMETER; + } + + TempImageRecordCodeSection.CodeSegmentBase = FirstImageRecordCodeSection->CodeSegmentBase; + TempImageRecordCodeSection.CodeSegmentSize = FirstImageRecordCodeSection->CodeSegmentSize; + + FirstImageRecordCodeSection->CodeSegmentBase = SecondImageRecordCodeSection->CodeSegmentBase; + FirstImageRecordCodeSection->CodeSegmentSize = SecondImageRecordCodeSection->CodeSegmentSize; + + SecondImageRecordCodeSection->CodeSegmentBase = TempImageRecordCodeSection.CodeSegmentBase; + SecondImageRecordCodeSection->CodeSegmentSize = TempImageRecordCodeSection.CodeSegmentSize; + + return EFI_SUCCESS; +} + +/** + Sort the code sections in the input ImageRecord based upon CodeSegmentBase from low to high. + + @param[in] ImageRecord IMAGE_PROPERTIES_RECORD to be sorted + + @retval EFI_SUCCESS The code sections in the input ImageRecord were sorted successfully + @retval EFI_ABORTED An error occurred while sorting the code sections in the input ImageRecord + @retval EFI_INVALID_PARAMETER ImageRecord is NULL +**/ +EFI_STATUS +EFIAPI +SortImageRecordCodeSection ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord + ) +{ + EFI_STATUS Status; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *NextImageRecordCodeSection; + LIST_ENTRY *ImageRecordCodeSectionLink; + LIST_ENTRY *NextImageRecordCodeSectionLink; + LIST_ENTRY *ImageRecordCodeSectionEndLink; + LIST_ENTRY *ImageRecordCodeSectionList; + + if (ImageRecord == NULL) { + return EFI_INVALID_PARAMETER; + } + + ImageRecordCodeSectionList = &ImageRecord->CodeSegmentList; + + ImageRecordCodeSectionLink = ImageRecordCodeSectionList->ForwardLink; + NextImageRecordCodeSectionLink = ImageRecordCodeSectionLink->ForwardLink; + ImageRecordCodeSectionEndLink = ImageRecordCodeSectionList; + while (ImageRecordCodeSectionLink != ImageRecordCodeSectionEndLink) { + ImageRecordCodeSection = CR ( + ImageRecordCodeSectionLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE + ); + while (NextImageRecordCodeSectionLink != ImageRecordCodeSectionEndLink) { + NextImageRecordCodeSection = CR ( + NextImageRecordCodeSectionLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE + ); + if (ImageRecordCodeSection->CodeSegmentBase > NextImageRecordCodeSection->CodeSegmentBase) { + Status = SwapImageRecordCodeSection (ImageRecordCodeSection, NextImageRecordCodeSection); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_ABORTED; + } + } + + NextImageRecordCodeSectionLink = NextImageRecordCodeSectionLink->ForwardLink; + } + + ImageRecordCodeSectionLink = ImageRecordCodeSectionLink->ForwardLink; + NextImageRecordCodeSectionLink = ImageRecordCodeSectionLink->ForwardLink; + } + + return EFI_SUCCESS; +} + +/** + Check if the code sections in the input ImageRecord are valid. + The code sections are valid if they don't overlap, are contained + within the the ImageRecord's ImageBase and ImageSize, and are + contained within the MAX_ADDRESS. + + @param[in] ImageRecord IMAGE_PROPERTIES_RECORD to be checked + + @retval TRUE The code sections in the input ImageRecord are valid + @retval FALSE The code sections in the input ImageRecord are invalid +**/ +BOOLEAN +EFIAPI +IsImageRecordCodeSectionValid ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord + ) +{ + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *LastImageRecordCodeSection; + LIST_ENTRY *ImageRecordCodeSectionLink; + LIST_ENTRY *ImageRecordCodeSectionEndLink; + LIST_ENTRY *ImageRecordCodeSectionList; + + if (ImageRecord == NULL) { + return FALSE; + } + + DEBUG ((DEBUG_VERBOSE, "ImageCode SegmentCount - 0x%x\n", ImageRecord->CodeSegmentCount)); + + ImageRecordCodeSectionList = &ImageRecord->CodeSegmentList; + + ImageRecordCodeSectionLink = ImageRecordCodeSectionList->ForwardLink; + ImageRecordCodeSectionEndLink = ImageRecordCodeSectionList; + LastImageRecordCodeSection = NULL; + while (ImageRecordCodeSectionLink != ImageRecordCodeSectionEndLink) { + ImageRecordCodeSection = CR ( + ImageRecordCodeSectionLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE + ); + if (ImageRecordCodeSection->CodeSegmentSize == 0) { + return FALSE; + } + + if (ImageRecordCodeSection->CodeSegmentBase < ImageRecord->ImageBase) { + return FALSE; + } + + if (ImageRecordCodeSection->CodeSegmentBase >= MAX_ADDRESS - ImageRecordCodeSection->CodeSegmentSize) { + return FALSE; + } + + if ((ImageRecordCodeSection->CodeSegmentBase + ImageRecordCodeSection->CodeSegmentSize) > (ImageRecord->ImageBase + ImageRecord->ImageSize)) { + return FALSE; + } + + if (LastImageRecordCodeSection != NULL) { + if ((LastImageRecordCodeSection->CodeSegmentBase + LastImageRecordCodeSection->CodeSegmentSize) > ImageRecordCodeSection->CodeSegmentBase) { + return FALSE; + } + } + + LastImageRecordCodeSection = ImageRecordCodeSection; + ImageRecordCodeSectionLink = ImageRecordCodeSectionLink->ForwardLink; + } + + return TRUE; +} + +/** + Swap two image records. + + @param[in] FirstImageRecord The first image record. + @param[in] SecondImageRecord The second image record. + + @retval EFI_SUCCESS The image records were swapped successfully + @retval EFI_INVALID_PARAMETER FirstImageRecord or SecondImageRecord is NULL +**/ +EFI_STATUS +EFIAPI +SwapImageRecord ( + IN IMAGE_PROPERTIES_RECORD *FirstImageRecord, + IN IMAGE_PROPERTIES_RECORD *SecondImageRecord + ) +{ + IMAGE_PROPERTIES_RECORD TempImageRecord; + + if ((FirstImageRecord == NULL) || (SecondImageRecord == NULL)) { + return EFI_INVALID_PARAMETER; + } + + TempImageRecord.ImageBase = FirstImageRecord->ImageBase; + TempImageRecord.ImageSize = FirstImageRecord->ImageSize; + TempImageRecord.CodeSegmentCount = FirstImageRecord->CodeSegmentCount; + + FirstImageRecord->ImageBase = SecondImageRecord->ImageBase; + FirstImageRecord->ImageSize = SecondImageRecord->ImageSize; + FirstImageRecord->CodeSegmentCount = SecondImageRecord->CodeSegmentCount; + + SecondImageRecord->ImageBase = TempImageRecord.ImageBase; + SecondImageRecord->ImageSize = TempImageRecord.ImageSize; + SecondImageRecord->CodeSegmentCount = TempImageRecord.CodeSegmentCount; + + SwapListEntries (&FirstImageRecord->CodeSegmentList, &SecondImageRecord->CodeSegmentList); + return EFI_SUCCESS; +} + +/** + Sort the input ImageRecordList based upon the ImageBase from low to high. + + @param[in] ImageRecordList Image record list to be sorted + + @retval EFI_SUCCESS The image record list was sorted successfully + @retval EFI_ABORTED An error occurred while sorting the image record list + @retval EFI_INVALID_PARAMETER ImageRecordList is NULL +**/ +EFI_STATUS +EFIAPI +SortImageRecord ( + IN LIST_ENTRY *ImageRecordList + ) +{ + IMAGE_PROPERTIES_RECORD *ImageRecord; + IMAGE_PROPERTIES_RECORD *NextImageRecord; + LIST_ENTRY *ImageRecordLink; + LIST_ENTRY *NextImageRecordLink; + LIST_ENTRY *ImageRecordEndLink; + EFI_STATUS Status; + + if (ImageRecordList == NULL) { + return EFI_INVALID_PARAMETER; + } + + ImageRecordLink = ImageRecordList->ForwardLink; + NextImageRecordLink = ImageRecordLink->ForwardLink; + ImageRecordEndLink = ImageRecordList; + while (ImageRecordLink != ImageRecordEndLink) { + ImageRecord = CR ( + ImageRecordLink, + IMAGE_PROPERTIES_RECORD, + Link, + IMAGE_PROPERTIES_RECORD_SIGNATURE + ); + while (NextImageRecordLink != ImageRecordEndLink) { + NextImageRecord = CR ( + NextImageRecordLink, + IMAGE_PROPERTIES_RECORD, + Link, + IMAGE_PROPERTIES_RECORD_SIGNATURE + + ); + if (ImageRecord->ImageBase > NextImageRecord->ImageBase) { + Status = SwapImageRecord (ImageRecord, NextImageRecord); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_ABORTED; + } + } + + NextImageRecordLink = NextImageRecordLink->ForwardLink; + } + + ImageRecordLink = ImageRecordLink->ForwardLink; + NextImageRecordLink = ImageRecordLink->ForwardLink; + } + + return EFI_SUCCESS; +} + +/** + Extract the .efi filename out of the input PDB. + + @param[in] PdbPointer Pointer to the PDB file path. + @param[out] EfiFileName Pointer to the .efi filename. + @param[in] EfiFileNameSize Size of the .efi filename buffer. +**/ +STATIC +VOID +GetFilename ( + IN CHAR8 *PdbPointer, + OUT CHAR8 *EfiFileName, + IN UINTN EfiFileNameSize + ) +{ + UINTN Index; + UINTN StartIndex; + + if ((PdbPointer == NULL) || (EfiFileNameSize < 5)) { + return; + } + + // Print Module Name by Pdb file path. + StartIndex = 0; + for (Index = 0; PdbPointer[Index] != 0; Index++) { + if ((PdbPointer[Index] == '\\') || (PdbPointer[Index] == '/')) { + StartIndex = Index + 1; + } + } + + // Copy the PDB file name to EfiFileName and replace .pdb with .efi + for (Index = 0; Index < EfiFileNameSize - 4; Index++) { + EfiFileName[Index] = PdbPointer[Index + StartIndex]; + if (EfiFileName[Index] == 0) { + EfiFileName[Index] = '.'; + } + + if (EfiFileName[Index] == '.') { + EfiFileName[Index + 1] = 'e'; + EfiFileName[Index + 2] = 'f'; + EfiFileName[Index + 3] = 'i'; + EfiFileName[Index + 4] = 0; + break; + } + } + + if (Index == sizeof (EfiFileName) - 4) { + EfiFileName[Index] = 0; + } +} + +/** + Debug dumps the input list of IMAGE_PROPERTIES_RECORD structs. + + @param[in] ImageRecordList Head of the IMAGE_PROPERTIES_RECORD list +**/ +VOID +EFIAPI +DumpImageRecords ( + IN LIST_ENTRY *ImageRecordList + ) +{ + LIST_ENTRY *ImageRecordLink; + IMAGE_PROPERTIES_RECORD *CurrentImageRecord; + LIST_ENTRY *CodeSectionLink; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *CurrentCodeSection; + CHAR8 *PdbPointer; + CHAR8 EfiFileName[256]; + + if (ImageRecordList == NULL) { + return; + } + + ImageRecordLink = ImageRecordList->ForwardLink; + + while (ImageRecordLink != ImageRecordList) { + CurrentImageRecord = CR ( + ImageRecordLink, + IMAGE_PROPERTIES_RECORD, + Link, + IMAGE_PROPERTIES_RECORD_SIGNATURE + ); + + PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)CurrentImageRecord->ImageBase); + if (PdbPointer != NULL) { + GetFilename (PdbPointer, EfiFileName, sizeof (EfiFileName)); + DEBUG (( + DEBUG_INFO, + "%a: 0x%llx - 0x%llx\n", + EfiFileName, + CurrentImageRecord->ImageBase, + CurrentImageRecord->ImageBase + CurrentImageRecord->ImageSize + )); + } else { + DEBUG (( + DEBUG_INFO, + "Unknown Image: 0x%llx - 0x%llx\n", + CurrentImageRecord->ImageBase, + CurrentImageRecord->ImageBase + CurrentImageRecord->ImageSize + )); + } + + CodeSectionLink = CurrentImageRecord->CodeSegmentList.ForwardLink; + + while (CodeSectionLink != &CurrentImageRecord->CodeSegmentList) { + CurrentCodeSection = CR ( + CodeSectionLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE + ); + + DEBUG (( + DEBUG_INFO, + " Code Section: 0x%llx - 0x%llx\n", + CurrentCodeSection->CodeSegmentBase, + CurrentCodeSection->CodeSegmentBase + CurrentCodeSection->CodeSegmentSize + )); + + CodeSectionLink = CodeSectionLink->ForwardLink; + } + + ImageRecordLink = ImageRecordLink->ForwardLink; + } +} + +/** + Find image record according to image base and size. + + @param[in] ImageBase Base of PE image + @param[in] ImageSize Size of PE image + @param[in] ImageRecordList Image record list to be searched + + @retval NULL No IMAGE_PROPERTIES_RECORD matches ImageBase + and ImageSize in the input ImageRecordList + @retval Other The found IMAGE_PROPERTIES_RECORD +**/ +IMAGE_PROPERTIES_RECORD * +EFIAPI +FindImageRecord ( + IN EFI_PHYSICAL_ADDRESS ImageBase, + IN UINT64 ImageSize, + IN LIST_ENTRY *ImageRecordList + ) +{ + IMAGE_PROPERTIES_RECORD *ImageRecord; + LIST_ENTRY *ImageRecordLink; + + if (ImageRecordList == NULL) { + return NULL; + } + + for (ImageRecordLink = ImageRecordList->ForwardLink; + ImageRecordLink != ImageRecordList; + ImageRecordLink = ImageRecordLink->ForwardLink) + { + ImageRecord = CR ( + ImageRecordLink, + IMAGE_PROPERTIES_RECORD, + Link, + IMAGE_PROPERTIES_RECORD_SIGNATURE + ); + + if ((ImageBase == ImageRecord->ImageBase) && + (ImageSize == ImageRecord->ImageSize)) + { + return ImageRecord; + } + } + + return NULL; +} + +/** + Creates an IMAGE_PROPERTIES_RECORD from a loaded PE image. The PE/COFF header will be found + and parsed to determine the number of code segments and their base addresses and sizes. + + @param[in] ImageBase Base of the PE image + @param[in] ImageSize Size of the PE image + @param[in] RequiredAlignment If non-NULL, the alignment specified in the PE/COFF header + will be compared against this value. + @param[out] ImageRecord On out, a populated image properties record + + @retval EFI_INVALID_PARAMETER This function ImageBase or ImageRecord was NULL, or the + image located at ImageBase was not a valid PE/COFF image + @retval EFI_OUT_OF_RESOURCES Failure to Allocate() + @retval EFI_ABORTED The input Alignment was non-NULL and did not match the + alignment specified in the PE/COFF header + @retval EFI_SUCCESS The image properties record was successfully created +**/ +EFI_STATUS +EFIAPI +CreateImagePropertiesRecord ( + IN CONST VOID *ImageBase, + IN CONST UINT64 ImageSize, + IN CONST UINT32 *RequiredAlignment OPTIONAL, + OUT IMAGE_PROPERTIES_RECORD *ImageRecord + ) +{ + EFI_STATUS Status; + EFI_IMAGE_DOS_HEADER *DosHdr; + EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr; + EFI_IMAGE_SECTION_HEADER *Section; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + UINTN Index; + UINT8 *Name; + UINT32 SectionAlignment; + UINT32 PeCoffHeaderOffset; + + if ((ImageRecord == NULL) || (ImageBase == NULL)) { + return EFI_INVALID_PARAMETER; + } + + DEBUG (( + DEBUG_VERBOSE, + "Creating Image Properties Record: 0x%016lx - 0x%016lx\n", + (EFI_PHYSICAL_ADDRESS)(UINTN)ImageBase, + ImageSize + )); + + // + // Step 1: record whole region + // + Status = EFI_SUCCESS; + ImageRecord->Signature = IMAGE_PROPERTIES_RECORD_SIGNATURE; + ImageRecord->ImageBase = (EFI_PHYSICAL_ADDRESS)(UINTN)ImageBase; + ImageRecord->ImageSize = ImageSize; + ImageRecord->CodeSegmentCount = 0; + InitializeListHead (&ImageRecord->Link); + InitializeListHead (&ImageRecord->CodeSegmentList); + + // Check PE/COFF image + DosHdr = (EFI_IMAGE_DOS_HEADER *)(UINTN)ImageBase; + PeCoffHeaderOffset = 0; + if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) { + PeCoffHeaderOffset = DosHdr->e_lfanew; + } + + Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINT8 *)(UINTN)ImageBase + PeCoffHeaderOffset); + if (Hdr.Pe32->Signature != EFI_IMAGE_NT_SIGNATURE) { + DEBUG ((DEBUG_VERBOSE, "Hdr.Pe32->Signature invalid - 0x%x\n", Hdr.Pe32->Signature)); + return EFI_INVALID_PARAMETER; + } + + // Get SectionAlignment + if (Hdr.Pe32->OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) { + SectionAlignment = Hdr.Pe32->OptionalHeader.SectionAlignment; + } else { + SectionAlignment = Hdr.Pe32Plus->OptionalHeader.SectionAlignment; + } + + // Check RequiredAlignment + if ((RequiredAlignment != NULL) && ((SectionAlignment & (*RequiredAlignment - 1)) != 0)) { + DEBUG (( + DEBUG_WARN, + "!!!!!!!! Image Section Alignment(0x%x) does not match Required Alignment (0x%x) !!!!!!!!\n", + SectionAlignment, + *RequiredAlignment + )); + + return EFI_ABORTED; + } + + Section = (EFI_IMAGE_SECTION_HEADER *)( + (UINT8 *)(UINTN)ImageBase + + PeCoffHeaderOffset + + sizeof (UINT32) + + sizeof (EFI_IMAGE_FILE_HEADER) + + Hdr.Pe32->FileHeader.SizeOfOptionalHeader + ); + for (Index = 0; Index < Hdr.Pe32->FileHeader.NumberOfSections; Index++) { + Name = Section[Index].Name; + DEBUG (( + DEBUG_VERBOSE, + " Section - '%c%c%c%c%c%c%c%c'\n", + Name[0], + Name[1], + Name[2], + Name[3], + Name[4], + Name[5], + Name[6], + Name[7] + )); + + if ((Section[Index].Characteristics & EFI_IMAGE_SCN_CNT_CODE) != 0) { + DEBUG ((DEBUG_VERBOSE, " VirtualSize - 0x%08x\n", Section[Index].Misc.VirtualSize)); + DEBUG ((DEBUG_VERBOSE, " VirtualAddress - 0x%08x\n", Section[Index].VirtualAddress)); + DEBUG ((DEBUG_VERBOSE, " SizeOfRawData - 0x%08x\n", Section[Index].SizeOfRawData)); + DEBUG ((DEBUG_VERBOSE, " PointerToRawData - 0x%08x\n", Section[Index].PointerToRawData)); + DEBUG ((DEBUG_VERBOSE, " PointerToRelocations - 0x%08x\n", Section[Index].PointerToRelocations)); + DEBUG ((DEBUG_VERBOSE, " PointerToLinenumbers - 0x%08x\n", Section[Index].PointerToLinenumbers)); + DEBUG ((DEBUG_VERBOSE, " NumberOfRelocations - 0x%08x\n", Section[Index].NumberOfRelocations)); + DEBUG ((DEBUG_VERBOSE, " NumberOfLinenumbers - 0x%08x\n", Section[Index].NumberOfLinenumbers)); + DEBUG ((DEBUG_VERBOSE, " Characteristics - 0x%08x\n", Section[Index].Characteristics)); + + // Record code section(s) + ImageRecordCodeSection = AllocatePool (sizeof (*ImageRecordCodeSection)); + if (ImageRecordCodeSection == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ImageRecordCodeSection->Signature = IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE; + + ImageRecordCodeSection->CodeSegmentBase = (UINTN)ImageBase + Section[Index].VirtualAddress; + ImageRecordCodeSection->CodeSegmentSize = Section[Index].SizeOfRawData; + + InsertTailList (&ImageRecord->CodeSegmentList, &ImageRecordCodeSection->Link); + ImageRecord->CodeSegmentCount++; + } + } + + if (ImageRecord->CodeSegmentCount > 0) { + SortImageRecordCodeSection (ImageRecord); + } + + return Status; +} + +/** + Deleted an image properties record. The function will also call + RemoveEntryList() on each code segment and the input ImageRecord before + freeing each pool. + + @param[in] ImageRecord The IMAGE_PROPERTIES_RECORD to delete +**/ +VOID +EFIAPI +DeleteImagePropertiesRecord ( + IN IMAGE_PROPERTIES_RECORD *ImageRecord + ) +{ + LIST_ENTRY *CodeSegmentListHead; + IMAGE_PROPERTIES_RECORD_CODE_SECTION *ImageRecordCodeSection; + + if (ImageRecord == NULL) { + return; + } + + CodeSegmentListHead = &ImageRecord->CodeSegmentList; + while (!IsListEmpty (CodeSegmentListHead)) { + ImageRecordCodeSection = CR ( + CodeSegmentListHead->ForwardLink, + IMAGE_PROPERTIES_RECORD_CODE_SECTION, + Link, + IMAGE_PROPERTIES_RECORD_CODE_SECTION_SIGNATURE + ); + RemoveEntryList (&ImageRecordCodeSection->Link); + FreePool (ImageRecordCodeSection); + } + + if (!IsListEmpty (&ImageRecord->Link)) { + RemoveEntryList (&ImageRecord->Link); + } + + FreePool (ImageRecord); +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/MdeModulePkg.dec b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/MdeModulePkg.dec new file mode 100644 index 0000000000000000000000000000000000000000..2fd03476a4646d727a2fc88add63987d8c664255 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/MdeModulePkg.dec @@ -0,0 +1,2254 @@ +## @file MdeModulePkg.dec +# This package provides the modules that conform to UEFI/PI Industry standards. +# It also provides the definitions(including PPIs/PROTOCOLs/GUIDs and library classes) +# and libraries instances, which are used for those modules. +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) Microsoft Corporation.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = MdeModulePkg + PACKAGE_UNI_FILE = MdeModulePkg.uni + PACKAGE_GUID = BA0D78D6-2CAF-414b-BD4D-B6762A894288 + PACKAGE_VERSION = 0.98 + +[Includes] + Include + Test/Mock/Include + +[Includes.Common.Private] + Library/BrotliCustomDecompressLib/brotli/c/include + +[LibraryClasses] + ## @libraryclass Defines a set of methods to reset whole system. + ResetSystemLib|Include/Library/ResetSystemLib.h + + ## @libraryclass Business logic for storing and testing variable policies + VariablePolicyLib|Include/Library/VariablePolicyLib.h + + ## @libraryclass Defines a set of helper functions for resetting the system. + ResetUtilityLib|Include/Library/ResetUtilityLib.h + + ## @libraryclass Provides HII related functions. + HiiLib|Include/Library/HiiLib.h + + ## @libraryclass Defines a set of interfaces on how to process capusle image update. + CapsuleLib|Include/Library/CapsuleLib.h + + ## @libraryclass Provides global variables that are pointers + # to the UEFI HII related protocols. + # + UefiHiiServicesLib|Include/Library/UefiHiiServicesLib.h + + ## @libraryclass Provides a set of interfaces to abstract the policy of security measurement. + # + SecurityManagementLib|Include/Library/SecurityManagementLib.h + + ## @libraryclass OEM status code libary is used to report status code to OEM device. + # + OemHookStatusCodeLib|Include/Library/OemHookStatusCodeLib.h + + ## @libraryclass Debug Agent is used to provide soft debug capability. + # + DebugAgentLib|Include/Library/DebugAgentLib.h + + ## @libraryclass Provide platform specific hooks. + # + PlatformHookLib|Include/Library/PlatformHookLib.h + + ## @libraryclass Provide platform specific hooks for SMM core. + # + SmmCorePlatformHookLib|Include/Library/SmmCorePlatformHookLib.h + + ## @libraryclass Provide capability to maintain the data integrity cross S3 phase. + # + LockBoxLib|Include/Library/LockBoxLib.h + + ## @libraryclass Provide the CPU exception handler. + # + CpuExceptionHandlerLib|Include/Library/CpuExceptionHandlerLib.h + + ## @libraryclass Provides platform specific display interface. + # + CustomizedDisplayLib|Include/Library/CustomizedDisplayLib.h + + ## @libraryclass Provides sorting functions + SortLib|Include/Library/SortLib.h + + ## @libraryclass Provides core boot manager functions + UefiBootManagerLib|Include/Library/UefiBootManagerLib.h + + ## @libraryclass Provides core boot manager functions + PlatformBootManagerLib|Include/Library/PlatformBootManagerLib.h + + ## @libraryclass Provides common interfaces about TPM measurement for other modules. + # + TpmMeasurementLib|Include/Library/TpmMeasurementLib.h + + ## @libraryclass Provides authenticated variable services. + # + AuthVariableLib|Include/Library/AuthVariableLib.h + + ## @libraryclass Provides variable check services and database management. + # + VarCheckLib|Include/Library/VarCheckLib.h + + ## @libraryclass Provides services to get variable error flag and do platform variable cleanup. + # + PlatformVarCleanupLib|Include/Library/PlatformVarCleanupLib.h + + ## @libraryclass Provides services to get do the file explorer. + # + FileExplorerLib|Include/Library/FileExplorerLib.h + + ## @libraryclass Provides interfaces about logo display. + # + BootLogoLib|Include/Library/BootLogoLib.h + + ## @libraryclass Provides interfaces about Ipmi submit generic commond. + # + IpmiLib|Include/Library/IpmiLib.h + + ## @libraryclass Provides interfaces to send/receive IPMI command. + # + IpmiCommandLib|Include/Library/IpmiCommandLib.h + + ## @libraryclass Provides interfaces for platform to return root bridge information to PciHostBridgeDxe driver. + # + PciHostBridgeLib|Include/Library/PciHostBridgeLib.h + + ## @libraryclass Provides services to record memory profile of multilevel caller. + # + MemoryProfileLib|Include/Library/MemoryProfileLib.h + + ## @libraryclass Provides an interface for performing UEFI Graphics Output Protocol Video blt operations. + ## + FrameBufferBltLib|Include/Library/FrameBufferBltLib.h + + ## @libraryclass Provides services to authenticate a UEFI defined FMP Capsule. + # + FmpAuthenticationLib|Include/Library/FmpAuthenticationLib.h + + ## @libraryclass Provides a service to register non-discoverable device + ## + NonDiscoverableDeviceRegistrationLib|Include/Library/NonDiscoverableDeviceRegistrationLib.h + + ## @libraryclass Provides services to convert a BMP graphics image to a GOP BLT buffer + # and to convert a GOP BLT buffer to a BMP graphics image. + # + BmpSupportLib|Include/Library/BmpSupportLib.h + + ## @libraryclass Provides services to display completion progress when + # processing a firmware update that updates the firmware image in a firmware + # device. A platform may provide its own instance of this library class to + # customize how a user is informed of completion progress. + # + DisplayUpdateProgressLib|Include/Library/DisplayUpdateProgressLib.h + + ## @libraryclass This library contains helper functions for marshalling and + # registering new policies with the VariablePolicy infrastructure. + # + VariablePolicyHelperLib|Include/Library/VariablePolicyHelperLib.h + + ## @libraryclass Provides services to access UEFI variable flash information. + # + VariableFlashInfoLib|Include/Library/VariableFlashInfoLib.h + + ## @libraryclass Memory Attribute Table support logic for tracking and reporting + # runtime images + # + ImagePropertiesRecordLib|Include/Library/ImagePropertiesRecordLib.h + + ## @libraryclass Platform SPI Host Controller library which provides low-level + # control over the SPI hardware + # + SpiHcPlatformLib|Include/Library/SpiHcPlatformLib.h + +[Guids] + ## MdeModule package token space guid + # Include/Guid/MdeModulePkgTokenSpace.h + gEfiMdeModulePkgTokenSpaceGuid = { 0xA1AFF049, 0xFDEB, 0x442a, { 0xB3, 0x20, 0x13, 0xAB, 0x4C, 0xB7, 0x2B, 0xBC }} + + ## Hob guid for Pcd DataBase + # Include/Guid/PcdDataBaseHobGuid.h + gPcdDataBaseHobGuid = { 0xEA296D92, 0x0B69, 0x423C, { 0x8C, 0x28, 0x33, 0xB4, 0xE0, 0xA9, 0x12, 0x68 }} + + ## Guid for PCD DataBase signature. + # Include/Guid/PcdDataBaseSignatureGuid.h + gPcdDataBaseSignatureGuid = { 0x3c7d193c, 0x682c, 0x4c14, { 0xa6, 0x8f, 0x55, 0x2d, 0xea, 0x4f, 0x43, 0x7e }} + + ## Guid for EDKII implementation GUIDed opcodes + # Include/Guid/MdeModuleHii.h + gEfiIfrTianoGuid = { 0xf0b1735, 0x87a0, 0x4193, {0xb2, 0x66, 0x53, 0x8c, 0x38, 0xaf, 0x48, 0xce }} + + ## Guid for EDKII implementation extension, used to indaicate there are bit fields in the varstore. + # Include/Guid/MdeModuleHii.h + gEdkiiIfrBitVarstoreGuid = {0x82DDD68B, 0x9163, 0x4187, {0x9B, 0x27, 0x20, 0xA8, 0xFD, 0x60,0xA7, 0x1D}} + + ## Guid for Framework vfr GUIDed opcodes. + # Include/Guid/MdeModuleHii.h + gEfiIfrFrameworkGuid = { 0x31ca5d1a, 0xd511, 0x4931, { 0xb7, 0x82, 0xae, 0x6b, 0x2b, 0x17, 0x8c, 0xd7 }} + + ## Guid to specify the System Non Volatile FV + # Include/Guid/SystemNvDataGuid.h + gEfiSystemNvDataFvGuid = { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + + ## GUID used as the signature of FTW working block header. + # Include/Guid/SystemNvDataGuid.h + gEdkiiWorkingBlockSignatureGuid = { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + + ## GUID used to build FTW last write data hob and install PPI to inform the check for FTW last write data has been done. + # Include/Guid/FaultTolerantWrite.h + gEdkiiFaultTolerantWriteGuid = { 0x1d3e9cb8, 0x43af, 0x490b, { 0x83, 0xa, 0x35, 0x16, 0xaa, 0x53, 0x20, 0x47 }} + + ## Guid specify the device is the console out device. + # Include/Guid/ConsoleOutDevice.h + gEfiConsoleOutDeviceGuid = { 0xD3B36F2C, 0xD551, 0x11D4, { 0x9A, 0x46, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Guid specify the device is the console in device. + # Include/Guid/ConsoleInDevice.h + gEfiConsoleInDeviceGuid = { 0xD3B36F2B, 0xD551, 0x11D4, { 0x9A, 0x46, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Hob and Variable guid specify the platform memory type information. + # Include/Guid/MemoryTypeInformation.h + gEfiMemoryTypeInformationGuid = { 0x4C19049F, 0x4137, 0x4DD3, { 0x9C, 0x10, 0x8B, 0x97, 0xA8, 0x3F, 0xFD, 0xFA }} + + ## Capsule update hob and variable guid + # Include/Guid/CapsuleVendor.h + gEfiCapsuleVendorGuid = { 0x711C703F, 0xC285, 0x4B10, { 0xA3, 0xB0, 0x36, 0xEC, 0xBD, 0x3C, 0x8B, 0xE2 }} + + ## Guid specifiy the device is the StdErr device. + # Include/Guid/StandardErrorDevice.h + gEfiStandardErrorDeviceGuid = { 0xD3B36F2D, 0xD551, 0x11D4, { 0x9A, 0x46, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Guid acted as variable store header's signature and to specify the variable list entries put in the EFI system table. + # Include/Guid/VariableFormat.h + gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + + ## Guid acted as the authenticated variable store header's signature, and to specify the variable list entries put in the EFI system table. + # Include/Guid/AuthenticatedVariableFormat.h + gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + + # Include/Guid/VariableIndexTable.h + gEfiVariableIndexTableGuid = { 0x8cfdb8c8, 0xd6b2, 0x40f3, { 0x8e, 0x97, 0x02, 0x30, 0x7c, 0xc9, 0x8b, 0x7c }} + + ## Guid is defined for SMM variable module to notify SMM variable wrapper module when variable write service was ready. + # Include/Guid/SmmVariableCommon.h + gSmmVariableWriteGuid = { 0x93ba1826, 0xdffb, 0x45dd, { 0x82, 0xa7, 0xe7, 0xdc, 0xaa, 0x3b, 0xbd, 0xf3 }} + + ## Guid of the variable flash information HOB. + # Include/Guid/VariableFlashInfo.h + gVariableFlashInfoHobGuid = { 0x5d11c653, 0x8154, 0x4ac3, { 0xa8, 0xc2, 0xfb, 0xa2, 0x89, 0x20, 0xfc, 0x90 }} + + ## Performance protocol guid that also acts as the performance HOB guid and performance variable GUID + # Include/Guid/Performance.h + gPerformanceProtocolGuid = { 0x76B6BDFA, 0x2ACD, 0x4462, { 0x9E, 0x3F, 0xCB, 0x58, 0xC9, 0x69, 0xD9, 0x37 } } + gSmmPerformanceProtocolGuid = { 0xf866226a, 0xeaa5, 0x4f5a, { 0xa9, 0xa, 0x6c, 0xfb, 0xa5, 0x7c, 0x58, 0x8e } } + gPerformanceExProtocolGuid = { 0x1ea81bec, 0xf01a, 0x4d98, { 0xa2, 0x1, 0x4a, 0x61, 0xce, 0x2f, 0xc0, 0x22 } } + gSmmPerformanceExProtocolGuid = { 0x931fc048, 0xc71d, 0x4455, { 0x89, 0x30, 0x47, 0x6, 0x30, 0xe3, 0xe, 0xe5 } } + # Include/Guid/PerformanceMeasurement.h + gEdkiiPerformanceMeasurementProtocolGuid = { 0xc85d06be, 0x5f75, 0x48ce, { 0xa8, 0x0f, 0x12, 0x36, 0xba, 0x3b, 0x87, 0xb1 } } + gEdkiiSmmPerformanceMeasurementProtocolGuid = { 0xd56b6d73, 0x1a7b, 0x4015, { 0x9b, 0xb4, 0x7b, 0x07, 0x17, 0x29, 0xed, 0x24 } } + + ## Guid is defined for CRC32 encapsulation scheme. + # Include/Guid/Crc32GuidedSectionExtraction.h + gEfiCrc32GuidedSectionExtractionGuid = { 0xFC1BCDB0, 0x7D31, 0x49aa, {0x93, 0x6A, 0xA4, 0x60, 0x0D, 0x9D, 0xD0, 0x83 } } + + ## Include/Guid/StatusCodeCallbackGuid.h + gStatusCodeCallbackGuid = {0xe701458c, 0x4900, 0x4ca5, {0xb7, 0x72, 0x3d, 0x37, 0x94, 0x9f, 0x79, 0x27}} + + ## GUID identifies status code records HOB that originate from the PEI status code + # Include/Guid/MemoryStatusCodeRecord.h + gMemoryStatusCodeRecordGuid = { 0x060CC026, 0x4C0D, 0x4DDA, { 0x8F, 0x41, 0x59, 0x5F, 0xEF, 0x00, 0xA5, 0x02 }} + + ## GUID used to pass DEBUG() macro information through the Status Code Protocol and Status Code PPI + # Include/Guid/StatusCodeDataTypeDebug.h + gEfiStatusCodeDataTypeDebugGuid = { 0x9A4E9246, 0xD553, 0x11D5, { 0x87, 0xE2, 0x00, 0x06, 0x29, 0x45, 0xC3, 0xB9 }} + + ## A configuration Table Guid for Load module at fixed address + # Include/Guid/LoadModuleAtFixedAddress.h + gLoadFixedAddressConfigurationTableGuid = { 0x2CA88B53,0xD296,0x4080, { 0xA4,0xA5,0xCA,0xD9,0xBA,0xE2,0x4B,0x9 } } + + ## GUID used to store the global debug mask value into an EFI Variable + # Include/Guid/DebugMask.h + gEfiGenericVariableGuid = { 0x59d1c24f, 0x50f1, 0x401a, {0xb1, 0x01, 0xf3, 0x3e, 0x0d, 0xae, 0xd4, 0x43} } + + ## Event for the DXE Core to signal idle events + # Include/Guid/EventIdle.h + gIdleLoopEventGuid = { 0x3c8d294c, 0x5fc3, 0x4451, { 0xbb, 0x31, 0xc4, 0xc0, 0x32, 0x29, 0x5e, 0x6c } } + + ## Include/Guid/RecoveryDevice.h + gRecoveryOnFatUsbDiskGuid = { 0x0FFBCE19, 0x324C, 0x4690, { 0xA0, 0x09, 0x98, 0xC6, 0xAE, 0x2E, 0xB1, 0x86 }} + + ## Include/Guid/RecoveryDevice.h + gRecoveryOnFatIdeDiskGuid = { 0xB38573B6, 0x6200, 0x4AC5, { 0xB5, 0x1D, 0x82, 0xE6, 0x59, 0x38, 0xD7, 0x83 }} + + ## Include/Guid/RecoveryDevice.h + gRecoveryOnFatFloppyDiskGuid = { 0x2E3D2E75, 0x9B2E, 0x412D, { 0xB4, 0xB1, 0x70, 0x41, 0x6B, 0x87, 0x00, 0xFF }} + + ## Include/Guid/RecoveryDevice.h + gRecoveryOnDataCdGuid = { 0x5CAC0099, 0x0DC9, 0x48E5, { 0x80, 0x68, 0xBB, 0x95, 0xF5, 0x40, 0x0A, 0x9F }} + + ## Include/Guid/RecoveryDevice.h + gRecoveryOnFatNvmeDiskGuid = { 0xC770A27F, 0x956A, 0x497A, { 0x85, 0x48, 0xE0, 0x61, 0x97, 0x58, 0x8B, 0xF6 }} + + ## Include/Guid/SmmLockBox.h + gEfiSmmLockBoxCommunicationGuid = { 0x2a3cfebd, 0x27e8, 0x4d0a, { 0x8b, 0x79, 0xd6, 0x88, 0xc2, 0xa3, 0xe1, 0xc0 }} + + ## Include/Guid/AcpiS3Context.h + gEfiAcpiVariableGuid = { 0xAF9FFD67, 0xEC10, 0x488A, { 0x9D, 0xFC, 0x6C, 0xBF, 0x5E, 0xE2, 0x2C, 0x2E }} + + ## Include/Guid/AcpiS3Context.h + gEfiAcpiS3ContextGuid = { 0xef98d3a, 0x3e33, 0x497a, { 0xa4, 0x1, 0x77, 0xbe, 0x3e, 0xb7, 0x4f, 0x38 }} + + ## Include/Guid/BootScriptExecutorVariable.h + gEfiBootScriptExecutorVariableGuid = { 0x3079818c, 0x46d4, 0x4a73, { 0xae, 0xf3, 0xe3, 0xe4, 0x6c, 0xf1, 0xee, 0xdb }} + gEfiBootScriptExecutorContextGuid = { 0x79cb58c4, 0xac51, 0x442f, { 0xaf, 0xd7, 0x98, 0xe4, 0x7d, 0x2e, 0x99, 0x8 }} + + ## Include/Guid/UsbKeyBoardLayout.h + gUsbKeyboardLayoutPackageGuid = { 0xc0f3b43, 0x44de, 0x4907, { 0xb4, 0x78, 0x22, 0x5f, 0x6f, 0x62, 0x89, 0xdc }} + gUsbKeyboardLayoutKeyGuid = { 0x3a4d7a7c, 0x18a, 0x4b42, { 0x81, 0xb3, 0xdc, 0x10, 0xe3, 0xb5, 0x91, 0xbd }} + + ## Include/Guid/HiiResourceSampleHii.h + gHiiResourceSamleFormSetGuid = { 0x4f4ef7f0, 0xaa29, 0x4ce9, { 0xba, 0x41, 0x64, 0x3e, 0x1, 0x23, 0xa9, 0x9f }} + + ## Include/Guid/DriverSampleHii.h + gDriverSampleFormSetGuid = { 0xA04A27f4, 0xDF00, 0x4D42, { 0xB5, 0x52, 0x39, 0x51, 0x13, 0x02, 0x11, 0x3D }} + gDriverSampleInventoryGuid = { 0xb3f56470, 0x6141, 0x4621, { 0x8f, 0x19, 0x70, 0x4e, 0x57, 0x7a, 0xa9, 0xe8 }} + gEfiIfrRefreshIdOpGuid = { 0xF5E655D9, 0x02A6, 0x46f2, { 0x9E, 0x76, 0xB8, 0xBE, 0x8E, 0x60, 0xAB, 0x22 }} + + ## Include/Guid/PlatDriOverrideHii.h + gPlatformOverridesManagerGuid = { 0x8614567d, 0x35be, 0x4415, { 0x8d, 0x88, 0xbd, 0x7d, 0xc, 0x9c, 0x70, 0xc0 }} + + ## Include/Guid/ZeroGuid.h + gZeroGuid = { 0x0, 0x0, 0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}} + + ## Include/Guid/MtcVendor.h + gMtcVendorGuid = { 0xeb704011, 0x1402, 0x11d3, { 0x8e, 0x77, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b }} + + ## Guid for Firmware Performance Data Table (FPDT) implementation. + # Include/Guid/FirmwarePerformance.h + gEfiFirmwarePerformanceGuid = { 0xc095791a, 0x3001, 0x47b2, { 0x80, 0xc9, 0xea, 0xc7, 0x31, 0x9f, 0x2f, 0xa4 }} + gFirmwarePerformanceS3PointerGuid = { 0xdc65adc, 0xa973, 0x4130, { 0x8d, 0xf0, 0x2a, 0xdb, 0xeb, 0x9e, 0x4a, 0x31 }} + + ## Include/Guid/ExitBootServiceFailed.h + gEventExitBootServicesFailedGuid = { 0x4f6c5507, 0x232f, 0x4787, { 0xb9, 0x5e, 0x72, 0xf8, 0x62, 0x49, 0xc, 0xb1 } } + + ## Include/Guid/ConnectConInEvent.h + gConnectConInEventGuid = { 0xdb4e8151, 0x57ed, 0x4bed, { 0x88, 0x33, 0x67, 0x51, 0xb5, 0xd1, 0xa8, 0xd7 }} + + ## Include/Guid/StatusCodeDataTypeVariable.h + gEdkiiStatusCodeDataTypeVariableGuid = { 0xf6ee6dbb, 0xd67f, 0x4ea0, { 0x8b, 0x96, 0x6a, 0x71, 0xb1, 0x9d, 0x84, 0xad }} + + ## Include/Guid/MemoryProfile.h + gEdkiiMemoryProfileGuid = { 0x821c9a09, 0x541a, 0x40f6, { 0x9f, 0x43, 0xa, 0xd1, 0x93, 0xa1, 0x2c, 0xfe }} + gEdkiiSmmMemoryProfileGuid = { 0xe22bbcca, 0x516a, 0x46a8, { 0x80, 0xe2, 0x67, 0x45, 0xe8, 0x36, 0x93, 0xbd }} + + ## Include/Protocol/VarErrorFlag.h + gEdkiiVarErrorFlagGuid = { 0x4b37fe8, 0xf6ae, 0x480b, { 0xbd, 0xd5, 0x37, 0xd9, 0x8c, 0x5e, 0x89, 0xaa } } + + ## GUID indicates the BROTLI custom compress/decompress algorithm. + gBrotliCustomDecompressGuid = { 0x3D532050, 0x5CDA, 0x4FD0, { 0x87, 0x9E, 0x0F, 0x7F, 0x63, 0x0D, 0x5A, 0xFB }} + + ## GUID indicates the LZMA custom compress/decompress algorithm. + # Include/Guid/LzmaDecompress.h + gLzmaCustomDecompressGuid = { 0xEE4E5898, 0x3914, 0x4259, { 0x9D, 0x6E, 0xDC, 0x7B, 0xD7, 0x94, 0x03, 0xCF }} + gLzmaF86CustomDecompressGuid = { 0xD42AE6BD, 0x1352, 0x4bfb, { 0x90, 0x9A, 0xCA, 0x72, 0xA6, 0xEA, 0xE8, 0x89 }} + + ## Include/Guid/TtyTerm.h + gEfiTtyTermGuid = { 0x7d916d80, 0x5bb1, 0x458c, {0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94 }} + gEdkiiLinuxTermGuid = { 0xe4364a7f, 0xf825, 0x430e, {0x9d, 0x3a, 0x9c, 0x9b, 0xe6, 0x81, 0x7c, 0xa5 }} + gEdkiiXtermR6Guid = { 0xfbfca56b, 0xbb36, 0x4b78, {0xaa, 0xab, 0xbe, 0x1b, 0x97, 0xec, 0x7c, 0xcb }} + gEdkiiVT400Guid = { 0x8e46dddd, 0x3d49, 0x4a9d, {0xb8, 0x75, 0x3c, 0x08, 0x6f, 0x6a, 0xa2, 0xbd }} + gEdkiiSCOTermGuid = { 0xfc7dd6e0, 0x813c, 0x434d, {0xb4, 0xda, 0x3b, 0xd6, 0x49, 0xe9, 0xe1, 0x5a }} + + ## Include/Guid/HiiBootMaintenanceFormset.h + gEfiIfrBootMaintenanceGuid = { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a, 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 }} + + gEfiIfrFrontPageGuid = { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a, 0xa3, 0x0f, 0xdc, 0x4b, 0x44, 0x1e } } + + ## Include/Guid/RamDiskHii.h + gRamDiskFormSetGuid = { 0x2a46715f, 0x3581, 0x4a55, { 0x8e, 0x73, 0x2b, 0x76, 0x9a, 0xaa, 0x30, 0xc5 }} + + ## Include/Guid/PiSmmCommunicationRegionTable.h + gEdkiiPiSmmCommunicationRegionTableGuid = { 0x4e28ca50, 0xd582, 0x44ac, {0xa1, 0x1f, 0xe3, 0xd5, 0x65, 0x26, 0xdb, 0x34}} + + ## Include/Guid/PiSmmMemoryAttributesTable.h + gEdkiiPiSmmMemoryAttributesTableGuid = { 0x6b9fd3f7, 0x16df, 0x45e8, {0xbd, 0x39, 0xb9, 0x4a, 0x66, 0x54, 0x1a, 0x5d}} + + ## Include/Guid/SmiHandlerProfile.h + gSmiHandlerProfileGuid = {0x49174342, 0x7108, 0x409b, {0x8b, 0xbe, 0x65, 0xfd, 0xa8, 0x53, 0x89, 0xf5}} + + ## Include/Guid/NonDiscoverableDevice.h + gEdkiiNonDiscoverableAhciDeviceGuid = { 0xC7D35798, 0xE4D2, 0x4A93, {0xB1, 0x45, 0x54, 0x88, 0x9F, 0x02, 0x58, 0x4B } } + gEdkiiNonDiscoverableAmbaDeviceGuid = { 0x94440339, 0xCC93, 0x4506, {0xB4, 0xC6, 0xEE, 0x8D, 0x0F, 0x4C, 0xA1, 0x91 } } + gEdkiiNonDiscoverableEhciDeviceGuid = { 0xEAEE5615, 0x0CFD, 0x45FC, {0x87, 0x69, 0xA0, 0xD8, 0x56, 0x95, 0xAF, 0x85 } } + gEdkiiNonDiscoverableNvmeDeviceGuid = { 0xC5F25542, 0x2A79, 0x4A26, {0x81, 0xBB, 0x4E, 0xA6, 0x32, 0x33, 0xB3, 0x09 } } + gEdkiiNonDiscoverableOhciDeviceGuid = { 0xB20005B0, 0xBB2D, 0x496F, {0x86, 0x9C, 0x23, 0x0B, 0x44, 0x79, 0xE7, 0xD1 } } + gEdkiiNonDiscoverableSdhciDeviceGuid = { 0x1DD1D619, 0xF9B8, 0x463E, {0x86, 0x81, 0xD1, 0xDC, 0x7C, 0x07, 0xB7, 0x2C } } + gEdkiiNonDiscoverableUfsDeviceGuid = { 0x2EA77912, 0x80A8, 0x4947, {0xBE, 0x69, 0xCD, 0xD0, 0x0A, 0xFB, 0xE5, 0x56 } } + gEdkiiNonDiscoverableUhciDeviceGuid = { 0xA8CDA0A2, 0x4F37, 0x4A1B, {0x8E, 0x10, 0x8E, 0xF3, 0xCC, 0x3B, 0xF3, 0xA8 } } + gEdkiiNonDiscoverableXhciDeviceGuid = { 0xB1BE0BC5, 0x6C28, 0x442D, {0xAA, 0x37, 0x15, 0x1B, 0x42, 0x57, 0xBD, 0x78 } } + + ## Include/Guid/PlatformHasAcpi.h + gEdkiiPlatformHasAcpiGuid = { 0xf0966b41, 0xc23f, 0x41b9, { 0x96, 0x04, 0x0f, 0xf7, 0xe1, 0x11, 0x96, 0x5a } } + + ## Include/Guid/ExtendedFirmwarePerformance.h + gEdkiiFpdtExtendedFirmwarePerformanceGuid = { 0x3b387bfd, 0x7abc, 0x4cf2, { 0xa0, 0xca, 0xb6, 0xa1, 0x6c, 0x1b, 0x1b, 0x25 } } + + ## Include/Guid/EndofS3Resume.h + gEdkiiEndOfS3ResumeGuid = { 0x96f5296d, 0x05f7, 0x4f3c, {0x84, 0x67, 0xe4, 0x56, 0x89, 0x0e, 0x0c, 0xb5 } } + + ## Used (similar to Variable Services) to communicate policies to the enforcement engine. + # {DA1B0D11-D1A7-46C4-9DC9-F3714875C6EB} + gVarCheckPolicyLibMmiHandlerGuid = { 0xda1b0d11, 0xd1a7, 0x46c4, { 0x9d, 0xc9, 0xf3, 0x71, 0x48, 0x75, 0xc6, 0xeb }} + + ## Include/Guid/S3SmmInitDone.h + gEdkiiS3SmmInitDoneGuid = { 0x8f9d4825, 0x797d, 0x48fc, { 0x84, 0x71, 0x84, 0x50, 0x25, 0x79, 0x2e, 0xf6 } } + + ## Include/Guid/S3StorageDeviceInitList.h + gS3StorageDeviceInitListGuid = { 0x310e9b8c, 0xcf90, 0x421e, { 0x8e, 0x9b, 0x9e, 0xef, 0xb6, 0x17, 0xc8, 0xef } } + + ## Include/Guid/SerialPortLibVendor.h + gEdkiiSerialPortLibVendorGuid = { 0xD3987D4B, 0x971A, 0x435F, { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } } + + ## GUID indicates the capsule is to store Capsule On Disk file names. + gEdkiiCapsuleOnDiskNameGuid = { 0x98c80a4f, 0xe16b, 0x4d11, { 0x93, 0x9a, 0xab, 0xe5, 0x61, 0x26, 0x3, 0x30 } } + + ## Include/Guid/MigratedFvInfo.h + gEdkiiMigrationInfoGuid = { 0xb4b140a5, 0x72f6, 0x4c21, { 0x93, 0xe4, 0xac, 0xc4, 0xec, 0xcb, 0x23, 0x23 } } + gEdkiiMigratedFvInfoGuid = { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4, 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } } + + ## Include/Guid/RngAlgorithm.h + gEdkiiRngAlgorithmUnSafe = { 0x869f728c, 0x409d, 0x4ab4, {0xac, 0x03, 0x71, 0xd3, 0x09, 0xc1, 0xb3, 0xf4 }} + + # + # GUID defined in UniversalPayload + # + ## Include/UniversalPayload/PciRootBridges.h + gUniversalPayloadPciRootBridgeInfoGuid = { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }} + + ## Include/UniversalPayload/SmbiosTable.h + gUniversalPayloadSmbios3TableGuid = { 0x92b7896c, 0x3362, 0x46ce, { 0x99, 0xb3, 0x4f, 0x5e, 0x3c, 0x34, 0xeb, 0x42 } } + + ## Include/UniversalPayload/SmbiosTable.h + gUniversalPayloadSmbiosTableGuid = { 0x590a0d26, 0x06e5, 0x4d20, { 0x8a, 0x82, 0x59, 0xea, 0x1b, 0x34, 0x98, 0x2d } } + + ## Include/UniversalPayload/AcpiTable.h + gUniversalPayloadAcpiTableGuid = { 0x9f9a9506, 0x5597, 0x4515, { 0xba, 0xb6, 0x8b, 0xcd, 0xe7, 0x84, 0xba, 0x87 } } + + ## Include/UniversalPayload/ExtraData.h + gUniversalPayloadExtraDataGuid = {0x15a5baf6, 0x1c91, 0x467d, {0x9d, 0xfb, 0x31, 0x9d, 0x17, 0x8d, 0x4b, 0xb4}} + + ## Include/UniversalPayload/SerialPortInfo.h + gUniversalPayloadSerialPortInfoGuid = { 0xaa7e190d, 0xbe21, 0x4409, { 0x8e, 0x67, 0xa2, 0xcd, 0xf, 0x61, 0xe1, 0x70 } } + + ## Include/Guid/TraceHubDebugInfoHob.h + gTraceHubDebugInfoHobGuid = { 0xf88c9c23, 0x646c, 0x4f6c, { 0x8e, 0x3d, 0x36, 0xa9, 0x43, 0xc1, 0x08, 0x35 } } + + ## GUID used for Boot Discovery Policy FormSet guid and related variables. + gBootDiscoveryPolicyMgrFormsetGuid = { 0x5b6f7107, 0xbb3c, 0x4660, { 0x92, 0xcd, 0x54, 0x26, 0x90, 0x28, 0x0b, 0xbd } } + +[Ppis] + ## Include/Ppi/FirmwareVolumeShadowPpi.h + gEdkiiPeiFirmwareVolumeShadowPpiGuid = { 0x7dfe756c, 0xed8d, 0x4d77, {0x9e, 0xc4, 0x39, 0x9a, 0x8a, 0x81, 0x51, 0x16 } } + + ## Include/Ppi/AtaController.h + gPeiAtaControllerPpiGuid = { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }} + + ## Include/Ppi/UsbHostController.h + gPeiUsbHostControllerPpiGuid = { 0x652B38A9, 0x77F4, 0x453F, { 0x89, 0xD5, 0xE7, 0xBD, 0xC3, 0x52, 0xFC, 0x53 }} + + ## Include/Ppi/Usb2HostController.h + gPeiUsb2HostControllerPpiGuid = { 0xfedd6305, 0xe2d7, 0x4ed5, { 0x9f, 0xaa, 0xda, 0x8, 0xe, 0x33, 0x6c, 0x22 }} + + ## Include/Ppi/UsbController.h + gPeiUsbControllerPpiGuid = { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }} + + ## Include/Ppi/UsbIo.h + gPeiUsbIoPpiGuid = { 0x7C29785C, 0x66B9, 0x49FC, { 0xB7, 0x97, 0x1C, 0xA5, 0x55, 0x0E, 0xF2, 0x83 }} + + ## Include/Ppi/SecPerformance.h + gPeiSecPerformancePpiGuid = { 0x0ecc666b, 0x4662, 0x47f9, { 0x9d, 0xd5, 0xd0, 0x96, 0xff, 0x7d, 0xa4, 0x9e }} + + ## Include/Ppi/SmmCommunication.h + gEfiPeiSmmCommunicationPpiGuid = { 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf }} + + ## Include/Ppi/SmmAccess.h + gPeiSmmAccessPpiGuid = { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }} + + ## Include/Ppi/SmmControl.h + gPeiSmmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} + + ## Include/Ppi/PostBootScriptTable.h + gPeiPostScriptTablePpiGuid = { 0x88c9d306, 0x900, 0x4eb5, { 0x82, 0x60, 0x3e, 0x2d, 0xbe, 0xda, 0x1f, 0x89}} + + ## Include/Ppi/SerialPortPei.h + gPeiSerialPortPpiGuid = { 0x490e9d85, 0x8aef, 0x4193, { 0x8e, 0x56, 0xf7, 0x34, 0xa9, 0xff, 0xac, 0x8b}} + + ## Include/Ppi/UfsHostController.h + gEdkiiPeiUfsHostControllerPpiGuid = { 0xdc54b283, 0x1a77, 0x4cd6, { 0x83, 0xbb, 0xfd, 0xda, 0x46, 0x9a, 0x2e, 0xc6 }} + + ## Include/Ppi/IpmiPpi.h + gPeiIpmiPpiGuid = { 0xa9731431, 0xd968, 0x4277, { 0xb7, 0x52, 0xa3, 0xa9, 0xa6, 0xae, 0x18, 0x98 }} + + ## Include/Ppi/SdMmcHostController.h + gEdkiiPeiSdMmcHostControllerPpiGuid = { 0xb30dfeed, 0x947f, 0x4396, { 0xb1, 0x5a, 0xdf, 0xbd, 0xb9, 0x16, 0xdc, 0x24 }} + + ## Include/Ppi/IoMmu.h + gEdkiiIoMmuPpiGuid = { 0x70b0af26, 0xf847, 0x4bb6, { 0xaa, 0xb9, 0xcd, 0xe8, 0x4f, 0xc6, 0x14, 0x31 } } + + ## Include/Ppi/PlatformSpecificResetFilter.h + gEdkiiPlatformSpecificResetFilterPpiGuid = { 0x8c9f4de3, 0x7b90, 0x47ef, { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } } + + ## Include/Ppi/PlatformSpecificResetNotification.h + gEdkiiPlatformSpecificResetNotificationPpiGuid = { 0xe09f355d, 0xdae8, 0x4910, { 0xb1, 0x4a, 0x92, 0x78, 0xf, 0xdc, 0xf7, 0xcb } } + + ## Include/Ppi/PlatformSpecificResetHandler.h + gEdkiiPlatformSpecificResetHandlerPpiGuid = { 0x75cf14ae, 0x3441, 0x49dc, { 0xaa, 0x10, 0xbb, 0x35, 0xa7, 0xba, 0x8b, 0xab } } + + ## Include/Ppi/NvmExpressHostController.h + gEdkiiPeiNvmExpressHostControllerPpiGuid = { 0xcae3aa63, 0x676f, 0x4da3, { 0xbd, 0x50, 0x6c, 0xc5, 0xed, 0xde, 0x9a, 0xad } } + + ## Include/Ppi/AtaAhciController.h + gEdkiiPeiAtaAhciHostControllerPpiGuid = { 0x61dd33ea, 0x421f, 0x4cc0, { 0x89, 0x29, 0xff, 0xee, 0xa9, 0xa1, 0xa2, 0x61 } } + + ## Include/Ppi/StorageSecurityCommand.h + gEdkiiPeiStorageSecurityCommandPpiGuid = { 0x35de0b4e, 0x30fb, 0x46c3, { 0xbd, 0x84, 0x1f, 0xdb, 0xa1, 0x58, 0xbb, 0x56 } } + + ## Include/Ppi/AtaPassThru.h + gEdkiiPeiAtaPassThruPpiGuid = { 0xa16473fd, 0xd474, 0x4c89, { 0xae, 0xc7, 0x90, 0xb8, 0x3c, 0x73, 0x86, 0x9 } } + + ## Include/Ppi/Debug.h + gEdkiiDebugPpiGuid = { 0x999e699c, 0xb013, 0x475e, { 0xb1, 0x7b, 0xf3, 0xa8, 0xae, 0x5c, 0x48, 0x75 } } + + ## Include/Ppi/NvmExpressPassThru.h + gEdkiiPeiNvmExpressPassThruPpiGuid = { 0x6af31b2c, 0x3be, 0x46c1, { 0xb1, 0x2d, 0xea, 0x4a, 0x36, 0xdf, 0xa7, 0x4c } } + + ## Include/Ppi/PciDevice.h + gEdkiiPeiPciDevicePpiGuid = { 0x1597ab4f, 0xd542, 0x4efe, { 0x9a, 0xf7, 0xb2, 0x44, 0xec, 0x54, 0x4c, 0x0b } } + + ## Include/Ppi/CapsuleOnDisk.h + gEdkiiPeiCapsuleOnDiskPpiGuid = { 0x71a9ea61, 0x5a35, 0x4a5d, { 0xac, 0xef, 0x9c, 0xf8, 0x6d, 0x6d, 0x67, 0xe0 } } + gEdkiiPeiBootInCapsuleOnDiskModePpiGuid = { 0xb08a11e4, 0xe2b7, 0x4b75, { 0xb5, 0x15, 0xaf, 0x61, 0x6, 0x68, 0xbf, 0xd1 } } + + ## Include/Ppi/MemoryAttribute.h + gEdkiiMemoryAttributePpiGuid = { 0x1be840de, 0x2d92, 0x41ec, { 0xb6, 0xd3, 0x19, 0x64, 0x13, 0x50, 0x51, 0xfb } } + +[Protocols] + ## Load File protocol provides capability to load and unload EFI image into memory and execute it. + # Include/Protocol/LoadPe32Image.h + # This protocol is deprecated. Native EDKII module should NOT use this protocol to load/unload image. + # If developer need implement such functionality, they should use BasePeCoffLib. + gEfiLoadPeImageProtocolGuid = { 0x5CB5C776, 0x60D5, 0x45EE, { 0x88, 0x3C, 0x45, 0x27, 0x08, 0xCD, 0x74, 0x3F }} + + ## Print protocols define basic print functions to print the format unicode and ascii string. + # Include/Protocol/Print2.h + gEfiPrint2ProtocolGuid = { 0xf05976ef, 0x83f1, 0x4f3d, { 0x86, 0x19, 0xf7, 0x59, 0x5d, 0x41, 0xe5, 0x38 } } + gEfiPrint2SProtocolGuid = { 0xcc252d2, 0xc106, 0x4661, { 0xb5, 0xbd, 0x31, 0x47, 0xa4, 0xf8, 0x1f, 0x92 } } + + ## This protocol defines the generic memory test interfaces in Dxe phase. + # Include/Protocol/GenericMemoryTest.h + gEfiGenericMemTestProtocolGuid = { 0x309DE7F1, 0x7F5E, 0x4ACE, { 0xB4, 0x9C, 0x53, 0x1B, 0xE5, 0xAA, 0x95, 0xEF }} + + ## This protocol defines the Debugger Configuration interface. + # Include/Protocol/DebuggerConfiguration.h + gEfiDebuggerConfigurationProtocolGuid = { 0x577d959c, 0xe967, 0x4546, { 0x86, 0x20, 0xc7, 0x78, 0xfa, 0xe5, 0xda, 0x05 }} + + ## Fault Tolerant Write protocol provides boot-time service to do fault tolerant write capability for block devices. + # Include/Protocol/FaultTolerantWrite.h + gEfiFaultTolerantWriteProtocolGuid = { 0x3EBD9E82, 0x2C78, 0x4DE6, { 0x97, 0x86, 0x8D, 0x4B, 0xFC, 0xB7, 0xC8, 0x81 }} + + ## This protocol provides boot-time service to do fault tolerant write capability for block devices in SMM environment. + # Include/Protocol/SmmFaultTolerantWrite.h + gEfiSmmFaultTolerantWriteProtocolGuid = { 0x3868fc3b, 0x7e45, 0x43a7, { 0x90, 0x6c, 0x4b, 0xa4, 0x7d, 0xe1, 0x75, 0x4d }} + + ## This protocol is used to abstract the swap operation of boot block and backup block of boot FV. + # Include/Protocol/SwapAddressRange.h + gEfiSwapAddressRangeProtocolGuid = { 0x1259F60D, 0xB754, 0x468E, { 0xA7, 0x89, 0x4D, 0xB8, 0x5D, 0x55, 0xE8, 0x7E }} + + ## This protocol is used to abstract the swap operation of boot block and backup block of boot FV in SMM environment. + # Include/Protocol/SmmSwapAddressRange.h + gEfiSmmSwapAddressRangeProtocolGuid = { 0x67c4f112, 0x3385, 0x4e55, { 0x9c, 0x5b, 0xc0, 0x5b, 0x71, 0x7c, 0x42, 0x28 }} + + ## This protocol is intended for use as a means to store data in the EFI SMM environment. + # Include/Protocol/SmmVariableProtocol.h + gEfiSmmVariableProtocolGuid = { 0xed32d533, 0x99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 }} + + ## This protocol is intended for use as a means to mark a variable read-only after the event EFI_END_OF_DXE_EVENT_GUID is signaled. + # Include/Protocol/VariableLock.h + gEdkiiVariableLockProtocolGuid = { 0xcd3d0a05, 0x9e24, 0x437c, { 0xa8, 0x91, 0x1e, 0xe0, 0x53, 0xdb, 0x76, 0x38 }} + + ## Include/Protocol/VarCheck.h + gEdkiiVarCheckProtocolGuid = { 0xaf23b340, 0x97b4, 0x4685, { 0x8d, 0x4f, 0xa3, 0xf2, 0x81, 0x69, 0xb2, 0x1d } } + + ## Include/Protocol/SmmVarCheck.h + gEdkiiSmmVarCheckProtocolGuid = { 0xb0d8f3c1, 0xb7de, 0x4c11, { 0xbc, 0x89, 0x2f, 0xb5, 0x62, 0xc8, 0xc4, 0x11 } } + + ## This protocol is similar with DXE FVB protocol and used in the UEFI SMM evvironment. + # Include/Protocol/SmmFirmwareVolumeBlock.h + gEfiSmmFirmwareVolumeBlockProtocolGuid = { 0xd326d041, 0xbd31, 0x4c01, { 0xb5, 0xa8, 0x62, 0x8b, 0xe8, 0x7f, 0x6, 0x53 }} + + ## This protocol allows the error level mask for DEBUG() macros to be adjusted for DXE Phase modules + # Include/Guid/DebugMask.h + gEfiDebugMaskProtocolGuid = { 0x4c8a2451, 0xc207, 0x405b, {0x96, 0x94, 0x99, 0xea, 0x13, 0x25, 0x13, 0x41} } + + ## Include/Protocol/LockBox.h + gEfiLockBoxProtocolGuid = { 0xbd445d79, 0xb7ad, 0x4f04, { 0x9a, 0xd8, 0x29, 0xbd, 0x20, 0x40, 0xeb, 0x3c }} + + ## Include/Protocol/FormBrowserEx.h + gEdkiiFormBrowserExProtocolGuid = { 0x1f73b18d, 0x4630, 0x43c1, { 0xa1, 0xde, 0x6f, 0x80, 0x85, 0x5d, 0x7d, 0xa4 } } + + ## Include/Protocol/EbcVmTest.h + gEfiEbcVmTestProtocolGuid = { 0xAAEACCFD, 0xF27B, 0x4C17, { 0xB6, 0x10, 0x75, 0xCA, 0x1F, 0x2D, 0xFB, 0x52 } } + + ## Include/Protocol/EbcSimpleDebugger.h + gEfiEbcSimpleDebuggerProtocolGuid = { 0x2a72d11e, 0x7376, 0x40f6, { 0x9c, 0x68, 0x23, 0xfa, 0x2f, 0xe3, 0x63, 0xf1 } } + + ## Include/Protocol/BootLogo.h + gEfiBootLogoProtocolGuid = { 0xcdea2bd3, 0xfc25, 0x4c1c, { 0xb9, 0x7c, 0xb3, 0x11, 0x86, 0x6, 0x49, 0x90 } } + + # Include/Protocol/BootLogo2.h + gEdkiiBootLogo2ProtocolGuid = { 0x4b5dc1df, 0x1eaa, 0x48b2, { 0xa7, 0xe9, 0xea, 0xc4, 0x89, 0xa0, 0xb, 0x5c } } + + ## Include/Protocol/DisplayProtocol.h + gEdkiiFormDisplayEngineProtocolGuid = { 0x9bbe29e9, 0xfda1, 0x41ec, { 0xad, 0x52, 0x45, 0x22, 0x13, 0x74, 0x2d, 0x2e } } + + ## Include/Protocol/FormBrowserEx2.h + gEdkiiFormBrowserEx2ProtocolGuid = { 0xa770c357, 0xb693, 0x4e6d, { 0xa6, 0xcf, 0xd2, 0x1c, 0x72, 0x8e, 0x55, 0xb } } + + ## Include/Protocol/UfsHostController.h + gEdkiiUfsHostControllerProtocolGuid = { 0xebc01af5, 0x7a9, 0x489e, { 0xb7, 0xce, 0xdc, 0x8, 0x9e, 0x45, 0x9b, 0x2f } } + + ## Include/Protocol/UfsHostControllerPlatform.h + gEdkiiUfsHcPlatformProtocolGuid = { 0x3d18ba13, 0xd9b1, 0x4dd4, {0xb9, 0x16, 0xd3, 0x07, 0x96, 0x53, 0x9e, 0xd8}} + + ## Include/Protocol/EsrtManagement.h + gEsrtManagementProtocolGuid = { 0xa340c064, 0x723c, 0x4a9c, { 0xa4, 0xdd, 0xd5, 0xb4, 0x7a, 0x26, 0xfb, 0xb0 }} + + ## Include/Protocol/SmmExitBootServices.h + gEdkiiSmmExitBootServicesProtocolGuid = { 0x296eb418, 0xc4c8, 0x4e05, { 0xab, 0x59, 0x39, 0xe8, 0xaf, 0x56, 0xf0, 0xa } } + + ## Include/Protocol/SmmLegacyBoot.h + gEdkiiSmmLegacyBootProtocolGuid = { 0x85a8ab57, 0x644, 0x4110, { 0x85, 0xf, 0x98, 0x13, 0x22, 0x4, 0x70, 0x70 } } + + ## Include/Protocol/SmmReadyToBoot.h + gEdkiiSmmReadyToBootProtocolGuid = { 0x6e057ecf, 0xfa99, 0x4f39, { 0x95, 0xbc, 0x59, 0xf9, 0x92, 0x1d, 0x17, 0xe4 } } + + ## Include/Protocol/PlatformLogo.h + gEdkiiPlatformLogoProtocolGuid = { 0x53cd299f, 0x2bc1, 0x40c0, { 0x8c, 0x07, 0x23, 0xf6, 0x4f, 0xdb, 0x30, 0xe0 } } + + ## Include/Protocol/FileExplorer.h + gEfiFileExplorerProtocolGuid = { 0x2C03C536, 0x4594, 0x4515, { 0x9E, 0x7A, 0xD3, 0xD2, 0x04, 0xFE, 0x13, 0x63 } } + + ## Include/Protocol/IpmiProtocol.h + gIpmiProtocolGuid = { 0xdbc6381f, 0x5554, 0x4d14, { 0x8f, 0xfd, 0x76, 0xd7, 0x87, 0xb8, 0xac, 0xbf } } + gSmmIpmiProtocolGuid = { 0x5169af60, 0x8c5a, 0x4243, { 0xb3, 0xe9, 0x56, 0xc5, 0x6d, 0x18, 0xee, 0x26 } } + + ## PS/2 policy protocol abstracts the specific platform initialization and setting. + # Include/Protocol/Ps2Policy.h + gEfiPs2PolicyProtocolGuid = { 0x4DF19259, 0xDC71, 0x4D46, { 0xBE, 0xF1, 0x35, 0x7B, 0xB5, 0x78, 0xC4, 0x18 } } + + ## Include/Protocol/NonDiscoverableDevice.h + gEdkiiNonDiscoverableDeviceProtocolGuid = { 0x0d51905b, 0xb77e, 0x452a, {0xa2, 0xc0, 0xec, 0xa0, 0xcc, 0x8d, 0x51, 0x4a } } + + ## Include/Protocol/IoMmu.h + gEdkiiIoMmuProtocolGuid = { 0x4e939de9, 0xd948, 0x4b0f, { 0x88, 0xed, 0xe6, 0xe1, 0xce, 0x51, 0x7c, 0x1e } } + + ## Include/Protocol/DeviceSecurity.h + gEdkiiDeviceSecurityProtocolGuid = { 0x5d6b38c8, 0x5510, 0x4458, { 0xb4, 0x8d, 0x95, 0x81, 0xcf, 0xa7, 0xb0, 0xd } } + gEdkiiDeviceIdentifierTypePciGuid = { 0x2509b2f1, 0xa022, 0x4cca, { 0xaf, 0x70, 0xf9, 0xd3, 0x21, 0xfb, 0x66, 0x49 } } + gEdkiiDeviceIdentifierTypeUsbGuid = { 0x7394f350, 0x394d, 0x488c, { 0xbb, 0x75, 0xc, 0xab, 0x7b, 0x12, 0xa, 0xc5 } } + + ## Include/Protocol/SmmMemoryAttribute.h + gEdkiiSmmMemoryAttributeProtocolGuid = { 0x69b792ea, 0x39ce, 0x402d, { 0xa2, 0xa6, 0xf7, 0x21, 0xde, 0x35, 0x1d, 0xfe } } + + ## Include/Protocol/SdMmcOverride.h + gEdkiiSdMmcOverrideProtocolGuid = { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } } + + ## Include/Protocol/PlatformSpecificResetFilter.h + gEdkiiPlatformSpecificResetFilterProtocolGuid = { 0x695d7835, 0x8d47, 0x4c11, { 0xab, 0x22, 0xfa, 0x8a, 0xcc, 0xe7, 0xae, 0x7a } } + ## Include/Protocol/PlatformSpecificResetHandler.h + gEdkiiPlatformSpecificResetHandlerProtocolGuid = { 0x2df6ba0b, 0x7092, 0x440d, { 0xbd, 0x4, 0xfb, 0x9, 0x1e, 0xc3, 0xf3, 0xc1 } } + + ## Include/Protocol/FirmwareManagementProgress.h + gEdkiiFirmwareManagementProgressProtocolGuid = { 0x1849bda2, 0x6952, 0x4e86, { 0xa1, 0xdb, 0x55, 0x9a, 0x3c, 0x47, 0x9d, 0xf1 } } + + ## Include/Protocol/AtaAtapiPolicy.h + gEdkiiAtaAtapiPolicyProtocolGuid = { 0xe59cd769, 0x5083, 0x4f26,{ 0x90, 0x94, 0x6c, 0x91, 0x9f, 0x91, 0x6c, 0x4e } } + + ## Include/Protocol/PeCoffImageEmulator.h + gEdkiiPeCoffImageEmulatorProtocolGuid = { 0x96f46153, 0x97a7, 0x4793, { 0xac, 0xc1, 0xfa, 0x19, 0xbf, 0x78, 0xea, 0x97 } } + + ## Include/Protocol/PlatformBootManager.h + gEdkiiPlatformBootManagerProtocolGuid = { 0xaa17add4, 0x756c, 0x460d, { 0x94, 0xb8, 0x43, 0x88, 0xd7, 0xfb, 0x3e, 0x59 } } + +# +# [Error.gEfiMdeModulePkgTokenSpaceGuid] +# 0x80000001 | Invalid value provided. +# 0x80000002 | Reserved bits must be set to zero. +# 0x80000003 | Incorrect progress code provided. +# 0x80000004 | Invalid foreground color specified. +# 0x80000005 | Invalid background color specified. +# 0x80000006 | Incorrect error code provided. +# + + ## Include/Protocol/VariablePolicy.h + gEdkiiVariablePolicyProtocolGuid = { 0x81D1675C, 0x86F6, 0x48DF, { 0xBD, 0x95, 0x9A, 0x6E, 0x4F, 0x09, 0x25, 0xC3 } } + + ## Include/Protocol/UsbEthernetProtocol.h + gEdkIIUsbEthProtocolGuid = { 0x8d8969cc, 0xfeb0, 0x4303, { 0xb2, 0x1a, 0x1f, 0x11, 0x6f, 0x38, 0x56, 0x43 } } + +[PcdsFeatureFlag] + ## Indicates if the platform can support update capsule across a system reset.

+ # TRUE - Supports update capsule across a system reset.
+ # FALSE - Does not support update capsule across a system reset.
+ # @Prompt Enable update capsule across a system reset. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE|BOOLEAN|0x0001001d + + ## Indicates if all PCD PPI services will be enabled.

+ # TRUE - All PCD PPI services will be produced.
+ # FALSE - Minimal PCD PPI services (only GetService) will be produced.
+ # @Prompt Enable full PEI PCD services. + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiFullPcdDatabaseEnable|TRUE|BOOLEAN|0x00010020 + + ## Indicates if the Device Path To Text Protocol should be produced by the platform. + # It can be disabled to save size.

+ # TRUE - Device Path To Text Protocol will be produced.
+ # FALSE - Device Path To Text Protocol will not be produced.
+ # @Prompt Enable Device Path to Text support. + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathToText|TRUE|BOOLEAN|0x00010037 + + ## Indicates if the Device Path From Text Protocol should be produced by the platform. + # It can be disabled to save size.

+ # TRUE - Device Path From Text Protocol will be produced.
+ # FALSE - Device Path From Text Protocol will not be produced.
+ # @Prompt Enable Device Path From Text support. + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathFromText|TRUE|BOOLEAN|0x00010038 + + ## Indicates if the UEFI variable runtime cache should be enabled. + # This setting only applies if SMM variables are enabled. When enabled, all variable + # data for Runtime Service GetVariable () and GetNextVariableName () calls is retrieved + # from a runtime data buffer referred to as the "runtime cache". An SMI is not triggered + # at all for these requests. Variables writes still trigger an SMI. This can greatly + # reduce overall system SMM usage as most boots tend to issue far more variable reads + # than writes.

+ # TRUE - The UEFI variable runtime cache is enabled.
+ # FALSE - The UEFI variable runtime cache is disabled.
+ # @Prompt Enable the UEFI variable runtime cache. + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|TRUE|BOOLEAN|0x00010039 + + ## Indicates if the statistics about variable usage will be collected. This information is + # stored as a vendor configuration table into the EFI system table. + # Set this PCD to TRUE to use VariableInfo application in MdeModulePkg\Application directory to get + # variable usage info. VariableInfo application will not output information if not set to TRUE.

+ # TRUE - Statistics about variable usage will be collected.
+ # FALSE - Statistics about variable usage will not be collected.
+ # @Prompt Enable variable statistics collection. + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE|BOOLEAN|0x0001003f + + ## Indicates if Unicode Collation Protocol will be installed.

+ # TRUE - Installs Unicode Collation Protocol.
+ # FALSE - Does not install Unicode Collation Protocol.
+ # @Prompt Enable Unicode Collation support. + gEfiMdeModulePkgTokenSpaceGuid.PcdUnicodeCollationSupport|TRUE|BOOLEAN|0x00010040 + + ## Indicates if Unicode Collation 2 Protocol will be installed.

+ # TRUE - Installs Unicode Collation 2 Protocol.
+ # FALSE - Does not install Unicode Collation 2 Protocol.
+ # @Prompt Enable Unicode Collation 2 support. + gEfiMdeModulePkgTokenSpaceGuid.PcdUnicodeCollation2Support|TRUE|BOOLEAN|0x00010041 + + ## Indicates if Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size.

+ # TRUE - Installs Graphics Output Protocol on virtual handle created by ConsplitterDxe.
+ # FALSE - Does not install Graphics Output Protocol on virtual handle created by ConsplitterDxe.
+ # @Prompt Enable ConOut GOP support. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE|BOOLEAN|0x00010042 + + ## Indicates if UGA Draw Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size.

+ # TRUE - Installs UGA Draw Protocol on virtual handle created by ConsplitterDxe.
+ # FALSE - Does not install UGA Draw Protocol on virtual handle created by ConsplitterDxe.
+ # @Prompt Enable ConOut UGA support. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|TRUE|BOOLEAN|0x00010043 + + ## Indicates PeiCore will first search TE section from the PEIM to load the image, or PE32 section, when PeiCore dispatches a PEI module. + # This PCD is used to tune PEI phase performance to reduce the search image time. + # It can be set according to the generated image section type.

+ # TRUE - PeiCore will first search TE section from PEIM to load the image, if TE section is not found, then PeiCore will search PE section.
+ # FALSE - PeiCore will first search PE section from PEIM to load the image.
+ # @Prompt PeiCore search TE section first. + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|TRUE|BOOLEAN|0x00010044 + + ## Indicates if to turn off the support of legacy usb. So legacy usb device driver can not make use of SMI + # interrupt to access usb device in the case of absence of usb stack. + # DUET platform requires the token to be TRUE.

+ # TRUE - Turn off usb legacy support.
+ # FALSE - Does not turn off usb legacy support.
+ # @Prompt Turn off USB legacy support. + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|FALSE|BOOLEAN|0x00010047 + + ## Indicates if HiiImageProtocol will be installed. + # FALSE is for size reduction.

+ # TRUE - Installs HiiImageProtocol.
+ # FALSE - Does not install HiiImageProtocol.
+ # @Prompt Enable HII image support. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportHiiImageProtocol|TRUE|BOOLEAN|0x00010100 + + ## Indicates if USB KeyBoard Driver disables the default keyboard layout. + # The default keyboard layout serves as the backup when no keyboard layout can be retrieved + # from HII database.

+ # TRUE - USB KeyBoard Driver will disable the default keyboard layout.
+ # FALSE - USB KeyBoard Driver will not disable the default keyboard layout.
+ # @Prompt Disable default keyboard layout in USB KeyBoard Driver. + gEfiMdeModulePkgTokenSpaceGuid.PcdDisableDefaultKeyboardLayoutInUsbKbDriver|FALSE|BOOLEAN|0x00010200 + + ## Indicates if HelloWorld Application will print the verbose information. + # This PCD is a sample to explain FeatureFlag PCD usage.

+ # TRUE - HelloWorld Application will print the verbose information.
+ # FALSE - HelloWorld Application will not print the verbose information.
+ # @Prompt Enable HelloWorld print. + gEfiMdeModulePkgTokenSpaceGuid.PcdHelloWorldPrintEnable|TRUE|BOOLEAN|0x0001200a + + ## Indicates if FULL FTW protocol services (total six APIs) will be produced.

+ # TRUE - Produces FULL FTW protocol services (total six APIs).
+ # FALSE - Only FTW Write service is available.
+ # @Prompt Enable FULL FTW services. + gEfiMdeModulePkgTokenSpaceGuid.PcdFullFtwServiceEnable|TRUE|BOOLEAN|0x0001200b + + ## Indicates if DXE IPL supports the UEFI decompression algorithm.

+ # TRUE - DXE IPL will support UEFI decompression.
+ # FALSE - DXE IPL will not support UEFI decompression to save space.
+ # @Prompt Enable UEFI decompression support in DXE IPL. + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|TRUE|BOOLEAN|0x0001200c + + ## Indicates if PciBus driver supports the hot plug device.

+ # TRUE - PciBus driver supports the hot plug device.
+ # FALSE - PciBus driver doesn't support the hot plug device.
+ # @Prompt Enable PciBus hot plug device support. + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE|BOOLEAN|0x0001003d + + ## Indicates if the PciBus driver probes non-standard, such as 2K/1K/512, granularity for PCI to PCI bridge I/O window.

+ # TRUE - PciBus driver probes non-standard granularity for PCI to PCI bridge I/O window.
+ # FALSE - PciBus driver doesn't probe non-standard granularity for PCI to PCI bridge I/O window.
+ # @Prompt Enable PCI bridge IO alignment probe. + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBridgeIoAlignmentProbe|FALSE|BOOLEAN|0x0001004e + + ## Indicates if PEI phase StatusCode will be replayed in DXE phase.

+ # TRUE - Replays PEI phase StatusCode in DXE phased.
+ # FALSE - Does not replay PEI phase StatusCode in DXE phase.
+ # @Prompt Enable PEI StatusCode replay in DXE phase + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeReplayIn|FALSE|BOOLEAN|0x0001002d + + ## Indicates if ACPI SDT protocol will be installed.

+ # TRUE - Installs ACPI SDT protocol.
+ # FALSE - Does not install ACPI SDT protocol.
+ # @Prompt Enable ACPI SDT support. + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|FALSE|BOOLEAN|0x0001004d + + ## Indicates if the unaligned I/O, MMIO, and PCI Configuration cycles through the PCI I/O Protocol are enabled. + # The default value for this PCD is false to disable support for unaligned PCI I/O Protocol requests.

+ # TRUE - Enables the unaligned I/O, MMIO, and PCI Configuration cycles through the PCI I/O Protocol.
+ # FALSE - Disables the unaligned I/O, MMIO, and PCI Configuration cycles through the PCI I/O Protocol.
+ # @Prompt Enable unaligned PCI I/O support. + gEfiMdeModulePkgTokenSpaceGuid.PcdUnalignedPciIoEnable|FALSE|BOOLEAN|0x0001003e + + ## Indicates if TEXT statement is always set to GrayOut statement in HII Form Browser.

+ # TRUE - TEXT statement will always be set to GrayOut.
+ # FALSE - TEXT statement will be set to GrayOut only when GrayOut condition is TRUE.
+ # @Prompt Always GrayOut TEXT statement. + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|FALSE|BOOLEAN|0x0001004f + + ## Indicates if unselectable menu should be gray out in HII Form Browser.

+ # TRUE - The unselectable menu will be set to GrayOut.
+ # FALSE - The menu will be show as normal menu entry even if it is not selectable.
+ # @Prompt GrayOut read only menu. + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|FALSE|BOOLEAN|0x00010070 + + ## Indicates if recovery from IDE disk will be supported.

+ # TRUE - Supports recovery from IDE disk.
+ # FALSE - Does not support recovery from IDE disk.
+ # @Prompt Enable recovery on IDE disk. + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk|TRUE|BOOLEAN|0x00010060 + + ## Indicates if recovery from FAT floppy disk will be supported.

+ # TRUE - Supports recovery from FAT floppy disk.
+ # FALSE - Does not support recovery from FAT floppy disk.
+ # @Prompt Enable recovery on FAT floppy disk. + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk|TRUE|BOOLEAN|0x00010061 + + ## Indicates if recovery from data CD will be supported.

+ # TRUE - Supports recovery from data CD.
+ # FALSE - Does not support recovery from data CD.
+ # @Prompt Enable recovery on data CD. + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD|TRUE|BOOLEAN|0x00010062 + + ## Indicates if recovery from FAT USB disk will be supported.

+ # TRUE - Supports recovery from USB disk.
+ # FALSE - Does not support recovery from USB disk.
+ # @Prompt Enable recovery on FAT USB disk. + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatUsbDisk|TRUE|BOOLEAN|0x00010063 + + ## Indicates if S3 performance data will be supported in ACPI FPDT table.

+ # TRUE - S3 performance data will be supported in ACPI FPDT table.
+ # FALSE - S3 performance data will not be supported in ACPI FPDT table.
+ # @Prompt Enable S3 performance data support. + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|TRUE|BOOLEAN|0x00010064 + + ## Indicates if PS2 keyboard does a extended verification during start. + # Add this PCD mainly consider the use case of simulator. This PCD maybe set to FALSE for + # Extended verification will take some performance. It can be set to FALSE for boot performance.

+ # TRUE - Turn on PS2 keyboard extended verification.
+ # FALSE - Turn off PS2 keyboard extended verification.
+ # @Prompt Turn on PS2 Keyboard Extended Verification + gEfiMdeModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|TRUE|BOOLEAN|0x00010072 + + ## Indicates if Serial device uses half hand shake.

+ # TRUE - Serial device uses half hand shake.
+ # FALSE - Serial device doesn't use half hand shake.
+ # @Prompt Enable Serial device Half Hand Shake + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHalfHandshake|FALSE|BOOLEAN|0x00010073 + + ## Indicates if HII data and configuration has been exported.

+ # Add this PCD mainly consider the use case of simulator. This PCD maybe set to FALSE for + # simulator platform because the performance cost for this feature. + # TRUE - Export HII data and configuration data.
+ # FALSE - Does not export HII data and configuration.
+ # @Prompt Enable export HII data and configuration to be used in OS runtime. + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|TRUE|BOOLEAN|0x00010074 + + ## Indicates if PS2 mouse does a extended verification during start. + # Extended verification will take some performance. It can be set to FALSE for boot performance.

+ # TRUE - Turn on PS2 mouse extended verification.
+ # FALSE - Turn off PS2 mouse extended verification.
+ # @Prompt Turn on PS2 Mouse Extended Verification + gEfiMdeModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|TRUE|BOOLEAN|0x00010075 + + ## Indicates whether 64-bit PCI MMIO BARs should degrade to 32-bit in the presence of an option ROM + # On X64 platforms, Option ROMs may contain code that executes in the context of a legacy BIOS (CSM), + # which requires that all PCI MMIO BARs are located below 4 GB + # TRUE - All PCI MMIO BARs of a device will be located below 4 GB if it has an option ROM + # FALSE - PCI MMIO BARs of a device may be located above 4 GB even if it has an option ROM + # @Prompt Degrade 64-bit PCI MMIO BARs for legacy BIOS option ROMs + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|TRUE|BOOLEAN|0x0001003a + + ## Indicates if the platform can support process non-reset capsule image at runtime.

+ # TRUE - Supports process non-reset capsule image at runtime.
+ # FALSE - Does not support process non-reset capsule image at runtime.
+ # @Prompt Enable process non-reset capsule image at runtime. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportProcessCapsuleAtRuntime|FALSE|BOOLEAN|0x00010079 + +[PcdsFeatureFlag.IA32, PcdsFeatureFlag.ARM, PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.LOONGARCH64] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE|BOOLEAN|0x0001003a + +[PcdsFeatureFlag.IA32, PcdsFeatureFlag.X64] + ## Indicates if DxeIpl should switch to long mode to enter DXE phase. + # TRUE - DxeIpl will load a 64-bit DxeCore and switch to long mode to hand over to DxeCore.
+ # FALSE - DxeIpl will load a 32-bit or 64-bit DxeCore and perform stack switch to hand over to DxeCore.
+ # @Prompt DxeIpl switch to long mode. + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE|BOOLEAN|0x0001003b + + ## Indicates if DxeIpl should rebuild page tables. This flag only + # makes sense in the case where the DxeIpl and the DxeCore are both X64.

+ # TRUE - DxeIpl will rebuild page tables.
+ # FALSE - DxeIpl will not rebuild page tables.
+ # @Prompt DxeIpl rebuild page tables. + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplBuildPageTables|TRUE|BOOLEAN|0x0001003c + +[PcdsFixedAtBuild] + ## Flag of enabling/disabling the feature of Loading Module at Fixed Address.

+ # 0xFFFFFFFFFFFFFFFF: Enable the feature as fixed offset to TOLM.
+ # 0: Disable the feature.
+ # Other Value: Enable the feature as fixed absolute address, and the value is the top memory address.
+ # @Prompt Enable LMFA feature. + # @Expression 0x80000001 | (gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable == 0xFFFFFFFFFFFFFFFF || gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable <= 0x0FFFFFFFFFFFFFFF) + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0|UINT64|0x30001015 + + ## Progress Code for OS Loader LoadImage start.

+ # PROGRESS_CODE_OS_LOADER_LOAD = (EFI_SOFTWARE_DXE_BS_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x03058000
+ # @Prompt Progress Code for OS Loader LoadImage start. + # @ValidList 0x80000003 | 0x03058000 + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderLoad|0x03058000|UINT32|0x30001030 + + ## Progress Code for OS Loader StartImage start.

+ # PROGRESS_CODE_OS_LOADER_START = (EFI_SOFTWARE_DXE_BS_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03058001
+ # @Prompt Progress Code for OS Loader StartImage start. + # @ValidList 0x80000003 | 0x03058001 + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderStart|0x03058001|UINT32|0x30001031 + + ## Progress Code for S3 Suspend start.

+ # PROGRESS_CODE_S3_SUSPEND_START = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x03078000
+ # @Prompt Progress Code for S3 Suspend start. + # @ValidList 0x80000003 | 0x03078000 + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x30001032 + + ## Progress Code for S3 Suspend end.

+ # PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+ # @Prompt Progress Code for S3 Suspend end. + # @ValidList 0x80000003 | 0x03078001 + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001033 + + ## Error Code for SetVariable failure.

+ # EDKII_ERROR_CODE_SET_VARIABLE = (EFI_SOFTWARE_DXE_BS_DRIVER | (EFI_OEM_SPECIFIC | 0x00000002)) = 0x03058002
+ # @Prompt Error Code for SetVariable failure. + # @ValidList 0x80000006 | 0x03058002 + gEfiMdeModulePkgTokenSpaceGuid.PcdErrorCodeSetVariable|0x03058002|UINT32|0x30001040 + + ## Mask to control the NULL address detection in code for different phases. + # If enabled, accessing NULL address in UEFI or SMM code can be caught.

+ # BIT0 - Enable NULL pointer detection for UEFI.
+ # BIT1 - Enable NULL pointer detection for SMM.
+ # BIT2..5 - Reserved for future uses.
+ # BIT6 - Enable non-stop mode.
+ # BIT7 - Disable NULL pointer detection just after EndOfDxe.
+ # This is a workaround for those unsolvable NULL access issues in + # OptionROM, boot loader, etc. It can also help to avoid unnecessary + # exception caused by legacy memory (0-4095) access after EndOfDxe, + # such as Windows 7 boot on Qemu.
+ # @Prompt Enable NULL address detection. + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask|0x0|UINT8|0x30001050 + + ## Init Value in Temp Stack to be shared between SEC and PEI_CORE + # SEC fills the full temp stack with this values. When switch stack, PeiCore can check + # this value in the temp stack to know how many stack has been used. + # @Prompt Init Value in Temp Stack + gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack|0x5AA55AA5|UINT32|0x30001051 + + ## Indicates which type allocation need guard page. + # + # If a bit is set, a head guard page and a tail guard page will be added just + # before and after corresponding type of pages allocated if there's enough + # free pages for all of them. The page allocation for the type related to + # cleared bits keeps the same as ususal. + # + # This PCD is only valid if BIT0 and/or BIT2 are set in PcdHeapGuardPropertyMask. + # + # Below is bit mask for this PCD: (Order is same as UEFI spec)
+ # EfiReservedMemoryType 0x0000000000000001
+ # EfiLoaderCode 0x0000000000000002
+ # EfiLoaderData 0x0000000000000004
+ # EfiBootServicesCode 0x0000000000000008
+ # EfiBootServicesData 0x0000000000000010
+ # EfiRuntimeServicesCode 0x0000000000000020
+ # EfiRuntimeServicesData 0x0000000000000040
+ # EfiConventionalMemory 0x0000000000000080
+ # EfiUnusableMemory 0x0000000000000100
+ # EfiACPIReclaimMemory 0x0000000000000200
+ # EfiACPIMemoryNVS 0x0000000000000400
+ # EfiMemoryMappedIO 0x0000000000000800
+ # EfiMemoryMappedIOPortSpace 0x0000000000001000
+ # EfiPalCode 0x0000000000002000
+ # EfiPersistentMemory 0x0000000000004000
+ # OEM Reserved 0x4000000000000000
+ # OS Reserved 0x8000000000000000
+ # e.g. LoaderCode+LoaderData+BootServicesCode+BootServicesData are needed, 0x1E should be used.
+ # @Prompt The memory type mask for Page Guard. + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPageType|0x0|UINT64|0x30001052 + + ## Indicates which type allocation need guard page. + # + # If a bit is set, a head guard page and a tail guard page will be added just + # before and after corresponding type of pages which the allocated pool occupies, + # if there's enough free memory for all of them. The pool allocation for the + # type related to cleared bits keeps the same as ususal. + # + # This PCD is only valid if BIT1 and/or BIT3 are set in PcdHeapGuardPropertyMask. + # + # Below is bit mask for this PCD: (Order is same as UEFI spec)
+ # EfiReservedMemoryType 0x0000000000000001
+ # EfiLoaderCode 0x0000000000000002
+ # EfiLoaderData 0x0000000000000004
+ # EfiBootServicesCode 0x0000000000000008
+ # EfiBootServicesData 0x0000000000000010
+ # EfiRuntimeServicesCode 0x0000000000000020
+ # EfiRuntimeServicesData 0x0000000000000040
+ # EfiConventionalMemory 0x0000000000000080
+ # EfiUnusableMemory 0x0000000000000100
+ # EfiACPIReclaimMemory 0x0000000000000200
+ # EfiACPIMemoryNVS 0x0000000000000400
+ # EfiMemoryMappedIO 0x0000000000000800
+ # EfiMemoryMappedIOPortSpace 0x0000000000001000
+ # EfiPalCode 0x0000000000002000
+ # EfiPersistentMemory 0x0000000000004000
+ # OEM Reserved 0x4000000000000000
+ # OS Reserved 0x8000000000000000
+ # e.g. LoaderCode+LoaderData+BootServicesCode+BootServicesData are needed, 0x1E should be used.
+ # @Prompt The memory type mask for Pool Guard. + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPoolType|0x0|UINT64|0x30001053 + + ## This mask is to control Heap Guard behavior. + # + # Note: + # a) Heap Guard is for debug purpose and should not be enabled in product + # BIOS. + # b) Due to the limit of pool memory implementation and the alignment + # requirement of UEFI spec, BIT7 is a try-best setting which cannot + # guarantee that the returned pool is exactly adjacent to head guard + # page or tail guard page. + # c) UEFI freed-memory guard and UEFI pool/page guard cannot be enabled + # at the same time. + # + # BIT0 - Enable UEFI page guard.
+ # BIT1 - Enable UEFI pool guard.
+ # BIT2 - Enable SMM page guard.
+ # BIT3 - Enable SMM pool guard.
+ # BIT4 - Enable UEFI freed-memory guard (Use-After-Free memory detection).
+ # BIT6 - Enable non-stop mode.
+ # BIT7 - The direction of Guard Page for Pool Guard. + # 0 - The returned pool is near the tail guard page.
+ # 1 - The returned pool is near the head guard page.
+ # @Prompt The Heap Guard feature mask + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask|0x0|UINT8|0x30001054 + + ## Indicates if UEFI Stack Guard will be enabled. + # If enabled, stack overflow in UEFI can be caught, preventing chaotic consequences.

+ # TRUE - UEFI Stack Guard will be enabled.
+ # FALSE - UEFI Stack Guard will be disabled.
+ # @Prompt Enable UEFI Stack Guard. + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0x30001055 + + ## Indicate debug level of Trace Hub. + # 0x0 - TraceHubDebugLevelError.
+ # 0x1 - TraceHubDebugLevelErrorWarning.
+ # 0x2 - TraceHubDebugLevelErrorWarningInfo.
+ # 0x3 - TraceHubDebugLevelErrorWarningInfoVerbose.
+ # @Prompt Debug level of Trace Hub. + gEfiMdeModulePkgTokenSpaceGuid.PcdTraceHubDebugLevel|0|UINT8|0x30001056 + + ## Flag to enable or disable Trace Hub message. + # FALSE - Disable Trace Hub debug message.
+ # TRUE - Enable Trace Hub debug message.
+ # @Prompt Enable or Disable Trace Hub message. + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableTraceHubDebugMsg|0|BOOLEAN|0x30001057 + + ## Indicate MMIO address where Trace Hub message output to. + # @Prompt Output MMIO address of Trace Hub message. + gEfiMdeModulePkgTokenSpaceGuid.PcdTraceHubDebugMmioAddress|0|UINT64|0x30001058 + + ## Indicates if images with large load address (>0x100000) should attempted to load at specified location. + # If enabled, attempt to allocate at specfied location will be attempted with a fall back to any address. + # TRUE - UEFI will attempt to load at specified location.
+ # FALSE - UEFI will load at any address
+ # @Prompt Enable large address image loading. + gEfiMdeModulePkgTokenSpaceGuid.PcdImageLargeAddressLoad|TRUE|BOOLEAN|0x30001059 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + ## Dynamic type PCD can be registered callback function for Pcd setting action. + # PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of callback function + # for a dynamic PCD used in PEI phase. + # @Prompt Max PEI PCD callback number per PCD entry. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPcdCallBackNumberPerPcdEntry|0x08|UINT32|0x0001000f + + ## VPD type PCD allows a developer to point to an absolute physical address PcdVpdBaseAddress + # to store PCD value. + # @Prompt VPD base address. + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0|UINT32|0x00010010 + + ## Maximum stack size for PeiCore. + # @Prompt Maximum stack size for PeiCore. + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x20000|UINT32|0x00010032 + + ## The maximum size of a single non-HwErr type variable. + # @Prompt Maximum variable size. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400|UINT32|0x30000003 + + ## The maximum size of a single authenticated variable. + # The value is 0 as default for compatibility that maximum authenticated variable size is specified by PcdMaxVariableSize. + # @Prompt Maximum authenticated variable size. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x00|UINT32|0x30000009 + + ## The maximum size of a single non-authenticated volatile variable. + # The default value is 0 for compatibility: in that case, the maximum + # non-authenticated volatile variable size remains specified by + # PcdMaxVariableSize. Only the MdeModulePkg/Universal/Variable/RuntimeDxe + # driver supports this PCD. + # @Prompt Maximum non-authenticated volatile variable size. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVolatileVariableSize|0x00|UINT32|0x3000000a + + ## The maximum size of single hardware error record variable.

+ # In IA32/X64 platforms, this value should be larger than 1KB.
+ # In IA64 platforms, this value should be larger than 128KB.
+ # @Prompt Maximum HwErr variable size. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000|UINT32|0x30000004 + + ## The size of reserved HwErr variable space. Note that this value must be less than (PcdFlashNvStorageVariableSize - EFI_FIRMWARE_VOLUME_HEADER.HeaderLength - sizeof (VARIABLE_STORE_HEADER)). + # In EdkII implementation, HwErr type variable is stored with common non-volatile variables in the same NV region. + # so the platform integrator should ensure this value is less than (PcdFlashNvStorageVariableSize - EFI_FIRMWARE_VOLUME_HEADER.HeaderLength - sizeof (VARIABLE_STORE_HEADER)). + # this value is used to guarantee the space of HwErr type variable and not populated by common variable. + # @Prompt HwErr variable storage size. + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0000|UINT32|0x30000006 + + ## The size of maximum user NV variable space.

+ # Note that this value must be less than (PcdFlashNvStorageVariableSize - EFI_FIRMWARE_VOLUME_HEADER.HeaderLength - sizeof (VARIABLE_STORE_HEADER) - PcdHwErrStorageSize).
+ # If the value is 0, it means user variable share the same NV storage with system variable, + # this is designed to keep the compatibility for the platform that does not allocate special region for user variable.
+ # If the value is non-0, the below 4 types of variables will be regarded as System Variable after EndOfDxe, their property could be got by VarCheck protocol, + # otherwise the variable will be regarded as user variable.
+ # 1) UEFI defined variables (gEfiGlobalVariableGuid and gEfiImageSecurityDatabaseGuid(auth variable) variables at least).
+ # 2) Variables managed by Variable driver internally.
+ # 3) Variables need to be locked, they MUST be set by VariableLock protocol.
+ # 4) Important variables during platform boot, their property SHOULD be set by VarCheck protocol.
+ # The PCD is used to guarantee the space of system variable and not populated by user variable.
+ # @Prompt Maximum user NV variable space size. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxUserNvVariableSpaceSize|0x00|UINT32|0x00000009 + + ## The size of NV variable space reserved at UEFI boottime.

+ # Note that this value must be less than (PcdFlashNvStorageVariableSize - EFI_FIRMWARE_VOLUME_HEADER.HeaderLength - sizeof (VARIABLE_STORE_HEADER) - PcdHwErrStorageSize).
+ # In EdkII implementation, variable driver can reserved some NV storage region for boottime settings. + # So at UEFI runtime, the variable service consumer can not exhaust full NV storage region.
+ # Then the common NV variable space size at boottime will be + # (PcdFlashNvStorageVariableSize - EFI_FIRMWARE_VOLUME_HEADER.HeaderLength - sizeof (VARIABLE_STORE_HEADER) - PcdHwErrStorageSize),
+ # and the common NV variable space size at runtime will be + # (PcdFlashNvStorageVariableSize - EFI_FIRMWARE_VOLUME_HEADER.HeaderLength - sizeof (VARIABLE_STORE_HEADER) - PcdHwErrStorageSize) - PcdBoottimeReservedNvVariableSpaceSize.
+ # @Prompt Boottime reserved NV variable space size. + gEfiMdeModulePkgTokenSpaceGuid.PcdBoottimeReservedNvVariableSpaceSize|0x00|UINT32|0x30000007 + + ## Reclaim variable space at EndOfDxe.

+ # The value is FALSE as default for compatibility that variable driver tries to reclaim variable space at ReadyToBoot event.
+ # If the value is set to TRUE, variable driver tries to reclaim variable space at EndOfDxe event.
+ # @Prompt Reclaim variable space at EndOfDxe. + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|FALSE|BOOLEAN|0x30000008 + + ## The size of volatile buffer. This buffer is used to store VOLATILE attribute variables. + # @Prompt Variable storage size. + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000|UINT32|0x30000005 + + ## Toggle for whether the VariablePolicy engine should allow disabling. + # The engine is enabled at power-on, but the interface allows the platform to + # disable enforcement for servicing flexibility. If this PCD is disabled, it will block the ability to + # disable the enforcement and VariablePolicy enforcement will always be ON. + # TRUE - VariablePolicy can be disabled by request through the interface (until interface is locked) + # FALSE - VariablePolicy interface will not accept requests to disable and is ALWAYS ON + # @Prompt Allow VariablePolicy enforcement to be disabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdAllowVariablePolicyEnforcementDisable|FALSE|BOOLEAN|0x30000020 + + ## FFS filename to find the ACPI tables. + # @Prompt FFS name of ACPI tables storage. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile|{ 0x25, 0x4e, 0x37, 0x7e, 0x01, 0x8e, 0xee, 0x4f, 0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd }|VOID*|0x30000016 + + ## FFS filename to find the capsule coalesce image. + # @Prompt FFS name of capsule coalesce image. + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleCoalesceFile|{ 0xA6, 0xE4, 0xFD, 0xF7, 0x4C, 0x29, 0x3c, 0x49, 0xB5, 0x0F, 0x97, 0x34, 0x55, 0x3B, 0xB7, 0x57 }|VOID*|0x30000017 + + ## Maximum number of performance log entries during PEI phase. + # Use PcdMaxPeiPerformanceLogEntries16 if the number of entries required is + # more than 255. + # @Prompt Maximum number of PEI performance log entries. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f + + ## Maximum number of performance log entries during PEI phase. + # If set to 0, then PcdMaxPeiPerformanceLogEntries determines the number of + # entries. If greater than 0, then this PCD determines the number of entries, + # and PcdMaxPeiPerformanceLogEntries is ignored. + # @Prompt Maximum number of PEI performance log entries. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries16|0|UINT16|0x00010035 + + ## Indicates the 16550 serial port registers are in MMIO space, or in I/O space. Default is I/O space.

+ # TRUE - 16550 serial port registers are in MMIO space.
+ # FALSE - 16550 serial port registers are in I/O space.
+ # @Prompt Serial port registers use MMIO. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE|BOOLEAN|0x00020000 + + ## Indicates the access width for 16550 serial port registers. + # Default is 8-bit access mode.

+ # 8 - 16550 serial port registers are accessed in 8-bit width.
+ # 32 - 16550 serial port registers are accessed in 32-bit width.
+ # @Prompt Serial port register access width. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterAccessWidth|8|UINT8|0x00020007 + + ## Indicates if the 16550 serial port hardware flow control will be enabled. Default is FALSE.

+ # TRUE - 16550 serial port hardware flow control will be enabled.
+ # FALSE - 16550 serial port hardware flow control will be disabled.
+ # @Prompt Enable serial port hardware flow control. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE|BOOLEAN|0x00020001 + + ## Indicates if the 16550 serial Tx operations will be blocked if DSR is not asserted (no cable). Default is FALSE. + # This PCD is ignored if PcdSerialUseHardwareFlowControl is FALSE.

+ # TRUE - 16550 serial Tx operations will be blocked if DSR is not asserted.
+ # FALSE - 16550 serial Tx operations will not be blocked if DSR is not asserted.
+ # @Prompt Enable serial port cable detetion. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE|BOOLEAN|0x00020006 + + ## Base address of 16550 serial port registers in MMIO or I/O space. Default is 0x3F8. + # @Prompt Base address of serial port registers. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8|UINT64|0x00020002 + + ## Baud rate for the 16550 serial port. Default is 115200 baud. + # @Prompt Baud rate for serial port. + # @ValidList 0x80000001 | 921600, 460800, 230400, 115200, 57600, 38400, 19200, 9600, 7200, 4800, 3600, 2400, 2000, 1800, 1200, 600, 300, 150, 134, 110, 75, 50 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200|UINT32|0x00020003 + + ## Line Control Register (LCR) for the 16550 serial port. This encodes data bits, parity, and stop bits.

+ # BIT1..BIT0 - Data bits. 00b = 5 bits, 01b = 6 bits, 10b = 7 bits, 11b = 8 bits
+ # BIT2 - Stop Bits. 0 = 1 stop bit. 1 = 1.5 stop bits if 5 data bits selected, otherwise 2 stop bits.
+ # BIT5..BIT3 - Parity. xx0b = No Parity, 001b = Odd Parity, 011b = Even Parity, 101b = Mark Parity, 111b=Stick Parity
+ # BIT7..BIT6 - Reserved. Must be 0.
+ # + # Default is No Parity, 8 Data Bits, 1 Stop Bit.
+ # @Prompt Serial port Line Control settings. + # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl & 0xC0) == 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03|UINT8|0x00020004 + + ## FIFO Control Register (FCR) for the 16550 serial port.

+ # BIT0 - FIFO Enable. 0 = Disable FIFOs. 1 = Enable FIFOs.
+ # BIT1 - Clear receive FIFO. 1 = Clear FIFO.
+ # BIT2 - Clear transmit FIFO. 1 = Clear FIFO.
+ # BIT4..BIT3 - Reserved. Must be 0.
+ # BIT5 - Enable 64-byte FIFO. 0 = Disable 64-byte FIFO. 1 = Enable 64-byte FIFO
+ # BIT7..BIT6 - Reserved. Must be 0.
+ # + # Default is to enable and clear all FIFOs.
+ # @Prompt Serial port FIFO Control settings. + # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl & 0xD8) == 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07|UINT8|0x00020005 + + ## Maximum address that the DXE Core will allocate the EFI_SYSTEM_TABLE_POINTER + # structure. The default value for this PCD is 0, which means that the DXE Core + # will allocate the buffer from the EFI_SYSTEM_TABLE_POINTER structure on a 4MB + # boundary as close to the top of memory as feasible. If this PCD is set to a + # value other than 0, then the DXE Core will first attempt to allocate the + # EFI_SYSTEM_TABLE_POINTER structure on a 4MB boundary below the address specified + # by this PCD, and if that allocation fails, retry the allocation on a 4MB + # boundary as close to the top of memory as feasible. + # @Prompt Maximum Efi System Table Pointer address. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxEfiSystemTablePointerAddress|0x0|UINT64|0x30001027 + + ## Indicates if to shadow PEIM on S3 boot path after memory is ready.

+ # TRUE - Shadow PEIM on S3 boot path after memory is ready.
+ # FALSE - Not shadow PEIM on S3 boot path after memory is ready.
+ # @Prompt Shadow Peim On S3 Boot. + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|FALSE|BOOLEAN|0x30001028 + + ## Indicates if to shadow PEIM and PeiCore after memory is ready.

+ # This PCD is used on other boot path except for S3 boot. + # TRUE - Shadow PEIM and PeiCore after memory is ready.
+ # FALSE - Not shadow PEIM after memory is ready.
+ # @Prompt Shadow Peim and PeiCore on boot + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnBoot|TRUE|BOOLEAN|0x30001029 + + ## Enable the feature that evacuate temporary memory to permanent memory or not

+ # Set FALSE as default, if the developer need this feature to avoid this vulnerability, please + # enable it to shadow all PEIMs no matter the behavior controled by PcdShadowPeimOnBoot or + # PcdShadowPeimOnS3Boot
+ # TRUE - Evacuate temporary memory, the actions include copy memory, convert PPI pointers and so on.
+ # FALSE - Do nothing, for example, no copy memory, no convert PPI pointers and so on.
+ # @Prompt Evacuate temporary memory to permanent memory + gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes|FALSE|BOOLEAN|0x3000102A + + ## The mask is used to control memory profile behavior.

+ # BIT0 - Enable UEFI memory profile.
+ # BIT1 - Enable SMRAM profile.
+ # BIT7 - Disable recording at the start.
+ # @Prompt Memory Profile Property. + # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask & 0x7C) == 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask|0x0|UINT8|0x30001041 + + ## The mask is used to control SmiHandlerProfile behavior.

+ # BIT0 - Enable SmiHandlerProfile.
+ # @Prompt SmiHandlerProfile Property. + # @Expression 0x80000002 | (gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask & 0xFE) == 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0|UINT8|0x00000108 + + ## This flag is to control which memory types of alloc info will be recorded by DxeCore & SmmCore.

+ # For SmmCore, only EfiRuntimeServicesCode and EfiRuntimeServicesData are valid.
+ # + # Below is bit mask for this PCD: (Order is same as UEFI spec)
+ # EfiReservedMemoryType 0x0001
+ # EfiLoaderCode 0x0002
+ # EfiLoaderData 0x0004
+ # EfiBootServicesCode 0x0008
+ # EfiBootServicesData 0x0010
+ # EfiRuntimeServicesCode 0x0020
+ # EfiRuntimeServicesData 0x0040
+ # EfiConventionalMemory 0x0080
+ # EfiUnusableMemory 0x0100
+ # EfiACPIReclaimMemory 0x0200
+ # EfiACPIMemoryNVS 0x0400
+ # EfiMemoryMappedIO 0x0800
+ # EfiMemoryMappedIOPortSpace 0x1000
+ # EfiPalCode 0x2000
+ # EfiPersistentMemory 0x4000
+ # OEM Reserved 0x4000000000000000
+ # OS Reserved 0x8000000000000000
+ # + # e.g. Reserved+ACPINvs+ACPIReclaim+RuntimeCode+RuntimeData are needed, 0x661 should be used.
+ # + # @Prompt Memory profile memory type. + gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfileMemoryType|0x0|UINT64|0x30001042 + + ## This PCD is to control which drivers need memory profile data.

+ # For example:
+ # One image only (Shell):
+ # Header GUID
+ # {0x04, 0x06, 0x14, 0x00, 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1,
+ # 0x7F, 0xFF, 0x04, 0x00}
+ # Two or more images (Shell + WinNtSimpleFileSystem):
+ # {0x04, 0x06, 0x14, 0x00, 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1,
+ # 0x7F, 0x01, 0x04, 0x00,
+ # 0x04, 0x06, 0x14, 0x00, 0x8B, 0xE1, 0x25, 0x9C, 0xBA, 0x76, 0xDA, 0x43, 0xA1, 0x32, 0xDB, 0xB0, 0x99, 0x7C, 0xEF, 0xEF,
+ # 0x7F, 0xFF, 0x04, 0x00}
+ # @Prompt Memory profile driver path. + gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfileDriverPath|{0x0}|VOID*|0x00001043 + + ## Set image protection policy. The policy is bitwise. + # If a bit is set, the image will be protected by DxeCore if it is aligned. + # The code section becomes read-only, and the data section becomes non-executable. + # If a bit is clear, nothing will be done to image code/data sections.

+ # BIT0 - Image from unknown device.
+ # BIT1 - Image from firmware volume.
+ #
+ # Note: If a bit is cleared, the data section could be still non-executable if + # PcdDxeNxMemoryProtectionPolicy is enabled for EfiLoaderData, EfiBootServicesData + # and/or EfiRuntimeServicesData.
+ #
+ # @Prompt Set image protection policy. + # @ValidRange 0x80000002 | 0x00000000 - 0x0000001F + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x00000002|UINT32|0x00001047 + + ## Set DXE memory protection policy. The policy is bitwise. + # If a bit is set, memory regions of the associated type will be mapped + # non-executable.
+ # If a bit is cleared, nothing will be done to associated type of memory.
+ #
+ # Below is bit mask for this PCD: (Order is same as UEFI spec)
+ # EfiReservedMemoryType 0x0001
+ # EfiLoaderCode 0x0002
+ # EfiLoaderData 0x0004
+ # EfiBootServicesCode 0x0008
+ # EfiBootServicesData 0x0010
+ # EfiRuntimeServicesCode 0x0020
+ # EfiRuntimeServicesData 0x0040
+ # EfiConventionalMemory 0x0080
+ # EfiUnusableMemory 0x0100
+ # EfiACPIReclaimMemory 0x0200
+ # EfiACPIMemoryNVS 0x0400
+ # EfiMemoryMappedIO 0x0800
+ # EfiMemoryMappedIOPortSpace 0x1000
+ # EfiPalCode 0x2000
+ # EfiPersistentMemory 0x4000
+ # OEM Reserved 0x4000000000000000
+ # OS Reserved 0x8000000000000000
+ # + # NOTE: User must NOT set NX protection for EfiLoaderCode / EfiBootServicesCode / EfiRuntimeServicesCode.
+ # User MUST set the same NX protection for EfiBootServicesData and EfiConventionalMemory.
+ # + # e.g. 0x7FD5 can be used for all memory except Code.
+ # e.g. 0x7BD4 can be used for all memory except Code and ACPINVS/Reserved.
+ # + # @Prompt Set DXE memory protection policy. + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0x0000000|UINT64|0x00001048 + + ## PCI Serial Device Info. It is an array of Device, Function, and Power Management + # information that describes the path that contains zero or more PCI to PCI bridges + # followed by a PCI serial device. Each array entry is 4-bytes in length. The + # first byte is the PCI Device Number, then second byte is the PCI Function Number, + # and the last two bytes are the offset to the PCI power management capabilities + # register used to manage the D0-D3 states. If a PCI power management capabilities + # register is not present, then the last two bytes in the offset is set to 0. The + # array is terminated by an array entry with a PCI Device Number of 0xFF. For a + # non-PCI fixed address serial device, such as an ISA serial device, the value is 0xFF. + # @Prompt Pci Serial Device Info + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF}|VOID*|0x00010067 + + ## PCI Serial Parameters. It is an array of VendorID, DeviceID, ClockRate, Offset, + # BarIndex, RegisterStride, ReceiveFifoDepth, TransmitFifoDepth information that + # describes the parameters of special PCI serial devices. + # Each array entry is 24-byte in length. The array is terminated + # by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a + # standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF. + # The C style structure is defined as below:
+ # typedef struct {
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
+ # UINT16 DeviceId; ///< Device ID to match the PCI device.
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz.
+ # UINT64 Offset; ///< The byte offset into to the BAR.
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address.
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ # UINT8 Reserved[2];
+ # } PCI_SERIAL_PARAMETER;
+ # It contains zero or more instances of the above structure.
+ # For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs + # to contain two instances of the above structure, with the VendorId and DeviceId + # equals to the Device ID and Vendor ID of the device; If the PCI device uses the + # first two BARs to support two UARTs, BarIndex of first instance equals to 0 and + # BarIndex of second one equals to 1; If the PCI device uses the first BAR to + # support both UARTs, BarIndex of both instance equals to 0, Offset of first + # instance equals to 0 and Offset of second one equals to a value bigger than or + # equal to 8.
+ # For certain UART whose register needs to be accessed in DWORD aligned address, + # RegisterStride equals to 4. + # @Prompt Pci Serial Parameters + gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0xFF, 0xFF}|VOID*|0x00010071 + + ## Serial Port Extended Transmit FIFO Size. The default is 64 bytes. + # @Prompt Serial Port Extended Transmit FIFO Size in Bytes + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|64|UINT32|0x00010068 + + ## This PCD points to the file name GUID of the BootManagerMenuApp + # Platform can customize the PCD to point to different application for Boot Manager Menu + # @Prompt Boot Manager Menu File + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x0001006b + + ## This PCD points to the formset GUID of the driver health management form + # The form will be popped up by BDS core when there are Configuration Required driver health instances. + # Platform can customize the PCD to point to different formset. + # @Prompt Driver Health Management Form + gEfiMdeModulePkgTokenSpaceGuid.PcdDriverHealthConfigureForm|{ 0xf4, 0xd9, 0x96, 0x42, 0xfc, 0xf6, 0xde, 0x4d, 0x86, 0x85, 0x8c, 0xe2, 0xd7, 0x9d, 0x90, 0xf0 }|VOID*|0x0001006c + + ## The number of bytes between registers in serial device. The default is 1 byte. + # @Prompt Serial Port Register Stride in Bytes + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1|UINT32|0x0001006d + + ## This PCD to include the driver guid of VFR drivers for VarCheckHiiBin generation.

+ # Default is gZeroGuid that means no VFR driver will be parsed for VarCheckHiiBin generation.
+ # If it is set to an all FFs GUID, it means all modules in all FVs will be parsed for VarCheckHiiBin generation.
+ # @Prompt Driver guid array of VFR drivers for VarCheckHiiBin generation. + gEfiMdeModulePkgTokenSpaceGuid.PcdVarCheckVfrDriverGuidArray|{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x3000103A + + ## Indicates which ACPI versions are targeted by the ACPI tables exposed to the OS + # These values are aligned with the definitions in MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h + # BIT 1 - EFI_ACPI_TABLE_VERSION_1_0B.
+ # BIT 2 - EFI_ACPI_TABLE_VERSION_2_0.
+ # BIT 3 - EFI_ACPI_TABLE_VERSION_3_0.
+ # BIT 4 - EFI_ACPI_TABLE_VERSION_4_0.
+ # BIT 5 - EFI_ACPI_TABLE_VERSION_5_0.
+ # @Prompt Exposed ACPI table versions. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x3E|UINT32|0x0001004c + + ## This PCD defines the MAX repair count. + # The default value is 0 that means infinite. + # @Prompt MAX repair count + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxRepairCount|0x00|UINT32|0x00010076 + + ## Status Code for Capsule subclass definitions.

+ # EFI_OEM_SPECIFIC_SUBCLASS_CAPSULE = 0x00810000
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule subclass definitions + # @ValidList 0x80000003 | 0x00810000 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeSubClassCapsule|0x00810000|UINT32|0x00000100 + + ## Status Code for Capsule Process Begin.

+ # EFI_CAPSULE_PROCESS_CAPSULES_BEGIN = (EFI_OEM_SPECIFIC | 0x00000001) = 0x00008001
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule Process Begin + # @ValidList 0x80000003 | 0x00008001 + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleStatusCodeProcessCapsulesBegin|0x00008001|UINT32|0x00000101 + + ## Status Code for Capsule Process End.

+ # EFI_CAPSULE_PROCESS_CAPSULES_END = (EFI_OEM_SPECIFIC | 0x00000002) = 0x00008002
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule Process End + # @ValidList 0x80000003 | 0x00008002 + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleStatusCodeProcessCapsulesEnd|0x00008002|UINT32|0x00000102 + + ## Status Code for Capsule Process Updating Firmware.

+ # EFI_CAPSULE_UPDATING_FIRMWARE = (EFI_OEM_SPECIFIC | 0x00000003) = 0x00008003
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule Process Updating Firmware + # @ValidList 0x80000003 | 0x00008003 + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleStatusCodeUpdatingFirmware|0x00008003|UINT32|0x00000103 + + ## Status Code for Capsule Process Update Firmware Success.

+ # EFI_CAPSULE_UPDATE_FIRMWARE_SUCCESS = (EFI_OEM_SPECIFIC | 0x00000004) = 0x00008004
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule Process Update Firmware Success + # @ValidList 0x80000003 | 0x00008004 + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleStatusCodeUpdateFirmwareSuccess|0x00008004|UINT32|0x00000104 + + ## Status Code for Capsule Process Update Firmware Failed.

+ # EFI_CAPSULE_UPDATE_FIRMWARE_FAILED = (EFI_OEM_SPECIFIC | 0x00000005) = 0x00008005
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule Process Update Firmware Failed + # @ValidList 0x80000003 | 0x00008005 + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleStatusCodeUpdateFirmwareFailed|0x00008005|UINT32|0x00000105 + + ## Status Code for Capsule Resetting System.

+ # EFI_CAPSULE_RESETTING_SYSTEM = (EFI_OEM_SPECIFIC | 0x00000006) = 0x00008006
+ # NOTE: The default value of this PCD may collide with other OEM specific status codes. + # Override the value of this PCD in the platform DSC file as needed. + # @Prompt Status Code for Capsule Resetting System + # @ValidList 0x80000003 | 0x00008006 + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleStatusCodeResettingSystem|0x00008006|UINT32|0x00000106 + + ## CapsuleMax value in capsule report variable. + # @Prompt CapsuleMax value in capsule report variable. + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleMax|0xFFFF|UINT16|0x00000107 + + ## Control which FPDT record format will be used to store the performance entry. + # On TRUE, the string FPDT record will be used to store every performance entry. + # On FALSE, the different FPDT record will be used to store the different performance entries. + # @Prompt String FPDT Record Enable Only + gEfiMdeModulePkgTokenSpaceGuid.PcdEdkiiFpdtStringRecordEnableOnly|FALSE|BOOLEAN|0x00000109 + + ## Indicates the allowable maximum number of Reset Filters, Reset Notifications or Reset Handlers in PEI phase. + # @Prompt Maximum Number of PEI Reset Filters, Reset Notifications or Reset Handlers. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaximumPeiResetNotifies|0x10|UINT32|0x0000010A + + ## Capsule On Disk is to deliver capsules via files on Mass Storage device.

+ # This PCD indicates if the Capsule On Disk is supported.
+ # TRUE - Capsule On Disk is supported.
+ # FALSE - Capsule On Disk is not supported.
+ # If platform does not use this feature, this PCD should be set to FALSE.

+ # Two sulotions to deliver Capsule On Disk:
+ # a) If PcdCapsuleInRamSupport = TRUE, Load Capsule On Disk image out of TCB, and reuse + # Capsule In Ram to deliver capsule.
+ # b) If PcdCapsuleInRamSupport = FALSE, Relocate Capsule On Disk image to RootDir out + # of TCB, and reuse FatPei to load capsules from external storage.
+ # Note:
+ # If Both Capsule In Ram and Capsule On Disk are provisioned at the same time, the Capsule + # On Disk will be bypassed. + # @Prompt Enable Capsule On Disk support. + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE|BOOLEAN|0x0000002d + + ## Maximum permitted encapsulation levels of sections in a firmware volume, + # in the DXE phase. Minimum value is 1. Sections nested more deeply are + # rejected. + # @Prompt Maximum permitted FwVol section nesting depth (exclusive). + gEfiMdeModulePkgTokenSpaceGuid.PcdFwVolDxeMaxEncapsulationDepth|0x10|UINT32|0x00000030 + + ## Indicates the default timeout value for SD/MMC Host Controller operations in microseconds. + # @Prompt SD/MMC Host Controller Operations Timeout (us). + gEfiMdeModulePkgTokenSpaceGuid.PcdSdMmcGenericTimeoutValue|1000000|UINT32|0x00000031 + + ## The Retry Count of AHCI command if there is a failure + # @Prompt The value of Retry Count, Default value is 5. + gEfiMdeModulePkgTokenSpaceGuid.PcdAhciCommandRetryCount|5|UINT32|0x00000032 + +[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## This PCD defines the Console output row. The default value is 25 according to UEFI spec. + # This PCD could be set to 0 then console output would be at max column and max row. + # @Prompt Console output row. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|25|UINT32|0x40000006 + + ## This PCD defines the Console output column. The default value is 80 according to UEFI spec. + # This PCD could be set to 0 then console output would be at max column and max row. + # @Prompt Console output column. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|80|UINT32|0x40000007 + + ## This PCD defines the video horizontal resolution. + # If this PCD is set to 0 then video resolution would be at highest resolution. + # @Prompt Video horizontal resolution. + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800|UINT32|0x40000009 + + ## This PCD defines the video vertical resolution. + # If this PCD is set to 0 then video resolution would be at highest resolution. + # @Prompt Video vertical resolution. + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600|UINT32|0x4000000a + + # The 4 PCDs below are used to specify the video resolution and text mode of text setup. + # To make text setup work in this resolution, PcdVideoHorizontalResolution, PcdVideoVerticalResolution, + # PcdConOutColumn and PcdConOutRow should be created as PcdsDynamic or PcdsDynamicEx in platform DSC file. + # Then BDS setup will update these PCDs defined in MdeModulePkg.dec and reconnect console drivers + # (GraphicsConsole, Terminal, Consplitter) to make the video resolution and text mode work + # for text setup. + + ## Specify the video horizontal resolution of text setup. + # @Prompt Video Horizontal Resolution of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800|UINT32|0x4000000b + + ## Specify the video vertical resolution of text setup. + # @Prompt Video Vertical Resolution of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600|UINT32|0x4000000c + + ## Specify the console output column of text setup. + # @Prompt Console Output Column of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|80|UINT32|0x4000000d + + ## Specify the console output row of text setup. + # @Prompt Console Output Row of Text Setup + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|25|UINT32|0x4000000e + + ## Specify the Boot Discovery Policy settings + # To support configuring from setup page, this PCD should be overridden in DynamicHii type in its platform .dsc: + # gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy|L"BootDiscoveryPolicy"|gBootDiscoveryPolicyMgrFormsetGuid|0 + # @Prompt Boot Discovery Policy + gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy|2|UINT32|0x4000000f + +[PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20|UINT32|0x0001004c + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## UART clock frequency is for the baud rate configuration. + # @Prompt Serial Port Clock Rate. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|1843200|UINT32|0x00010066 + + ## This PCD points to the front page formset GUID + # Compare the FormsetGuid or ClassGuid with this PCD value can detect whether in front page + # @Prompt Front Page Formset. + gEfiMdeModulePkgTokenSpaceGuid.PcdFrontPageFormSetGuid|{ 0xbc, 0x30, 0x0c, 0x9e,0x06, 0x3f, 0xa6, 0x4b, 0x82, 0x88, 0x9, 0x17, 0x9b, 0x85, 0x5d, 0xbe }|VOID*|0x0001006e + + ## Base address of the NV variable range in flash device. + # @Prompt Base address of flash NV variable range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0|UINT32|0x30000001 + + ## Size of the NV variable range. Note that this value should less than or equal to PcdFlashNvStorageFtwSpareSize. + # The root cause is that variable driver will use FTW protocol to reclaim variable region. + # If the length of variable region is larger than FTW spare size, it means the whole variable region can not + # be reflushed through the manner of fault tolerant write. + # @Prompt Size of flash NV variable range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0|UINT32|0x30000002 + + ## Base address of the FTW spare block range in flash device. Note that this value should be block size aligned. + # @Prompt Base address of flash FTW spare block range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0|UINT32|0x30000013 + + ## Size of the FTW spare block range. Note that this value should larger than PcdFlashNvStorageVariableSize and block size aligned. + # The root cause is that variable driver will use FTW protocol to reclaim variable region. + # If the length of variable region is larger than FTW spare size, it means the whole variable region can not + # be reflushed through the manner of fault tolerant write. + # @Prompt Size of flash FTW spare block range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x0|UINT32|0x30000014 + + ## Base address of the FTW working block range in flash device. + # If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this value should be block size aligned. + # @Prompt Base address of flash FTW working block range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0|UINT32|0x30000010 + + ## Size of the FTW working block range. + # If the value is less than one block size, the work space range should not span blocks. + # If the value is larger than one block size, it should be block size aligned. + # @Prompt Size of flash FTW working block range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0|UINT32|0x30000011 + + ## 64-bit Base address of the NV variable range in flash device. + # @Prompt 64-bit Base address of flash NV variable range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0|UINT64|0x80000001 + + ## 64-bit Base address of the FTW spare block range in flash device. Note that this value should be block size aligned. + # @Prompt 64-bit Base address of flash FTW spare block range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0|UINT64|0x80000013 + + ## 64-bit Base address of the FTW working block range in flash device. + # If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this value should be block size aligned. + # @Prompt 64-bit Base address of flash FTW working block range. + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0|UINT64|0x80000010 + + ## Indicates if Variable driver will enable emulated variable NV mode.

+ # If this PCD is configured to dynamic, its value should be set before Variable driver starts to work,
+ # otherwise default value will take effect.
+ # TRUE - An EMU variable NV storage will be allocated or reserved for NV variables.
+ # FALSE - No EMU variable NV storage will be allocated or reserved for NV variables.
+ # @Prompt EMU variable NV mode enable. + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|FALSE|BOOLEAN|0x01100001 + + ## This PCD defines the base address of reserved memory range for EMU variable NV storage. + # A non-ZERO value indicates a valid range reserved with size given by PcdVariableStoreSize. + # @Prompt Base of reserved memory range for EMU variable NV storage. + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0|UINT64|0x40000008 + + ## This PCD defines the times to print hello world string. + # This PCD is a sample to explain UINT32 PCD usage. + # @Prompt HellowWorld print times. + gEfiMdeModulePkgTokenSpaceGuid.PcdHelloWorldPrintTimes|1|UINT32|0x40000005 + + ## This PCD defines the HelloWorld print string. + # This PCD is a sample to explain String typed PCD usage. + # @Prompt HelloWorld print string. + gEfiMdeModulePkgTokenSpaceGuid.PcdHelloWorldPrintString|L"UEFI Hello World!\n"|VOID*|0x40000004 + + ## Indicates the maximum size of the capsule image with a reset flag that the platform can support. + # The default max size is 100MB (0x6400000) for more than one large capsule images. + # @Prompt Max size of populated capsule. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizePopulateCapsule|0x6400000|UINT32|0x0001001e + + ## Indicates the maximum size of the capsule image without a reset flag that the platform can support. + # The default max size is 10MB (0xa00000) for the casule image without reset flag setting. + # @Prompt Max size of non-populated capsule. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0xa00000|UINT32|0x0001001f + + ## Null-terminated Unicode string of the firmware vendor name that is the default name filled into the EFI System Table. + # @Prompt Firmware vendor. + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"EDK II"|VOID*|0x00010050 + + ## Firmware revision that is the default revision filled into the EFI System Table. + # @Prompt Firmware revision. + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|0x00010000|UINT32|0x00010051 + + ## Null-terminated Unicode string that describes the firmware version. + # @Prompt Firmware version string. + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|0x00010052 + + ## Null-terminated Unicode string that contains the date the firmware was released + # @Prompt Firmware release data string. + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L""|VOID*|0x00010053 + + ## PcdStatusCodeMemorySize is used when PcdStatusCodeUseMemory is set to true. + # (PcdStatusCodeMemorySize * KBytes) is the total taken memory size.

+ # The default value in PeiPhase is 1 KBytes.
+ # The default value in DxePhase is 128 KBytes.
+ # @Prompt StatusCode memory size. + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1|UINT16|0x00010054 + + ## Indicates if to reset system when memory type information changes.

+ # TRUE - Resets system when memory type information changes.
+ # FALSE - Does not reset system when memory type information changes.
+ # @Prompt Reset on memory type information change. + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE|BOOLEAN|0x00010056 + + ## Indicates if the BDS supports Platform Recovery.

+ # TRUE - BDS supports Platform Recovery.
+ # FALSE - BDS does not support Platform Recovery.
+ # @Prompt Support Platform Recovery. + gEfiMdeModulePkgTokenSpaceGuid.PcdPlatformRecoverySupport|TRUE|BOOLEAN|0x00010078 + + ## Specify the foreground color for Subtile text in HII Form Browser. The default value is EFI_BLUE. + # Only following values defined in UEFI specification are valid:

+ # 0x00 (EFI_BLACK)
+ # 0x01 (EFI_BLUE)
+ # 0x02 (EFI_GREEN)
+ # 0x03 (EFI_CYAN)
+ # 0x04 (EFI_RED)
+ # 0x05 (EFI_MAGENTA)
+ # 0x06 (EFI_BROWN)
+ # 0x07 (EFI_LIGHTGRAY)
+ # 0x08 (EFI_DARKGRAY)
+ # 0x09 (EFI_LIGHTBLUE)
+ # 0x0A (EFI_LIGHTGREEN)
+ # 0x0B (EFI_LIGHTCYAN)
+ # 0x0C (EFI_LIGHTRED)
+ # 0x0D (EFI_LIGHTMAGENTA)
+ # 0x0E (EFI_YELLOW)
+ # 0x0F (EFI_WHITE)
+ # @Prompt Foreground color for browser subtile. + # @ValidRange 0x80000004 | 0x00 - 0x0F + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x01|UINT8|0x00010057 + + ## Specify the foreground color for prompt and Question value text in HII Form Browser. The default value is EFI_BLACK. + # Only following values defined in UEFI specification are valid:

+ # 0x00 (EFI_BLACK)
+ # 0x01 (EFI_BLUE)
+ # 0x02 (EFI_GREEN)
+ # 0x03 (EFI_CYAN)
+ # 0x04 (EFI_RED)
+ # 0x05 (EFI_MAGENTA)
+ # 0x06 (EFI_BROWN)
+ # 0x07 (EFI_LIGHTGRAY)
+ # 0x08 (EFI_DARKGRAY)
+ # 0x09 (EFI_LIGHTBLUE)
+ # 0x0A (EFI_LIGHTGREEN)
+ # 0x0B (EFI_LIGHTCYAN)
+ # 0x0C (EFI_LIGHTRED)
+ # 0x0D (EFI_LIGHTMAGENTA)
+ # 0x0E (EFI_YELLOW)
+ # 0x0F (EFI_WHITE)
+ # @Prompt Foreground color for browser field. + # @ValidRange 0x80000004 | 0x00 - 0x0F + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x00|UINT8|0x00010058 + + ## Specify the foreground color for highlighted prompt and Question value text in HII Form Browser. + # The default value is EFI_LIGHTGRAY. Only following values defined in UEFI specification are valid:

+ # 0x00 (EFI_BLACK)
+ # 0x01 (EFI_BLUE)
+ # 0x02 (EFI_GREEN)
+ # 0x03 (EFI_CYAN)
+ # 0x04 (EFI_RED)
+ # 0x05 (EFI_MAGENTA)
+ # 0x06 (EFI_BROWN)
+ # 0x07 (EFI_LIGHTGRAY)
+ # 0x08 (EFI_DARKGRAY)
+ # 0x09 (EFI_LIGHTBLUE)
+ # 0x0A (EFI_LIGHTGREEN)
+ # 0x0B (EFI_LIGHTCYAN)
+ # 0x0C (EFI_LIGHTRED)
+ # 0x0D (EFI_LIGHTMAGENTA)
+ # 0x0E (EFI_YELLOW)
+ # 0x0F (EFI_WHITE)
+ # @Prompt Foreground color for highlighted browser field. + # @ValidRange 0x80000004 | 0x00 - 0x0F + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextHighlightColor|0x07|UINT8|0x00010059 + + ## Specify the background color for highlighted prompt and Question value text in HII Form Browser. + # The default value is EFI_BACKGROUND_BLACK. Only following values defined in UEFI specification are valid:

+ # 0x00 (EFI_BACKGROUND_BLACK)
+ # 0x10 (EFI_BACKGROUND_BLUE)
+ # 0x20 (EFI_BACKGROUND_GREEN)
+ # 0x30 (EFI_BACKGROUND_CYAN)
+ # 0x40 (EFI_BACKGROUND_RED)
+ # 0x50 (EFI_BACKGROUND_MAGENTA)
+ # 0x60 (EFI_BACKGROUND_BROWN)
+ # 0x70 (EFI_BACKGROUND_LIGHTGRAY)
+ # @Prompt Background color for highlighted browser field. + # @ValidList 0x80000005 | 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldBackgroundHighlightColor|0x00|UINT8|0x0001005A + + ## Time in second to delay for SATA devices to spin-up for recovery. + # @Prompt SATA spin-up delay time in second for recovery path. + gEfiMdeModulePkgTokenSpaceGuid.PcdSataSpinUpDelayInSecForRecoveryPath|15|UINT16|0x0001005B + + ## This PCD is used to specify memory size with page number for a pre-allocated ACPI reserved memory + # to hold runtime(after SmmReadyToLock) created S3 boot script entries. The default page number is 2. + # When changing the value of this PCD, the platform developer should make sure the memory size is + # large enough to hold the S3 boot script node created in runtime(after SmmReadyToLock) phase. + # @Prompt Reserved page number for S3 Boot Script Runtime Table. + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptRuntimeTableReservePageNumber|0x2|UINT16|0x0001005C + + ## The PCD is used to specify the stack size when capsule IA32 PEI transfers to long mode in PEI phase. + # The default size is 32K. When changing the value of this PCD, the platform developer should + # make sure the memory size is large enough to meet capsule PEI requirement in capsule update path. + # @Prompt Stack size for CapsulePei transfer to long mode. + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsulePeiLongModeStackSize|0x8000|UINT32|0x0001005D + + ## Indicates if 1G page table will be enabled.

+ # TRUE - 1G page table will be enabled.
+ # FALSE - 1G page table will not be enabled.
+ # @Prompt Enable 1G page table support. + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|FALSE|BOOLEAN|0x0001005E + + ## Indicates if the Single Root I/O virtualization is supported.

+ # TRUE - Single Root I/O virtualization is supported.
+ # FALSE - Single Root I/O virtualization is not supported.
+ # @Prompt Enable SRIOV support. + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE|BOOLEAN|0x10000044 + + ## Indicates if the Alternative Routing-ID is supported.

+ # TRUE - Alternative Routing-ID is supported.
+ # FALSE - Alternative Routing-ID is not supported.
+ # @Prompt Enable ARI support. + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE|BOOLEAN|0x10000045 + + ## Indicates if the Multi Root I/O virtualization is supported.

+ # TRUE - Multi Root I/O virtualization is supported.
+ # FALSE - Multi Root I/O virtualization is not supported.
+ # @Prompt Enable MRIOV support. + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE|BOOLEAN|0x10000046 + + ## Single root I/O virtualization virtual function memory BAR alignment.

+ # BITN set indicates 2 of n+12 power
+ # BIT0 set indicates 4KB alignment
+ # BIT1 set indicates 8KB alignment
+ # @Prompt SRIOV system page size. + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1|UINT32|0x10000047 + + ## SMBIOS version. + # @Prompt SMBIOS version. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0303|UINT16|0x00010055 + + ## SMBIOS Docrev field in SMBIOS 3.0 (64-bit) Entry Point Structure. + # @Prompt SMBIOS Docrev field in SMBIOS 3.0 (64-bit) Entry Point Structure. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0|UINT8|0x0001006A + + ## SMBIOS produce method. + # BIT0 set indicates 32-bit entry point and table are produced.
+ # BIT1 set indicates 64-bit entry point and table are produced.
+ # @Prompt The policy to produce SMBIOS entry point and table. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x3|UINT32|0x00010069 + + ## This PCD specifies the additional pad size in FPDT Basic Boot Performance Table for + # the extension FPDT boot records received after EndOfDxe and before ExitBootService. + # @Prompt Pad size for extension FPDT boot records. + gEfiMdeModulePkgTokenSpaceGuid.PcdExtFpdtBootRecordPadSize|0x30000|UINT32|0x0001005F + + ## Indicates if ConIn device are connected on demand.

+ # TRUE - ConIn device are not connected during BDS and ReadKeyStroke/ReadKeyStrokeEx produced + # by Consplitter should be called before any real key read operation.
+ # FALSE - ConIn device may be connected normally during BDS.
+ # @Prompt ConIn connect on demand. + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE|BOOLEAN|0x10000060 + + ## Indicates if the S.M.A.R.T feature of attached ATA hard disks will be enabled.

+ # TRUE - S.M.A.R.T feature of attached ATA hard disks will be enabled.
+ # FALSE - S.M.A.R.T feature of attached ATA hard disks will be default status.
+ # @Prompt Enable ATA S.M.A.R.T feature. + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE|BOOLEAN|0x00010065 + + ## Indicates if full PCI enumeration is disabled.

+ # TRUE - Full PCI enumeration is disabled.
+ # FALSE - Full PCI enumeration is not disabled.
+ # @Prompt Disable full PCI enumeration. + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE|BOOLEAN|0x10000048 + + ## Disk I/O - Number of Data Buffer block. + # Define the size in block of the pre-allocated buffer. It provide better + # performance for large Disk I/O requests. + # @Prompt Disk I/O - Number of Data Buffer block. + gEfiMdeModulePkgTokenSpaceGuid.PcdDiskIoDataBufferBlockNum|64|UINT32|0x30001039 + + ## This PCD specifies the PCI-based UFS host controller mmio base address. + # Define the mmio base address of the pci-based UFS host controller. If there are multiple UFS + # host controllers, their mmio base addresses are calculated one by one from this base address. + # @Prompt Mmio base address of pci-based UFS host controller. + gEfiMdeModulePkgTokenSpaceGuid.PcdUfsPciHostControllerMmioBase|0xd0000000|UINT32|0x10000061 + + ## Specify Max ESRT cache entry number supported for FMP instances + # + # @Prompt Max FMP ESRT entry number to be synced & cached in repository. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxFmpEsrtCacheNum|32|UINT32|0x0000006b + + ## Specify Max ESRT cache entry number supported for Non FMP instances + # + # @Prompt Max Non-FMP ESRT entry number to be cached in repository. + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxNonFmpEsrtCacheNum|32|UINT32|0x0000006c + + ## Specify of Capsule Flag defined by CapsuleGuid to request system reboot after capsule process + # + # @Prompt Flag to request system reboot after processing capsule. + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemRebootAfterCapsuleProcessFlag|0x0001|UINT16|0x0000006d + + ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to follow ACPI specification. + # @Prompt Default OEM ID for ACPI table creation. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 + + ## Default OEM Table ID for ACPI table creation, it is "EDK2 ". + # According to ACPI specification, this field is particularly useful when + # defining a definition block to distinguish definition block functions. + # The OEM assigns each dissimilar table a new OEM Table ID. + # This PCD is ignored for definition block. + # @Prompt Default OEM Table ID for ACPI table creation. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x30001035 + + ## Default OEM Revision for ACPI table creation. + # According to ACPI specification, for LoadTable() opcode, the OS can also + # check the OEM Table ID and Revision ID against a database for a newer + # revision Definition Block of the same OEM Table ID and load it instead. + # This PCD is ignored for definition block. + # @Prompt Default OEM Revision for ACPI table creation. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001036 + + ## Default Creator ID for ACPI table creation. + # According to ACPI specification, for tables containing Definition Blocks, + # this is the ID for the ASL Compiler. + # This PCD is ignored for definition block. + # @Prompt Default Creator ID for ACPI table creation. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037 + + ## Default Creator Revision for ACPI table creation. + # According to ACPI specification, for tables containing Definition Blocks, + # this is the revision for the ASL Compiler. + # This PCD is ignored for definition block. + # @Prompt Default Creator Revision for ACPI table creation. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038 + + ## Indicates if to set NX for stack.

+ # For the DxeIpl and the DxeCore are both X64, set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE.
+ # For the DxeIpl and the DxeCore are both IA32 (PcdDxeIplSwitchToLongMode is FALSE), set NX for stack feature also require + # IA32 PAE is supported and Execute Disable Bit is available.
+ #
+ # TRUE - Set NX for stack.
+ # FALSE - Do nothing for stack.
+ #
+ # Note: If this PCD is set to FALSE, NX could be still applied to stack due to PcdDxeNxMemoryProtectionPolicy enabled for + # EfiBootServicesData.
+ #
+ # @Prompt Set NX for stack. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|FALSE|BOOLEAN|0x0001006f + + ## This PCD specifies the PCI-based SD/MMC host controller mmio base address. + # Define the mmio base address of the pci-based SD/MMC host controller. If there are multiple SD/MMC + # host controllers, their mmio base addresses are calculated one by one from this base address. + # @Prompt Mmio base address of pci-based SD/MMC host controller. + gEfiMdeModulePkgTokenSpaceGuid.PcdSdMmcPciHostControllerMmioBase|0xd0000000|UINT32|0x30001043 + + ## Indicates if ACPI S3 will be enabled.

+ # TRUE - ACPI S3 will be enabled.
+ # FALSE - ACPI S3 will be disabled.
+ # @Prompt ACPI S3 Enable. + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|TRUE|BOOLEAN|0x01100000 + + ## Specify memory size for boot script executor stack usage in S3 phase. + # The default size 32K. When changing the value make sure the memory size is large enough + # to meet boot script executor requirement in the S3 phase. + # @Prompt Reserved S3 Boot Script Stack ACPI Memory Size + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptStackSize|0x8000|UINT32|0x02000000 + + ## Indicates if to use the optimized timing for best PS2 detection performance. + # Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.

+ # TRUE - Use the optimized timing for best PS2 detection performance.
+ # FALSE - Use the normal timing to detect PS2.
+ # @Prompt Enable fast PS2 detection + gEfiMdeModulePkgTokenSpaceGuid.PcdFastPS2Detection|FALSE|BOOLEAN|0x30001044 + + ## This is recover file name in PEI phase. + # The file must be in the root directory. + # The file name must be the 8.3 format. + # The PCD data must be in UNICODE format. + # @Prompt Recover file name in PEI phase + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryFileName|L"FVMAIN.FV"|VOID*|0x30001045 + + ## This is Capsule Temp Relocation file name in PEI phase. + # The file must be in the root directory. + # The file name must be the 8.3 format. + # The PCD data must be in UNICODE format. + # CapsuleOnDiskLoadPei PEI module will set value of this PCD to PcdRecoveryFileName, then + # leverage recovery to get Capsule On Disk Temp Relocation file. + # Note: The file name must be shorter than PcdRecoveryFileName, otherwise CapsuleOnDiskLoadPei + # PEI module will fail to get Capsule On Disk Temp Relocation file. + # @Prompt Capsule On Disk Temp Relocation file name in PEI phase + gEfiMdeModulePkgTokenSpaceGuid.PcdCoDRelocationFileName|L"Cod.tmp"|VOID*|0x30001048 + + ## This PCD hold a list GUIDs for the ImageTypeId to indicate the + # FMP capsule is a system FMP. + # @Prompt A list of system FMP ImageTypeId GUIDs + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x0}|VOID*|0x30001046 + + ## This PCD holds the address mask for page table entries when memory encryption is + # enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. + # This mask should be applied when creating 1:1 virtual to physical mapping tables. + # @Prompt The address mask when memory encryption is enabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0|UINT64|0x30001047 + + ## Indicates if 5-Level Paging will be enabled in long mode. 5-Level Paging will not be enabled + # when the PCD is TRUE but CPU doesn't support 5-Level Paging. + # TRUE - 5-Level Paging will be enabled.
+ # FALSE - 5-Level Paging will not be enabled.
+ # @Prompt Enable 5-Level Paging support in long mode. + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable|FALSE|BOOLEAN|0x0001105F + + ## Capsule In Ram is to use memory to deliver the capsules that will be processed after system + # reset.

+ # This PCD indicates if the Capsule In Ram is supported.
+ # TRUE - Capsule In Ram is supported.
+ # FALSE - Capsule In Ram is not supported. + # @Prompt Enable Capsule In Ram support. + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleInRamSupport|TRUE|BOOLEAN|0x0000002e + + ## Full device path of platform specific device to store Capsule On Disk temp relocation file.
+ # If this PCD is set, Capsule On Disk temp relocation file will be stored in the device specified + # by this PCD, instead of the EFI System Partition that stores capsule image file. + # @Prompt Capsule On Disk relocation device path. + gEfiMdeModulePkgTokenSpaceGuid.PcdCodRelocationDevPath|{0xFF}|VOID*|0x0000002f + + ## Indicates which TCG Platform Firmware Profile revision the EDKII firmware follows. + # The revision number is defined in MdePkg/Include/IndustryStandard/UefiTcgPlatform.h + # 0: This is for compatiblity support. + # 105: This is the first revision to support 800-155 is related event, such as + # EV_EFI_PLATFORM_FIRMWARE_BLOB2 and EV_EFI_HANDOFF_TABLES2. + # @Prompt TCG Platform Firmware Profile revision. + gEfiMdeModulePkgTokenSpaceGuid.PcdTcgPfpMeasurementRevision|0|UINT32|0x00010077 + + ## Indicates if StatusCode is reported via Serial port.

+ # TRUE - Reports StatusCode via Serial port.
+ # FALSE - Does not report StatusCode via Serial port.
+ # @Prompt Enable StatusCode via Serial port. + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE|BOOLEAN|0x00010022 + + ## Indicates if StatusCode is stored in memory. + # The memory is boot time memory in PEI Phase and is runtime memory in DXE Phase.

+ # TRUE - Stores StatusCode in memory.
+ # FALSE - Does not store StatusCode in memory.
+ # @Prompt Enable StatusCode via memory. + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOLEAN|0x00010023 + + ## Indicates if the PCIe Resizable BAR Capability Supported.

+ # TRUE - PCIe Resizable BAR Capability is supported.
+ # FALSE - PCIe Resizable BAR Capability is not supported.
+ # @Prompt Enable PCIe Resizable BAR Capability support. + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|FALSE|BOOLEAN|0x10000024 + + ## This PCD holds the shared bit mask for page table entries when Tdx is enabled. + # @Prompt The shared bit mask when Intel Tdx is enabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0|UINT64|0x10000025 + + ## Indicates if the Usb Network rate limiting Supported.

+ # TRUE - Usb Network rate limiting is supported.
+ # FALSE - Usb Network rate limiting is not supported.
+ # @Prompt Enable Usb Network rate limiting support. + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableUsbNetworkRateLimiting|FALSE|BOOLEAN|0x10000026 + + ## The rate limiting Credit value is check in rate limiter event. + # It is to control the RateLimitingCreditCount max value. + # @Prompt The value is use for Usb Network rate limiting supported. + gEfiMdeModulePkgTokenSpaceGuid.PcdUsbNetworkRateLimitingCredit|10|UINT32|0x10000027 + + ## The value of rate limiter event for timeout check. Default value is 100(unit 1ms). + # @Prompt The value is use for Usb Network rate limiting supported. + gEfiMdeModulePkgTokenSpaceGuid.PcdUsbNetworkRateLimitingFactor|100|UINT32|0x10000028 + +[PcdsPatchableInModule] + ## Specify memory size with page number for PEI code when + # Loading Module at Fixed Address feature is enabled. + # The value will be set by the build tool. + # @Prompt LMFA PEI code page number. + # @ValidList 0x80000001 | 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadFixAddressPeiCodePageNumber|0|UINT32|0x00000029 + + ## Specify memory size with page number for DXE boot time code when + # Loading Module at Fixed Address feature is enabled. + # The value will be set by the build tool. + # @Prompt LMFA DXE boot code page number. + # @ValidList 0x80000001 | 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadFixAddressBootTimeCodePageNumber|0|UINT32|0x0000002a + + ## Specify memory size with page number for DXE runtime code when + # Loading Module at Fixed Address feature is enabled. + # The value will be set by the build tool. + # @Prompt LMFA DXE runtime code page number. + # @ValidList 0x80000001 | 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadFixAddressRuntimeCodePageNumber|0|UINT32|0x0000002b + + ## Specify memory size with page number for SMM code when + # Loading Module at Fixed Address feature is enabled. + # The value will be set by the build tool. + # @Prompt LMFA SMM code page number. + # @ValidList 0x80000001 | 0 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadFixAddressSmmCodePageNumber|0|UINT32|0x0000002c + +[PcdsDynamic, PcdsDynamicEx] + ## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Data pointer. + # @ValidList 0x80000001 | 0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0|UINT64|0x00030000 + + ## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library + # instance which records the S3 boot script table start address, length, etc. To introduce this PCD is + # only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the + # default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library. + # @Prompt S3 Boot Script Table Private Smm Data pointer. + # @ValidList 0x80000001 | 0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0x0|UINT64|0x00030001 + + ## This dynamic PCD holds the information if there is any test key used by the platform. + # @Prompt If there is any test key used by the platform. + gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed|FALSE|BOOLEAN|0x00030003 + + ## This dynamic PCD holds the base address of the Guest-Hypervisor Communication Block (GHCB) pool allocation. + # @Prompt GHCB Pool Base Address + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0|UINT64|0x00030007 + + ## This dynamic PCD holds the total size of the Guest-Hypervisor Communication Block (GHCB) pool allocation. + # The amount of memory allocated for GHCBs is dependent on the number of APs. + # @Prompt GHCB Pool Size + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008 + +[PcdsDynamicEx] + ## This dynamic PCD enables the default variable setting. + # Its value is the default store ID value. The default value is zero as Standard default. + # When its value is set in PEI, it will trig the default setting to be applied as the default EFI variable. + # @Prompt NV Storage DefaultId + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNvStoreDefaultId|0x0|UINT16|0x00030004 + + ## This dynamic PCD holds the DynamicHii PCD value. Its value is the auto generated. + # @Prompt NV Storage Default Value Buffer + gEfiMdeModulePkgTokenSpaceGuid.PcdNvStoreDefaultValueBuffer|{0x0}|VOID*|0x00030005 + + ## VPD type PCD allows a developer to point to an absolute physical address PcdVpdBaseAddress64 + # to store PCD value. It will be DynamicExDefault only. + # It is used to set VPD region base address. So, it can't be DynamicExVpd PCD. Its value is + # required to be accessed in PcdDxe driver entry point. So, its value must be set in PEI phase. + # It can't depend on EFI variable service, and can't be DynamicExHii PCD. + # @Prompt 64bit VPD base address. + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64|0x0|UINT64|0x00030006 + +[UserExtensions.TianoCore."ExtraFiles"] + MdeModulePkgExtra.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/MdeModulePkg.dsc b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/MdeModulePkg.dsc new file mode 100644 index 0000000000000000000000000000000000000000..94088a0e7b13f76923cdb021398b511d964b5525 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/MdeModulePkg.dsc @@ -0,0 +1,541 @@ +## @file +# EFI/PI Reference Module Package for All Architectures +# +# (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) Microsoft Corporation. +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + PLATFORM_NAME = MdeModule + PLATFORM_GUID = 587CE499-6CBE-43cd-94E2-186218569478 + PLATFORM_VERSION = 0.98 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/MdeModule + SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses] + # + # Entry point + # + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + # + # UEFI & PI + # + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + # + # Generic Modules + # + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf + # + # Misc + # + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf + PlatformBootManagerLib|MdeModulePkg/Library/PlatformBootManagerLibNull/PlatformBootManagerLibNull.inf + PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridgeLibNull.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.inf + + FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLibGraphics/DisplayUpdateProgressLibGraphics.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf + IpmiCommandLib|MdeModulePkg/Library/BaseIpmiCommandLibNull/BaseIpmiCommandLibNull.inf + SpiHcPlatformLib|MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.inf +[LibraryClasses.EBC.PEIM] + IoLib|MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + +[LibraryClasses.common.DXE_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + +[LibraryClasses.common.SMM_CORE] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf + SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf + SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + DebugLib|MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +[LibraryClasses.common.MM_STANDALONE] + HobLib|MdeModulePkg/Library/BaseHobLibNull/BaseHobLibNull.inf + MemoryAllocationLib|MdeModulePkg/Library/BaseMemoryAllocationLibNull/BaseMemoryAllocationLibNull.inf + StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf + MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxStandaloneMmLib.inf + MemLib|StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + + # + # It is not possible to prevent ARM compiler calls to generic intrinsic functions. + # This library provides the instrinsic functions generated by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # + # Since software stack checking may be heuristically enabled by the compiler + # include BaseStackCheckLib unconditionally. + # + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[LibraryClasses.EBC, LibraryClasses.RISCV64, LibraryClasses.LOONGARCH64] + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + +[PcdsFeatureFlag] + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathFromText|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathToText|FALSE + +[PcdsFixedAtBuild] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizePopulateCapsule|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|28 + +[PcdsDynamicExDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryFileName|L"FVMAIN.FV" + +[Components] + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + MdeModulePkg/Application/DumpDynPcd/DumpDynPcd.inf + MdeModulePkg/Application/MemoryProfileInfo/MemoryProfileInfo.inf + + MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + MdeModulePkg/Logo/Logo.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.inf + MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridgeLibNull.inf + MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf + MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + MdeModulePkg/Library/BaseHobLibNull/BaseHobLibNull.inf + MdeModulePkg/Library/BaseMemoryAllocationLibNull/BaseMemoryAllocationLibNull.inf + MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.inf + + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupportDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.inf + MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.inf + MdeModulePkg/Bus/Sd/SdBlockIoPei/SdBlockIoPei.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.inf + MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf + MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.inf + MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsBlockIoPei.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/UhciPei/UhciPei.inf + MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf + MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf + MdeModulePkg/Bus/Pci/IdeBusPei/IdeBusPei.inf + MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf + MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AhciPei/AhciPei.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcNcm/UsbCdcNcm.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbRndis/UsbRndis.inf + MdeModulePkg/Bus/I2c/I2cDxe/I2cBusDxe.inf + MdeModulePkg/Bus/I2c/I2cDxe/I2cHostDxe.inf + MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf + MdeModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf + MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpDxe.inf + MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf + MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf + MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf + MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + MdeModulePkg/Library/UefiMemoryAllocationProfileLib/UefiMemoryAllocationProfileLib.inf + MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationProfileLib.inf + MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.inf + MdeModulePkg/Library/DxePrintLibPrint2Protocol/DxePrintLibPrint2Protocol.inf + MdeModulePkg/Library/PeiCrc32GuidedSectionExtractLib/PeiCrc32GuidedSectionExtractLib.inf + MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.inf + MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + MdeModulePkg/Library/ResetUtilityLib/ResetUtilityLib.inf + MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf + MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf + MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSystemLib.inf + MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + MdeModulePkg/Library/DxeDebugPrintErrorLevelLib/DxeDebugPrintErrorLevelLib.inf + MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + MdeModulePkg/Library/PeiDebugPrintHobLib/PeiDebugPrintHobLib.inf + MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf + MdeModulePkg/Library/PlatformHookLibSerialPortPpi/PlatformHookLibSerialPortPpi.inf + MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + MdeModulePkg/Library/PeiDebugLibDebugPpi/PeiDebugLibDebugPpi.inf + MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + MdeModulePkg/Library/PlatformBootManagerLibNull/PlatformBootManagerLibNull.inf + MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf + MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf + MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLibStandaloneMm.inf + MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + MdeModulePkg/Library/VarCheckPcdLib/VarCheckPcdLib.inf + MdeModulePkg/Library/PlatformVarCleanupLib/PlatformVarCleanupLib.inf + MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + MdeModulePkg/Library/DxeFileExplorerProtocol/DxeFileExplorerProtocol.inf + MdeModulePkg/Library/BaseIpmiLibNull/BaseIpmiLibNull.inf + MdeModulePkg/Library/DxeIpmiLibIpmiProtocol/DxeIpmiLibIpmiProtocol.inf + MdeModulePkg/Library/PeiIpmiLibIpmiPpi/PeiIpmiLibIpmiPpi.inf + MdeModulePkg/Library/SmmIpmiLibSmmIpmiProtocol/SmmIpmiLibSmmIpmiProtocol.inf + MdeModulePkg/Library/BaseIpmiCommandLibNull/BaseIpmiCommandLibNull.inf + MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf + MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf + MdeModulePkg/Library/DisplayUpdateProgressLibGraphics/DisplayUpdateProgressLibGraphics.inf + MdeModulePkg/Library/DisplayUpdateProgressLibText/DisplayUpdateProgressLibText.inf + MdeModulePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf + + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + MdeModulePkg/Application/UiApp/UiApp.inf{ + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.inf + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + MdeModulePkg/Universal/CapsuleOnDiskLoadPei/CapsuleOnDiskLoadPei.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/DebugPortDxe/DebugPortDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf + MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf { + + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf + } + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf { + + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf + } + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf + MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf + + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Application/VariableInfo/VariableInfo.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Universal/Variable/MmVariablePei/MmVariablePei.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/TimestampDxe/TimestampDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/HiiResourcesSampleDxe/HiiResourcesSampleDxe.inf + MdeModulePkg/Universal/LegacyRegion2Dxe/LegacyRegion2Dxe.inf + + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf { + + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + } + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/SectionExtractionPei/SectionExtractionPei.inf { + + NULL|MdeModulePkg/Library/PeiCrc32GuidedSectionExtractLib/PeiCrc32GuidedSectionExtractLib.inf + } + + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + + MdeModulePkg/Universal/FileExplorerDxe/FileExplorerDxe.inf { + + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + } + + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/LoadFileOnFv2/LoadFileOnFv2.inf + + MdeModulePkg/Universal/DebugServicePei/DebugServicePei.inf + + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf + MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf + MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf + MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf + MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf + +[Components.IA32, Components.X64, Components.AARCH64] + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + MdeModulePkg/Universal/EbcDxe/EbcDebugger.inf + MdeModulePkg/Universal/EbcDxe/EbcDebuggerConfig.inf + +[Components.IA32, Components.X64, Components.ARM, Components.AARCH64] + MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf + MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + +!if $(TOOL_CHAIN_TAG) != "XCODE5" + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteStandaloneMm.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableStandaloneMm.inf +!endif + +[Components.IA32, Components.X64] + MdeModulePkg/Universal/DebugSupportDxe/DebugSupportDxe.inf + MdeModulePkg/Application/SmiHandlerProfileInfo/SmiHandlerProfileInfo.inf + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + NULL|MdeModulePkg/Library/VarCheckPcdLib/VarCheckPcdLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + NULL|MdeModulePkg/Library/VarCheckPcdLib/VarCheckPcdLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf + MdeModulePkg/Library/SmmReportStatusCodeLib/StandaloneMmReportStatusCodeLib.inf + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerStandaloneMm.inf + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterStandaloneMm.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + MdeModulePkg/Library/SmmMemoryAllocationProfileLib/SmmMemoryAllocationProfileLib.inf + MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationProfileLib.inf + MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf + MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.inf + MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.inf + MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf + MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf + MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf + MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxStandaloneMmLib.inf + MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf + MdeModulePkg/Library/SmmSmiHandlerProfileLib/SmmSmiHandlerProfileLib.inf + MdeModulePkg/Library/SmmSmiHandlerProfileLib/StandaloneMmSmiHandlerProfileLib.inf + MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaArchCustomDecompressLib.inf + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + MdeModulePkg/Universal/Acpi/SmmS3SaveState/SmmS3SaveState.inf + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceStandaloneMm.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + MdeModulePkg/Universal/RegularExpressionDxe/RegularExpressionDxe.inf + MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + MdeModulePkg/Library/TraceHubDebugSysTLib/BaseTraceHubDebugSysTLib.inf + MdeModulePkg/Library/TraceHubDebugSysTLib/PeiTraceHubDebugSysTLib.inf + MdeModulePkg/Library/TraceHubDebugSysTLib/DxeSmmTraceHubDebugSysTLib.inf + MdeModulePkg/Library/BaseSpiHcPlatformLibNull/BaseSpiHcPlatformLibNull.inf + +[Components.X64] + MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf + +[BuildOptions] + diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Universal/DisplayEngineDxe/InputHandler.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Universal/DisplayEngineDxe/InputHandler.c new file mode 100644 index 0000000000000000000000000000000000000000..91db87eb540dc3bfb3780ee38ccac3c39e9ef2af --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Universal/DisplayEngineDxe/InputHandler.c @@ -0,0 +1,1735 @@ +/** @file +Implementation for handling user input from the User Interfaces. + +Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "FormDisplay.h" + +/** + Get maximum and minimum info from this opcode. + + @param OpCode Pointer to the current input opcode. + @param Minimum The minimum size info for this opcode. + @param Maximum The maximum size info for this opcode. + +**/ +VOID +GetFieldFromOp ( + IN EFI_IFR_OP_HEADER *OpCode, + OUT UINTN *Minimum, + OUT UINTN *Maximum + ) +{ + EFI_IFR_STRING *StringOp; + EFI_IFR_PASSWORD *PasswordOp; + + if (OpCode->OpCode == EFI_IFR_STRING_OP) { + StringOp = (EFI_IFR_STRING *)OpCode; + *Minimum = StringOp->MinSize; + *Maximum = StringOp->MaxSize; + } else if (OpCode->OpCode == EFI_IFR_PASSWORD_OP) { + PasswordOp = (EFI_IFR_PASSWORD *)OpCode; + *Minimum = PasswordOp->MinSize; + *Maximum = PasswordOp->MaxSize; + } else { + *Minimum = 0; + *Maximum = 0; + } +} + +/** + Get string or password input from user. + + @param MenuOption Pointer to the current input menu. + @param Prompt The prompt string shown on popup window. + @param StringPtr Old user input and destination for use input string. + + @retval EFI_SUCCESS If string input is read successfully + @retval EFI_DEVICE_ERROR If operation fails + +**/ +EFI_STATUS +ReadString ( + IN UI_MENU_OPTION *MenuOption, + IN CHAR16 *Prompt, + IN OUT CHAR16 *StringPtr + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Key; + CHAR16 NullCharacter; + UINTN ScreenSize; + CHAR16 Space[2]; + CHAR16 KeyPad[2]; + CHAR16 *TempString; + CHAR16 *BufferedString; + UINTN Index; + UINTN Index2; + UINTN Count; + UINTN Start; + UINTN Top; + UINTN DimensionsWidth; + UINTN DimensionsHeight; + UINTN CurrentCursor; + BOOLEAN CursorVisible; + UINTN Minimum; + UINTN Maximum; + FORM_DISPLAY_ENGINE_STATEMENT *Question; + BOOLEAN IsPassword; + UINTN MaxLen; + + DimensionsWidth = gStatementDimensions.RightColumn - gStatementDimensions.LeftColumn; + DimensionsHeight = gStatementDimensions.BottomRow - gStatementDimensions.TopRow; + + NullCharacter = CHAR_NULL; + ScreenSize = GetStringWidth (Prompt) / sizeof (CHAR16); + Space[0] = L' '; + Space[1] = CHAR_NULL; + + Question = MenuOption->ThisTag; + GetFieldFromOp (Question->OpCode, &Minimum, &Maximum); + + if (Question->OpCode->OpCode == EFI_IFR_PASSWORD_OP) { + IsPassword = TRUE; + } else { + IsPassword = FALSE; + } + + MaxLen = Maximum + 1; + TempString = AllocateZeroPool (MaxLen * sizeof (CHAR16)); + ASSERT (TempString); + + if (ScreenSize < (Maximum + 1)) { + ScreenSize = Maximum + 1; + } + + if ((ScreenSize + 2) > DimensionsWidth) { + ScreenSize = DimensionsWidth - 2; + } + + BufferedString = AllocateZeroPool (ScreenSize * 2); + ASSERT (BufferedString); + + Start = (DimensionsWidth - ScreenSize - 2) / 2 + gStatementDimensions.LeftColumn + 1; + Top = ((DimensionsHeight - 6) / 2) + gStatementDimensions.TopRow - 1; + + // + // Display prompt for string + // + // CreateDialog (NULL, "", Prompt, Space, "", NULL); + CreateMultiStringPopUp (ScreenSize, 4, &NullCharacter, Prompt, Space, &NullCharacter); + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_BLACK, EFI_LIGHTGRAY)); + + CursorVisible = gST->ConOut->Mode->CursorVisible; + gST->ConOut->EnableCursor (gST->ConOut, TRUE); + + CurrentCursor = GetStringWidth (StringPtr) / 2 - 1; + if (CurrentCursor != 0) { + // + // Show the string which has beed saved before. + // + SetUnicodeMem (BufferedString, ScreenSize - 1, L' '); + PrintStringAt (Start + 1, Top + 3, BufferedString); + + if ((GetStringWidth (StringPtr) / 2) > (DimensionsWidth - 2)) { + Index = (GetStringWidth (StringPtr) / 2) - DimensionsWidth + 2; + } else { + Index = 0; + } + + if (IsPassword) { + gST->ConOut->SetCursorPosition (gST->ConOut, Start + 1, Top + 3); + } + + for (Count = 0; Index + 1 < GetStringWidth (StringPtr) / 2; Index++, Count++) { + BufferedString[Count] = StringPtr[Index]; + + if (IsPassword) { + PrintCharAt ((UINTN)-1, (UINTN)-1, L'*'); + } + } + + if (!IsPassword) { + PrintStringAt (Start + 1, Top + 3, BufferedString); + } + + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK)); + gST->ConOut->SetCursorPosition (gST->ConOut, Start + GetStringWidth (StringPtr) / 2, Top + 3); + } + + do { + Status = WaitForKeyStroke (&Key); + ASSERT_EFI_ERROR (Status); + + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_BLACK, EFI_LIGHTGRAY)); + switch (Key.UnicodeChar) { + case CHAR_NULL: + switch (Key.ScanCode) { + case SCAN_LEFT: + if (CurrentCursor > 0) { + CurrentCursor--; + } + + break; + + case SCAN_RIGHT: + if (CurrentCursor < (GetStringWidth (StringPtr) / 2 - 1)) { + CurrentCursor++; + } + + break; + + case SCAN_ESC: + FreePool (TempString); + FreePool (BufferedString); + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK)); + gST->ConOut->EnableCursor (gST->ConOut, CursorVisible); + return EFI_DEVICE_ERROR; + + case SCAN_DELETE: + for (Index = CurrentCursor; StringPtr[Index] != CHAR_NULL; Index++) { + StringPtr[Index] = StringPtr[Index + 1]; + PrintCharAt (Start + Index + 1, Top + 3, IsPassword && StringPtr[Index] != CHAR_NULL ? L'*' : StringPtr[Index]); + } + + break; + + default: + break; + } + + break; + + case CHAR_CARRIAGE_RETURN: + if (GetStringWidth (StringPtr) >= ((Minimum + 1) * sizeof (CHAR16))) { + FreePool (TempString); + FreePool (BufferedString); + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK)); + gST->ConOut->EnableCursor (gST->ConOut, CursorVisible); + return EFI_SUCCESS; + } else { + // + // Simply create a popup to tell the user that they had typed in too few characters. + // To save code space, we can then treat this as an error and return back to the menu. + // + do { + CreateDialog (&Key, &NullCharacter, gMiniString, gPressEnter, &NullCharacter, NULL); + } while (Key.UnicodeChar != CHAR_CARRIAGE_RETURN); + + FreePool (TempString); + FreePool (BufferedString); + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK)); + gST->ConOut->EnableCursor (gST->ConOut, CursorVisible); + return EFI_DEVICE_ERROR; + } + + case CHAR_BACKSPACE: + if ((StringPtr[0] != CHAR_NULL) && (CurrentCursor != 0)) { + for (Index = 0; Index < CurrentCursor - 1; Index++) { + TempString[Index] = StringPtr[Index]; + } + + Count = GetStringWidth (StringPtr) / 2 - 1; + if (Count >= CurrentCursor) { + for (Index = CurrentCursor - 1, Index2 = CurrentCursor; Index2 < Count; Index++, Index2++) { + TempString[Index] = StringPtr[Index2]; + } + + TempString[Index] = CHAR_NULL; + } + + // + // Effectively truncate string by 1 character + // + StrCpyS (StringPtr, MaxLen, TempString); + CurrentCursor--; + } + + default: + // + // If it is the beginning of the string, don't worry about checking maximum limits + // + if ((StringPtr[0] == CHAR_NULL) && (Key.UnicodeChar != CHAR_BACKSPACE)) { + StrnCpyS (StringPtr, MaxLen, &Key.UnicodeChar, 1); + CurrentCursor++; + } else if ((GetStringWidth (StringPtr) < ((Maximum + 1) * sizeof (CHAR16))) && (Key.UnicodeChar != CHAR_BACKSPACE)) { + KeyPad[0] = Key.UnicodeChar; + KeyPad[1] = CHAR_NULL; + Count = GetStringWidth (StringPtr) / 2 - 1; + if (CurrentCursor < Count) { + for (Index = 0; Index < CurrentCursor; Index++) { + TempString[Index] = StringPtr[Index]; + } + + TempString[Index] = CHAR_NULL; + StrCatS (TempString, MaxLen, KeyPad); + StrCatS (TempString, MaxLen, StringPtr + CurrentCursor); + StrCpyS (StringPtr, MaxLen, TempString); + } else { + StrCatS (StringPtr, MaxLen, KeyPad); + } + + CurrentCursor++; + } + + // + // If the width of the input string is now larger than the screen, we nee to + // adjust the index to start printing portions of the string + // + SetUnicodeMem (BufferedString, ScreenSize - 1, L' '); + PrintStringAt (Start + 1, Top + 3, BufferedString); + + if ((GetStringWidth (StringPtr) / 2) > (DimensionsWidth - 2)) { + Index = (GetStringWidth (StringPtr) / 2) - DimensionsWidth + 2; + } else { + Index = 0; + } + + if (IsPassword) { + gST->ConOut->SetCursorPosition (gST->ConOut, Start + 1, Top + 3); + } + + for (Count = 0; Index + 1 < GetStringWidth (StringPtr) / 2; Index++, Count++) { + BufferedString[Count] = StringPtr[Index]; + + if (IsPassword) { + PrintCharAt ((UINTN)-1, (UINTN)-1, L'*'); + } + } + + if (!IsPassword) { + PrintStringAt (Start + 1, Top + 3, BufferedString); + } + + break; + } + + gST->ConOut->SetAttribute (gST->ConOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK)); + gST->ConOut->SetCursorPosition (gST->ConOut, Start + CurrentCursor + 1, Top + 3); + } while (TRUE); +} + +/** + Adjust the value to the correct one. Rules follow the sample: + like: Year change: 2012.02.29 -> 2013.02.29 -> 2013.02.01 + Month change: 2013.03.29 -> 2013.02.29 -> 2013.02.28 + + @param QuestionValue Pointer to current question. + @param Sequence The sequence of the field in the question. +**/ +VOID +AdjustQuestionValue ( + IN EFI_HII_VALUE *QuestionValue, + IN UINT8 Sequence + ) +{ + UINT8 Month; + UINT16 Year; + UINT8 Maximum; + UINT8 Minimum; + + Month = QuestionValue->Value.date.Month; + Year = QuestionValue->Value.date.Year; + Minimum = 1; + + switch (Month) { + case 2: + if (((Year % 4) == 0) && (((Year % 100) != 0) || ((Year % 400) == 0))) { + Maximum = 29; + } else { + Maximum = 28; + } + + break; + case 4: + case 6: + case 9: + case 11: + Maximum = 30; + break; + default: + Maximum = 31; + break; + } + + // + // Change the month area. + // + if (Sequence == 0) { + if (QuestionValue->Value.date.Day > Maximum) { + QuestionValue->Value.date.Day = Maximum; + } + } + + // + // Change the Year area. + // + if (Sequence == 2) { + if (QuestionValue->Value.date.Day > Maximum) { + QuestionValue->Value.date.Day = Minimum; + } + } +} + +/** + Get field info from numeric opcode. + + @param OpCode Pointer to the current input opcode. + @param IntInput Whether question shows with EFI_IFR_DISPLAY_INT_DEC type. + @param QuestionValue Input question value, with EFI_HII_VALUE type. + @param Value Return question value, always return UINT64 type. + @param Minimum The minimum size info for this opcode. + @param Maximum The maximum size info for this opcode. + @param Step The step size info for this opcode. + @param StorageWidth The storage width info for this opcode. + +**/ +VOID +GetValueFromNum ( + IN EFI_IFR_OP_HEADER *OpCode, + IN BOOLEAN IntInput, + IN EFI_HII_VALUE *QuestionValue, + OUT UINT64 *Value, + OUT UINT64 *Minimum, + OUT UINT64 *Maximum, + OUT UINT64 *Step, + OUT UINT16 *StorageWidth + ) +{ + EFI_IFR_NUMERIC *NumericOp; + + NumericOp = (EFI_IFR_NUMERIC *)OpCode; + + switch (NumericOp->Flags & EFI_IFR_NUMERIC_SIZE) { + case EFI_IFR_NUMERIC_SIZE_1: + if (IntInput) { + *Minimum = (INT64)(INT8)NumericOp->data.u8.MinValue; + *Maximum = (INT64)(INT8)NumericOp->data.u8.MaxValue; + *Value = (INT64)(INT8)QuestionValue->Value.u8; + } else { + *Minimum = NumericOp->data.u8.MinValue; + *Maximum = NumericOp->data.u8.MaxValue; + *Value = QuestionValue->Value.u8; + } + + *Step = NumericOp->data.u8.Step; + *StorageWidth = (UINT16)sizeof (UINT8); + break; + + case EFI_IFR_NUMERIC_SIZE_2: + if (IntInput) { + *Minimum = (INT64)(INT16)NumericOp->data.u16.MinValue; + *Maximum = (INT64)(INT16)NumericOp->data.u16.MaxValue; + *Value = (INT64)(INT16)QuestionValue->Value.u16; + } else { + *Minimum = NumericOp->data.u16.MinValue; + *Maximum = NumericOp->data.u16.MaxValue; + *Value = QuestionValue->Value.u16; + } + + *Step = NumericOp->data.u16.Step; + *StorageWidth = (UINT16)sizeof (UINT16); + break; + + case EFI_IFR_NUMERIC_SIZE_4: + if (IntInput) { + *Minimum = (INT64)(INT32)NumericOp->data.u32.MinValue; + *Maximum = (INT64)(INT32)NumericOp->data.u32.MaxValue; + *Value = (INT64)(INT32)QuestionValue->Value.u32; + } else { + *Minimum = NumericOp->data.u32.MinValue; + *Maximum = NumericOp->data.u32.MaxValue; + *Value = QuestionValue->Value.u32; + } + + *Step = NumericOp->data.u32.Step; + *StorageWidth = (UINT16)sizeof (UINT32); + break; + + case EFI_IFR_NUMERIC_SIZE_8: + if (IntInput) { + *Minimum = (INT64)NumericOp->data.u64.MinValue; + *Maximum = (INT64)NumericOp->data.u64.MaxValue; + *Value = (INT64)QuestionValue->Value.u64; + } else { + *Minimum = NumericOp->data.u64.MinValue; + *Maximum = NumericOp->data.u64.MaxValue; + *Value = QuestionValue->Value.u64; + } + + *Step = NumericOp->data.u64.Step; + *StorageWidth = (UINT16)sizeof (UINT64); + break; + + default: + break; + } + + if (*Maximum == 0) { + *Maximum = (UINT64)-1; + } +} + +/** + This routine reads a numeric value from the user input. + + @param MenuOption Pointer to the current input menu. + + @retval EFI_SUCCESS If numerical input is read successfully + @retval EFI_DEVICE_ERROR If operation fails + +**/ +EFI_STATUS +GetNumericInput ( + IN UI_MENU_OPTION *MenuOption + ) +{ + UINTN Column; + UINTN Row; + CHAR16 InputText[MAX_NUMERIC_INPUT_WIDTH]; + CHAR16 FormattedNumber[MAX_NUMERIC_INPUT_WIDTH - 1]; + UINT64 PreviousNumber[MAX_NUMERIC_INPUT_WIDTH - 3]; + UINTN Count; + UINTN Loop; + BOOLEAN ManualInput; + BOOLEAN HexInput; + BOOLEAN IntInput; + BOOLEAN Negative; + BOOLEAN ValidateFail; + BOOLEAN DateOrTime; + UINTN InputWidth; + UINT64 EditValue; + UINT64 Step; + UINT64 Minimum; + UINT64 Maximum; + UINTN EraseLen; + UINT8 Digital; + EFI_INPUT_KEY Key; + EFI_HII_VALUE *QuestionValue; + FORM_DISPLAY_ENGINE_STATEMENT *Question; + EFI_IFR_NUMERIC *NumericOp; + UINT16 StorageWidth; + + Column = MenuOption->OptCol; + Row = MenuOption->Row; + PreviousNumber[0] = 0; + Count = 0; + InputWidth = 0; + Digital = 0; + StorageWidth = 0; + Minimum = 0; + Maximum = 0; + NumericOp = NULL; + IntInput = FALSE; + HexInput = FALSE; + Negative = FALSE; + ValidateFail = FALSE; + + Question = MenuOption->ThisTag; + QuestionValue = &Question->CurrentValue; + ZeroMem (InputText, MAX_NUMERIC_INPUT_WIDTH * sizeof (CHAR16)); + + // + // Only two case, user can enter to this function: Enter and +/- case. + // In Enter case, gDirection = 0; in +/- case, gDirection = SCAN_LEFT/SCAN_WRIGHT + // + ManualInput = (BOOLEAN)(gDirection == 0 ? TRUE : FALSE); + + if ((Question->OpCode->OpCode == EFI_IFR_DATE_OP) || (Question->OpCode->OpCode == EFI_IFR_TIME_OP)) { + DateOrTime = TRUE; + } else { + DateOrTime = FALSE; + } + + // + // Prepare Value to be edit + // + EraseLen = 0; + EditValue = 0; + if (Question->OpCode->OpCode == EFI_IFR_DATE_OP) { + Step = 1; + Minimum = 1; + + switch (MenuOption->Sequence) { + case 0: + Maximum = 12; + EraseLen = 4; + EditValue = QuestionValue->Value.date.Month; + break; + + case 1: + switch (QuestionValue->Value.date.Month) { + case 2: + if (((QuestionValue->Value.date.Year % 4) == 0) && + (((QuestionValue->Value.date.Year % 100) != 0) || + ((QuestionValue->Value.date.Year % 400) == 0))) + { + Maximum = 29; + } else { + Maximum = 28; + } + + break; + case 4: + case 6: + case 9: + case 11: + Maximum = 30; + break; + default: + Maximum = 31; + break; + } + + EraseLen = 3; + EditValue = QuestionValue->Value.date.Day; + break; + + case 2: + Maximum = 0xffff; + EraseLen = 5; + EditValue = QuestionValue->Value.date.Year; + break; + + default: + break; + } + } else if (Question->OpCode->OpCode == EFI_IFR_TIME_OP) { + Step = 1; + Minimum = 0; + + switch (MenuOption->Sequence) { + case 0: + Maximum = 23; + EraseLen = 4; + EditValue = QuestionValue->Value.time.Hour; + break; + + case 1: + Maximum = 59; + EraseLen = 3; + EditValue = QuestionValue->Value.time.Minute; + break; + + case 2: + Maximum = 59; + EraseLen = 3; + EditValue = QuestionValue->Value.time.Second; + break; + + default: + break; + } + } else { + ASSERT (Question->OpCode->OpCode == EFI_IFR_NUMERIC_OP); + NumericOp = (EFI_IFR_NUMERIC *)Question->OpCode; + GetValueFromNum (Question->OpCode, (NumericOp->Flags & EFI_IFR_DISPLAY) == 0, QuestionValue, &EditValue, &Minimum, &Maximum, &Step, &StorageWidth); + EraseLen = gOptionBlockWidth; + } + + if ((Question->OpCode->OpCode == EFI_IFR_NUMERIC_OP) && (NumericOp != NULL)) { + if ((NumericOp->Flags & EFI_IFR_DISPLAY) == EFI_IFR_DISPLAY_UINT_HEX) { + HexInput = TRUE; + } else if ((NumericOp->Flags & EFI_IFR_DISPLAY) == 0) { + // + // Display with EFI_IFR_DISPLAY_INT_DEC type. Support negative number. + // + IntInput = TRUE; + } + } + + // + // Enter from "Enter" input, clear the old word showing. + // + if (ManualInput) { + if (Question->OpCode->OpCode == EFI_IFR_NUMERIC_OP) { + if (HexInput) { + InputWidth = StorageWidth * 2; + } else { + switch (StorageWidth) { + case 1: + InputWidth = 3; + break; + + case 2: + InputWidth = 5; + break; + + case 4: + InputWidth = 10; + break; + + case 8: + InputWidth = 20; + break; + + default: + InputWidth = 0; + break; + } + + if (IntInput) { + // + // Support an extra '-' for negative number. + // + InputWidth += 1; + } + } + + InputText[0] = LEFT_NUMERIC_DELIMITER; + SetUnicodeMem (InputText + 1, InputWidth, L' '); + ASSERT (InputWidth + 2 < MAX_NUMERIC_INPUT_WIDTH); + InputText[InputWidth + 1] = RIGHT_NUMERIC_DELIMITER; + InputText[InputWidth + 2] = L'\0'; + + PrintStringAt (Column, Row, InputText); + Column++; + } + + if (Question->OpCode->OpCode == EFI_IFR_DATE_OP) { + if (MenuOption->Sequence == 2) { + InputWidth = 4; + } else { + InputWidth = 2; + } + + if (MenuOption->Sequence == 0) { + InputText[0] = LEFT_NUMERIC_DELIMITER; + SetUnicodeMem (InputText + 1, InputWidth, L' '); + InputText[InputWidth + 1] = DATE_SEPARATOR; + InputText[InputWidth + 2] = L'\0'; + } else if (MenuOption->Sequence == 1) { + SetUnicodeMem (InputText, InputWidth, L' '); + InputText[InputWidth] = DATE_SEPARATOR; + InputText[InputWidth + 1] = L'\0'; + } else { + SetUnicodeMem (InputText, InputWidth, L' '); + InputText[InputWidth] = RIGHT_NUMERIC_DELIMITER; + InputText[InputWidth + 1] = L'\0'; + } + + PrintStringAt (Column, Row, InputText); + if (MenuOption->Sequence == 0) { + Column++; + } + } + + if (Question->OpCode->OpCode == EFI_IFR_TIME_OP) { + InputWidth = 2; + + if (MenuOption->Sequence == 0) { + InputText[0] = LEFT_NUMERIC_DELIMITER; + SetUnicodeMem (InputText + 1, InputWidth, L' '); + InputText[InputWidth + 1] = TIME_SEPARATOR; + InputText[InputWidth + 2] = L'\0'; + } else if (MenuOption->Sequence == 1) { + SetUnicodeMem (InputText, InputWidth, L' '); + InputText[InputWidth] = TIME_SEPARATOR; + InputText[InputWidth + 1] = L'\0'; + } else { + SetUnicodeMem (InputText, InputWidth, L' '); + InputText[InputWidth] = RIGHT_NUMERIC_DELIMITER; + InputText[InputWidth + 1] = L'\0'; + } + + PrintStringAt (Column, Row, InputText); + if (MenuOption->Sequence == 0) { + Column++; + } + } + } + + // + // First time we enter this handler, we need to check to see if + // we were passed an increment or decrement directive + // + do { + Key.UnicodeChar = CHAR_NULL; + if (gDirection != 0) { + Key.ScanCode = gDirection; + gDirection = 0; + goto TheKey2; + } + + WaitForKeyStroke (&Key); + +TheKey2: + switch (Key.UnicodeChar) { + case '+': + case '-': + if (ManualInput && IntInput) { + // + // In Manual input mode, check whether input the negative flag. + // + if (Key.UnicodeChar == '-') { + if (Negative) { + break; + } + + Negative = TRUE; + PrintCharAt (Column++, Row, Key.UnicodeChar); + } + } else { + if (Key.UnicodeChar == '+') { + Key.ScanCode = SCAN_RIGHT; + } else { + Key.ScanCode = SCAN_LEFT; + } + + Key.UnicodeChar = CHAR_NULL; + goto TheKey2; + } + + break; + + case CHAR_NULL: + switch (Key.ScanCode) { + case SCAN_LEFT: + case SCAN_RIGHT: + if (DateOrTime && !ManualInput) { + // + // By setting this value, we will return back to the caller. + // We need to do this since an auto-refresh will destroy the adjustment + // based on what the real-time-clock is showing. So we always commit + // upon changing the value. + // + gDirection = SCAN_DOWN; + } + + if ((Step != 0) && !ManualInput) { + if (Key.ScanCode == SCAN_LEFT) { + if (IntInput) { + if ((INT64)EditValue >= (INT64)Minimum + (INT64)Step) { + EditValue = EditValue - Step; + } else if ((INT64)EditValue > (INT64)Minimum) { + EditValue = Minimum; + } else { + EditValue = Maximum; + } + } else { + if (EditValue >= Minimum + Step) { + EditValue = EditValue - Step; + } else if (EditValue > Minimum) { + EditValue = Minimum; + } else { + EditValue = Maximum; + } + } + } else if (Key.ScanCode == SCAN_RIGHT) { + if (IntInput) { + if ((INT64)EditValue + (INT64)Step <= (INT64)Maximum) { + EditValue = EditValue + Step; + } else if ((INT64)EditValue < (INT64)Maximum) { + EditValue = Maximum; + } else { + EditValue = Minimum; + } + } else { + if (EditValue + Step <= Maximum) { + EditValue = EditValue + Step; + } else if (EditValue < Maximum) { + EditValue = Maximum; + } else { + EditValue = Minimum; + } + } + } + + ZeroMem (FormattedNumber, 21 * sizeof (CHAR16)); + if (Question->OpCode->OpCode == EFI_IFR_DATE_OP) { + if (MenuOption->Sequence == 2) { + // + // Year + // + UnicodeSPrint (FormattedNumber, 21 * sizeof (CHAR16), L"%04d", (UINT16)EditValue); + } else { + // + // Month/Day + // + UnicodeSPrint (FormattedNumber, 21 * sizeof (CHAR16), L"%02d", (UINT8)EditValue); + } + + if (MenuOption->Sequence == 0) { + ASSERT (EraseLen >= 2); + FormattedNumber[EraseLen - 2] = DATE_SEPARATOR; + } else if (MenuOption->Sequence == 1) { + ASSERT (EraseLen >= 1); + FormattedNumber[EraseLen - 1] = DATE_SEPARATOR; + } + } else if (Question->OpCode->OpCode == EFI_IFR_TIME_OP) { + UnicodeSPrint (FormattedNumber, 21 * sizeof (CHAR16), L"%02d", (UINT8)EditValue); + + if (MenuOption->Sequence == 0) { + ASSERT (EraseLen >= 2); + FormattedNumber[EraseLen - 2] = TIME_SEPARATOR; + } else if (MenuOption->Sequence == 1) { + ASSERT (EraseLen >= 1); + FormattedNumber[EraseLen - 1] = TIME_SEPARATOR; + } + } else { + QuestionValue->Value.u64 = EditValue; + PrintFormattedNumber (Question, FormattedNumber, 21 * sizeof (CHAR16)); + } + + gST->ConOut->SetAttribute (gST->ConOut, GetFieldTextColor ()); + for (Loop = 0; Loop < EraseLen; Loop++) { + PrintStringAt (MenuOption->OptCol + Loop, MenuOption->Row, L" "); + } + + gST->ConOut->SetAttribute (gST->ConOut, GetHighlightTextColor ()); + + if (MenuOption->Sequence == 0) { + PrintCharAt (MenuOption->OptCol, Row, LEFT_NUMERIC_DELIMITER); + Column = MenuOption->OptCol + 1; + } + + PrintStringAt (Column, Row, FormattedNumber); + + if (!DateOrTime || (MenuOption->Sequence == 2)) { + PrintCharAt ((UINTN)-1, (UINTN)-1, RIGHT_NUMERIC_DELIMITER); + } + } + + goto EnterCarriageReturn; + + case SCAN_UP: + case SCAN_DOWN: + goto EnterCarriageReturn; + + case SCAN_ESC: + return EFI_DEVICE_ERROR; + + default: + break; + } + + break; + +EnterCarriageReturn: + + case CHAR_CARRIAGE_RETURN: + // + // Validate input value with Minimum value. + // + ValidateFail = FALSE; + if (IntInput) { + // + // After user input Enter, need to check whether the input value. + // If input a negative value, should compare with maximum value. + // else compare with the minimum value. + // + if (Negative) { + ValidateFail = (INT64)EditValue > (INT64)Maximum ? TRUE : FALSE; + } else { + ValidateFail = (INT64)EditValue < (INT64)Minimum ? TRUE : FALSE; + } + + if (ValidateFail) { + UpdateStatusBar (INPUT_ERROR, TRUE); + break; + } + } else if (EditValue < Minimum) { + UpdateStatusBar (INPUT_ERROR, TRUE); + break; + } + + UpdateStatusBar (INPUT_ERROR, FALSE); + CopyMem (&gUserInput->InputValue, &Question->CurrentValue, sizeof (EFI_HII_VALUE)); + QuestionValue = &gUserInput->InputValue; + // + // Store Edit value back to Question + // + if (Question->OpCode->OpCode == EFI_IFR_DATE_OP) { + switch (MenuOption->Sequence) { + case 0: + QuestionValue->Value.date.Month = (UINT8)EditValue; + break; + + case 1: + QuestionValue->Value.date.Day = (UINT8)EditValue; + break; + + case 2: + QuestionValue->Value.date.Year = (UINT16)EditValue; + break; + + default: + break; + } + } else if (Question->OpCode->OpCode == EFI_IFR_TIME_OP) { + switch (MenuOption->Sequence) { + case 0: + QuestionValue->Value.time.Hour = (UINT8)EditValue; + break; + + case 1: + QuestionValue->Value.time.Minute = (UINT8)EditValue; + break; + + case 2: + QuestionValue->Value.time.Second = (UINT8)EditValue; + break; + + default: + break; + } + } else { + // + // Numeric + // + QuestionValue->Value.u64 = EditValue; + } + + // + // Adjust the value to the correct one. + // Sample like: 2012.02.29 -> 2013.02.29 -> 2013.02.01 + // 2013.03.29 -> 2013.02.29 -> 2013.02.28 + // + if ((Question->OpCode->OpCode == EFI_IFR_DATE_OP) && + ((MenuOption->Sequence == 0) || (MenuOption->Sequence == 2))) + { + AdjustQuestionValue (QuestionValue, (UINT8)MenuOption->Sequence); + } + + return EFI_SUCCESS; + + case CHAR_BACKSPACE: + if (ManualInput) { + if (Count == 0) { + if (Negative) { + Negative = FALSE; + Column--; + PrintStringAt (Column, Row, L" "); + } + + break; + } + + // + // Remove a character + // + EditValue = PreviousNumber[Count - 1]; + UpdateStatusBar (INPUT_ERROR, FALSE); + Count--; + Column--; + PrintStringAt (Column, Row, L" "); + } + + break; + + default: + if (ManualInput) { + if (HexInput) { + if ((Key.UnicodeChar >= L'0') && (Key.UnicodeChar <= L'9')) { + Digital = (UINT8)(Key.UnicodeChar - L'0'); + } else if ((Key.UnicodeChar >= L'A') && (Key.UnicodeChar <= L'F')) { + Digital = (UINT8)(Key.UnicodeChar - L'A' + 0x0A); + } else if ((Key.UnicodeChar >= L'a') && (Key.UnicodeChar <= L'f')) { + Digital = (UINT8)(Key.UnicodeChar - L'a' + 0x0A); + } else { + UpdateStatusBar (INPUT_ERROR, TRUE); + break; + } + } else { + if ((Key.UnicodeChar > L'9') || (Key.UnicodeChar < L'0')) { + UpdateStatusBar (INPUT_ERROR, TRUE); + break; + } + } + + // + // If Count exceed input width, there is no way more is valid + // + if (Count >= InputWidth) { + break; + } + + // + // Someone typed something valid! + // + if (Count != 0) { + if (HexInput) { + EditValue = LShiftU64 (EditValue, 4) + Digital; + } else if (IntInput && Negative) { + // + // Save the negative number. + // + EditValue = ~(MultU64x32 (~(EditValue - 1), 10) + (Key.UnicodeChar - L'0')) + 1; + } else { + EditValue = MultU64x32 (EditValue, 10) + (Key.UnicodeChar - L'0'); + } + } else { + if (HexInput) { + EditValue = Digital; + } else if (IntInput && Negative) { + // + // Save the negative number. + // + EditValue = ~(Key.UnicodeChar - L'0') + 1; + } else { + EditValue = Key.UnicodeChar - L'0'; + } + } + + if (IntInput) { + ValidateFail = FALSE; + // + // When user input a new value, should check the current value. + // If user input a negative value, should compare it with minimum + // value, else compare it with maximum value. + // + if (Negative) { + ValidateFail = (INT64)EditValue < (INT64)Minimum ? TRUE : FALSE; + } else { + ValidateFail = (INT64)EditValue > (INT64)Maximum ? TRUE : FALSE; + } + + if (ValidateFail) { + UpdateStatusBar (INPUT_ERROR, TRUE); + ASSERT (Count < ARRAY_SIZE (PreviousNumber)); + EditValue = PreviousNumber[Count]; + break; + } + } else { + if (EditValue > Maximum) { + UpdateStatusBar (INPUT_ERROR, TRUE); + ASSERT (Count < ARRAY_SIZE (PreviousNumber)); + EditValue = PreviousNumber[Count]; + break; + } + } + + UpdateStatusBar (INPUT_ERROR, FALSE); + + Count++; + ASSERT (Count < (ARRAY_SIZE (PreviousNumber))); + PreviousNumber[Count] = EditValue; + + gST->ConOut->SetAttribute (gST->ConOut, GetHighlightTextColor ()); + PrintCharAt (Column, Row, Key.UnicodeChar); + Column++; + } + + break; + } + } while (TRUE); +} + +/** + Adjust option order base on the question value. + + @param Question Pointer to current question. + @param PopUpMenuLines The line number of the pop up menu. + + @retval EFI_SUCCESS If Option input is processed successfully + @retval EFI_DEVICE_ERROR If operation fails + +**/ +EFI_STATUS +AdjustOptionOrder ( + IN FORM_DISPLAY_ENGINE_STATEMENT *Question, + OUT UINTN *PopUpMenuLines + ) +{ + UINTN Index; + EFI_IFR_ORDERED_LIST *OrderList; + UINT8 *ValueArray; + UINT8 ValueType; + LIST_ENTRY *Link; + DISPLAY_QUESTION_OPTION *OneOfOption; + EFI_HII_VALUE *HiiValueArray; + + Link = GetFirstNode (&Question->OptionListHead); + OneOfOption = DISPLAY_QUESTION_OPTION_FROM_LINK (Link); + ValueArray = Question->CurrentValue.Buffer; + ValueType = OneOfOption->OptionOpCode->Type; + OrderList = (EFI_IFR_ORDERED_LIST *)Question->OpCode; + + for (Index = 0; Index < OrderList->MaxContainers; Index++) { + if (GetArrayData (ValueArray, ValueType, Index) == 0) { + break; + } + } + + *PopUpMenuLines = Index; + + // + // Prepare HiiValue array + // + HiiValueArray = AllocateZeroPool (*PopUpMenuLines * sizeof (EFI_HII_VALUE)); + ASSERT (HiiValueArray != NULL); + + for (Index = 0; Index < *PopUpMenuLines; Index++) { + HiiValueArray[Index].Type = ValueType; + HiiValueArray[Index].Value.u64 = GetArrayData (ValueArray, ValueType, Index); + } + + for (Index = 0; Index < *PopUpMenuLines; Index++) { + OneOfOption = ValueToOption (Question, &HiiValueArray[*PopUpMenuLines - Index - 1]); + if (OneOfOption == NULL) { + return EFI_NOT_FOUND; + } + + RemoveEntryList (&OneOfOption->Link); + + // + // Insert to head. + // + InsertHeadList (&Question->OptionListHead, &OneOfOption->Link); + } + + FreePool (HiiValueArray); + + return EFI_SUCCESS; +} + +/** + Base on the type to compare the value. + + @param Value1 The first value need to compare. + @param Value2 The second value need to compare. + @param Type The value type for above two values. + + @retval TRUE The two value are same. + @retval FALSE The two value are different. + +**/ +BOOLEAN +IsValuesEqual ( + IN EFI_IFR_TYPE_VALUE *Value1, + IN EFI_IFR_TYPE_VALUE *Value2, + IN UINT8 Type + ) +{ + switch (Type) { + case EFI_IFR_TYPE_BOOLEAN: + case EFI_IFR_TYPE_NUM_SIZE_8: + return (BOOLEAN)(Value1->u8 == Value2->u8); + + case EFI_IFR_TYPE_NUM_SIZE_16: + return (BOOLEAN)(Value1->u16 == Value2->u16); + + case EFI_IFR_TYPE_NUM_SIZE_32: + return (BOOLEAN)(Value1->u32 == Value2->u32); + + case EFI_IFR_TYPE_NUM_SIZE_64: + return (BOOLEAN)(Value1->u64 == Value2->u64); + + default: + ASSERT (FALSE); + return FALSE; + } +} + +/** + Base on the type to set the value. + + @param Dest The dest value. + @param Source The source value. + @param Type The value type for above two values. + +**/ +VOID +SetValuesByType ( + OUT EFI_IFR_TYPE_VALUE *Dest, + IN EFI_IFR_TYPE_VALUE *Source, + IN UINT8 Type + ) +{ + switch (Type) { + case EFI_IFR_TYPE_BOOLEAN: + Dest->b = Source->b; + break; + + case EFI_IFR_TYPE_NUM_SIZE_8: + Dest->u8 = Source->u8; + break; + + case EFI_IFR_TYPE_NUM_SIZE_16: + Dest->u16 = Source->u16; + break; + + case EFI_IFR_TYPE_NUM_SIZE_32: + Dest->u32 = Source->u32; + break; + + case EFI_IFR_TYPE_NUM_SIZE_64: + Dest->u64 = Source->u64; + break; + + default: + ASSERT (FALSE); + break; + } +} + +/** + Get selection for OneOf and OrderedList (Left/Right will be ignored). + + @param MenuOption Pointer to the current input menu. + + @retval EFI_SUCCESS If Option input is processed successfully + @retval EFI_DEVICE_ERROR If operation fails + +**/ +EFI_STATUS +GetSelectionInputPopUp ( + IN UI_MENU_OPTION *MenuOption + ) +{ + EFI_INPUT_KEY Key; + UINTN Index; + CHAR16 *StringPtr; + CHAR16 *TempStringPtr; + UINTN Index2; + UINTN TopOptionIndex; + UINTN HighlightOptionIndex; + UINTN Start; + UINTN End; + UINTN Top; + UINTN Bottom; + UINTN PopUpMenuLines; + UINTN MenuLinesInView; + UINTN PopUpWidth; + CHAR16 Character; + INT32 SavedAttribute; + BOOLEAN ShowDownArrow; + BOOLEAN ShowUpArrow; + UINTN DimensionsWidth; + LIST_ENTRY *Link; + BOOLEAN OrderedList; + UINT8 *ValueArray; + UINT8 *ReturnValue; + UINT8 ValueType; + EFI_HII_VALUE HiiValue; + DISPLAY_QUESTION_OPTION *OneOfOption; + DISPLAY_QUESTION_OPTION *CurrentOption; + FORM_DISPLAY_ENGINE_STATEMENT *Question; + INTN Result; + EFI_IFR_ORDERED_LIST *OrderList; + + DimensionsWidth = gStatementDimensions.RightColumn - gStatementDimensions.LeftColumn; + + ValueArray = NULL; + ValueType = 0; + CurrentOption = NULL; + ShowDownArrow = FALSE; + ShowUpArrow = FALSE; + + ZeroMem (&HiiValue, sizeof (EFI_HII_VALUE)); + + Question = MenuOption->ThisTag; + if (Question->OpCode->OpCode == EFI_IFR_ORDERED_LIST_OP) { + Link = GetFirstNode (&Question->OptionListHead); + OneOfOption = DISPLAY_QUESTION_OPTION_FROM_LINK (Link); + ValueArray = Question->CurrentValue.Buffer; + ValueType = OneOfOption->OptionOpCode->Type; + OrderedList = TRUE; + OrderList = (EFI_IFR_ORDERED_LIST *)Question->OpCode; + } else { + OrderedList = FALSE; + OrderList = NULL; + } + + // + // Calculate Option count + // + PopUpMenuLines = 0; + if (OrderedList) { + AdjustOptionOrder (Question, &PopUpMenuLines); + } else { + Link = GetFirstNode (&Question->OptionListHead); + while (!IsNull (&Question->OptionListHead, Link)) { + OneOfOption = DISPLAY_QUESTION_OPTION_FROM_LINK (Link); + PopUpMenuLines++; + Link = GetNextNode (&Question->OptionListHead, Link); + } + } + + // + // Get the number of one of options present and its size + // + PopUpWidth = 0; + HighlightOptionIndex = 0; + Link = GetFirstNode (&Question->OptionListHead); + for (Index = 0; Index < PopUpMenuLines; Index++) { + OneOfOption = DISPLAY_QUESTION_OPTION_FROM_LINK (Link); + + StringPtr = GetToken (OneOfOption->OptionOpCode->Option, gFormData->HiiHandle); + if (StrLen (StringPtr) > PopUpWidth) { + PopUpWidth = StrLen (StringPtr); + } + + FreePool (StringPtr); + HiiValue.Type = OneOfOption->OptionOpCode->Type; + SetValuesByType (&HiiValue.Value, &OneOfOption->OptionOpCode->Value, HiiValue.Type); + if (!OrderedList && (CompareHiiValue (&Question->CurrentValue, &HiiValue, &Result, NULL) == EFI_SUCCESS) && (Result == 0)) { + // + // Find current selected Option for OneOf + // + HighlightOptionIndex = Index; + } + + Link = GetNextNode (&Question->OptionListHead, Link); + } + + // + // Perform popup menu initialization. + // + PopUpWidth = PopUpWidth + POPUP_PAD_SPACE_COUNT; + + SavedAttribute = gST->ConOut->Mode->Attribute; + gST->ConOut->SetAttribute (gST->ConOut, GetPopupColor ()); + + if ((PopUpWidth + POPUP_FRAME_WIDTH) > DimensionsWidth) { + PopUpWidth = DimensionsWidth - POPUP_FRAME_WIDTH; + } + + Start = (DimensionsWidth - PopUpWidth - POPUP_FRAME_WIDTH) / 2 + gStatementDimensions.LeftColumn; + End = Start + PopUpWidth + POPUP_FRAME_WIDTH; + Top = gStatementDimensions.TopRow; + Bottom = gStatementDimensions.BottomRow - 1; + + MenuLinesInView = Bottom - Top - 1; + if (MenuLinesInView >= PopUpMenuLines) { + Top = Top + (MenuLinesInView - PopUpMenuLines) / 2; + Bottom = Top + PopUpMenuLines + 1; + } else { + ShowDownArrow = TRUE; + } + + if (HighlightOptionIndex > (MenuLinesInView - 1)) { + TopOptionIndex = HighlightOptionIndex - MenuLinesInView + 1; + } else { + TopOptionIndex = 0; + } + + do { + // + // Clear that portion of the screen + // + ClearLines (Start, End, Top, Bottom, GetPopupColor ()); + + // + // Draw "One of" pop-up menu + // + Character = BOXDRAW_DOWN_RIGHT; + PrintCharAt (Start, Top, Character); + for (Index = Start; Index + 2 < End; Index++) { + if ((ShowUpArrow) && ((Index + 1) == (Start + End) / 2)) { + Character = GEOMETRICSHAPE_UP_TRIANGLE; + } else { + Character = BOXDRAW_HORIZONTAL; + } + + PrintCharAt ((UINTN)-1, (UINTN)-1, Character); + } + + Character = BOXDRAW_DOWN_LEFT; + PrintCharAt ((UINTN)-1, (UINTN)-1, Character); + Character = BOXDRAW_VERTICAL; + for (Index = Top + 1; Index < Bottom; Index++) { + PrintCharAt (Start, Index, Character); + PrintCharAt (End - 1, Index, Character); + } + + // + // Move to top Option + // + Link = GetFirstNode (&Question->OptionListHead); + for (Index = 0; Index < TopOptionIndex; Index++) { + Link = GetNextNode (&Question->OptionListHead, Link); + } + + // + // Display the One of options + // + Index2 = Top + 1; + for (Index = TopOptionIndex; (Index < PopUpMenuLines) && (Index2 < Bottom); Index++) { + OneOfOption = DISPLAY_QUESTION_OPTION_FROM_LINK (Link); + Link = GetNextNode (&Question->OptionListHead, Link); + + StringPtr = GetToken (OneOfOption->OptionOpCode->Option, gFormData->HiiHandle); + ASSERT (StringPtr != NULL); + // + // If the string occupies multiple lines, truncate it to fit in one line, + // and append a "..." for indication. + // + if (StrLen (StringPtr) > (PopUpWidth - 1)) { + TempStringPtr = AllocateZeroPool (sizeof (CHAR16) * (PopUpWidth - 1)); + ASSERT (TempStringPtr != NULL); + CopyMem (TempStringPtr, StringPtr, (sizeof (CHAR16) * (PopUpWidth - 5))); + FreePool (StringPtr); + StringPtr = TempStringPtr; + StrCatS (StringPtr, PopUpWidth - 1, L"..."); + } + + if (Index == HighlightOptionIndex) { + // + // Highlight the selected one + // + CurrentOption = OneOfOption; + + gST->ConOut->SetAttribute (gST->ConOut, GetPickListColor ()); + PrintStringAt (Start + 2, Index2, StringPtr); + gST->ConOut->SetAttribute (gST->ConOut, GetPopupColor ()); + } else { + gST->ConOut->SetAttribute (gST->ConOut, GetPopupColor ()); + PrintStringAt (Start + 2, Index2, StringPtr); + } + + Index2++; + FreePool (StringPtr); + } + + Character = BOXDRAW_UP_RIGHT; + PrintCharAt (Start, Bottom, Character); + for (Index = Start; Index + 2 < End; Index++) { + if ((ShowDownArrow) && ((Index + 1) == (Start + End) / 2)) { + Character = GEOMETRICSHAPE_DOWN_TRIANGLE; + } else { + Character = BOXDRAW_HORIZONTAL; + } + + PrintCharAt ((UINTN)-1, (UINTN)-1, Character); + } + + Character = BOXDRAW_UP_LEFT; + PrintCharAt ((UINTN)-1, (UINTN)-1, Character); + + // + // Get User selection + // + Key.UnicodeChar = CHAR_NULL; + if ((gDirection == SCAN_UP) || (gDirection == SCAN_DOWN)) { + Key.ScanCode = gDirection; + gDirection = 0; + goto TheKey; + } + + WaitForKeyStroke (&Key); + +TheKey: + switch (Key.UnicodeChar) { + case '+': + if (OrderedList) { + if ((TopOptionIndex > 0) && (TopOptionIndex == HighlightOptionIndex)) { + // + // Highlight reaches the top of the popup window, scroll one menu item. + // + TopOptionIndex--; + ShowDownArrow = TRUE; + } + + if (TopOptionIndex == 0) { + ShowUpArrow = FALSE; + } + + if (HighlightOptionIndex > 0) { + HighlightOptionIndex--; + + ASSERT (CurrentOption != NULL); + SwapListEntries (CurrentOption->Link.BackLink, &CurrentOption->Link); + } + } + + break; + + case '-': + // + // If an ordered list op-code, we will allow for a popup of +/- keys + // to create an ordered list of items + // + if (OrderedList) { + if (((TopOptionIndex + MenuLinesInView) < PopUpMenuLines) && + (HighlightOptionIndex == (TopOptionIndex + MenuLinesInView - 1))) + { + // + // Highlight reaches the bottom of the popup window, scroll one menu item. + // + TopOptionIndex++; + ShowUpArrow = TRUE; + } + + if ((TopOptionIndex + MenuLinesInView) == PopUpMenuLines) { + ShowDownArrow = FALSE; + } + + if (HighlightOptionIndex < (PopUpMenuLines - 1)) { + HighlightOptionIndex++; + + ASSERT (CurrentOption != NULL); + SwapListEntries (&CurrentOption->Link, CurrentOption->Link.ForwardLink); + } + } + + break; + + case '^': + if ((TopOptionIndex > 0) && (TopOptionIndex == HighlightOptionIndex)) { + // + // Highlight reaches the top of the popup window, scroll one menu item. + // + TopOptionIndex--; + ShowDownArrow = TRUE; + } + + if (TopOptionIndex == 0) { + ShowUpArrow = FALSE; + } + + if (HighlightOptionIndex > 0) { + HighlightOptionIndex--; + } + + break; + + case 'V': + case 'v': + if (((TopOptionIndex + MenuLinesInView) < PopUpMenuLines) && + (HighlightOptionIndex == (TopOptionIndex + MenuLinesInView - 1))) + { + // + // Highlight reaches the bottom of the popup window, scroll one menu item. + // + TopOptionIndex++; + ShowUpArrow = TRUE; + } + + if ((TopOptionIndex + MenuLinesInView) == PopUpMenuLines) { + ShowDownArrow = FALSE; + } + + if (HighlightOptionIndex < (PopUpMenuLines - 1)) { + HighlightOptionIndex++; + } + + break; + + case CHAR_NULL: + switch (Key.ScanCode) { + case SCAN_UP: + case SCAN_DOWN: + if (Key.ScanCode == SCAN_UP) { + if ((TopOptionIndex > 0) && (TopOptionIndex == HighlightOptionIndex)) { + // + // Highlight reaches the top of the popup window, scroll one menu item. + // + TopOptionIndex--; + ShowDownArrow = TRUE; + } + + if (TopOptionIndex == 0) { + ShowUpArrow = FALSE; + } + + if (HighlightOptionIndex > 0) { + HighlightOptionIndex--; + } + } else { + if (((TopOptionIndex + MenuLinesInView) < PopUpMenuLines) && + (HighlightOptionIndex == (TopOptionIndex + MenuLinesInView - 1))) + { + // + // Highlight reaches the bottom of the popup window, scroll one menu item. + // + TopOptionIndex++; + ShowUpArrow = TRUE; + } + + if ((TopOptionIndex + MenuLinesInView) == PopUpMenuLines) { + ShowDownArrow = FALSE; + } + + if (HighlightOptionIndex < (PopUpMenuLines - 1)) { + HighlightOptionIndex++; + } + } + + break; + + case SCAN_ESC: + gST->ConOut->SetAttribute (gST->ConOut, SavedAttribute); + + // + // Restore link list order for orderedlist + // + if (OrderedList) { + HiiValue.Type = ValueType; + HiiValue.Value.u64 = 0; + for (Index = 0; Index < OrderList->MaxContainers; Index++) { + HiiValue.Value.u64 = GetArrayData (ValueArray, ValueType, Index); + if (HiiValue.Value.u64 == 0) { + break; + } + + OneOfOption = ValueToOption (Question, &HiiValue); + if (OneOfOption == NULL) { + return EFI_NOT_FOUND; + } + + RemoveEntryList (&OneOfOption->Link); + InsertTailList (&Question->OptionListHead, &OneOfOption->Link); + } + } + + return EFI_DEVICE_ERROR; + + default: + break; + } + + break; + + case CHAR_CARRIAGE_RETURN: + // + // return the current selection + // + if (OrderedList) { + ReturnValue = AllocateZeroPool (Question->CurrentValue.BufferLen); + ASSERT (ReturnValue != NULL); + Index = 0; + Link = GetFirstNode (&Question->OptionListHead); + while (!IsNull (&Question->OptionListHead, Link)) { + OneOfOption = DISPLAY_QUESTION_OPTION_FROM_LINK (Link); + Link = GetNextNode (&Question->OptionListHead, Link); + + SetArrayData (ReturnValue, ValueType, Index, OneOfOption->OptionOpCode->Value.u64); + + Index++; + if (Index > OrderList->MaxContainers) { + break; + } + } + + if (CompareMem (ReturnValue, ValueArray, Question->CurrentValue.BufferLen) == 0) { + FreePool (ReturnValue); + return EFI_DEVICE_ERROR; + } else { + gUserInput->InputValue.Buffer = ReturnValue; + gUserInput->InputValue.BufferLen = Question->CurrentValue.BufferLen; + } + } else { + ASSERT (CurrentOption != NULL); + gUserInput->InputValue.Type = CurrentOption->OptionOpCode->Type; + if (IsValuesEqual (&Question->CurrentValue.Value, &CurrentOption->OptionOpCode->Value, gUserInput->InputValue.Type)) { + return EFI_DEVICE_ERROR; + } else { + SetValuesByType (&gUserInput->InputValue.Value, &CurrentOption->OptionOpCode->Value, gUserInput->InputValue.Type); + } + } + + gST->ConOut->SetAttribute (gST->ConOut, SavedAttribute); + + return EFI_SUCCESS; + + default: + break; + } + } while (TRUE); +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/IndustryStandard/SpiNorFlashJedecSfdp.h b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/IndustryStandard/SpiNorFlashJedecSfdp.h new file mode 100644 index 0000000000000000000000000000000000000000..6275489d73ef2d5c6efeb704e8efc048e9f299ff --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/IndustryStandard/SpiNorFlashJedecSfdp.h @@ -0,0 +1,323 @@ +/** @file + SPI NOR Flash JEDEC Serial Flash Discoverable Parameters (SFDP) + header file. + + Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - JEDEC Standard, JESD216F.02 + https://www.jedec.org/document_search?search_api_views_fulltext=JESD216 + + @par Glossary: + - SFDP - Serial Flash Discoverable Parameters + - PTP - Parameter Table Pointer +**/ + +#ifndef SPI_NOR_FLASH_JEDEC_H_ +#define SPI_NOR_FLASH_JEDEC_H_ + +#include + +#define SFDP_HEADER_SIGNATURE 0x50444653 +#define SFDP_SUPPORTED_MAJOR_REVISION 0x1ul + +/// JEDEC Basic Flash Parameter Header +#define SFDP_BASIC_PARAMETER_ID_LSB 0x00 +#define SFDP_BASIC_PARAMETER_ID_MSB 0xFF + +/// +/// JDEC Sector Map Parameter Header and Table +/// +#define SFDP_SECTOR_MAP_PARAMETER_ID_LSB 0x81 +#define SFDP_FOUR_BYTE_ADDRESS_INSTRUCTION_LSB 0x84 +#define SFDP_SECTOR_MAP_PARAMETER_ID_MSB 0xFF + +#define SFDP_FLASH_MEMORY_DENSITY_4GBIT 0x80000000 + +#pragma pack (1) +typedef struct _SFDP_HEADER { + UINT32 Signature; + UINT32 MinorRev : 8; + UINT32 MajorRev : 8; + UINT32 NumParameterHeaders : 8; + UINT32 AccessProtocol : 8; +} SFDP_HEADER; + +typedef struct _SFDP_PARAMETER_HEADER { + UINT32 IdLsb : 8; + UINT32 MinorRev : 8; + UINT32 MajorRev : 8; + UINT32 Length : 8; + UINT32 TablePointer : 24; + UINT32 IdMsb : 8; +} SFDP_PARAMETER_HEADER; + +typedef struct _SFDP_BASIC_FLASH_PARAMETER { + // DWORD 1 + UINT32 EraseSizes : 2; + UINT32 WriteGranularity : 1; + UINT32 VolatileStatusBlockProtect : 1; + UINT32 WriteEnableVolatileStatus : 1; + UINT32 Unused1Dw1 : 3; + UINT32 FourKEraseInstr : 8; + UINT32 FastRead112 : 1; + UINT32 AddressBytes : 2; + UINT32 DtrClocking : 1; + UINT32 FastRead122 : 1; + UINT32 FastRead144 : 1; + UINT32 FastRead114 : 1; + UINT32 Unused2Dw1 : 9; + // DWORD 2 + UINT32 Density; + // DWORD 3 + // Fast Read 144 + UINT32 FastRead144Dummy : 5; + UINT32 FastRead144ModeClk : 3; + UINT32 FastRead144Instr : 8; + // Fast Read 114 + UINT32 FastRead114Dummy : 5; + UINT32 FastRead114ModeClk : 3; + UINT32 FastRead114Instr : 8; + // DWORD 4 + // Fast Read 112 + UINT32 FastRead112Dummy : 5; + UINT32 FastRead112ModeClk : 3; + UINT32 FastRead112Instr : 8; + // Fast Read 122 + UINT32 FastRead122Dummy : 5; + UINT32 FastRead122ModeClk : 3; + UINT32 FastRead122Instr : 8; + // DWORD 5 + UINT32 FastRead222 : 1; + UINT32 Unused1Dw5 : 3; + UINT32 FastRead444 : 1; + UINT32 Unused2Dw5 : 27; + // DWORD 6 + UINT32 UnusedDw6 : 16; + // Fast Read 222 + UINT32 FastRead222Dummy : 5; + UINT32 FastRead222ModeClk : 3; + UINT32 FastRead222Instr : 8; + // DWORD 7 + UINT32 UnusedDw7 : 16; + // Fast Read 444 + UINT32 FastRead444Dummy : 5; + UINT32 FastRead444ModeClk : 3; + UINT32 FastRead444Instr : 8; + // DWORD 8 + UINT32 Erase1Size : 8; + UINT32 Erase1Instr : 8; + UINT32 Erase2Size : 8; + UINT32 Erase2Instr : 8; + // DWORD 9 + UINT32 Erase3Size : 8; + UINT32 Erase3Instr : 8; + UINT32 Erase4Size : 8; + UINT32 Erase4Instr : 8; + // DWORD 10 + UINT32 EraseMultiplier : 4; + UINT32 Erase1Time : 7; + UINT32 Erase2Time : 7; + UINT32 Erase3Time : 7; + UINT32 Erase4Time : 7; + // DWORD 11 + UINT32 ProgramMultiplier : 4; + UINT32 PageSize : 4; + UINT32 PPTime : 6; + UINT32 BPFirstTime : 5; + UINT32 BPAdditionalTime : 5; + UINT32 ChipEraseTime : 7; + UINT32 Unused1Dw11 : 1; + // DWORD 12 + UINT32 ProgSuspendProhibit : 4; + UINT32 EraseSuspendProhibit : 4; + UINT32 Unused1Dw13 : 1; + UINT32 ProgResumeToSuspend : 4; + UINT32 ProgSuspendInProgressTime : 7; + UINT32 EraseResumeToSuspend : 4; + UINT32 EraseSuspendInProgressTime : 7; + UINT32 SuspendResumeSupported : 1; + // DWORD 13 + UINT32 Unused13; + // DWORD 14 + UINT32 Unused14; + // DWORD 15 + UINT32 Unused15; + // DWORD 16 + UINT32 Unused16; + // DWORD 17 + UINT32 FastRead188Dummy : 5; + UINT32 FastRead188ModeClk : 3; + UINT32 FastRead188Instr : 8; + UINT32 FastRead118Dummy : 5; + UINT32 FastRead118ModeClk : 3; + UINT32 FastRead118Instr : 8; + // + // Don't care about remaining DWORDs + // DWORD 18 to DWORD 23 + // + UINT32 Unused18; + UINT32 Unused19; + UINT32 Unused20; + UINT32 Unused21; + UINT32 Unused22; + UINT32 Unused23; +} SFDP_BASIC_FLASH_PARAMETER; +#pragma pack () + +#define SPI_UNIFORM_4K_ERASE_SUPPORTED 0x01 +#define SPI_UNIFORM_4K_ERASE_UNSUPPORTED 0x03 + +/// +/// Number of address bytes opcode can support +/// +#define SPI_ADDR_3BYTE_ONLY 0x00 +#define SPI_ADDR_3OR4BYTE 0x01 +#define SPI_ADDR_4BYTE_ONLY 0x02 + +#define SFDP_ERASE_TYPES_NUMBER 4 +#define SFDP_ERASE_TYPE_1 0x0001 +#define SFDP_ERASE_TYPE_2 0x0002 +#define SFDP_ERASE_TYPE_3 0x0003 +#define SFDP_ERASE_TYPE_4 0x0004 + +/// +/// Read/Write Array Commands +/// +#define SPI_FLASH_READ 0x03 +#define SPI_FLASH_READ_DUMMY 0x00 +#define SPI_FLASH_READ_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_FAST_READ 0x0B +#define SPI_FLASH_FAST_READ_DUMMY 0x01 +#define SPI_FLASH_FAST_READ_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_PP 0x02 +#define SPI_FLASH_PP_DUMMY 0x00 +#define SPI_FLASH_PP_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_PAGE_SIZE 256 +#define SPI_FLASH_SE 0x20 +#define SPI_FLASH_SE_DUMMY 0x00 +#define SPI_FLASH_SE_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_BE32K 0x52 +#define SPI_FLASH_BE32K_DUMMY 0x00 +#define SPI_FLASH_BE32K_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_BE 0xD8 +#define SPI_FLASH_BE_DUMMY 0x00 +#define SPI_FLASH_BE_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_CE 0x60 +#define SPI_FLASH_CE_DUMMY 0x00 +#define SPI_FLASH_CE_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_RDID 0x9F +#define SPI_FLASH_RDID_DUMMY 0x00 +#define SPI_FLASH_RDID_ADDR_BYTES SPI_ADDR_3OR4BYTE + +/// +/// Register Setting Commands +/// +#define SPI_FLASH_WREN 0x06 +#define SPI_FLASH_WREN_DUMMY 0x00 +#define SPI_FLASH_WREN_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_WRDI 0x04 +#define SPI_FLASH_WRDI_DUMMY 0x00 +#define SPI_FLASH_WRDI_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_RDSR 0x05 +#define SPI_FLASH_RDSR_DUMMY 0x00 +#define SPI_FLASH_RDSR_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_SR_NOT_WIP 0x0 +#define SPI_FLASH_SR_WIP BIT0 +#define SPI_FLASH_SR_WEL BIT1 +#define SPI_FLASH_WRSR 0x01 +#define SPI_FLASH_WRSR_DUMMY 0x00 +#define SPI_FLASH_WRSR_ADDR_BYTES SPI_ADDR_3OR4BYTE +#define SPI_FLASH_WREN_50H 0x50 +#define SPI_FLASH_RDSFDP 0x5A +#define SPI_FLASH_RDSFDP_DUMMY 0x01 +#define SPI_FLASH_RDSFDP_ADDR_BYTES SPI_ADDR_3BYTE_ONLY +#define ERASE_TYPICAL_TIME_UNITS_MASK 0x60 +#define ERASE_TYPICAL_TIME_BIT_POSITION 5 +#define ERASE_TYPICAL_TIME_UNIT_1_MS_BITMAP 0x00 +#define ERASE_TYPICAL_TIME_UNIT_1_MS 1 +#define ERASE_TYPICAL_TIME_UNIT_16_MS_BITMAP 0x01 +#define ERASE_TYPICAL_TIME_UNIT_16_MS 16 +#define ERASE_TYPICAL_TIME_UNIT_128_MS_BITMAP 0x02 +#define ERASE_TYPICAL_TIME_UNIT_128_MS 128 +#define ERASE_TYPICAL_TIME_UNIT_1000_MS_BITMAP 0x03 +#define ERASE_TYPICAL_TIME_UNIT_1000_MS 1000 +#define ERASE_TYPICAL_TIME_COUNT_MASK 0x1f + +/// +/// Flash Device Configuration Detection Command descriptor. +/// +typedef struct { + // DWORD 1 + UINT32 DescriptorEnd : 1; ///< Descriptor Sequence End Indicator. + UINT32 DescriptorType : 1; ///< Descriptor Type. + UINT32 Reserve1 : 6; ///< Bit [7:2] is reserved. + UINT32 DetectionInstruction : 8; ///< Sector map configuration detection command. + UINT32 DetectionLatency : 4; ///< Configuration detection command read latency. + UINT32 Reserve2 : 2; ///< Bit [21:20] is reserved. + UINT32 DetectionCommandAddressLen : 2; ///< Configuration detection command address length. + UINT32 ReadDataMask : 8; ///< Bit mask of the interst bit of the returned + ///< byte read from the detection command. + // DWORD 2 + UINT32 CommandAddress : 32; ///< Sector map configuration detection command address. +} SFDP_SECTOR_CONFIGURATION_COMMAND; + +#define SFDP_SECTOR_MAP_TABLE_ENTRY_TYPE_COMMAND 0 +#define SFDP_SECTOR_MAP_TABLE_ENTRY_TYPE_MAP 1 +#define SFDP_SECTOR_MAP_TABLE_ENTRY_LAST 1 + +/// +/// Definition of Configuration detection command address length. +/// +typedef enum { + SpdfConfigurationCommandAddressNone = 0, + SpdfConfigurationCommandAddress3Byte = 1, + SpdfConfigurationCommandAddress4Byte = 2, + SpdfConfigurationCommandAddressVariable = 3 +} SPDF_CONFIGURATION_COMMAND_ADDR_LENGTH; + +/// +/// Flash Device Configuration Map descriptor. +/// +typedef struct { + // DWORD 1 + UINT32 DescriptorEnd : 1; ///< Descriptor Sequence End Indicator. + UINT32 DescriptorType : 1; ///< Descriptor Type. + UINT32 Reserve1 : 6; ///< Bit [7:2] is reserved. + UINT32 ConfigurationID : 8; ///< ID of this configuration. + UINT32 RegionCount : 8; ///< The region count of this configuration. + UINT32 Reserve2 : 8; ///< [31:24] is reserved. +} SFDP_SECTOR_CONFIGURATION_MAP; + +typedef struct { + UINT32 DescriptorEnd : 1; ///< Descriptor Sequence End Indicator. + UINT32 DescriptorType : 1; ///< Descriptor Type. +} SFDP_SECTOR_CONFIGURATION_GENERIC_HEADER; + +/// +/// Flash Device Region Definition. +/// +typedef struct _SFDP_SECTOR_REGION { + // DWORD 1 + UINT32 EraseType1 : 1; ///< Earse type 1 is supported. + UINT32 EraseType2 : 1; ///< Earse type 2 is supported. + UINT32 EraseType3 : 1; ///< Earse type 3 is supported. + UINT32 EraseType4 : 1; ///< Earse type 4 is supported. + UINT32 Reserve1 : 4; ///< Bit [7:4] is reserved. + UINT32 RegionSize : 24; ///< Region size in 256 Byte unit. +} SFDP_SECTOR_REGION; +#define SFDP_SECTOR_REGION_SIZE_UNIT 256 + +/// +/// Sector Map Table structure, the entry could be +/// either Configuration Detection Command descriptor, +/// or Configuration Map descriptor. +/// +typedef union _SFDP_SECTOR_MAP_TABLE { + SFDP_SECTOR_CONFIGURATION_GENERIC_HEADER GenericHeader; + SFDP_SECTOR_CONFIGURATION_COMMAND ConfigurationCommand; ///< Fash configuration detection command. + SFDP_SECTOR_CONFIGURATION_MAP ConfigurationMap; ///< Flash map descriptor. +} SFDP_SECTOR_MAP_TABLE; + +#endif // SPI_NOR_FLASH_JEDEC_H_ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiConfiguration.h b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiConfiguration.h new file mode 100644 index 0000000000000000000000000000000000000000..5d447213c34b1d3fbe88bc23745f28bb8d9b7e36 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiConfiguration.h @@ -0,0 +1,295 @@ +/** @file + This file defines the SPI Configuration Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_CONFIGURATION_PROTOCOL_H__ +#define __SPI_CONFIGURATION_PROTOCOL_H__ + +/// +/// Global ID for the SPI Configuration Protocol +/// +#define EFI_SPI_CONFIGURATION_GUID \ + { 0x85a6d3e6, 0xb65b, 0x4afc, \ + { 0xb3, 0x8f, 0xc6, 0xd5, 0x4a, 0xf6, 0xdd, 0xc8 }} + +/// +/// Macros to easily specify frequencies in hertz, kilohertz and megahertz. +/// +#define Hz(Frequency) (Frequency) +#define KHz(Frequency) (1000 * Hz (Frequency)) +#define MHz(Frequency) (1000 * KHz (Frequency)) + +typedef struct _EFI_SPI_PERIPHERAL EFI_SPI_PERIPHERAL; + +/** + Manipulate the chip select for a SPI device. + + This routine must be called at or below TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. + The SPI bus layer calls this routine either in the board layer or in the SPI + controller to manipulate the chip select pin at the start and end of a SPI + transaction. + + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set successfully + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The SpiPeripheral->ChipSelectParameter value + is invalid + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_CHIP_SELECT)( + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine must be called at or below TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The clock + generator will choose a supported clock frequency + which is less then or equal to this value. + Specify zero to turn the clock generator off. + The actual clock frequency supported by the clock + generator will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by CLockHz + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_CLOCK)( + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/// +/// The EFI_SPI_PART data structure provides a description of a SPI part which +/// is independent of the use on the board. This data is available directly +/// from the part's datasheet and may be provided by the vendor. +/// +typedef struct _EFI_SPI_PART { + /// + /// A Unicode string specifying the SPI chip vendor. + /// + CONST CHAR16 *Vendor; + + /// + /// A Unicode string specifying the SPI chip part number. + /// + CONST CHAR16 *PartNumber; + + /// + /// The minimum SPI bus clock frequency used to access this chip. This value + /// may be specified in the chip's datasheet. If not, use the value of zero. + /// + UINT32 MinClockHz; + + /// + /// The maximum SPI bus clock frequency used to access this chip. This value + /// is found in the chip's datasheet. + /// + UINT32 MaxClockHz; + + /// + /// Specify the polarity of the chip select pin. This value can be found in + /// the SPI chip's datasheet. Specify TRUE when a one asserts the chip select + /// and FALSE when a zero asserts the chip select. + /// + BOOLEAN ChipSelectPolarity; +} EFI_SPI_PART; + +/// +/// The EFI_SPI_BUS data structure provides the connection details between the +/// physical SPI bus and the EFI_SPI_HC_PROTOCOL instance which controls that +/// SPI bus. This data structure also describes the details of how the clock is +/// generated for that SPI bus. Finally this data structure provides the list +/// of physical SPI devices which are attached to the SPI bus. +/// +typedef struct _EFI_SPI_BUS { + /// + /// A Unicode string describing the SPI bus + /// + CONST CHAR16 *FriendlyName; + + /// + /// Address of the first EFI_SPI_PERIPHERAL data structure connected to this + /// bus. Specify NULL if there are no SPI peripherals connected to this bus. + /// + CONST EFI_SPI_PERIPHERAL *Peripherallist; + + /// + /// Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely + /// describes the SPI controller. + /// + CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath; + + /// + /// Address of the routine which controls the clock used by the SPI bus for + /// this SPI peripheral. The SPI host co ntroller's clock routine is called + /// when this value is set to NULL. + /// + EFI_SPI_CLOCK Clock; + + /// + /// Address of a data structure containing the additional values which + /// describe the necessary control for the clock. When Clock is NULL, + /// the declaration for this data structure is provided by the vendor of the + /// host's SPI controller driver. When Clock is not NULL, the declaration for + /// this data structure is provided by the board layer. + /// + VOID *ClockParameter; +} EFI_SPI_BUS; + +/// +/// Definitions of SPI Part Attributes. +/// +#define SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0 +#define SPl_PART_SUPPORTS_4_B1T_DATA_BUS_WIDTH BIT1 +#define SPl_PART_SUPPORTS_8_B1T_DATA_BUS_WIDTH BIT2 + +/// +/// The EFI_SPI_PERIPHERAL data structure describes how a specific block of +/// logic which is connected to the SPI bus. This data structure also selects +/// which upper level driver is used to manipulate this SPI device. +/// The SpiPeripheraLDriverGuid is available from the vendor of the SPI +/// peripheral driver. +/// +struct _EFI_SPI_PERIPHERAL { + /// + /// Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if + /// the current data structure is the last one on the SPI bus. + /// + CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral; + + /// + /// A unicode string describing the function of the SPI part. + /// + CONST CHAR16 *FriendlyName; + + /// + /// Address of a GUID provided by the vendor of the SPI peripheral driver. + /// Instead of using a " EFI_SPI_IO_PROTOCOL" GUID, the SPI bus driver uses + /// this GUID to identify an EFI_SPI_IO_PROTOCOL data structure and to + /// provide the connection points for the SPI peripheral drivers. + /// This reduces the comparison logic in the SPI peripheral driver's + /// Supported routine. + /// + CONST GUID *SpiPeripheralDriverGuid; + + /// + /// The address of an EFI_SPI_PART data structure which describes this chip. + /// + CONST EFI_SPI_PART *SpiPart; + + /// + /// The maximum clock frequency is specified in the EFI_SPI_P ART. When this + /// this value is non-zero and less than the value in the EFI_SPI_PART then + /// this value is used for the maximum clock frequency for the SPI part. + /// + UINT32 MaxClockHz; + + /// + /// Specify the idle value of the clock as found in the datasheet. + /// Use zero (0) if the clock'S idle value is low or one (1) if the the + /// clock's idle value is high. + /// + BOOLEAN ClockPolarity; + + /// + /// Specify the clock delay after chip select. Specify zero (0) to delay an + /// entire clock cycle or one (1) to delay only half a clock cycle. + /// + BOOLEAN ClockPhase; + + /// + /// SPI peripheral attributes, select zero or more of: + /// * SPI_PART_SUPPORTS_2_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to + /// support a 2-bit data bus + /// * SPI_PART_SUPPORTS_4_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to + /// support a 4-bit data bus + /// + UINT32 Attributes; + + /// + /// Address of a vendor specific data structure containing additional board + /// configuration details related to the SPI chip. The SPI peripheral layer + /// uses this data structure when configuring the chip. + /// + CONST VOID *ConfigurationData; + + /// + /// The address of an EFI_SPI_BUS data structure which describes the SPI bus + /// to which this chip is connected. + /// + CONST EFI_SPI_BUS *SpiBus; + + /// + /// Address of the routine which controls the chip select pin for this SPI + /// peripheral. Call the SPI host controller's chip select routine when this + /// value is set to NULL. + /// + EFI_SPI_CHIP_SELECT ChipSelect; + + /// + /// Address of a data structure containing the additional values which + /// describe the necessary control for the chip select. When ChipSelect is + /// NULL, the declaration for this data structure is provided by the vendor + /// of the host's SPI controller driver. The vendor's documentation specifies + /// the necessary values to use for the chip select pin selection and + /// control. When Chipselect is not NULL, the declaration for this data + /// structure is provided by the board layer. + /// + VOID *ChipSelectParameter; +}; + +/// +/// Describe the details of the board's SPI busses to the SPI driver stack. +/// The board layer uses the EFI_SPI_CONFIGURATION_PROTOCOL to expose the data +/// tables which describe the board's SPI busses, The SPI bus layer uses these +/// tables to configure the clock, chip select and manage the SPI transactions +/// on the SPI controllers. +/// +typedef struct _EFI_SPI_CONFIGURATION_PROTOCOL { + /// + /// The number of SPI busses on the board. + /// + UINT32 BusCount; + + /// + /// The address of an array of EFI_SPI_BUS data structure addresses. + /// + CONST EFI_SPI_BUS *CONST *CONST Buslist; +} EFI_SPI_CONFIGURATION_PROTOCOL; + +extern EFI_GUID gEfiSpiConfigurationProtocolGuid; + +#endif // __SPI_CONFIGURATION_PROTOCOL_H__ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiHc.h b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiHc.h new file mode 100644 index 0000000000000000000000000000000000000000..b6b5fc8530faf9bc005eb0d6f8b3f40dd14cd39e --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiHc.h @@ -0,0 +1,202 @@ +/** @file + This file defines the SPI Host Controller Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_HC_PROTOCOL_H__ +#define __SPI_HC_PROTOCOL_H__ + +#include +#include + +/// +/// Global ID for the SPI Host Controller Protocol +/// +#define EFI_SPI_HOST_GUID \ + { 0xc74e5db2, 0xfa96, 0x4ae2, \ + { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }} + +/// +/// EDK2-style name +/// +#define EFI_SPI_HC_PROTOCOL_GUID EFI_SPI_HOST_GUID + +typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL; + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT)( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK)( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION)( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ); + +/// +/// Definitions of SPI Host Controller Attributes. +/// +#define HC_SUPPORTS_WRITE_ONLY_OPERATIONS BIT0 +#define HC_SUPPORTS_READ_ONLY_OPERATIONS BIT1 +#define HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS BIT2 +#define HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT3 +#define HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT4 +#define HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT5 +#define HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT6 +#define HC_SUPPORTS_8_BIT_DATA_BUS_WIDTH BIT7 +#define HC_TRANSFER_SIZE_INCLUDES_OPCODE BIT8 +#define HC_TRANSFER_SIZE_INCLUDES_ADDRESS BIT9 +/// +/// Support a SPI data transaction between the SPI controller and a SPI chip. +/// +struct _EFI_SPI_HC_PROTOCOL { + /// + /// Host control attributes, may have zero or more of the following set: + /// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS + /// * HC_SUPPORTS_READ_ONLY_OPERATIONS + /// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS + /// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS + /// - The SPI host controller requires the transmit frame to be in most + /// significant bits instead of least significant bits.The host driver + /// will adjust the frames if necessary. + /// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS + /// - The SPI host controller places the receive frame to be in most + /// significant bits instead of least significant bits.The host driver + /// will adjust the frames to be in the least significant bits if + /// necessary. + /// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH + /// - The SPI controller supports a 2 - bit data bus + /// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH + /// - The SPI controller supports a 4 - bit data bus + /// * HC_TRANSFER_SIZE_INCLUDES_OPCODE + /// - Transfer size includes the opcode byte + /// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS + /// - Transfer size includes the 3 address bytes + /// The SPI host controller must support full - duplex (receive while + /// sending) operation.The SPI host controller must support a 1 - bit bus + /// width. + /// + UINT32 Attributes; + + /// + /// Mask of frame sizes which the SPI host controller supports. Frame size of + /// N-bits is supported when bit N-1 is set. The host controller must support + /// a frame size of 8-bits. + /// + UINT32 FrameSizeSupportMask; + + /// + /// Maximum transfer size in bytes: 1 - Oxffffffff + /// + UINT32 MaximumTransferBytes; + + /// + /// Assert or deassert the SPI chip select. + /// + EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect; + + /// + /// Set up the clock generator to produce the correct clock frequency, phase + /// and polarity for a SPI chip. + /// + EFI_SPI_HC_PROTOCOL_CLOCK Clock; + + /// + /// Perform the SPI transaction on the SPI peripheral using the SPI host + /// controller. + /// + EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction; +}; + +extern EFI_GUID gEfiSpiHcProtocolGuid; + +#endif // __SPI_HC_PROTOCOL_H__ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiIo.h b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiIo.h new file mode 100644 index 0000000000000000000000000000000000000000..8d0eade05abfee9978cd923a864d67ade60bc9ef --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Protocol/SpiIo.h @@ -0,0 +1,296 @@ +/** @file + This file defines the SPI I/O Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_IO_PROTOCOL_H__ +#define __SPI_IO_PROTOCOL_H__ + +#include +#include + +typedef struct _EFI_SPI_IO_PROTOCOL EFI_SPI_IO_PROTOCOL; + +/// +/// Note: The UEFI PI 1.6 specification does not specify values for the +/// members below. The order matches the specification. +/// +typedef enum { + /// + /// Data flowing in both direction between the host and + /// SPI peripheral.ReadBytes must equal WriteBytes and both ReadBuffer and + /// WriteBuffer must be provided. + /// + SPI_TRANSACTION_FULL_DUPLEX, + + /// + /// Data flowing from the host to the SPI peripheral.ReadBytes must be + /// zero.WriteBytes must be non - zero and WriteBuffer must be provided. + /// + SPI_TRANSACTION_WRITE_ONLY, + + /// + /// Data flowing from the SPI peripheral to the host.WriteBytes must be + /// zero.ReadBytes must be non - zero and ReadBuffer must be provided. + /// + SPI_TRANSACTION_READ_ONLY, + + /// + /// Data first flowing from the host to the SPI peripheral and then data + /// flows from the SPI peripheral to the host.These types of operations get + /// used for SPI flash devices when control data (opcode, address) must be + /// passed to the SPI peripheral to specify the data to be read. + /// + SPI_TRANSACTION_WRITE_THEN_READ +} EFI_SPI_TRANSACTION_TYPE; + +/** + Initiate a SPI transaction between the host and a SPI peripheral. + + This routine must be called at or below TPL_NOTIFY. + This routine works with the SPI bus layer to pass the SPI transaction to the + SPI controller for execution on the SPI bus. There are four types of + supported transactions supported by this routine: + * Full Duplex: WriteBuffer and ReadBuffer are the same size. + * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0 + * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0 + * Write Then Read: WriteBuffer contains control data to write to SPI + peripheral before data is placed into the ReadBuffer. + Both WriteBytes and ReadBytes must be non-zero. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] TransactionType Type of SPI transaction. + @param[in] DebugTransaction Set TRUE only when debugging is desired. + Debugging may be turned on for a single SPI + transaction. Only this transaction will display + debugging messages. All other transactions with + this value set to FALSE will not display any + debugging messages. + @param[in] ClockHz Specify the ClockHz value as zero (0) to use + the maximum clock frequency supported by the + SPI controller and part. Specify a non-zero + value only when a specific SPI transaction + requires a reduced clock rate. + @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4 + @param[in] FrameSize Frame size in bits, range: 1 - 32 + @param[in] WriteBytes The length of the WriteBuffer in bytes. + Specify zero for read-only operations. + @param[in] WriteBuffer The buffer containing data to be sent from the + host to the SPI chip. Specify NULL for read + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The transmit frame is in the least + significant N bits. + @param[in] ReadBytes The length of the ReadBuffer in bytes. + Specify zero for write-only operations. + @param[out] ReadBuffer The buffer to receeive data from the SPI chip + during the transaction. Specify NULL for write + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The received frame is in the least + significant N bits. + + @retval EFI_SUCCESS The SPI transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The writeBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION)( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN EFI_SPI_TRANSACTION_TYPE TransactionType, + IN BOOLEAN DebugTransaction, + IN UINT32 ClockHz OPTIONAL, + IN UINT32 BusWidth, + IN UINT32 FrameSize, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT32 ReadBytes, + OUT UINT8 *ReadBuffer + ); + +/** + Update the SPI peripheral associated with this SPI 10 instance. + + Support socketed SPI parts by allowing the SPI peripheral driver to replace + the SPI peripheral after the connection is made. An example use is socketed + SPI NOR flash parts, where the size and parameters change depending upon + device is in the socket. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure. + + @retval EFI_SUCCESS The SPI peripheral was updated successfully + @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL, + or the SpiPeripheral->SpiBus is NULL, + or the SpiP eripheral - >SpiBus pointing at + wrong bus, + or the SpiP eripheral - >SpiPart is NULL + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL)( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral + ); + +/// +/// The EFI_SPI_BUS_ TRANSACTION data structure contains the description of the +/// SPI transaction to perform on the host controller. +/// +typedef struct _EFI_SPI_BUS_TRANSACTION { + /// + /// Pointer to the SPI peripheral being manipulated. + /// + CONST EFI_SPI_PERIPHERAL *SpiPeripheral; + + /// + /// Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE + /// values. + /// + EFI_SPI_TRANSACTION_TYPE TransactionType; + + /// + /// TRUE if the transaction is being debugged. Debugging may be turned on for + /// a single SPI transaction. Only this transaction will display debugging + /// messages. All other transactions with this value set to FALSE will not + /// display any debugging messages. + /// + BOOLEAN DebugTransaction; + + /// + /// SPI bus width in bits: 1, 2, 4 + /// + UINT32 BusWidth; + + /// + /// Frame size in bits, range: 1 - 32 + /// + UINT32 FrameSize; + + /// + /// Length of the write buffer in bytes + /// + UINT32 WriteBytes; + + /// + /// Buffer containing data to send to the SPI peripheral + /// Frame sizes 1 - 8 bits: UINT8 (one byte) per frame + /// Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame + /// + UINT8 *WriteBuffer; + + /// + /// Length of the read buffer in bytes + /// + UINT32 ReadBytes; + + /// + /// Buffer to receive the data from the SPI peripheral + /// * Frame sizes 1 - 8 bits: UINT8 (one byte) per frame + /// * Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame + /// * Frame sizes 17 - 32 bits : UINT32 (four bytes) per frame + /// + UINT8 *ReadBuffer; +} EFI_SPI_BUS_TRANSACTION; + +/// +/// Definitions of SPI I/O Attributes. +/// +#define SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0 +#define SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT1 +#define SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH BIT2 +#define SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE BIT3 +#define SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS BIT4 + +/// +/// Support managed SPI data transactions between the SPI controller and a SPI +/// chip. +/// +struct _EFI_SPI_IO_PROTOCOL { + /// + /// Address of an EFI_SPI_PERIPHERAL data structure associated with this + /// protocol instance. + /// + CONST EFI_SPI_PERIPHERAL *SpiPeripheral; + + /// + /// Address of the original EFI_SPI_PERIPHERAL data structure associated with + /// this protocol instance. + /// + CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral; + + /// + /// Mask of frame sizes which the SPI 10 layer supports. Frame size of N-bits + /// is supported when bit N-1 is set. The host controller must support a + /// frame size of 8-bits. Frame sizes of 16, 24 and 32-bits are converted to + /// 8-bit frame sizes by the SPI bus layer if the frame size is not supported + /// by the SPI host controller. + /// + UINT32 FrameSizeSupportMask; + + /// + /// Maximum transfer size in bytes: 1 - Oxffffffff + /// + UINT32 MaximumTransferBytes; + + /// + /// Transaction attributes: One or more from: + /// * SPI_10_SUPPORTS_2_B1T_DATA_BUS_W1DTH + /// - The SPI host and peripheral supports a 2-bit data bus + /// * SPI_IO_SUPPORTS_4_BIT_DATA_BUS_W1DTH + /// - The SPI host and peripheral supports a 4-bit data bus + /// * SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE + /// - Transfer size includes the opcode byte + /// * SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS + /// - Transfer size includes the 3 address bytes + /// + UINT32 Attributes; + + /// + /// Pointer to legacy SPI controller protocol + /// + CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol; + + /// + /// Initiate a SPI transaction between the host and a SPI peripheral. + /// + EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction; + + /// + /// Update the SPI peripheral associated with this SPI 10 instance. + /// + EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral; +}; + +#endif // __SPI_IO_PROTOCOL_H__ diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Register/Amd/Fam17Msr.h b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Register/Amd/Fam17Msr.h new file mode 100644 index 0000000000000000000000000000000000000000..8079d5fc3787cbf0619d31d65df28f3aa52f574c --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -0,0 +1,143 @@ +/** @file + MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2025, Advanced Micro Devices. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 + +**/ + +#ifndef __FAM17_MSR_H__ +#define __FAM17_MSR_H__ + +/** + Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register + +**/ +#define MSR_SEV_ES_GHCB 0xc0010130 + +#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register +#define MSR_CPUID_NAME_STRING1 0xC0010031ul +#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING3 0xC0010033ul +#define MSR_CPUID_NAME_STRING4 0xC0010034ul +#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register + +/** + MSR information returned for #MSR_SEV_ES_GHCB +**/ +typedef union { + struct { + UINT32 Function : 12; + UINT32 Reserved1 : 20; + UINT32 Reserved2 : 32; + } GhcbInfo; + + struct { + UINT8 Reserved[3]; + UINT8 SevEncryptionBitPos; + UINT16 SevEsProtocolMin; + UINT16 SevEsProtocolMax; + } GhcbProtocol; + + struct { + UINT32 Function : 12; + UINT32 ReasonCodeSet : 4; + UINT32 ReasonCode : 8; + UINT32 Reserved1 : 8; + UINT32 Reserved2 : 32; + } GhcbTerminate; + + struct { + UINT64 Function : 12; + UINT64 Features : 52; + } GhcbHypervisorFeatures; + + struct { + UINT64 Function : 12; + UINT64 GuestFrameNumber : 52; + } GhcbGpaRegister; + + struct { + UINT64 Function : 12; + UINT64 GuestFrameNumber : 40; + UINT64 Operation : 4; + UINT64 Reserved : 8; + } SnpPageStateChangeRequest; + + struct { + UINT32 Function : 12; + UINT32 Reserved : 20; + UINT32 ErrorCode; + } SnpPageStateChangeResponse; + + VOID *Ghcb; + + UINT64 GhcbPhysicalAddress; +} MSR_SEV_ES_GHCB_REGISTER; + +#define GHCB_INFO_SEV_INFO 1 +#define GHCB_INFO_SEV_INFO_GET 2 +#define GHCB_INFO_CPUID_REQUEST 4 +#define GHCB_INFO_CPUID_RESPONSE 5 +#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18 +#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE 19 +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20 +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE 21 +#define GHCB_HYPERVISOR_FEATURES_REQUEST 128 +#define GHCB_HYPERVISOR_FEATURES_RESPONSE 129 +#define GHCB_INFO_TERMINATE_REQUEST 256 + +#define GHCB_TERMINATE_GHCB 0 +#define GHCB_TERMINATE_GHCB_GENERAL 0 +#define GHCB_TERMINATE_GHCB_PROTOCOL 1 + +/** + Secure Encrypted Virtualization (SEV) status register + +**/ +#define MSR_SEV_STATUS 0xc0010131 + +/** + MSR information returned for #MSR_SEV_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled + /// + UINT32 SevBit : 1; + + /// + /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled + /// + UINT32 SevEsBit : 1; + + /// + /// [Bit 2] Secure Nested Paging (SevSnp) is enabled + /// + UINT32 SevSnpBit : 1; + + UINT32 Reserved2 : 29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SEV_STATUS_REGISTER; + +#endif diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..6accc1259cb9f6a6eda2322fbfb4dc8d62428b8a --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf @@ -0,0 +1,48 @@ +## @file +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +## @file +# Instance of PCI Express Library using the 256 MB PCI Express MMIO window. +# +# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform +# PCI Configuration cycles. Layers on top of an I/O Library instance. +# +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved. +# Portions copyright (c) 2016, American Megatrends, Inc. All rights reserved. +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmPciExpressLib + FILE_GUID = 00D24382-8231-4B18-A4F0-2D94D8FE2E81 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciExpressLib|DXE_SMM_DRIVER SMM_CORE + CONSTRUCTOR = SmmPciExpressLibConstructor + +[Sources] + PciExpressLib.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + PcdLib + DebugLib + IoLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/MdePkg.dec b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/MdePkg.dec new file mode 100644 index 0000000000000000000000000000000000000000..a0e006bd42077392b1564b1a75eb4dba44cd8435 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/MdePkg.dec @@ -0,0 +1,2549 @@ +## @file MdePkg.dec +# This Package provides all definitions, library classes and libraries instances. +# +# It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of +# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards. +# +# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+# Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = MdePkg + PACKAGE_UNI_FILE = MdePkg.uni + PACKAGE_GUID = 1E73767F-8F52-4603-AEB4-F29B510B6766 + PACKAGE_VERSION = 1.08 + + +[Includes] + Include + Test/UnitTest/Include + Test/Mock/Include + Library/MipiSysTLib/mipisyst/library/include + +[Includes.IA32] + Include/Ia32 + +[Includes.X64] + Include/X64 + +[Includes.EBC] + Include/Ebc + +[Includes.ARM] + Include/Arm + +[Includes.AARCH64] + Include/AArch64 + +[Includes.RISCV64] + Include/RiscV64 + +[Includes.LOONGARCH64] + Include/LoongArch64 + +[LibraryClasses] + ## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec + # and the standard requests defined in Usb 1.1 spec. + ## + UefiUsbLib|Include/Library/UefiUsbLib.h + + ## @libraryclass Provides a service to retrieve a pointer to the EFI Runtime Services Table. + # Only available to DXE and UEFI module types. + UefiRuntimeServicesTableLib|Include/Library/UefiRuntimeServicesTableLib.h + + ## @libraryclass Provides library functions for each of the UEFI Runtime Services. + # Only available to DXE and UEFI module types. + UefiRuntimeLib|Include/Library/UefiRuntimeLib.h + + ## @libraryclass Provides library functions for common UEFI operations. + # Only available to DXE and UEFI module types. + ## + UefiLib|Include/Library/UefiLib.h + + ## @libraryclass Module entry point library for UEFI drivers, DXE Drivers, DXE SMM Driver and DXE Runtime Drivers + UefiDriverEntryPoint|Include/Library/UefiDriverEntryPoint.h + + ## @libraryclass UEFI Decompress Library Functions defintion for UEFI compress algorithm. + UefiDecompressLib|Include/Library/UefiDecompressLib.h + + ## @libraryclass Provides a service to retrieve a pointer to the EFI Boot Services Table. + # Only available to DXE and UEFI module types. + UefiBootServicesTableLib|Include/Library/UefiBootServicesTableLib.h + + ## @libraryclass Module entry point library for UEFI Applications. + UefiApplicationEntryPoint|Include/Library/UefiApplicationEntryPoint.h + + ## @libraryclass Provides calibrated delay and performance counter services. + TimerLib|Include/Library/TimerLib.h + + ## @libraryclass Provides library functions to access SMBUS devices. + # Libraries of this class must be ported to a specific SMBUS controller. + SmbusLib|Include/Library/SmbusLib.h + + ## @libraryclass Provides the functions to submit Scsi commands defined in SCSI-2 specification for scsi device. + UefiScsiLib|Include/Library/UefiScsiLib.h + + ## @libraryclass Provides a service to publish discovered system resources. + ResourcePublicationLib|Include/Library/ResourcePublicationLib.h + + ## @libraryclass Provides services to log status code records. + ReportStatusCodeLib|Include/Library/ReportStatusCodeLib.h + + ## @libraryclass Provides services to print a formatted string to a buffer. + # All combinations of Unicode and ASCII strings are supported. + ## + PrintLib|Include/Library/PrintLib.h + + ## @libraryclass Provides an ordered collection data structure. + OrderedCollectionLib|Include/Library/OrderedCollectionLib.h + + ## @libraryclass Provides services to send progress/error codes to a POST card. + PostCodeLib|Include/Library/PostCodeLib.h + + ## @libraryclass Provides services to log the execution times and retrieve them later. + PerformanceLib|Include/Library/PerformanceLib.h + + ## @libraryclass Provides a service to retrieve a pointer to the PEI Services Table. + PeiServicesTablePointerLib|Include/Library/PeiServicesTablePointerLib.h + + ## @libraryclass Provides library functions for all PEI Services. + PeiServicesLib|Include/Library/PeiServicesLib.h + + ## @libraryclass Module entry point library for PEIM. + PeimEntryPoint|Include/Library/PeimEntryPoint.h + + ## @libraryclass Module entry point library for PEI core. + PeiCoreEntryPoint|Include/Library/PeiCoreEntryPoint.h + + ## @libraryclass Provides services to load and relocate a PE/COFF image. + PeCoffLib|Include/Library/PeCoffLib.h + ## @libraryclass Provides extra action services for unloading and relocating a PE/COFF image on some specific platform such + ## as NT32 emulator. + PeCoffExtraActionLib|Include/Library/PeCoffExtraActionLib.h + + ## @libraryclass Provides a service to retrieve the PE/COFF entry point from a PE/COFF image. + PeCoffGetEntryPointLib|Include/Library/PeCoffGetEntryPointLib.h + + ## @libraryclass Provides services to return the PCI segment information. + PciSegmentInfoLib|Include/Library/PciSegmentInfoLib.h + + ## @libraryclass Provides services to access PCI Configuration Space on a platform with multiple PCI segments. + PciSegmentLib|Include/Library/PciSegmentLib.h + + ## @libraryclass The multiple segments PCI configuration Library Services that carry out + ## PCI configuration and enable the PCI operations to be replayed during an + ## S3 resume. This library class maps directly on top of the PciSegmentLib class. + S3PciSegmentLib|Include/Library/S3PciSegmentLib.h + + ## @libraryclass Provides services to access PCI Configuration Space. + PciLib|Include/Library/PciLib.h + + ## @libraryclass Provides services to access PCI Configuration Space using the MMIO PCI Express window. + PciExpressLib|Include/Library/PciExpressLib.h + + ## @libraryclass Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC. + PciCf8Lib|Include/Library/PciCf8Lib.h + + ## @libraryclass Provides library services to get and set Platform Configuration Database entries. + PcdLib|Include/Library/PcdLib.h + + ## @libraryclass Provides services to allocate and free memory buffers of various memory types and alignments. + MemoryAllocationLib|Include/Library/MemoryAllocationLib.h + + ## @libraryclass Provide services to access I/O Ports and MMIO registers. + IoLib|Include/Library/IoLib.h + + ## @libraryclass Provide services to create, get and update HSTI table in AIP protocol. + HstiLib|Include/Library/HstiLib.h + + ## @libraryclass Provides services to create and parse HOBs. Only available for PEI and DXE module types. + HobLib|Include/Library/HobLib.h + + ## @libraryclass Provides a service to retrieve a pointer to the DXE Services Table. + # Only available to DXE module types. + ## + DxeServicesTableLib|Include/Library/DxeServicesTableLib.h + + ## @libraryclass Module entry point library for DXE core. + DxeCoreEntryPoint|Include/Library/DxeCoreEntryPoint.h + + ## @libraryclass Provides library functions to construct and parse UEFI Device Paths. + DevicePathLib|Include/Library/DevicePathLib.h + + ## @libraryclass Provides services to print debug and assert messages to a debug output device. + DebugLib|Include/Library/DebugLib.h + + ## @libraryclass Provides CPU architecture specific functions that can not be defined in the Base Library + # due to dependencies on the PAL Library + ## + CpuLib|Include/Library/CpuLib.h + + ## @libraryclass Provides services to maintain instruction and data caches. + CacheMaintenanceLib|Include/Library/CacheMaintenanceLib.h + + ## @libraryclass Provides copy memory, fill memory, zero memory, and GUID functions. + BaseMemoryLib|Include/Library/BaseMemoryLib.h + + ## @libraryclass Provides string functions, linked list functions, math functions, synchronization functions + # and CPU architecture specific functions. + ## + BaseLib|Include/Library/BaseLib.h + + ## @libraryclass This library provides common functions to process the different guided section data. + ExtractGuidedSectionLib|Include/Library/ExtractGuidedSectionLib.h + + ## @libraryclass Provides three common serial I/O port functions. + SerialPortLib|Include/Library/SerialPortLib.h + + ## @libraryclass Provides a set of PI library functions and macros for DXE phase. + DxeServicesLib|Include/Library/DxeServicesLib.h + + ## @libraryclass Provides synchronization functions. + ## + SynchronizationLib|Include/Library/SynchronizationLib.h + + ## @libraryclass Defines library APIs used by modules to save S3 Boot + # Script Opcodes. These OpCode will be restored by S3 + # related modules. + S3BootScriptLib|Include/Library/S3BootScriptLib.h + + ## @libraryclass I/O and MMIO Library Services that do I/O and also enable + # the I/O operatation to be replayed during an S3 resume. + # This library class maps directly on top of the IoLib class. + S3IoLib|Include/Library/S3IoLib.h + + ## @libraryclass PCI configuration Library Services that do PCI configuration + # and also enable the PCI operations to be replayed during an + # S3 resume. This library class maps directly on top of the + # PciLib class. + S3PciLib|Include/Library/S3PciLib.h + + ## @libraryclass Smbus Library Services that do SMBus transactions and also + # enable the operatation to be replayed during an S3 resume. + # This library class maps directly on top of the SmbusLib class. + S3SmbusLib|Include/Library/S3SmbusLib.h + + ## @libraryclass Stall Services that do stall and also enable the Stall + # operatation to be replayed during an S3 resume. This + # library class maps directly on top of the Timer class. + S3StallLib|Include/Library/S3StallLib.h + + ## @libraryclass Defines library APIs used by modules to get/set print error level. + DebugPrintErrorLevelLib|Include/Library/DebugPrintErrorLevelLib.h + + ## @libraryclass provides EFI_FILE_HANDLE services + FileHandleLib|Include/Library/FileHandleLib.h + + ## @libraryclass provides helper functions to prevent integer overflow during + # type conversion, addition, subtraction, and multiplication. + ## + SafeIntLib|Include/Library/SafeIntLib.h + + ## @libraryclass Provides a service to retrieve a pointer to the Standalone MM Services Table. + # Only available to MM_STANDALONE, SMM/DXE Combined and SMM module types. + MmServicesTableLib|Include/Library/MmServicesTableLib.h + + ## @libraryclass Module entry point library for standalone MM drivers. + StandaloneMmDriverEntryPoint|Include/Library/StandaloneMmDriverEntryPoint.h + + ## @libraryclass Provides a unit test framework + # + UnitTestLib|Include/Library/UnitTestLib.h + + ## @libraryclass Provides service to get the manufacturer given JEP106 bytes. + JedecJep106Lib|Include/Library/JedecJep106Lib.h + + ## @libraryclass Extension to BaseLib for host based unit tests that allows a + # subset of BaseLib services to be hooked for emulation. + # + UnitTestHostBaseLib|Test/UnitTest/Include/Library/UnitTestHostBaseLib.h + + ## @libraryclass This library provides an interface to request non-MMRAM pages to be mapped + # or unblocked from inside MM environment. + # + MmUnblockMemoryLib|Include/Library/MmUnblockMemoryLib.h + + ## @libraryclass This library provides interfances to filter and trace port IO/MMIO/MSR access. + # + # + RegisterFilterLib|Include/Library/RegisterFilterLib.h + + ## @libraryclass This library provides interfances to probe ConfidentialComputing guest type. + # + # + CcProbeLib|Include/Library/CcProbeLib.h + + ## @libraryclass Provides function for SMM CPU Rendezvous Library. + SmmCpuRendezvousLib|Include/Library/SmmCpuRendezvousLib.h + + ## @libraryclass Provides services to generate Entropy using a TRNG. + # + ArmTrngLib|Include/Library/ArmTrngLib.h + + ## @libraryclass Provides APIs for third-party library libfdt. + # + FdtLib|Include/Library/FdtLib.h + + ## @libraryclass Provides general mipi sys-T services. + # + MipiSysTLib|Include/Library/MipiSysTLib.h + + ## @libraryclass Provides API to output Trace Hub debug message. + # + TraceHubDebugSysTLib|Include/Library/TraceHubDebugSysTLib.h + +[LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64] + ## @libraryclass Provides services to generate random number. + # + RngLib|Include/Library/RngLib.h + +[LibraryClasses.IA32, LibraryClasses.X64] + ## @libraryclass Abstracts both S/W SMI generation and detection. + ## + SmmLib|Include/Library/SmmLib.h + + ## @libraryclass Provides a service to retrieve a pointer to the SMM Services Table. + # Only available to SMM/DXE Combined and SMM module types. + SmmServicesTableLib|Include/Library/SmmServicesTableLib.h + + ## @libraryclass Provides services for Smm Memory Operation. + # + SmmMemLib|Include/Library/SmmMemLib.h + + ## @libraryclass Provides services for Smm IO Operation. + # + SmmIoLib|Include/Library/SmmIoLib.h + + ## @libraryclass Provides services to enable/disable periodic SMI handlers. + # + SmmPeriodicSmiLib|Include/Library/SmmPeriodicSmiLib.h + + ## @libraryclass Provides services to log the SMI handler registration. + SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h + + ## @libraryclass Provides function to support TDX processing. + TdxLib|Include/Library/TdxLib.h + +[LibraryClasses.RISCV64] + ## @libraryclass Provides function to make ecalls to SBI + BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h + +[Guids] + # + # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 + # + ## Include/Guid/GlobalVariable.h + gEfiGlobalVariableGuid = { 0x8BE4DF61, 0x93CA, 0x11D2, { 0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C }} + + ## Include/Guid/PcAnsi.h + gEfiVT100PlusGuid = { 0x7BAEC70B, 0x57E0, 0x4C76, { 0x8E, 0x87, 0x2F, 0x9E, 0x28, 0x08, 0x83, 0x43 }} + + ## Include/Guid/PcAnsi.h + gEfiVT100Guid = { 0xDFA66065, 0xB419, 0x11D3, { 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Guid/PcAnsi.h + gEfiPcAnsiGuid = { 0xE0C14753, 0xF9BE, 0x11D2, { 0x9A, 0x0C, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Guid/PcAnsi.h + gEfiVTUTF8Guid = { 0xAD15A0D6, 0x8BEC, 0x4ACF, { 0xA0, 0x73, 0xD0, 0x1D, 0xE7, 0x7E, 0x2D, 0x88 }} + + ## Include/Guid/PcAnsi.h + gEfiUartDevicePathGuid = { 0x37499a9d, 0x542f, 0x4c89, { 0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 }} + + ## Include/Guid/PcAnsi.h + gEfiSasDevicePathGuid = { 0xd487ddb4, 0x008b, 0x11d9, { 0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d }} + + ## Include/Guid/Gpt.h + gEfiPartTypeLegacyMbrGuid = { 0x024DEE41, 0x33E7, 0x11D3, { 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F }} + + ## Include/Guid/Gpt.h + gEfiPartTypeSystemPartGuid = { 0xC12A7328, 0xF81F, 0x11D2, { 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B }} + + ## Include/Guid/Gpt.h + gEfiPartTypeUnusedGuid = { 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }} + + ## Include/Guid/DebugImageInfoTable.h + gEfiDebugImageInfoTableGuid = { 0x49152E77, 0x1ADA, 0x4764, { 0xB7, 0xA2, 0x7A, 0xFE, 0xFE, 0xD9, 0x5E, 0x8B }} + + ## Include/Guid/Acpi.h + gEfiAcpiTableGuid = { 0x8868E871, 0xE4F1, 0x11D3, { 0xBC, 0x22, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Guid/Acpi.h + gEfiAcpi20TableGuid = { 0x8868E871, 0xE4F1, 0x11D3, { 0xBC, 0x22, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Guid/Acpi.h + gEfiAcpi10TableGuid = { 0xEB9D2D30, 0x2D88, 0x11D3, { 0x9A, 0x16, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Guid/SmBios.h + gEfiSmbiosTableGuid = { 0xEB9D2D31, 0x2D88, 0x11D3, { 0x9A, 0x16, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Guid/Mps.h + gEfiMpsTableGuid = { 0xEB9D2D2F, 0x2D88, 0x11D3, { 0x9A, 0x16, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/AuthenticationInfo.h + gEfiAuthenticationChapLocalGuid = { 0xC280C73E, 0x15CA, 0x11DA, { 0xB0, 0xCA, 0x00, 0x10, 0x83, 0xFF, 0xCA, 0x4D }} + + ## Include/Protocol/AuthenticationInfo.h + gEfiAuthenticationChapRadiusGuid = { 0xD6062B50, 0x15CA, 0x11DA, { 0x92, 0x19, 0x00, 0x10, 0x83, 0xFF, 0xCA, 0x4D }} + + ## Include/Guid/FileSystemVolumeLabelInfo.h + gEfiFileSystemVolumeLabelInfoIdGuid = { 0xDB47D7D3, 0xFE81, 0x11D3, { 0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Guid/FileSystemInfo.h + gEfiFileSystemInfoGuid = { 0x09576E93, 0x6D3F, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Guid/FileInfo.h + gEfiFileInfoGuid = { 0x09576E92, 0x6D3F, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/Bis.h + gBootObjectAuthorizationParmsetGuid = { 0xEDD35E31, 0x07B9, 0x11D2, { 0x83, 0xA3, 0x00, 0xA0, 0xC9, 0x1F, 0xAD, 0xCF }} + + ## Include/Protocol/PlatformToDriverConfiguration.h + gEfiPlatformToDriverConfigurationClpGuid = { 0x345ecc0e, 0xcb6, 0x4b75, { 0xbb, 0x57, 0x1b, 0x12, 0x9c, 0x47, 0x33,0x3e }} + + ## Include/Guid/HiiKeyBoardLayout.h + gEfiHiiKeyBoardLayoutGuid = { 0x14982a4f, 0xb0ed, 0x45b8, { 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmMD5Guid = { 0x0AF7C79C, 0x65B5, 0x4319, { 0xB0, 0xAE, 0x44, 0xEC, 0x48, 0x4E, 0x4A, 0xD7 }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmSha512Guid = { 0xCAA4381E, 0x750C, 0x4770, { 0xB8, 0x70, 0x7A, 0x23, 0xB4, 0xE4, 0x21, 0x30 }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmSha384Guid = { 0xEFA96432, 0xDE33, 0x4DD2, { 0xAE, 0xE6, 0x32, 0x8C, 0x33, 0xDF, 0x77, 0x7A }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmSha256Guid = { 0x51AA59DE, 0xFDF2, 0x4EA3, { 0xBC, 0x63, 0x87, 0x5F, 0xB7, 0x84, 0x2E, 0xE9 }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmSha224Guid = { 0x8DF01A06, 0x9BD5, 0x4BF7, { 0xB0, 0x21, 0xDB, 0x4F, 0xD9, 0xCC, 0xF4, 0x5B }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmSha1Guid = { 0x2AE9D80F, 0x3FB2, 0x4095, { 0xB7, 0xB1, 0xE9, 0x31, 0x57, 0xB9, 0x46, 0xB6 }} + + ## Include/Guid/EventGroup.h + gEfiEventReadyToBootGuid = { 0x7CE88FB3, 0x4BD7, 0x4679, { 0x87, 0xA8, 0xA8, 0xD8, 0xDE, 0xE5, 0x0D, 0x2B }} + + ## Include/Guid/EventGroup.h + gEfiEventAfterReadyToBootGuid = { 0x3a2a00ad, 0x98b9, 0x4cdf, { 0xa4, 0x78, 0x70, 0x27, 0x77, 0xf1, 0xc1, 0x0b }} + + ## Include/Guid/EventGroup.h + gEfiEventMemoryMapChangeGuid = { 0x78BEE926, 0x692F, 0x48FD, { 0x9E, 0xDB, 0x01, 0x42, 0x2E, 0xF0, 0xD7, 0xAB }} + + ## Include/Guid/EventGroup.h + gEfiEventVirtualAddressChangeGuid = { 0x13FA7698, 0xC831, 0x49C7, { 0x87, 0xEA, 0x8F, 0x43, 0xFC, 0xC2, 0x51, 0x96 }} + + ## Include/Guid/EventGroup.h + gEfiEventBeforeExitBootServicesGuid = { 0x8BE0E274, 0x3970, 0x4B44, { 0x80, 0xC5, 0x1A, 0xB9, 0x50, 0x2F, 0x3B, 0xFC }} + + ## Include/Guid/EventGroup.h + gEfiEventExitBootServicesGuid = { 0x27ABF055, 0xB1B8, 0x4C26, { 0x80, 0x48, 0x74, 0x8F, 0x37, 0xBA, 0xA2, 0xDF }} + + ## Include/Protocol/DebugPort.h + gEfiDebugPortVariableGuid = { 0xEBA4E8D2, 0x3858, 0x41EC, { 0xA2, 0x81, 0x26, 0x47, 0xBA, 0x96, 0x60, 0xD0 }} + + ## Include/Protocol/DebugPort.h + gEfiDebugPortDevicePathGuid = { 0xEBA4E8D2, 0x3858, 0x41EC, { 0xA2, 0x81, 0x26, 0x47, 0xBA, 0x96, 0x60, 0xD0 }} + + ## Include/Guid/HiiPlatformSetupFormset.h + gEfiHiiPlatformSetupFormsetGuid = { 0x93039971, 0x8545, 0x4b04, { 0xb4, 0x5e, 0x32, 0xeb, 0x83, 0x26, 0x04, 0x0e }} + + ## Include/Guid/HiiPlatformSetupFormset.h + gEfiHiiDriverHealthFormsetGuid = { 0xf22fc20c, 0x8cf4, 0x45eb, { 0x8e, 0x6, 0xad, 0x4e, 0x50, 0xb9, 0x5d, 0xd3 }} + + ## Include/Guid/HiiPlatformSetupFormset.h + gEfiHiiUserCredentialFormsetGuid = { 0x337f4407, 0x5aee, 0x4b83, { 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd }} + + ## Include/Guid/HiiFormMapMethodGuid.h + gEfiHiiStandardFormGuid = { 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 }} + + ## Include/Guid/MemoryOverwriteControl.h + gEfiMemoryOverwriteControlDataGuid = { 0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29 }} + + ## Include/IndustryStandard/MemoryOverwriteRequestControlLock.h + gEfiMemoryOverwriteRequestControlLockGuid = { 0xBB983CCF, 0x151D, 0x40E1, {0xA0, 0x7B, 0x4A, 0x17, 0xBE, 0x16, 0x82, 0x92}} + + ## Include/Guid/WinCertificate.h + gEfiCertTypeRsa2048Sha256Guid = { 0xa7717414, 0xc616, 0x4977, {0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeCmcGuid = { 0x2DCE8BB1, 0xBDD7, 0x450e, { 0xB9, 0xAD, 0x9C, 0xF4, 0xEB, 0xD4, 0xF8, 0x90 }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeCpeGuid = { 0x4E292F96, 0xD843, 0x4a55, { 0xA8, 0xC2, 0xD4, 0x81, 0xF2, 0x7E, 0xBE, 0xEE }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeMceGuid = { 0xE8F56FFE, 0x919C, 0x4cc5, { 0xBA, 0x88, 0x65, 0xAB, 0xE1, 0x49, 0x13, 0xBB }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypePcieGuid = { 0xCF93C01F, 0x1A16, 0x4dfc, { 0xB8, 0xBC, 0x9C, 0x4D, 0xAF, 0x67, 0xC1, 0x04 }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeInitGuid = { 0xCC5263E8, 0x9308, 0x454a, { 0x89, 0xD0, 0x34, 0x0B, 0xD3, 0x9B, 0xC9, 0x8E }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeNmiGuid = { 0x5BAD89FF, 0xB7E6, 0x42c9, { 0x81, 0x4A, 0xCF, 0x24, 0x85, 0xD6, 0xE9, 0x8A }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeBootGuid = { 0x3D61A466, 0xAB40, 0x409a, { 0xA6, 0x98, 0xF3, 0x62, 0xD4, 0x64, 0xB3, 0x8F }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeDmarGuid = { 0x667DD791, 0xC6B3, 0x4c27, { 0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D, 0xEB, 0x41 }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeSeaGuid = { 0x9A78788A, 0xBBE8, 0x11E4, { 0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D, 0x46, 0xB0 }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypeSeiGuid = { 0x5C284C81, 0xB0AE, 0x4E87, { 0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23 }} + + ## Include/Guid/Cper.h + gEfiEventNotificationTypePeiGuid = { 0x09A9D5AC, 0x5204, 0x4214, { 0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B, 0xCD }} + + ## Include/Guid/Cper.h + gEfiProcessorGenericErrorSectionGuid = { 0x9876ccad, 0x47b4, 0x4bdb, { 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb }} + + ## Include/Guid/Cper.h + gEfiProcessorSpecificErrorSectionGuid = { 0xdc3ea0b0, 0xa144, 0x4797, { 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d }} + + ## Include/Guid/Cper.h + gEfiIa32X64ProcessorErrorSectionGuid = { 0xdc3ea0b0, 0xa144, 0x4797, { 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d }} + + ## Include/Guid/Cper.h + gEfiPlatformMemoryErrorSectionGuid = { 0xa5bc1114, 0x6f64, 0x4ede, { 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1 }} + + ## Include/Guid/Cper.h + gEfiPcieErrorSectionGuid = { 0xd995e954, 0xbbc1, 0x430f, { 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35 }} + + ## Include/Guid/Cper.h + gEfiFirmwareErrorSectionGuid = { 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed }} + + ## Include/Guid/Cper.h + gEfiPciBusErrorSectionGuid = { 0xc5753963, 0x3b84, 0x4095, { 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd }} + + ## Include/Guid/Cper.h + gEfiPciDevErrorSectionGuid = { 0xeb5e4685, 0xca66, 0x4769, { 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26 }} + + ## Include/Guid/Cper.h + gEfiDMArGenericErrorSectionGuid = { 0x5b51fef7, 0xc79d, 0x4434, { 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64 }} + + ## Include/Guid/Cper.h + gEfiDirectedIoDMArErrorSectionGuid = { 0x71761d37, 0x32b2, 0x45cd, { 0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf }} + + ## Include/Guid/Cper.h + gEfiIommuDMArErrorSectionGuid = { 0x036f84e1, 0x7f37, 0x428c, { 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec }} + + # + # GUID defined in UEFI2.2 + # + ## Include/Protocol/UserManager.h + gEfiEventUserProfileChangedGuid = { 0xbaf1e6de, 0x209e, 0x4adb, {0x8d, 0x96, 0xfd, 0x8b, 0x71, 0xf3, 0xf6, 0x83 }} + + ## Include/Protocol/UserManager.h + gEfiUserCredentialClassUnknownGuid = { 0x5cf32e68, 0x7660, 0x449b, { 0x80, 0xe6, 0x7e, 0xa3, 0x6e, 0x3, 0xf6, 0xa8 }} + + ## Include/Protocol/UserManager.h + gEfiUserCredentialClassPasswordGuid = { 0xf8e5058c, 0xccb6, 0x4714, { 0xb2, 0x20, 0x3f, 0x7e, 0x3a, 0x64, 0xb, 0xd1 }} + + ## Include/Protocol/UserManager.h + gEfiUserCredentialClassSmartCardGuid = { 0x5f03ba33, 0x8c6b, 0x4c24, { 0xaa, 0x2e, 0x14, 0xa2, 0x65, 0x7b, 0xd4, 0x54 }} + + ## Include/Protocol/UserManager.h + gEfiUserCredentialClassFingerprintGuid = { 0x32cba21f, 0xf308, 0x4cbc, { 0x9a, 0xb5, 0xf5, 0xa3, 0x69, 0x9f, 0x4, 0x4a }} + + ## Include/Protocol/UserManager.h + gEfiUserCredentialClassHandprintGuid = { 0x5917ef16, 0xf723, 0x4bb9, { 0xa6, 0x4b, 0xd8, 0xc5, 0x32, 0xf4, 0xd8, 0xb5 }} + + ## Include/Protocol/UserManager.h + gEfiUserCredentialClassSecureCardGuid = { 0x8a6b4a83, 0x42fe, 0x45d2, { 0xa2, 0xef, 0x46, 0xf0, 0x6c, 0x7d, 0x98, 0x52 }} + + ## Include/Protocol/UserManager.h + gEfiUserInfoAccessSetupAdminGuid = { 0x85b75607, 0xf7ce, 0x471e, { 0xb7, 0xe4, 0x2a, 0xea, 0x5f, 0x72, 0x32, 0xee }} + + ## Include/Protocol/UserManager.h + gEfiUserInfoAccessSetupNormalGuid = { 0x1db29ae0, 0x9dcb, 0x43bc, { 0x8d, 0x87, 0x5d, 0xa1, 0x49, 0x64, 0xdd, 0xe2 }} + + ## Include/Protocol/UserManager.h + gEfiUserInfoAccessSetupRestrictedGuid = { 0xbdb38125, 0x4d63, 0x49f4, { 0x82, 0x12, 0x61, 0xcf, 0x5a, 0x19, 0xa, 0xf8 }} + + ## Include/Guid/ImageAuthentication.h + gEfiImageSecurityDatabaseGuid = { 0xd719b2cb, 0x3d3a, 0x4596, {0xa3, 0xbc, 0xda, 0xd0, 0xe, 0x67, 0x65, 0x6f }} + gEfiCertSha256Guid = { 0xc1c41626, 0x504c, 0x4092, {0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28 }} + gEfiCertRsa2048Guid = { 0x3c5766e8, 0x269c, 0x4e34, {0xaa, 0x14, 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6 }} + gEfiCertRsa2048Sha256Guid = { 0xe2b36190, 0x879b, 0x4a3d, {0xad, 0x8d, 0xf2, 0xe7, 0xbb, 0xa3, 0x27, 0x84 }} + gEfiCertSha1Guid = { 0x826ca512, 0xcf10, 0x4ac9, {0xb1, 0x87, 0xbe, 0x1, 0x49, 0x66, 0x31, 0xbd }} + gEfiCertRsa2048Sha1Guid = { 0x67f8444f, 0x8743, 0x48f1, {0xa3, 0x28, 0x1e, 0xaa, 0xb8, 0x73, 0x60, 0x80 }} + gEfiCertX509Guid = { 0xa5c059a1, 0x94e4, 0x4aa7, {0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72 }} + + # + # GUIDs defined in UEFI2.3.1 + # + ## Include/Protocol/Kms.h + gEfiKmsFormatGeneric128Guid = { 0xec8a3d69, 0x6ddf, 0x4108, {0x94, 0x76, 0x73, 0x37, 0xfc, 0x52, 0x21, 0x36 }} + gEfiKmsFormatGeneric160Guid = { 0xa3b3e6f8, 0xefca, 0x4bc1, {0x88, 0xfb, 0xcb, 0x87, 0x33, 0x9b, 0x25, 0x79 }} + gEfiKmsFormatGeneric256Guid = { 0x70f64793, 0xc323, 0x4261, {0xac, 0x2c, 0xd8, 0x76, 0xf2, 0x7c, 0x53, 0x45 }} + gEfiKmsFormatGeneric512Guid = { 0x978fe043, 0xd7af, 0x422e, {0x8a, 0x92, 0x2b, 0x48, 0xe4, 0x63, 0xbd, 0xe6 }} + gEfiKmsFormatGeneric1024Guid = { 0x43be0b44, 0x874b, 0x4ead, {0xb0, 0x9c, 0x24, 0x1a, 0x4f, 0xbd, 0x7e, 0xb3 }} + gEfiKmsFormatGeneric2048Guid = { 0x40093f23, 0x630c, 0x4626, {0x9c, 0x48, 0x40, 0x37, 0x3b, 0x19, 0xcb, 0xbe }} + gEfiKmsFormatGeneric3072Guid = { 0xb9237513, 0x6c44, 0x4411, {0xa9, 0x90, 0x21, 0xe5, 0x56, 0xe0, 0x5a, 0xde }} + gEfiKmsFormatMd2128Guid = { 0x78be11c4, 0xee44, 0x4a22, {0x9f, 0x05, 0x03, 0x85, 0x2e, 0xc5, 0xc9, 0x78 }} + gEfiKmsFormatMdc2128Guid = { 0xf7ad60f8, 0xefa8, 0x44a3, {0x91, 0x13, 0x23, 0x1f, 0x39, 0x9e, 0xb4, 0xc7 }} + gEfiKmsFormatMd4128Guid = { 0xd1c17aa1, 0xcac5, 0x400f, {0xbe, 0x17, 0xe2, 0xa2, 0xae, 0x06, 0x67, 0x7c }} + gEfiKmsFormatMdc4128Guid = { 0x3fa4f847, 0xd8eb, 0x4df4, {0xbd, 0x49, 0x10, 0x3a, 0x0a, 0x84, 0x7b, 0xbc }} + gEfiKmsFormatMd5128Guid = { 0xdcbc3662, 0x9cda, 0x4b52, {0xa0, 0x4c, 0x82, 0xeb, 0x1d, 0x23, 0x48, 0xc7 }} + gEfiKmsFormatMd5sha128Guid = { 0x1c178237, 0x6897, 0x459e, {0x9d, 0x36, 0x67, 0xce, 0x8e, 0xf9, 0x4f, 0x76 }} + gEfiKmsFormatSha1160Guid = { 0x453c5e5a, 0x482d, 0x43f0, {0x87, 0xc9, 0x59, 0x41, 0xf3, 0xa3, 0x8a, 0xc2 }} + gEfiKmsFormatSha256256Guid = { 0x6bb4f5cd, 0x8022, 0x448d, {0xbc, 0x6d, 0x77, 0x1b, 0xae, 0x93, 0x5f, 0xc6 }} + gEfiKmsFormatSha512512Guid = { 0x2f240e12, 0xe14d, 0x475c, {0x83, 0xb0, 0xef, 0xff, 0x22, 0xd7, 0x7b, 0xe7 }} + gEfiKmsFormatAesxts128Guid = { 0x4776e33f, 0xdb47, 0x479a, {0xa2, 0x5f, 0xa1, 0xcd, 0x0a, 0xfa, 0xb3, 0x8b }} + gEfiKmsFormatAesxts256Guid = { 0xdc7e8613, 0xc4bb, 0x4db0, {0x84, 0x62, 0x13, 0x51, 0x13, 0x57, 0xab, 0xe2 }} + gEfiKmsFormatAescbc128Guid = { 0xa0e8ee6a, 0x0e92, 0x44d4, {0x86, 0x1b, 0x0e, 0xaa, 0x4a, 0xca, 0x44, 0xa2 }} + gEfiKmsFormatAescbc256Guid = { 0xd7e69789, 0x1f68, 0x45e8, {0x96, 0xef, 0x3b, 0x64, 0x07, 0xa5, 0xb2, 0xdc }} + gEfiKmsFormatRsasha11024Guid = { 0x56417bed, 0x6bbe, 0x4882, {0x86, 0xa0, 0x3a, 0xe8, 0xbb, 0x17, 0xf8, 0xf9 }} + gEfiKmsFormatRsasha12048Guid = { 0xf66447d4, 0x75a6, 0x463e, {0xa8, 0x19, 0x07, 0x7f, 0x2d, 0xda, 0x05, 0xe9 }} + gEfiKmsFormatRsasha2562048Guid = { 0xa477af13, 0x877d, 0x4060, {0xba, 0xa1, 0x25, 0xd1, 0xbe, 0xa0, 0x8a, 0xd3 }} + gEfiKmsFormatRsasha2563072Guid = { 0x4e1356c2, 0xeed, 0x463f, {0x81, 0x47, 0x99, 0x33, 0xab, 0xdb, 0xc7, 0xd5 }} + + ## Include/Guid/ImageAuthentication.h + gEfiCertSha224Guid = { 0xb6e5233, 0xa65c, 0x44c9, {0x94, 0x7, 0xd9, 0xab, 0x83, 0xbf, 0xc8, 0xbd }} + gEfiCertSha384Guid = { 0xff3e5307, 0x9fd0, 0x48c9, {0x85, 0xf1, 0x8a, 0xd5, 0x6c, 0x70, 0x1e, 0x1 }} + gEfiCertSha512Guid = { 0x93e0fae, 0xa6c4, 0x4f50, {0x9f, 0x1b, 0xd4, 0x1e, 0x2b, 0x89, 0xc1, 0x9a }} + gEfiCertPkcs7Guid = { 0x4aafd29d, 0x68df, 0x49ee, {0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7 }} + + ## Include/Protocol/Hash.h + gEfiHashAlgorithmSha1NoPadGuid = { 0x24c5dc2f, 0x53e2, 0x40ca, { 0x9e, 0xd6, 0xa5, 0xd9, 0xa4, 0x9f, 0x46, 0x3b }} + gEfiHashAlgorithmSha256NoPadGuid = { 0x8628752a, 0x6cb7, 0x4814, { 0x96, 0xfc, 0x24, 0xa8, 0x15, 0xac, 0x22, 0x26 }} + + # + # GUIDs defined in UEFI2.4 + # + ## Include/Guid/FmpCapsule.h + gEfiFmpCapsuleGuid = { 0x6dcbd5ed, 0xe82d, 0x4c44, {0xbd, 0xa1, 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a }} + + ## Include/Guid/ImageAuthentication.h + gEfiCertX509Sha256Guid = { 0x3bd2a492, 0x96c0, 0x4079, {0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed }} + gEfiCertX509Sha384Guid = { 0x7076876e, 0x80c2, 0x4ee6, {0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b }} + gEfiCertX509Sha512Guid = { 0x446dbf63, 0x2502, 0x4cda, {0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d }} + + ## Include/Protocol/Rng.h + gEfiRngAlgorithmSp80090Hash256Guid = { 0xa7af67cb, 0x603b, 0x4d42, {0xba, 0x21, 0x70, 0xbf, 0xb6, 0x29, 0x3f, 0x96 }} + gEfiRngAlgorithmSp80090Hmac256Guid = { 0xc5149b43, 0xae85, 0x4f53, {0x99, 0x82, 0xb9, 0x43, 0x35, 0xd3, 0xa9, 0xe7 }} + gEfiRngAlgorithmSp80090Ctr256Guid = { 0x44f0de6e, 0x4d8c, 0x4045, {0xa8, 0xc7, 0x4d, 0xd1, 0x68, 0x85, 0x6b, 0x9e }} + gEfiRngAlgorithmX9313DesGuid = { 0x63c4785a, 0xca34, 0x4012, {0xa3, 0xc8, 0x0b, 0x6a, 0x32, 0x4f, 0x55, 0x46 }} + gEfiRngAlgorithmX931AesGuid = { 0xacd03321, 0x777e, 0x4d3d, {0xb1, 0xc8, 0x20, 0xcf, 0xd8, 0x88, 0x20, 0xc9 }} + gEfiRngAlgorithmRaw = { 0xe43176d7, 0xb6e8, 0x4827, {0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61 }} + gEfiRngAlgorithmArmRndr = { 0x43d2fde3, 0x9d4e, 0x4d79, {0x02, 0x96, 0xa8, 0x9b, 0xca, 0x78, 0x08, 0x41 }} + + ## Include/Protocol/AdapterInformation.h + gEfiAdapterInfoMediaStateGuid = { 0xD7C74207, 0xA831, 0x4A26, {0xB1, 0xF5, 0xD1, 0x93, 0x06, 0x5C, 0xE8, 0xB6 }} + gEfiAdapterInfoNetworkBootGuid = { 0x1FBD2960, 0x4130, 0x41E5, {0x94, 0xAC, 0xD2, 0xCF, 0x03, 0x7F, 0xB3, 0x7C }} + gEfiAdapterInfoSanMacAddressGuid = { 0x114da5ef, 0x2cf1, 0x4e12, {0x9b, 0xbb, 0xc4, 0x70, 0xb5, 0x52, 0x5, 0xd9 }} + + ## Include/Guid/CapsuleReport.h + gEfiCapsuleReportGuid = { 0x39b68c46, 0xf7fb, 0x441b, {0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 }} + + # + # GUIDs defined in UEFI2.5 + # + + ## Include/Guid/SystemResourceTable.h + gEfiSystemResourceTableGuid = { 0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 }} + + ## Include/Protocol/AdapterInformation.h + gEfiAdapterInfoUndiIpv6SupportGuid = { 0x4bd56be3, 0x4975, 0x4d8a, {0xa0, 0xad, 0xc4, 0x91, 0x20, 0x4b, 0x5d, 0x4d }} + + ## Include/Protocol/RegularExpressionProtocol.h + gEfiRegexSyntaxTypePosixExtendedGuid = {0x5F05B20F, 0x4A56, 0xC231, {0xFA, 0x0B, 0xA7, 0xB1, 0xF1, 0x10, 0x04, 0x1D }} + + ## Include/Protocol/RegularExpressionProtocol.h + gEfiRegexSyntaxTypeEcma262Guid = { 0x9A473A4A, 0x4CEB, 0xB95A, {0x41, 0x5E, 0x5B, 0xA0, 0xBC, 0x63, 0x9B, 0x2E }} + + ## Include/Protocol/RegularExpressionProtocol.h + gEfiRegexSyntaxTypePerlGuid = {0x63E60A51, 0x497D, 0xD427, {0xC4, 0xA5, 0xB8, 0xAB, 0xDC, 0x3A, 0xAE, 0xB6 }} + + ## Include/Guid/Cper.h + gEfiPlatformMemory2ErrorSectionGuid = { 0x61EC04FC, 0x48E6, 0xD813, { 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 }} + + ## Include/Protocol/BlockIoCrypto.h + gEfiBlockIoCryptoAlgoAesXtsGuid = { 0x2f87ba6a, 0x5c04, 0x4385, {0xa7, 0x80, 0xf3, 0xbf, 0x78, 0xa9, 0x7b, 0xec }} + gEfiBlockIoCryptoAlgoAesCbcMsBitlockerGuid = { 0x689e4c62, 0x70bf, 0x4cf3, {0x88, 0xbb, 0x33, 0xb3, 0x18, 0x26, 0x86, 0x70 }} + + ## Include/Protocol/SmartCardEdge.h + gEfiPaddingRsassaPkcs1V1P5Guid = { 0x9317ec24, 0x7cb0, 0x4d0e, {0x8b, 0x32, 0x2e, 0xd9, 0x20, 0x9c, 0xd8, 0xaf }} + gEfiPaddingRsassaPssGuid = { 0x7b2349e0, 0x522d, 0x4f8e, {0xb9, 0x27, 0x69, 0xd9, 0x7c, 0x9e, 0x79, 0x5f }} + gEfiPaddingNoneGuid = { 0x3629ddb1, 0x228c, 0x452e, {0xb6, 0x16, 0x09, 0xed, 0x31, 0x6a, 0x97, 0x00 }} + gEfiPaddingRsaesPkcs1V1P5Guid = { 0xe1c1d0a9, 0x40b1, 0x4632, {0xbd, 0xcc, 0xd9, 0xd6, 0xe5, 0x29, 0x56, 0x31 }} + gEfiPaddingRsaesOaepGuid = { 0xc1e63ac4, 0xd0cf, 0x4ce6, {0x83, 0x5b, 0xee, 0xd0, 0xe6, 0xa8, 0xa4, 0x5b }} + + ## Include/Guid/SmBios.h + gEfiSmbios3TableGuid = { 0xF2FD1544, 0x9794, 0x4A2C, { 0x99, 0x2E, 0xE5, 0xBB, 0xCF, 0x20, 0xE3, 0x94 }} + + ## Include/Protocol/BootManagerPolicy.h + gEfiBootManagerPolicyConsoleGuid = { 0xCAB0E94C, 0xE15F, 0x11E3, { 0x91, 0x8D, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA }} + gEfiBootManagerPolicyNetworkGuid = { 0xD04159DC, 0xE15F, 0x11E3, { 0xB2, 0x61, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA }} + gEfiBootManagerPolicyConnectAllGuid = { 0x113B2126, 0xFC8A, 0x11E3, { 0xBD, 0x6C, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA }} + + ## Include/Protocol/DevicePath.h + gEfiVirtualDiskGuid = { 0x77AB535A, 0x45FC, 0x624B, {0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }} + gEfiVirtualCdGuid = { 0x3D5ABD30, 0x4175, 0x87CE, {0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }} + gEfiPersistentVirtualDiskGuid = { 0x5CEA02C9, 0x4D07, 0x69D3, {0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }} + gEfiPersistentVirtualCdGuid = { 0x08018188, 0x42CD, 0xBB48, {0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }} + + # + # GUIDs defined in UEFI2.6 + # + + ## Include/Guid/MemoryAttributesTable.h + gEfiMemoryAttributesTableGuid = { 0xdcfa911d, 0x26eb, 0x469f, {0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20}} + + ## Include/Guid/Cper.h + gEfiArmProcessorErrorSectionGuid = { 0xe19e3d16, 0xbc11, 0x11e4, { 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0 }} + + ## Guid for Image decoder + ## Include/Protocol/ImageDecoder.h + gEfiHiiImageDecoderNameJpegGuid = { 0xefefd093, 0x0d9b, 0x46eb, { 0xa8, 0x56, 0x48, 0x35, 0x07, 0x00, 0xc9, 0x08 }} + gEfiHiiImageDecoderNamePngGuid = { 0xaf060190, 0x5e3a, 0x4025, { 0xaf, 0xbd, 0xe1, 0xf9, 0x05, 0xbf, 0xaa, 0x4c }} + + # + # GUIDs defined in UEFI2.7 + # + ## Include/Guid/Btt.h + gEfiBttAbstractionGuid = { 0x18633bfc, 0x1735, 0x4217, { 0x8a, 0xc9, 0x17, 0x23, 0x92, 0x82, 0xd3, 0xf8 }} + + # GUIDs defined in UEFI2.8 + # + ## Include/Guid/JsonCapsule.h + gEfiJsonConfigDataTableGuid = { 0x87367f87, 0x1119, 0x41ce, { 0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }} + gEfiJsonCapsuleDataTableGuid = { 0x35e7a725, 0x8dd2, 0x4cac, { 0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }} + gEfiJsonCapsuleResultTableGuid = { 0xdbc461c3, 0xb3de, 0x422a, { 0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }} + gEfiJsonCapsuleIdGuid = { 0x67d6f4cd, 0xd6b8, 0x4573, { 0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }} + + ## Include/Guid/HiiPlatformSetupFormset.h + gEfiHiiRestStyleFormsetGuid = { 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 }} + + # GUIDs defined in UEFI2.8a + # + ## Include/Guid/RtPropertiesTable.h + gEfiRtPropertiesTableGuid = { 0xeb66918a, 0x7eef, 0x402a, { 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }} + + ## Include/Protocol/SerilaIo.h + gEfiSerialTerminalDeviceTypeGuid = { 0x6AD9A60F, 0x5815, 0x4C7C, { 0x8A, 0x10, 0x50, 0x53, 0xD2, 0xBF, 0x7A, 0x1B }} + + # + # GUID defined in PI1.0 + # + ## Include/Guid/AprioriFileName.h + gPeiAprioriFileNameGuid = { 0x1b45cc0a, 0x156a, 0x428a, { 0XAF, 0x62, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 }} + + ## Include/Guid/Apriori.h + gAprioriGuid = { 0xFC510EE7, 0xFFDC, 0x11D4, { 0xBD, 0x41, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Guid/FirmwareFileSystem2.h + gEfiFirmwareFileSystem2Guid = { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 }} + + ## Include/Guid/FirmwareFileSystem2.h + gEfiFirmwareVolumeTopFileGuid = { 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x09 }} + + ## Include/Guid/MemoryAllocationHob.h + gEfiHobMemoryAllocModuleGuid = { 0xF8E21975, 0x0899, 0x4F58, { 0xA4, 0xBE, 0x55, 0x25, 0xA9, 0xC6, 0xD7, 0x7A }} + + ## Include/Guid/MemoryAllocationHob.h + gEfiHobMemoryAllocStackGuid = { 0x4ED4BF27, 0x4092, 0x42E9, { 0x80, 0x7D, 0x52, 0x7B, 0x1D, 0x00, 0xC9, 0xBD }} + + ## Include/Guid/MemoryAllocationHob.h + gEfiHobMemoryAllocBspStoreGuid = { 0x564B33CD, 0xC92A, 0x4593, { 0x90, 0xBF, 0x24, 0x73, 0xE4, 0x3C, 0x63, 0x22 }} + + ## Include/Guid/EventLegacyBios.h + gEfiEventLegacyBootGuid = { 0x2A571201, 0x4966, 0x47F6, { 0x8B, 0x86, 0xF3, 0x1E, 0x41, 0xF3, 0x2F, 0x10 }} + + ## Include/Guid/HobList.h + gEfiHobListGuid = { 0x7739F24C, 0x93D7, 0x11D4, { 0x9A, 0x3A, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Guid/DxeServices.h + gEfiDxeServicesTableGuid = { 0x05AD34BA, 0x6F02, 0x4214, { 0x95, 0x2E, 0x4D, 0xA0, 0x39, 0x8E, 0x2B, 0xB9 }} + + ## Include/Guid/MdePkgTokenSpace.h + gEfiMdePkgTokenSpaceGuid = { 0x914AEBE7, 0x4635, 0x459b, { 0xAA, 0x1C, 0x11, 0xE2, 0x19, 0xB0, 0x3A, 0x10 }} + + ## Include/Guid/HardwareErrorVariable.h + gEfiHardwareErrorVariableGuid = { 0x414E6BDD, 0xE47B, 0x47cc, { 0xB2, 0x44, 0xBB, 0x61, 0x02, 0x0C, 0xF5, 0x16 }} + + # + # GUID defined in PI1.2 + # + ## Include/Guid/EventGroup.h + gEfiEventDxeDispatchGuid = { 0x7081E22F, 0xCAC6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xCF, 0x88, 0xE5 }} + + ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Ide interface. + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoIdeInterfaceGuid = { 0x5E948FE3, 0x26D3, 0x42B5, { 0xAF, 0x17, 0x61, 0x02, 0x87, 0x18, 0x8D, 0xEC }} + + ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Scsi interface. + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoScsiInterfaceGuid = { 0x08F74BAA, 0xEA36, 0x41D9, { 0x95, 0x21, 0x21, 0xA7, 0x0F, 0x87, 0x80, 0xBC }} + + ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Usb interface. + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoUsbInterfaceGuid = { 0xCB871572, 0xC11A, 0x47B5, { 0xB4, 0x92, 0x67, 0x5E, 0xAF, 0xA7, 0x77, 0x27 }} + + ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Ahci interface. + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoAhciInterfaceGuid = { 0x9e498932, 0x4abc, 0x45af, { 0xa3, 0x4d, 0x02, 0x47, 0x78, 0x7b, 0xe7, 0xc6 }} + + ## Include/Guid/StatusCodeDataTypeId.h + gEfiStatusCodeDataTypeStringGuid = { 0x92D11080, 0x496F, 0x4D95, { 0xBE, 0x7E, 0x03, 0x74, 0x88, 0x38, 0x2B, 0x0A }} + + ## Include/Guid/StatusCodeDataTypeId.h + gEfiStatusCodeSpecificDataGuid = { 0x335984BD, 0xE805, 0x409A, { 0xB8, 0xF8, 0xD2, 0x7E, 0xCE, 0x5F, 0xF7, 0xA6 }} + + ## Include/Guid/FirmwareFileSystem3.h + gEfiFirmwareFileSystem3Guid = { 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }} + + # + # GUID defined in PI1.2.1 + # + ## Include/Guid/EventGroup.h + gEfiEndOfDxeEventGroupGuid = { 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, 0xf0, 0x47, 0x8, 0x80 }} + + ## Include/Guid/FirmwareContentsSigned.h + gEfiFirmwareContentsSignedGuid = { 0xf9d89e8, 0x9259, 0x4f76, { 0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf }} + + ## Include/Guid/VectorHandoffTable.h + gEfiVectorHandoffTableGuid = { 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }} + + ## Include/IndustryStandard/Hsti.h + gAdapterInfoPlatformSecurityGuid = {0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }} + + # + # GUID defined in PI1.3 + # + ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify Nvme interface. + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoNvmeInterfaceGuid = { 0x3ab14680, 0x5d3f, 0x4a4d, { 0xbc, 0xdc, 0xcc, 0x38, 0x0, 0x18, 0xc7, 0xf7 }} + + # + # GUID defined in PI1.4 + # + ## Include/Guid/GraphicsInfoHob.h + gEfiGraphicsInfoHobGuid = { 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 }} + + ## Guid for EFI_DISK_INFO_PROTOCOL.Interface to specify UFS interface. + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoUfsInterfaceGuid = { 0x4b3029cc, 0x6b98, 0x47fb, { 0xbc, 0x96, 0x76, 0xdc, 0xb8, 0x4, 0x41, 0xf0 }} + + # + # GUID defined in PI1.5 + # + ## Include/Guid/GraphicsInfoHob.h + gEfiGraphicsDeviceInfoHobGuid = { 0xe5cb2ac9, 0xd35d, 0x4430, { 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 }} + + ## Include/Guid/SmramMemoryReserve.h + gEfiSmmSmramMemoryGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d }} + + # + # GUID defined in PI1.6 + # + ## Include/Protocol/DiskInfo.h + gEfiDiskInfoSdMmcInterfaceGuid = { 0x8deec992, 0xd39c, 0x4a5c, { 0xab, 0x6b, 0x98, 0x6e, 0x14, 0x24, 0x2b, 0x9d }} + + # + # GUID defined in Windows UEFI Firmware Update Platform doc + # + ## Include/IndustryStandard/WindowsUxCapsule.h + gWindowsUxCapsuleGuid = { 0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97}} + + # + # GUID indicates the tiano custom compress/decompress algorithm. + # + gTianoCustomDecompressGuid = { 0xA31280AD, 0x481E, 0x41B6, { 0x95, 0xE8, 0x12, 0x7F, 0x4C, 0x98, 0x47, 0x79 }} + + # + # GUID used to provide initrd to linux via LoadFile2 protocol + # + gLinuxEfiInitrdMediaGuid = {0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}} + + ## Include/Protocol/CcMeasurement.h + gEfiCcFinalEventsTableGuid = { 0xdd4a4648, 0x2de7, 0x4665, { 0x96, 0x4d, 0x21, 0xd9, 0xef, 0x5f, 0xb4, 0x46 }} + + # + # SPI NOR flash JEDEC Serial Flash Discoverable Parameters (SFDP) driver GUID + # + gEdk2JedecSfdpSpiDxeDriverGuid = { 0xBE71701E, 0xB63C, 0x4574, { 0x9C, 0x5C, 0x36, 0x29, 0xE8, 0xEA, 0xC4, 0x14 }} + gEdk2JedecSfdpSpiSmmDriverGuid = { 0x95A1E915, 0x195C, 0x477C, { 0x92, 0x6F, 0x7E, 0x24, 0x67, 0xC1, 0xB3, 0x1F }} + +[Guids.IA32, Guids.X64] + ## Include/Guid/Cper.h + gEfiIa32X64ErrorTypeCacheCheckGuid = { 0xA55701F5, 0xE3EF, 0x43de, { 0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }} + + ## Include/Guid/Cper.h + gEfiIa32X64ErrorTypeTlbCheckGuid = { 0xFC06B535, 0x5E1F, 0x4562, { 0x9F, 0x25, 0x0A, 0x3B, 0x9A, 0xDB, 0x63, 0xC3 }} + + ## Include/Guid/Cper.h + gEfiIa32X64ErrorTypeBusCheckGuid = { 0x1CF3F8B3, 0xC5B1, 0x49a2, { 0xAA, 0x59, 0x5E, 0xEF, 0x92, 0xFF, 0xA6, 0x3C }} + + ## Include/Guid/Cper.h + gEfiIa32X64ErrorTypeMsCheckGuid = { 0x48AB7F57, 0xDC34, 0x4f6c, { 0xA7, 0xD3, 0xB0, 0xB5, 0xB0, 0xA7, 0x43, 0x14 }} + +[Ppis] + ## Include/Ppi/MasterBootMode.h + gEfiPeiMasterBootModePpiGuid = { 0x7408d748, 0xfc8c, 0x4ee6, {0x92, 0x88, 0xc4, 0xbe, 0xc0, 0x92, 0xa4, 0x10 } } + + ## Include/Ppi/DxeIpl.h + gEfiDxeIplPpiGuid = {0xae8ce5d, 0xe448, 0x4437, {0xa8, 0xd7, 0xeb, 0xf5, 0xf1, 0x94, 0xf7, 0x31 }} + + ## Include/Ppi/MemoryDiscovered.h + gEfiPeiMemoryDiscoveredPpiGuid = {0xf894643d, 0xc449, 0x42d1, {0x8e, 0xa8, 0x85, 0xbd, 0xd8, 0xc6, 0x5b, 0xde } } + + ## Include/Ppi/BootInRecoveryMode.h + gEfiPeiBootInRecoveryModePpiGuid = { 0x17ee496a, 0xd8e4, 0x4b9a, {0x94, 0xd1, 0xce, 0x82, 0x72, 0x30, 0x8, 0x50 } } + + ## Include/Ppi/EndOfPeiPhase.h + gEfiEndOfPeiSignalPpiGuid = {0x605EA650, 0xC65C, 0x42e1, {0xBA, 0x80, 0x91, 0xA5, 0x2A, 0xB6, 0x18, 0xC6 } } + + ## Include/Ppi/Reset.h + gEfiPeiResetPpiGuid = { 0xef398d58, 0x9dfd, 0x4103, {0xbf, 0x94, 0x78, 0xc6, 0xf4, 0xfe, 0x71, 0x2f } } + + ## Include/Ppi/StatusCode.h + gEfiPeiStatusCodePpiGuid = { 0x229832d3, 0x7a30, 0x4b36, {0xb8, 0x27, 0xf4, 0xc, 0xb7, 0xd4, 0x54, 0x36 } } + + ## Include/Ppi/Security2.h + gEfiPeiSecurity2PpiGuid = { 0xdcd0be23, 0x9586, 0x40f4, { 0xb6, 0x43, 0x6, 0x52, 0x2c, 0xed, 0x4e, 0xde } } + + ## Include/Ppi/TemporaryRamSupport.h + gEfiTemporaryRamSupportPpiGuid = { 0xdbe23aa9, 0xa345, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} } + + ## Include/Ppi/CpuIo.h + gEfiPeiCpuIoPpiInstalledGuid = { 0xe6af1f7b, 0xfc3f, 0x46da, {0xa8, 0x28, 0xa3, 0xb4, 0x57, 0xa4, 0x42, 0x82 } } + + ## Include/Ppi/PciCfg2.h + gEfiPciCfg2PpiGuid = { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } } + + ## Include/Ppi/Stall.h + gEfiPeiStallPpiGuid = { 0x1f4c6f90, 0xb06b, 0x48d8, {0xa2, 0x01, 0xba, 0xe5, 0xf1, 0xcd, 0x7d, 0x56 } } + + ## Include/Ppi/ReadOnlyVariable2.h + gEfiPeiReadOnlyVariable2PpiGuid = { 0x2ab86ef5, 0xecb5, 0x4134, { 0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4 } } + + ## Include/Ppi/SecPlatformInformation.h + gEfiSecPlatformInformationPpiGuid = { 0x6f8c2b35, 0xfef4, 0x448d, {0x82, 0x56, 0xe1, 0x1b, 0x19, 0xd6, 0x10, 0x77 } } + + ## Include/Ppi/LoadImage.h + gEfiPeiLoadedImagePpiGuid = { 0xc1fcd448, 0x6300, 0x4458, { 0xb8, 0x64, 0x28, 0xdf, 0x1, 0x53, 0x64, 0xbc } } + + ## Include/Ppi/Smbus2.h + gEfiPeiSmbus2PpiGuid = { 0x9ca93627, 0xb65b, 0x4324, { 0xa2, 0x2, 0xc0, 0xb4, 0x61, 0x76, 0x45, 0x43 } } + + ## Include/Ppi/FirmwareVolumeInfo.h + gEfiPeiFirmwareVolumeInfoPpiGuid = { 0x49edb1c1, 0xbf21, 0x4761, { 0xbb, 0x12, 0xeb, 0x0, 0x31, 0xaa, 0xbb, 0x39 } } + + ## Include/Ppi/LoadFile.h + gEfiPeiLoadFilePpiGuid = { 0xb9e0abfe, 0x5979, 0x4914, { 0x97, 0x7f, 0x6d, 0xee, 0x78, 0xc2, 0x78, 0xa6 } } + + ## Include/Ppi/Decompress.h + gEfiPeiDecompressPpiGuid = { 0x1a36e4e7, 0xfab6, 0x476a, { 0x8e, 0x75, 0x69, 0x5a, 0x5, 0x76, 0xfd, 0xd7 } } + + ## Include/Ppi/Pcd.h + gPcdPpiGuid = { 0x6e81c58, 0x4ad7, 0x44bc, { 0x83, 0x90, 0xf1, 0x2, 0x65, 0xf7, 0x24, 0x80 } } + + ## Include/Ppi/PcdInfo.h + gGetPcdInfoPpiGuid = { 0x4d8b155b, 0xc059, 0x4c8f, { 0x89, 0x26, 0x6, 0xfd, 0x43, 0x31, 0xdb, 0x8a } } + + # + # PPIs defined in PI 1.2. + # + + ## Include/Ppi/RecoveryModule.h + gEfiPeiRecoveryModulePpiGuid = { 0xFB6D9542, 0x612D, 0x4f45, { 0x87, 0x2f, 0x5c, 0xff, 0x52, 0xe9, 0x3d, 0xcf }} + + ## Include/Ppi/DeviceRecoveryModule.h + gEfiPeiDeviceRecoveryModulePpiGuid = { 0x0DE2CE25, 0x446A, 0x45a7, { 0xBF, 0xC9, 0x37, 0xDA, 0x26, 0x34, 0x4B, 0x37 }} + + ## Include/Ppi/BlockIo.h + gEfiPeiVirtualBlockIoPpiGuid = { 0x695d8aa1, 0x42ee, 0x4c46, { 0x80, 0x5c, 0x6e, 0xa6, 0xbc, 0xe7, 0x99, 0xe3 }} + + ## Include/Ppi/S3Resume2.h + gEfiPeiS3Resume2PpiGuid = { 0x6D582DBC, 0xDB85, 0x4514, {0x8F, 0xCC, 0x5A, 0xDF, 0x62, 0x27, 0xB1, 0x47 }} + + ## Include/Ppi/ReportStatusCodeHandler.h + gEfiPeiRscHandlerPpiGuid = { 0x65d394, 0x9951, 0x4144, {0x82, 0xa3, 0xa, 0xfc, 0x85, 0x79, 0xc2, 0x51 }} + + ## Include/Ppi/PiPcd.h + gEfiPeiPcdPpiGuid = { 0x1f34d25, 0x4de2, 0x23ad, { 0x3f, 0xf3, 0x36, 0x35, 0x3f, 0xf3, 0x23, 0xf1 } } + + # + # PPIs defined in PI 1.2.1. + # + + ## Include/Ppi/PiPcdInfo.h + gEfiGetPcdInfoPpiGuid = { 0xa60c6b59, 0xe459, 0x425d, { 0x9c, 0x69, 0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } } + + ## Include/Ppi/TemporaryRamDone.h + gEfiTemporaryRamDonePpiGuid = { 0xceab683c, 0xec56, 0x4a2d, { 0xa9, 0x6, 0x40, 0x53, 0xfa, 0x4e, 0x9c, 0x16 } } + + ## Include/Ppi/VectorHandoffInfo.h + gEfiVectorHandoffInfoPpiGuid = { 0x3cd652b4, 0x6d33, 0x4dce, { 0x89, 0xdb, 0x83, 0xdf, 0x97, 0x66, 0xfc, 0xca }} + + ## Include/Ppi/IsaHc.h + gEfiIsaHcPpiGuid = { 0x8d48bd70, 0xc8a3, 0x4c06, {0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58 } } + + ## Include/Ppi/SuperIo.h + gEfiSioPpiGuid = { 0x23a464ad, 0xcb83, 0x48b8, {0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22 } } + + # + # PPIs defined in PI 1.3. + # + + ## Include/Ppi/I2cMaster.h + gEfiPeiI2cMasterPpiGuid = { 0xb3bfab9b, 0x9f9c, 0x4e8b, { 0xad, 0x37, 0x7f, 0x8c, 0x51, 0xfc, 0x62, 0x80 }} + + ## Include/Ppi/FirmwareVolumeInfo2.h + gEfiPeiFirmwareVolumeInfo2PpiGuid = { 0xea7ca24b, 0xded5, 0x4dad, { 0xa3, 0x89, 0xbf, 0x82, 0x7e, 0x8f, 0x9b, 0x38 } } + + # + # PPIs defined in PI 1.4. + # + + ## Include/Ppi/Graphics.h + gEfiPeiGraphicsPpiGuid = { 0x6ecd1463, 0x4a4a, 0x461b, { 0xaf, 0x5f, 0x5a, 0x33, 0xe3, 0xb2, 0x16, 0x2b } } + + ## Include/Ppi/MpServices.h + gEfiPeiMpServicesPpiGuid = { 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } } + + ## Include/Ppi/Capsule.h + gEfiPeiCapsulePpiGuid = { 0x3acf33ee, 0xd892, 0x40f4, { 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d }} + ## Keep name backwards compatible before PI Version 1.4 + gPeiCapsulePpiGuid = { 0x3acf33ee, 0xd892, 0x40f4, { 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d }} + + ## Include/Ppi/Reset2.h + gEfiPeiReset2PpiGuid = { 0x6cc45765, 0xcce4, 0x42fd, {0xbc, 0x56, 0x1, 0x1a, 0xaa, 0xc6, 0xc9, 0xa8 } } + + ## Include/Ppi/BlockIo2.h + gEfiPeiVirtualBlockIo2PpiGuid = { 0x26cc0fad, 0xbeb3, 0x478a, { 0x91, 0xb2, 0xc, 0x18, 0x8f, 0x72, 0x61, 0x98 }} + + ## Include/Ppi/SecPlatformInformation.h + gEfiSecPlatformInformation2PpiGuid = { 0x9e9f374b, 0x8f16, 0x4230, {0x98, 0x24, 0x58, 0x46, 0xee, 0x76, 0x6a, 0x97 } } + + # + # PPIs defined in PI 1.5. + # + + ## Include/Ppi/SecHobData.h + gEfiSecHobDataPpiGuid = { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } } + + ## Include/Ppi/MmAccess.h + gEfiPeiMmAccessPpiGuid = { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }} + + ## Include/Ppi/MmControl.h + gEfiPeiMmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} + + ## Include/Ppi/MmConfiguration.h + gEfiPeiMmConfigurationPpi = { 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } } + + ## Include/Ppi/MmCommunication.h + gEfiPeiMmCommunicationPpiGuid = { 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } } + + # + # PPIs defined in PI 1.7. + # + + ## Include/Ppi/PeiCoreFvLocation.h + gEfiPeiCoreFvLocationPpiGuid = { 0x52888eae, 0x5b10, 0x47d0, { 0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 }} + + ## Include/Ppi/DelayedDispatch.h + gEfiPeiDelayedDispatchPpiGuid = { 0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6 }} + +[Protocols] + ## Include/Protocol/MemoryAccept.h + gEdkiiMemoryAcceptProtocolGuid = { 0x38c74800, 0x5590, 0x4db4, { 0xa0, 0xf3, 0x67, 0x5d, 0x9b, 0x8e, 0x80, 0x26 }} + + ## Include/Protocol/Pcd.h + gPcdProtocolGuid = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }} + + ## Include/Protocol/PcdInfo.h + gGetPcdInfoProtocolGuid = { 0x5be40f57, 0xfa68, 0x4610, { 0xbb, 0xbf, 0xe9, 0xc5, 0xfc, 0xda, 0xd3, 0x65 } } + + ## Include/Protocol/CcMeasurement.h + gEfiCcMeasurementProtocolGuid = { 0x96751a3d, 0x72f4, 0x41a6, { 0xa7, 0x94, 0xed, 0x5d, 0x0e, 0x67, 0xae, 0x6b }} + + # + # Protocols defined in PI1.0. + # + + ## Include/Protocol/Bds.h + gEfiBdsArchProtocolGuid = { 0x665E3FF6, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/Cpu.h + gEfiCpuArchProtocolGuid = { 0x26BACCB1, 0x6F42, 0x11D4, { 0xBC, 0xE7, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Protocol/Metronome.h + gEfiMetronomeArchProtocolGuid = { 0x26BACCB2, 0x6F42, 0x11D4, { 0xBC, 0xE7, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Protocol/MonotonicCounter.h + gEfiMonotonicCounterArchProtocolGuid = { 0x1DA97072, 0xBDDC, 0x4B30, { 0x99, 0xF1, 0x72, 0xA0, 0xB5, 0x6F, 0xFF, 0x2A }} + + ## Include/Protocol/RealTimeClock.h + gEfiRealTimeClockArchProtocolGuid = { 0x27CFAC87, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/Reset.h + gEfiResetArchProtocolGuid = { 0x27CFAC88, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/Runtime.h + gEfiRuntimeArchProtocolGuid = { 0xb7dfb4e1, 0x052f, 0x449f, { 0x87, 0xbe, 0x98, 0x18, 0xfc, 0x91, 0xb7, 0x33 }} + + ## Include/Protocol/Security.h + gEfiSecurityArchProtocolGuid = { 0xA46423E3, 0x4617, 0x49F1, { 0xB9, 0xFF, 0xD1, 0xBF, 0xA9, 0x11, 0x58, 0x39 }} + + ## Include/Protocol/SecurityPolicy.h + gEfiSecurityPolicyProtocolGuid = { 0x78E4D245, 0xCD4D, 0x4A05, { 0xA2, 0xBA, 0x47, 0x43, 0xE8, 0x6C, 0xFC, 0xAB }} + + ## Include/Protocol/Timer.h + gEfiTimerArchProtocolGuid = { 0x26BACCB3, 0x6F42, 0x11D4, { 0xBC, 0xE7, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Protocol/VariableWrite.h + gEfiVariableWriteArchProtocolGuid = { 0x6441F818, 0x6362, 0x4E44, { 0xB5, 0x70, 0x7D, 0xBA, 0x31, 0xDD, 0x24, 0x53 }} + + ## Include/Protocol/Variable.h + gEfiVariableArchProtocolGuid = { 0x1E5668E2, 0x8481, 0x11D4, { 0xBC, 0xF1, 0x00, 0x80, 0xC7, 0x3C, 0x88, 0x81 }} + + ## Include/Protocol/WatchdogTimer.h + gEfiWatchdogTimerArchProtocolGuid = { 0x665E3FF5, 0x46CC, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/StatusCode.h + gEfiStatusCodeRuntimeProtocolGuid = { 0xD2B2B828, 0x0826, 0x48A7, { 0xB3, 0xDF, 0x98, 0x3C, 0x00, 0x60, 0x24, 0xF0 }} + + ## Include/Protocol/SmbusHc.h + gEfiSmbusHcProtocolGuid = {0xe49d33ed, 0x513d, 0x4634, { 0xb6, 0x98, 0x6f, 0x55, 0xaa, 0x75, 0x1c, 0x1b} } + + ## Include/Protocol/FirmwareVolume2.h + gEfiFirmwareVolume2ProtocolGuid = { 0x220e73b6, 0x6bdb, 0x4413, { 0x84, 0x5, 0xb9, 0x74, 0xb1, 0x8, 0x61, 0x9a } } + + ## Include/Protocol/FirmwareVolumeBlock.h + gEfiFirmwareVolumeBlockProtocolGuid = { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } } + + ## Include/Protocol/Capsule.h + gEfiCapsuleArchProtocolGuid = { 0x5053697E, 0x2CBC, 0x4819, { 0x90, 0xD9, 0x05, 0x80, 0xDE, 0xEE, 0x57, 0x54 }} + + # + # Protocols defined in PI 1.2. + # + + ## Include/Protocol/MpService.h + gEfiMpServiceProtocolGuid = { 0x3fdda605, 0xa76e, 0x4f46, { 0xad, 0x29, 0x12, 0xf4, 0x53, 0x1b, 0x3d, 0x08 }} + + ## Include/Protocol/PciHostBridgeResourceAllocation.h + gEfiPciHostBridgeResourceAllocationProtocolGuid = { 0xCF8034BE, 0x6768, 0x4d8b, { 0xb7, 0x39, 0x7c, 0xce, 0x68, 0x3a, 0x9f, 0xbe }} + + ## Include/Protocol/PciPlatform.h + gEfiPciPlatformProtocolGuid = { 0x07d75280, 0x27d4, 0x4d69, { 0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41 }} + + ## Include/Protocol/PciOverride.h + gEfiPciOverrideProtocolGuid = { 0xb5b35764, 0x460c, 0x4a06, {0x99, 0xfc, 0x77, 0xa1, 0x7c, 0x1b, 0x5c, 0xeb }} + + ## Include/Protocol/PciEnumerationComplete.h + gEfiPciEnumerationCompleteProtocolGuid = { 0x30cfe3e7, 0x3de1, 0x4586, {0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93}} + + + ## Include/Protocol/IncompatiblePciDeviceSupport.h + gEfiIncompatiblePciDeviceSupportProtocolGuid = { 0xeb23f55a, 0x7863, 0x4ac2, { 0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75 }} + + ## Include/Protocol/PciHotPlugInit.h + gEfiPciHotPlugInitProtocolGuid = { 0xaa0e8bc1, 0xdabc, 0x46b0, { 0xa8, 0x44, 0x37, 0xb8, 0x16, 0x9b, 0x2b, 0xea }} + + ## This protocol is used to add or remove all PCI child devices on the PCI root bridge. + # Include/Protocol/PciHotPlugRequest.h + gEfiPciHotPlugRequestProtocolGuid = { 0x19CB87AB, 0x2CB9, 0x4665, { 0x83, 0x60, 0xDD, 0xCF, 0x60, 0x54, 0xF7, 0x9D }} + + ## Include/Protocol/IdeControllerInit.h + gEfiIdeControllerInitProtocolGuid = { 0xa1e37052, 0x80d9, 0x4e65, { 0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 }} + + ## Disk Info protocol is used to export Inquiry Data for a drive. + # Include/Protocol/DiskInfo.h + gEfiDiskInfoProtocolGuid = { 0xD432A67F, 0x14DC, 0x484B, { 0xB3, 0xBB, 0x3F, 0x02, 0x91, 0x84, 0x93, 0x27 }} + + ## Include/Protocol/Smbios.h + gEfiSmbiosProtocolGuid = {0x3583ff6, 0xcb36, 0x4940, { 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7}} + + ## Include/Protocol/S3SaveState.h + gEfiS3SaveStateProtocolGuid = {0xe857caf6, 0xc046, 0x45dc, { 0xbe, 0x3f, 0xee, 0x7, 0x65, 0xfb, 0xa8, 0x87}} + + ## Include/Protocol/S3SmmSaveState.h + gEfiS3SmmSaveStateProtocolGuid = {0x320afe62, 0xe593, 0x49cb, { 0xa9, 0xf1, 0xd4, 0xc2, 0xf4, 0xaf, 0x1, 0x4c}} + + ## Include/Protocol/ReportStatusCodeHandler.h + gEfiRscHandlerProtocolGuid = { 0x86212936, 0xe76, 0x41c8, { 0xa0, 0x3a, 0x2a, 0xf2, 0xfc, 0x1c, 0x39, 0xe2 }} + + ## Include/Protocol/SmmReportStatusCodeHandler.h + gEfiSmmRscHandlerProtocolGuid = { 0x2ff29fa7, 0x5e80, 0x4ed9, { 0xb3, 0x80, 0x1, 0x7d, 0x3c, 0x55, 0x4f, 0xf4 }} + + ## Include/Protocol/AcpiSystemDescriptionTable.h + gEfiAcpiSdtProtocolGuid = { 0xeb97088e, 0xcfdf, 0x49c6, { 0xbe, 0x4b, 0xd9, 0x6, 0xa5, 0xb2, 0xe, 0x86 }} + + ## Include/Protocol/SuperIo.h + gEfiSioProtocolGuid = { 0x215fdd18, 0xbd50, 0x4feb, { 0x89, 0xb, 0x58, 0xca, 0xb, 0x47, 0x39, 0xe9 }} + + ## Include/Protocol/SmmCpuIo2.h + gEfiSmmCpuIo2ProtocolGuid = { 0x3242a9d8, 0xce70, 0x4aa0, { 0x95, 0x5d, 0x5e, 0x7b, 0x14, 0x0d, 0xe4, 0xd2 }} + + ## Include/Protocol/SmmBase2.h + gEfiSmmBase2ProtocolGuid = { 0xf4ccbfb7, 0xf6e0, 0x47fd, { 0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }} + + ## Include/Protocol/SmmAccess2.h + gEfiSmmAccess2ProtocolGuid = { 0xc2702b74, 0x800c, 0x4131, { 0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac }} + + ## Include/Protocol/SmmControl2.h + gEfiSmmControl2ProtocolGuid = { 0x843dc720, 0xab1e, 0x42cb, { 0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b}} + + ## Include/Protocol/SmmConfiguration.h + gEfiSmmConfigurationProtocolGuid= { 0x26eeb3de, 0xb689, 0x492e, { 0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }} + + ## Include/Protocol/SmmReadyToLock.h + gEfiSmmReadyToLockProtocolGuid = { 0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 }} + + ## Include/Protocol/DxeSmmReadyToLock.h + gEfiDxeSmmReadyToLockProtocolGuid = { 0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e }} + + ## Include/Protocol/SmmCommunication.h + gEfiSmmCommunicationProtocolGuid = { 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 }} + + ## Include/Protocol/SmmStatusCode.h + gEfiSmmStatusCodeProtocolGuid = { 0x6afd2b77, 0x98c1, 0x4acd, { 0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1}} + + ## Include/Protocol/SmmCpu.h + gEfiSmmCpuProtocolGuid = { 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 }} + + ## Include/Protocol/SmmPciRootBridgeIo.h + gEfiSmmPciRootBridgeIoProtocolGuid = { 0x8bc1714d, 0xffcb, 0x41c3, { 0x89, 0xdc, 0x6c, 0x74, 0xd0, 0x6d, 0x98, 0xea }} + + ## Include/Protocol/SmmSwDispatch2.h + gEfiSmmSwDispatch2ProtocolGuid = { 0x18a3c6dc, 0x5eea, 0x48c8, {0xa1, 0xc1, 0xb5, 0x33, 0x89, 0xf9, 0x89, 0x99 }} + + ## Include/Protocol/SmmSxDispatch2.h + gEfiSmmSxDispatch2ProtocolGuid = { 0x456d2859, 0xa84b, 0x4e47, {0xa2, 0xee, 0x32, 0x76, 0xd8, 0x86, 0x99, 0x7d }} + + ## Include/Protocol/SmmPeriodicTimerDispatch2.h + gEfiSmmPeriodicTimerDispatch2ProtocolGuid = { 0x4cec368e, 0x8e8e, 0x4d71, {0x8b, 0xe1, 0x95, 0x8c, 0x45, 0xfc, 0x8a, 0x53 }} + + ## Include/Protocol/SmmUsbDispatch2.h + gEfiSmmUsbDispatch2ProtocolGuid = { 0xee9b8d90, 0xc5a6, 0x40a2, {0xbd, 0xe2, 0x52, 0x55, 0x8d, 0x33, 0xcc, 0xa1 }} + + ## Include/Protocol/SmmGpiDispatch2.h + gEfiSmmGpiDispatch2ProtocolGuid = { 0x25566b03, 0xb577, 0x4cbf, {0x95, 0x8c, 0xed, 0x66, 0x3e, 0xa2, 0x43, 0x80 }} + + ## Include/Protocol/SmmStandbyButtonDispatch2.h + gEfiSmmStandbyButtonDispatch2ProtocolGuid = { 0x7300c4a1, 0x43f2, 0x4017, {0xa5, 0x1b, 0xc8, 0x1a, 0x7f, 0x40, 0x58, 0x5b }} + + ## Include/Protocol/SmmPowerButtonDispatch2.h + gEfiSmmPowerButtonDispatch2ProtocolGuid = { 0x1b1183fa, 0x1823, 0x46a7, {0x88, 0x72, 0x9c, 0x57, 0x87, 0x55, 0x40, 0x9d }} + + ## Include/Protocol/SmmIoTrapDispatch2.h + gEfiSmmIoTrapDispatch2ProtocolGuid = { 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0xe, 0x29, 0x41, 0x8d, 0xf9, 0x30 }} + + ## Include/Protocol/PiPcd.h + gEfiPcdProtocolGuid = { 0x13a3f0f6, 0x264a, 0x3ef0, { 0xf2, 0xe0, 0xde, 0xc5, 0x12, 0x34, 0x2f, 0x34 } } + + ## Include/Protocol/FirmwareVolumeBlock.h + gEfiFirmwareVolumeBlock2ProtocolGuid = { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } } + + ## Include/Protocol/CpuIo2.h + gEfiCpuIo2ProtocolGuid = {0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f } } + + ## Include/Protocol/LegacyRegion2.h + gEfiLegacyRegion2ProtocolGuid = {0x70101eaf, 0x85, 0x440c, {0xb3, 0x56, 0x8e, 0xe3, 0x6f, 0xef, 0x24, 0xf0 } } + + # + # Protocols defined in PI 1.2.1 + # + + ## Include/Protocol/Security2.h + gEfiSecurity2ArchProtocolGuid = { 0x94ab2f58, 0x1438, 0x4ef1, {0x91, 0x52, 0x18, 0x94, 0x1a, 0x3a, 0x0e, 0x68 } } + + ## Include/Protocol/SmmEndOfDxe.h + gEfiSmmEndOfDxeProtocolGuid = { 0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d }} + + ## Include/Protocol/IsaHc.h + gEfiIsaHcProtocolGuid = { 0xbcdaf080, 0x1bde, 0x4e22, {0xae, 0x6a, 0x43, 0x54, 0x1e, 0x12, 0x8e, 0xc4 } } + gEfiIsaHcServiceBindingProtocolGuid = { 0xfad7933a, 0x6c21, 0x4234, {0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81 } } + + ## Include/Protocol/SuperIoControl.h + gEfiSioControlProtocolGuid = { 0xb91978df, 0x9fc1, 0x427d, { 0xbb, 0x5, 0x4c, 0x82, 0x84, 0x55, 0xca, 0x27 } } + + ## Include/Protocol/PiPcdInfo.h + gEfiGetPcdInfoProtocolGuid = { 0xfd0f4478, 0xefd, 0x461d, { 0xba, 0x2d, 0xe5, 0x8c, 0x45, 0xfd, 0x5f, 0x5e } } + + # + # Protocols defined in PI 1.3. + # + + ## Include/Protocol/I2cMaster.h + gEfiI2cMasterProtocolGuid = { 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} + + ## Include/Protocol/I2cIo.h + gEfiI2cIoProtocolGuid = { 0xb60a3e6b, 0x18c4, 0x46e5, { 0xa2, 0x9a, 0xc9, 0xa1, 0x06, 0x65, 0xa2, 0x8e }} + + ## Include/Protocol/I2cEnumerate.h + gEfiI2cEnumerateProtocolGuid = { 0xda8cd7c4, 0x1c00, 0x49e2, { 0x80, 0x3e, 0x52, 0x14, 0xe7, 0x01, 0x89, 0x4c }} + + ## Include/Protocol/I2cHost.h + gEfiI2cHostProtocolGuid = { 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, 0x33, 0x85, 0x49, 0x48 }} + + ## Include/Protocol/I2cBusConfigurationManagement.h + gEfiI2cBusConfigurationManagementProtocolGuid = { 0x55b71fb5, 0x17c6, 0x410e, { 0xb5, 0xbd, 0x5f, 0xa2, 0xe3, 0xd4, 0x46, 0x6b }} + + # + # Protocols defined in PI 1.5. + # + + ## Include/Protocol/MmMp.h + gEfiMmMpProtocolGuid = { 0x5d5450d7, 0x990c, 0x4180, { 0xa8, 0x3, 0x8e, 0x63, 0xf0, 0x60, 0x83, 0x7 }} + + ## Include/Protocol/MmEndOfDxe.h + gEfiMmEndOfDxeProtocolGuid = { 0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d }} + + ## Include/Protocol/MmIoTrapDispatch.h + gEfiMmIoTrapDispatchProtocolGuid = { 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0xe, 0x29, 0x41, 0x8d, 0xf9, 0x30 }} + + ## Include/Protocol/MmPowerButtonDispatch.h + gEfiMmPowerButtonDispatchProtocolGuid = { 0x1b1183fa, 0x1823, 0x46a7, {0x88, 0x72, 0x9c, 0x57, 0x87, 0x55, 0x40, 0x9d }} + + ## Include/Protocol/MmStandbyButtonDispatch.h + gEfiMmStandbyButtonDispatchProtocolGuid = { 0x7300c4a1, 0x43f2, 0x4017, {0xa5, 0x1b, 0xc8, 0x1a, 0x7f, 0x40, 0x58, 0x5b }} + + ## Include/Protocol/MmGpiDispatch.h + gEfiMmGpiDispatchProtocolGuid = { 0x25566b03, 0xb577, 0x4cbf, {0x95, 0x8c, 0xed, 0x66, 0x3e, 0xa2, 0x43, 0x80 }} + + ## Include/Protocol/MmUsbDispatch.h + gEfiMmUsbDispatchProtocolGuid = { 0xee9b8d90, 0xc5a6, 0x40a2, {0xbd, 0xe2, 0x52, 0x55, 0x8d, 0x33, 0xcc, 0xa1 }} + + ## Include/Protocol/MmPeriodicTimerDispatch.h + gEfiMmPeriodicTimerDispatchProtocolGuid = { 0x4cec368e, 0x8e8e, 0x4d71, {0x8b, 0xe1, 0x95, 0x8c, 0x45, 0xfc, 0x8a, 0x53 }} + + ## Include/Protocol/MmSxDispatch.h + gEfiMmSxDispatchProtocolGuid = { 0x456d2859, 0xa84b, 0x4e47, {0xa2, 0xee, 0x32, 0x76, 0xd8, 0x86, 0x99, 0x7d }} + + ## Include/Protocol/MmSwDispatch.h + gEfiMmSwDispatchProtocolGuid = { 0x18a3c6dc, 0x5eea, 0x48c8, {0xa1, 0xc1, 0xb5, 0x33, 0x89, 0xf9, 0x89, 0x99 }} + + ## Include/Protocol/MmPciRootBridgeIo.h + gEfiMmPciRootBridgeIoProtocolGuid = { 0x8bc1714d, 0xffcb, 0x41c3, { 0x89, 0xdc, 0x6c, 0x74, 0xd0, 0x6d, 0x98, 0xea }} + + ## Include/Protocol/MmCpu.h + gEfiMmCpuProtocolGuid = { 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 }} + + ## Include/Protocol/MmStatusCode.h + gEfiMmStatusCodeProtocolGuid = { 0x6afd2b77, 0x98c1, 0x4acd, { 0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1}} + + ## Include/Protocol/DxeMmReadyToLock.h + gEfiDxeMmReadyToLockProtocolGuid = { 0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e }} + + ## Include/Protocol/MmConfiguration.h + gEfiMmConfigurationProtocolGuid= { 0x26eeb3de, 0xb689, 0x492e, { 0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }} + + ## Include/Protocol/MmReadyToLock.h + gEfiMmReadyToLockProtocolGuid = { 0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 }} + + ## Include/Protocol/MmControl.h + gEfiMmControlProtocolGuid = { 0x843dc720, 0xab1e, 0x42cb, { 0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b}} + + ## Include/Protocol/MmAccess.h + gEfiMmAccessProtocolGuid = { 0xc2702b74, 0x800c, 0x4131, { 0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac }} + + ## Include/Protocol/MmBase.h + gEfiMmBaseProtocolGuid = { 0xf4ccbfb7, 0xf6e0, 0x47fd, { 0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }} + + ## Include/Protocol/MmCpuIo.h + gEfiMmCpuIoProtocolGuid = { 0x3242a9d8, 0xce70, 0x4aa0, { 0x95, 0x5d, 0x5e, 0x7b, 0x14, 0x0d, 0xe4, 0xd2 }} + + ## Include/Protocol/MmReportStatusCodeHandler.h + gEfiMmRscHandlerProtocolGuid = { 0x2ff29fa7, 0x5e80, 0x4ed9, { 0xb3, 0x80, 0x1, 0x7d, 0x3c, 0x55, 0x4f, 0xf4 }} + + ## Include/Protocol/MmCommunication.h + gEfiMmCommunicationProtocolGuid = { 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 }} + + # + # Protocols defined in PI 1.6. + # + + ## Include/Protocol/LegacySpiController.h + gEfiLegacySpiControllerProtocolGuid = { 0x39136fc7, 0x1a11, 0x49de, { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }} + + ## Include/Protocol/LegacySpiFlash.h + gEfiLegacySpiFlashProtocolGuid = { 0xf01bed57, 0x04bc, 0x4f3f, { 0x96, 0x60, 0xd6, 0xf2, 0xea, 0x22, 0x82, 0x59 }} + + ## Include/Protocol/LegacySpiSmmController.h + gEfiLegacySpiSmmControllerProtocolGuid = { 0x62331b78, 0xd8d0, 0x4c8c, { 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }} + + ## Include/Protocol/LegacySpiSmmFlash.h + gEfiLegacySpiSmmFlashProtocolGuid = { 0x5e3848d4, 0x0db5, 0x4fc0, { 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }} + + ## Include/Protocol/SpiConfiguration.h + gEfiSpiConfigurationProtocolGuid = { 0x85a6d3e6, 0xb65b, 0x4afc, { 0xb3, 0x8f, 0xc6, 0xd5, 0x4a, 0xf6, 0xdd, 0xc8 }} + + ## Include/Protocol/SpiHc.h + gEfiSpiHcProtocolGuid = { 0xc74e5db2, 0xfa96, 0x4ae2, { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }} + + ## Include/Protocol/SpiNorFlash.h + gEfiSpiNorFlashProtocolGuid = { 0xb57ec3fe, 0xf833, 0x4ba6, { 0x85, 0x78, 0x2a, 0x7d, 0x6a, 0x87, 0x44, 0x4b }} + + ## Include/Protocol/SpiSmmConfiguration.h + gEfiSpiSmmConfigurationProtocolGuid = { 0x995c6eca, 0x171b, 0x45fd, { 0xa3, 0xaa, 0xfd, 0x4c, 0x9c, 0x9d, 0xef, 0x59 }} + + ## Include/Protocol/SpiSmmHc.h + gEfiSpiSmmHcProtocolGuid = { 0xe9f02217, 0x2093, 0x4470, { 0x8a, 0x54, 0x5c, 0x2c, 0xff, 0xe7, 0x3e, 0xcb }} + + ## Include/Protocol/SpiSmmNorFlash.h + gEfiSpiSmmNorFlashProtocolGuid = { 0xaab18f19, 0xfe14, 0x4666, { 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a }} + + # + # Protocols defined in PI 1.7. + # + + ## Include/Protocol/MmCommunication2.h + gEfiMmCommunication2ProtocolGuid = { 0x378daedc, 0xf06b, 0x4446, { 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 }} + + # + # Protocols defined in UEFI2.1/UEFI2.0/EFI1.1 + # + + ## Include/Protocol/DebugPort.h + gEfiDebugPortProtocolGuid = { 0xEBA4E8D2, 0x3858, 0x41EC, { 0xA2, 0x81, 0x26, 0x47, 0xBA, 0x96, 0x60, 0xD0 }} + + ## Include/Protocol/DebugSupport.h + gEfiDebugSupportProtocolGuid = { 0x2755590C, 0x6F3C, 0x42FA, { 0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 }} + + ## Include/Protocol/Decompress.h + gEfiDecompressProtocolGuid = { 0xD8117CFE, 0x94A6, 0x11D4, { 0x9A, 0x3A, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/DeviceIo.h + gEfiDeviceIoProtocolGuid = { 0xAF6AC311, 0x84C3, 0x11D2, { 0x8E, 0x3C, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/DevicePath.h + gEfiDevicePathProtocolGuid = { 0x09576E91, 0x6D3F, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/DevicePathFromText.h + gEfiDevicePathFromTextProtocolGuid = { 0x05C99A21, 0xC70F, 0x4AD2, { 0x8A, 0x5F, 0x35, 0xDF, 0x33, 0x43, 0xF5, 0x1E }} + + ## Include/Protocol/DevicePathToText.h + gEfiDevicePathToTextProtocolGuid = { 0x8B843E20, 0x8132, 0x4852, { 0x90, 0xCC, 0x55, 0x1A, 0x4E, 0x4A, 0x7F, 0x1C }} + + ## Include/Protocol/DevicePathUtilities.h + gEfiDevicePathUtilitiesProtocolGuid = { 0x0379BE4E, 0xD706, 0x437D, { 0xB0, 0x37, 0xED, 0xB8, 0x2F, 0xB7, 0x72, 0xA4 }} + + ## Include/Protocol/DriverBinding.h + gEfiDriverBindingProtocolGuid = { 0x18A031AB, 0xB443, 0x4D1A, { 0xA5, 0xC0, 0x0C, 0x09, 0x26, 0x1E, 0x9F, 0x71 }} + + ## Include/Protocol/PlatformDriverOverride.h + gEfiPlatformDriverOverrideProtocolGuid = { 0x6b30c738, 0xa391, 0x11d4, {0x9a, 0x3b, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } } + + ## Include/Protocol/DriverFamilyOverride.h + gEfiDriverFamilyOverrideProtocolGuid = { 0xb1ee129e, 0xda36, 0x4181, { 0x91, 0xf8, 0x4, 0xa4, 0x92, 0x37, 0x66, 0xa7 }} + + ## Include/Protocol/BusSpecificDriverOverride.h + gEfiBusSpecificDriverOverrideProtocolGuid = { 0x3BC1B285, 0x8A15, 0x4A82, { 0xAA, 0xBF, 0x4D, 0x7D, 0x13, 0xFB, 0x32, 0x65 }} + + ## Include/Protocol/DriverDiagnostics2.h + gEfiDriverDiagnostics2ProtocolGuid = { 0x4D330321, 0x025F, 0x4AAC, { 0x90, 0xD8, 0x5E, 0xD9, 0x00, 0x17, 0x3B, 0x63 }} + + ## Include/Protocol/DriverDiagnostics.h + gEfiDriverDiagnosticsProtocolGuid = { 0x0784924F, 0xE296, 0x11D4, { 0x9A, 0x49, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/ComponentName2.h + gEfiComponentName2ProtocolGuid = { 0x6A7A5CFF, 0xE8D9, 0x4F70, { 0xBA, 0xDA, 0x75, 0xAB, 0x30, 0x25, 0xCE, 0x14 }} + + ## Include/Protocol/ComponentName.h + gEfiComponentNameProtocolGuid = { 0x107A772C, 0xD5E1, 0x11D4, { 0x9A, 0x46, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/DriverConfiguration2.h + gEfiDriverConfiguration2ProtocolGuid = { 0xBFD7DC1D, 0x24F1, 0x40D9, { 0x82, 0xE7, 0x2E, 0x09, 0xBB, 0x6B, 0x4E, 0xBE }} + + ## Include/Protocol/DriverConfiguration.h + gEfiDriverConfigurationProtocolGuid = { 0x107A772B, 0xD5E1, 0x11D4, { 0x9A, 0x46, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/PlatformToDriverConfiguration.h + gEfiPlatformToDriverConfigurationProtocolGuid = { 0x642cd590, 0x8059, 0x4c0a, { 0xa9, 0x58, 0xc5, 0xec, 0x7, 0xd2, 0x3c, 0x4b } } + + ## Include/Protocol/DriverSupportedEfiVersion.h + gEfiDriverSupportedEfiVersionProtocolGuid = { 0x5c198761, 0x16a8, 0x4e69, { 0x97, 0x2c, 0x89, 0xd6, 0x79, 0x54, 0xf8, 0x1d } } + + ## Include/Protocol/SimpleTextIn.h + gEfiSimpleTextInProtocolGuid = { 0x387477C1, 0x69C7, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/SimpleTextInEx.h + gEfiSimpleTextInputExProtocolGuid = {0xdd9e7534, 0x7762, 0x4698, { 0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa } } + + ## Include/Protocol/SimpleTextOut.h + gEfiSimpleTextOutProtocolGuid = { 0x387477C2, 0x69C7, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/SimplePointer.h + gEfiSimplePointerProtocolGuid = { 0x31878C87, 0x0B75, 0x11D5, { 0x9A, 0x4F, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/AbsolutePointer.h + gEfiAbsolutePointerProtocolGuid = { 0x8D59D32B, 0xC655, 0x4AE9, { 0x9B, 0x15, 0xF2, 0x59, 0x04, 0x99, 0x2A, 0x43 } } + + ## Include/Protocol/SerialIo.h + gEfiSerialIoProtocolGuid = { 0xBB25CF6F, 0xF1D4, 0x11D2, { 0x9A, 0x0C, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0xFD }} + + ## Include/Protocol/GraphicsOutput.h + gEfiGraphicsOutputProtocolGuid = { 0x9042A9DE, 0x23DC, 0x4A38, { 0x96, 0xFB, 0x7A, 0xDE, 0xD0, 0x80, 0x51, 0x6A }} + + ## Include/Protocol/EdidDiscovered.h + gEfiEdidDiscoveredProtocolGuid = { 0x1C0C34F6, 0xD380, 0x41FA, { 0xA0, 0x49, 0x8A, 0xD0, 0x6C, 0x1A, 0x66, 0xAA }} + + ## Include/Protocol/EdidActive.h + gEfiEdidActiveProtocolGuid = { 0xBD8C1056, 0x9F36, 0x44EC, { 0x92, 0xA8, 0xA6, 0x33, 0x7F, 0x81, 0x79, 0x86 }} + + ## Include/Protocol/EdidOverride.h + gEfiEdidOverrideProtocolGuid = { 0x48ECB431, 0xFB72, 0x45C0, { 0xA9, 0x22, 0xF4, 0x58, 0xFE, 0x04, 0x0B, 0xD5 }} + + ## Include/Protocol/UgaIo.h + gEfiUgaIoProtocolGuid = { 0x61A4D49E, 0x6F68, 0x4F1B, { 0xB9, 0x22, 0xA8, 0x6E, 0xED, 0x0B, 0x07, 0xA2 }} + + ## Include/Protocol/UgaDraw.h + gEfiUgaDrawProtocolGuid = { 0x982C298B, 0xF4FA, 0x41CB, { 0xB8, 0x38, 0x77, 0xAA, 0x68, 0x8F, 0xB8, 0x39 }} + + ## Include/Protocol/LoadedImage.h + gEfiLoadedImageProtocolGuid = { 0x5B1B31A1, 0x9562, 0x11D2, { 0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/LoadedImage.h + gEfiLoadedImageDevicePathProtocolGuid = { 0xbc62157e, 0x3e33, 0x4fec, {0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf }} + + ## Include/Protocol/LoadFile.h + gEfiLoadFileProtocolGuid = { 0x56EC3091, 0x954C, 0x11D2, { 0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/LoadFile2.h + gEfiLoadFile2ProtocolGuid = { 0x4006c0c1, 0xfcb3, 0x403e, {0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d }} + + ## Include/Protocol/SimpleFileSystem.h + gEfiSimpleFileSystemProtocolGuid = { 0x964E5B22, 0x6459, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/TapeIo.h + gEfiTapeIoProtocolGuid = { 0x1E93E633, 0xD65A, 0x459E, { 0xAB, 0x84, 0x93, 0xD9, 0xEC, 0x26, 0x6D, 0x18 }} + + ## Include/Protocol/DiskIo.h + gEfiDiskIoProtocolGuid = { 0xCE345171, 0xBA0B, 0x11D2, { 0x8E, 0x4F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/BlockIo.h + gEfiBlockIoProtocolGuid = { 0x964E5B21, 0x6459, 0x11D2, { 0x8E, 0x39, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/UnicodeCollation.h + gEfiUnicodeCollationProtocolGuid = { 0x1D85CD7F, 0xF43D, 0x11D2, { 0x9A, 0x0C, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/UnicodeCollation.h + gEfiUnicodeCollation2ProtocolGuid = {0xa4c751fc, 0x23ae, 0x4c3e, { 0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49 }} + + ## Include/Protocol/PciRootBridgeIo.h + gEfiPciRootBridgeIoProtocolGuid = { 0x2F707EBB, 0x4A1A, 0x11D4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/PciIo.h + gEfiPciIoProtocolGuid = { 0x4CF5B200, 0x68B8, 0x4CA5, { 0x9E, 0xEC, 0xB2, 0x3E, 0x3F, 0x50, 0x02, 0x9A }} + + ## Include/Protocol/ScsiIo.h + gEfiScsiIoProtocolGuid = { 0x932F47e6, 0x2362, 0x4002, { 0x80, 0x3E, 0x3C, 0xD5, 0x4B, 0x13, 0x8F, 0x85 }} + + ## Include/Protocol/ScsiPassThruExt.h + gEfiExtScsiPassThruProtocolGuid = { 0x143b7632, 0xb81b, 0x4cb7, {0xab, 0xd3, 0xb6, 0x25, 0xa5, 0xb9, 0xbf, 0xfe }} + + ## Include/Protocol/ScsiPassThru.h + gEfiScsiPassThruProtocolGuid = { 0xA59E8FCF, 0xBDA0, 0x43BB, { 0x90, 0xB1, 0xD3, 0x73, 0x2E, 0xCA, 0xA8, 0x77 }} + + ## Include/Protocol/IScsiInitiatorName.h + gEfiIScsiInitiatorNameProtocolGuid = { 0x59324945, 0xEC44, 0x4C0D, { 0xB1, 0xCD, 0x9D, 0xB1, 0x39, 0xDF, 0x07, 0x0C }} + + ## Include/Protocol/Usb2HostController.h + gEfiUsb2HcProtocolGuid = { 0x3E745226, 0x9818, 0x45B6, { 0xA2, 0xAC, 0xD7, 0xCD, 0x0E, 0x8B, 0xA2, 0xBC }} + + ## Include/Protocol/UsbHostController.h + gEfiUsbHcProtocolGuid = { 0xF5089266, 0x1AA0, 0x4953, { 0x97, 0xD8, 0x56, 0x2F, 0x8A, 0x73, 0xB5, 0x19 }} + + ## Include/Protocol/UsbIo.h + gEfiUsbIoProtocolGuid = { 0x2B2F68D6, 0x0CD2, 0x44CF, { 0x8E, 0x8B, 0xBB, 0xA2, 0x0B, 0x1B, 0x5B, 0x75 }} + + ## Include/Protocol/AcpiTable.h + gEfiAcpiTableProtocolGuid = { 0xFFE06BDD, 0x6107, 0x46A6, { 0x7B, 0xB2, 0x5A, 0x9C, 0x7E, 0xC5, 0x27, 0x5C }} + + ## Include/Protocol/Ebc.h + gEfiEbcProtocolGuid = { 0x13AC6DD1, 0x73D0, 0x11D4, { 0xB0, 0x6B, 0x00, 0xAA, 0x00, 0xBD, 0x6D, 0xE7 }} + + ## Include/Protocol/SimpleNetwork.h + gEfiSimpleNetworkProtocolGuid = { 0xA19832B9, 0xAC25, 0x11D3, { 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/NetworkInterfaceIdentifier.h + gEfiNetworkInterfaceIdentifierProtocolGuid_31 = { 0x1ACED566, 0x76ED, 0x4218, { 0xBC, 0x81, 0x76, 0x7F, 0x1F, 0x97, 0x7A, 0x89 }} + + ## Include/Protocol/NetworkInterfaceIdentifier.h + gEfiNetworkInterfaceIdentifierProtocolGuid = { 0xE18541CD, 0xF755, 0x4F73, { 0x92, 0x8D, 0x64, 0x3C, 0x8A, 0x79, 0xB2, 0x29 }} + + ## Include/Protocol/PxeBaseCodeCallBack.h + gEfiPxeBaseCodeCallbackProtocolGuid = { 0x245DCA21, 0xFB7B, 0x11D3, { 0x8F, 0x01, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B }} + + ## Include/Protocol/PxeBaseCode.h + gEfiPxeBaseCodeProtocolGuid = { 0x03C4E603, 0xAC28, 0x11D3, { 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} + + ## Include/Protocol/Bis.h + gEfiBisProtocolGuid = { 0x0B64AAB0, 0x5429, 0x11D4, { 0x98, 0x16, 0x00, 0xA0, 0xC9, 0x1F, 0xAD, 0xCF }} + + ## Include/Protocol/ManagedNetwork.h + gEfiManagedNetworkServiceBindingProtocolGuid = { 0xF36FF770, 0xA7E1, 0x42CF, { 0x9E, 0xD2, 0x56, 0xF0, 0xF2, 0x71, 0xF4, 0x4C }} + + ## Include/Protocol/ManagedNetwork.h + gEfiManagedNetworkProtocolGuid = { 0x7ab33a91, 0xace5, 0x4326, { 0xb5, 0x72, 0xe7, 0xee, 0x33, 0xd3, 0x9f, 0x16 }} + + ## Include/Protocol/Arp.h + gEfiArpServiceBindingProtocolGuid = { 0xF44C00EE, 0x1F2C, 0x4A00, { 0xAA, 0x09, 0x1C, 0x9F, 0x3E, 0x08, 0x00, 0xA3 }} + + ## Include/Protocol/Arp.h + gEfiArpProtocolGuid = { 0xF4B427BB, 0xBA21, 0x4F16, { 0xBC, 0x4E, 0x43, 0xE4, 0x16, 0xAB, 0x61, 0x9C }} + + ## Include/Protocol/Dhcp4.h + gEfiDhcp4ServiceBindingProtocolGuid = { 0x9D9A39D8, 0xBD42, 0x4A73, { 0xA4, 0xD5, 0x8E, 0xE9, 0x4B, 0xE1, 0x13, 0x80 }} + + ## Include/Protocol/Dhcp4.h + gEfiDhcp4ProtocolGuid = { 0x8A219718, 0x4EF5, 0x4761, { 0x91, 0xC8, 0xC0, 0xF0, 0x4B, 0xDA, 0x9E, 0x56 }} + + ## Include/Protocol/Tcp4.h + gEfiTcp4ServiceBindingProtocolGuid = { 0x00720665, 0x67EB, 0x4A99, { 0xBA, 0xF7, 0xD3, 0xC3, 0x3A, 0x1C, 0x7C, 0xC9 }} + + ## Include/Protocol/Tcp4.h + gEfiTcp4ProtocolGuid = { 0x65530BC7, 0xA359, 0x410F, { 0xB0, 0x10, 0x5A, 0xAD, 0xC7, 0xEC, 0x2B, 0x62 }} + + ## Include/Protocol/Ip4.h + gEfiIp4ServiceBindingProtocolGuid = { 0xC51711E7, 0xB4BF, 0x404A, { 0xBF, 0xB8, 0x0A, 0x04, 0x8E, 0xF1, 0xFF, 0xE4 }} + + ## Include/Protocol/Ip4.h + gEfiIp4ProtocolGuid = { 0x41D94CD2, 0x35B6, 0x455A, { 0x82, 0x58, 0xD4, 0xE5, 0x13, 0x34, 0xAA, 0xDD }} + + ## Include/Protocol/Ip4Config.h + gEfiIp4ConfigProtocolGuid = { 0x3B95AA31, 0x3793, 0x434B, { 0x86, 0x67, 0xC8, 0x07, 0x08, 0x92, 0xE0, 0x5E }} + + ## Include/Protocol/Udp4.h + gEfiUdp4ServiceBindingProtocolGuid = { 0x83F01464, 0x99BD, 0x45E5, { 0xB3, 0x83, 0xAF, 0x63, 0x05, 0xD8, 0xE9, 0xE6 }} + + ## Include/Protocol/Udp4.h + gEfiUdp4ProtocolGuid = { 0x3AD9DF29, 0x4501, 0x478D, { 0xB1, 0xF8, 0x7F, 0x7F, 0xE7, 0x0E, 0x50, 0xF3 }} + + ## Include/Protocol/Mtftp4.h + gEfiMtftp4ServiceBindingProtocolGuid = { 0x2FE800BE, 0x8F01, 0x4AA6, { 0x94, 0x6B, 0xD7, 0x13, 0x88, 0xE1, 0x83, 0x3F }} + + ## Include/Protocol/Mtftp4.h + gEfiMtftp4ProtocolGuid = { 0x78247C57, 0x63DB, 0x4708, { 0x99, 0xC2, 0xA8, 0xB4, 0xA9, 0xA6, 0x1F, 0x6B }} + + ## Include/Protocol/AuthenticationInfo.h + gEfiAuthenticationInfoProtocolGuid = { 0x7671D9D0, 0x53DB, 0x4173, { 0xAA, 0x69, 0x23, 0x27, 0xF2, 0x1F, 0x0B, 0xC7 }} + + ## Include/Protocol/Hash.h + gEfiHashServiceBindingProtocolGuid = { 0x42881c98, 0xa4f3, 0x44b0, { 0xa3, 0x9d, 0xdf, 0xa1, 0x86, 0x67, 0xd8, 0xcd }} + + ## Include/Protocol/Hash.h + gEfiHashProtocolGuid = { 0xC5184932, 0xDBA5, 0x46DB, { 0xA5, 0xBA, 0xCC, 0x0B, 0xDA, 0x9C, 0x14, 0x35 }} + + ## Include/Protocol/TcgService.h + gEfiTcgProtocolGuid = { 0xf541796d, 0xa62e, 0x4954, { 0xa7, 0x75, 0x95, 0x84, 0xf6, 0x1b, 0x9c, 0xdd }} + + ## Include/Protocol/TrEEProtocol.h + gEfiTrEEProtocolGuid = {0x607f766c, 0x7455, 0x42be, { 0x93, 0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f }} + + ## Include/Protocol/Tcg2Protocol.h + gEfiTcg2ProtocolGuid = {0x607f766c, 0x7455, 0x42be, { 0x93, 0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f }} + gEfiTcg2FinalEventsTableGuid = {0x1e2ed096, 0x30e2, 0x4254, { 0xbd, 0x89, 0x86, 0x3b, 0xbe, 0xf8, 0x23, 0x25 }} + + ## Include/Protocol/FormBrowser2.h + gEfiFormBrowser2ProtocolGuid = {0xb9d4c360, 0xbcfb, 0x4f9b, {0x92, 0x98, 0x53, 0xc1, 0x36, 0x98, 0x22, 0x58}} + + ## Include/Protocol/HiiString.h + gEfiHiiStringProtocolGuid = {0x0fd96974, 0x23aa, 0x4cdc, {0xb9, 0xcb, 0x98, 0xd1, 0x77, 0x50, 0x32, 0x2a}} + + ## Include/Protocol/HiiImage.h + gEfiHiiImageProtocolGuid = {0x31a6406a, 0x6bdf, 0x4e46, {0xb2, 0xa2, 0xeb, 0xaa, 0x89, 0xc4, 0x09, 0x20}} + + ## Include/Protocol/HiiConfigRouting.h + gEfiHiiConfigRoutingProtocolGuid = {0x587e72d7, 0xcc50, 0x4f79, {0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f}} + + ## Include/Protocol/HiiDatabase.h + gEfiHiiDatabaseProtocolGuid = {0xef9fc172, 0xa1b2, 0x4693, {0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42}} + + ## Include/Protocol/HiiFont.h + gEfiHiiFontProtocolGuid = {0xe9ca4775, 0x8657, 0x47fc, {0x97, 0xe7, 0x7e, 0xd6, 0x5a, 0x08, 0x43, 0x24}} + + ## Include/Protocol/HiiConfigAccess.h + gEfiHiiConfigAccessProtocolGuid = {0x330d4706, 0xf2a0, 0x4e4f, {0xa3, 0x69, 0xb6, 0x6f, 0xa8, 0xd5, 0x43, 0x85}} + + ## Include/Protocol/HiiPackageList.h + gEfiHiiPackageListProtocolGuid = { 0x6a1ee763, 0xd47a, 0x43b4, {0xaa, 0xbe, 0xef, 0x1d, 0xe2, 0xab, 0x56, 0xfc}} + + # + # Protocols defined in UEFI2.2 + # + ## Include/Protocol/Ip6.h + gEfiIp6ServiceBindingProtocolGuid = { 0xec835dd3, 0xfe0f, 0x617b, {0xa6, 0x21, 0xb3, 0x50, 0xc3, 0xe1, 0x33, 0x88 }} + + ## Include/Protocol/Ip6.h + gEfiIp6ProtocolGuid = { 0x2c8759d5, 0x5c2d, 0x66ef, {0x92, 0x5f, 0xb6, 0x6c, 0x10, 0x19, 0x57, 0xe2 }} + + ## Include/Protocol/Ip6Config.h + gEfiIp6ConfigProtocolGuid = { 0x937fe521, 0x95ae, 0x4d1a, {0x89, 0x29, 0x48, 0xbc, 0xd9, 0x0a, 0xd3, 0x1a }} + + ## Include/Protocol/Mtftp6.h + gEfiMtftp6ServiceBindingProtocolGuid = { 0xd9760ff3, 0x3cca, 0x4267, {0x80, 0xf9, 0x75, 0x27, 0xfa, 0xfa, 0x42, 0x23 }} + + ## Include/Protocol/Mtftp6.h + gEfiMtftp6ProtocolGuid = { 0xbf0a78ba, 0xec29, 0x49cf, {0xa1, 0xc9, 0x7a, 0xe5, 0x4e, 0xab, 0x6a, 0x51 }} + + ## Include/Protocol/Dhcp6.h + gEfiDhcp6ServiceBindingProtocolGuid = { 0x9fb9a8a1, 0x2f4a, 0x43a6, {0x88, 0x9c, 0xd0, 0xf7, 0xb6, 0xc4, 0x7a, 0xd5 }} + + ## Include/Protocol/Dhcp6.h + gEfiDhcp6ProtocolGuid = { 0x87c8bad7, 0x595, 0x4053, {0x82, 0x97, 0xde, 0xde, 0x39, 0x5f, 0x5d, 0x5b }} + + ## Include/Protocol/Udp6.h + gEfiUdp6ServiceBindingProtocolGuid = { 0x66ed4721, 0x3c98, 0x4d3e, {0x81, 0xe3, 0xd0, 0x3d, 0xd3, 0x9a, 0x72, 0x54 }} + + ## Include/Protocol/Udp6.h + gEfiUdp6ProtocolGuid = { 0x4f948815, 0xb4b9, 0x43cb, {0x8a, 0x33, 0x90, 0xe0, 0x60, 0xb3, 0x49, 0x55 }} + + ## Include/Protocol/Tcp6.h + gEfiTcp6ServiceBindingProtocolGuid = { 0xec20eb79, 0x6c1a, 0x4664, {0x9a, 0x0d, 0xd2, 0xe4, 0xcc, 0x16, 0xd6, 0x64 }} + + ## Include/Protocol/Tcp6.h + gEfiTcp6ProtocolGuid = { 0x46e44855, 0xbd60, 0x4ab7, {0xab, 0x0d, 0xa6, 0x79, 0xb9, 0x44, 0x7d, 0x77 }} + + ## Include/Protocol/VlanConfig.h + gEfiVlanConfigProtocolGuid = { 0x9e23d768, 0xd2f3, 0x4366, {0x9f, 0xc3, 0x3a, 0x7a, 0xba, 0x86, 0x43, 0x74 }} + + ## Include/Protocol/Eap.h + gEfiEapProtocolGuid = { 0x5d9f96db, 0xe731, 0x4caa, {0xa0, 0xd, 0x72, 0xe1, 0x87, 0xcd, 0x77, 0x62 }} + + ## Include/Protocol/EapManagement.h + gEfiEapManagementProtocolGuid = { 0xbb62e663, 0x625d, 0x40b2, {0xa0, 0x88, 0xbb, 0xe8, 0x36, 0x23, 0xa2, 0x45 }} + + ## Include/Protocol/Ftp4.h + gEfiFtp4ServiceBindingProtocolGuid = { 0xfaaecb1, 0x226e, 0x4782, {0xaa, 0xce, 0x7d, 0xb9, 0xbc, 0xbf, 0x4d, 0xaf }} + + ## Include/Protocol/Ftp4.h + gEfiFtp4ProtocolGuid = { 0xeb338826, 0x681b, 0x4295, {0xb3, 0x56, 0x2b, 0x36, 0x4c, 0x75, 0x7b, 0x9 }} + + ## Include/Protocol/IpSecConfig.h + gEfiIpSecConfigProtocolGuid = { 0xce5e5929, 0xc7a3, 0x4602, {0xad, 0x9e, 0xc9, 0xda, 0xf9, 0x4e, 0xbf, 0xcf }} + + ## Include/Protocol/DriverHealth.h + gEfiDriverHealthProtocolGuid = { 0x2a534210, 0x9280, 0x41d8, {0xae, 0x79, 0xca, 0xda, 0x1, 0xa2, 0xb1, 0x27 }} + + ## Include/Protocol/DeferredImageLoad.h + gEfiDeferredImageLoadProtocolGuid = { 0x15853d7c, 0x3ddf, 0x43e0, {0xa1, 0xcb, 0xeb, 0xf8, 0x5b, 0x8f, 0x87, 0x2c }} + + ## Include/Protocol/UserCredential.h + gEfiUserCredentialProtocolGuid = { 0x71ee5e94, 0x65b9, 0x45d5, {0x82, 0x1a, 0x3a, 0x4d, 0x86, 0xcf, 0xe6, 0xbe }} + + ## Include/Protocol/UserManager.h + gEfiUserManagerProtocolGuid = { 0x6fd5b00c, 0xd426, 0x4283, {0x98, 0x87, 0x6c, 0xf5, 0xcf, 0x1c, 0xb1, 0xfe }} + + ## Include/Protocol/AtaPassThru.h + gEfiAtaPassThruProtocolGuid = { 0x1d3de7f0, 0x807, 0x424f, {0xaa, 0x69, 0x11, 0xa5, 0x4e, 0x19, 0xa4, 0x6f }} + + # + # Protocols defined in UEFI2.3 + # + ## Include/Protocol/FirmwareManagement.h + gEfiFirmwareManagementProtocolGuid = { 0x86c77a67, 0xb97, 0x4633, {0xa1, 0x87, 0x49, 0x10, 0x4d, 0x6, 0x85, 0xc7 }} + + ## Include/Protocol/IpSec.h + gEfiIpSecProtocolGuid = { 0xdfb386f7, 0xe100, 0x43ad, {0x9c, 0x9a, 0xed, 0x90, 0xd0, 0x8a, 0x5e, 0x12 }} + + ## Include/Protocol/IpSec.h + gEfiIpSec2ProtocolGuid = { 0xa3979e64, 0xace8, 0x4ddc, {0xbc, 0x7, 0x4d, 0x66, 0xb8, 0xfd, 0x9, 0x77 }} + + # + # Protocols defined in UEFI2.3.1 + # + ## Include/Protocol/Kms.h + gEfiKmsProtocolGuid = { 0xEC3A978D, 0x7C4E, 0x48FA, {0x9A, 0xBE, 0x6A, 0xD9, 0x1C, 0xC8, 0xF8, 0x11 }} + + ## Include/Protocol/BlockIo2.h + gEfiBlockIo2ProtocolGuid = { 0xa77b2472, 0xe282, 0x4e9f, {0xa2, 0x45, 0xc2, 0xc0, 0xe2, 0x7b, 0xbc, 0xc1 }} + + ## Include/Protocol/StorageSecurityCommand.h + gEfiStorageSecurityCommandProtocolGuid = { 0xc88b0b6d, 0x0dfc, 0x49a7, {0x9c, 0xb4, 0x49, 0x7, 0x4b, 0x4c, 0x3a, 0x78 }} + + ## Include/Protocol/UserCredential2.h + gEfiUserCredential2ProtocolGuid = { 0xe98adb03, 0xb8b9, 0x4af8, {0xba, 0x20, 0x26, 0xe9, 0x11, 0x4c, 0xbc, 0xe5 }} + + # + # Protocols defined in UEFI2.4 + # + ## Include/Protocol/DiskIo2.h + gEfiDiskIo2ProtocolGuid = { 0x151c8eae, 0x7f2c, 0x472c, { 0x9e, 0x54, 0x98, 0x28, 0x19, 0x4f, 0x6a, 0x88 }} + + ## Include/Protocol/Timestamp.h + gEfiTimestampProtocolGuid = { 0xafbfde41, 0x2e6e, 0x4262, {0xba, 0x65, 0x62, 0xb9, 0x23, 0x6e, 0x54, 0x95 }} + + ## Include/Protocol/Rng.h + gEfiRngProtocolGuid = { 0x3152bca5, 0xeade, 0x433d, {0x86, 0x2e, 0xc0, 0x1c, 0xdc, 0x29, 0x1f, 0x44 }} + + ## Include/Protocol/AdapterInformation.h + gEfiAdapterInformationProtocolGuid = { 0xE5DD1403, 0xD622, 0xC24E, {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }} + + # + # Protocols defined in UEFI2.5 + # + ## Include/Protocol/NvmExpressPassthru.h + gEfiNvmExpressPassThruProtocolGuid = { 0x52c78312, 0x8edc, 0x4233, { 0x98, 0xf2, 0x1a, 0x1a, 0xa5, 0xe3, 0x88, 0xa5 }} + + ## Include/Protocol/Hash2.h + gEfiHash2ServiceBindingProtocolGuid = { 0xda836f8d, 0x217f, 0x4ca0, { 0x99, 0xc2, 0x1c, 0xa4, 0xe1, 0x60, 0x77, 0xea }} + + ## Include/Protocol/Hash2.h + gEfiHash2ProtocolGuid = { 0x55b1d734, 0xc5e1, 0x49db, { 0x96, 0x47, 0xb1, 0x6a, 0xfb, 0xe, 0x30, 0x5b }} + + ## Include/Protocol/BlockIoCrypto.h + gEfiBlockIoCryptoProtocolGuid = { 0xa00490ba, 0x3f1a, 0x4b4c, { 0xab, 0x90, 0x4f, 0xa9, 0x97, 0x26, 0xa1, 0xe8 }} + + ## Include/Protocol/SmartCardReader.h + gEfiSmartCardReaderProtocolGuid = { 0x2a4d1adf, 0x21dc, 0x4b81, {0xa4, 0x2f, 0x8b, 0x8e, 0xe2, 0x38, 0x00, 0x60 }} + + ## Include/Protocol/SmartCardEdge.h + gEfiSmartCardEdgeProtocolGuid = { 0xd317f29b, 0xa325, 0x4712, {0x9b, 0xf1, 0xc6, 0x19, 0x54, 0xdc, 0x19, 0x8c }} + + ## Include/Protocol/UsbFunctionIo.h + gEfiUsbFunctionIoProtocolGuid = { 0x32d2963a, 0xfe5d, 0x4f30, {0xb6, 0x33, 0x6e, 0x5d, 0xc5, 0x58, 0x3, 0xcc }} + + ## Include/Protocol/BluetoothHc.h + gEfiBluetoothHcProtocolGuid = { 0xb3930571, 0xbeba, 0x4fc5, { 0x92, 0x3, 0x94, 0x27, 0x24, 0x2e, 0x6a, 0x43 }} + + ## Include/Protocol/BluetoothIo.h + gEfiBluetoothIoServiceBindingProtocolGuid = { 0x388278d3, 0x7b85, 0x42f0, { 0xab, 0xa9, 0xfb, 0x4b, 0xfd, 0x69, 0xf5, 0xab }} + gEfiBluetoothIoProtocolGuid = { 0x467313de, 0x4e30, 0x43f1, { 0x94, 0x3e, 0x32, 0x3f, 0x89, 0x84, 0x5d, 0xb5 }} + + ## Include/Protocol/BluetoothConfig.h + gEfiBluetoothConfigProtocolGuid = { 0x62960cf3, 0x40ff, 0x4263, { 0xa7, 0x7c, 0xdf, 0xde, 0xbd, 0x19, 0x1b, 0x4b }} + + ## Include/Protocol/RegularExpressionProtocol.h + gEfiRegularExpressionProtocolGuid = { 0xB3F79D9A, 0x436C, 0xDC11, {0xB0, 0x52, 0xCD, 0x85, 0xDF, 0x52, 0x4C, 0xE6 }} + + ## Include/Protocol/BootManagerPolicy.h + gEfiBootManagerPolicyProtocolGuid = { 0xfedf8e0c, 0xe147, 0x11e3, { 0x99, 0x03, 0xb8, 0xe8, 0x56, 0x2c, 0xba, 0xfa }} + + ## Include/Protocol/HiiConfigKeyword.h + gEfiConfigKeywordHandlerProtocolGuid = {0x0a8badd5, 0x03b8, 0x4d19, {0xb1, 0x28, 0x7b, 0x8f, 0x0e, 0xda, 0xa5, 0x96}} + + ## Include/Protocol/WiFi.h + gEfiWiFiProtocolGuid = { 0xda55bc9, 0x45f8, 0x4bb4, {0x87, 0x19, 0x52, 0x24, 0xf1, 0x8a, 0x4d, 0x45 }} + + ## Include/Protocol/EapManagement2.h + gEfiEapManagement2ProtocolGuid = { 0x5e93c847, 0x456d, 0x40b3, {0xa6, 0xb4, 0x78, 0xb0, 0xc9, 0xcf, 0x7f, 0x20 }} + + ## Include/Protocol/EapConfiguration.h + gEfiEapConfigurationProtocolGuid = { 0xe5b58dbb, 0x7688, 0x44b4, {0x97, 0xbf, 0x5f, 0x1d, 0x4b, 0x7c, 0xc8, 0xdb }} + + ## Include/Protocol/Pkcs7Verify.h + gEfiPkcs7VerifyProtocolGuid = { 0x47889fb2, 0xd671, 0x4fab, { 0xa0, 0xca, 0xdf, 0x0e, 0x44, 0xdf, 0x70, 0xd6 }} + + ## Include/Protocol/Ip4Config2.h + gEfiIp4Config2ProtocolGuid = { 0x5b446ed1, 0xe30b, 0x4faa, {0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80 }} + + ## Include/Protocol/Dns4.h + gEfiDns4ServiceBindingProtocolGuid = { 0xb625b186, 0xe063, 0x44f7, { 0x89, 0x5, 0x6a, 0x74, 0xdc, 0x6f, 0x52, 0xb4 }} + + ## Include/Protocol/Dns4.h + gEfiDns4ProtocolGuid = { 0xae3d28cc, 0xe05b, 0x4fa1, { 0xa0, 0x11, 0x7e, 0xb5, 0x5a, 0x3f, 0x14, 0x1 }} + + ## Include/Protocol/Dns6.h + gEfiDns6ServiceBindingProtocolGuid = { 0x7f1647c8, 0xb76e, 0x44b2, { 0xa5, 0x65, 0xf7, 0xf, 0xf1, 0x9c, 0xd1, 0x9e }} + + ## Include/Protocol/Dns6.h + gEfiDns6ProtocolGuid = { 0xca37bc1f, 0xa327, 0x4ae9, { 0x82, 0x8a, 0x8c, 0x40, 0xd8, 0x50, 0x6a, 0x17 }} + + ## Include/Protocol/Http.h + gEfiHttpServiceBindingProtocolGuid = { 0xbdc8e6af, 0xd9bc, 0x4379, {0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c }} + + ## Include/Protocol/Http.h + gEfiHttpProtocolGuid = { 0x7a59b29b, 0x910b, 0x4171, {0x82, 0x42, 0xa8, 0x5a, 0x0d, 0xf2, 0x5b, 0x5b }} + + ## Include/Protocol/HttpUtilities.h + gEfiHttpUtilitiesProtocolGuid = { 0x3e35c163, 0x4074, 0x45dd, {0x43, 0x1e, 0x23, 0x98, 0x9d, 0xd8, 0x6b, 0x32 }} + + ## Include/Protocol/Tls.h + gEfiTlsServiceBindingProtocolGuid = { 0x952cb795, 0xff36, 0x48cf, {0xa2, 0x49, 0x4d, 0xf4, 0x86, 0xd6, 0xab, 0x8d }} + + ## Include/Protocol/Tls.h + gEfiTlsProtocolGuid = { 0xca959f, 0x6cfa, 0x4db1, {0x95, 0xbc, 0xe4, 0x6c, 0x47, 0x51, 0x43, 0x90 }} + + ## Include/Protocol/TlsConfig.h + gEfiTlsConfigurationProtocolGuid = { 0x1682fe44, 0xbd7a, 0x4407, { 0xb7, 0xc7, 0xdc, 0xa3, 0x7c, 0xa3, 0x92, 0x2d }} + + ## Include/Protocol/Rest.h + gEfiRestProtocolGuid = { 0x0db48a36, 0x4e54, 0xea9c, {0x9b, 0x09, 0x1e, 0xa5, 0xbe, 0x3a, 0x66, 0x0b }} + + ## Include/Protocol/Supplicant.h + gEfiSupplicantServiceBindingProtocolGuid = { 0x45bcd98e, 0x59ad, 0x4174, { 0x95, 0x46, 0x34, 0x4a, 0x7, 0x48, 0x58, 0x98 }} + gEfiSupplicantProtocolGuid = { 0x54fcc43e, 0xaa89, 0x4333, { 0x9a, 0x85, 0xcd, 0xea, 0x24, 0x5, 0x1e, 0x9e }} + + # + # Protocols defined in UEFI2.6 + # + ## Include/Protocol/WiFi2.h + gEfiWiFi2ProtocolGuid = { 0x1b0fb9bf, 0x699d, 0x4fdd, {0xa7, 0xc3, 0x25, 0x46, 0x68, 0x1b, 0xf6, 0x3b }} + + ## Include/Protocol/RamDisk.h + gEfiRamDiskProtocolGuid = { 0xab38a0df, 0x6873, 0x44a9, { 0x87, 0xe6, 0xd4, 0xeb, 0x56, 0x14, 0x84, 0x49 }} + + ## Include/Protocol/ImageDecoder.h + gEfiHiiImageDecoderProtocolGuid = { 0x9e66f251, 0x727c, 0x418c, { 0xbf, 0xd6, 0xc2, 0xb4, 0x25, 0x28, 0x18, 0xea }} + + ## Include/Protocol/HiiImageEx.h + gEfiHiiImageExProtocolGuid = { 0x1a1241e6, 0x8f19, 0x41a9, { 0xbc, 0xe, 0xe8, 0xef, 0x39, 0xe0, 0x65, 0x46 }} + + ## Include/Protocol/SdMmcPassThru.h + gEfiSdMmcPassThruProtocolGuid = { 0x716ef0d9, 0xff83, 0x4f69, {0x81, 0xe9, 0x51, 0x8b, 0xd3, 0x9a, 0x8e, 0x70 }} + + ## Include/Protocol/EraseBlock.h + gEfiEraseBlockProtocolGuid = { 0x95a9a93e, 0xa86e, 0x4926, {0xaa, 0xef, 0x99, 0x18, 0xe7, 0x72, 0xd9, 0x87 }} + + # + # Protocols defined in UEFI2.7 + # + ## Include/Protocol/BluetoothAttribute.h + gEfiBluetoothAttributeProtocolGuid = { 0x898890e9, 0x84b2, 0x4f3a, { 0x8c, 0x58, 0xd8, 0x57, 0x78, 0x13, 0xe0, 0xac } } + gEfiBluetoothAttributeServiceBindingProtocolGuid = { 0x5639867a, 0x8c8e, 0x408d, {0xac, 0x2f, 0x4b, 0x61, 0xbd, 0xc0, 0xbb, 0xbb }} + + ## Include/Protocol/BluetoothLeConfig.h + gEfiBluetoothLeConfigProtocolGuid = { 0x8f76da58, 0x1f99, 0x4275, { 0xa4, 0xec, 0x47, 0x56, 0x51, 0x5b, 0x1c, 0xe8 } } + + ## Include/Protocol/UfsDeviceConfig.h + gEfiUfsDeviceConfigProtocolGuid = { 0xb81bfab0, 0xeb3, 0x4cf9, { 0x84, 0x65, 0x7f, 0xa9, 0x86, 0x36, 0x16, 0x64 }} + + ## Include/Protocol/HttpBootCallback.h + gEfiHttpBootCallbackProtocolGuid = {0xba23b311, 0x343d, 0x11e6, {0x91, 0x85, 0x58, 0x20, 0xb1, 0xd6, 0x52, 0x99}} + + ## Include/Protocol/ResetNotification.h + gEfiResetNotificationProtocolGuid = { 0x9da34ae0, 0xeaf9, 0x4bbf, { 0x8e, 0xc3, 0xfd, 0x60, 0x22, 0x6c, 0x44, 0xbe } } + + ## Include/Protocol/PartitionInfo.h + gEfiPartitionInfoProtocolGuid = { 0x8cf2f62c, 0xbc9b, 0x4821, { 0x80, 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0 }} + + ## Include/Protocol/HiiPopup.h + gEfiHiiPopupProtocolGuid = { 0x4311edc0, 0x6054, 0x46d4, { 0x9e, 0x40, 0x89, 0x3e, 0xa9, 0x52, 0xfc, 0xcc }} + + ## Include/Protocol/NvdimmLabel.h + gEfiNvdimmLabelProtocolGuid = { 0xd40b6b80, 0x97d5, 0x4282, { 0xbb, 0x1d, 0x22, 0x3a, 0x16, 0x91, 0x80, 0x58 }} + + # + # Protocols defined in UEFI2.8 + # + ## Include/Protocol/RestEx.h + gEfiRestExProtocolGuid = { 0x55648b91, 0xe7d, 0x40a3, { 0xa9, 0xb3, 0xa8, 0x15, 0xd7, 0xea, 0xdf, 0x97 }} + gEfiRestExServiceBindingProtocolGuid = { 0x456bbe01, 0x99d0, 0x45ea, { 0xbb, 0x5f, 0x16, 0xd8, 0x4b, 0xed, 0xc5, 0x59 }} + + ## Include/Protocol/RestJsonStructure.h + gEfiRestJsonStructureProtocolGuid = { 0xa9a048f6, 0x48a0, 0x4714, {0xb7, 0xda, 0xa9, 0xad,0x87, 0xd4, 0xda, 0xc9 }} + + ## Include/Protocol/RedfishDiscover.h + gEfiRedfishDiscoverProtocolGuid = { 0x5db12509, 0x4550, 0x4347, { 0x96, 0xb3, 0x73, 0xc0, 0xff, 0x6e, 0x86, 0x9f }} + + ## Include/Protocol/MemoryAttribute.h + gEfiMemoryAttributeProtocolGuid = { 0xf4560cf6, 0x40ec, 0x4b4a, { 0xa1, 0x92, 0xbf, 0x1d, 0x57, 0xd0, 0xb1, 0x89 }} + + # + # Protocols defined in Shell2.0 + # + ## Include/Protocol/Shell.h + gEfiShellProtocolGuid = { 0x6302d008, 0x7f9b, 0x4f30, {0x87, 0xac, 0x60, 0xc9, 0xfe, 0xf5, 0xda, 0x4e }} + + ## Include/Protocol/ShellParameters.h + gEfiShellParametersProtocolGuid = { 0x752f3136, 0x4e16, 0x4fdc, {0xa2, 0x2a, 0xe5, 0xf4, 0x68, 0x12, 0xf4, 0xca }} + + # + # Protocols defined in Shell2.1 + # + ## Include/Protocol/ShellDynamicCommand.h + gEfiShellDynamicCommandProtocolGuid = { 0x3c7200e9, 0x005f, 0x4ea4, {0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }} + +# +# [Error.gEfiMdePkgTokenSpaceGuid] +# 0x80000001 | Invalid value provided. +# 0x80000002 | Reserved bits must be set to zero. +# 0x80000003 | Incorrect progress code provided. +# + +[PcdsFeatureFlag] + ## Indicates if the component name protocol will be installed.

+ # TRUE - Does not install component name protocol.
+ # FALSE - Install component name protocol.
+ # @Prompt Disable Component Name Protocol. + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE|BOOLEAN|0x0000000d + + ## Indicates if the diagnostics name protocol will be installed.

+ # TRUE - Does not install diagnostics name protocol.
+ # FALSE - Install diagnostics name protocol.
+ # @Prompt Disable Diagnostics Name protocol. + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|FALSE|BOOLEAN|0x0000000e + + ## Indicates if the component name2 protocol will be installed.

+ # TRUE - Does not install component name2 protocol.
+ # FALSE - Install component name2 protocol.
+ # @Prompt Disable Component Name2 Protocol. + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|FALSE|BOOLEAN|0x00000010 + + ## Indicates if the diagnostics2 name protocol will be installed.

+ # TRUE - Does not install diagnostics2 name protocol.
+ # FALSE - Install diagnostics2 name protocol.
+ # @Prompt Disable Diagnostics2 Name Protocol. + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|FALSE|BOOLEAN|0x00000011 + + ## Indicates if EFI 1.1 ISO 639-2 language supports are obsolete

+ # TRUE - Deprecate global variable LangCodes.
+ # FALSE - Does not deprecate global variable LangCodes.
+ # @Prompt Deprecate Global Variable LangCodes. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|FALSE|BOOLEAN|0x00000012 + + ## Indicates if UGA Draw Protocol is still consumed.

+ # TRUE - Consume UGA Draw protocol.
+ # FALSE - Does not consume UGA Draw protocol.
+ # @Prompt Consume UGA Draw Protocol. + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|TRUE|BOOLEAN|0x00000027 + + ## Indicates if a check will be made to see if a specified node is a member of linked list + # in the following BaseLib functions: GetNextNode(), IsNull(), IsNodeAtEnd(), SwapListEntries().

+ # TRUE - Verify a specified node is a member of linked list.
+ # FALSE - Does not verify a specified node is a member of linked list.
+ # @Prompt Verify Node In List. + gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList|FALSE|BOOLEAN|0x00000028 + + ## If TRUE, OrderedCollectionLib is instructed to validate the + # ORDERED_COLLECTION structure at the end of such operations (typically + # structure modifications) that justify validation of the structure for unit + # testing purposes. + # @Prompt Validate ORDERED_COLLECTION structure + gEfiMdePkgTokenSpaceGuid.PcdValidateOrderedCollection|FALSE|BOOLEAN|0x0000002a + +[PcdsFixedAtBuild] + ## Status code value for indicating a watchdog timer has expired. + # EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_TIMER_EXPIRED + # @Prompt Progress Code for WatchDog Timer Expired. + # @ValidList 0x80000003 | 0x00011003 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueEfiWatchDogTimerExpired|0x00011003|UINT32|0x00000013 + + ## Status code value for indicating the invocation of SetVirtualAddressMap() + # EFI_SOFTWARE_EFI_RUNTIME_SERVICE | EFI_SW_RS_PC_SET_VIRTUAL_ADDRESS_MAP + # @Prompt Progress Code for Invocation of SetVirtualAddressMap. + # @ValidList 0x80000003 | 0x03111004 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueSetVirtualAddressMap|0x03111004|UINT32|0x00000014 + + ## Status code value for indicating the start of memory test + # EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST + # @Prompt Progress Code for Memory Test Start. + # @ValidList 0x80000003 | 0x00051006 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueMemoryTestStarted|0x00051006|UINT32|0x00000015 + + ## Status code value for indicating memory error in memory test + # EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_UNCORRECTABLE + # @Prompt Progress Code for Memory Error. + # @ValidList 0x80000003 | 0x00051003 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueUncorrectableMemoryError|0x00051003|UINT32|0x00000016 + + ## Status code value for console operation failure. + # EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_CONTROLLER_ERROR + # @Prompt Progress Code for Console Error. + # @ValidList 0x80000003 | 0x01040006 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueRemoteConsoleError|0x01040006|UINT32|0x00000017 + + ## Status code value for console reset operation failure. + # EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_PC_RESET + # @Prompt Progress Code for Console Reset. + # @ValidList 0x80000003 | 0x01040001 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueRemoteConsoleReset|0x01040001|UINT32|0x00000018 + + ## Status code value for console input operation failure. + # EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_INPUT_ERROR + # @Prompt Progress Code for Console Input Error. + # @ValidList 0x80000003 | 0x01040007 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueRemoteConsoleInputError|0x01040007|UINT32|0x00000019 + + ## Status code value for console output operation failure. + # EFI_PERIPHERAL_REMOTE_CONSOLE | EFI_P_EC_OUTPUT_ERROR + # @Prompt Progress Code for Console Output Error. + # @ValidList 0x80000003 | 0x01040008 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueRemoteConsoleOutputError|0x01040008|UINT32|0x0000001a + + ## Status code value for mouse operation failure. + # EFI_PERIPHERAL_MOUSE | EFI_P_EC_INTERFACE_ERROR + # @Prompt Progress Code for Module Device Failure. + # @ValidList 0x80000003 | 0x01020005 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueMouseInterfaceError|0x01020005|UINT32|0x30001000 + + ## Status code value for indicating mouse device has been enabled. + # EFI_PERIPHERAL_MOUSE | EFI_P_PC_ENABLE + # @Prompt Progress Code for Enable Mouse Device. + # @ValidList 0x80000003 | 0x01020004 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueMouseEnable|0x01020004|UINT32|0x30001001 + + ## Status code value for indicating mouse device has been disabled. + # EFI_PERIPHERAL_MOUSE | EFI_P_PC_DISABLE + # @Prompt Progress Code for Disable Mouse Device. + # @ValidList 0x80000003 | 0x01020002 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueMouseDisable|0x01020002|UINT32|0x30001002 + + ## Status code value for enabling keyboard device. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_PC_ENABLE + # @Prompt Progress Code for Enable Keyboard Device. + # @ValidList 0x80000003 | 0x01010004 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardEnable|0x01010004|UINT32|0x30001003 + + ## Status code value for disabling keyboard device. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_PC_DISABLE + # @Prompt Progress Code for Disable Keyboard Device. + # @ValidList 0x80000003 | 0x01010002 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardDisable|0x01010002|UINT32|0x30001004 + + ## Status code value for indicating presence of keyboard. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_PC_PRESENCE_DETECT + # @Prompt Progress Code for Detect Keyboard Device. + # @ValidList 0x80000003 | 0x01010003 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardPresenceDetect|0x01010003|UINT32|0x30001005 + + ## Status code value for keyboard operation reset operation. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_PC_RESET + # @Prompt Progress Code for Keyboard Device Reset. + # @ValidList 0x80000003 | 0x01010001 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardReset|0x01010001|UINT32|0x30001006 + + ## Status code value for keyboard clear buffer operation. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_KEYBOARD_PC_CLEAR_BUFFER + # @Prompt Progress Code for Keyboard Device Clear Buffer. + # @ValidList 0x80000003 | 0x01011000 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardClearBuffer|0x01011000|UINT32|0x30001007 + + ## Status code value for keyboard device self-test. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_KEYBOARD_PC_SELF_TEST + # @Prompt Progress Code for Keyboard Device SelfTest. + # @ValidList 0x80000003 | 0x01011001 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardSelfTest|0x01011001|UINT32|0x30001008 + + ## Status code value for indicating keyboard device failure. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_INTERFACE_ERROR + # @Prompt Progress Code for Keyboard Device Failure. + # @ValidList 0x80000003 | 0x01010005 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardInterfaceError|0x01010005|UINT32|0x30001009 + + ## Status code value for indicating keyboard input handler failure. + # EFI_PERIPHERAL_KEYBOARD | EFI_P_EC_INPUT_ERROR + # @Prompt Progress Code for Keyboard Input Failure. + # @ValidList 0x80000003 | 0x01010007 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueKeyboardInputError|0x01010007|UINT32|0x3000100a + + ## Status code value for mouse input handler failure. + # EFI_PERIPHERAL_MOUSE | EFI_P_EC_INPUT_ERROR + # @Prompt Progress Code for Mouse Input Failure. + # @ValidList 0x80000003 | 0x01020007 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueMouseInputError|0x01020007|UINT32|0x3000100b + + ## Status code value for mouse device reset operation. + # EFI_PERIPHERAL_MOUSE | EFI_P_PC_RESET + # @Prompt Progress Code for Mouse Device Reset. + # @ValidList 0x80000003 | 0x01020001 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueMouseReset|0x01020001|UINT32|0x3000100c + + ## Status code value for indicating the handoff from PEI phase to DXE phase. + # EFI_SOFTWARE_PEI_CORE | EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEXT + # @Prompt Progress Code for Handoff from Pei phase to Dxe phase. + # @ValidList 0x80000003 | 0x3021001 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValuePeiHandoffToDxe|0x3021001|UINT32|0x3000100d + + ## Status code value for indicating one PEIM is dispatched. + # EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN + # @Prompt Progress Code for Dispatching One PEIM. + # @ValidList 0x80000003 | 0x3020002 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValuePeimDispatch|0x3020002|UINT32|0x3000100e + + ## Status code value for PeiCore entry. + # EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT + # @Prompt Progress Code for PeiCore Entry. + # @ValidList 0x80000003 | 0x3020000 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValuePeiCoreEntry|0x3020000|UINT32|0x3000100f + + ## Status code value for DxeCore entry. + # EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_PC_ENTRY_POINT + # @Prompt Progress Code for DxeCore Entry. + # @ValidList 0x80000003 | 0x3041000 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueDxeCoreEntry|0x3041000|UINT32|0x30001010 + + ## Status code value for handoff from DxeCore to BDS. + # EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT + # @Prompt Progress Code for Handoff from DxeCore to BDS. + # @ValidList 0x80000003 | 0x3041001 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueDxeCoreHandoffToBds|0x3041001|UINT32|0x30001011 + + ## Status code value for indicating boot service exit. + # EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_BS_PC_EXIT_BOOT_SERVICES + # @Prompt Progress Code for Exit of Boot Service. + # @ValidList 0x80000003 | 0x3101019 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueBootServiceExit|0x3101019|UINT32|0x30001012 + + ## Status code value for indicating the beginning of DXE driver. + # EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_BEGIN + # @Prompt Progress Code for Begin of DXE Driver. + # @ValidList 0x80000003 | 0x3040002 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueDxeDriverBegin|0x3040002|UINT32|0x30001013 + + ## Status code value for indicating the end of DXE drive. + # EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_END + # @Prompt Progress Code for End of DXE Driver. + # @ValidList 0x80000003 | 0x3040003 + gEfiMdePkgTokenSpaceGuid.PcdStatusCodeValueDxeDriverEnd|0x3040003|UINT32|0x30001014 + + ## This flag is used to control build time optimization based on debug print level. + # Its default value is 0xFFFFFFFF to expose all debug print level. + # BIT0 - Initialization message.
+ # BIT1 - Warning message.
+ # BIT2 - Load Event message.
+ # BIT3 - File System message.
+ # BIT4 - Allocate or Free Pool message.
+ # BIT5 - Allocate or Free Page message.
+ # BIT6 - Information message.
+ # BIT7 - Dispatcher message.
+ # BIT8 - Variable message.
+ # BIT10 - Boot Manager message.
+ # BIT12 - BlockIo Driver message.
+ # BIT14 - Network Driver message.
+ # BIT16 - UNDI Driver message.
+ # BIT17 - LoadFile message.
+ # BIT19 - Event message.
+ # BIT20 - Global Coherency Database changes message.
+ # BIT21 - Memory range cachability changes message.
+ # BIT22 - Detailed debug message.
+ # BIT23 - Manageability debug message.
+ # BIT31 - Error message.
+ # @Prompt Fixed Debug Message Print Level. + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0xFFFFFFFF|UINT32|0x30001016 + + ## Indicates the control flow enforcement enabling state. + # If enabled, it uses control flow enforcement technology to prevent ROP or JOP.

+ # BIT0 - SMM CET Shadow Stack is enabled.
+ # Other - reserved + # @Prompt Enable control flow enforcement. + gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask|0x0|UINT32|0x30001017 + + ## Indicates the type of instruction sequence to use for a speculation + # barrier. The default instruction sequence is LFENCE.

+ # 0x00 - No operation.
+ # 0x01 - LFENCE (IA32/X64).
+ # 0x02 - CPUID (IA32/X64).
+ # Other - reserved + # @Prompt Speculation Barrier Type. + gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0x01|UINT8|0x30001018 + + ## SPI NOR Flash operation retry counts + # 0x00000000: No retry + # 0xFFFFFFFF: Maximum retry value + # + # @Prompt SPI NOR Flash Operation Retry Value + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationRetryCount|0x00000003|UINT32|0x30001019 + + ## SPI NOR Flash operation retry counts for the fixed timeout value + # 0x00000000: No retry + # 0xFFFFFFFF: Maximum retry value + # + # @Prompt SPI NOR Flash Operation Retry Value for the Fixed Timeout Value + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashFixedTimeoutRetryCount|0x0000FFFF|UINT32|0x3000101A + + ## SPI NOR Flash operation delay in microseconds + # Deafult is set to 0x00000010 microseconds + # + # @Prompt SPI NOR Flash Operation Delay in Microseconds (16 us) + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds|0x00000010|UINT32|0x3000101B + +[PcdsFixedAtBuild,PcdsPatchableInModule] + ## Indicates the maximum length of unicode string used in the following + # BaseLib functions: StrLen(), StrSize(), StrCmp(), StrnCmp(), StrCpy(), StrnCpy()

+ # 0 - No length check for unicode string.
+ # >0 - Maximum length of unicode string.
+ # @Prompt Maximum Length of Unicode String. + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000|UINT32|0x00000001 + + ## Indicates the maximum length of ascii string used in the following + # BaseLib functions: AsciiStrLen(), AsciiStrSize(), AsciiStrCmp(), AsciiStrnCmp(), + # AsciiStrCpy(), AsciiStrnCpy().

+ # 0 - No length check for ascii string.
+ # >0 - Maximum length of ascii string.
+ # @Prompt Maximum Length of Ascii String. + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000|UINT32|0x00000002 + + ## Indicates the maximum node number of linked list.

+ # 0 - No node number check for linked list.
+ # >0 - Maximum node number of linked list.
+ # @Prompt Maximum Length of Linked List. + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000|UINT32|0x00000003 + + ## Indicates the maximum node number of device path.

+ # 0 - No node number check for device path.
+ # >0 - Maximum node number of device path.
+ # @Prompt Maximum node number of device path. + gEfiMdePkgTokenSpaceGuid.PcdMaximumDevicePathNodeCount|0|UINT32|0x00000029 + + ## Indicates the timeout tick of holding spin lock.

+ # 0 - No timeout.
+ # >0 - Timeout tick of holding spin lock.
+ # @Prompt Spin Lock Timeout (us). + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000|UINT32|0x00000004 + + ## The mask is used to control DebugLib behavior.

+ # BIT0 - Enable Debug Assert.
+ # BIT1 - Enable Debug Print.
+ # BIT2 - Enable Debug Code.
+ # BIT3 - Enable Clear Memory.
+ # BIT4 - Enable BreakPoint as ASSERT.
+ # BIT5 - Enable DeadLoop as ASSERT.
+ # @Prompt Debug Property. + # @Expression 0x80000002 | (gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask & 0xC0) == 0 + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0|UINT8|0x00000005 + + ## This flag is used to control the print out Debug message.

+ # BIT0 - Initialization message.
+ # BIT1 - Warning message.
+ # BIT2 - Load Event message.
+ # BIT3 - File System message.
+ # BIT4 - Allocate or Free Pool message.
+ # BIT5 - Allocate or Free Page message.
+ # BIT6 - Information message.
+ # BIT7 - Dispatcher message.
+ # BIT8 - Variable message.
+ # BIT10 - Boot Manager message.
+ # BIT12 - BlockIo Driver message.
+ # BIT14 - Network Driver message.
+ # BIT16 - UNDI Driver message.
+ # BIT17 - LoadFile message.
+ # BIT19 - Event message.
+ # BIT20 - Global Coherency Database changes message.
+ # BIT21 - Memory range cachability changes message.
+ # BIT22 - Detailed debug message.
+ # BIT23 - Manageability messages.
+ # BIT31 - Error message.
+ # @Prompt Debug Message Print Level. + # @Expression 0x80000002 | (gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel & 0x7F84AA00) == 0 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000|UINT32|0x00000006 + + ## The mask is used to control ReportStatusCodeLib behavior.

+ # BIT0 - Enable Progress Code.
+ # BIT1 - Enable Error Code.
+ # BIT2 - Enable Debug Code.
+ # @Prompt Report Status Code Property. + # @Expression 0x80000002 | (gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask & 0xF8) == 0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0|UINT8|0x00000007 + + ## This value is used to fill a segment of memory when PcdDebugPropertyMask Clear Memory is enabled. + # @Prompt Value to Clear Memory. + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF|UINT8|0x00000008 + + ## The mask is used to control PerformanceLib behavior.

+ # BIT0 - Enable Performance Measurement.
+ # BIT1 - Disable Start Image Logging.
+ # BIT2 - Disable Load Image logging.
+ # BIT3 - Disable Binding Support logging.
+ # BIT4 - Disable Binding Start logging.
+ # BIT5 - Disable Binding Stop logging.
+ # BIT6 - Disable all other general Perfs.
+ # BIT1-BIT6 are evaluated when BIT0 is set.
+ # @Prompt Performance Measurement Property. + # @Expression 0x80000002 | (gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask & 0x80) == 0 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0|UINT8|0x00000009 + + ## The mask is used to control PostCodeLib behavior.

+ # BIT0 - Enable Post Code.
+ # BIT1 - Enable Post Code with Description.
+ # @Prompt Post Code Property. + # @Expression 0x80000002 | (gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask & 0xFC) == 0 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0|UINT8|0x0000000b + + ## The bit width of data to be written to Port80. The default value is 8. + # @Prompt Port80 Data Width + # @ValidList 0x80000001 | 8, 16, 32 + gEfiMdePkgTokenSpaceGuid.PcdPort80DataWidth|8|UINT8|0x0000002d + + ## The maximum printable number of characters. UefLib functions: AsciiPrint(), AsciiErrorPrint(), + # PrintXY(), AsciiPrintXY(), Print(), ErrorPrint() base on this PCD value to print characters. + # @Prompt Maximum Printable Number of Characters. + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320|UINT32|0x101 + + ## This is the print buffer length for FileHandleLib. + # FileHandlePrintLine() sizes buffers based on this PCD value for printing. + # @Prompt Number of Printable Characters. + gEfiMdePkgTokenSpaceGuid.PcdUefiFileHandleLibPrintBufferSize|1536|UINT16|0x201 + + ## Indicates the allowable maximum number in extract handler table. + # @Prompt Maximum Number of GuidedExtractHandler. + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10|UINT32|0x00000025 + + ## Indicates the default timeouts for USB transfers in milliseconds. + # @Prompt USB Transfer Timeout (ms). + gEfiMdePkgTokenSpaceGuid.PcdUsbTransferTimeoutValue|3000|UINT32|0x00000026 + + ## This value is used to set the available memory address to store Guided Extract Handlers. + # The required memory space is decided by the value of PcdMaximumGuidedExtractHandler. + # @Prompt Memory Address of GuidedExtractHandler Table. + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x1000000|UINT64|0x30001015 + + ## This value is the IPMI KCS Interface I/O base address used to transmit IPMI commands. + # The value of 0xca2 is the default I/O base address defined in IPMI specification. + # @Prompt IPMI KCS Interface I/O Base Address + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x00000031 + + ## This is SMBus slave address for the SSIF to the BMC. + # The recommended value defined by IPMI specification is 0x20 (section 12.12). + # @Prompt IPMI SSIF SMBus slave address + gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifSmbusSlaveAddr|0x20|UINT8|0x00000032 + + ## This is the maximum number of IPMI SSIF request retries. + # The IPMI specification specified min value is 5 (section 12.17). + # @Prompt Number of IPMI SSIF request retries. + gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifRequestRetryCount|0x05|UINT8|0x00000033 + + ## This is the required interval for each IPMI request retry. + # The IPMI specification specified a time range of 60ms to 250ms (section 12.17). + # The default setting is min. + # @Prompt Time between IPMI SSIF request retries. + gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifRequestRetryIntervalMicrosecond|60000|UINT32|0x00000034 + + ## This value is the maximum retries of an IPMI SSIF response + # The default value is the same as the Linux Kernel ipmi_ssif driver. + # @Prompt Number of IPMI SSIF response retries. + gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifResponseRetryCount|250|UINT8|0x00000035 + + ## This is the required interval for each IPMI response retry. + # The IPMI specification specified min value is 60ms (section 12.17). + # @Prompt Time-out for a response, internal + gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifResponseRetryIntervalMicrosecond|60000|UINT32|0x00000036 + + ## Indicates IPMI Interface Type + # The IPMI specification defines the following interface types: (section C1-1.1) + # 0 - Unknown + # 1 - KCS : Keyboard Controller Style + # 2 - SMIC : Server Management Interface Chip + # 3 - BT : Block Transfer + # 4 - SSIF : SMBus System Interface + gEfiMdePkgTokenSpaceGuid.PcdIpmiInterfaceType|0|UINT8|0x00000038 + +[PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64] + ## GUID identifying the Rng algorithm implemented by CPU instruction. + # @Prompt CPU Rng algorithm's GUID. + gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037 + +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] + # + # Configurability to override RISC-V CPU Features + # BIT 0 = Cache Management Operations. This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. + # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. + # + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## This value is used to set the base address of PCI express hierarchy. + # @Prompt PCI Express Base Address. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a + + ## This value is used to set the base address of PCI MMIO window that provides I/O access. + # @Prompt PCI I/O Memory Map Window Base Address. + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000040 + + ## This value is used for the 32-bit PCI memory map I/O base address translation. + # @Prompt 32-bit PCI Memory Map I/O Base Address translation. + gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000041 + + ## This value is used for the 64-bit PCI memory map I/O base address translation. + # @Prompt 64-bit PCI Memory Map I/O Base Address translation. + gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000042 + + ## This value is used to set the size of PCI express hierarchy. The default is 256 MB. + # @Prompt PCI Express Base Size. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000|UINT64|0x0000000f + + ## Default current ISO 639-2 language: English & French. + # @Prompt Default Value of LangCodes Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001c + + ## Default current ISO 639-2 language: English. + # @Prompt Default Value of Lang Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLang|"eng"|VOID*|0x0000001d + + ## Default platform supported RFC 4646 languages: (American) English & French. + # @Prompt Default Value of PlatformLangCodes Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en;fr;en-US;fr-FR"|VOID*|0x0000001e + + ## Default current RFC 4646 language: (American) English. + # @Prompt Default Value of PlatformLang Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US"|VOID*|0x0000001f + + ## Indicates the default baud rate of UART. + # @Prompt Default UART Baud Rate. + # @ValidList 0x80000001 | 115200, 57600, 38400, 19200, 9600, 7200, 4800, 3600, 2400, 2000, 1800, 1200, 600, 300, 150, 134, 110, 75, 50 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200|UINT64|0x00000020 + + ## Indicates the number of efficient data bit in UART transaction. + # @Prompt Default UART Data Bit. + # @ValidRange 0x80000001 | 5 - 8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8|UINT8|0x00000021 + + ## Indicates the setting of data parity in UART transaction.

+ # 0 - Default Parity.
+ # 1 - No Parity.
+ # 2 - Even Parity.
+ # 3 - Odd Parity.
+ # 4 - Mark Parity.
+ # 5 - Space Parity.
+ # @Prompt Default UART Parity. + # @ValidRange 0x80000001 | 0 - 5 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1|UINT8|0x00000022 + + ## Indicates the setting of stop bit in UART transaction.

+ # 0 - Default Stop Bits.
+ # 1 - One Stop Bit.
+ # 2 - One Five Stop Bits.
+ # 3 - Two Stop Bits.
+ # @Prompt Default UART Stop Bits. + # @ValidRange 0x80000001 | 0 - 3 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1|UINT8|0x00000023 + + ## Indicates the usable type of terminal.

+ # 0 - PCANSI
+ # 1 - VT100
+ # 2 - VT100+
+ # 3 - UTF8
+ # 4 - TTYTERM, NOT defined in UEFI SPEC
+ # @Prompt Default Terminal Type. + # @ValidRange 0x80000001 | 0 - 4 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0|UINT8|0x00000024 + + ## Indicates the receive FIFO depth of UART controller.

+ # @Prompt Default UART Receive FIFO Depth. + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|1|UINT16|0x00000030 + + ## Error level for hardware recorder. + # If value 0, platform does not support feature of hardware error record. + # @Prompt Error Level For Hardware Recorder + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|0|UINT16|0x0000002b + + ## The number of seconds that the firmware will wait before initiating the original default boot selection. + # A value of 0 indicates that the default boot selection is to be initiated immediately on boot. + # The value of 0xFFFF then firmware will wait for user input before booting. + # @Prompt Boot Timeout (s) + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000002c + + ## This value is used to configure X86 Processor FSB clock. + # @Prompt FSB Clock. + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|200000000|UINT32|0x0000000c + + ## This dynamic PCD indicates the memory encryption attribute of the guest. + # @Prompt Memory encryption attribute + gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0|UINT64|0x0000002e + +[UserExtensions.TianoCore."ExtraFiles"] + MdePkgExtra.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c b/Platform/AMD/TurinBoard/Override/edk2/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c new file mode 100644 index 0000000000000000000000000000000000000000..41b25ab749d06eb65978c31768c49dd5e6e9bdc5 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c @@ -0,0 +1,2917 @@ +/** @file + This module implements Tcg2 Protocol. + +Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define PERF_ID_TCG2_DXE 0x3120 + +typedef struct { + CHAR16 *VariableName; + EFI_GUID *VendorGuid; +} VARIABLE_TYPE; + +#define TCG2_DEFAULT_MAX_COMMAND_SIZE 0x1000 +#define TCG2_DEFAULT_MAX_RESPONSE_SIZE 0x1000 + +typedef struct { + EFI_GUID *EventGuid; + EFI_TCG2_EVENT_LOG_FORMAT LogFormat; +} TCG2_EVENT_INFO_STRUCT; + +TCG2_EVENT_INFO_STRUCT mTcg2EventInfo[] = { + { &gTcgEventEntryHobGuid, EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 }, + { &gTcgEvent2EntryHobGuid, EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 }, +}; + +#define TCG_EVENT_LOG_AREA_COUNT_MAX 2 + +typedef struct { + EFI_TCG2_EVENT_LOG_FORMAT EventLogFormat; + EFI_PHYSICAL_ADDRESS Lasa; + UINT64 Laml; + UINTN EventLogSize; + UINT8 *LastEvent; + BOOLEAN EventLogStarted; + BOOLEAN EventLogTruncated; + UINTN Next800155EventOffset; +} TCG_EVENT_LOG_AREA_STRUCT; + +typedef struct _TCG_DXE_DATA { + EFI_TCG2_BOOT_SERVICE_CAPABILITY BsCap; + TCG_EVENT_LOG_AREA_STRUCT EventLogAreaStruct[TCG_EVENT_LOG_AREA_COUNT_MAX]; + BOOLEAN GetEventLogCalled[TCG_EVENT_LOG_AREA_COUNT_MAX]; + TCG_EVENT_LOG_AREA_STRUCT FinalEventLogAreaStruct[TCG_EVENT_LOG_AREA_COUNT_MAX]; + EFI_TCG2_FINAL_EVENTS_TABLE *FinalEventsTable[TCG_EVENT_LOG_AREA_COUNT_MAX]; +} TCG_DXE_DATA; + +TCG_DXE_DATA mTcgDxeData = { + { + sizeof (EFI_TCG2_BOOT_SERVICE_CAPABILITY), // Size + { 1, 1 }, // StructureVersion + { 1, 1 }, // ProtocolVersion + EFI_TCG2_BOOT_HASH_ALG_SHA1, // HashAlgorithmBitmap + EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2, // SupportedEventLogs + TRUE, // TPMPresentFlag + TCG2_DEFAULT_MAX_COMMAND_SIZE, // MaxCommandSize + TCG2_DEFAULT_MAX_RESPONSE_SIZE, // MaxResponseSize + 0, // ManufacturerID + 0, // NumberOfPCRBanks + 0, // ActivePcrBanks + }, +}; + +UINTN mBootAttempts = 0; +CHAR16 mBootVarName[] = L"BootOrder"; + +VARIABLE_TYPE mVariableType[] = { + { EFI_SECURE_BOOT_MODE_NAME, &gEfiGlobalVariableGuid }, + { EFI_PLATFORM_KEY_NAME, &gEfiGlobalVariableGuid }, + { EFI_KEY_EXCHANGE_KEY_NAME, &gEfiGlobalVariableGuid }, + { EFI_IMAGE_SECURITY_DATABASE, &gEfiImageSecurityDatabaseGuid }, + { EFI_IMAGE_SECURITY_DATABASE1, &gEfiImageSecurityDatabaseGuid }, +}; + +EFI_HANDLE mImageHandle; + +/** + Measure PE image into TPM log based on the authenticode image hashing in + PE/COFF Specification 8.0 Appendix A. + + Caution: This function may receive untrusted input. + PE/COFF image is external input, so this function will validate its data structure + within this image buffer before use. + + Notes: PE/COFF image is checked by BasePeCoffLib PeCoffLoaderGetImageInfo(). + + @param[in] PCRIndex TPM PCR index + @param[in] ImageAddress Start address of image buffer. + @param[in] ImageSize Image size + @param[out] DigestList Digest list of this image. + + @retval EFI_SUCCESS Successfully measure image. + @retval EFI_OUT_OF_RESOURCES No enough resource to measure image. + @retval other error value +**/ +EFI_STATUS +MeasurePeImageAndExtend ( + IN UINT32 PCRIndex, + IN EFI_PHYSICAL_ADDRESS ImageAddress, + IN UINTN ImageSize, + OUT TPML_DIGEST_VALUES *DigestList + ); + +/** + + This function dump raw data. + + @param Data raw data + @param Size raw data size + +**/ +VOID +InternalDumpData ( + IN UINT8 *Data, + IN UINTN Size + ) +{ + UINTN Index; + + for (Index = 0; Index < Size; Index++) { + DEBUG ((DEBUG_INFO, "%02x", (UINTN)Data[Index])); + } +} + +/** + + This function initialize TCG_PCR_EVENT2_HDR for EV_NO_ACTION Event Type other than EFI Specification ID event + The behavior is defined by TCG PC Client PFP Spec. Section 9.3.4 EV_NO_ACTION Event Types + + @param[in, out] NoActionEvent Event Header of EV_NO_ACTION Event + @param[in] EventSize Event Size of the EV_NO_ACTION Event + +**/ +VOID +InitNoActionEvent ( + IN OUT TCG_PCR_EVENT2_HDR *NoActionEvent, + IN UINT32 EventSize + ) +{ + UINT32 DigestListCount; + TPMI_ALG_HASH HashAlgId; + UINT8 *DigestBuffer; + + DigestBuffer = (UINT8 *)NoActionEvent->Digests.digests; + DigestListCount = 0; + + NoActionEvent->PCRIndex = 0; + NoActionEvent->EventType = EV_NO_ACTION; + + // + // Set Hash count & hashAlg accordingly, while Digest.digests[n].digest to all 0 + // + ZeroMem (&NoActionEvent->Digests, sizeof (NoActionEvent->Digests)); + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA1) != 0) { + HashAlgId = TPM_ALG_SHA1; + CopyMem (DigestBuffer, &HashAlgId, sizeof (TPMI_ALG_HASH)); + DigestBuffer += sizeof (TPMI_ALG_HASH) + GetHashSizeFromAlgo (HashAlgId); + DigestListCount++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA256) != 0) { + HashAlgId = TPM_ALG_SHA256; + CopyMem (DigestBuffer, &HashAlgId, sizeof (TPMI_ALG_HASH)); + DigestBuffer += sizeof (TPMI_ALG_HASH) + GetHashSizeFromAlgo (HashAlgId); + DigestListCount++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA384) != 0) { + HashAlgId = TPM_ALG_SHA384; + CopyMem (DigestBuffer, &HashAlgId, sizeof (TPMI_ALG_HASH)); + DigestBuffer += sizeof (TPMI_ALG_HASH) + GetHashSizeFromAlgo (HashAlgId); + DigestListCount++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA512) != 0) { + HashAlgId = TPM_ALG_SHA512; + CopyMem (DigestBuffer, &HashAlgId, sizeof (TPMI_ALG_HASH)); + DigestBuffer += sizeof (TPMI_ALG_HASH) + GetHashSizeFromAlgo (HashAlgId); + DigestListCount++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SM3_256) != 0) { + HashAlgId = TPM_ALG_SM3_256; + CopyMem (DigestBuffer, &HashAlgId, sizeof (TPMI_ALG_HASH)); + DigestBuffer += sizeof (TPMI_ALG_HASH) + GetHashSizeFromAlgo (HashAlgId); + DigestListCount++; + } + + // + // Set Digests Count + // + WriteUnaligned32 ((UINT32 *)&NoActionEvent->Digests.count, DigestListCount); + + // + // Set Event Size + // + WriteUnaligned32 ((UINT32 *)DigestBuffer, EventSize); +} + +/** + + This function dump raw data with colume format. + + @param Data raw data + @param Size raw data size + +**/ +VOID +InternalDumpHex ( + IN UINT8 *Data, + IN UINTN Size + ) +{ + UINTN Index; + UINTN Count; + UINTN Left; + + #define COLUME_SIZE (16 * 2) + + Count = Size / COLUME_SIZE; + Left = Size % COLUME_SIZE; + for (Index = 0; Index < Count; Index++) { + DEBUG ((DEBUG_INFO, "%04x: ", Index * COLUME_SIZE)); + InternalDumpData (Data + Index * COLUME_SIZE, COLUME_SIZE); + DEBUG ((DEBUG_INFO, "\n")); + } + + if (Left != 0) { + DEBUG ((DEBUG_INFO, "%04x: ", Index * COLUME_SIZE)); + InternalDumpData (Data + Index * COLUME_SIZE, Left); + DEBUG ((DEBUG_INFO, "\n")); + } +} + +/** + Get All processors EFI_CPU_LOCATION in system. LocationBuf is allocated inside the function + Caller is responsible to free LocationBuf. + + @param[out] LocationBuf Returns Processor Location Buffer. + @param[out] Num Returns processor number. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_UNSUPPORTED MpService protocol not found. + +**/ +EFI_STATUS +GetProcessorsCpuLocation ( + OUT EFI_CPU_PHYSICAL_LOCATION **LocationBuf, + OUT UINTN *Num + ) +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpProtocol; + UINTN ProcessorNum; + UINTN EnabledProcessorNum; + EFI_PROCESSOR_INFORMATION ProcessorInfo; + EFI_CPU_PHYSICAL_LOCATION *ProcessorLocBuf; + UINTN Index; + + Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpProtocol); + if (EFI_ERROR (Status)) { + // + // MP protocol is not installed + // + return EFI_UNSUPPORTED; + } + + Status = MpProtocol->GetNumberOfProcessors ( + MpProtocol, + &ProcessorNum, + &EnabledProcessorNum + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gBS->AllocatePool ( + EfiBootServicesData, + sizeof (EFI_CPU_PHYSICAL_LOCATION) * ProcessorNum, + (VOID **)&ProcessorLocBuf + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Get each processor Location info + // + for (Index = 0; Index < ProcessorNum; Index++) { + Status = MpProtocol->GetProcessorInfo ( + MpProtocol, + Index, + &ProcessorInfo + ); + if (EFI_ERROR (Status)) { + FreePool (ProcessorLocBuf); + return Status; + } + + // + // Get all Processor Location info & measure + // + CopyMem ( + &ProcessorLocBuf[Index], + &ProcessorInfo.Location, + sizeof (EFI_CPU_PHYSICAL_LOCATION) + ); + } + + *LocationBuf = ProcessorLocBuf; + *Num = ProcessorNum; + + return Status; +} + +/** + The EFI_TCG2_PROTOCOL GetCapability function call provides protocol + capability information and state information. + + @param[in] This Indicates the calling context + @param[in, out] ProtocolCapability The caller allocates memory for a EFI_TCG2_BOOT_SERVICE_CAPABILITY + structure and sets the size field to the size of the structure allocated. + The callee fills in the fields with the EFI protocol capability information + and the current EFI TCG2 state information up to the number of fields which + fit within the size of the structure passed in. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + The ProtocolCapability variable will not be populated. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + The ProtocolCapability variable will not be populated. + @retval EFI_BUFFER_TOO_SMALL The ProtocolCapability variable is too small to hold the full response. + It will be partially populated (required Size field will be set). +**/ +EFI_STATUS +EFIAPI +Tcg2GetCapability ( + IN EFI_TCG2_PROTOCOL *This, + IN OUT EFI_TCG2_BOOT_SERVICE_CAPABILITY *ProtocolCapability + ) +{ + DEBUG ((DEBUG_VERBOSE, "Tcg2GetCapability ...\n")); + + if ((This == NULL) || (ProtocolCapability == NULL)) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_VERBOSE, "Size - 0x%x\n", ProtocolCapability->Size)); + DEBUG ((DEBUG_VERBOSE, " 1.1 - 0x%x, 1.0 - 0x%x\n", sizeof (EFI_TCG2_BOOT_SERVICE_CAPABILITY), sizeof (TREE_BOOT_SERVICE_CAPABILITY_1_0))); + + if (ProtocolCapability->Size < mTcgDxeData.BsCap.Size) { + // + // Handle the case that firmware support 1.1 but OS only support 1.0. + // + if ((mTcgDxeData.BsCap.ProtocolVersion.Major > 0x01) || + ((mTcgDxeData.BsCap.ProtocolVersion.Major == 0x01) && ((mTcgDxeData.BsCap.ProtocolVersion.Minor > 0x00)))) + { + if (ProtocolCapability->Size >= sizeof (TREE_BOOT_SERVICE_CAPABILITY_1_0)) { + CopyMem (ProtocolCapability, &mTcgDxeData.BsCap, sizeof (TREE_BOOT_SERVICE_CAPABILITY_1_0)); + ProtocolCapability->Size = sizeof (TREE_BOOT_SERVICE_CAPABILITY_1_0); + ProtocolCapability->StructureVersion.Major = 1; + ProtocolCapability->StructureVersion.Minor = 0; + ProtocolCapability->ProtocolVersion.Major = 1; + ProtocolCapability->ProtocolVersion.Minor = 0; + DEBUG ((DEBUG_ERROR, "TreeGetCapability (Compatible) - %r\n", EFI_SUCCESS)); + return EFI_SUCCESS; + } + } + + ProtocolCapability->Size = mTcgDxeData.BsCap.Size; + return EFI_BUFFER_TOO_SMALL; + } + + CopyMem (ProtocolCapability, &mTcgDxeData.BsCap, mTcgDxeData.BsCap.Size); + DEBUG ((DEBUG_VERBOSE, "Tcg2GetCapability - %r\n", EFI_SUCCESS)); + return EFI_SUCCESS; +} + +/** + This function dump PCR event. + + @param[in] EventHdr TCG PCR event structure. +**/ +VOID +DumpEvent ( + IN TCG_PCR_EVENT_HDR *EventHdr + ) +{ + UINTN Index; + + DEBUG ((DEBUG_INFO, " Event:\n")); + DEBUG ((DEBUG_INFO, " PCRIndex - %d\n", EventHdr->PCRIndex)); + DEBUG ((DEBUG_INFO, " EventType - 0x%08x\n", EventHdr->EventType)); + DEBUG ((DEBUG_INFO, " Digest - ")); + for (Index = 0; Index < sizeof (TCG_DIGEST); Index++) { + DEBUG ((DEBUG_INFO, "%02x ", EventHdr->Digest.digest[Index])); + } + + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, " EventSize - 0x%08x\n", EventHdr->EventSize)); + InternalDumpHex ((UINT8 *)(EventHdr + 1), EventHdr->EventSize); +} + +/** + This function dump TCG_EfiSpecIDEventStruct. + + @param[in] TcgEfiSpecIdEventStruct A pointer to TCG_EfiSpecIDEventStruct. +**/ +VOID +DumpTcgEfiSpecIdEventStruct ( + IN TCG_EfiSpecIDEventStruct *TcgEfiSpecIdEventStruct + ) +{ + TCG_EfiSpecIdEventAlgorithmSize *DigestSize; + UINTN Index; + UINT8 *VendorInfoSize; + UINT8 *VendorInfo; + UINT32 NumberOfAlgorithms; + + DEBUG ((DEBUG_INFO, " TCG_EfiSpecIDEventStruct:\n")); + DEBUG ((DEBUG_INFO, " signature - '")); + for (Index = 0; Index < sizeof (TcgEfiSpecIdEventStruct->signature); Index++) { + DEBUG ((DEBUG_INFO, "%c", TcgEfiSpecIdEventStruct->signature[Index])); + } + + DEBUG ((DEBUG_INFO, "'\n")); + DEBUG ((DEBUG_INFO, " platformClass - 0x%08x\n", TcgEfiSpecIdEventStruct->platformClass)); + DEBUG ((DEBUG_INFO, " specVersion - %d.%d%d\n", TcgEfiSpecIdEventStruct->specVersionMajor, TcgEfiSpecIdEventStruct->specVersionMinor, TcgEfiSpecIdEventStruct->specErrata)); + DEBUG ((DEBUG_INFO, " uintnSize - 0x%02x\n", TcgEfiSpecIdEventStruct->uintnSize)); + + CopyMem (&NumberOfAlgorithms, TcgEfiSpecIdEventStruct + 1, sizeof (NumberOfAlgorithms)); + DEBUG ((DEBUG_INFO, " NumberOfAlgorithms - 0x%08x\n", NumberOfAlgorithms)); + + DigestSize = (TCG_EfiSpecIdEventAlgorithmSize *)((UINT8 *)TcgEfiSpecIdEventStruct + sizeof (*TcgEfiSpecIdEventStruct) + sizeof (NumberOfAlgorithms)); + for (Index = 0; Index < NumberOfAlgorithms; Index++) { + DEBUG ((DEBUG_INFO, " digest(%d)\n", Index)); + DEBUG ((DEBUG_INFO, " algorithmId - 0x%04x\n", DigestSize[Index].algorithmId)); + DEBUG ((DEBUG_INFO, " digestSize - 0x%04x\n", DigestSize[Index].digestSize)); + } + + VendorInfoSize = (UINT8 *)&DigestSize[NumberOfAlgorithms]; + DEBUG ((DEBUG_INFO, " VendorInfoSize - 0x%02x\n", *VendorInfoSize)); + VendorInfo = VendorInfoSize + 1; + DEBUG ((DEBUG_INFO, " VendorInfo - ")); + for (Index = 0; Index < *VendorInfoSize; Index++) { + DEBUG ((DEBUG_INFO, "%02x ", VendorInfo[Index])); + } + + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + This function get size of TCG_EfiSpecIDEventStruct. + + @param[in] TcgEfiSpecIdEventStruct A pointer to TCG_EfiSpecIDEventStruct. +**/ +UINTN +GetTcgEfiSpecIdEventStructSize ( + IN TCG_EfiSpecIDEventStruct *TcgEfiSpecIdEventStruct + ) +{ + TCG_EfiSpecIdEventAlgorithmSize *DigestSize; + UINT8 *VendorInfoSize; + UINT32 NumberOfAlgorithms; + + CopyMem (&NumberOfAlgorithms, TcgEfiSpecIdEventStruct + 1, sizeof (NumberOfAlgorithms)); + + DigestSize = (TCG_EfiSpecIdEventAlgorithmSize *)((UINT8 *)TcgEfiSpecIdEventStruct + sizeof (*TcgEfiSpecIdEventStruct) + sizeof (NumberOfAlgorithms)); + VendorInfoSize = (UINT8 *)&DigestSize[NumberOfAlgorithms]; + return sizeof (TCG_EfiSpecIDEventStruct) + sizeof (UINT32) + (NumberOfAlgorithms * sizeof (TCG_EfiSpecIdEventAlgorithmSize)) + sizeof (UINT8) + (*VendorInfoSize); +} + +/** + This function dump PCR event 2. + + @param[in] TcgPcrEvent2 TCG PCR event 2 structure. +**/ +VOID +DumpEvent2 ( + IN TCG_PCR_EVENT2 *TcgPcrEvent2 + ) +{ + UINTN Index; + UINT32 DigestIndex; + UINT32 DigestCount; + TPMI_ALG_HASH HashAlgo; + UINT32 DigestSize; + UINT8 *DigestBuffer; + UINT32 EventSize; + UINT8 *EventBuffer; + + DEBUG ((DEBUG_INFO, " Event:\n")); + DEBUG ((DEBUG_INFO, " PCRIndex - %d\n", TcgPcrEvent2->PCRIndex)); + DEBUG ((DEBUG_INFO, " EventType - 0x%08x\n", TcgPcrEvent2->EventType)); + + DEBUG ((DEBUG_INFO, " DigestCount: 0x%08x\n", TcgPcrEvent2->Digest.count)); + + DigestCount = TcgPcrEvent2->Digest.count; + HashAlgo = TcgPcrEvent2->Digest.digests[0].hashAlg; + DigestBuffer = (UINT8 *)&TcgPcrEvent2->Digest.digests[0].digest; + for (DigestIndex = 0; DigestIndex < DigestCount; DigestIndex++) { + DEBUG ((DEBUG_INFO, " HashAlgo : 0x%04x\n", HashAlgo)); + DEBUG ((DEBUG_INFO, " Digest(%d): ", DigestIndex)); + DigestSize = GetHashSizeFromAlgo (HashAlgo); + for (Index = 0; Index < DigestSize; Index++) { + DEBUG ((DEBUG_INFO, "%02x ", DigestBuffer[Index])); + } + + DEBUG ((DEBUG_INFO, "\n")); + // + // Prepare next + // + CopyMem (&HashAlgo, DigestBuffer + DigestSize, sizeof (TPMI_ALG_HASH)); + DigestBuffer = DigestBuffer + DigestSize + sizeof (TPMI_ALG_HASH); + } + + DEBUG ((DEBUG_INFO, "\n")); + DigestBuffer = DigestBuffer - sizeof (TPMI_ALG_HASH); + + CopyMem (&EventSize, DigestBuffer, sizeof (TcgPcrEvent2->EventSize)); + DEBUG ((DEBUG_INFO, " EventSize - 0x%08x\n", EventSize)); + EventBuffer = DigestBuffer + sizeof (TcgPcrEvent2->EventSize); + InternalDumpHex (EventBuffer, EventSize); +} + +/** + This function returns size of TCG PCR event 2. + + @param[in] TcgPcrEvent2 TCG PCR event 2 structure. + + @return size of TCG PCR event 2. +**/ +UINTN +GetPcrEvent2Size ( + IN TCG_PCR_EVENT2 *TcgPcrEvent2 + ) +{ + UINT32 DigestIndex; + UINT32 DigestCount; + TPMI_ALG_HASH HashAlgo; + UINT32 DigestSize; + UINT8 *DigestBuffer; + UINT32 EventSize; + UINT8 *EventBuffer; + + DigestCount = TcgPcrEvent2->Digest.count; + HashAlgo = TcgPcrEvent2->Digest.digests[0].hashAlg; + DigestBuffer = (UINT8 *)&TcgPcrEvent2->Digest.digests[0].digest; + for (DigestIndex = 0; DigestIndex < DigestCount; DigestIndex++) { + DigestSize = GetHashSizeFromAlgo (HashAlgo); + // + // Prepare next + // + CopyMem (&HashAlgo, DigestBuffer + DigestSize, sizeof (TPMI_ALG_HASH)); + DigestBuffer = DigestBuffer + DigestSize + sizeof (TPMI_ALG_HASH); + } + + DigestBuffer = DigestBuffer - sizeof (TPMI_ALG_HASH); + + CopyMem (&EventSize, DigestBuffer, sizeof (TcgPcrEvent2->EventSize)); + EventBuffer = DigestBuffer + sizeof (TcgPcrEvent2->EventSize); + + return (UINTN)EventBuffer + EventSize - (UINTN)TcgPcrEvent2; +} + +/** + This function dump event log. + + @param[in] EventLogFormat The type of the event log for which the information is requested. + @param[in] EventLogLocation A pointer to the memory address of the event log. + @param[in] EventLogLastEntry If the Event Log contains more than one entry, this is a pointer to the + address of the start of the last entry in the event log in memory. + @param[in] FinalEventsTable A pointer to the memory address of the final event table. +**/ +VOID +DumpEventLog ( + IN EFI_TCG2_EVENT_LOG_FORMAT EventLogFormat, + IN EFI_PHYSICAL_ADDRESS EventLogLocation, + IN EFI_PHYSICAL_ADDRESS EventLogLastEntry, + IN EFI_TCG2_FINAL_EVENTS_TABLE *FinalEventsTable + ) +{ + TCG_PCR_EVENT_HDR *EventHdr; + TCG_PCR_EVENT2 *TcgPcrEvent2; + TCG_EfiSpecIDEventStruct *TcgEfiSpecIdEventStruct; + UINTN NumberOfEvents; + + DEBUG ((DEBUG_INFO, "EventLogFormat: (0x%x)\n", EventLogFormat)); + + switch (EventLogFormat) { + case EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2: + EventHdr = (TCG_PCR_EVENT_HDR *)(UINTN)EventLogLocation; + while ((UINTN)EventHdr <= EventLogLastEntry) { + DumpEvent (EventHdr); + EventHdr = (TCG_PCR_EVENT_HDR *)((UINTN)EventHdr + sizeof (TCG_PCR_EVENT_HDR) + EventHdr->EventSize); + } + + if (FinalEventsTable == NULL) { + DEBUG ((DEBUG_INFO, "FinalEventsTable: NOT FOUND\n")); + } else { + DEBUG ((DEBUG_INFO, "FinalEventsTable: (0x%x)\n", FinalEventsTable)); + DEBUG ((DEBUG_INFO, " Version: (0x%x)\n", FinalEventsTable->Version)); + DEBUG ((DEBUG_INFO, " NumberOfEvents: (0x%x)\n", FinalEventsTable->NumberOfEvents)); + + EventHdr = (TCG_PCR_EVENT_HDR *)(UINTN)(FinalEventsTable + 1); + for (NumberOfEvents = 0; NumberOfEvents < FinalEventsTable->NumberOfEvents; NumberOfEvents++) { + DumpEvent (EventHdr); + EventHdr = (TCG_PCR_EVENT_HDR *)((UINTN)EventHdr + sizeof (TCG_PCR_EVENT_HDR) + EventHdr->EventSize); + } + } + + break; + case EFI_TCG2_EVENT_LOG_FORMAT_TCG_2: + // + // Dump first event + // + EventHdr = (TCG_PCR_EVENT_HDR *)(UINTN)EventLogLocation; + DumpEvent (EventHdr); + + TcgEfiSpecIdEventStruct = (TCG_EfiSpecIDEventStruct *)(EventHdr + 1); + DumpTcgEfiSpecIdEventStruct (TcgEfiSpecIdEventStruct); + + TcgPcrEvent2 = (TCG_PCR_EVENT2 *)((UINTN)TcgEfiSpecIdEventStruct + GetTcgEfiSpecIdEventStructSize (TcgEfiSpecIdEventStruct)); + while ((UINTN)TcgPcrEvent2 <= EventLogLastEntry) { + DumpEvent2 (TcgPcrEvent2); + TcgPcrEvent2 = (TCG_PCR_EVENT2 *)((UINTN)TcgPcrEvent2 + GetPcrEvent2Size (TcgPcrEvent2)); + } + + if (FinalEventsTable == NULL) { + DEBUG ((DEBUG_INFO, "FinalEventsTable: NOT FOUND\n")); + } else { + DEBUG ((DEBUG_INFO, "FinalEventsTable: (0x%x)\n", FinalEventsTable)); + DEBUG ((DEBUG_INFO, " Version: (0x%x)\n", FinalEventsTable->Version)); + DEBUG ((DEBUG_INFO, " NumberOfEvents: (0x%x)\n", FinalEventsTable->NumberOfEvents)); + + TcgPcrEvent2 = (TCG_PCR_EVENT2 *)(UINTN)(FinalEventsTable + 1); + for (NumberOfEvents = 0; NumberOfEvents < FinalEventsTable->NumberOfEvents; NumberOfEvents++) { + DumpEvent2 (TcgPcrEvent2); + TcgPcrEvent2 = (TCG_PCR_EVENT2 *)((UINTN)TcgPcrEvent2 + GetPcrEvent2Size (TcgPcrEvent2)); + } + } + + break; + } + + return; +} + +/** + The EFI_TCG2_PROTOCOL Get Event Log function call allows a caller to + retrieve the address of a given event log and its last entry. + + @param[in] This Indicates the calling context + @param[in] EventLogFormat The type of the event log for which the information is requested. + @param[out] EventLogLocation A pointer to the memory address of the event log. + @param[out] EventLogLastEntry If the Event Log contains more than one entry, this is a pointer to the + address of the start of the last entry in the event log in memory. + @param[out] EventLogTruncated If the Event Log is missing at least one entry because an event would + have exceeded the area allocated for events, this value is set to TRUE. + Otherwise, the value will be FALSE and the Event Log will be complete. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect + (e.g. asking for an event log whose format is not supported). +**/ +EFI_STATUS +EFIAPI +Tcg2GetEventLog ( + IN EFI_TCG2_PROTOCOL *This, + IN EFI_TCG2_EVENT_LOG_FORMAT EventLogFormat, + OUT EFI_PHYSICAL_ADDRESS *EventLogLocation, + OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry, + OUT BOOLEAN *EventLogTruncated + ) +{ + UINTN Index; + + DEBUG ((DEBUG_INFO, "Tcg2GetEventLog ... (0x%x)\n", EventLogFormat)); + + if (This == NULL) { + return EFI_INVALID_PARAMETER; + } + + for (Index = 0; Index < sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0]); Index++) { + if (EventLogFormat == mTcg2EventInfo[Index].LogFormat) { + break; + } + } + + if (Index == sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0])) { + return EFI_INVALID_PARAMETER; + } + + if ((mTcg2EventInfo[Index].LogFormat & mTcgDxeData.BsCap.SupportedEventLogs) == 0) { + return EFI_INVALID_PARAMETER; + } + + if (!mTcgDxeData.BsCap.TPMPresentFlag) { + if (EventLogLocation != NULL) { + *EventLogLocation = 0; + } + + if (EventLogLastEntry != NULL) { + *EventLogLastEntry = 0; + } + + if (EventLogTruncated != NULL) { + *EventLogTruncated = FALSE; + } + + return EFI_SUCCESS; + } + + if (EventLogLocation != NULL) { + *EventLogLocation = mTcgDxeData.EventLogAreaStruct[Index].Lasa; + DEBUG ((DEBUG_INFO, "Tcg2GetEventLog (EventLogLocation - %x)\n", *EventLogLocation)); + } + + if (EventLogLastEntry != NULL) { + if (!mTcgDxeData.EventLogAreaStruct[Index].EventLogStarted) { + *EventLogLastEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)0; + } else { + *EventLogLastEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)mTcgDxeData.EventLogAreaStruct[Index].LastEvent; + } + + DEBUG ((DEBUG_INFO, "Tcg2GetEventLog (EventLogLastEntry - %x)\n", *EventLogLastEntry)); + } + + if (EventLogTruncated != NULL) { + *EventLogTruncated = mTcgDxeData.EventLogAreaStruct[Index].EventLogTruncated; + DEBUG ((DEBUG_INFO, "Tcg2GetEventLog (EventLogTruncated - %x)\n", *EventLogTruncated)); + } + + DEBUG ((DEBUG_INFO, "Tcg2GetEventLog - %r\n", EFI_SUCCESS)); + + // Dump Event Log for debug purpose + if ((EventLogLocation != NULL) && (EventLogLastEntry != NULL)) { + DumpEventLog (EventLogFormat, *EventLogLocation, *EventLogLastEntry, mTcgDxeData.FinalEventsTable[Index]); + } + + // + // All events generated after the invocation of EFI_TCG2_GET_EVENT_LOG SHALL be stored + // in an instance of an EFI_CONFIGURATION_TABLE named by the VendorGuid of EFI_TCG2_FINAL_EVENTS_TABLE_GUID. + // + mTcgDxeData.GetEventLogCalled[Index] = TRUE; + + return EFI_SUCCESS; +} + +/** + Return if this is a Tcg800155PlatformIdEvent. + + @param[in] NewEventHdr Pointer to a TCG_PCR_EVENT_HDR/TCG_PCR_EVENT_EX data structure. + @param[in] NewEventHdrSize New event header size. + @param[in] NewEventData Pointer to the new event data. + @param[in] NewEventSize New event data size. + + @retval TRUE This is a Tcg800155PlatformIdEvent. + @retval FALSE This is NOT a Tcg800155PlatformIdEvent. + +**/ +BOOLEAN +Is800155Event ( + IN VOID *NewEventHdr, + IN UINT32 NewEventHdrSize, + IN UINT8 *NewEventData, + IN UINT32 NewEventSize + ) +{ + if ((((TCG_PCR_EVENT2_HDR *)NewEventHdr)->EventType == EV_NO_ACTION) && + (NewEventSize >= sizeof (TCG_Sp800_155_PlatformId_Event2)) && + (CompareMem ( + NewEventData, + TCG_Sp800_155_PlatformId_Event2_SIGNATURE, + sizeof (TCG_Sp800_155_PlatformId_Event2_SIGNATURE) - 1 + ) == 0)) + { + return TRUE; + } + + return FALSE; +} + +/** + Add a new entry to the Event Log. + + @param[in, out] EventLogAreaStruct The event log area data structure + @param[in] NewEventHdr Pointer to a TCG_PCR_EVENT_HDR/TCG_PCR_EVENT_EX data structure. + @param[in] NewEventHdrSize New event header size. + @param[in] NewEventData Pointer to the new event data. + @param[in] NewEventSize New event data size. + + @retval EFI_SUCCESS The new event log entry was added. + @retval EFI_OUT_OF_RESOURCES No enough memory to log the new event. + +**/ +EFI_STATUS +TcgCommLogEvent ( + IN OUT TCG_EVENT_LOG_AREA_STRUCT *EventLogAreaStruct, + IN VOID *NewEventHdr, + IN UINT32 NewEventHdrSize, + IN UINT8 *NewEventData, + IN UINT32 NewEventSize + ) +{ + UINTN NewLogSize; + BOOLEAN Record800155Event; + + if (NewEventSize > MAX_ADDRESS - NewEventHdrSize) { + return EFI_OUT_OF_RESOURCES; + } + + NewLogSize = NewEventHdrSize + NewEventSize; + + if (NewLogSize > MAX_ADDRESS - EventLogAreaStruct->EventLogSize) { + return EFI_OUT_OF_RESOURCES; + } + + if (NewLogSize + EventLogAreaStruct->EventLogSize > EventLogAreaStruct->Laml) { + DEBUG ((DEBUG_INFO, " Laml - 0x%x\n", EventLogAreaStruct->Laml)); + DEBUG ((DEBUG_INFO, " NewLogSize - 0x%x\n", NewLogSize)); + DEBUG ((DEBUG_INFO, " LogSize - 0x%x\n", EventLogAreaStruct->EventLogSize)); + DEBUG ((DEBUG_INFO, "TcgCommLogEvent - %r\n", EFI_OUT_OF_RESOURCES)); + return EFI_OUT_OF_RESOURCES; + } + + // + // Check 800-155 event + // Record to 800-155 event offset only. + // If the offset is 0, no need to record. + // + Record800155Event = Is800155Event (NewEventHdr, NewEventHdrSize, NewEventData, NewEventSize); + if (Record800155Event) { + if (EventLogAreaStruct->Next800155EventOffset != 0) { + CopyMem ( + (UINT8 *)(UINTN)EventLogAreaStruct->Lasa + EventLogAreaStruct->Next800155EventOffset + NewLogSize, + (UINT8 *)(UINTN)EventLogAreaStruct->Lasa + EventLogAreaStruct->Next800155EventOffset, + EventLogAreaStruct->EventLogSize - EventLogAreaStruct->Next800155EventOffset + ); + + CopyMem ( + (UINT8 *)(UINTN)EventLogAreaStruct->Lasa + EventLogAreaStruct->Next800155EventOffset, + NewEventHdr, + NewEventHdrSize + ); + CopyMem ( + (UINT8 *)(UINTN)EventLogAreaStruct->Lasa + EventLogAreaStruct->Next800155EventOffset + NewEventHdrSize, + NewEventData, + NewEventSize + ); + + EventLogAreaStruct->Next800155EventOffset += NewLogSize; + EventLogAreaStruct->LastEvent += NewLogSize; + EventLogAreaStruct->EventLogSize += NewLogSize; + } + + return EFI_SUCCESS; + } + + EventLogAreaStruct->LastEvent = (UINT8 *)(UINTN)EventLogAreaStruct->Lasa + EventLogAreaStruct->EventLogSize; + EventLogAreaStruct->EventLogSize += NewLogSize; + CopyMem (EventLogAreaStruct->LastEvent, NewEventHdr, NewEventHdrSize); + CopyMem ( + EventLogAreaStruct->LastEvent + NewEventHdrSize, + NewEventData, + NewEventSize + ); + return EFI_SUCCESS; +} + +/** + Add a new entry to the Event Log. + + @param[in] EventLogFormat The type of the event log for which the information is requested. + @param[in] NewEventHdr Pointer to a TCG_PCR_EVENT_HDR/TCG_PCR_EVENT_EX data structure. + @param[in] NewEventHdrSize New event header size. + @param[in] NewEventData Pointer to the new event data. + @param[in] NewEventSize New event data size. + + @retval EFI_SUCCESS The new event log entry was added. + @retval EFI_OUT_OF_RESOURCES No enough memory to log the new event. + +**/ +EFI_STATUS +TcgDxeLogEvent ( + IN EFI_TCG2_EVENT_LOG_FORMAT EventLogFormat, + IN VOID *NewEventHdr, + IN UINT32 NewEventHdrSize, + IN UINT8 *NewEventData, + IN UINT32 NewEventSize + ) +{ + EFI_STATUS Status; + UINTN Index; + TCG_EVENT_LOG_AREA_STRUCT *EventLogAreaStruct; + + for (Index = 0; Index < sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0]); Index++) { + if (EventLogFormat == mTcg2EventInfo[Index].LogFormat) { + break; + } + } + + if (Index == sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0])) { + return EFI_INVALID_PARAMETER; + } + + // + // Record to normal event log + // + EventLogAreaStruct = &mTcgDxeData.EventLogAreaStruct[Index]; + + if (EventLogAreaStruct->EventLogTruncated) { + return EFI_VOLUME_FULL; + } + + Status = TcgCommLogEvent ( + EventLogAreaStruct, + NewEventHdr, + NewEventHdrSize, + NewEventData, + NewEventSize + ); + + if (Status == EFI_OUT_OF_RESOURCES) { + EventLogAreaStruct->EventLogTruncated = TRUE; + return EFI_VOLUME_FULL; + } else if (Status == EFI_SUCCESS) { + EventLogAreaStruct->EventLogStarted = TRUE; + } + + // + // If GetEventLog is called, record to FinalEventsTable, too. + // + if (mTcgDxeData.GetEventLogCalled[Index]) { + if (mTcgDxeData.FinalEventsTable[Index] == NULL) { + // + // no need for FinalEventsTable + // + return EFI_SUCCESS; + } + + EventLogAreaStruct = &mTcgDxeData.FinalEventLogAreaStruct[Index]; + + if (EventLogAreaStruct->EventLogTruncated) { + return EFI_VOLUME_FULL; + } + + Status = TcgCommLogEvent ( + EventLogAreaStruct, + NewEventHdr, + NewEventHdrSize, + NewEventData, + NewEventSize + ); + if (Status == EFI_OUT_OF_RESOURCES) { + EventLogAreaStruct->EventLogTruncated = TRUE; + return EFI_VOLUME_FULL; + } else if (Status == EFI_SUCCESS) { + EventLogAreaStruct->EventLogStarted = TRUE; + // + // Increase the NumberOfEvents in FinalEventsTable + // + (mTcgDxeData.FinalEventsTable[Index])->NumberOfEvents++; + DEBUG ((DEBUG_INFO, "FinalEventsTable->NumberOfEvents - 0x%x\n", (mTcgDxeData.FinalEventsTable[Index])->NumberOfEvents)); + DEBUG ((DEBUG_INFO, " Size - 0x%x\n", (UINTN)EventLogAreaStruct->EventLogSize)); + } + } + + return Status; +} + +/** + Get TPML_DIGEST_VALUES compact binary buffer size. + + @param[in] DigestListBin TPML_DIGEST_VALUES compact binary buffer. + + @return TPML_DIGEST_VALUES compact binary buffer size. +**/ +UINT32 +GetDigestListBinSize ( + IN VOID *DigestListBin + ) +{ + UINTN Index; + UINT16 DigestSize; + UINT32 TotalSize; + UINT32 Count; + TPMI_ALG_HASH HashAlg; + + Count = ReadUnaligned32 (DigestListBin); + TotalSize = sizeof (Count); + DigestListBin = (UINT8 *)DigestListBin + sizeof (Count); + for (Index = 0; Index < Count; Index++) { + HashAlg = ReadUnaligned16 (DigestListBin); + TotalSize += sizeof (HashAlg); + DigestListBin = (UINT8 *)DigestListBin + sizeof (HashAlg); + + DigestSize = GetHashSizeFromAlgo (HashAlg); + TotalSize += DigestSize; + DigestListBin = (UINT8 *)DigestListBin + DigestSize; + } + + return TotalSize; +} + +/** + Copy TPML_DIGEST_VALUES compact binary into a buffer + + @param[in,out] Buffer Buffer to hold copied TPML_DIGEST_VALUES compact binary. + @param[in] DigestListBin TPML_DIGEST_VALUES compact binary buffer. + @param[in] HashAlgorithmMask HASH bits corresponding to the desired digests to copy. + @param[out] HashAlgorithmMaskCopied Pointer to HASH bits corresponding to the digests copied. + + @return The end of buffer to hold TPML_DIGEST_VALUES compact binary. +**/ +VOID * +CopyDigestListBinToBuffer ( + IN OUT VOID *Buffer, + IN VOID *DigestListBin, + IN UINT32 HashAlgorithmMask, + OUT UINT32 *HashAlgorithmMaskCopied + ) +{ + UINTN Index; + UINT16 DigestSize; + UINT32 Count; + TPMI_ALG_HASH HashAlg; + UINT32 DigestListCount; + UINT32 *DigestListCountPtr; + + DigestListCountPtr = (UINT32 *)Buffer; + DigestListCount = 0; + (*HashAlgorithmMaskCopied) = 0; + + Count = ReadUnaligned32 (DigestListBin); + Buffer = (UINT8 *)Buffer + sizeof (Count); + DigestListBin = (UINT8 *)DigestListBin + sizeof (Count); + for (Index = 0; Index < Count; Index++) { + HashAlg = ReadUnaligned16 (DigestListBin); + DigestListBin = (UINT8 *)DigestListBin + sizeof (HashAlg); + DigestSize = GetHashSizeFromAlgo (HashAlg); + + if (IsHashAlgSupportedInHashAlgorithmMask (HashAlg, HashAlgorithmMask)) { + CopyMem (Buffer, &HashAlg, sizeof (HashAlg)); + Buffer = (UINT8 *)Buffer + sizeof (HashAlg); + CopyMem (Buffer, DigestListBin, DigestSize); + Buffer = (UINT8 *)Buffer + DigestSize; + DigestListCount++; + (*HashAlgorithmMaskCopied) |= GetHashMaskFromAlgo (HashAlg); + } else { + DEBUG ((DEBUG_ERROR, "WARNING: CopyDigestListBinToBuffer Event log has HashAlg unsupported by PCR bank (0x%x)\n", HashAlg)); + } + + DigestListBin = (UINT8 *)DigestListBin + DigestSize; + } + + WriteUnaligned32 (DigestListCountPtr, DigestListCount); + + return Buffer; +} + +/** + Add a new entry to the Event Log. + + @param[in] DigestList A list of digest. + @param[in,out] NewEventHdr Pointer to a TCG_PCR_EVENT_HDR data structure. + @param[in] NewEventData Pointer to the new event data. + + @retval EFI_SUCCESS The new event log entry was added. + @retval EFI_OUT_OF_RESOURCES No enough memory to log the new event. +**/ +EFI_STATUS +TcgDxeLogHashEvent ( + IN TPML_DIGEST_VALUES *DigestList, + IN OUT TCG_PCR_EVENT_HDR *NewEventHdr, + IN UINT8 *NewEventData + ) +{ + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN Index; + EFI_STATUS RetStatus; + TCG_PCR_EVENT2 TcgPcrEvent2; + UINT8 *DigestBuffer; + UINT32 *EventSizePtr; + + DEBUG ((DEBUG_INFO, "SupportedEventLogs - 0x%08x\n", mTcgDxeData.BsCap.SupportedEventLogs)); + + RetStatus = EFI_SUCCESS; + for (Index = 0; Index < sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0]); Index++) { + if ((mTcgDxeData.BsCap.SupportedEventLogs & mTcg2EventInfo[Index].LogFormat) != 0) { + DEBUG ((DEBUG_INFO, " LogFormat - 0x%08x\n", mTcg2EventInfo[Index].LogFormat)); + switch (mTcg2EventInfo[Index].LogFormat) { + case EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2: + Status = GetDigestFromDigestList (TPM_ALG_SHA1, DigestList, &NewEventHdr->Digest); + if (!EFI_ERROR (Status)) { + // + // Enter critical region + // + OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + NewEventHdr, + sizeof (TCG_PCR_EVENT_HDR), + NewEventData, + NewEventHdr->EventSize + ); + if (Status != EFI_SUCCESS) { + RetStatus = Status; + } + + gBS->RestoreTPL (OldTpl); + // + // Exit critical region + // + } + + break; + case EFI_TCG2_EVENT_LOG_FORMAT_TCG_2: + ZeroMem (&TcgPcrEvent2, sizeof (TcgPcrEvent2)); + TcgPcrEvent2.PCRIndex = NewEventHdr->PCRIndex; + TcgPcrEvent2.EventType = NewEventHdr->EventType; + DigestBuffer = (UINT8 *)&TcgPcrEvent2.Digest; + EventSizePtr = CopyDigestListToBuffer (DigestBuffer, DigestList, mTcgDxeData.BsCap.ActivePcrBanks); + CopyMem (EventSizePtr, &NewEventHdr->EventSize, sizeof (NewEventHdr->EventSize)); + + // + // Enter critical region + // + OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + &TcgPcrEvent2, + sizeof (TcgPcrEvent2.PCRIndex) + sizeof (TcgPcrEvent2.EventType) + GetDigestListBinSize (DigestBuffer) + sizeof (TcgPcrEvent2.EventSize), + NewEventData, + NewEventHdr->EventSize + ); + if (Status != EFI_SUCCESS) { + RetStatus = Status; + } + + gBS->RestoreTPL (OldTpl); + // + // Exit critical region + // + break; + } + } + } + + return RetStatus; +} + +/** + Do a hash operation on a data buffer, extend a specific TPM PCR with the hash result, + and add an entry to the Event Log. + + @param[in] Flags Bitmap providing additional information. + @param[in] HashData Physical address of the start of the data buffer + to be hashed, extended, and logged. + @param[in] HashDataLen The length, in bytes, of the buffer referenced by HashData + @param[in, out] NewEventHdr Pointer to a TCG_PCR_EVENT_HDR data structure. + @param[in] NewEventData Pointer to the new event data. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to log the new event. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + +**/ +EFI_STATUS +TcgDxeHashLogExtendEvent ( + IN UINT64 Flags, + IN UINT8 *HashData, + IN UINT64 HashDataLen, + IN OUT TCG_PCR_EVENT_HDR *NewEventHdr, + IN UINT8 *NewEventData + ) +{ + EFI_STATUS Status; + TPML_DIGEST_VALUES DigestList; + TCG_PCR_EVENT2_HDR NoActionEvent; + + if (!mTcgDxeData.BsCap.TPMPresentFlag) { + return EFI_DEVICE_ERROR; + } + + if (NewEventHdr->EventType == EV_NO_ACTION) { + // + // Do not do TPM extend for EV_NO_ACTION + // + Status = EFI_SUCCESS; + InitNoActionEvent (&NoActionEvent, NewEventHdr->EventSize); + if ((Flags & EFI_TCG2_EXTEND_ONLY) == 0) { + Status = TcgDxeLogHashEvent (&(NoActionEvent.Digests), NewEventHdr, NewEventData); + } + + return Status; + } + + Status = HashAndExtend ( + NewEventHdr->PCRIndex, + HashData, + (UINTN)HashDataLen, + &DigestList + ); + if (!EFI_ERROR (Status)) { + if ((Flags & EFI_TCG2_EXTEND_ONLY) == 0) { + Status = TcgDxeLogHashEvent (&DigestList, NewEventHdr, NewEventData); + } + } + + if (Status == EFI_DEVICE_ERROR) { + DEBUG ((DEBUG_ERROR, "TcgDxeHashLogExtendEvent - %r. Disable TPM.\n", Status)); + mTcgDxeData.BsCap.TPMPresentFlag = FALSE; + REPORT_STATUS_CODE ( + EFI_ERROR_CODE | EFI_ERROR_MINOR, + (PcdGet32 (PcdStatusCodeSubClassTpmDevice) | EFI_P_EC_INTERFACE_ERROR) + ); + } + + return Status; +} + +/** + The EFI_TCG2_PROTOCOL HashLogExtendEvent function call provides callers with + an opportunity to extend and optionally log events without requiring + knowledge of actual TPM commands. + The extend operation will occur even if this function cannot create an event + log entry (e.g. due to the event log being full). + + @param[in] This Indicates the calling context + @param[in] Flags Bitmap providing additional information. + @param[in] DataToHash Physical address of the start of the data buffer to be hashed. + @param[in] DataToHashLen The length in bytes of the buffer referenced by DataToHash. + @param[in] Event Pointer to data buffer containing information about the event. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + @retval EFI_VOLUME_FULL The extend operation occurred, but the event could not be written to one or more event logs. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_UNSUPPORTED The PE/COFF image type is not supported. +**/ +EFI_STATUS +EFIAPI +Tcg2HashLogExtendEvent ( + IN EFI_TCG2_PROTOCOL *This, + IN UINT64 Flags, + IN EFI_PHYSICAL_ADDRESS DataToHash, + IN UINT64 DataToHashLen, + IN EFI_TCG2_EVENT *Event + ) +{ + EFI_STATUS Status; + TCG_PCR_EVENT_HDR NewEventHdr; + TPML_DIGEST_VALUES DigestList; + + DEBUG ((DEBUG_VERBOSE, "Tcg2HashLogExtendEvent ...\n")); + + if ((This == NULL) || (Event == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Do not check hash data size for EV_NO_ACTION event. + // + if ((Event->Header.EventType != EV_NO_ACTION) && (DataToHash == 0)) { + return EFI_INVALID_PARAMETER; + } + + if (!mTcgDxeData.BsCap.TPMPresentFlag) { + return EFI_DEVICE_ERROR; + } + + if (Event->Size < Event->Header.HeaderSize + sizeof (UINT32)) { + return EFI_INVALID_PARAMETER; + } + + if (Event->Header.PCRIndex > MAX_PCR_INDEX) { + return EFI_INVALID_PARAMETER; + } + + NewEventHdr.PCRIndex = Event->Header.PCRIndex; + NewEventHdr.EventType = Event->Header.EventType; + NewEventHdr.EventSize = Event->Size - sizeof (UINT32) - Event->Header.HeaderSize; + if ((Flags & PE_COFF_IMAGE) != 0) { + Status = MeasurePeImageAndExtend ( + NewEventHdr.PCRIndex, + DataToHash, + (UINTN)DataToHashLen, + &DigestList + ); + if (!EFI_ERROR (Status)) { + if ((Flags & EFI_TCG2_EXTEND_ONLY) == 0) { + Status = TcgDxeLogHashEvent (&DigestList, &NewEventHdr, Event->Event); + } + } + + if (Status == EFI_DEVICE_ERROR) { + DEBUG ((DEBUG_ERROR, "MeasurePeImageAndExtend - %r. Disable TPM.\n", Status)); + mTcgDxeData.BsCap.TPMPresentFlag = FALSE; + REPORT_STATUS_CODE ( + EFI_ERROR_CODE | EFI_ERROR_MINOR, + (PcdGet32 (PcdStatusCodeSubClassTpmDevice) | EFI_P_EC_INTERFACE_ERROR) + ); + } + } else { + Status = TcgDxeHashLogExtendEvent ( + Flags, + (UINT8 *)(UINTN)DataToHash, + DataToHashLen, + &NewEventHdr, + Event->Event + ); + } + + DEBUG ((DEBUG_VERBOSE, "Tcg2HashLogExtendEvent - %r\n", Status)); + return Status; +} + +/** + This service enables the sending of commands to the TPM. + + @param[in] This Indicates the calling context + @param[in] InputParameterBlockSize Size of the TPM input parameter block. + @param[in] InputParameterBlock Pointer to the TPM input parameter block. + @param[in] OutputParameterBlockSize Size of the TPM output parameter block. + @param[in] OutputParameterBlock Pointer to the TPM output parameter block. + + @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received. + @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. +**/ +EFI_STATUS +EFIAPI +Tcg2SubmitCommand ( + IN EFI_TCG2_PROTOCOL *This, + IN UINT32 InputParameterBlockSize, + IN UINT8 *InputParameterBlock, + IN UINT32 OutputParameterBlockSize, + IN UINT8 *OutputParameterBlock + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Tcg2SubmitCommand ...\n")); + + if ((This == NULL) || + (InputParameterBlockSize == 0) || (InputParameterBlock == NULL) || + (OutputParameterBlockSize == 0) || (OutputParameterBlock == NULL)) + { + return EFI_INVALID_PARAMETER; + } + + if (!mTcgDxeData.BsCap.TPMPresentFlag) { + return EFI_DEVICE_ERROR; + } + + if (InputParameterBlockSize > mTcgDxeData.BsCap.MaxCommandSize) { + return EFI_INVALID_PARAMETER; + } + + if (OutputParameterBlockSize > mTcgDxeData.BsCap.MaxResponseSize) { + return EFI_INVALID_PARAMETER; + } + + Status = Tpm2SubmitCommand ( + InputParameterBlockSize, + InputParameterBlock, + &OutputParameterBlockSize, + OutputParameterBlock + ); + DEBUG ((DEBUG_INFO, "Tcg2SubmitCommand - %r\n", Status)); + return Status; +} + +/** + This service returns the currently active PCR banks. + + @param[in] This Indicates the calling context + @param[out] ActivePcrBanks Pointer to the variable receiving the bitmap of currently active PCR banks. + + @retval EFI_SUCCESS The bitmap of active PCR banks was stored in the ActivePcrBanks parameter. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. +**/ +EFI_STATUS +EFIAPI +Tcg2GetActivePCRBanks ( + IN EFI_TCG2_PROTOCOL *This, + OUT UINT32 *ActivePcrBanks + ) +{ + if (ActivePcrBanks == NULL) { + return EFI_INVALID_PARAMETER; + } + + *ActivePcrBanks = mTcgDxeData.BsCap.ActivePcrBanks; + return EFI_SUCCESS; +} + +/** + This service sets the currently active PCR banks. + + @param[in] This Indicates the calling context + @param[in] ActivePcrBanks Bitmap of the requested active PCR banks. At least one bit SHALL be set. + + @retval EFI_SUCCESS The bitmap in ActivePcrBank parameter is already active. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. +**/ +EFI_STATUS +EFIAPI +Tcg2SetActivePCRBanks ( + IN EFI_TCG2_PROTOCOL *This, + IN UINT32 ActivePcrBanks + ) +{ + EFI_STATUS Status; + UINT32 ReturnCode; + + DEBUG ((DEBUG_INFO, "Tcg2SetActivePCRBanks ... (0x%x)\n", ActivePcrBanks)); + + if (ActivePcrBanks == 0) { + return EFI_INVALID_PARAMETER; + } + + if ((ActivePcrBanks & (~mTcgDxeData.BsCap.HashAlgorithmBitmap)) != 0) { + return EFI_INVALID_PARAMETER; + } + + if (ActivePcrBanks == mTcgDxeData.BsCap.ActivePcrBanks) { + // + // Need clear previous SET_PCR_BANKS setting + // + ReturnCode = Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction (TCG2_PHYSICAL_PRESENCE_NO_ACTION, 0); + } else { + ReturnCode = Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction (TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS, ActivePcrBanks); + } + + if (ReturnCode == TCG_PP_SUBMIT_REQUEST_TO_PREOS_SUCCESS) { + Status = EFI_SUCCESS; + } else if (ReturnCode == TCG_PP_SUBMIT_REQUEST_TO_PREOS_GENERAL_FAILURE) { + Status = EFI_OUT_OF_RESOURCES; + } else if (ReturnCode == TCG_PP_SUBMIT_REQUEST_TO_PREOS_NOT_IMPLEMENTED) { + Status = EFI_UNSUPPORTED; + } else { + Status = EFI_DEVICE_ERROR; + } + + DEBUG ((DEBUG_INFO, "Tcg2SetActivePCRBanks - %r\n", Status)); + + return Status; +} + +/** + This service retrieves the result of a previous invocation of SetActivePcrBanks. + + @param[in] This Indicates the calling context + @param[out] OperationPresent Non-zero value to indicate a SetActivePcrBank operation was invoked during the last boot. + @param[out] Response The response from the SetActivePcrBank request. + + @retval EFI_SUCCESS The result value could be returned. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. +**/ +EFI_STATUS +EFIAPI +Tcg2GetResultOfSetActivePcrBanks ( + IN EFI_TCG2_PROTOCOL *This, + OUT UINT32 *OperationPresent, + OUT UINT32 *Response + ) +{ + UINT32 ReturnCode; + + if ((OperationPresent == NULL) || (Response == NULL)) { + return EFI_INVALID_PARAMETER; + } + + ReturnCode = Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction (OperationPresent, Response); + if (ReturnCode == TCG_PP_RETURN_TPM_OPERATION_RESPONSE_SUCCESS) { + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + +EFI_TCG2_PROTOCOL mTcg2Protocol = { + Tcg2GetCapability, + Tcg2GetEventLog, + Tcg2HashLogExtendEvent, + Tcg2SubmitCommand, + Tcg2GetActivePCRBanks, + Tcg2SetActivePCRBanks, + Tcg2GetResultOfSetActivePcrBanks, +}; + +/** + Check whether PSP measurement data is present and save it into TCG log + + @retval TRUE PSP measurement data is present + @retval FALSE PSP measurement data is not present + +**/ +BOOLEAN +IsAmdTcgLogPresent ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 DesiredConfig; + UINT32 ConfigStatus; + UINT32 LogDataSize; + UINT8 LogData[0x1000]; + UINT8 *Buffer; + TCG_PCR_EVENT_HDR *TcgPcrEventPtr; + TCG_PCR_EVENT2_HDR *TcgPcrEvent2Ptr; + UINT32 EventHdrSize; + UINT32 EventSize; + + LogDataSize = sizeof (LogData); + Status = PspMboxGetDTPMData (&DesiredConfig, &ConfigStatus, &LogDataSize, LogData); + if (!EFI_ERROR(Status)) { + DEBUG((DEBUG_INFO, "DesiredConfig = 0x%x, ConfigStatus = 0x%x, LogDataSize = 0x%x\n", DesiredConfig, ConfigStatus, LogDataSize)); + if ((DesiredConfig != 0) && (LogDataSize != 0)) { + Buffer = &LogData[0]; + TcgPcrEventPtr = (TCG_PCR_EVENT_HDR *)Buffer; + Status = TcgDxeLogEvent ( + EFI_TCG2_EVENT_LOG_FORMAT_TCG_2, + TcgPcrEventPtr, + sizeof (TCG_PCR_EVENT_HDR), + &LogData[sizeof (TCG_PCR_EVENT_HDR)], + TcgPcrEventPtr->EventSize + ); + Buffer = &LogData[sizeof (TCG_PCR_EVENT_HDR) + TcgPcrEventPtr->EventSize]; + + while (Buffer < &LogData[LogDataSize]) { + TcgPcrEvent2Ptr = (TCG_PCR_EVENT2_HDR *)Buffer; + EventHdrSize = sizeof (TcgPcrEvent2Ptr->PCRIndex) + sizeof (TcgPcrEvent2Ptr->EventType) + sizeof (TcgPcrEvent2Ptr->Digests.count) + + sizeof (TcgPcrEvent2Ptr->Digests.digests[0].hashAlg) + sizeof (TcgPcrEvent2Ptr->Digests.digests[0].digest.sha256); + Buffer += EventHdrSize; + EventSize = *(UINT32 *)Buffer; + EventHdrSize += sizeof (TcgPcrEvent2Ptr->EventSize); + Buffer += sizeof (TcgPcrEvent2Ptr->EventSize); + Status = TcgDxeLogEvent ( + EFI_TCG2_EVENT_LOG_FORMAT_TCG_2, + TcgPcrEvent2Ptr, + EventHdrSize, + Buffer, + EventSize + ); + Buffer += EventSize; + } + return TRUE; + } + } else { + DEBUG((DEBUG_INFO, "PspMboxGetDTPMData Fail!!! Status = %r\n", Status)); + } + + return FALSE; +} + +/** + Initialize the Event Log and log events passed from the PEI phase. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + +**/ +EFI_STATUS +SetupEventLog ( + VOID + ) +{ + EFI_STATUS Status; + VOID *TcgEvent; + EFI_PEI_HOB_POINTERS GuidHob; + EFI_PHYSICAL_ADDRESS Lasa; + UINTN Index; + VOID *DigestListBin; + TPML_DIGEST_VALUES TempDigestListBin; + UINT32 DigestListBinSize; + UINT8 *Event; + UINT32 EventSize; + UINT32 *EventSizePtr; + UINT32 HashAlgorithmMaskCopied; + TCG_EfiSpecIDEventStruct *TcgEfiSpecIdEventStruct; + UINT8 TempBuf[sizeof (TCG_EfiSpecIDEventStruct) + sizeof (UINT32) + (HASH_COUNT * sizeof (TCG_EfiSpecIdEventAlgorithmSize)) + sizeof (UINT8)]; + TCG_PCR_EVENT_HDR SpecIdEvent; + TCG_PCR_EVENT2_HDR NoActionEvent; + TCG_EfiSpecIdEventAlgorithmSize *DigestSize; + TCG_EfiSpecIdEventAlgorithmSize *TempDigestSize; + UINT8 *VendorInfoSize; + UINT32 NumberOfAlgorithms; + TCG_EfiStartupLocalityEvent StartupLocalityEvent; + + DEBUG ((DEBUG_INFO, "SetupEventLog\n")); + + // + // 1. Create Log Area + // + for (Index = 0; Index < sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0]); Index++) { + if ((mTcgDxeData.BsCap.SupportedEventLogs & mTcg2EventInfo[Index].LogFormat) != 0) { + mTcgDxeData.EventLogAreaStruct[Index].EventLogFormat = mTcg2EventInfo[Index].LogFormat; + if (PcdGet8 (PcdTpm2AcpiTableRev) >= 4) { + Status = gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIMemoryNVS, + EFI_SIZE_TO_PAGES (PcdGet32 (PcdTcgLogAreaMinLen)), + &Lasa + ); + } else { + Status = gBS->AllocatePages ( + AllocateAnyPages, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (PcdGet32 (PcdTcgLogAreaMinLen)), + &Lasa + ); + } + + if (EFI_ERROR (Status)) { + return Status; + } + + mTcgDxeData.EventLogAreaStruct[Index].Lasa = Lasa; + mTcgDxeData.EventLogAreaStruct[Index].Laml = PcdGet32 (PcdTcgLogAreaMinLen); + mTcgDxeData.EventLogAreaStruct[Index].Next800155EventOffset = 0; + + if ((PcdGet8 (PcdTpm2AcpiTableRev) >= 4) || + (mTcg2EventInfo[Index].LogFormat == EFI_TCG2_EVENT_LOG_FORMAT_TCG_2)) + { + // + // Report TCG2 event log address and length, so that they can be reported in TPM2 ACPI table. + // Ignore the return status, because those fields are optional. + // + PcdSet32S (PcdTpm2AcpiTableLaml, (UINT32)mTcgDxeData.EventLogAreaStruct[Index].Laml); + PcdSet64S (PcdTpm2AcpiTableLasa, mTcgDxeData.EventLogAreaStruct[Index].Lasa); + } + + // + // To initialize them as 0xFF is recommended + // because the OS can know the last entry for that. + // + SetMem ((VOID *)(UINTN)Lasa, PcdGet32 (PcdTcgLogAreaMinLen), 0xFF); + // + // Create first entry for Log Header Entry Data unless PSP already created it + // + if ((mTcg2EventInfo[Index].LogFormat != EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2) && !IsAmdTcgLogPresent ()) { + // + // TcgEfiSpecIdEventStruct + // + TcgEfiSpecIdEventStruct = (TCG_EfiSpecIDEventStruct *)TempBuf; + CopyMem (TcgEfiSpecIdEventStruct->signature, TCG_EfiSpecIDEventStruct_SIGNATURE_03, sizeof (TcgEfiSpecIdEventStruct->signature)); + TcgEfiSpecIdEventStruct->platformClass = PcdGet8 (PcdTpmPlatformClass); + TcgEfiSpecIdEventStruct->specVersionMajor = TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2; + TcgEfiSpecIdEventStruct->specVersionMinor = TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2; + TcgEfiSpecIdEventStruct->specErrata = (UINT8)PcdGet32 (PcdTcgPfpMeasurementRevision); + TcgEfiSpecIdEventStruct->uintnSize = sizeof (UINTN)/sizeof (UINT32); + NumberOfAlgorithms = 0; + DigestSize = (TCG_EfiSpecIdEventAlgorithmSize *)((UINT8 *)TcgEfiSpecIdEventStruct + sizeof (*TcgEfiSpecIdEventStruct) + sizeof (NumberOfAlgorithms)); + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA1) != 0) { + TempDigestSize = DigestSize; + TempDigestSize += NumberOfAlgorithms; + TempDigestSize->algorithmId = TPM_ALG_SHA1; + TempDigestSize->digestSize = SHA1_DIGEST_SIZE; + NumberOfAlgorithms++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA256) != 0) { + TempDigestSize = DigestSize; + TempDigestSize += NumberOfAlgorithms; + TempDigestSize->algorithmId = TPM_ALG_SHA256; + TempDigestSize->digestSize = SHA256_DIGEST_SIZE; + NumberOfAlgorithms++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA384) != 0) { + TempDigestSize = DigestSize; + TempDigestSize += NumberOfAlgorithms; + TempDigestSize->algorithmId = TPM_ALG_SHA384; + TempDigestSize->digestSize = SHA384_DIGEST_SIZE; + NumberOfAlgorithms++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA512) != 0) { + TempDigestSize = DigestSize; + TempDigestSize += NumberOfAlgorithms; + TempDigestSize->algorithmId = TPM_ALG_SHA512; + TempDigestSize->digestSize = SHA512_DIGEST_SIZE; + NumberOfAlgorithms++; + } + + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SM3_256) != 0) { + TempDigestSize = DigestSize; + TempDigestSize += NumberOfAlgorithms; + TempDigestSize->algorithmId = TPM_ALG_SM3_256; + TempDigestSize->digestSize = SM3_256_DIGEST_SIZE; + NumberOfAlgorithms++; + } + + CopyMem (TcgEfiSpecIdEventStruct + 1, &NumberOfAlgorithms, sizeof (NumberOfAlgorithms)); + TempDigestSize = DigestSize; + TempDigestSize += NumberOfAlgorithms; + VendorInfoSize = (UINT8 *)TempDigestSize; + *VendorInfoSize = 0; + + SpecIdEvent.PCRIndex = 0; + SpecIdEvent.EventType = EV_NO_ACTION; + ZeroMem (&SpecIdEvent.Digest, sizeof (SpecIdEvent.Digest)); + SpecIdEvent.EventSize = (UINT32)GetTcgEfiSpecIdEventStructSize (TcgEfiSpecIdEventStruct); + + // + // Log TcgEfiSpecIdEventStruct as the first Event. Event format is TCG_PCR_EVENT. + // TCG EFI Protocol Spec. Section 5.3 Event Log Header + // TCG PC Client PFP spec. Section 9.2 Measurement Event Entries and Log + // + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + &SpecIdEvent, + sizeof (SpecIdEvent), + (UINT8 *)TcgEfiSpecIdEventStruct, + SpecIdEvent.EventSize + ); + // + // record the offset at the end of 800-155 event. + // the future 800-155 event can be inserted here. + // + mTcgDxeData.EventLogAreaStruct[Index].Next800155EventOffset = \ + mTcgDxeData.EventLogAreaStruct[Index].EventLogSize; + + // + // Tcg800155PlatformIdEvent. Event format is TCG_PCR_EVENT2 + // + GuidHob.Guid = GetFirstGuidHob (&gTcg800155PlatformIdEventHobGuid); + while (GuidHob.Guid != NULL) { + InitNoActionEvent (&NoActionEvent, GET_GUID_HOB_DATA_SIZE (GuidHob.Guid)); + + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + &NoActionEvent, + sizeof (NoActionEvent.PCRIndex) + sizeof (NoActionEvent.EventType) + GetDigestListBinSize (&NoActionEvent.Digests) + sizeof (NoActionEvent.EventSize), + GET_GUID_HOB_DATA (GuidHob.Guid), + GET_GUID_HOB_DATA_SIZE (GuidHob.Guid) + ); + + GuidHob.Guid = GET_NEXT_HOB (GuidHob); + GuidHob.Guid = GetNextGuidHob (&gTcg800155PlatformIdEventHobGuid, GuidHob.Guid); + } + + // + // EfiStartupLocalityEvent. Event format is TCG_PCR_EVENT2 + // + GuidHob.Guid = GetFirstGuidHob (&gTpm2StartupLocalityHobGuid); + if (GuidHob.Guid != NULL) { + // + // Get Locality Indicator from StartupLocality HOB + // + StartupLocalityEvent.StartupLocality = *(UINT8 *)(GET_GUID_HOB_DATA (GuidHob.Guid)); + CopyMem (StartupLocalityEvent.Signature, TCG_EfiStartupLocalityEvent_SIGNATURE, sizeof (StartupLocalityEvent.Signature)); + DEBUG ((DEBUG_INFO, "SetupEventLog: Set Locality from HOB into StartupLocalityEvent 0x%02x\n", StartupLocalityEvent.StartupLocality)); + + // + // Initialize StartupLocalityEvent + // + InitNoActionEvent (&NoActionEvent, sizeof (StartupLocalityEvent)); + + // + // Log EfiStartupLocalityEvent as the second Event + // TCG PC Client PFP spec. Section 9.3.4.3 Startup Locality Event + // + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + &NoActionEvent, + sizeof (NoActionEvent.PCRIndex) + sizeof (NoActionEvent.EventType) + GetDigestListBinSize (&NoActionEvent.Digests) + sizeof (NoActionEvent.EventSize), + (UINT8 *)&StartupLocalityEvent, + sizeof (StartupLocalityEvent) + ); + } + } + } + } + + // + // 2. Create Final Log Area + // + for (Index = 0; Index < sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0]); Index++) { + if ((mTcgDxeData.BsCap.SupportedEventLogs & mTcg2EventInfo[Index].LogFormat) != 0) { + if (mTcg2EventInfo[Index].LogFormat == EFI_TCG2_EVENT_LOG_FORMAT_TCG_2) { + Status = gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIMemoryNVS, + EFI_SIZE_TO_PAGES (PcdGet32 (PcdTcg2FinalLogAreaLen)), + &Lasa + ); + if (EFI_ERROR (Status)) { + return Status; + } + + SetMem ((VOID *)(UINTN)Lasa, PcdGet32 (PcdTcg2FinalLogAreaLen), 0xFF); + + // + // Initialize + // + mTcgDxeData.FinalEventsTable[Index] = (VOID *)(UINTN)Lasa; + (mTcgDxeData.FinalEventsTable[Index])->Version = EFI_TCG2_FINAL_EVENTS_TABLE_VERSION; + (mTcgDxeData.FinalEventsTable[Index])->NumberOfEvents = 0; + + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogFormat = mTcg2EventInfo[Index].LogFormat; + mTcgDxeData.FinalEventLogAreaStruct[Index].Lasa = Lasa + sizeof (EFI_TCG2_FINAL_EVENTS_TABLE); + mTcgDxeData.FinalEventLogAreaStruct[Index].Laml = PcdGet32 (PcdTcg2FinalLogAreaLen) - sizeof (EFI_TCG2_FINAL_EVENTS_TABLE); + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogSize = 0; + mTcgDxeData.FinalEventLogAreaStruct[Index].LastEvent = (VOID *)(UINTN)mTcgDxeData.FinalEventLogAreaStruct[Index].Lasa; + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogStarted = FALSE; + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogTruncated = FALSE; + mTcgDxeData.FinalEventLogAreaStruct[Index].Next800155EventOffset = 0; + + // + // Install to configuration table for EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 + // + Status = gBS->InstallConfigurationTable (&gEfiTcg2FinalEventsTableGuid, (VOID *)mTcgDxeData.FinalEventsTable[Index]); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + // + // No need to handle EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 + // + mTcgDxeData.FinalEventsTable[Index] = NULL; + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogFormat = mTcg2EventInfo[Index].LogFormat; + mTcgDxeData.FinalEventLogAreaStruct[Index].Lasa = 0; + mTcgDxeData.FinalEventLogAreaStruct[Index].Laml = 0; + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogSize = 0; + mTcgDxeData.FinalEventLogAreaStruct[Index].LastEvent = 0; + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogStarted = FALSE; + mTcgDxeData.FinalEventLogAreaStruct[Index].EventLogTruncated = FALSE; + mTcgDxeData.FinalEventLogAreaStruct[Index].Next800155EventOffset = 0; + } + } + } + + // + // 3. Sync data from PEI to DXE + // + Status = EFI_SUCCESS; + for (Index = 0; Index < sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0]); Index++) { + if ((mTcgDxeData.BsCap.SupportedEventLogs & mTcg2EventInfo[Index].LogFormat) != 0) { + GuidHob.Raw = GetHobList (); + Status = EFI_SUCCESS; + while (!EFI_ERROR (Status) && + (GuidHob.Raw = GetNextGuidHob (mTcg2EventInfo[Index].EventGuid, GuidHob.Raw)) != NULL) + { + TcgEvent = AllocateCopyPool (GET_GUID_HOB_DATA_SIZE (GuidHob.Guid), GET_GUID_HOB_DATA (GuidHob.Guid)); + ASSERT (TcgEvent != NULL); + GuidHob.Raw = GET_NEXT_HOB (GuidHob); + switch (mTcg2EventInfo[Index].LogFormat) { + case EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2: + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + TcgEvent, + sizeof (TCG_PCR_EVENT_HDR), + ((TCG_PCR_EVENT *)TcgEvent)->Event, + ((TCG_PCR_EVENT_HDR *)TcgEvent)->EventSize + ); + break; + case EFI_TCG2_EVENT_LOG_FORMAT_TCG_2: + DigestListBin = (UINT8 *)TcgEvent + sizeof (TCG_PCRINDEX) + sizeof (TCG_EVENTTYPE); + DigestListBinSize = GetDigestListBinSize (DigestListBin); + // + // Save event size. + // + CopyMem (&EventSize, (UINT8 *)DigestListBin + DigestListBinSize, sizeof (UINT32)); + Event = (UINT8 *)DigestListBin + DigestListBinSize + sizeof (UINT32); + // + // Filter inactive digest in the event2 log from PEI HOB. + // + CopyMem (&TempDigestListBin, DigestListBin, GetDigestListBinSize (DigestListBin)); + EventSizePtr = CopyDigestListBinToBuffer ( + DigestListBin, + &TempDigestListBin, + mTcgDxeData.BsCap.ActivePcrBanks, + &HashAlgorithmMaskCopied + ); + if (HashAlgorithmMaskCopied != mTcgDxeData.BsCap.ActivePcrBanks) { + DEBUG (( + DEBUG_ERROR, + "ERROR: The event2 log includes digest hash mask 0x%x, but required digest hash mask is 0x%x\n", + HashAlgorithmMaskCopied, + mTcgDxeData.BsCap.ActivePcrBanks + )); + } + + // + // Restore event size. + // + CopyMem (EventSizePtr, &EventSize, sizeof (UINT32)); + DigestListBinSize = GetDigestListBinSize (DigestListBin); + + Status = TcgDxeLogEvent ( + mTcg2EventInfo[Index].LogFormat, + TcgEvent, + sizeof (TCG_PCRINDEX) + sizeof (TCG_EVENTTYPE) + DigestListBinSize + sizeof (UINT32), + Event, + EventSize + ); + break; + } + + FreePool (TcgEvent); + } + } + } + + return Status; +} + +/** + Measure and log an action string, and extend the measurement result into PCR[PCRIndex]. + + @param[in] PCRIndex PCRIndex to extend + @param[in] String A specific string that indicates an Action event. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +TcgMeasureAction ( + IN TPM_PCRINDEX PCRIndex, + IN CHAR8 *String + ) +{ + TCG_PCR_EVENT_HDR TcgEvent; + + TcgEvent.PCRIndex = PCRIndex; + TcgEvent.EventType = EV_EFI_ACTION; + TcgEvent.EventSize = (UINT32)AsciiStrLen (String); + return TcgDxeHashLogExtendEvent ( + 0, + (UINT8 *)String, + TcgEvent.EventSize, + &TcgEvent, + (UINT8 *)String + ); +} + +/** + Measure and log EFI handoff tables, and extend the measurement result into PCR[1]. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +MeasureHandoffTables ( + VOID + ) +{ + EFI_STATUS Status; + TCG_PCR_EVENT_HDR TcgEvent; + EFI_HANDOFF_TABLE_POINTERS HandoffTables; + UINTN ProcessorNum; + EFI_CPU_PHYSICAL_LOCATION *ProcessorLocBuf; + + ProcessorLocBuf = NULL; + Status = EFI_SUCCESS; + + if (PcdGet8 (PcdTpmPlatformClass) == TCG_PLATFORM_TYPE_SERVER) { + // + // Tcg Server spec. + // Measure each processor EFI_CPU_PHYSICAL_LOCATION with EV_TABLE_OF_DEVICES to PCR[1] + // + Status = GetProcessorsCpuLocation (&ProcessorLocBuf, &ProcessorNum); + + if (!EFI_ERROR (Status)) { + TcgEvent.PCRIndex = 1; + TcgEvent.EventType = EV_TABLE_OF_DEVICES; + TcgEvent.EventSize = sizeof (HandoffTables); + + HandoffTables.NumberOfTables = 1; + HandoffTables.TableEntry[0].VendorGuid = gEfiMpServiceProtocolGuid; + HandoffTables.TableEntry[0].VendorTable = ProcessorLocBuf; + + Status = TcgDxeHashLogExtendEvent ( + 0, + (UINT8 *)(UINTN)ProcessorLocBuf, + sizeof (EFI_CPU_PHYSICAL_LOCATION) * ProcessorNum, + &TcgEvent, + (UINT8 *)&HandoffTables + ); + + FreePool (ProcessorLocBuf); + } + } + + return Status; +} + +/** + Measure and log Separator event, and extend the measurement result into a specific PCR. + + @param[in] PCRIndex PCR index. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +MeasureSeparatorEvent ( + IN TPM_PCRINDEX PCRIndex + ) +{ + TCG_PCR_EVENT_HDR TcgEvent; + UINT32 EventData; + + DEBUG ((DEBUG_INFO, "MeasureSeparatorEvent Pcr - %x\n", PCRIndex)); + + EventData = 0; + TcgEvent.PCRIndex = PCRIndex; + TcgEvent.EventType = EV_SEPARATOR; + TcgEvent.EventSize = (UINT32)sizeof (EventData); + return TcgDxeHashLogExtendEvent ( + 0, + (UINT8 *)&EventData, + sizeof (EventData), + &TcgEvent, + (UINT8 *)&EventData + ); +} + +/** + Measure and log an EFI variable, and extend the measurement result into a specific PCR. + + @param[in] PCRIndex PCR Index. + @param[in] EventType Event type. + @param[in] VarName A Null-terminated string that is the name of the vendor's variable. + @param[in] VendorGuid A unique identifier for the vendor. + @param[in] VarData The content of the variable data. + @param[in] VarSize The size of the variable data. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +MeasureVariable ( + IN TPM_PCRINDEX PCRIndex, + IN TCG_EVENTTYPE EventType, + IN CHAR16 *VarName, + IN EFI_GUID *VendorGuid, + IN VOID *VarData, + IN UINTN VarSize + ) +{ + EFI_STATUS Status; + TCG_PCR_EVENT_HDR TcgEvent; + UINTN VarNameLength; + UEFI_VARIABLE_DATA *VarLog; + + DEBUG ((DEBUG_INFO, "Tcg2Dxe: MeasureVariable (Pcr - %x, EventType - %x, ", (UINTN)PCRIndex, (UINTN)EventType)); + DEBUG ((DEBUG_INFO, "VariableName - %s, VendorGuid - %g)\n", VarName, VendorGuid)); + + VarNameLength = StrLen (VarName); + TcgEvent.PCRIndex = PCRIndex; + TcgEvent.EventType = EventType; + + TcgEvent.EventSize = (UINT32)(sizeof (*VarLog) + VarNameLength * sizeof (*VarName) + VarSize + - sizeof (VarLog->UnicodeName) - sizeof (VarLog->VariableData)); + + VarLog = (UEFI_VARIABLE_DATA *)AllocatePool (TcgEvent.EventSize); + if (VarLog == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + VarLog->VariableName = *VendorGuid; + VarLog->UnicodeNameLength = VarNameLength; + VarLog->VariableDataLength = VarSize; + CopyMem ( + VarLog->UnicodeName, + VarName, + VarNameLength * sizeof (*VarName) + ); + if ((VarSize != 0) && (VarData != NULL)) { + CopyMem ( + (CHAR16 *)VarLog->UnicodeName + VarNameLength, + VarData, + VarSize + ); + } + + if (EventType == EV_EFI_VARIABLE_DRIVER_CONFIG) { + // + // Digest is the event data (UEFI_VARIABLE_DATA) + // + Status = TcgDxeHashLogExtendEvent ( + 0, + (UINT8 *)VarLog, + TcgEvent.EventSize, + &TcgEvent, + (UINT8 *)VarLog + ); + } else { + ASSERT (VarData != NULL); + Status = TcgDxeHashLogExtendEvent ( + 0, + (UINT8 *)VarData, + VarSize, + &TcgEvent, + (UINT8 *)VarLog + ); + } + + FreePool (VarLog); + return Status; +} + +/** + Read then Measure and log an EFI variable, and extend the measurement result into a specific PCR. + + @param[in] PCRIndex PCR Index. + @param[in] EventType Event type. + @param[in] VarName A Null-terminated string that is the name of the vendor's variable. + @param[in] VendorGuid A unique identifier for the vendor. + @param[out] VarSize The size of the variable data. + @param[out] VarData Pointer to the content of the variable. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +ReadAndMeasureVariable ( + IN TPM_PCRINDEX PCRIndex, + IN TCG_EVENTTYPE EventType, + IN CHAR16 *VarName, + IN EFI_GUID *VendorGuid, + OUT UINTN *VarSize, + OUT VOID **VarData + ) +{ + EFI_STATUS Status; + + Status = GetVariable2 (VarName, VendorGuid, VarData, VarSize); + if (EventType == EV_EFI_VARIABLE_DRIVER_CONFIG) { + if (EFI_ERROR (Status)) { + // + // It is valid case, so we need handle it. + // + *VarData = NULL; + *VarSize = 0; + } + } else { + // + // if status error, VarData is freed and set NULL by GetVariable2 + // + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + } + + Status = MeasureVariable ( + PCRIndex, + EventType, + VarName, + VendorGuid, + *VarData, + *VarSize + ); + return Status; +} + +/** + Read then Measure and log an EFI boot variable, and extend the measurement result into PCR[1]. +according to TCG PC Client PFP spec 0021 Section 2.4.4.2 + + @param[in] VarName A Null-terminated string that is the name of the vendor's variable. + @param[in] VendorGuid A unique identifier for the vendor. + @param[out] VarSize The size of the variable data. + @param[out] VarData Pointer to the content of the variable. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +ReadAndMeasureBootVariable ( + IN CHAR16 *VarName, + IN EFI_GUID *VendorGuid, + OUT UINTN *VarSize, + OUT VOID **VarData + ) +{ + return ReadAndMeasureVariable ( + 1, + EV_EFI_VARIABLE_BOOT, + VarName, + VendorGuid, + VarSize, + VarData + ); +} + +/** + Read then Measure and log an EFI Secure variable, and extend the measurement result into PCR[7]. + + @param[in] VarName A Null-terminated string that is the name of the vendor's variable. + @param[in] VendorGuid A unique identifier for the vendor. + @param[out] VarSize The size of the variable data. + @param[out] VarData Pointer to the content of the variable. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +ReadAndMeasureSecureVariable ( + IN CHAR16 *VarName, + IN EFI_GUID *VendorGuid, + OUT UINTN *VarSize, + OUT VOID **VarData + ) +{ + return ReadAndMeasureVariable ( + 7, + EV_EFI_VARIABLE_DRIVER_CONFIG, + VarName, + VendorGuid, + VarSize, + VarData + ); +} + +/** + Measure and log all EFI boot variables, and extend the measurement result into a specific PCR. + + The EFI boot variables are BootOrder and Boot#### variables. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +MeasureAllBootVariables ( + VOID + ) +{ + EFI_STATUS Status; + UINT16 *BootOrder; + UINTN BootCount; + UINTN Index; + VOID *BootVarData; + UINTN Size; + + Status = ReadAndMeasureBootVariable ( + mBootVarName, + &gEfiGlobalVariableGuid, + &BootCount, + (VOID **)&BootOrder + ); + if ((Status == EFI_NOT_FOUND) || (BootOrder == NULL)) { + return EFI_SUCCESS; + } + + if (EFI_ERROR (Status)) { + // + // BootOrder can't be NULL if status is not EFI_NOT_FOUND + // + FreePool (BootOrder); + return Status; + } + + BootCount /= sizeof (*BootOrder); + for (Index = 0; Index < BootCount; Index++) { + UnicodeSPrint (mBootVarName, sizeof (mBootVarName), L"Boot%04x", BootOrder[Index]); + Status = ReadAndMeasureBootVariable ( + mBootVarName, + &gEfiGlobalVariableGuid, + &Size, + &BootVarData + ); + if (!EFI_ERROR (Status)) { + FreePool (BootVarData); + } + } + + FreePool (BootOrder); + return EFI_SUCCESS; +} + +/** + Measure and log all EFI Secure variables, and extend the measurement result into a specific PCR. + + The EFI boot variables are BootOrder and Boot#### variables. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +MeasureAllSecureVariables ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Data; + UINTN DataSize; + UINTN Index; + + Status = EFI_NOT_FOUND; + for (Index = 0; Index < sizeof (mVariableType)/sizeof (mVariableType[0]); Index++) { + Status = ReadAndMeasureSecureVariable ( + mVariableType[Index].VariableName, + mVariableType[Index].VendorGuid, + &DataSize, + &Data + ); + if (!EFI_ERROR (Status)) { + if (Data != NULL) { + FreePool (Data); + } + } + } + + // + // Measure DBT if present and not empty + // + Status = GetVariable2 (EFI_IMAGE_SECURITY_DATABASE2, &gEfiImageSecurityDatabaseGuid, &Data, &DataSize); + if (!EFI_ERROR (Status)) { + Status = MeasureVariable ( + 7, + EV_EFI_VARIABLE_DRIVER_CONFIG, + EFI_IMAGE_SECURITY_DATABASE2, + &gEfiImageSecurityDatabaseGuid, + Data, + DataSize + ); + FreePool (Data); + } else { + DEBUG ((DEBUG_INFO, "Skip measuring variable %s since it's deleted\n", EFI_IMAGE_SECURITY_DATABASE2)); + } + + return EFI_SUCCESS; +} + +/** + Measure and log launch of FirmwareDebugger, and extend the measurement result into a specific PCR. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Out of memory. + @retval EFI_DEVICE_ERROR The operation was unsuccessful. + +**/ +EFI_STATUS +MeasureLaunchOfFirmwareDebugger ( + VOID + ) +{ + TCG_PCR_EVENT_HDR TcgEvent; + + TcgEvent.PCRIndex = 7; + TcgEvent.EventType = EV_EFI_ACTION; + TcgEvent.EventSize = sizeof (FIRMWARE_DEBUGGER_EVENT_STRING) - 1; + return TcgDxeHashLogExtendEvent ( + 0, + (UINT8 *)FIRMWARE_DEBUGGER_EVENT_STRING, + sizeof (FIRMWARE_DEBUGGER_EVENT_STRING) - 1, + &TcgEvent, + (UINT8 *)FIRMWARE_DEBUGGER_EVENT_STRING + ); +} + +/** + Measure and log all Secure Boot Policy, and extend the measurement result into a specific PCR. + + Platform firmware adhering to the policy must therefore measure the following values into PCR[7]: (in order listed) + - The contents of the SecureBoot variable + - The contents of the PK variable + - The contents of the KEK variable + - The contents of the EFI_IMAGE_SECURITY_DATABASE variable + - The contents of the EFI_IMAGE_SECURITY_DATABASE1 variable + - Separator + - Entries in the EFI_IMAGE_SECURITY_DATABASE that are used to validate EFI Drivers or EFI Boot Applications in the boot path + + NOTE: Because of the above, UEFI variables PK, KEK, EFI_IMAGE_SECURITY_DATABASE, + EFI_IMAGE_SECURITY_DATABASE1 and SecureBoot SHALL NOT be measured into PCR[3]. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context +**/ +VOID +EFIAPI +MeasureSecureBootPolicy ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *Protocol; + + Status = gBS->LocateProtocol (&gEfiVariableWriteArchProtocolGuid, NULL, (VOID **)&Protocol); + if (EFI_ERROR (Status)) { + return; + } + + if (PcdGetBool (PcdFirmwareDebuggerInitialized)) { + Status = MeasureLaunchOfFirmwareDebugger (); + DEBUG ((DEBUG_INFO, "MeasureLaunchOfFirmwareDebugger - %r\n", Status)); + } + + Status = MeasureAllSecureVariables (); + DEBUG ((DEBUG_INFO, "MeasureAllSecureVariables - %r\n", Status)); + + // + // We need measure Separator(7) here, because this event must be between SecureBootPolicy (Configure) + // and ImageVerification (Authority) + // There might be a case that we need measure UEFI image from DriverOrder, besides BootOrder. So + // the Authority measurement happen before ReadToBoot event. + // + Status = MeasureSeparatorEvent (7); + DEBUG ((DEBUG_INFO, "MeasureSeparatorEvent - %r\n", Status)); + return; +} + +/** + Ready to Boot Event notification handler. + + Sequence of OS boot events is measured in this event notification handler. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context + +**/ +VOID +EFIAPI +OnReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + TPM_PCRINDEX PcrIndex; + + PERF_START_EX (mImageHandle, "EventRec", "Tcg2Dxe", 0, PERF_ID_TCG2_DXE); + if (mBootAttempts == 0) { + // + // Measure handoff tables. + // + Status = MeasureHandoffTables (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "HOBs not Measured. Error!\n")); + } + + // + // Measure BootOrder & Boot#### variables. + // + Status = MeasureAllBootVariables (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Boot Variables not Measured. Error!\n")); + } + + // + // 1. This is the first boot attempt. + // + Status = TcgMeasureAction ( + 4, + EFI_CALLING_EFI_APPLICATION + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a not Measured. Error!\n", EFI_CALLING_EFI_APPLICATION)); + } + + // + // 2. Draw a line between pre-boot env and entering post-boot env. + // PCR[7] is already done. + // + for (PcrIndex = 0; PcrIndex < 7; PcrIndex++) { + Status = MeasureSeparatorEvent (PcrIndex); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Separator Event not Measured. Error!\n")); + } + } + + // + // 3. Measure GPT. It would be done in SAP driver. + // + + // + // 4. Measure PE/COFF OS loader. It would be done in SAP driver. + // + + // + // 5. Read & Measure variable. BootOrder already measured. + // + } else { + // + // 6. Not first attempt, meaning a return from last attempt + // + Status = TcgMeasureAction ( + 4, + EFI_RETURNING_FROM_EFI_APPLICATION + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a not Measured. Error!\n", EFI_RETURNING_FROM_EFI_APPLICATION)); + } + + // + // 7. Next boot attempt, measure "Calling EFI Application from Boot Option" again + // TCG PC Client PFP spec Section 2.4.4.5 Step 4 + // + Status = TcgMeasureAction ( + 4, + EFI_CALLING_EFI_APPLICATION + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a not Measured. Error!\n", EFI_CALLING_EFI_APPLICATION)); + } + } + + DEBUG ((DEBUG_INFO, "TPM2 Tcg2Dxe Measure Data when ReadyToBoot\n")); + // + // Increase boot attempt counter. + // + mBootAttempts++; + PERF_END_EX (mImageHandle, "EventRec", "Tcg2Dxe", 0, PERF_ID_TCG2_DXE + 1); +} + +/** + Exit Boot Services Event notification handler. + + Measure invocation and success of ExitBootServices. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context + +**/ +VOID +EFIAPI +OnExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + // + // Measure invocation of ExitBootServices, + // + Status = TcgMeasureAction ( + 5, + EFI_EXIT_BOOT_SERVICES_INVOCATION + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a not Measured. Error!\n", EFI_EXIT_BOOT_SERVICES_INVOCATION)); + } + + // + // Measure success of ExitBootServices + // + Status = TcgMeasureAction ( + 5, + EFI_EXIT_BOOT_SERVICES_SUCCEEDED + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a not Measured. Error!\n", EFI_EXIT_BOOT_SERVICES_SUCCEEDED)); + } +} + +/** + Exit Boot Services Failed Event notification handler. + + Measure Failure of ExitBootServices. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context + +**/ +VOID +EFIAPI +OnExitBootServicesFailed ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + // + // Measure Failure of ExitBootServices, + // + Status = TcgMeasureAction ( + 5, + EFI_EXIT_BOOT_SERVICES_FAILED + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a not Measured. Error!\n", EFI_EXIT_BOOT_SERVICES_FAILED)); + } +} + +/** + This routine is called to properly shutdown the TPM before system reset. + It follow chapter "12.2.3 Startup State" in Trusted Platform Module Library + Part 1: Architecture, Revision 01.16. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or + EfiResetShutdown the data buffer starts with a Null-terminated + string, optionally followed by additional binary data. + The string is a description that the caller may use to further + indicate the reason for the system reset. + For a ResetType of EfiResetPlatformSpecific the data buffer + also starts with a Null-terminated string that is followed + by an EFI_GUID that describes the specific type of reset to perform. +**/ +VOID +EFIAPI +ShutdownTpmOnReset ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + EFI_STATUS Status; + + Status = Tpm2Shutdown (TPM_SU_CLEAR); + DEBUG ((DEBUG_VERBOSE, "Tpm2Shutdown (SU_CLEAR) - %r\n", Status)); +} + +/** + Hook the system reset to properly shutdown TPM. + It follow chapter "12.2.3 Startup State" in Trusted Platform Module Library + Part 1: Architecture, Revision 01.16. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context +**/ +VOID +EFIAPI +OnResetNotificationInstall ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify; + + Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify); + if (!EFI_ERROR (Status)) { + Status = ResetNotify->RegisterResetNotify (ResetNotify, ShutdownTpmOnReset); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_VERBOSE, "TCG2: Hook system reset to properly shutdown TPM.\n")); + + gBS->CloseEvent (Event); + } +} + +/** + The function install Tcg2 protocol. + + @retval EFI_SUCCESS Tcg2 protocol is installed. + @retval other Some error occurs. +**/ +EFI_STATUS +InstallTcg2 ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiTcg2ProtocolGuid, + &mTcg2Protocol, + NULL + ); + return Status; +} + +/** + The driver's entry point. It publishes EFI Tcg2 Protocol. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. +**/ +EFI_STATUS +EFIAPI +DriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + VOID *Registration; + UINT32 MaxCommandSize; + UINT32 MaxResponseSize; + UINTN Index; + EFI_TCG2_EVENT_ALGORITHM_BITMAP TpmHashAlgorithmBitmap; + UINT32 ActivePCRBanks; + UINT32 NumberOfPCRBanks; + + mImageHandle = ImageHandle; + + if (CompareGuid (PcdGetPtr (PcdTpmInstanceGuid), &gEfiTpmDeviceInstanceNoneGuid) || + CompareGuid (PcdGetPtr (PcdTpmInstanceGuid), &gEfiTpmDeviceInstanceTpm12Guid)) + { + DEBUG ((DEBUG_INFO, "No TPM2 instance required!\n")); + return EFI_UNSUPPORTED; + } + + if (GetFirstGuidHob (&gTpmErrorHobGuid) != NULL) { + DEBUG ((DEBUG_ERROR, "TPM2 error!\n")); + return EFI_DEVICE_ERROR; + } + + Status = Tpm2RequestUseTpm (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "TPM2 not detected!\n")); + return Status; + } + + // + // Fill information + // + ASSERT (TCG_EVENT_LOG_AREA_COUNT_MAX == sizeof (mTcg2EventInfo)/sizeof (mTcg2EventInfo[0])); + + mTcgDxeData.BsCap.Size = sizeof (EFI_TCG2_BOOT_SERVICE_CAPABILITY); + mTcgDxeData.BsCap.ProtocolVersion.Major = 1; + mTcgDxeData.BsCap.ProtocolVersion.Minor = 1; + mTcgDxeData.BsCap.StructureVersion.Major = 1; + mTcgDxeData.BsCap.StructureVersion.Minor = 1; + + DEBUG ((DEBUG_INFO, "Tcg2.ProtocolVersion - %02x.%02x\n", mTcgDxeData.BsCap.ProtocolVersion.Major, mTcgDxeData.BsCap.ProtocolVersion.Minor)); + DEBUG ((DEBUG_INFO, "Tcg2.StructureVersion - %02x.%02x\n", mTcgDxeData.BsCap.StructureVersion.Major, mTcgDxeData.BsCap.StructureVersion.Minor)); + + Status = Tpm2GetCapabilityManufactureID (&mTcgDxeData.BsCap.ManufacturerID); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityManufactureID fail!\n")); + } else { + DEBUG ((DEBUG_INFO, "Tpm2GetCapabilityManufactureID - %08x\n", mTcgDxeData.BsCap.ManufacturerID)); + } + + DEBUG_CODE_BEGIN (); + UINT32 FirmwareVersion1; + UINT32 FirmwareVersion2; + + Status = Tpm2GetCapabilityFirmwareVersion (&FirmwareVersion1, &FirmwareVersion2); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityFirmwareVersion fail!\n")); + } else { + DEBUG ((DEBUG_INFO, "Tpm2GetCapabilityFirmwareVersion - %08x %08x\n", FirmwareVersion1, FirmwareVersion2)); + } + + DEBUG_CODE_END (); + + Status = Tpm2GetCapabilityMaxCommandResponseSize (&MaxCommandSize, &MaxResponseSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityMaxCommandResponseSize fail!\n")); + } else { + mTcgDxeData.BsCap.MaxCommandSize = (UINT16)MaxCommandSize; + mTcgDxeData.BsCap.MaxResponseSize = (UINT16)MaxResponseSize; + DEBUG ((DEBUG_INFO, "Tpm2GetCapabilityMaxCommandResponseSize - %08x, %08x\n", MaxCommandSize, MaxResponseSize)); + } + + // + // Get supported PCR and current Active PCRs + // + Status = Tpm2GetCapabilitySupportedAndActivePcrs (&TpmHashAlgorithmBitmap, &ActivePCRBanks); + ASSERT_EFI_ERROR (Status); + + mTcgDxeData.BsCap.HashAlgorithmBitmap = TpmHashAlgorithmBitmap & PcdGet32 (PcdTcg2HashAlgorithmBitmap); + mTcgDxeData.BsCap.ActivePcrBanks = ActivePCRBanks & PcdGet32 (PcdTcg2HashAlgorithmBitmap); + + // + // Need calculate NumberOfPCRBanks here, because HashAlgorithmBitmap might be removed by PCD. + // + NumberOfPCRBanks = 0; + for (Index = 0; Index < 32; Index++) { + if ((mTcgDxeData.BsCap.HashAlgorithmBitmap & (1u << Index)) != 0) { + NumberOfPCRBanks++; + } + } + + if (PcdGet32 (PcdTcg2NumberOfPCRBanks) == 0) { + mTcgDxeData.BsCap.NumberOfPCRBanks = NumberOfPCRBanks; + } else { + mTcgDxeData.BsCap.NumberOfPCRBanks = PcdGet32 (PcdTcg2NumberOfPCRBanks); + if (PcdGet32 (PcdTcg2NumberOfPCRBanks) > NumberOfPCRBanks) { + DEBUG ((DEBUG_ERROR, "ERROR: PcdTcg2NumberOfPCRBanks(0x%x) > NumberOfPCRBanks(0x%x)\n", PcdGet32 (PcdTcg2NumberOfPCRBanks), NumberOfPCRBanks)); + mTcgDxeData.BsCap.NumberOfPCRBanks = NumberOfPCRBanks; + } + } + + mTcgDxeData.BsCap.SupportedEventLogs = EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 | EFI_TCG2_EVENT_LOG_FORMAT_TCG_2; + if ((mTcgDxeData.BsCap.ActivePcrBanks & EFI_TCG2_BOOT_HASH_ALG_SHA1) == 0) { + // + // No need to expose TCG1.2 event log if SHA1 bank does not exist. + // + mTcgDxeData.BsCap.SupportedEventLogs &= ~EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2; + } + + DEBUG ((DEBUG_INFO, "Tcg2.SupportedEventLogs - 0x%08x\n", mTcgDxeData.BsCap.SupportedEventLogs)); + DEBUG ((DEBUG_INFO, "Tcg2.HashAlgorithmBitmap - 0x%08x\n", mTcgDxeData.BsCap.HashAlgorithmBitmap)); + DEBUG ((DEBUG_INFO, "Tcg2.NumberOfPCRBanks - 0x%08x\n", mTcgDxeData.BsCap.NumberOfPCRBanks)); + DEBUG ((DEBUG_INFO, "Tcg2.ActivePcrBanks - 0x%08x\n", mTcgDxeData.BsCap.ActivePcrBanks)); + + if (mTcgDxeData.BsCap.TPMPresentFlag) { + // + // Setup the log area and copy event log from hob list to it + // + Status = SetupEventLog (); + ASSERT_EFI_ERROR (Status); + + // + // Measure handoff tables, Boot#### variables etc. + // + Status = EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + OnReadyToBoot, + NULL, + &Event + ); + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + OnExitBootServices, + NULL, + &gEfiEventExitBootServicesGuid, + &Event + ); + + // + // Measure Exit Boot Service failed + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + OnExitBootServicesFailed, + NULL, + &gEventExitBootServicesFailedGuid, + &Event + ); + + // + // Create event callback, because we need access variable on SecureBootPolicyVariable + // We should use VariableWriteArch instead of VariableArch, because Variable driver + // may update SecureBoot value based on last setting. + // + EfiCreateProtocolNotifyEvent (&gEfiVariableWriteArchProtocolGuid, TPL_CALLBACK, MeasureSecureBootPolicy, NULL, &Registration); + + // + // Hook the system reset to properly shutdown TPM. + // + EfiCreateProtocolNotifyEvent (&gEfiResetNotificationProtocolGuid, TPL_CALLBACK, OnResetNotificationInstall, NULL, &Registration); + } + + // + // Install Tcg2Protocol + // + Status = InstallTcg2 (); + DEBUG ((DEBUG_INFO, "InstallTcg2 - %r\n", Status)); + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf b/Platform/AMD/TurinBoard/Override/edk2/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..0a468887d8d366d39a13d7b22412a8d7c0a1e1b1 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf @@ -0,0 +1,124 @@ +## @file +# Produces Tcg2 protocol and measure boot environment +# +# Spec Compliance Info: +# "TCG PC Client Platform Firmware Profile Specification for TPM Family 2.0 Level 00 Revision 1.03 v51" +# along with +# "Errata for PC Client Specific Platform Firmware Profile Specification Version 1.0 Revision 1.03" +# "TCG EFI Protocol Specification" "Family 2.0" "Level 00 Revision 00.13" +# along with +# "Errata Version 0.5 for TCG EFI Protocol Specification" +# +# This module will produce Tcg2 protocol and measure boot environment. +# +# Caution: This module requires additional review when modified. +# This driver will have external input - PE/COFF image. +# This external input must be validated carefully to avoid security issue like +# buffer overflow, integer overflow. +# +# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Tcg2Dxe + MODULE_UNI_FILE = Tcg2Dxe.uni + FILE_GUID = FDFF263D-5F68-4591-87BA-B768F445A9AF + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DriverEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + Tcg2Dxe.c + MeasureBootPeCoff.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + CryptoPkg/CryptoPkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModulePspPkg.dec + +[LibraryClasses] + MemoryAllocationLib + BaseLib + UefiBootServicesTableLib + HobLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + BaseMemoryLib + DebugLib + Tpm2CommandLib + PrintLib + UefiLib + Tpm2DeviceLib + HashLib + PerformanceLib + ReportStatusCodeLib + Tcg2PhysicalPresenceLib + PeCoffLib + AmdPspMboxLibV2 + +[Guids] + ## SOMETIMES_CONSUMES ## Variable:L"SecureBoot" + ## SOMETIMES_CONSUMES ## Variable:L"PK" + ## SOMETIMES_CONSUMES ## Variable:L"KEK" + ## SOMETIMES_CONSUMES ## Variable:L"BootXXXX" + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## Variable:L"db" + ## SOMETIMES_CONSUMES ## Variable:L"dbx" + gEfiImageSecurityDatabaseGuid + + gTcgEventEntryHobGuid ## SOMETIMES_CONSUMES ## HOB + gTpmErrorHobGuid ## SOMETIMES_CONSUMES ## HOB + gEfiEventExitBootServicesGuid ## CONSUMES ## Event + gEventExitBootServicesFailedGuid ## SOMETIMES_CONSUMES ## Event + gEfiTpmDeviceInstanceNoneGuid ## SOMETIMES_CONSUMES ## GUID # TPM device identifier + gEfiTpmDeviceInstanceTpm12Guid ## SOMETIMES_CONSUMES ## GUID # TPM device identifier + + gTcgEvent2EntryHobGuid ## SOMETIMES_CONSUMES ## HOB + gTpm2StartupLocalityHobGuid ## SOMETIMES_CONSUMES ## HOB + gTcg800155PlatformIdEventHobGuid ## SOMETIMES_CONSUMES ## HOB + +[Protocols] + gEfiTcg2ProtocolGuid ## PRODUCES + gEfiTcg2FinalEventsTableGuid ## PRODUCES + gEfiMpServiceProtocolGuid ## SOMETIMES_CONSUMES + gEfiVariableWriteArchProtocolGuid ## NOTIFY + gEfiResetNotificationProtocolGuid ## CONSUMES + +[Pcd] + gEfiSecurityPkgTokenSpaceGuid.PcdTpmPlatformClass ## SOMETIMES_CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdFirmwareDebuggerInitialized ## SOMETIMES_CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeSubClassTpmDevice ## SOMETIMES_CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2NumberOfPCRBanks ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTcgLogAreaMinLen ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2FinalLogAreaLen ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableLaml ## PRODUCES + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableLasa ## PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdTcgPfpMeasurementRevision ## CONSUMES + +[Depex] + # According to PcdTpm2AcpiTableRev definition in SecurityPkg.dec + # This PCD should be configured at DynamicHii or DynamicHiiEx. + # So, this PCD read operation depends on GetVariable service. + # Add VariableArch protocol dependency to make sure PCD read works. + gEfiVariableArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + Tcg2DxeExtra.uni diff --git a/Platform/AMD/TurinBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/Platform/AMD/TurinBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c new file mode 100644 index 0000000000000000000000000000000000000000..a432f000b2d355972dc12b3f2c3d8e69d2cdf158 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -0,0 +1,2023 @@ +/** @file +Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. + +Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PiSmmCpuDxeSmm.h" + +// +// SMM CPU Private Data structure that contains SMM Configuration Protocol +// along its supporting fields. +// +SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = { + SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature + NULL, // SmmCpuHandle + NULL, // Pointer to ProcessorInfo array + NULL, // Pointer to Operation array + NULL, // Pointer to CpuSaveStateSize array + NULL, // Pointer to CpuSaveState array + { + { 0 } + }, // SmmReservedSmramRegion + { + SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp + 0, // SmmCoreEntryContext.CurrentlyExecutingCpu + 0, // SmmCoreEntryContext.NumberOfCpus + NULL, // SmmCoreEntryContext.CpuSaveStateSize + NULL // SmmCoreEntryContext.CpuSaveState + }, + NULL, // SmmCoreEntry + { + mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions + RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry + }, + NULL, // pointer to Ap Wrapper Func array + { NULL, NULL }, // List_Entry for Tokens. +}; + +CPU_HOT_PLUG_DATA mCpuHotPlugData = { + CPU_HOT_PLUG_DATA_REVISION_1, // Revision + 0, // Array Length of SmBase and APIC ID + NULL, // Pointer to APIC ID array + NULL, // Pointer to SMBASE array + 0, // Reserved + 0, // SmrrBase + 0 // SmrrSize +}; + +// +// Global pointer used to access mSmmCpuPrivateData from outside and inside SMM +// +SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData; + +// +// SMM Relocation variables +// +volatile BOOLEAN *mRebased; + +/// +/// Handle for the SMM CPU Protocol +/// +EFI_HANDLE mSmmCpuHandle = NULL; + +/// +/// SMM CPU Protocol instance +/// +EFI_SMM_CPU_PROTOCOL mSmmCpu = { + SmmReadSaveState, + SmmWriteSaveState +}; + +/// +/// SMM Memory Attribute Protocol instance +/// +EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = { + EdkiiSmmGetMemoryAttributes, + EdkiiSmmSetMemoryAttributes, + EdkiiSmmClearMemoryAttributes +}; + +EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; + +BOOLEAN mSmmRelocated = FALSE; +volatile BOOLEAN *mSmmInitialized = NULL; +UINT32 mBspApicId = 0; + +// +// SMM stack information +// +UINTN mSmmStackArrayBase; +UINTN mSmmStackArrayEnd; +UINTN mSmmStackSize; + +UINTN mSmmShadowStackSize; +BOOLEAN mCetSupported = TRUE; + +UINTN mMaxNumberOfCpus = 0; +UINTN mNumberOfCpus = 0; + +// +// SMM ready to lock flag +// +BOOLEAN mSmmReadyToLock = FALSE; + +// +// Global used to cache PCD for SMM Code Access Check enable +// +BOOLEAN mSmmCodeAccessCheckEnable = FALSE; + +// +// Global used to cache SMM Debug Agent Supported ot not +// +BOOLEAN mSmmDebugAgentSupport = FALSE; + +// +// Global copy of the PcdPteMemoryEncryptionAddressOrMask +// +UINT64 mAddressEncMask = 0; + +// +// Spin lock used to serialize setting of SMM Code Access Check feature +// +SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; + +// +// Saved SMM ranges information +// +EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; +UINTN mSmmCpuSmramRangeCount; + +UINT8 mPhysicalAddressBits; + +// +// Control register contents saved for SMM S3 resume state initialization. +// +UINT32 mSmmCr0; +UINT32 mSmmCr4; + +/** + Initialize IDT to setup exception handlers for SMM. + +**/ +VOID +InitializeSmmIdt ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN InterruptState; + IA32_DESCRIPTOR DxeIdtr; + + // + // There are 32 (not 255) entries in it since only processor + // generated exceptions will be handled. + // + gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; + // + // Allocate page aligned IDT, because it might be set as read only. + // + gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1)); + ASSERT (gcSmiIdtr.Base != 0); + ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1); + + // + // Disable Interrupt and save DXE IDT table + // + InterruptState = SaveAndDisableInterrupts (); + AsmReadIdtr (&DxeIdtr); + // + // Load SMM temporary IDT table + // + AsmWriteIdtr (&gcSmiIdtr); + // + // Setup SMM default exception handlers, SMM IDT table + // will be updated and saved in gcSmiIdtr + // + Status = InitializeCpuExceptionHandlers (NULL); + ASSERT_EFI_ERROR (Status); + // + // Restore DXE IDT table and CPU interrupt + // + AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr); + SetInterruptState (InterruptState); +} + +/** + Search module name by input IP address and output it. + + @param CallerIpAddress Caller instruction pointer. + +**/ +VOID +DumpModuleInfoByIp ( + IN UINTN CallerIpAddress + ) +{ + UINTN Pe32Data; + VOID *PdbPointer; + + // + // Find Image Base + // + Pe32Data = PeCoffSearchImageBase (CallerIpAddress); + if (Pe32Data != 0) { + DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress)); + PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data); + if (PdbPointer != NULL) { + DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer)); + } + } +} + +/** + Read information from the CPU save state. + + @param This EFI_SMM_CPU_PROTOCOL instance + @param Width The number of bytes to read from the CPU save state. + @param Register Specifies the CPU register to read form the save state. + @param CpuIndex Specifies the zero-based index of the CPU save state. + @param Buffer Upon return, this holds the CPU register value read from the save state. + + @retval EFI_SUCCESS The register was read from Save State + @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor + @retval EFI_INVALID_PARAMETER This or Buffer is NULL. + +**/ +EFI_STATUS +EFIAPI +SmmReadSaveState ( + IN CONST EFI_SMM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + + // + // Retrieve pointer to the specified CPU's SMM Save State buffer + // + if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // The SpeculationBarrier() call here is to ensure the above check for the + // CpuIndex has been completed before the execution of subsequent codes. + // + SpeculationBarrier (); + + // + // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID + // + if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) { + // + // The pseudo-register only supports the 64-bit size specified by Width. + // + if (Width != sizeof (UINT64)) { + return EFI_INVALID_PARAMETER; + } + + // + // If the processor is in SMM at the time the SMI occurred, + // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer. + // Otherwise, EFI_NOT_FOUND is returned. + // + if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) { + *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId; + return EFI_SUCCESS; + } else { + return EFI_NOT_FOUND; + } + } + + if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) { + return EFI_INVALID_PARAMETER; + } + + Status = MmSaveStateReadRegister (CpuIndex, Register, Width, Buffer); + + return Status; +} + +/** + Write data to the CPU save state. + + @param This EFI_SMM_CPU_PROTOCOL instance + @param Width The number of bytes to read from the CPU save state. + @param Register Specifies the CPU register to write to the save state. + @param CpuIndex Specifies the zero-based index of the CPU save state + @param Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written from Save State + @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor + @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not correct + +**/ +EFI_STATUS +EFIAPI +SmmWriteSaveState ( + IN CONST EFI_SMM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + IN CONST VOID *Buffer + ) +{ + EFI_STATUS Status; + + // + // Retrieve pointer to the specified CPU's SMM Save State buffer + // + if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored + // + if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) { + return EFI_SUCCESS; + } + + if (!mSmmMpSyncData->CpuData[CpuIndex].Present) { + return EFI_INVALID_PARAMETER; + } + + Status = MmSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); + + return Status; +} + +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID + ) +{ + UINT32 ApicId; + UINTN Index; + BOOLEAN IsBsp; + + // + // Update SMM IDT entries' code segment and load IDT + // + AsmWriteIdtr (&gcSmiIdtr); + ApicId = GetApicId (); + + IsBsp = (BOOLEAN)(mBspApicId == ApicId); + + ASSERT (mNumberOfCpus <= mMaxNumberOfCpus); + + for (Index = 0; Index < mNumberOfCpus; Index++) { + if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { + PERF_CODE ( + MpPerfBegin (Index, SMM_MP_PERF_PROCEDURE_ID (SmmInitHandler)); + ); + // + // Initialize SMM specific features on the currently executing CPU + // + SmmCpuFeaturesInitializeProcessor ( + Index, + IsBsp, + gSmmCpuPrivate->ProcessorInfo, + &mCpuHotPlugData + ); + + if (!mSmmS3Flag) { + // + // Check XD and BTS features on each processor on normal boot + // + CheckFeatureSupported (); + } else if (IsBsp) { + // + // BSP rebase is already done above. + // Initialize private data during S3 resume + // + InitializeMpSyncData (); + } + + if (!mSmmRelocated) { + // + // Hook return after RSM to set SMM re-based flag + // + SemaphoreHook (Index, &mRebased[Index]); + } + + PERF_CODE ( + MpPerfEnd (Index, SMM_MP_PERF_PROCEDURE_ID (SmmInitHandler)); + ); + + return; + } + } + + ASSERT (FALSE); +} + +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init. + +**/ +VOID +ExecuteFirstSmiInit ( + VOID + ) +{ + UINTN Index; + + PERF_FUNCTION_BEGIN (); + + if (mSmmInitialized == NULL) { + mSmmInitialized = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * mMaxNumberOfCpus); + } + + ASSERT (mSmmInitialized != NULL); + if (mSmmInitialized == NULL) { + PERF_FUNCTION_END (); + return; + } + + // + // Reset the mSmmInitialized to false. + // + ZeroMem ((VOID *)mSmmInitialized, sizeof (BOOLEAN) * mMaxNumberOfCpus); + + // + // Get the BSP ApicId. + // + mBspApicId = GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index = 0; Index < mNumberOfCpus; Index++) { + while (!(BOOLEAN)mSmmInitialized[Index]) { + } + } + + PERF_FUNCTION_END (); +} + +/** + Relocate SmmBases for each processor. + + Execute on first boot and all S3 resumes + +**/ +VOID +EFIAPI +SmmRelocateBases ( + VOID + ) +{ + UINT8 BakBuf[BACK_BUF_SIZE]; + SMRAM_SAVE_STATE_MAP BakBuf2; + SMRAM_SAVE_STATE_MAP *CpuStatePtr; + UINT8 *U8Ptr; + UINTN Index; + UINTN BspIndex; + + PERF_FUNCTION_BEGIN (); + + // + // Make sure the reserved size is large enough for procedure SmmInitTemplate. + // + ASSERT (sizeof (BakBuf) >= gcSmmInitSize); + + // + // Patch ASM code template with current CR0, CR3, and CR4 values + // + mSmmCr0 = (UINT32)AsmReadCr0 (); + PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4); + PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4); + mSmmCr4 = (UINT32)AsmReadCr4 (); + PatchInstructionX86 (gPatchSmmCr4, mSmmCr4 & (~CR4_CET_ENABLE), 4); + + // + // Patch GDTR for SMM base relocation + // + gcSmiInitGdtr.Base = gcSmiGdtr.Base; + gcSmiInitGdtr.Limit = gcSmiGdtr.Limit; + + U8Ptr = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); + CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + + // + // Backup original contents at address 0x38000 + // + CopyMem (BakBuf, U8Ptr, sizeof (BakBuf)); + CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2)); + + // + // Load image for relocation + // + CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize); + + // + // Retrieve the local APIC ID of current processor + // + mBspApicId = GetApicId (); + + // + // Relocate SM bases for all APs + // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate + // + BspIndex = (UINTN)-1; + for (Index = 0; Index < mNumberOfCpus; Index++) { + mRebased[Index] = FALSE; + if (mBspApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) { + SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId); + // + // Wait for this AP to finish its 1st SMI + // + while (!mRebased[Index]) { + } + } else { + // + // BSP will be Relocated later + // + BspIndex = Index; + } + } + + // + // Relocate BSP's SMM base + // + ASSERT (BspIndex != (UINTN)-1); + SendSmiIpi (mBspApicId); + // + // Wait for the BSP to finish its 1st SMI + // + while (!mRebased[BspIndex]) { + } + + // + // Restore contents at address 0x38000 + // + CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2)); + CopyMem (U8Ptr, BakBuf, sizeof (BakBuf)); + PERF_FUNCTION_END (); +} + +/** + SMM Ready To Lock event notification handler. + + The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to + perform additional lock actions that must be performed from SMM on the next SMI. + + @param[in] Protocol Points to the protocol's unique identifier. + @param[in] Interface Points to the interface instance. + @param[in] Handle The handle on which the interface was installed. + + @retval EFI_SUCCESS Notification handler runs successfully. + **/ +EFI_STATUS +EFIAPI +SmmReadyToLockEventNotify ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + GetAcpiCpuData (); + + // + // Cache a copy of UEFI memory map before we start profiling feature. + // + GetUefiMemoryMap (); + + // + // Set SMM ready to lock flag and return + // + mSmmReadyToLock = TRUE; + return EFI_SUCCESS; +} + +/** + Function to compare 2 SMM_BASE_HOB_DATA pointer based on ProcessorIndex. + + @param[in] Buffer1 pointer to SMM_BASE_HOB_DATA poiner to compare + @param[in] Buffer2 pointer to second SMM_BASE_HOB_DATA pointer to compare + + @retval 0 Buffer1 equal to Buffer2 + @retval <0 Buffer1 is less than Buffer2 + @retval >0 Buffer1 is greater than Buffer2 +**/ +INTN +EFIAPI +SmBaseHobCompare ( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 + ) +{ + if ((*(SMM_BASE_HOB_DATA **)Buffer1)->ProcessorIndex > (*(SMM_BASE_HOB_DATA **)Buffer2)->ProcessorIndex) { + return 1; + } else if ((*(SMM_BASE_HOB_DATA **)Buffer1)->ProcessorIndex < (*(SMM_BASE_HOB_DATA **)Buffer2)->ProcessorIndex) { + return -1; + } + + return 0; +} + +/** + Extract SmBase for all CPU from SmmBase HOB. + + @param[in] MaxNumberOfCpus Max NumberOfCpus. + + @param[out] AllocatedSmBaseBuffer Pointer to SmBase Buffer allocated + by this function. Only set if the + function returns EFI_SUCCESS. + + @retval EFI_SUCCESS SmBase Buffer output successfully. + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. + @retval EFI_NOT_FOUND gSmmBaseHobGuid was never created. +**/ +STATIC +EFI_STATUS +GetSmBase ( + IN UINTN MaxNumberOfCpus, + OUT UINTN **AllocatedSmBaseBuffer + ) +{ + UINTN HobCount; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + UINTN NumberOfProcessors; + SMM_BASE_HOB_DATA **SmBaseHobs; + UINTN *SmBaseBuffer; + UINTN HobIndex; + UINTN SortBuffer; + UINTN ProcessorIndex; + UINT64 PrevProcessorIndex; + EFI_HOB_GUID_TYPE *FirstSmmBaseGuidHob; + + SmmBaseHobData = NULL; + HobIndex = 0; + ProcessorIndex = 0; + HobCount = 0; + NumberOfProcessors = 0; + + FirstSmmBaseGuidHob = GetFirstGuidHob (&gSmmBaseHobGuid); + if (FirstSmmBaseGuidHob == NULL) { + return EFI_NOT_FOUND; + } + + GuidHob = FirstSmmBaseGuidHob; + while (GuidHob != NULL) { + HobCount++; + SmmBaseHobData = GET_GUID_HOB_DATA (GuidHob); + NumberOfProcessors += SmmBaseHobData->NumberOfProcessors; + + if (NumberOfProcessors >= MaxNumberOfCpus) { + break; + } + + GuidHob = GetNextGuidHob (&gSmmBaseHobGuid, GET_NEXT_HOB (GuidHob)); + } + + ASSERT (NumberOfProcessors == MaxNumberOfCpus); + if (NumberOfProcessors != MaxNumberOfCpus) { + CpuDeadLoop (); + } + + SmBaseHobs = AllocatePool (sizeof (SMM_BASE_HOB_DATA *) * HobCount); + if (SmBaseHobs == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Record each SmmBaseHob pointer in the SmBaseHobs. + // The FirstSmmBaseGuidHob is to speed up this while-loop + // without needing to look for SmBaseHob from beginning. + // + GuidHob = FirstSmmBaseGuidHob; + while (HobIndex < HobCount) { + SmBaseHobs[HobIndex++] = GET_GUID_HOB_DATA (GuidHob); + GuidHob = GetNextGuidHob (&gSmmBaseHobGuid, GET_NEXT_HOB (GuidHob)); + } + + SmBaseBuffer = (UINTN *)AllocatePool (sizeof (UINTN) * (MaxNumberOfCpus)); + ASSERT (SmBaseBuffer != NULL); + if (SmBaseBuffer == NULL) { + FreePool (SmBaseHobs); + return EFI_OUT_OF_RESOURCES; + } + + QuickSort (SmBaseHobs, HobCount, sizeof (SMM_BASE_HOB_DATA *), (BASE_SORT_COMPARE)SmBaseHobCompare, &SortBuffer); + PrevProcessorIndex = 0; + for (HobIndex = 0; HobIndex < HobCount; HobIndex++) { + // + // Make sure no overlap and no gap in the CPU range covered by each HOB + // + ASSERT (SmBaseHobs[HobIndex]->ProcessorIndex == PrevProcessorIndex); + + // + // Cache each SmBase in order. + // + for (ProcessorIndex = 0; ProcessorIndex < SmBaseHobs[HobIndex]->NumberOfProcessors; ProcessorIndex++) { + SmBaseBuffer[PrevProcessorIndex + ProcessorIndex] = (UINTN)SmBaseHobs[HobIndex]->SmBase[ProcessorIndex]; + } + + PrevProcessorIndex += SmBaseHobs[HobIndex]->NumberOfProcessors; + } + + FreePool (SmBaseHobs); + *AllocatedSmBaseBuffer = SmBaseBuffer; + return EFI_SUCCESS; +} + +/** + Function to compare 2 MP_INFORMATION2_HOB_DATA pointer based on ProcessorIndex. + + @param[in] Buffer1 pointer to MP_INFORMATION2_HOB_DATA poiner to compare + @param[in] Buffer2 pointer to second MP_INFORMATION2_HOB_DATA pointer to compare + + @retval 0 Buffer1 equal to Buffer2 + @retval <0 Buffer1 is less than Buffer2 + @retval >0 Buffer1 is greater than Buffer2 +**/ +INTN +EFIAPI +MpInformation2HobCompare ( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 + ) +{ + if ((*(MP_INFORMATION2_HOB_DATA **)Buffer1)->ProcessorIndex > (*(MP_INFORMATION2_HOB_DATA **)Buffer2)->ProcessorIndex) { + return 1; + } else if ((*(MP_INFORMATION2_HOB_DATA **)Buffer1)->ProcessorIndex < (*(MP_INFORMATION2_HOB_DATA **)Buffer2)->ProcessorIndex) { + return -1; + } + + return 0; +} + +/** + Extract NumberOfCpus, MaxNumberOfCpus and EFI_PROCESSOR_INFORMATION for all CPU from gEfiMpServiceProtocolGuid. + + @param[out] NumberOfCpus Pointer to NumberOfCpus. + @param[out] MaxNumberOfCpus Pointer to MaxNumberOfCpus. + + @retval ProcessorInfo Pointer to EFI_PROCESSOR_INFORMATION buffer. +**/ +EFI_PROCESSOR_INFORMATION * +GetMpInformationFromMpServices ( + OUT UINTN *NumberOfCpus, + OUT UINTN *MaxNumberOfCpus + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN NumberOfEnabledProcessors; + UINTN NumberOfProcessors; + EFI_MP_SERVICES_PROTOCOL *MpService; + EFI_PROCESSOR_INFORMATION *ProcessorInfo; + + if ((NumberOfCpus == NULL) || (MaxNumberOfCpus == NULL)) { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return NULL; + } + + ProcessorInfo = NULL; + *NumberOfCpus = 0; + *MaxNumberOfCpus = 0; + + /// Get the MP Services Protocol + Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpService); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return NULL; + } + + /// Get the number of processors + Status = MpService->GetNumberOfProcessors (MpService, &NumberOfProcessors, &NumberOfEnabledProcessors); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return NULL; + } + + ASSERT (NumberOfProcessors <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber)); + + /// Allocate buffer for processor information + ProcessorInfo = AllocateZeroPool (sizeof (EFI_PROCESSOR_INFORMATION) * NumberOfProcessors); + if (ProcessorInfo == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return NULL; + } + + /// Get processor information + for (Index = 0; Index < NumberOfProcessors; Index++) { + Status = MpService->GetProcessorInfo (MpService, Index | CPU_V2_EXTENDED_TOPOLOGY, &ProcessorInfo[Index]); + if (EFI_ERROR (Status)) { + FreePool (ProcessorInfo); + DEBUG ((DEBUG_ERROR, "%a: Failed to get processor information for processor %d\n", __func__, Index)); + ASSERT_EFI_ERROR (Status); + return NULL; + } + } + + *NumberOfCpus = NumberOfEnabledProcessors; + + ASSERT (*NumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber)); + // + // If support CPU hot plug, we need to allocate resources for possibly hot-added processors + // + if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + *MaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber); + } else { + *MaxNumberOfCpus = *NumberOfCpus; + } + + return ProcessorInfo; +} + +/** + Extract NumberOfCpus, MaxNumberOfCpus and EFI_PROCESSOR_INFORMATION for all CPU from MpInformation2 HOB. + + @param[out] NumberOfCpus Pointer to NumberOfCpus. + @param[out] MaxNumberOfCpus Pointer to MaxNumberOfCpus. + + @retval ProcessorInfo Pointer to EFI_PROCESSOR_INFORMATION buffer. +**/ +EFI_PROCESSOR_INFORMATION * +GetMpInformation ( + OUT UINTN *NumberOfCpus, + OUT UINTN *MaxNumberOfCpus + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_HOB_GUID_TYPE *FirstMpInfo2Hob; + MP_INFORMATION2_HOB_DATA *MpInformation2HobData; + UINTN HobCount; + UINTN HobIndex; + MP_INFORMATION2_HOB_DATA **MpInfo2Hobs; + UINTN SortBuffer; + UINTN ProcessorIndex; + UINT64 PrevProcessorIndex; + MP_INFORMATION2_ENTRY *MpInformation2Entry; + EFI_PROCESSOR_INFORMATION *ProcessorInfo; + + GuidHob = NULL; + MpInformation2HobData = NULL; + FirstMpInfo2Hob = NULL; + MpInfo2Hobs = NULL; + HobIndex = 0; + HobCount = 0; + + FirstMpInfo2Hob = GetFirstGuidHob (&gMpInformation2HobGuid); + if (FirstMpInfo2Hob == NULL) { + DEBUG ((DEBUG_INFO, "%a: [INFO] gMpInformation2HobGuid HOB not found.\n", __func__)); + return GetMpInformationFromMpServices (NumberOfCpus, MaxNumberOfCpus); + } + + GuidHob = FirstMpInfo2Hob; + while (GuidHob != NULL) { + MpInformation2HobData = GET_GUID_HOB_DATA (GuidHob); + + // + // This is the last MpInformationHob in the HOB list. + // + if (MpInformation2HobData->NumberOfProcessors == 0) { + ASSERT (HobCount != 0); + break; + } + + HobCount++; + *NumberOfCpus += MpInformation2HobData->NumberOfProcessors; + GuidHob = GetNextGuidHob (&gMpInformation2HobGuid, GET_NEXT_HOB (GuidHob)); + } + + ASSERT (*NumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber)); + + // + // If support CPU hot plug, we need to allocate resources for possibly hot-added processors + // + if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + *MaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber); + } else { + *MaxNumberOfCpus = *NumberOfCpus; + } + + MpInfo2Hobs = AllocatePool (sizeof (MP_INFORMATION2_HOB_DATA *) * HobCount); + ASSERT (MpInfo2Hobs != NULL); + if (MpInfo2Hobs == NULL) { + return NULL; + } + + // + // Record each MpInformation2Hob pointer in the MpInfo2Hobs. + // The FirstMpInfo2Hob is to speed up this while-loop without + // needing to look for MpInfo2Hob from beginning. + // + GuidHob = FirstMpInfo2Hob; + while (HobIndex < HobCount) { + MpInfo2Hobs[HobIndex++] = GET_GUID_HOB_DATA (GuidHob); + GuidHob = GetNextGuidHob (&gMpInformation2HobGuid, GET_NEXT_HOB (GuidHob)); + } + + ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * (*MaxNumberOfCpus)); + ASSERT (ProcessorInfo != NULL); + if (ProcessorInfo == NULL) { + FreePool (MpInfo2Hobs); + return NULL; + } + + QuickSort (MpInfo2Hobs, HobCount, sizeof (MP_INFORMATION2_HOB_DATA *), (BASE_SORT_COMPARE)MpInformation2HobCompare, &SortBuffer); + PrevProcessorIndex = 0; + for (HobIndex = 0; HobIndex < HobCount; HobIndex++) { + // + // Make sure no overlap and no gap in the CPU range covered by each HOB + // + ASSERT (MpInfo2Hobs[HobIndex]->ProcessorIndex == PrevProcessorIndex); + + // + // Cache each EFI_PROCESSOR_INFORMATION in order. + // + for (ProcessorIndex = 0; ProcessorIndex < MpInfo2Hobs[HobIndex]->NumberOfProcessors; ProcessorIndex++) { + MpInformation2Entry = GET_MP_INFORMATION_ENTRY (MpInfo2Hobs[HobIndex], ProcessorIndex); + CopyMem ( + &ProcessorInfo[PrevProcessorIndex + ProcessorIndex], + &MpInformation2Entry->ProcessorInfo, + sizeof (EFI_PROCESSOR_INFORMATION) + ); + } + + PrevProcessorIndex += MpInfo2Hobs[HobIndex]->NumberOfProcessors; + } + + FreePool (MpInfo2Hobs); + return ProcessorInfo; +} + +/** + The module Entry Point of the CPU SMM driver. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval Other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +PiCpuSmmEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN Index; + VOID *Buffer; + UINTN BufferPages; + UINTN TileCodeSize; + UINTN TileDataSize; + UINTN TileSize; + UINT8 *Stacks; + VOID *Registration; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + UINTN FamilyId; + UINTN ModelId; + UINT32 Cr3; + + PERF_FUNCTION_BEGIN (); + + // + // Initialize address fixup + // + PiSmmCpuSmmInitFixupAddress (); + PiSmmCpuSmiEntryFixupAddress (); + + // + // Initialize Debug Agent to support source level debug in SMM code + // + InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, &mSmmDebugAgentSupport, NULL); + + // + // Report the start of CPU SMM initialization. + // + REPORT_STATUS_CODE ( + EFI_PROGRESS_CODE, + EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT + ); + + // + // Find out SMRR Base and SMRR Size + // + FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize); + + // + // Retrive NumberOfProcessors, MaxNumberOfCpus and EFI_PROCESSOR_INFORMATION for all CPU from MpInformation2 HOB. + // + gSmmCpuPrivate->ProcessorInfo = GetMpInformation (&mNumberOfCpus, &mMaxNumberOfCpus); + ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL); + + // + // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE. + // A constant BSP index makes no sense because it may be hot removed. + // + DEBUG_CODE_BEGIN (); + if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection)); + } + + DEBUG_CODE_END (); + + // + // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable. + // + mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable); + DEBUG ((DEBUG_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable)); + + // + // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable. + // Make sure AddressEncMask is contained to smallest supported address field. + // + mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64; + DEBUG ((DEBUG_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask)); + + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus; + + PERF_CODE ( + InitializeMpPerf (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); + ); + + // + // The CPU save state and code for the SMI entry point are tiled within an SMRAM + // allocated buffer. The minimum size of this buffer for a uniprocessor system + // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area + // just below SMBASE + 64KB. If more than one CPU is present in the platform, + // then the SMI entry point and the CPU save state areas can be tiles to minimize + // the total amount SMRAM required for all the CPUs. The tile size can be computed + // by adding the // CPU save state size, any extra CPU specific context, and + // the size of code that must be placed at the SMI entry point to transfer + // control to a C function in the native SMM execution mode. This size is + // rounded up to the nearest power of 2 to give the tile size for a each CPU. + // The total amount of memory required is the maximum number of CPUs that + // platform supports times the tile size. The picture below shows the tiling, + // where m is the number of tiles that fit in 32KB. + // + // +-----------------------------+ <-- 2^n offset from Base of allocated buffer + // | CPU m+1 Save State | + // +-----------------------------+ + // | CPU m+1 Extra Data | + // +-----------------------------+ + // | Padding | + // +-----------------------------+ + // | CPU 2m SMI Entry | + // +#############################+ <-- Base of allocated buffer + 64 KB + // | CPU m-1 Save State | + // +-----------------------------+ + // | CPU m-1 Extra Data | + // +-----------------------------+ + // | Padding | + // +-----------------------------+ + // | CPU 2m-1 SMI Entry | + // +=============================+ <-- 2^n offset from Base of allocated buffer + // | . . . . . . . . . . . . | + // +=============================+ <-- 2^n offset from Base of allocated buffer + // | CPU 2 Save State | + // +-----------------------------+ + // | CPU 2 Extra Data | + // +-----------------------------+ + // | Padding | + // +-----------------------------+ + // | CPU m+1 SMI Entry | + // +=============================+ <-- Base of allocated buffer + 32 KB + // | CPU 1 Save State | + // +-----------------------------+ + // | CPU 1 Extra Data | + // +-----------------------------+ + // | Padding | + // +-----------------------------+ + // | CPU m SMI Entry | + // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB + // | CPU 0 Save State | + // +-----------------------------+ + // | CPU 0 Extra Data | + // +-----------------------------+ + // | Padding | + // +-----------------------------+ + // | CPU m-1 SMI Entry | + // +=============================+ <-- 2^n offset from Base of allocated buffer + // | . . . . . . . . . . . . | + // +=============================+ <-- 2^n offset from Base of allocated buffer + // | Padding | + // +-----------------------------+ + // | CPU 1 SMI Entry | + // +=============================+ <-- 2^n offset from Base of allocated buffer + // | Padding | + // +-----------------------------+ + // | CPU 0 SMI Entry | + // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB + // + + // + // Retrieve CPU Family + // + AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); + FamilyId = (RegEax >> 8) & 0xf; + ModelId = (RegEax >> 4) & 0xf; + if ((FamilyId == 0x06) || (FamilyId == 0x0f)) { + ModelId = ModelId | ((RegEax >> 12) & 0xf0); + } + + RegEdx = 0; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >= CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); + } + + // + // Determine the mode of the CPU at the time an SMI occurs + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.4.1.1 + // + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if ((RegEdx & BIT29) != 0) { + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + if (FamilyId == 0x06) { + if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) { + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + } + + DEBUG ((DEBUG_INFO, "PcdControlFlowEnforcementPropertyMask = %d\n", PcdGet32 (PcdControlFlowEnforcementPropertyMask))); + if (PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) { + AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL); + if (RegEax >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) { + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, &RegEdx); + DEBUG ((DEBUG_INFO, "CPUID[7/0] ECX - 0x%08x\n", RegEcx)); + DEBUG ((DEBUG_INFO, " CET_SS - 0x%08x\n", RegEcx & CPUID_CET_SS)); + DEBUG ((DEBUG_INFO, " CET_IBT - 0x%08x\n", RegEdx & CPUID_CET_IBT)); + if ((RegEcx & CPUID_CET_SS) == 0) { + mCetSupported = FALSE; + PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1); + } + + if (mCetSupported) { + AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL); + DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx)); + AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL); + DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx)); + AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL); + DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx)); + } + } else { + mCetSupported = FALSE; + PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1); + } + } else { + mCetSupported = FALSE; + PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1); + } + + // + // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU + // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point. + // This size is rounded up to nearest power of 2. + // + TileCodeSize = GetSmiHandlerSize (); + TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB); + TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); + TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB); + TileSize = TileDataSize + TileCodeSize - 1; + TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); + DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); + + // + // If the TileSize is larger than space available for the SMI Handler of + // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save + // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then + // the SMI Handler size must be reduced or the size of the extra CPU specific + // context must be reduced. + // + ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET)); + + // + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. + // + mCpuHotPlugData.SmBase = NULL; + Status = GetSmBase (mMaxNumberOfCpus, &mCpuHotPlugData.SmBase); + if (Status == EFI_OUT_OF_RESOURCES) { + ASSERT (Status != EFI_OUT_OF_RESOURCES); + CpuDeadLoop (); + } + + if (!EFI_ERROR (Status)) { + ASSERT (mCpuHotPlugData.SmBase != NULL); + // + // Check whether the Required TileSize is enough. + // + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Required TileSize = 0x%08x, Actual TileSize = 0x%08x\n", TileSize, SIZE_8KB)); + FreePool (mCpuHotPlugData.SmBase); + FreePool (gSmmCpuPrivate->ProcessorInfo); + CpuDeadLoop (); + return RETURN_BUFFER_TOO_SMALL; + } + + mSmmRelocated = TRUE; + } else { + ASSERT (Status == EFI_NOT_FOUND); + ASSERT (mCpuHotPlugData.SmBase == NULL); + // + // When the HOB doesn't exist, allocate new SMBASE itself. + // + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + + mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus); + if (mCpuHotPlugData.SmBase == NULL) { + ASSERT (mCpuHotPlugData.SmBase != NULL); + CpuDeadLoop (); + } + + // + // very old processors (i486 + pentium) need 32k not 4k alignment, exclude them. + // + ASSERT (FamilyId >= 6); + // + // Allocate buffer for all of the tiles. + // + BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1)); + Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB); + if (Buffer == NULL) { + DEBUG ((DEBUG_ERROR, "Failed to allocate %Lu pages.\n", (UINT64)BufferPages)); + CpuDeadLoop (); + return EFI_OUT_OF_RESOURCES; + } + + ASSERT (Buffer != NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } + + // + // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. + // + gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus); + ASSERT (gSmmCpuPrivate->Operation != NULL); + + gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus); + ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL); + + gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus); + ASSERT (gSmmCpuPrivate->CpuSaveState != NULL); + + mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize; + mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState; + + // + // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA. + // + mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus); + ASSERT (mCpuHotPlugData.ApicId != NULL); + mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus; + + // + // Retrieve APIC ID of each enabled processor from the MP Services protocol. + // Also compute the SMBASE address, CPU Save State address, and CPU Save state + // size for each CPU in the platform + // + for (Index = 0; Index < mMaxNumberOfCpus; Index++) { + if (!mSmmRelocated) { + mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + } + + gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP); + gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); + gSmmCpuPrivate->Operation[Index] = SmmCpuNone; + + if (Index < mNumberOfCpus) { + mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId; + + DEBUG (( + DEBUG_INFO, + "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n", + Index, + (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId, + mCpuHotPlugData.SmBase[Index], + gSmmCpuPrivate->CpuSaveState[Index], + gSmmCpuPrivate->CpuSaveStateSize[Index] + )); + } else { + gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID; + mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID; + } + } + + // + // Allocate SMI stacks for all processors. + // + mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize))); + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + // + // SMM Stack Guard Enabled + // 2 more pages is allocated for each processor, one is guard page and the other is known good stack. + // + // +--------------------------------------------------+-----+--------------------------------------------------+ + // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack | + // +--------------------------------------------------+-----+--------------------------------------------------+ + // | 4K | 4K PcdCpuSmmStackSize| | 4K | 4K PcdCpuSmmStackSize| + // |<---------------- mSmmStackSize ----------------->| |<---------------- mSmmStackSize ----------------->| + // | | | | + // |<------------------ Processor 0 ----------------->| |<------------------ Processor n ----------------->| + // + mSmmStackSize += EFI_PAGES_TO_SIZE (2); + } + + mSmmShadowStackSize = 0; + if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { + mSmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize))); + + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + // + // SMM Stack Guard Enabled + // Append Shadow Stack after normal stack + // 2 more pages is allocated for each processor, one is guard page and the other is known good shadow stack. + // + // |= Stacks + // +--------------------------------------------------+---------------------------------------------------------------+ + // | Known Good Stack | Guard Page | SMM Stack | Known Good Shadow Stack | Guard Page | SMM Shadow Stack | + // +--------------------------------------------------+---------------------------------------------------------------+ + // | 4K | 4K |PcdCpuSmmStackSize| 4K | 4K |PcdCpuSmmShadowStackSize| + // |<---------------- mSmmStackSize ----------------->|<--------------------- mSmmShadowStackSize ------------------->| + // | | + // |<-------------------------------------------- Processor N ------------------------------------------------------->| + // + mSmmShadowStackSize += EFI_PAGES_TO_SIZE (2); + } else { + // + // SMM Stack Guard Disabled (Known Good Stack is still required for potential stack switch.) + // Append Shadow Stack after normal stack with 1 more page as known good shadow stack. + // 1 more pages is allocated for each processor, it is known good stack. + // + // + // |= Stacks + // +-------------------------------------+--------------------------------------------------+ + // | Known Good Stack | SMM Stack | Known Good Shadow Stack | SMM Shadow Stack | + // +-------------------------------------+--------------------------------------------------+ + // | 4K |PcdCpuSmmStackSize| 4K |PcdCpuSmmShadowStackSize| + // |<---------- mSmmStackSize ---------->|<--------------- mSmmShadowStackSize ------------>| + // | | + // |<-------------------------------- Processor N ----------------------------------------->| + // + mSmmShadowStackSize += EFI_PAGES_TO_SIZE (1); + mSmmStackSize += EFI_PAGES_TO_SIZE (1); + } + } + + Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize))); + ASSERT (Stacks != NULL); + mSmmStackArrayBase = (UINTN)Stacks; + mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1; + + DEBUG ((DEBUG_INFO, "Stacks - 0x%x\n", Stacks)); + DEBUG ((DEBUG_INFO, "mSmmStackSize - 0x%x\n", mSmmStackSize)); + DEBUG ((DEBUG_INFO, "PcdCpuSmmStackGuard - 0x%x\n", FeaturePcdGet (PcdCpuSmmStackGuard))); + if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { + DEBUG ((DEBUG_INFO, "mSmmShadowStackSize - 0x%x\n", mSmmShadowStackSize)); + } + + // + // Set SMI stack for SMM base relocation + // + PatchInstructionX86 ( + gPatchSmmInitStack, + (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)), + sizeof (UINTN) + ); + + // + // Initialize IDT + // + InitializeSmmIdt (); + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! + // + if (!mSmmRelocated) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus); + ASSERT (mRebased != NULL); + SmmRelocateBases (); + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + + DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); + + // + // SMM Time initialization + // + InitializeSmmTimer (); + + // + // Initialize MP globals + // + Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize, mSmmShadowStackSize); + + if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { + for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { + SetShadowStack ( + Cr3, + (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + (mSmmStackSize + mSmmShadowStackSize) * Index, + mSmmShadowStackSize + ); + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + ConvertMemoryPageAttributes ( + Cr3, + mPagingMode, + (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index, + EFI_PAGES_TO_SIZE (1), + EFI_MEMORY_RP, + TRUE, + NULL + ); + } + } + } + + // + // For relocated SMBASE, some MSRs & CSRs are still required to be configured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init. + // + if (mSmmRelocated) { + ExecuteFirstSmiInit (); + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + + // + // Fill in SMM Reserved Regions + // + gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0; + gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0; + + // + // Install the SMM Configuration Protocol onto a new handle on the handle database. + // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer + // to an SMRAM address will be present in the handle database + // + Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces ( + &gSmmCpuPrivate->SmmCpuHandle, + &gEfiSmmConfigurationProtocolGuid, + &gSmmCpuPrivate->SmmConfiguration, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // + // Install the SMM CPU Protocol into SMM protocol database + // + Status = gSmst->SmmInstallProtocolInterface ( + &mSmmCpuHandle, + &gEfiSmmCpuProtocolGuid, + EFI_NATIVE_INTERFACE, + &mSmmCpu + ); + ASSERT_EFI_ERROR (Status); + + // + // Install the SMM Memory Attribute Protocol into SMM protocol database + // + Status = gSmst->SmmInstallProtocolInterface ( + &mSmmCpuHandle, + &gEdkiiSmmMemoryAttributeProtocolGuid, + EFI_NATIVE_INTERFACE, + &mSmmMemoryAttribute + ); + ASSERT_EFI_ERROR (Status); + + // + // Initialize global buffer for MM MP. + // + InitializeDataForMmMp (); + + // + // Initialize Package First Thread Index Info. + // + InitPackageFirstThreadIndexInfo (); + + // + // Install the SMM Mp Protocol into SMM protocol database + // + Status = gSmst->SmmInstallProtocolInterface ( + &mSmmCpuHandle, + &gEfiMmMpProtocolGuid, + EFI_NATIVE_INTERFACE, + &mSmmMp + ); + ASSERT_EFI_ERROR (Status); + + // + // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported. + // + if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData); + ASSERT_EFI_ERROR (Status); + } + + // + // Initialize SMM CPU Services Support + // + Status = InitializeSmmCpuServices (mSmmCpuHandle); + ASSERT_EFI_ERROR (Status); + + // + // register SMM Ready To Lock Protocol notification + // + Status = gSmst->SmmRegisterProtocolNotify ( + &gEfiSmmReadyToLockProtocolGuid, + SmmReadyToLockEventNotify, + &Registration + ); + ASSERT_EFI_ERROR (Status); + + // + // Initialize SMM Profile feature + // + InitSmmProfile (Cr3); + + GetAcpiS3EnableFlag (); + InitSmmS3ResumeState (Cr3); + + DEBUG ((DEBUG_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n")); + + PERF_FUNCTION_END (); + return EFI_SUCCESS; +} + +/** + Function to compare 2 EFI_SMRAM_DESCRIPTOR based on CpuStart. + + @param[in] Buffer1 pointer to Device Path poiner to compare + @param[in] Buffer2 pointer to second DevicePath pointer to compare + + @retval 0 Buffer1 equal to Buffer2 + @retval <0 Buffer1 is less than Buffer2 + @retval >0 Buffer1 is greater than Buffer2 +**/ +INTN +EFIAPI +CpuSmramRangeCompare ( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 + ) +{ + if (((EFI_SMRAM_DESCRIPTOR *)Buffer1)->CpuStart > ((EFI_SMRAM_DESCRIPTOR *)Buffer2)->CpuStart) { + return 1; + } else if (((EFI_SMRAM_DESCRIPTOR *)Buffer1)->CpuStart < ((EFI_SMRAM_DESCRIPTOR *)Buffer2)->CpuStart) { + return -1; + } + + return 0; +} + +/** + + Find out SMRAM information including SMRR base and SMRR size. + + @param SmrrBase SMRR base + @param SmrrSize SMRR size + +**/ +VOID +FindSmramInfo ( + OUT UINT32 *SmrrBase, + OUT UINT32 *SmrrSize + ) +{ + EFI_STATUS Status; + UINTN Size; + EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; + EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; + UINTN Index; + UINT64 MaxSize; + BOOLEAN Found; + EFI_SMRAM_DESCRIPTOR SmramDescriptor; + + // + // Get SMM Access Protocol + // + Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess); + ASSERT_EFI_ERROR (Status); + + // + // Get SMRAM information + // + Size = 0; + Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL); + ASSERT (Status == EFI_BUFFER_TOO_SMALL); + + mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); + ASSERT (mSmmCpuSmramRanges != NULL); + + Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges); + ASSERT_EFI_ERROR (Status); + + mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR); + + // + // Sort the mSmmCpuSmramRanges + // + QuickSort (mSmmCpuSmramRanges, mSmmCpuSmramRangeCount, sizeof (EFI_SMRAM_DESCRIPTOR), (BASE_SORT_COMPARE)CpuSmramRangeCompare, &SmramDescriptor); + + // + // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size + // + CurrentSmramRange = NULL; + for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) { + // + // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization + // + if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) { + continue; + } + + if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) { + if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) { + if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) { + MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize; + CurrentSmramRange = &mSmmCpuSmramRanges[Index]; + } + } + } + } + + ASSERT (CurrentSmramRange != NULL); + + *SmrrBase = (UINT32)CurrentSmramRange->CpuStart; + *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize; + + do { + Found = FALSE; + for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { + if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) && + (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize))) + { + *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart; + *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize); + Found = TRUE; + } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) { + *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize); + Found = TRUE; + } + } + } while (Found); + + DEBUG ((DEBUG_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize)); +} + +/** +Configure SMM Code Access Check feature on an AP. +SMM Feature Control MSR will be locked after configuration. + +@param[in,out] Buffer Pointer to private data buffer. +**/ +VOID +EFIAPI +ConfigSmmCodeAccessCheckOnCurrentProcessor ( + IN OUT VOID *Buffer + ) +{ + UINTN CpuIndex; + UINT64 SmmFeatureControlMsr; + UINT64 NewSmmFeatureControlMsr; + + // + // Retrieve the CPU Index from the context passed in + // + CpuIndex = *(UINTN *)Buffer; + + // + // Get the current SMM Feature Control MSR value + // + SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl); + + // + // Compute the new SMM Feature Control MSR value + // + NewSmmFeatureControlMsr = SmmFeatureControlMsr; + if (mSmmCodeAccessCheckEnable) { + NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT; + if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) { + NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT; + } + } + + // + // Only set the SMM Feature Control MSR value if the new value is different than the current value + // + if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) { + SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr); + } + + // + // Release the spin lock user to serialize the updates to the SMM Feature Control MSR + // + ReleaseSpinLock (mConfigSmmCodeAccessCheckLock); +} + +/** +Configure SMM Code Access Check feature for all processors. +SMM Feature Control MSR will be locked after configuration. +**/ +VOID +ConfigSmmCodeAccessCheck ( + VOID + ) +{ + UINTN Index; + EFI_STATUS Status; + + PERF_FUNCTION_BEGIN (); + + // + // Check to see if the Feature Control MSR is supported on this CPU + // + Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu; + if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) { + mSmmCodeAccessCheckEnable = FALSE; + PERF_FUNCTION_END (); + return; + } + + // + // Check to see if the CPU supports the SMM Code Access Check feature + // Do not access this MSR unless the CPU supports the SmmRegFeatureControl + // + if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) { + mSmmCodeAccessCheckEnable = FALSE; + PERF_FUNCTION_END (); + return; + } + + // + // Initialize the lock used to serialize the MSR programming in BSP and all APs + // + InitializeSpinLock (mConfigSmmCodeAccessCheckLock); + + // + // Acquire Config SMM Code Access Check spin lock. The BSP will release the + // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor(). + // + AcquireSpinLock (mConfigSmmCodeAccessCheckLock); + + // + // Enable SMM Code Access Check feature on the BSP. + // + ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index); + + // + // Enable SMM Code Access Check feature for the APs. + // + for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { + if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) { + if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) { + // + // If this processor does not exist + // + continue; + } + + // + // Acquire Config SMM Code Access Check spin lock. The AP will release the + // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor(). + // + AcquireSpinLock (mConfigSmmCodeAccessCheckLock); + + // + // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP. + // + Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index); + ASSERT_EFI_ERROR (Status); + + // + // Wait for the AP to release the Config SMM Code Access Check spin lock. + // + while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) { + CpuPause (); + } + + // + // Release the Config SMM Code Access Check spin lock. + // + ReleaseSpinLock (mConfigSmmCodeAccessCheckLock); + } + } + + PERF_FUNCTION_END (); +} + +/** + Allocate pages for code. + + @param[in] Pages Number of pages to be allocated. + + @return Allocated memory. +**/ +VOID * +AllocateCodePages ( + IN UINTN Pages + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Memory; + + if (Pages == 0) { + return NULL; + } + + Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory); + if (EFI_ERROR (Status)) { + return NULL; + } + + return (VOID *)(UINTN)Memory; +} + +/** + Allocate aligned pages for code. + + @param[in] Pages Number of pages to be allocated. + @param[in] Alignment The requested alignment of the allocation. + Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return Allocated memory. +**/ +VOID * +AllocateAlignedCodePages ( + IN UINTN Pages, + IN UINTN Alignment + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Memory; + UINTN AlignedMemory; + UINTN AlignmentMask; + UINTN UnalignedPages; + UINTN RealPages; + + // + // Alignment must be a power of two or zero. + // + ASSERT ((Alignment & (Alignment - 1)) == 0); + + if (Pages == 0) { + return NULL; + } + + if (Alignment > EFI_PAGE_SIZE) { + // + // Calculate the total number of pages since alignment is larger than page size. + // + AlignmentMask = Alignment - 1; + RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment); + // + // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow. + // + ASSERT (RealPages > Pages); + + Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory); + if (EFI_ERROR (Status)) { + return NULL; + } + + AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask; + UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory); + if (UnalignedPages > 0) { + // + // Free first unaligned page(s). + // + Status = gSmst->SmmFreePages (Memory, UnalignedPages); + ASSERT_EFI_ERROR (Status); + } + + Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages); + UnalignedPages = RealPages - Pages - UnalignedPages; + if (UnalignedPages > 0) { + // + // Free last unaligned page(s). + // + Status = gSmst->SmmFreePages (Memory, UnalignedPages); + ASSERT_EFI_ERROR (Status); + } + } else { + // + // Do not over-allocate pages in this case. + // + Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory); + if (EFI_ERROR (Status)) { + return NULL; + } + + AlignedMemory = (UINTN)Memory; + } + + return (VOID *)AlignedMemory; +} + +/** + Perform the remaining tasks. + +**/ +VOID +PerformRemainingTasks ( + VOID + ) +{ + if (mSmmReadyToLock) { + PERF_FUNCTION_BEGIN (); + + // + // Check if all Aps enter SMM. In Relaxed-AP Sync Mode, BSP will not wait for + // all Aps arrive. However,PerformRemainingTasks() needs to wait all Aps arrive before calling + // SetMemMapAttributes() and ConfigSmmCodeAccessCheck() when mSmmReadyToLock + // is true. In SetMemMapAttributes(), SmmSetMemoryAttributesEx() will call + // FlushTlbForAll() that need to start up the aps. So it need to let all + // aps arrive. Same as SetMemMapAttributes(), ConfigSmmCodeAccessCheck() + // also will start up the aps. + // + if (EFI_ERROR (SmmCpuRendezvous (NULL, TRUE))) { + DEBUG ((DEBUG_ERROR, "PerformRemainingTasks: fail to wait for all AP check in SMM!\n")); + } + + // + // Start SMM Profile feature + // + if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { + SmmProfileStart (); + } + + // + // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable. + // + InitPaging (); + + // + // Mark critical region to be read-only in page table + // + SetMemMapAttributes (); + + if (IsRestrictedMemoryAccess ()) { + // + // For outside SMRAM, we only map SMM communication buffer or MMIO. + // + SetUefiMemMapAttributes (); + + // + // Set page table itself to be read-only + // + SetPageTableAttributes (); + } + + // + // Configure SMM Code Access Check feature if available. + // + ConfigSmmCodeAccessCheck (); + + // + // Measure performance of SmmCpuFeaturesCompleteSmmReadyToLock() from caller side + // as the implementation is provided by platform. + // + PERF_START (NULL, "SmmCompleteReadyToLock", NULL, 0); + SmmCpuFeaturesCompleteSmmReadyToLock (); + PERF_END (NULL, "SmmCompleteReadyToLock", NULL, 0); + + // + // Clean SMM ready to lock flag + // + mSmmReadyToLock = FALSE; + + PERF_FUNCTION_END (); + } +} + +/** + Perform the pre tasks. + +**/ +VOID +PerformPreTasks ( + VOID + ) +{ + RestoreSmmConfigurationInS3 (); +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/Platform/AMD/TurinBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf new file mode 100644 index 0000000000000000000000000000000000000000..634d9ec7686a4eca9187209b30941ba71e14b93d --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -0,0 +1,165 @@ +## @file +# CPU SMM driver. +# +# This SMM driver performs SMM initialization, deploy SMM Entry Vector, +# provides CPU specific services in SMM. +# +# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PiSmmCpuDxeSmm + MODULE_UNI_FILE = PiSmmCpuDxeSmm.uni + FILE_GUID = A3FF0EF5-0C28-42f5-B544-8C7DE1E80014 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + PI_SPECIFICATION_VERSION = 0x0001000A + ENTRY_POINT = PiCpuSmmEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + PiSmmCpuDxeSmm.c + PiSmmCpuDxeSmm.h + MpService.c + SyncTimer.c + CpuS3.c + CpuService.c + CpuService.h + SmmProfile.c + SmmProfile.h + SmmProfileInternal.h + SmramSaveState.c + SmmCpuMemoryManagement.c + SmmMp.h + SmmMp.c + SmmMpPerf.h + SmmMpPerf.c + +[Sources.Ia32] + Ia32/Semaphore.c + Ia32/PageTbl.c + Ia32/SmmFuncsArch.c + Ia32/SmmProfileArch.c + Ia32/SmmProfileArch.h + Ia32/SmmInit.nasm + Ia32/SmiEntry.nasm + Ia32/SmiException.nasm + Ia32/MpFuncs.nasm + Ia32/Cet.nasm + +[Sources.X64] + X64/Semaphore.c + X64/PageTbl.c + X64/SmmFuncsArch.c + X64/SmmProfileArch.c + X64/SmmProfileArch.h + X64/SmmInit.nasm + X64/SmiEntry.nasm + X64/SmiException.nasm + X64/MpFuncs.nasm + X64/Cet.nasm + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + PcdLib + DebugLib + BaseLib + SynchronizationLib + BaseMemoryLib + MtrrLib + IoLib + TimerLib + SmmServicesTableLib + MemoryAllocationLib + DebugAgentLib + HobLib + PciLib + LocalApicLib + SmmCpuPlatformHookLib + CpuExceptionHandlerLib + UefiLib + DxeServicesTableLib + CpuLib + ReportStatusCodeLib + SmmCpuFeaturesLib + PeCoffGetEntryPointLib + PerformanceLib + CpuPageTableLib + MmSaveStateLib + SmmCpuSyncLib + +[Protocols] + gEfiSmmAccess2ProtocolGuid ## CONSUMES + gEfiSmmConfigurationProtocolGuid ## PRODUCES + gEfiSmmCpuProtocolGuid ## PRODUCES + gEfiSmmReadyToLockProtocolGuid ## NOTIFY + gEfiSmmCpuServiceProtocolGuid ## PRODUCES + gEdkiiSmmMemoryAttributeProtocolGuid ## PRODUCES + gEfiMmMpProtocolGuid ## PRODUCES + gEdkiiSmmCpuRendezvousProtocolGuid ## PRODUCES + gEfiMpServiceProtocolGuid ## CONSUMES + +[Guids] + gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # it is used for S3 boot. + gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES + gMpInformation2HobGuid ## CONSUMES # Assume the HOB must has been created + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmApPerfLogEnable ## CONSUMES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize ## SOMETIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## SOMETIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress ## SOMETIMES_PRODUCES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize ## SOMETIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## CONSUMES + +[FixedPcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk ## CONSUMES + +[Depex] + TRUE + +[Pcd.X64] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess ## CONSUMES + +[UserExtensions.TianoCore."ExtraFiles"] + PiSmmCpuDxeSmmExtra.uni diff --git a/Platform/AMD/TurinBoard/PuricoBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/PuricoBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..554d7c0b1ccb0bb698c441ce152c8fbd0c19ef5a --- /dev/null +++ b/Platform/AMD/TurinBoard/PuricoBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("4462C5BB-B061-4771-85D3-674849AB82E0")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..0608cf05577454d26e68781d2b391acb1ff9387f --- /dev/null +++ b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.dsc @@ -0,0 +1,196 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Purico +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "PURICO " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20204F4349525550 # "PURICO " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|135 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..4701cd93633b714fb52ffdd4b6a02aab36b59910 --- /dev/null +++ b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..7c74ddd09ab6c449c6db397668da2491182f19fd --- /dev/null +++ b/Platform/AMD/TurinBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,243 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.IntDesignatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.ExtDesignatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.IntDesignatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.ExtDesignatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.IntDesignatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.ExtDesignatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.IntDesignatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..6390510db0e5a1f0424bd13d9fd9e35e5cfa6fd0 --- /dev/null +++ b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.dsc @@ -0,0 +1,204 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Quartz +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "QUARTZ " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20205A5452415551 # "QUARTZ " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc + diff --git a/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..4701cd93633b714fb52ffdd4b6a02aab36b59910 --- /dev/null +++ b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..737bf42d1f06ff942b57fd368ef439b1e7535768 --- /dev/null +++ b/Platform/AMD/TurinBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("4462C5BB-B061-4771-85D3-674849AB82E0")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/RubyBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..9c0f611cfa56e9c96d68d50cdd18842ad4d124a9 --- /dev/null +++ b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.dsc @@ -0,0 +1,196 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Ruby +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "RUBY " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020202059425552 # "RUBY " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/RubyBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..4701cd93633b714fb52ffdd4b6a02aab36b59910 --- /dev/null +++ b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..778cfda7dba5982095d87933bc65dc678f8dabf3 --- /dev/null +++ b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,243 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.IntDesignatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.ExtDesignatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.IntDesignatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.ExtDesignatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.IntDesignatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.ExtDesignatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.IntDesignatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..d77f4986255800299515aeabf63ba60e606bc09f --- /dev/null +++ b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.dsc @@ -0,0 +1,200 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Titanite +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "TITANITE" + + DEFINE SATA_OVERRIDE = TRUE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"A0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"A1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4554494E41544954 # "TITANITE" + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdEspiOffset|0x20000 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|135 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable2|0x30 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..2a1a93e93633c4d6493ad6da5101b59b1362b819 --- /dev/null +++ b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0xFF + DEFINE EFS_ESPI_BYTE1 = 0x0E +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..ebad8be1332478c54d19df917485747bb4fd2abd --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,239 @@ +/** @file + + Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** @file + This file implements BoardAcpiDxe driver. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param[in] Protocol The protocol to find. + @param[in] FfsGuid The FFS that contains the ACPI table. + @param[out] Instance Return pointer to the first instance of the protocol. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. +**/ +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + IN EFI_GUID *FfsGuid, + OUT VOID **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Size = 0; + FvStatus = 0; + Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *)(*Instance))->ReadFile ( + *Instance, + FfsGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + FreePool (HandleBuffer); + + return Status; +} + +/** + Publish ACPI table from FV. + + @param[in] FfsGuid The FFS that contains the ACPI table. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +PublishAcpiTablesFromFv ( + IN EFI_GUID *FfsGuid + ) +{ + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINT32 FvStatus; + UINTN Size; + UINTN TableHandle; + INTN Instance; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_ACPI_TABLE_VERSION Version; + + Instance = 0; + TableHandle = 0; + CurrentTable = NULL; + FwVol = NULL; + + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, " Looking for Platform ACPI table: %g\n", FfsGuid)); + + // + // Locate the firmware volume protocol + // + Status = LocateSupportProtocol ( + &gEfiFirmwareVolume2ProtocolGuid, + FfsGuid, + (VOID **)&FwVol + ); + ASSERT_EFI_ERROR (Status); + + // + // Read tables from the FV. + // + while (Status == EFI_SUCCESS) { + Status = FwVol->ReadSection ( + FwVol, + FfsGuid, + EFI_SECTION_RAW, + Instance, + (VOID **)&CurrentTable, + &Size, + &FvStatus + ); + if (!EFI_ERROR (Status)) { + BoardUpdateAcpiTable (CurrentTable, &Version); + // + // Add the table + // + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Failed to install ACPI table.\n")); + continue; + } + + Status = gBS->FreePool (CurrentTable); + CurrentTable = NULL; + // + // Increment the instance + // + Instance++; + } + } + + // + // Finished + // + return Status; +} + +/** + ACPI Platform driver installation function. + + @param[in] ImageHandle Handle for this drivers loaded image protocol. + @param[in] SystemTable EFI system table. + + @retval EFI_SUCCESS The driver installed without error. + @retval EFI_ABORTED The driver encountered an error and could not complete installation of + the ACPI tables. + +**/ +EFI_STATUS +EFIAPI +InstallAcpiBoard ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid); + if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) { + DEBUG ((DEBUG_ERROR, " Failed to publish platform ACPI table.\n")); + ASSERT (FALSE); + } + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..c2d05778459d3e427695194788300621146e6de8 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,66 @@ +## @file +# +# BoardAcpiDxe friver to install common ACPI tables. +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = BoardAcpiDxe + FILE_GUID = D62E99B5-42F1-4A98-8D21-7B4F6F739C16 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallAcpiBoard + +[Sources.common] + BoardAcpiDxe.c + Dsdt/Dsdt.asl + Dsdt/PciSsdt.asl + Dsdt/AmdPci.asi + +[Packages] + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BoardAcpiTableLib + DebugLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart0Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart1Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart2Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart3Irq + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + +[Depex] + gEfiAcpiTableProtocolGuid AND + gEfiFirmwareVolume2ProtocolGuid + +[BuildOptions.common] + # + # Specify the addtinoal directories for IASL compiler to serach FchSongshanI2C_I3C.asl from either /AGESA/AgesaModulePkg or /edk2-platforms/Platform/AMD. + # /AGESA/AgesaModulePkg has the higher priority to search if this driver is built with AGESA PI release, otherwise the driver is build with opensource AGESA. + # + MSFT:*_*_*_ASL_FLAGS = -I$(WORKSPACE)\AGESA\AgesaModulePkg\Fch\Kunlun\FchKunlunCore\Kunlun -I$(WORKSPACE)\edk2-platforms\Platform\AMD\AgesaModulePkg\Fch\Kunlun\FchKunlunCore\Kunlun + GCC:*_*_*_ASL_FLAGS = -I$(WORKSPACE)/AGESA/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun -I$(WORKSPACE)/edk2-platforms/Platform/AMD/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi new file mode 100644 index 0000000000000000000000000000000000000000..8113d277f088c02335a35e3be7197a86674d1718 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi @@ -0,0 +1,412 @@ +/** @file + + Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +External (PCI0, DeviceObj) +External (\_SB.PCI0.RP71, DeviceObj) +External (PCI3, DeviceObj) +External (\_SB.PCI3.RP71, DeviceObj) +External (POSS, FieldUnitObj) +External (POSC, FieldUnitObj) + +Name (SS1, Zero) +Name (SS2, Zero) +Name (SS3, One) +Name (SS4, Zero) +Name (PRWP, Package (0x02) +{ + Zero, + Zero +}) +Method (GPRW, 2, NotSerialized) +{ + PRWP [Zero] = Arg0 + Local0 = (SS1 << One) + Local0 |= (SS2 << 0x02) + Local0 |= (SS3 << 0x03) + Local0 |= (SS4 << 0x04) + If (((One << Arg1) & Local0)) + { + PRWP [One] = Arg1 + } + Else + { + Local0 >>= One + FindSetRightBit (Local0, PRWP [One]) + } + + Return (PRWP) +} + +Scope (PCI0) { + Device (AL2A) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, "AL2AHB") + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadOnly, 0xFEDC0000, 0x00001000) + }) + OperationRegion (LUIE, SystemMemory, 0xFEDC0020, 0x4) + Field(LUIE, AnyAcc, NoLock, Preserve) { + IER0, 1, // IO_Enable_Range_0 + IER1, 1, // IO_Enable_Range_1 + IER2, 1, // IO_Enable_Range_2 + IER3, 1, // IO_Enable_Range_3 + LUR1, 4, // Reserved + WUR0, 2, // Which_UART_RANGE_0 + WUR1, 2, // Which_UART_RANGE_0 + WUR2, 2, // Which_UART_RANGE_0 + WUR3, 2, // Which_UART_RANGE_0 + LUR2, 16, // Reserved + } + // Return _STA Disable value if Legacy Resources Enabled + // Otherwise return _STA Enabled valude (0xF) + // ARG0 = UART number 0-3 + Method (USTA, 1) { + If (LAnd (LEqual(IER0, One), LEqual (WUR0, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER1, One), LEqual (WUR1, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER2, One), LEqual (WUR2, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER3, One), LEqual (WUR3, Arg0))) { + Return (Zero) + } + Else { + Return (0xF) + } + } + + // Return _STA Enable value (0xF) if COMx address is being decoded + // Else return _STA Disable value (0x0) + // ARG0 = COM port number 1-4 + Method (CSTA, 1) { + If (LAnd (LEqual (Arg0, 1), LEqual (IER3, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 2), LEqual (IER1, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 3), LEqual (IER2, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 4), LEqual (IER0, 1))) { + Return (0xF) + } + Else { + Return (Zero) + } + } + } + Device (URT0) { + Name (_HID, "AMDI0020") + Name (_UID, Zero) + Method (_STA) { + Store (^^AL2A.USTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDC9000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDC7000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart0Irq)} + }) + } + + Device (URT1) { + Name (_HID, "AMDI0020") + Name (_UID, One) + Method (_STA) { + Store (^^AL2A.USTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCA000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDC8000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart1Irq)} + }) + } + + // UART 2 always disabled + Device (URT2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Name (_STA, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCE000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDCC000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart2Irq)} + }) + } + + // UART 3 always disabled + Device (URT3) { + Name (_HID, "AMDI0020") + Name (_UID, 0x3) + Name (_STA, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCF000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDCD000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart3Irq)} + }) + } + + Device (LPC0) { + Name (_ADR, 0x140003) + + // UARTx -> COM1: I/O port 0x3F8, IRQ PcdFchUart1Irq + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM1") + Name (_UID, One) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03F8, 0x03F8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart1Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM1", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM2: I/O port 0x2F8, IRQ PcdFchUart0Irq + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM2") + Name (_UID, 2) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x02F8, 0x02F8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart0Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM2", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM3: I/O port 0x3E8, IRQ PcdFchUart2Irq + Device (COM3) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM3") + Name (_UID, 3) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03E8, 0x03E8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart2Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM3", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM4: I/O port 0x2E8, IRQ PcdFchUart3Irq + Device (COM4) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM4") + Name (_UID, 4) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x02E8, 0x02E8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart3Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM4", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + Device (DMAC) { + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0, 0x0, 0x1, 0x10) + IO (Decode16, 0x81, 0x81, 0x1, 0xF) + IO (Decode16, 0xC0, 0xC0, 0x1, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) {4} + }) + } // Device (DMAC) + + Device (RTC) { + Name (_HID, EISAID ("PNP0B00")) + Name (_FIX, Package () {EISAID ("PNP0B00")}) + Name (_CRS, ResourceTemplate () { + IO (Decode16,0x70,0x70,0x01,0x02) + IO (Decode16,0x72,0x72,0x01,0x02) + }) + } // Device (RTC) + + Device (SPKR) { + Name (_HID, EISAID ("PNP0800")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x61, 0x61, 0x1, 0x1) + }) + } // Device (SPKR) + + Device (TMR) { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x40, 0x40, 0x1, 0x4) + }) + } // Device (TMR) + + Device (SYSR) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x10, 0x10, 0x1, 0x10) + IO (Decode16, 0x20, 0x20, 0x1, 0x2) + IO (Decode16, 0xA0, 0xA0, 0x1, 0x2) + IO (Decode16, 0x72, 0x72, 0x1, 0x2) + IO (Decode16, 0x80, 0x80, 0x1, 0x1) + IO (Decode16, 0xB0, 0xB0, 0x1, 0x2) + IO (Decode16, 0x92, 0x92, 0x1, 0x1) + IO (Decode16, 0xF0, 0xF0, 0x1, 0x1) + IO (Decode16, 0x400, 0x400, 0x01,0xd0) + IO (Decode16, 0x4D0, 0x4D0, 0x1, 0x2) + IO (Decode16, 0x4D6, 0x4D6, 0x1, 0x1) + IO (Decode16, 0xC00, 0xC00, 0x1, 0x2) + IO (Decode16, 0xC14, 0xC14, 0x1, 0x1) + IO (Decode16, 0xC50, 0xC50, 0x1, 0x3) + IO (Decode16, 0xC6C, 0xC6C, 0x1, 0x1) + IO (Decode16, 0xC6F, 0xC6F, 0x1, 0x1) + IO (Decode16, 0xCD0, 0xCD0, 0x1, 0xc) + }) + } // Device (SYSR) + + Device (SPIR) { // SPI ROM + Name (_HID, EISAID ("PNP0C01")) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadOnly, + FixedPcdGet32 (PcdFlashAreaBaseAddress), + FixedPcdGet32 (PcdFlashAreaSize) + ) + }) + } // Device (SPIR) + +#if FixedPcdGet8 (PcdIpmiInterfaceType) != 0 + Device (IPMK) { // IPMI KCS Device + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, Unicode ("IPMI_KCS")) // _STR: Description String + Name (_UID, Zero) // _UID: Unique ID + Name (_IFT, One) // _IFT: IPMI Interface Type + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress), // Range Minimum + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress), // Range Maximum + 0x00, // Alignment + 0x02 // Length + ) + }) + Method (_SRV, 0, NotSerialized) { // _SRV: IPMI Spec Revision + Return (0x0200) + } + Method (_STA, 0, NotSerialized) { // _STA: Status + If (FixedPcdGet8 (PcdIpmiInterfaceType) == _IFT) { + Return (0x0F) + } + Else { + Return (Zero) + } + } // Method (_STA) + } // Device (IPMK) +#endif + + } // Device (LPC0) +} // Device (PCI0) + + Scope (\_SB.PCI0.RP71) { + Device (XHC0) + { + Name (_ADR, 0x00000004) + Method (_PRW, 0, NotSerialized) + { + Return (GPRW (0x0B, 0x04)) + } + } + } +Scope (\_SB.PCI3.RP71) { + Device (XHC0) + { + Name (_ADR, 0x00000004) + Method (_PRW, 0, NotSerialized) + { + Return (GPRW (0x0B, 0x04)) + } + } + } + + +Scope (_GPE) +{ + Method (_L0B, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.PCI0.RP71.XHC0, 0x02) // Device Wake + Notify (\_SB.PCI3.RP71.XHC0, 0x02) // Device Wake + } +} diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl new file mode 100644 index 0000000000000000000000000000000000000000..27c68e809cbf1ad091deae7637033fc28cb5627f --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl @@ -0,0 +1,323 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, + "AMD ", + "AmdTable", + 0x00 +) + +// BEGIN OF ASL SCOPE +{ + Name (\_S0, Package(4) { + 0x00, 0x00, 0x00, 0x00 // PM1a_CNT.SLP_TYP = 0, PM1b_CNT.SLP_TYP = 0 + }) + Name (\_S5, Package(4) { + 0x05, 0x00, 0x00, 0x00 // PM1a_CNT.SLP_TYP = 5, PM1b_CNT.SLP_TYP = 0 + }) + + External (POSS, FieldUnitObj) + External (POSC, FieldUnitObj) + External (SMIR, FieldUnitObj) + External (DSMI, FieldUnitObj) + External (DRPB, FieldUnitObj) + External (DRPA, FieldUnitObj) + External (DIDX, FieldUnitObj) + External (DFIN, FieldUnitObj) + External (DOUT, FieldUnitObj) + External (DRPN, FieldUnitObj) + External (OSMI, FieldUnitObj) + External (ORPB, FieldUnitObj) + External (ORPA, FieldUnitObj) + External (OAG1, FieldUnitObj) + External (HSMI, FieldUnitObj) + External (HRPB, FieldUnitObj) + External (HRPA, FieldUnitObj) + External (HPCK, FieldUnitObj) + External (HPHM, FieldUnitObj) + External (AERM, FieldUnitObj) + External (CFLG, FieldUnitObj) + External (CTAG, FieldUnitObj) + + Scope (\_SB) { + Name (SUPP, 0) + Name (CTRL, 0) + Name (SUPC, Zero) + Name (CTRC, Zero) + Name (BUF, Buffer() {0x00, 0x00}) + Method (OSCI, 6, NotSerialized) + { + CreateDWordField (Arg3, 0, CDW1) + // Check for proper UUID + If (LOr(LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")), + // The _OSC interface for a CXL Host Bridge UUID + (LEqual(Arg0, ToUUID("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3 ,CTRL) + // Only allow native hot plug control if OS supports: + // \* ASPM + // \* Clock PM + // \* MSI/MSI-X + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + If (LNotEqual (Arg1, One)) + { + // Unknown revision + Or (CDW1, 0x08, CDW1) + } + + If(LAnd(LEqual(HPHM,6), LEqual(AERM,3))) + { + If(LEqual(And(CTRL,0x80), 0x80)) //OS request PCI Express Downstream Port Containment configuration control? + { + If(LEqual(And(CTRL,0x08), 0x08)) //OS request PCI Express Advanced Error Reporting control? + { + Store(0x0F,Local0) + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + Store (Arg5, HRPB) + Store (Arg4, HRPA) + // Trigger OSC SMI + Store (HSMI, SMIR) + } + } Else { + Store (0xDEADBABE, HRPA) + Store (HSMI, SMIR) + } + } Else { + Store (0xDEADBABE, HRPA) + Store (HSMI, SMIR) + } + } + + If(LEqual(Local0,0x0F)) + { + And(CTRL,POSC,CTRL) //Mask undefined bits + Or(CTRL,0x88,CTRL) //Restore the OS requst bit setting + Store(CTRL,POSC) + } Else { + And(CTRL,POSC,CTRL) + } + + If (LNotEqual (CDW3, CTRL)) + { + // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + // Update to RASD oreration region. + Store (SUPP, POSS) //Store SUPP (DWORD 2) to Platform RASD + // If CXL Host Bridge + If (LEqual (Arg0, ToUUID ("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))) { + CreateDWordField (Arg3, 12, CDW4) // CXL Support Field: + CreateDWordField (Arg3, 16, CDW5) // CXL Control Field: + Store(CDW4,SUPC) + Store(CDW5,CTRC) + // + // The firmware clear bit 0 to deny control over CXL Memory CXL + // Error Reporting if bit 0 or 1 are not set + // + // Check bit 0 + // RCD and RCH Port Register Access Supported + // + If (LNotEqual (And (SUPC, 0x01), 0x01)) + { + And (CTRC, 0xFE, CTRC) + } + // + // Check bit 1 + // CXL VH Register Access Supported + // + If (LNotEqual (And (SUPC, 0x02), 0x01)) + { + And (CTRC, 0xFE, CTRC) + } + // Update DWORD5 in the buffer + Store (CTRC, CDW5) + } + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } + + Method (HDSM, 7, Serialized) { + CreateWordField(BUF, 0, SUPF) + Store(0, SUPF) + // check for GUID and revision match + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))) { + If (LEqual(Arg1, 0x05)) { + Store (Arg2, DIDX) + Store (0x00, DFIN) + If (LEqual(Arg2, 0x0C)) { + Store (ObjectType(Arg3), Local0) + If (LEqual (Local0, 4)) { // Arg3 is a package obj + Store (DeRefOf (Index (Arg3, 0)), Local1) + } Else { // Assume Arg3 is an Integer obj + Store (Arg3, Local1) + } + Store (Local1, DFIN) + Store (Arg6, DRPN) + } + Store (Arg4, DRPB) + Store (Arg5, DRPA) + // Trigger EDR DSM SMI + Store (DSMI, SMIR) + // Function 0 + If (LEqual(Arg2, 0)) { + Store(DOUT, SUPF) + Return(BUF) + } + // Functions 0x0C, 0x0D + Return(DOUT) + } + } + // + // The OSPM can request the firmware to determine the optimum QoS Throttling Group (QTG) + // to which a device HDM range should be assigned, based on its performance characteristics. + // The OSPM evaluate this _DSM Function to retrieve QTG recommendations and map the device + // HDM range to an HPA range that is described by a CFMWS entry that follows the + // platform recommendations (CXL Revision 3.1) + // + If (LEqual (Arg0, ToUUID("f365f9a6-a7de-4071-a66a-b40c0b4f8e52"))) { + Name(MQTG, 1) //Max supported QoS Throttling Group (QTG) ID + Name(QTGR, Package(){0,1}) // QoS Throttling Group (QTG) Recommendations + + // + // Revision ID: 1 + // + If (LEqual(Arg1, 1)) + { + // + // Function Index: 01h + // + If (LEqual(Arg2, 1)) + { + // + // Package: Max Supported QTG ID and QTG Recommendations + // + Return + ( + Package(0x02){MQTG, QTGR} + ) + } + } + } + Return(BUF) // Failed + } // end HDSM + + Method (HOST, 4, Serialized) { + // OSPM calls this method after processing ErrorDisconnectRecover notification from firmware + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x0F) { // Error Disconnect Recover request + Store (Arg2, ORPB) + Store (Arg3, ORPA) + Store (Arg1, OAG1) + // Trigger EDR OST SMI + Store (OSMI, SMIR) + } // End Case(0xF) + } // End Switch + } // end HOST + + Method (CDSM, 4, Serialized) { + Name(FEID, 0) + Name(RSTV, 0) + Name(CPUN, 1024)//Maximum CpuNum = 1024 + Name (RBUF, Buffer (8) {0}) // Return buffer + + CreateByteField (RBUF, 0,VSTV)//BIT0:VolatileMemory ST Valid, BIT1:VolatileMemory ExtendedST Valid + CreateByteField (RBUF, 1,VMST)//VolatileMemory ST + CreateWordField (RBUF, 2,VEST)//VolatileMemory ExtendedST + CreateByteField (RBUF, 4,PSTV)///BIT0:PersistentMemory ST Valid, BIT1:PersistentMemory ExtendedST Valid + CreateByteField (RBUF, 5,PMST)//PersistentMemory ST + CreateWordField (RBUF, 6,PEST)//PersistentMemory ExtendedST + + if (LEqual(CFLG, 0)){ + Return(0) //CDMA not Support + } + + // check for GUID and revision match + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))) { + If (LEqual(Arg1, 0x07)) { //Revision: 7 + If (LEqual(Arg2, 0x0F)) { //Arg2, Function Index: 0Fh + + Store (ObjectType(Arg3), Local0) //Arg3 is a package obj + Store (DeRefOf (Index (Arg3, 0)), Local1) //FeatureID // DWORD (32 bits) + Store (DeRefOf (Index (Arg3, 1)), Local2) //FeatureArgument1: Target UID // DWORD (32 bits) + Store (DeRefOf (Index (Arg3, 2)), Local3) //FeatureArgument2 // DWORD (64 bits) + Store(Local1, FEID) + + switch (FEID){ + // + // For FeatureID == 0 (Processor Cache Steering Tags) + // + case(0) + { + //Name(LEN1, 4) //size of processor UID + //Name(LEN2, 2) //size of Steering Tag + Name(IDX1, 0) + Name(PUID, 0) + Name(XTAG, 0) + + While(LGreater(CPUN, 0)) { + Mid (CTAG, IDX1, 4, PUID) //(Extract processor UID) + Add (IDX1, 8, IDX1) + Mid (CTAG, IDX1, 2, XTAG) //(Extract Sterring Tag value) + + if ((PUID) == (Local2)){ //(ProcUid == Target UID) + Store(XTAG, VEST) + Store(XTAG, PEST) + And(XTAG, 0x00FF, VMST) + And(XTAG, 0x00FF, PMST) + Break + } + + Add (IDX1, 8, IDX1) //index the next CDMA_ST_MAP structure. + Decrement(CPUN) + } + + Or (VSTV, 0x03, VSTV) // VolatileMemory ST Valid + Or (PSTV, 0x03, PSTV) // PersistentMemory ST Valid + + Return (RBUF) + } + + default { + //For any other FeatureID: + //FeatureArgument1: DWORD: Reserved. + //FeatureArgument2: QWORD: Reserved. + //Return Value: QWORD: 0 (Not supported). + Return(0) + } + } + } + If (LEqual(Arg2, 0)) { + Return(0x8001)//SDCI _DSM function index is 0xF, so bit[15] and bit[0] should be 1 + } + } + } + + Return(Zero) //Not Support + } // end CDSM + } + + Include ("FchBreithorn.asi") + +}// End of ASL File diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl new file mode 100644 index 0000000000000000000000000000000000000000..8f27c1e5951116ea0a690c708c8fb66436a2b587 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl @@ -0,0 +1,30 @@ +/** @file + + Copyright (C) 2020-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/* + ACPI FCH device resources +*/ + +DefinitionBlock ( + "PciSsdt.aml", + "SSDT", + 0x02, // SSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // declared within the Definition Block are to be evaluated as 64-bit values + "AMD ", // OEM ID (6 byte string) + "AmdTable",// OEM table ID (8 byte string) + 0x00 // OEM version of SSDT table (4 byte Integer) +) + +// BEGIN OF ASL SCOPE +{ + Scope (\_SB) { + Include ("AmdPci.asi") + } +}// End of ASL File + diff --git a/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.c b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.c new file mode 100644 index 0000000000000000000000000000000000000000..addc4ca01e4582807b136416a17b3f7b3b635b4b --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.c @@ -0,0 +1,152 @@ +/** @file + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Entry point for Data Fabric Resouces PEIM. + + @param FileHandle Pointer to the FFS file header. + @param PeiServices Pointer to the PEI services table. + + @retval EFI_STATUS EFI_SUCCESS + EFI_STATUS respective failure status. +**/ +EFI_STATUS +EFIAPI +PeiDfResourcesInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + FABRIC_RESOURCE_FOR_EACH_RB *FabricResourceForEachRb; + UINT8 SocPresent; + UINT8 RbPerSocketPresent; + UINT8 i; + UINT8 j; + + DEBUG ((DEBUG_INFO, "Entered - %a\n", __func__)); + Status = (*PeiServices)->AllocatePool ( + PeiServices, + sizeof (FABRIC_RESOURCE_FOR_EACH_RB), + (VOID **)&FabricResourceForEachRb + ); + + if (!EFI_ERROR (Status)) { + SocPresent = (UINT8)FabricTopologyGetNumberOfProcessorsPresent (); + RbPerSocketPresent = (UINT8)FabricTopologyGetNumberOfRootBridgesOnSocket (0); + DEBUG ((DEBUG_INFO, "SoC count - %d\n", SocPresent)); + DEBUG ((DEBUG_INFO, "RB count - %d\n", RbPerSocketPresent * SocPresent)); + + // + // Mapping of resources for 1P system + // + // Logical Socket 0, Rb 0 is Physical Socket0, Rb 4 ---> PCI(0), FabricResourceForEachRb [0][4] + // Logical Socket 0, Rb 1 is Physical Socket0, Rb 7 ---> PCI(1), FabricResourceForEachRb [0][7] + // Logical Socket 0, Rb 2 is Physical Socket0, Rb 6 ---> PCI(2), FabricResourceForEachRb [0][6] + // Logical Socket 0, Rb 3 is Physical Socket0, Rb 5 ---> PCI(3), FabricResourceForEachRb [0][5] + // Logical Socket 0, Rb 4 is Physical Socket0, Rb 3 ---> PCI(4), FabricResourceForEachRb [0][3] + // Logical Socket 0, Rb 5 is Physical Socket0, Rb 2 ---> PCI(5), FabricResourceForEachRb [0][2] + // Logical Socket 0, Rb 6 is Physical Socket0, Rb 1 ---> PCI(6), FabricResourceForEachRb [0][1] + // Logical Socket 0, Rb 7 is Physical Socket0, Rb 0 ---> PCI(7), FabricResourceForEachRb [0][0] + // + + // + // Mapping of resources for 2P system, with 8 root bridges + // + // Logical Socket 0, Rb 0 is Physical Socket0, Rb 2 ---> PCI(0), FabricResourceForEachRb [0][2] + // Logical Socket 0, Rb 1 is Physical Socket0, Rb 3 ---> PCI(1), FabricResourceForEachRb [0][3] + // Logical Socket 0, Rb 2 is Physical Socket0, Rb 1 ---> PCI(2), FabricResourceForEachRb [0][1] + // Logical Socket 0, Rb 3 is Physical Socket0, Rb 0 ---> PCI(3), FabricResourceForEachRb [0][0] + // Logical Socket 1, Rb 0 is Physical Socket1, Rb 2 ---> PCI(4), FabricResourceForEachRb [1][2] + // Logical Socket 1, Rb 1 is Physical Socket1, Rb 3 ---> PCI(5), FabricResourceForEachRb [1][3] + // Logical Socket 1, Rb 2 is Physical Socket1, Rb 1 ---> PCI(6), FabricResourceForEachRb [1][1] + // Logical Socket 1, Rb 3 is Physical Socket1, Rb 0 ---> PCI(7), FabricResourceForEachRb [1][0] + // + + for (i = 0; i < 2; i++) { + for (j = 0; j < 8; j++) { + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[i][j].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[i][j].Alignment = 1; + + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[i][j].Size = SIZE_64GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[i][j].Alignment = 1; + + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[i][j].Alignment = 1; + + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[i][j].Size = SIZE_16MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[i][j].Alignment = 0xffffff; + } + } + + // Adjust IO SPACE, MAX available size is 64KB + // FabricResourceForEachRb->IO[0][0].Size = SIZE_8KB + SIZE_4KB; + + if (SocPresent == 1) { + FabricResourceForEachRb->IO[0][4].Size = SIZE_8KB; + FabricResourceForEachRb->IO[0][2].Size = SIZE_4KB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][4].Size = SIZE_2MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][5].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][6].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Size = SIZE_8MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Size = SIZE_16MB + SIZE_8MB; + } else { + FabricResourceForEachRb->IO[0][4].Size = SIZE_8KB; + FabricResourceForEachRb->IO[0][2].Size = SIZE_8KB; + FabricResourceForEachRb->IO[0][1].Size = SIZE_4KB; + FabricResourceForEachRb->IO[0][0].Size = SIZE_4KB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Size = SIZE_2MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][3].Size = SIZE_2MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][1].Size = SIZE_32MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Size = SIZE_32MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][2].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][3].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][1].Size = SIZE_2MB + SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][0].Size = SIZE_1MB; + } + + // Above 4G, PMem + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][0].Size = SIZE_512GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][1].Size = SIZE_512GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][2].Size = SIZE_512GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][3].Size = SIZE_1TB; + + // Below 4G, PMem + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][0].Size = SIZE_256MB + SIZE_32MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][1].Size = SIZE_128MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][2].Size = SIZE_128MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][3].Size = SIZE_128MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][4].Size = SIZE_64MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][0].Size = SIZE_64MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][4].Size = SIZE_64MB; + + // Primary RootBridge 2nd MMIO + // if NonP is 0 and PMem is non-zero, all available size would be assigned to PMem + FabricResourceForEachRb->PrimaryRbSecondNonPrefetchableMmioSizeBelow4G.Size = 0; + FabricResourceForEachRb->PrimaryRbSecondNonPrefetchableMmioSizeBelow4G.Alignment = 1; + FabricResourceForEachRb->PrimaryRbSecondPrefetchableMmioSizeBelow4G.Size = 1; + FabricResourceForEachRb->PrimaryRbSecondPrefetchableMmioSizeBelow4G.Alignment = 1; + + // Program bus numbers based on topology info + for (i = 0; i < SocPresent; i++) { + for (j = 0; j < RbPerSocketPresent; j++) { + FabricResourceForEachRb->PciBusNumber[i][j] = (UINT16) (FabricTopologyGetHostBridgeBusLimit(i, 0, j) - FabricTopologyGetHostBridgeBusBase (i, 0, j) + 1); + } + } + + PcdSet64S (PcdAmdFabricResourceDefaultSizePtr, (UINT64)(UINTN)FabricResourceForEachRb); + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.inf b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.inf new file mode 100644 index 0000000000000000000000000000000000000000..5afccc1244b1b2bbb7dde134b602b0f6b701869c --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.inf @@ -0,0 +1,38 @@ +## @file +# +# Component information file for Pre-defined Data Fabric resources module. +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = DfResourcesPei + FILE_GUID = A09C83C1-A653-461B-8761-6E91443B9D78 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeiDfResourcesInit + +[Sources] + DfResourcesPei.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + +[LibraryClasses] + BaseLib + BaseFabricTopologyLib + PcdLib + PeimEntryPoint + PeiServicesLib + +[Pcd] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFabricResourceDefaultSizePtr + +[Depex] + TRUE diff --git a/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInit.h b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInit.h new file mode 100644 index 0000000000000000000000000000000000000000..8151fcf7dac98e09883e252320a2655938928684 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInit.h @@ -0,0 +1,25 @@ +/** @file + + Header file of AMD FCH platform initialization library. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef FCH_PLATFORM_INIT_H_ +#define FCH_PLATFORM_INIT_H_ + +#include +#include +#include +#include +#include +#include + +#include + +#define SPI_BASE 0xFEC10000ul + +#endif // FCH_PLATFORM_INIT_H_ diff --git a/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.c b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.c new file mode 100644 index 0000000000000000000000000000000000000000..11d9ba4daa94eca67ff1ad53a1d550753cd5e045 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.c @@ -0,0 +1,164 @@ +/** @file + + + FCH initialization hook PEI. + + Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "FchPlatformInit.h" +#include + +#define PMCONTROL_REG 0x504 + +/** + Enable LPC IO Port for IPMI KCS interface. + +**/ +VOID +EnableLpcWideIoPort2 ( + IN VOID + ) +{ + if (FixedPcdGet8 (PcdIpmiInterfaceType) == IPMIDeviceInfoInterfaceTypeKCS) { + DEBUG ((DEBUG_INFO, "Enabling wide io port 2.\n")); + // + // Pleaser refer AMD PPR Vol 3 for respective Family/Model SoC + // for detail information. + // + + // + // Offset 0x090 (FCH::ITF::LPC::WIDE_IO_2) + // IO_Base_Address_2. 16-bit PCI I/O base address for + // wide generic port range. + // + PciWrite16 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + 0x90 + ), + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress) + ); + + // + // Offset 0x048 (FCH::ITF::LPC::IO_MEM_PORT_DECODE_ENABLE) + // Enables Wide IO port 2 (defined in registers 90/91h) enable. + // + PciWrite8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + (FCH_LPC_REG48 + 3) + ), + 0x2 + ); + + // + // Offset 0x074 (FCH::ITF::LPC::ALTERNATIVE_WIDE_IO_RANGE_ENABLE) + // Alternative_Wide_Io_2_Range_Enable to I/O address defined in + // reg0x90 and reg0x91. + // + PciWrite8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REG74 + ), + 0x8 + ); // Enable BIT3 for Alternative_Wide_Io_2_Range_Enable + } +} + +/** + Enable SPI TPM + +**/ +VOID +EnableSpiTpm ( + IN VOID + ) +{ + // Set TPM Decode + PciAndThenOr8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REG7C + ), + 0xFF, + 0x85 + ); + + // Set RouteTpm2Spi + PciAndThenOr8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REGA0 + ), + 0xFF, + 0x08 + ); + + // Set AGPIO76 As SPI_TPM_CS_L + MmioWrite8 ( + ACPI_MMIO_BASE + IOMUX_BASE + 0x4C, + ((MmioRead8 (ACPI_MMIO_BASE + IOMUX_BASE + 0x4C) & 0xFF) | 0x01) + ); +} + +/** + Clear SCI_EN bit in PMCONTROL register + +**/ +VOID +ClearSciEn ( + IN VOID + ) +{ + // Clear SCI_EN bit in PMCONTROL register + MmioWrite32 ( + ACPI_MMIO_BASE + PMIO_BASE + PMCONTROL_REG, + (MmioRead32 (ACPI_MMIO_BASE + PMIO_BASE + PMCONTROL_REG) & (~(UINT32) BIT0)) + ); +} + +/** + Entry point for FCH intialization PEIM + + @param FileHandle Pointer to the FFS file header. + @param PeiServices Pointer to the PEI services table. + + @retval EFI_STATUS EFI_SUCCESS + EFI_STATUS respective failure status. +**/ +EFI_STATUS +EFIAPI +FchInitEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG ((DEBUG_INFO, "Entered %a Platform FCH initialization.\n", __func__)); + + EnableLpcWideIoPort2 (); + EnableSpiTpm (); + ClearSciEn (); + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf new file mode 100644 index 0000000000000000000000000000000000000000..0ba0bc9398da428fbfd67cba76baf4c3f31d9586 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf @@ -0,0 +1,41 @@ +## @file +# +# INF file of AMD FCH initialization hook PEI library +# +# Copyright (C) 2023-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = FchPLatformInitPei + FILE_GUID = 520A04A3-1BAB-4E24-AF12-859F5D632B58 + MODULE_TYPE = PEIM + ENTRY_POINT = FchInitEntry + +[Sources] + FchPlatformInitPei.c + FchPlatformInit.h + +[Packages] + AgesaModulePkg/AgesaModuleFchPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + IoLib + PcdLib + PciLib + PeimEntryPoint + +[Pcd] + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLpcEnable + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress + +[Depex] + TRUE + diff --git a/Platform/AMD/TurinBoard/VolcanoBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000000000000000000000000000000000..f57a5743493cb1d5a1282a8d04fd3e635c222d4c --- /dev/null +++ b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,243 @@ +## @file +# +# Smbios Platform description. +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesignatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesignatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesignatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesignatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesignatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesignatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesignatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesignatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesignatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesignatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesignatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesignatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesignatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesignatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesignatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesignatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesignatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesignatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesignatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.IntDesignatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[10].DesinatorStr.ExtDesignatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.IntDesignatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[11].DesinatorStr.ExtDesignatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.IntDesignatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[12].DesinatorStr.ExtDesignatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.IntDesignatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[13].DesinatorStr.ExtDesignatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.dsc new file mode 100644 index 0000000000000000000000000000000000000000..3e5b308a4cbfca57d894a1612a75e576706ada06 --- /dev/null +++ b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.dsc @@ -0,0 +1,198 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Volcano +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "VOLCANO " + + DEFINE SATA_OVERRIDE = TRUE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = TRUE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"A0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"A1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204f4e41434C4F56 # "VOLCANO " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdEspiOffset|0x20000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|135 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable2|0x30 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.fdf new file mode 100644 index 0000000000000000000000000000000000000000..2a1a93e93633c4d6493ad6da5101b59b1362b819 --- /dev/null +++ b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.fdf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0xFF + DEFINE EFS_ESPI_BYTE1 = 0x0E +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf