diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index 75f196d145beb205ed196711eca78d7ea0615674..d4003324f889c45249548a547109c2222aa3c61b 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -89,8 +89,6 @@ body: - Platform/Ampere/Tools - Platform/BeagleBoard/BeagleBoardPkg - Platform/Bosc/XiangshanSeriesPkg - - Platform/Hisilicon/D03 - - Platform/Hisilicon/D05 - Platform/Hisilicon/D06 - Platform/Hisilicon/HiKey - Platform/Hisilicon/HiKey960 diff --git a/CODEOWNERS b/CODEOWNERS index 4054699ca9b7debb259aab567b23af690533ead4..a1cb4c6d0d78e68e5a0bf51383b688f0dac1487c 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -50,10 +50,6 @@ /Features/Ext4Pkg/** @heatd -# HiSilicon -/Platform/Hisilicon/** @leiflindholm -/Silicon/Hisilicon/** @leiflindholm - /Features/Intel/** @nate-desimone @SaiChaganty /Features/Intel/Debugging/** @nate-desimone @SaiChaganty @ydong10 /Features/Intel/OutOfBandManagement/IpmiFeaturePkg/** @nate-desimone @SaiChaganty diff --git a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini deleted file mode 100644 index dd575965c6dd023ec07f3c3bfe4c11b5feeacc5e..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini +++ /dev/null @@ -1,39 +0,0 @@ -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Head] -NumOfUpdate = 3 -NumOfRecovery = 0 -Update0 = SysFvMain -Update1 = SysCustom -Update2 = SysNvRam - -[SysFvMain] -FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x00000000 # Base address offset on flash -Length = 0x002D0000 # Length -ImageOffset = 0x00000000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - -[SysCustom] -FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x002F0000 # Base address offset on flash -Length = 0x00010000 # Length -ImageOffset = 0x002F0000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - -[SysNvRam] -FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x002D0000 # Base address offset on flash -Length = 0x00020000 # Length -ImageOffset = 0x002D0000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/Hisilicon/D03/D03.dec b/Platform/Hisilicon/D03/D03.dec deleted file mode 100644 index 206a632d5b4a4933f10a41753f1253791b3decac..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/D03.dec +++ /dev/null @@ -1,38 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -# -# D03 Package -# -# -# - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = D03Pkg - PACKAGE_GUID = D42C5D53-63FA-4FBA-9FD4-E8EA684FD3BE - PACKAGE_VERSION = 0.1 - -[Includes] - Include - -[Ppis] - -[Protocols] - -[Guids] - - -[LibraryClasses] - -[PcdsFixedAtBuild] - -[PcdsFeatureFlag] - - diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc deleted file mode 100644 index 522c94e169762671ab06bdc03596ad419553db51..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/D03.dsc +++ /dev/null @@ -1,514 +0,0 @@ -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - PLATFORM_NAME = D03 - PLATFORM_GUID = e5003abd-8809-6194-ac3d-a6a99ff52478 - PLATFORM_VERSION = 0.1 - DSC_SPECIFICATION = 0x00010005 - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 - BUILD_TARGETS = NOOPT|DEBUG|RELEASE - SKUID_IDENTIFIER = DEFAULT - FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf - - # - # Network definition - # - DEFINE NETWORK_SNP_ENABLE = FALSE - DEFINE NETWORK_IP6_ENABLE = FALSE - DEFINE NETWORK_TLS_ENABLE = FALSE - DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE - DEFINE NETWORK_ISCSI_ENABLE = FALSE - DEFINE NETWORK_VLAN_ENABLE = FALSE - -!include Silicon/Hisilicon/Hisilicon.dsc.inc -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses.common] - ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf - - I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf - TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf - - IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf - - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - - -!ifdef $(FDT_ENABLE) - #FDTUpdateLib - FdtUpdateLib|Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf -!endif #$(FDT_ENABLE) - - CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf - - SerdesLib|Silicon/Hisilicon/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf - - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf - RealTimeClockLib|Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf - - HisiOemMiscLib|Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/HisiOemMiscLib2PHi1610.inf - OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf - PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf - - BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf - - # USB Requirements - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - - LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf - PlatformPciLib|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf - SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf - PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf - PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf - PciPlatformLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf - -## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when -## input signal is de-asserted, except for virtual timer interrupt IRQ #27. -## So we choose to use virtual timer instead of physical one as a workaround. -## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. -[LibraryClasses.AARCH64] - ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf - -[LibraryClasses.common.SEC] - ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf - - -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf - SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf - -[BuildOptions] - GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1610/Include - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - - ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. - # It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE - gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE - -[PcdsDynamicExDefault.common.DEFAULT] - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 - gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89} - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55} - -[PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 - gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0 - - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 - - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x81000000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 - - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 - - - gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 - - - # Size of the region used by UEFI in permanent memory (Reserved 64MB) - gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 - - gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 - gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 - - - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x7 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3 - - ## Serial Terminal - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2F8 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - - gHisiTokenSpaceGuid.PcdUartClkInHz|1846100 - - gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000 - - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 - - - gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 - gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 - gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 - gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - - - !ifdef $(FIRMWARE_VER) - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" - !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 19.02 for Hisilicon D03" - !endif - - gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" - - gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"19.02" - - gHisiTokenSpaceGuid.PcdSystemProductName|L"D03" - gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" - gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D03" - gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" - - gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1612" - - # - # ARM PL390 General Interrupt Controller - # - - gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 - gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000 - - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } - - gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 - gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 - - gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000 - - gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 - gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 - - - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000 - - - gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000 - - gHisiTokenSpaceGuid.FdtFileAddress|0xA47C0000 - - gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 - - gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 - - gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 - - gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x2000000000 - - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 - gHisiTokenSpaceGuid.PcdNumaEnable|0 - - gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000 - - - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xB0000000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x8000000 - - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xB0000000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 - - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 - - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xAC000000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x4000000 - - gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000 - gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000 - gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000 - gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000 - - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xb2000000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0x5feffff - - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb8000000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x5feffff - - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xaa000000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x5feffff - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xB2000000 - gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xB8000000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xAA000000 - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xb7ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xbdff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xAfff0000 - - gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K - - gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K - - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K - - gHisiTokenSpaceGuid.Pcdsoctype|0x1610 - -################################################################################ -# -# Components Section - list of all EDK II Modules needed by this Platform -# -################################################################################ -[Components.common] - - # - # SEC - # - - # - # PEI Phase modules - # - ArmPlatformPkg/Sec/Sec.inf - MdeModulePkg/Core/Pei/PeiMain.inf - MdeModulePkg/Universal/PCD/Pei/Pcd.inf { - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - } - Platform/Hisilicon/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf - - ArmPlatformPkg/PlatformPei/PlatformPeim.inf - - Platform/Hisilicon/D03/MemoryInitPei/MemoryInitPeim.inf - ArmPkg/Drivers/CpuPei/CpuPei.inf - MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf - MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf - MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - - Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf - Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf - - Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - - MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - } - - # - # DXE - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf - } - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - } - - Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf - - # - # Architectural Protocols - # - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - - ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf - - Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf - - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - - MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { - - CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf - } - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - # Simple TextIn/TextOut for UEFI Terminal - EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf - - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - ArmPkg/Drivers/ArmGicDxe/ArmGicV3Dxe.inf - - ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - # - #ACPI - # - MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - - Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf - Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - - # - # Usb Support - # - Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf - MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf - MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - Platform/Hisilicon/D03/Drivers/OhciDxe/OhciDxe.inf - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf - - Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf - -!include NetworkPkg/Network.dsc.inc - Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf - - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf - } - MdeModulePkg/Application/HelloWorld/HelloWorld.inf - # - # Bds - # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - Platform/Hisilicon/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf - Platform/Hisilicon/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf - Platform/Hisilicon/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf - - Platform/Hisilicon/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf - - MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf - -!ifdef $(FDT_ENABLE) - Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { - - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } -!endif #$(FDT_ENABLE) - - #PCIe Support - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf { - - NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf - } - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf { - - NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf - } - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - - NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf - } - - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf - Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf - Platform/Hisilicon/Drivers/Sm750Dxe/UefiSmi.inf - - Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf - Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf - - - Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf - - # - # Memory test - # - MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { - - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf - } - - MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf - - # - # UEFI application (Shell Embedded Boot Loader) - # - ShellPkg/Application/Shell/Shell.inf { - - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf - OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf -!ifdef $(INCLUDE_DP) - NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf -!endif #$(INCLUDE_DP) - - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 - } -!ifdef $(INCLUDE_TFTP_COMMAND) - ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { - - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - } -!endif #$(INCLUDE_TFTP_COMMAND) diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf deleted file mode 100644 index 7badb3e6d1d4e99863dda96cb0fa16ea56821e32..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/D03.fdf +++ /dev/null @@ -1,401 +0,0 @@ -# -# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[DEFINES] - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ - -[FD.D03] -BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. - -Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device -ErasePolarity = 1 - -# This one is tricky, it must be: BlockSize * NumBlocks = Size -BlockSize = 0x00010000 -NumBlocks = 0x30 - -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# -################################################################################ - -0x00000000|0x00040000 -gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize -FILE = Platform/Hisilicon/D03/Sec/FVMAIN_SEC.Fv - -0x00040000|0x00240000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV = FVMAIN_COMPACT - -0x00280000|0x00020000 -gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base -FILE = Platform/Hisilicon/D03/bl1.bin -0x002A0000|0x00020000 -FILE = Platform/Hisilicon/D03/fip.bin - -0x002D0000|0x0000E000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -DATA = { - ## This is the EFI_FIRMWARE_VOLUME_HEADER - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - # FileSystemGuid: gEfiSystemNvDataFvGuid = - 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, - 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, - # FvLength: 0x20000 - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - #Signature "_FVH" #Attributes - 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, - #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision - 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, - #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - #Blockmap[1]: End - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid - 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, - 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, - #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 - 0xB8, 0xdF, 0x00, 0x00, - #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 - 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -0x002DE000|0x00002000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -#NV_FTW_WORKING -DATA = { - # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = - 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, - 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, - # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved - 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, - # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 - 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -0x002E0000|0x00010000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - -0x002F0000|0x00010000 -FILE = Platform/Hisilicon/D0x-CustomData.Fv - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ - -[FV.FvMain] -BlockSize = 0x40 -NumBlocks = 0 # This FV gets compressed so make it just big enough -FvAlignment = 16 # FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - INF Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - INF Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf - - INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf - - - INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf - INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # Multiple Console IO support - # - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - # Simple TextIn/TextOut for UEFI Terminal - - INF ArmPkg/Drivers/ArmGicDxe/ArmGicV3Dxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - - # - # Usb Support - # - - INF Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf - INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf - INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - INF Platform/Hisilicon/D03/Drivers/OhciDxe/OhciDxe.inf - INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - INF Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf - INF Platform/Hisilicon/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf - INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf - - INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf - INF Platform/Hisilicon/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf - INF Platform/Hisilicon/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf - - INF Platform/Hisilicon/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf - - - INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf - - INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf - - # - #ACPI - # - INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf - - INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf - INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - - # - #Network - # - - INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf - INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf - -!include NetworkPkg/Network.fdf.inc - -!ifdef $(FDT_ENABLE) - INF Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf -!endif #$(FDT_ENABLE) - - # - # PCI Support - # - INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf - INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - INF Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf - # VGA Driver - # - INF Platform/Hisilicon/Drivers/Sm750Dxe/UefiSmi.inf - - INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf - INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf - - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - # - # Build Shell from latest source code instead of prebuilt binary - # - INF ShellPkg/Application/Shell/Shell.inf -!ifdef $(INCLUDE_TFTP_COMMAND) - INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) - - INF MdeModulePkg/Application/UiApp/UiApp.inf - # - # Bds - # - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - -[FV.FVMAIN_COMPACT] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF ArmPlatformPkg/Sec/Sec.inf - INF MdeModulePkg/Core/Pei/PeiMain.inf - INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf - - INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - - INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf - - INF Platform/Hisilicon/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf - INF Platform/Hisilicon/D03/MemoryInitPei/MemoryInitPeim.inf - INF ArmPkg/Drivers/CpuPei/CpuPei.inf - INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf - INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf - INF Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf - - INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf - - INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } - } - -[FV.CapsuleDispatchFv] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf - -[FV.SystemFirmwareUpdateCargo] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid - FD = D03 - } - - FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid - FV = CapsuleDispatchFv - } - - FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid - Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini - } - -[FmpPayload.FmpPayloadSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 -IMAGE_TYPE_ID = 44c850f2-85ff-4be5-bf34-a59528df22d3 # PcdSystemFmpCapsuleImageTypeIdGuid -IMAGE_INDEX = 0x1 -HARDWARE_INSTANCE = 0x0 -MONOTONIC_COUNT = 0x1 -CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 - - FV = SystemFirmwareUpdateCargo - -[Capsule.D03FirmwareUpdateCapsuleFmpPkcs7] -CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid -CAPSULE_HEADER_SIZE = 0x20 -CAPSULE_HEADER_INIT_VERSION = 0x1 - - FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7 - -!include Silicon/Hisilicon/Hisilicon.fdf.inc - diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h deleted file mode 100644 index 94d904c35f88c5a56d60b25519498f2814395c2c..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __OEM_NIC_CONFIG_H__ -#define __OEM_NIC_CONFIG_H__ - -#define I2C_SLAVEADDR_EEPROM (0x52) - -#define I2C_OFFSET_EEPROM_ETH0 (0xc00) -#define I2C_OFFSET_EEPROM_ETH1 (I2C_OFFSET_EEPROM_ETH0 + 6) -#define I2C_OFFSET_EEPROM_ETH2 (I2C_OFFSET_EEPROM_ETH1 + 6) -#define I2C_OFFSET_EEPROM_ETH3 (I2C_OFFSET_EEPROM_ETH2 + 6) -#define I2C_OFFSET_EEPROM_ETH4 (I2C_OFFSET_EEPROM_ETH3 + 6) -#define I2C_OFFSET_EEPROM_ETH5 (I2C_OFFSET_EEPROM_ETH4 + 6) -#define I2C_OFFSET_EEPROM_ETH6 (I2C_OFFSET_EEPROM_ETH5 + 6) -#define I2C_OFFSET_EEPROM_ETH7 (I2C_OFFSET_EEPROM_ETH6 + 6) - -#define MAC_ADDR_LEN 6 - -#pragma pack(1) -typedef struct { - UINT16 Crc16; - UINT16 MacLen; - UINT8 Mac[MAC_ADDR_LEN]; -} NIC_MAC_ADDRESS; -#pragma pack() - -#endif diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c deleted file mode 100644 index 887c2b5e56aa77432911cd8c14fbb3c40f91a6cf..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c +++ /dev/null @@ -1,356 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define EEPROM_I2C_PORT 6 -#define EEPROM_PAGE_SIZE 0x40 - -EFI_STATUS -EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); - -EFI_STATUS -EFIAPI OemSetMac2P (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port); - -EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr); -EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr); - -volatile unsigned char g_2pserveraddr[4][6] = -{ - {0x00, 0x18, 0x16, 0x29, 0x11, 0x00}, - {0x00, 0x18, 0x16, 0x29, 0x11, 0x01}, - {0x00, 0x18, 0x16, 0x29, 0x11, 0x02}, - {0x00, 0x18, 0x16, 0x29, 0x11, 0x03} -}; - -UINT16 crc_tab[256] = { - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, - 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, - 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, - 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, - 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, - 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, - 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, - 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, - 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, - 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, - 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, - 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, - 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, - 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, - 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, - 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, - 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, - 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, - 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, - 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, - 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, - 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, - 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, -}; - -UINT16 make_crc_checksum(UINT8 *buf, UINT32 len) -{ - UINT16 StartCRC = 0; - - if (len > (512 * 1024)) - { - return 0; - } - - if (NULL == buf) - { - return 0; - } - - while (len) - { - StartCRC = crc_tab[((UINT8)((StartCRC >> 8) & 0xff)) ^ *(buf++)] ^ ((UINT16)(StartCRC << 8)); - len--; - } - - return StartCRC; -} - - -EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) -{ - I2C_DEVICE stI2cDev = {0}; - EFI_STATUS Status; - UINT16 I2cOffset; - UINT16 crc16; - NIC_MAC_ADDRESS stMacDesc = {0}; - UINT16 RemainderMacOffset; - UINT16 LessSizeOfPage; - - Status = I2CInit(0, EEPROM_I2C_PORT, Normal); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __func__, __LINE__, Status)); - return Status; - } - - I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS)); - - stI2cDev.DeviceType = DEVICE_TYPE_E2PROM; - stI2cDev.Port = EEPROM_I2C_PORT; - stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; - stI2cDev.Socket = 0; - RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; - LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; - //The length of NIC_MAC_ADDRESS is 10 bytes long, - //It surly less than EEPROM page size, so we could - //code as bellow, check the address whether across the page boundary, - //and split the data when across page boundary. - if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { - Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); - } else { - Status = I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); - if (!(EFI_ERROR(Status))) { - Status |= I2CRead( - &stI2cDev, - I2cOffset + LessSizeOfPage, - sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, - (UINT8 *)&stMacDesc + LessSizeOfPage - ); - } - } - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __func__, __LINE__, Status)); - return Status; - } - - crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + sizeof(stMacDesc.Mac)); - if ((crc16 != stMacDesc.Crc16) || (0 == crc16)) - { - return EFI_NOT_FOUND; - } - - gBS->CopyMem((VOID *)(pucAddr), (VOID *)(stMacDesc.Mac), MAC_ADDR_LEN); - - - return EFI_SUCCESS; -} - - -EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) -{ - I2C_DEVICE stI2cDev = {0}; - EFI_STATUS Status; - UINT16 I2cOffset; - NIC_MAC_ADDRESS stMacDesc = {0}; - - - stMacDesc.MacLen = MAC_ADDR_LEN; - UINT16 RemainderMacOffset; - UINT16 LessSizeOfPage; - gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN); - - stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN); - - Status = I2CInit(0, EEPROM_I2C_PORT, Normal); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __func__, __LINE__, Status)); - return Status; - } - - I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS)); - - stI2cDev.DeviceType = DEVICE_TYPE_E2PROM; - stI2cDev.Port = EEPROM_I2C_PORT; - stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; - stI2cDev.Socket = 0; - RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; - LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; - //The length of NIC_MAC_ADDRESS is 10 bytes long, - //It surly less than EEPROM page size, so we could - //code as bellow, check the address whether across the page boundary, - //and split the data when across page boundary. - if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { - Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); - } else { - Status = I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); - if (!(EFI_ERROR(Status))) { - Status |= I2CWrite( - &stI2cDev, - I2cOffset + LessSizeOfPage, - sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, - (UINT8 *)&stMacDesc + LessSizeOfPage - ); - } - } - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __func__, __LINE__, Status)); - return Status; - } - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI OemGetMac2P ( - IN OUT EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ) -{ - EFI_STATUS Status; - - if (NULL == Mac) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - Status = OemGetMacE2prom(Port, Mac->Addr); - if ((EFI_ERROR(Status))) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Get mac failed!\n", __func__, __LINE__)); - - Mac->Addr[0] = 0x00; - Mac->Addr[1] = 0x18; - Mac->Addr[2] = 0x82; - Mac->Addr[3] = 0x2F; - Mac->Addr[4] = 0x02; - Mac->Addr[5] = Port; - return Status; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI OemSetMac2P ( - IN EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ) -{ - EFI_STATUS Status; - - if (NULL == Mac) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - Status = OemSetMacE2prom(Port, Mac->Addr); - if ((EFI_ERROR(Status))) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Set mac failed!\n", __func__, __LINE__)); - return Status; - } - - return EFI_SUCCESS; -} - -HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = { - .GetMac = OemGetMac2P, - .SetMac = OemSetMac2P, -}; - -VOID OemFeedbackXGeStatus(BOOLEAN IsLinkup, BOOLEAN IsActOK, UINT32 port) -{ - UINT8 CpldValue = 0; - UINTN RegOffset = 0x10 + (UINTN)port * 4; - - if (port > 2) - { - return; - } - - if (IsLinkup) - { - CpldValue = ReadCpldReg(RegOffset); - CpldValue |= BIT2; - WriteCpldReg(RegOffset, CpldValue); - } - else - { - CpldValue = ReadCpldReg(RegOffset); - CpldValue &= ~((UINT8)BIT2); - WriteCpldReg(RegOffset, CpldValue); - } - - if (IsActOK) - { - CpldValue = ReadCpldReg(RegOffset); - CpldValue |= BIT4; - WriteCpldReg(RegOffset, CpldValue); - } - else - { - CpldValue = ReadCpldReg(RegOffset); - CpldValue &= ~((UINT8)BIT4); - WriteCpldReg(RegOffset, CpldValue); - } -} - -HISI_BOARD_XGE_STATUS_PROTOCOL mHisiBoardXgeStatusProtocol2p = { - .FeedbackXgeStatus = OemFeedbackXGeStatus, -}; - - -EFI_STATUS -EFIAPI -OemNicConfigEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - Status = gBS->InstallProtocolInterface( - &ImageHandle, - &gHisiBoardNicProtocolGuid, - EFI_NATIVE_INTERFACE, - &mHisiBoardNicProtocol2P - ); - - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __func__, __LINE__, Status)); - return Status; - } - - Status = gBS->InstallProtocolInterface( - &ImageHandle, - &gHisiBoardXgeStatusProtocolGuid, - EFI_NATIVE_INTERFACE, - &mHisiBoardXgeStatusProtocol2p - ); - - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __func__, __LINE__, Status)); - return Status; - } - - return EFI_SUCCESS; -} - diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf deleted file mode 100644 index 1071f5d651f5e55cadeb60604e47fe9438cd63d0..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = OemNicConfigPangea - FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = OemNicConfigEntry - -[Sources.common] - OemNicConfig2P.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[Protocols] - gHisiBoardNicProtocolGuid ##Produce - gHisiBoardXgeStatusProtocolGuid - -[LibraryClasses] - CpldIoLib - UefiDriverEntryPoint - UefiBootServicesTableLib - DebugLib - IoLib - TimerLib - I2CLib - PcdLib - -[FixedPcd] - -[Depex] - TRUE - -[BuildOptions] - diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc deleted file mode 100644 index 52149b1ed08c618b20960d3a0db159a09a01106f..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc +++ /dev/null @@ -1,75 +0,0 @@ -/** @file - System Firmware descriptor. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include - -#define PACKAGE_VERSION 0xFFFFFFFF -#define PACKAGE_VERSION_STRING L"Unknown" - -#define CURRENT_FIRMWARE_VERSION 0x00000002 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002" -#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 - -#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd') -#define IMAGE_ID_STRING L"ARMPlatformFd" - -// PcdSystemFmpCapsuleImageTypeIdGuid -#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } } - -typedef struct { - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; - // real string data - CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE_ID_STRING)]; - CHAR16 VersionNameStr[ARRAY_SIZE (CURRENT_FIRMWARE_VERSION_STRING)]; - CHAR16 PackageVersionNameStr[ARRAY_SIZE (PACKAGE_VERSION_STRING)]; -} IMAGE_DESCRIPTOR; - -IMAGE_DESCRIPTOR mImageDescriptor = -{ - { - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, - sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), - sizeof (IMAGE_DESCRIPTOR), - PACKAGE_VERSION, // PackageVersion - OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName - 1, // ImageIndex; - {0x0}, // Reserved - IMAGE_TYPE_ID_GUID, // ImageTypeId; - IMAGE_ID, // ImageId; - OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; - CURRENT_FIRMWARE_VERSION, // Version; - OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; - {0x0}, // Reserved2 - FixedPcdGet32 (PcdFdSize), // Size; - IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | - IMAGE_ATTRIBUTE_RESET_REQUIRED | - IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported; - IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | - IMAGE_ATTRIBUTE_RESET_REQUIRED | - IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting; - 0x0, // Compatibilities; - LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; - 0x00000000, // LastAttemptVersion; - 0, // LastAttemptStatus; - {0x0}, // Reserved3 - 0, // HardwareInstance; - }, - // real string data - {IMAGE_ID_STRING}, - {CURRENT_FIRMWARE_VERSION_STRING}, - {PACKAGE_VERSION_STRING}, -}; - -VOID* CONST ReferenceAcpiTable = &mImageDescriptor; diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf deleted file mode 100644 index 67568145740265c5ecb22f7599b00f140577a945..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ /dev/null @@ -1,44 +0,0 @@ -## @file -# System Firmware descriptor. -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = SystemFirmwareDescriptor - FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = SystemFirmwareDescriptorPeimEntry - -[Sources] - SystemFirmwareDescriptorPei.c - SystemFirmwareDescriptor.aslc - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - SignedCapsulePkg/SignedCapsulePkg.dec - -[LibraryClasses] - DebugLib - PcdLib - PeimEntryPoint - PeiServicesLib - -[FixedPcd] - gArmTokenSpaceGuid.PcdFdSize - -[Pcd] - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor - -[Depex] - TRUE diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c deleted file mode 100644 index 77f631d5d6f149960b600875721ce50006e65ae0..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c +++ /dev/null @@ -1,64 +0,0 @@ -/** @file - System Firmware descriptor producer. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -/** - Entrypoint for SystemFirmwareDescriptor PEIM. - - @param[in] FileHandle Handle of the file being invoked. - @param[in] PeiServices Describes the list of possible PEI Services. - - @retval EFI_SUCCESS PPI successfully installed. -**/ -EFI_STATUS -EFIAPI -SystemFirmwareDescriptorPeimEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; - UINTN Size; - UINTN Index; - UINT32 AuthenticationStatus; - - // - // Search RAW section. - // - - Index = 0; - while (TRUE) { - Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus); - if (EFI_ERROR (Status)) { - // Should not happen, must something wrong in FDF. - DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n")); - return EFI_NOT_FOUND; - } - if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) { - break; - } - Index++; - } - - DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length)); - - Size = Descriptor->Length; - PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); - - return EFI_SUCCESS; -} diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c deleted file mode 100644 index 07e9fbbe8316f95a010cb37b2dedd1d65436e18a..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c +++ /dev/null @@ -1,174 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#define PERI_SUBCTRL_BASE (0x40000000) -#define MDIO_SUBCTRL_BASE (0x60000000) -#define PCIE2_SUBCTRL_BASE (0xA0000000) -#define PCIE0_SUBCTRL_BASE (0xB0000000) -#define ALG_BASE (0xD0000000) - -#define SC_BROADCAST_EN_REG (0x16220) -#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230) -#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234) -#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238) -#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C) -#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240) -#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C) -#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200) -#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0) -#define SC_TM_CLKEN0_REG (0x2050) - -#define SC_TM_CLKEN0_REG_VALUE (0x3) -#define SC_BROADCAST_EN_REG_VALUE (0x7) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400) -#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7) -#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e) - -VOID PlatformTimerStart (VOID) -{ - // Timer0 clock enable - MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE); -} - -void QResetAp(VOID) -{ - MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); - (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); - ArmDataSynchronizationBarrier (); - ArmInstructionSynchronizationBarrier (); - - //SCCL A - if (!PcdGet64 (PcdTrustedFirmwareEnable)) - { - StartUpBSP (); - } -} - - -EFI_STATUS -EFIAPI -EarlyConfigEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - DEBUG((DEBUG_INFO,"SMMU CONFIG.........")); - (VOID)SmmuConfigForOS(); - DEBUG((DEBUG_INFO,"Done\n")); - - - DEBUG((DEBUG_INFO,"AP CONFIG.........")); - (VOID)QResetAp(); - DEBUG((DEBUG_INFO,"Done\n")); - - DEBUG((DEBUG_INFO,"MN CONFIG.........")); - (VOID)MN_CONFIG(); - DEBUG((DEBUG_INFO,"Done\n")); - - if(OemIsMpBoot()) - { - DEBUG((DEBUG_INFO,"Event Broadcast CONFIG.........")); - //EVENT broadcast - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); - MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); - - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); - MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); - - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); - MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); - - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); - MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); - - DEBUG((DEBUG_INFO,"Done\n")); - } - - DEBUG((DEBUG_INFO,"PCIE RAM Address CONFIG.........")); - - if(OemIsMpBoot()) - { - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0); - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0); - MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1); - MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0); - MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1); - } - - else - { - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0); - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2); - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0); - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0); - MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0); - } - - DEBUG((DEBUG_INFO,"Done\n")); - - MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE); - - DEBUG((DEBUG_INFO,"Timer CONFIG.........")); - PlatformTimerStart (); - DEBUG((DEBUG_INFO,"Done\n")); - - return EFI_SUCCESS; -} - diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf deleted file mode 100644 index 1f992024acc289e1faf37332750bb78551e2a8fa..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf +++ /dev/null @@ -1,50 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = EarlyConfigPeimD03 - FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = EarlyConfigEntry - -[Sources.common] - EarlyConfigPeimD03.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - - ArmPkg/ArmPkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - PeimEntryPoint - PcdLib - DebugLib - IoLib - CacheMaintenanceLib - - PlatformSysCtrlLib - ArmLib - -[Pcd] - gHisiTokenSpaceGuid.PcdMailBoxAddress - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - -[Depex] -## As we will clean mailbox in this module, need to wait memory init complete - gEfiPeiMemoryDiscoveredPpiGuid - -[BuildOptions] - diff --git a/Platform/Hisilicon/D03/Include/Library/CpldD03.h b/Platform/Hisilicon/D03/Include/Library/CpldD03.h deleted file mode 100644 index fce3319c448264e68a40f934c812e933f31de2e2..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Include/Library/CpldD03.h +++ /dev/null @@ -1,19 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __CPLD_D03_H__ -#define __CPLD_D03_H__ - -#define CPLD_BIOSINDICATE_FLAG 0x09 -#define CPLD_I2C_SWITCH_FLAG 0x17 -#define CPU_GET_I2C_CONTROL BIT2 -#define BMC_I2C_STATUS BIT3 - - -#endif diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h deleted file mode 100644 index da18d0f5589e9781a95531f4b4541eaa9a150cfa..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h +++ /dev/null @@ -1,172 +0,0 @@ -/** @file -* -* Copyright (c) 2011, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf -**/ - - -#ifndef __DS3231_REAL_TIME_CLOCK_H__ -#define __DS3231_REAL_TIME_CLOCK_H__ - -#define DS3231_REGADDR_SECONDS 0x00 -#define DS3231_REGADDR_MIUTES 0x01 -#define DS3231_REGADDR_HOURS 0x02 -#define DS3231_REGADDR_DAY 0x03 -#define DS3231_REGADDR_DATE 0x04 -#define DS3231_REGADDR_MONTH 0x05 -#define DS3231_REGADDR_YEAR 0x06 -#define DS3231_REGADDR_ALARM1SEC 0x07 -#define DS3231_REGADDR_ALARM1MIN 0x08 -#define DS3231_REGADDR_ALARM1HOUR 0x09 -#define DS3231_REGADDR_ALARM1DAY 0x0A -#define DS3231_REGADDR_ALARM2MIN 0x0B -#define DS3231_REGADDR_ALARM2HOUR 0x0C -#define DS3231_REGADDR_ALARM2DAY 0x0D -#define DS3231_REGADDR_CONTROL 0x0E -#define DS3231_REGADDR_STATUS 0x0F -#define DS3231_REGADDR_AGOFFSET 0x10 -#define DS3231_REGADDR_TEMPMSB 0x11 -#define DS3231_REGADDR_TEMPLSB 0x12 - - -typedef union { - struct{ - UINT8 A1IE:1; - UINT8 A2IE:1; - UINT8 INTCN:1; - UINT8 RSV:2; - UINT8 CONV:1; - UINT8 BBSQW:1; - UINT8 EOSC_N:1; - }bits; - UINT8 u8; -}RTC_DS3231_CONTROL; - -typedef union { - struct{ - UINT8 A1F:1; - UINT8 A2F:1; - UINT8 BSY:1; - UINT8 EN32KHZ:2; - UINT8 Rsv:3; - UINT8 OSF:1; - }bits; - UINT8 u8; -}RTC_DS3231_STATUS; - - -typedef union { - struct{ - UINT8 Data:7; - UINT8 Sign:1; - }bits; - UINT8 u8; -}RTC_DS3231_AGOFFSET; - -typedef union { - struct{ - UINT8 Data:7; - UINT8 Sign:1; - }bits; - UINT8 u8; -}RTC_DS3231_TEMPMSB; - - -typedef union { - struct{ - UINT8 Rsv:6; - UINT8 Data:2; - }bits; - UINT8 u8; -}RTC_DS3231_TEMPLSB; - -typedef union { - struct{ - UINT8 Seconds:4; - UINT8 Seconds10:3; - UINT8 Rsv:1; - }bits; - UINT8 u8; -}RTC_DS3231_SECONDS; - -typedef union { - struct{ - UINT8 Minutes:4; - UINT8 Minutes10:3; - UINT8 Rsv:1; - }bits; - UINT8 u8; -}RTC_DS3231_MINUTES; - -typedef union { - struct{ - UINT8 Hour:4; - UINT8 Hours10:1; - UINT8 PM_20Hours:1; - UINT8 Hour24_n:1; - UINT8 Rsv:1; - }bits; - UINT8 u8; -}RTC_DS3231_HOURS; - -typedef union { - struct{ - UINT8 Day:3; - UINT8 Rsv:5; - }bits; - UINT8 u8; -}RTC_DS3231_DAY; - -typedef union { - struct{ - UINT8 Month:4; - UINT8 Month10:1; - UINT8 Rsv:2; - UINT8 Century:1; - }bits; - UINT8 u8; -}RTC_DS3231_MONTH; - -typedef union { - struct{ - UINT8 Year:4; - UINT8 Year10:4; - }bits; - UINT8 u8; -}RTC_DS3231_YEAR; - -typedef union { - struct{ - UINT8 Seconds:4; - UINT8 Seconds10:3; - UINT8 A1M1:1; - }bits; - UINT8 u8; -}RTC_DS3231_ALARM1SEC; - -typedef union { - struct{ - UINT8 Minutes:4; - UINT8 Minutes10:3; - UINT8 A1M2:1; - }bits; - UINT8 u8; -}RTC_DS3231_ALARM1MIN; - -typedef union { - struct{ - UINT8 Hour:4; - UINT8 Hours10:1; - UINT8 PM_20Hours:1; - UINT8 Hours24:1; - UINT8 A1M3:1; - }bits; - UINT8 u8; -}RTC_DS3231_ALARM1HOUR; - -#endif diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c deleted file mode 100644 index 544dc0539bbb36379a0832b39a3e36d681ef202d..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c +++ /dev/null @@ -1,452 +0,0 @@ -/** @file - Implement EFI RealTimeClock runtime services via RTC Lib. - - Currently this driver does not support runtime virtual calling. - - Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
- Copyright (c) 2011-2013, ARM Ltd. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf - -**/ - -#include -#include -#include -#include -#include -#include -// Use EfiAtRuntime to check stage -#include -#include -#include -#include -#include -#include -#include -#include "DS3231RealTimeClock.h" -#include -#include - -extern I2C_DEVICE gRtcDevice; - -STATIC BOOLEAN mDS3231Initialized = FALSE; - -EFI_STATUS -IdentifyDS3231 ( - VOID - ) -{ - EFI_STATUS Status; - - Status = EFI_SUCCESS; - return Status; -} - -EFI_STATUS -SwitchRtcI2cChannelAndLock ( - VOID - ) -{ - UINT8 Temp; - UINT8 Count; - - for (Count = 0; Count < 20; Count++) { - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - - if ((Temp & BMC_I2C_STATUS) != 0) { - //The I2C channel is shared with BMC, - //Check if BMC has taken ownership of I2C. - //If so, wait 30ms, then try again. - //If not, start using I2C. - //And the CPLD_I2C_SWITCH_FLAG will be set to CPU_GET_I2C_CONTROL - //BMC will check this flag to decide to use I2C or not. - MicroSecondDelay (30000); - continue; - } - - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp | CPU_GET_I2C_CONTROL; - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - - //This is empirical value,give cpld some time to make sure the - //value is wrote in - MicroSecondDelay (2); - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - - if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL) { - return EFI_SUCCESS; - } - - //There need 30ms to keep consistent with the previous loops if the CPU failed - //to get control of I2C - MicroSecondDelay (30000); - } - - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp & ~CPU_GET_I2C_CONTROL; - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - - return EFI_NOT_READY; -} - - -EFI_STATUS -InitializeDS3231 ( - VOID - ) -{ - EFI_STATUS Status; - I2C_DEVICE Dev; - RTC_DS3231_CONTROL Temp; - RTC_DS3231_HOURS Hours; - - // Prepare the hardware - (VOID)IdentifyDS3231(); - - (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev)); - - Status = I2CInit(Dev.Socket,Dev.Port,Normal); - if (EFI_ERROR (Status)) { - goto EXIT; - } - // Ensure interrupts are masked. We do not want RTC interrupts in UEFI - Status = I2CRead(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8); - if (EFI_ERROR (Status)) { - goto EXIT; - } - Temp.bits.INTCN = 0; - Status = I2CWrite(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - MicroSecondDelay(2000); - Status = I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8); - if (EFI_ERROR (Status)) { - goto EXIT; - } - Hours.bits.Hour24_n = 0; - Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - - mDS3231Initialized = TRUE; - - EXIT: - return Status; -} - -/** - Returns the current time and date information, and the time-keeping capabilities - of the hardware platform. - - @param Time A pointer to storage to receive a snapshot of the current time. - @param Capabilities An optional pointer to a buffer to receive the real time clock - device's capabilities. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_INVALID_PARAMETER Time is NULL. - @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. - @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure. -**/ -EFI_STATUS -EFIAPI -LibGetTime ( - OUT EFI_TIME *Time, - OUT EFI_TIME_CAPABILITIES *Capabilities - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINT8 Temp; - UINT8 BaseHour = 0; - - UINT16 BaseYear = 1900; - - I2C_DEVICE Dev; - - // Ensure Time is a valid pointer - if (NULL == Time) { - return EFI_INVALID_PARAMETER; - } - - Status = SwitchRtcI2cChannelAndLock(); - if(EFI_ERROR (Status)) { - return Status; - } - - // Initialize the hardware if not already done - if (!mDS3231Initialized) { - Status = InitializeDS3231 (); - if (EFI_ERROR (Status)) { - Status = EFI_NOT_READY; - goto GExit; - } - } - - (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev)); - - Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp); - - Time->Month = ((Temp>>4)&1)*10+(Temp&0x0F); - - - if(Temp&0x80){ - BaseYear = 2000; - } - - Status |= I2CRead(&Dev,DS3231_REGADDR_YEAR,1,&Temp); - - Time->Year = BaseYear+(Temp>>4) *10 + (Temp&0x0F); - - Status |= I2CRead(&Dev,DS3231_REGADDR_DATE,1,&Temp); - - Time->Day = ((Temp>>4)&3) *10 + (Temp&0x0F); - - Status |= I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Temp); - - BaseHour = 0; - if((Temp&0x30) == 0x30){ - Status = EFI_DEVICE_ERROR; - goto GExit; - }else if(Temp&0x20){ - BaseHour = 20; - }else if(Temp&0x10){ - BaseHour = 10; - } - Time->Hour = BaseHour + (Temp&0x0F); - - Status |= I2CRead(&Dev,DS3231_REGADDR_MIUTES,1,&Temp); - - Time->Minute = ((Temp>>4)&7) * 10 + (Temp&0x0F); - - Status |= I2CRead(&Dev,DS3231_REGADDR_SECONDS,1,&Temp); - - Time->Second = (Temp>>4) * 10 + (Temp&0x0F); - - Time->Nanosecond = 0; - Time->Daylight = 0; - Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; - - if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) { - Status = EFI_UNSUPPORTED; - } - -GExit: - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp & ~CPU_GET_I2C_CONTROL; - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - - return Status; - -} - - -/** - Sets the current local time and date information. - - @param Time A pointer to the current time. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_INVALID_PARAMETER A time field is out of range. - @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. - -**/ -EFI_STATUS -EFIAPI -LibSetTime ( - IN EFI_TIME *Time - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - I2C_DEVICE Dev; - UINT8 Temp; - - UINT16 BaseYear = 1900; - - - - // Check the input parameters are within the range specified by UEFI - if(!IsTimeValid(Time)){ - return EFI_INVALID_PARAMETER; - } - - Status = SwitchRtcI2cChannelAndLock(); - if(EFI_ERROR (Status)) { - return Status; - } - - // Initialize the hardware if not already done - if (!mDS3231Initialized) { - Status = InitializeDS3231 (); - if (EFI_ERROR (Status)) { - goto EXIT; - } - } - - (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev)); - - Temp = ((Time->Second/10)<<4) | (Time->Second%10); - MicroSecondDelay(1000); - Status = I2CWrite(&Dev,DS3231_REGADDR_SECONDS,1,&Temp); - if(EFI_ERROR (Status)){ - goto EXIT; - } - - Temp = ((Time->Minute/10)<<4) | (Time->Minute%10); - MicroSecondDelay(1000); - Status = I2CWrite(&Dev,DS3231_REGADDR_MIUTES,1,&Temp); - if(EFI_ERROR (Status)){ - goto EXIT; - } - - Temp = 0; - if(Time->Hour > 19){ - Temp = 2; - } else if(Time->Hour > 9){ - Temp = 1; - } - - Temp = (Temp << 4) | (Time->Hour%10); - MicroSecondDelay(1000); - Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Temp); - if(EFI_ERROR (Status)){ - goto EXIT; - } - - Temp = ((Time->Day/10)<<4) | (Time->Day%10); - MicroSecondDelay(1000); - Status = I2CWrite(&Dev,DS3231_REGADDR_DATE,1,&Temp); - if(EFI_ERROR (Status)){ - goto EXIT; - } - - - Temp = 0; - if(Time->Year >= 2000){ - Temp = 0x8; - BaseYear = 2000; - } - - if(Time->Month > 9){ - Temp |= 0x1; - } - Temp = (Temp<<4) | (Time->Month%10); - MicroSecondDelay(1000); - Status = I2CWrite(&Dev,DS3231_REGADDR_MONTH,1,&Temp); - if(EFI_ERROR (Status)){ - goto EXIT; - } - - Temp = (((Time->Year-BaseYear)/10)<<4) | (Time->Year%10); - MicroSecondDelay(1000); - Status = I2CWrite(&Dev,DS3231_REGADDR_YEAR,1,&Temp); - if(EFI_ERROR (Status)){ - goto EXIT; - } - - EXIT: - - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp & ~CPU_GET_I2C_CONTROL; - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - - return Status; -} - - -/** - Returns the current wakeup alarm clock setting. - - @param Enabled Indicates if the alarm is currently enabled or disabled. - @param Pending Indicates if the alarm signal is pending and requires acknowledgement. - @param Time The current alarm setting. - - @retval EFI_SUCCESS The alarm settings were returned. - @retval EFI_INVALID_PARAMETER Any parameter is NULL. - @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. - -**/ -EFI_STATUS -EFIAPI -LibGetWakeupTime ( - OUT BOOLEAN *Enabled, - OUT BOOLEAN *Pending, - OUT EFI_TIME *Time - ) -{ - // Not a required feature - return EFI_UNSUPPORTED; -} - - -/** - Sets the system wakeup alarm clock time. - - @param Enabled Enable or disable the wakeup alarm. - @param Time If Enable is TRUE, the time to set the wakeup alarm for. - - @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If - Enable is FALSE, then the wakeup alarm was disabled. - @retval EFI_INVALID_PARAMETER A time field is out of range. - @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. - @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. - -**/ -EFI_STATUS -EFIAPI -LibSetWakeupTime ( - IN BOOLEAN Enabled, - OUT EFI_TIME *Time - ) -{ - // Not a required feature - return EFI_UNSUPPORTED; -} - - - -/** - This is the declaration of an EFI image entry point. This can be the entry point to an application - written to this specification, an EFI boot service driver, or an EFI runtime driver. - - @param ImageHandle Handle that identifies the loaded image. - @param SystemTable System Table for this image. - - @retval EFI_SUCCESS The operation completed successfully. - -**/ -EFI_STATUS -EFIAPI -LibRtcInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_TIME EfiTime; - - (VOID)LibGetTime (&EfiTime, NULL); - if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){ - EfiTime.Year = 2015; - EfiTime.Month = 1; - EfiTime.Day = 1; - EfiTime.Hour = 0; - EfiTime.Minute = 0; - EfiTime.Second = 0; - EfiTime.Nanosecond = 0; - Status = LibSetTime(&EfiTime); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", __func__, __LINE__, Status)); - } - } - - return EFI_SUCCESS; -} diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf deleted file mode 100644 index 29c6ecf98bd44b263535e4e43a40ac724acbcc07..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ /dev/null @@ -1,45 +0,0 @@ -#/** @file -# -# Copyright (c) 2006, Intel Corporation. All rights reserved.
-# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.
-# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2016, Linaro Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = DS3231RealTimeClockLib - FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = RealTimeClockLib - -[Sources.common] - DS3231RealTimeClockLib.c - -[Packages] - MdePkg/MdePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - Platform/Hisilicon/D03/D03.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - IoLib - UefiLib - DebugLib - PcdLib - I2CLib - TimeBaseLib - TimerLib -# Use EFiAtRuntime to check stage - UefiRuntimeLib - CpldIoLib - -[Pcd] - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c deleted file mode 100755 index 4633d299fe319cb6d33f6b545fa11ecfd5fdbe91..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c +++ /dev/null @@ -1,481 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef union AA_DAW -{ - /* Define the struct bits */ - struct - { - unsigned int sysdaw_id : 7 ; /* [6:0] */ - unsigned int interleave_en : 1 ; /* [7] */ - unsigned int sysdaw_size : 4 ; /* [11:8] */ - unsigned int reserved : 4 ; /* [15:12] */ - unsigned int sysdaw_addr : 16 ; /* [31:16] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; - -} AA_DAW_U; - - - -MAC_ADDRESS gMacAddress[1]; - - -CHAR8 *EthName[8]= -{ - "ethernet@0","ethernet@1", - "ethernet@2","ethernet@3", - "ethernet@4","ethernet@5", - "ethernet@6","ethernet@7" -}; - -UINT8 DawNum[4] = {0, 0, 0, 0}; -PHY_MEM_REGION *NodemRegion[4] = {NULL, NULL, NULL, NULL}; -UINTN NumaPages[4] = {0, 0, 0, 0}; - -CHAR8 *NumaNodeName[4]= -{ - "p0-ta","p0-tc", - "p1-ta","p1-tc", -}; - -STATIC -BOOLEAN -IsMemMapRegion ( - IN EFI_MEMORY_TYPE MemoryType - ) -{ - switch(MemoryType) - { - case EfiRuntimeServicesCode: - case EfiRuntimeServicesData: - case EfiConventionalMemory: - case EfiACPIReclaimMemory: - case EfiACPIMemoryNVS: - case EfiLoaderCode: - case EfiLoaderData: - case EfiBootServicesCode: - case EfiBootServicesData: - case EfiPalCode: - return TRUE; - default: - return FALSE; - } -} - - -EFI_STATUS -GetMacAddress (UINT32 Port) -{ - EFI_MAC_ADDRESS Mac; - EFI_STATUS Status; - HISI_BOARD_NIC_PROTOCOL *OemNic = NULL; - - Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __func__, __LINE__, Status)); - return Status; - } - - Status = OemNic->GetMac(&Mac, Port); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] GetMac failed %r\n", __func__, __LINE__, Status)); - return Status; - } - - gMacAddress[0].data0=Mac.Addr[0]; - gMacAddress[0].data1=Mac.Addr[1]; - gMacAddress[0].data2=Mac.Addr[2]; - gMacAddress[0].data3=Mac.Addr[3]; - gMacAddress[0].data4=Mac.Addr[4]; - gMacAddress[0].data5=Mac.Addr[5]; - DEBUG((DEBUG_INFO, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2, - gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5)); - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -DelPhyhandleUpdateMacAddress(IN VOID* Fdt) -{ - UINT8 port; - INTN ethernetnode; - INTN node; - INTN Error; - struct fdt_property *m_prop; - int m_oldlen; - EFI_STATUS Status = EFI_SUCCESS; - EFI_STATUS GetMacStatus = EFI_SUCCESS; - - node = fdt_subnode_offset(Fdt, 0, "soc"); - if (node < 0) - { - DEBUG ((DEBUG_ERROR, "can not find soc root node\n")); - return EFI_INVALID_PARAMETER; - } - else - { - for( port=0; port<8; port++ ) - { - GetMacStatus= GetMacAddress(port); - ethernetnode = fdt_subnode_offset(Fdt, node,EthName[port]); - if(!EFI_ERROR(GetMacStatus)) - { - - if (ethernetnode < 0) - { - DEBUG ((DEBUG_WARN, "Can not find ethernet@%d node\n",port)); - DEBUG ((DEBUG_WARN, "Suppose port %d is not enabled.\n", port)); - continue; - } - m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen); - if(m_prop) - { - Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address"); - if (Error) - { - DEBUG ((DEBUG_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error))); - Status = EFI_INVALID_PARAMETER; - } - Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS)); - if (Error) - { - DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error))); - Status = EFI_INVALID_PARAMETER; - } - } - } - } - } - return Status; -} - -STATIC -EFI_STATUS -UpdateRefClk (IN VOID* Fdt) -{ - INTN node; - INTN Error; - struct fdt_property *m_prop; - int m_oldlen; - UINTN ArchTimerFreq = 0; - UINT32 Data; - CONST CHAR8 *Property = "clock-frequency"; - - ArmArchTimerReadReg (CntFrq, &ArchTimerFreq); - if (!ArchTimerFreq) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - node = fdt_subnode_offset(Fdt, 0, "soc"); - if (node < 0) { - DEBUG ((DEBUG_ERROR, "can not find soc node\n")); - return EFI_INVALID_PARAMETER; - } - - node = fdt_subnode_offset(Fdt, node, "refclk"); - if (node < 0) { - DEBUG ((DEBUG_ERROR, "can not find refclk node\n")); - return EFI_INVALID_PARAMETER; - } - - m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen); - if(!m_prop) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Can't find property %a\n", __func__, __LINE__, Property)); - return EFI_INVALID_PARAMETER; - } - - Error = fdt_delprop(Fdt, node, Property); - if (Error) { - DEBUG ((DEBUG_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error))); - return EFI_INVALID_PARAMETER; - } - - // UINT32 is enough for refclk data length - Data = (UINT32) ArchTimerFreq; - Data = cpu_to_fdt32 (Data); - Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data)); - if (Error) { - DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error))); - return EFI_INVALID_PARAMETER; - } - - DEBUG ((DEBUG_INFO, "Update refclk successfully.\n")); - return EFI_SUCCESS; -} - -INTN -GetMemoryNode(VOID* Fdt) -{ - INTN node; - int m_oldlen; - struct fdt_property *m_prop; - INTN Error = 0; - - - node = fdt_subnode_offset(Fdt, 0, "memory"); - if (node < 0) - { - // Create the memory node - node = fdt_add_subnode(Fdt, 0, "memory"); - - if(node < 0) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] fdt add subnode error\n", __func__, __LINE__)); - - return node; - } - - } - //find the memory node property - m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen); - if(m_prop) - { - Error = fdt_delprop(Fdt, node, "reg"); - - if (Error) - { - DEBUG ((DEBUG_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error))); - node = -1; - return node; - } - } - - return node; -} - - -EFI_STATUS UpdateMemoryNode(VOID* Fdt) -{ - INTN Error = 0; - EFI_STATUS Status = EFI_SUCCESS; - UINT32 Index = 0; - UINT32 MemIndex; - INTN node; - EFI_MEMORY_DESCRIPTOR *MemoryMap; - EFI_MEMORY_DESCRIPTOR *MemoryMapPtr; - EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent; - UINTN MemoryMapSize; - UINTN Pages0 = 0; - UINTN Pages1 = 0; - UINTN MapKey; - UINTN DescriptorSize; - UINT32 DescriptorVersion; - PHY_MEM_REGION *mRegion; - UINTN MemoryMapLastEndAddress ; - UINTN MemoryMapcontinuousStartAddress ; - UINTN MemoryMapCurrentStartAddress; - BOOLEAN FindMemoryRegionFlag = FALSE; - - node = GetMemoryNode(Fdt); - if (node < 0) - { - DEBUG((DEBUG_ERROR, "Can not find memory node\n")); - return EFI_NOT_FOUND; - } - MemoryMap = NULL; - MemoryMapSize = 0; - MemIndex = 0; - - Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion); - if (Status == EFI_BUFFER_TOO_SMALL) - { - // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive - // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size. - Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1; - MemoryMap = AllocatePages (Pages0); - if (MemoryMap == NULL) - { - Status = EFI_OUT_OF_RESOURCES; - return Status; - } - Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion); - - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "FdtUpdateLib GetMemoryMap Error\n")); - FreePages (MemoryMap, Pages0); - return Status; - } - } - else - { - DEBUG ((DEBUG_ERROR, "FdtUpdateLib GetmemoryMap Status: %r\n",Status)); - return EFI_ABORTED; - } - - mRegion = NULL; - Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize)); - - mRegion = (PHY_MEM_REGION*)AllocatePool(Pages1); - if (mRegion == NULL) - { - Status = EFI_OUT_OF_RESOURCES; - FreePages (MemoryMap, Pages0); - return Status; - } - - - MemoryMapPtr = MemoryMap; - MemoryMapPtrCurrent = MemoryMapPtr; - MemoryMapLastEndAddress = 0; - MemoryMapcontinuousStartAddress = 0; - MemoryMapCurrentStartAddress = 0; - for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) - { - MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize); - MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart; - - if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type)) - { - continue; - } - else - { - FindMemoryRegionFlag = TRUE; - if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress) - { - mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32); - mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress); - mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32); - mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress); - MemIndex+=1; - MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress; - } - } - MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE); - } - if (FindMemoryRegionFlag) - { - mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32); - mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress); - mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32); - mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress); - } - - Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1)); - - FreePool (mRegion); - FreePages (MemoryMap, Pages0); - if (Error) - { - DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error))); - Status = EFI_INVALID_PARAMETER; - return Status; - } - - return Status; -} - - -EFI_STATUS -UpdateNumaNode(VOID* Fdt) -{ - //TODO: Need to update numa node - return EFI_SUCCESS; -} -/* - * Entry point for fdtupdate lib. - */ - -EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr) -{ - INTN Error; - VOID* Fdt; - UINT32 Size; - UINTN NewFdtBlobSize; - UINTN NewFdtBlobBase; - EFI_STATUS Status = EFI_SUCCESS; - EFI_STATUS UpdateNumaStatus = EFI_SUCCESS; - - - Error = fdt_check_header ((VOID*)(FdtFileAddr)); - if (0 != Error) - { - DEBUG ((DEBUG_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error))); - return EFI_INVALID_PARAMETER; - } - - Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr)); - NewFdtBlobSize = Size + ADD_FILE_LENGTH; - Fdt = (VOID*)(UINTN)FdtFileAddr; - - Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); - if (EFI_ERROR (Status)) - { - return EFI_OUT_OF_RESOURCES; - } - - - Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize)); - if (Error) { - DEBUG ((DEBUG_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error))); - Status = EFI_INVALID_PARAMETER; - goto EXIT; - } - - Fdt = (VOID*)(UINTN)NewFdtBlobBase; - Status = DelPhyhandleUpdateMacAddress(Fdt); - if (EFI_ERROR (Status)) - { - DEBUG ((DEBUG_ERROR, "DelPhyhandleUpdateMacAddress fail:\n")); - Status = EFI_SUCCESS; - } - - Status = UpdateRefClk (Fdt); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "UpdateiRefClk fail.\n")); - } - - Status = UpdateMemoryNode(Fdt); - if (EFI_ERROR (Status)) - { - DEBUG ((DEBUG_ERROR, "UpdateMemoryNode Error\n")); - goto EXIT; - } - - UpdateNumaStatus = UpdateNumaNode(Fdt); - if (EFI_ERROR (UpdateNumaStatus)) - { - DEBUG ((DEBUG_ERROR, "Update NumaNode fail\n")); - } - - gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize); - -EXIT: - gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize)); - - return Status; - - - -} diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf deleted file mode 100755 index e02c7b229a8b794396e796551f77d0984c8c87dc..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +++ /dev/null @@ -1,44 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = FdtUpdateLib - FILE_GUID = B80B9FF1-FAB9-4BE5-B602-5ABAA6B7A3D4 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = FdtUpdateLib - - -[Sources.common] - FdtUpdateLib.c - - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec - -[LibraryClasses] - ArmLib - FdtLib - PlatformSysCtrlLib - OemMiscLib - -[Protocols] - gHisiBoardNicProtocolGuid - -[Guids] - -[Pcd] - gHisiTokenSpaceGuid.PcdNumaEnable - - diff --git a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/BoardFeature2PHi1610.c deleted file mode 100644 index 41a11bbfe695eceff7a2a4e4438ec2d4aaf1de3a..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/BoardFeature2PHi1610.c +++ /dev/null @@ -1,190 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -I2C_DEVICE gRtcDevice = { - .Socket = 0, - .Port = 6, - .DeviceType = DEVICE_TYPE_SPD, - .SlaveDeviceAddress = 0x68 -}; - -SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = -{ - {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} -}; - -SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = -{ - {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} -}; - -SERDES_PARAM gSerdesParam = { - .Hilink0Mode = EmHilink0Pcie1X8, - .Hilink1Mode = EmHilink1Pcie0X8, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Sas1X4, - .Hilink6Mode = 0x0, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParam0 = { - .Hilink0Mode = EmHilink0Hccs1X8Width16, - .Hilink1Mode = EmHilink1Hccs0X8Width16, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Sas1X4, - .Hilink6Mode = 0x0, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParam1 = { - .Hilink0Mode = EmHilink0Hccs1X8Width16, - .Hilink1Mode = EmHilink1Hccs0X8Width16, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Pcie3X4, - .Hilink6Mode = 0xF, - .UseSsc = 0, -}; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId) -{ - if (ParamA == NULL) { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); - return EFI_SUCCESS; -} - - -VOID OemPcieResetAndOffReset(void) - { - return; - } - -SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { - // PCIe0 Slot 1 - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0001, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - - // PCIe0 Slot 4 - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0004, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - } -}; - - -UINT8 OemGetPcieSlotNumber () -{ - return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); -} - -EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { - {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, - - {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} -}; - -EFI_HII_HANDLE -EFIAPI -OemGetPackages ( - ) -{ - return HiiAddPackages ( - &gEfiCallerIdGuid, - NULL, - HisiOemMiscLib2PStrings, - NULL, - NULL - ); -} - - diff --git a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/BoardFeature2PHi1610Strings.uni b/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/BoardFeature2PHi1610Strings.uni deleted file mode 100644 index eb809d7dc1cd8a5a3a324309046a280174d3c978..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/BoardFeature2PHi1610Strings.uni +++ /dev/null @@ -1,50 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// --*/ - -/=# - -#langdef en-US "English" - -// -// Begin English Language Strings -// -#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" - -// -// DIMM Device Locator strings - -// D03 -#string STR_LEMON_C10_DIMM_000 #language en-US "J5" -#string STR_LEMON_C10_DIMM_001 #language en-US "J6" -#string STR_LEMON_C10_DIMM_002 #language en-US "J7" -#string STR_LEMON_C10_DIMM_010 #language en-US "J8" -#string STR_LEMON_C10_DIMM_011 #language en-US "J9" -#string STR_LEMON_C10_DIMM_012 #language en-US "J10" -#string STR_LEMON_C10_DIMM_020 #language en-US "J11" -#string STR_LEMON_C10_DIMM_021 #language en-US "J12" -#string STR_LEMON_C10_DIMM_022 #language en-US "J13" -#string STR_LEMON_C10_DIMM_030 #language en-US "J14" -#string STR_LEMON_C10_DIMM_031 #language en-US "J15" -#string STR_LEMON_C10_DIMM_032 #language en-US "J16" -#string STR_LEMON_C10_DIMM_100 #language en-US "J17" -#string STR_LEMON_C10_DIMM_101 #language en-US "J18" -#string STR_LEMON_C10_DIMM_102 #language en-US "J19" -#string STR_LEMON_C10_DIMM_110 #language en-US "J20" -#string STR_LEMON_C10_DIMM_111 #language en-US "J21" -#string STR_LEMON_C10_DIMM_112 #language en-US "J22" -#string STR_LEMON_C10_DIMM_120 #language en-US "J23" -#string STR_LEMON_C10_DIMM_121 #language en-US "J24" -#string STR_LEMON_C10_DIMM_122 #language en-US "J25" -#string STR_LEMON_C10_DIMM_130 #language en-US "J26" -#string STR_LEMON_C10_DIMM_131 #language en-US "J27" -#string STR_LEMON_C10_DIMM_132 #language en-US "J28" - -// -// End English Language Strings -// - diff --git a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/HisiOemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/HisiOemMiscLib2PHi1610.inf deleted file mode 100644 index 59887f2b10299c10a9bc878639cfb7ba040fa01b..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/HisiOemMiscLib2PHi1610.inf +++ /dev/null @@ -1,48 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = HisiOemMiscLib2P - FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = HisiOemMiscLib - -[Sources.common] - BoardFeature2PHi1610.c - OemMiscLib2PHi1610.c - BoardFeature2PHi1610Strings.uni - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseMemoryLib - PcdLib - TimerLib - -[BuildOptions] - -[Ppis] - gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES - -[Pcd] - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable - -[FixedPcd.common] - -[Guids] - -[Protocols] - diff --git a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/OemMiscLib2PHi1610.c deleted file mode 100644 index a8e7ed5532b0d77a14ed8f76fafe2f4e2fe8bd0f..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/HisiOemMiscLib2P/OemMiscLib2PHi1610.c +++ /dev/null @@ -1,167 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { - {67,0,0,0}, - {225,0,0,3}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF} -}; - -REPORT_PCIEDIDVID2BMC PcieDeviceToReport2P[PCIEDEVICE_REPORT_MAX] = { - {0x79,0,0,0}, - {0xFF,0xFF,0xFF,1}, - {0xC1,0,0,2}, - {0xF9,0,0,3}, - {0xFF,0xFF,0xFF,4}, - {0x11,0,0,5}, - {0x31,0,0,6}, - {0x21,0,0,7} -}; - -VOID -GetPciDidVid ( - REPORT_PCIEDIDVID2BMC *Report - ) -{ - if (OemIsMpBoot ()) { - (VOID)CopyMem ( - (VOID *)Report, - (VOID *)PcieDeviceToReport2P, - sizeof (PcieDeviceToReport2P) - ); - } else { - (VOID)CopyMem ( - (VOID *)Report, - (VOID *)PcieDeviceToReport, - sizeof (PcieDeviceToReport) - ); - } -} - -// Right now we only support 1P -BOOLEAN OemIsSocketPresent (UINTN Socket) -{ - if (0 == Socket) - { - return TRUE; - } - - if(1 == Socket) - { - return TRUE; - } - - return FALSE; -} - - -UINTN OemGetSocketNumber (VOID) -{ - - if(!OemIsMpBoot()) - { - return 1; - } - - return 2; - -} - - -UINTN OemGetDdrChannel (VOID) -{ - return 4; -} - - -UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) -{ - return 2; -} - - -// Nothing to do for EVB -VOID OemPostEndIndicator (VOID) -{ - - DEBUG((DEBUG_ERROR,"M3 release reset CONFIG.........")); - - MmioWrite32(0xd0002180, 0x3); - MmioWrite32(0xd0002194, 0xa4); - MmioWrite32(0xd0000a54, 0x1); - - MicroSecondDelay(10000); - - MmioWrite32(0xd0002108, 0x1); - MmioWrite32(0xd0002114, 0x1); - MmioWrite32(0xd0002120, 0x1); - MmioWrite32(0xd0003108, 0x1); - - MicroSecondDelay(500000); - DEBUG((DEBUG_ERROR,"Done\n")); - -} - - - -VOID CoreSelectBoot(VOID) -{ - if (!PcdGet64 (PcdTrustedFirmwareEnable)) - { - StartUpBSP (); - } - - return; -} - -BOOLEAN OemIsMpBoot() -{ - UINT32 Tmp; - - Tmp = MmioRead32(0x602E0050); - if ( ((Tmp >> 10) & 0xF) == 0x3) - return TRUE; - else - return FALSE; -} - -VOID OemLpcInit(VOID) -{ - LpcInit(); - return; -} - -UINT32 OemIsWarmBoot(VOID) -{ - return 0; -} - -VOID OemBiosSwitch(UINT32 Master) -{ - (VOID)Master; - return; -} - -BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) -{ - return TRUE; -} diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c deleted file mode 100644 index 419eb878f3fe289b6b5cc326eaf67ec3ee5e6e63..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ /dev/null @@ -1,142 +0,0 @@ -/** @file - - Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2016, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000}, - {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}}; -UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, - {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}}; -UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000}, - {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}}; -UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}, - {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}}; - -PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { - {// HostBridge 0 - /* Port 0 */ - { - 0, //Segment - PCI_HB0RB0_ECAM_BASE, //ecam - 0, //BusBase - 31, //BusLimit - PCI_HB0RB0_IO_BASE, //IoBase - (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit - PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB0_PCI_BASE), //RbPciBar - PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase - PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit - - }, - /* Port 1 */ - { - 1, //Segment - PCI_HB0RB1_ECAM_BASE,//ecam - 224, //BusBase - 254, //BusLimit - (PCI_HB0RB1_IO_BASE), //IoBase - (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit - PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB1_PCI_BASE), //RbPciBar - PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase - PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit - }, - /* Port 2 */ - { - 2, //Segment - PCI_HB0RB2_ECAM_BASE, - 128, //BusBase - 159, //BusLimit - (PCI_HB0RB2_IO_BASE), //IOBase - (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit - PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB2_PCI_BASE), //RbPciBar - PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase - PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit - }, - - /* Port 3 */ - { - 3, //Segment - PCI_HB0RB3_ECAM_BASE, - 96, //BusBase - 127, //BusLimit - (0), //IoBase - (0), //IoLimit - 0, - 0, - (PCI_HB0RB3_PCI_BASE), //RbPciBar - 0, - 0 - } - }, -{// HostBridge 1 - /* Port 0 */ - { - 4, //Segment - PCI_HB1RB0_ECAM_BASE, - 128, //BusBase - 159, //BusLimit - (0), //IoBase - (0), //IoLimit - 0, - 0, - (PCI_HB1RB0_PCI_BASE), //RbPciBar - 0, - 0 - }, - /* Port 1 */ - { - 5, //Segment - PCI_HB1RB1_ECAM_BASE, - 160, //BusBase - 191, //BusLimit - (0), //IoBase - (0), //IoLimit - 0, - 0, - (PCI_HB1RB1_PCI_BASE), //RbPciBar - 0, - 0 - }, - /* Port 2 */ - { - 6, //Segment - PCI_HB1RB2_ECAM_BASE, - 192, //BusBase - 223, //BusLimit - (0), //IoBase - (0), //IoLimit - 0, - 0, - (PCI_HB1RB2_PCI_BASE), //RbPciBar - 0, - 0 - }, - - /* Port 3 */ - { - 7, //Segment - PCI_HB1RB3_ECAM_BASE, - 224, //BusBase - 255, //BusLimit - (0), //IoBase - (0), //IoLimit - 0, - 0, - (PCI_HB1RB3_PCI_BASE), //RbPciBar - 0, - 0 - } - } -}; - diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf deleted file mode 100644 index 63d57ec46d7ba7ac84f6fd6c5833f0b53fdb00b4..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf +++ /dev/null @@ -1,177 +0,0 @@ -## @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2016, Linaro Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PlatformPciLib - FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - -[Sources] - PlatformPciLib.c - -[Packages] - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - PcdLib - -[FixedPcd] - gHisiTokenSpaceGuid.PcdHb1BaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PciHb0Rb0Base - gHisiTokenSpaceGuid.PciHb0Rb1Base - gHisiTokenSpaceGuid.PciHb0Rb2Base - gHisiTokenSpaceGuid.PciHb0Rb3Base - gHisiTokenSpaceGuid.PciHb0Rb4Base - gHisiTokenSpaceGuid.PciHb0Rb5Base - gHisiTokenSpaceGuid.PciHb0Rb6Base - gHisiTokenSpaceGuid.PciHb0Rb7Base - gHisiTokenSpaceGuid.PciHb1Rb0Base - gHisiTokenSpaceGuid.PciHb1Rb1Base - gHisiTokenSpaceGuid.PciHb1Rb2Base - gHisiTokenSpaceGuid.PciHb1Rb3Base - gHisiTokenSpaceGuid.PciHb1Rb4Base - gHisiTokenSpaceGuid.PciHb1Rb5Base - gHisiTokenSpaceGuid.PciHb1Rb6Base - gHisiTokenSpaceGuid.PciHb1Rb7Base - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress - - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase - - gHisiTokenSpaceGuid.PcdHb0Rb0IoBase - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize - gHisiTokenSpaceGuid.PcdHb0Rb1IoBase - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize - gHisiTokenSpaceGuid.PcdHb0Rb3IoBase - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize - gHisiTokenSpaceGuid.PcdHb0Rb4IoBase - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize - gHisiTokenSpaceGuid.PcdHb0Rb5IoBase - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize - gHisiTokenSpaceGuid.PcdHb0Rb6IoBase - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize - gHisiTokenSpaceGuid.PcdHb0Rb7IoBase - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize - gHisiTokenSpaceGuid.PcdHb1Rb0IoBase - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize - gHisiTokenSpaceGuid.PcdHb1Rb1IoBase - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize - gHisiTokenSpaceGuid.PcdHb1Rb2IoBase - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize - gHisiTokenSpaceGuid.PcdHb1Rb3IoBase - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize - gHisiTokenSpaceGuid.PcdHb1Rb4IoBase - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize - gHisiTokenSpaceGuid.PcdHb1Rb5IoBase - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize - gHisiTokenSpaceGuid.PcdHb1Rb6IoBase - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize - gHisiTokenSpaceGuid.PcdHb1Rb7IoBase - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize diff --git a/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini deleted file mode 100644 index dd575965c6dd023ec07f3c3bfe4c11b5feeacc5e..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini +++ /dev/null @@ -1,39 +0,0 @@ -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Head] -NumOfUpdate = 3 -NumOfRecovery = 0 -Update0 = SysFvMain -Update1 = SysCustom -Update2 = SysNvRam - -[SysFvMain] -FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x00000000 # Base address offset on flash -Length = 0x002D0000 # Length -ImageOffset = 0x00000000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - -[SysCustom] -FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x002F0000 # Base address offset on flash -Length = 0x00010000 # Length -ImageOffset = 0x002F0000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - -[SysNvRam] -FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x002D0000 # Base address offset on flash -Length = 0x00020000 # Length -ImageOffset = 0x002D0000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc deleted file mode 100644 index 35bfc601f331b64d531c7b9fbf09560f70f0a46b..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/D05.dsc +++ /dev/null @@ -1,644 +0,0 @@ -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - PLATFORM_NAME = D05 - PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6 - PLATFORM_VERSION = 0.1 - DSC_SPECIFICATION = 0x00010019 - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 - BUILD_TARGETS = NOOPT|DEBUG|RELEASE - SKUID_IDENTIFIER = DEFAULT - FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf - DEFINE EDK2_SKIP_PEICORE=0 - - # - # Network definition - # - DEFINE NETWORK_SNP_ENABLE = FALSE - DEFINE NETWORK_TLS_ENABLE = FALSE - DEFINE NETWORK_VLAN_ENABLE = FALSE - DEFINE NETWORK_IP6_ENABLE = FALSE - DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE - -!include Silicon/Hisilicon/Hisilicon.dsc.inc -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses.common] - ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf - - I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf - TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf - - IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf - - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - - -!ifdef $(FDT_ENABLE) - #FDTUpdateLib - FdtUpdateLib|Platform/Hisilicon/D05/Library/FdtUpdateLib/FdtUpdateLib.inf -!endif #$(FDT_ENABLE) - - CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf - - SerdesLib|Silicon/Hisilicon/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf - - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf - #D05 RTC hardware is same as D03 - RealTimeClockLib|Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf - - HisiOemMiscLib|Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/HisiOemMiscLibD05.inf - OemAddressMapLib|Platform/Hisilicon/D05/Library/OemAddressMapD05/OemAddressMapD05.inf - PlatformSysCtrlLib|Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf - - BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf - - # USB Requirements - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - - LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf - PlatformPciLib|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf - PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf - PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf - PciPlatformLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf - -[LibraryClasses.common.SEC] - ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf - - -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf - -[BuildOptions] - GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1616/Include - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - -!if $(EDK2_SKIP_PEICORE) == 1 - gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE -!endif - - ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. - # It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE - gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE - -[PcdsDynamicExDefault.common.DEFAULT] - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 - gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89} - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55} - -[PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 - gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0 - - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 - - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 - - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 - - - gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 - - - # Size of the region used by UEFI in permanent memory (Reserved 64MB) - gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 - - gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 - gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 - - - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 - # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - ## enable all the pcie device, because it is ok for bios - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 - # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - - ## Serial Terminal - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - - gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000 - - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 - # use the TTY terminal type (which has a working backspace) - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 - - - gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 - gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 - gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 - gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - - - gHisiTokenSpaceGuid.PcdIsMPBoot|1 - gHisiTokenSpaceGuid.PcdSocketMask|0x3 - !ifdef $(FIRMWARE_VER) - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" - !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 19.02 for Hisilicon D05" - !endif - - gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" - - gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"19.02" - - gHisiTokenSpaceGuid.PcdSystemProductName|L"D05" - gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" - gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05" - gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" - - gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616" - - - gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000 - gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 - - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } - gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 - gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 - - gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000 - - gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 - gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 - - - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000 - - - gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000 - - ## DTB address at spi flash - gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000 - - gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 - - gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 - - gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 - - gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000 - - gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000 - gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000 - - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 - gHisiTokenSpaceGuid.PcdNumaEnable|1 - gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000 - - gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000 - - - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000 - - gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000 - gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000 - gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000 - gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000 - gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000 - gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000 - gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000 - gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000 - gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000 - gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000 - gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000 - gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000 - gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000 - gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000 - gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000 - gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 - - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000 - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 - gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 - gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 - gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 - gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 - gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 - gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 - gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 - gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 - gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 - gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 - gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 - gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 - gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 - gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 - gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 - gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 - gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000 - gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000 - gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000 - gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000 - gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 - - gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K - - gHisiTokenSpaceGuid.Pcdsoctype|0x1610 - -################################################################################ -# -# Components Section - list of all EDK II Modules needed by this Platform -# -################################################################################ -[Components.common] - - # - # SEC - # - - # - # PEI Phase modules - # - ArmPlatformPkg/Sec/Sec.inf - MdeModulePkg/Core/Pei/PeiMain.inf - MdeModulePkg/Universal/PCD/Pei/Pcd.inf - Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf - - ArmPlatformPkg/PlatformPei/PlatformPeim.inf - - Platform/Hisilicon/D05/MemoryInitPei/MemoryInitPeim.inf - ArmPkg/Drivers/CpuPei/CpuPei.inf - MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf - MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf - MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - - Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf - Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf - - Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - - MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - } - - # - # DXE - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf - } - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf - - # - # Architectural Protocols - # - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - - ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf - - Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf - - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - - MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { - - CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf - } - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - # Simple TextIn/TextOut for UEFI Terminal - EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf - - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - ArmPkg/Drivers/ArmGicDxe/ArmGicV3Dxe.inf - - ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - # - #ACPI - # - Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - - Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf - Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf - Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - - # - # Usb Support - # - Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf - MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf - MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf - - Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf - -!include NetworkPkg/Network.dsc.inc - Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf - - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf - } - # - # Bds - # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - Platform/Hisilicon/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf - Platform/Hisilicon/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf - Platform/Hisilicon/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf - - Platform/Hisilicon/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf - - MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf - -!ifdef $(FDT_ENABLE) - Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { - - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } -!endif #$(FDT_ENABLE) - - #PCIe Support - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf { - - NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf - } - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf { - - NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf - } - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - - NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf - } - - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf - Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf - Platform/Hisilicon/Drivers/Sm750Dxe/UefiSmi.inf - Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf - - - Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf - - # - # Memory test - # - MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { - - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf - } - - MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf - - # - # UEFI application (Shell Embedded Boot Loader) - # - ShellPkg/Application/Shell/Shell.inf { - - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf -!if $(NETWORK_IP6_ENABLE) == TRUE - NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf -!endif - -!ifdef $(INCLUDE_DP) - NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf -!endif #$(INCLUDE_DP) - - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 - } -!ifdef $(INCLUDE_TFTP_COMMAND) - ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { - - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - } -!endif #$(INCLUDE_TFTP_COMMAND) diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf deleted file mode 100644 index 5ca7ec0b07ed7b86160c8daafa232342f45d9535..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/D05.fdf +++ /dev/null @@ -1,410 +0,0 @@ -# -# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. -# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[DEFINES] - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ -[FD.D05] - -BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. - -Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device -ErasePolarity = 1 - -# This one is tricky, it must be: BlockSize * NumBlocks = Size -BlockSize = 0x00010000 -NumBlocks = 0x30 - -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# -################################################################################ - -0x00000000|0x00040000 -gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize -FILE = Platform/Hisilicon/D05/Sec/FVMAIN_SEC.Fv - -0x00040000|0x00240000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV = FVMAIN_COMPACT - -0x00280000|0x00020000 -gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base -FILE = Platform/Hisilicon/D05/bl1.bin -0x002A0000|0x00020000 -FILE = Platform/Hisilicon/D05/fip.bin - -0x002D0000|0x0000E000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -DATA = { - ## This is the EFI_FIRMWARE_VOLUME_HEADER - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - # FileSystemGuid: gEfiSystemNvDataFvGuid = - 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, - 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, - # FvLength: 0x20000 - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - #Signature "_FVH" #Attributes - 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, - #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision - 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, - #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - #Blockmap[1]: End - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid - 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, - 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, - #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 - 0xB8, 0xdF, 0x00, 0x00, - #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 - 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -0x002DE000|0x00002000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -#NV_FTW_WORKING -DATA = { - # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = - 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, - 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, - # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved - 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, - # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 - 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -0x002E0000|0x00010000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - -0x002F0000|0x00010000 -FILE = Platform/Hisilicon/D0x-CustomData.Fv - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ - -[FV.FvMain] -BlockSize = 0x40 -NumBlocks = 0 # This FV gets compressed so make it just big enough -FvAlignment = 16 # FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - } - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - INF Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf - - INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf - - - INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf - INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # Multiple Console IO support - # - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - # Simple TextIn/TextOut for UEFI Terminal - - INF ArmPkg/Drivers/ArmGicDxe/ArmGicV3Dxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - - # - # Usb Support - # - - INF Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf - INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf - INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - INF Platform/Hisilicon/D05/Drivers/OhciDxe/OhciDxe.inf - INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf - INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - INF Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf - INF Platform/Hisilicon/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf - INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf - - INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf - INF Platform/Hisilicon/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf - INF Platform/Hisilicon/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf - - INF Platform/Hisilicon/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf - - - INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf - - INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf - - # - #ACPI - # - INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf - - INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf - INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf - INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - - # - #Network - # - - INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf - INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf - -!include NetworkPkg/Network.fdf.inc - -!ifdef $(FDT_ENABLE) - INF Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf -!endif #$(FDT_ENABLE) - - # - # PCI Support - # - INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf - INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - INF Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf - # VGA Driver - # - INF Platform/Hisilicon/Drivers/Sm750Dxe/UefiSmi.inf - INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf - INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf - - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - # - # Build Shell from latest source code instead of prebuilt binary - # - INF ShellPkg/Application/Shell/Shell.inf -!ifdef $(INCLUDE_TFTP_COMMAND) - INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) - - INF MdeModulePkg/Application/UiApp/UiApp.inf - # - # Bds - # - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - -[FV.FVMAIN_COMPACT] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - APRIORI PEI { - INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf - } - INF ArmPlatformPkg/Sec/Sec.inf - INF MdeModulePkg/Core/Pei/PeiMain.inf - INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf - - INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - - INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf - - INF Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf - INF Platform/Hisilicon/D05/MemoryInitPei/MemoryInitPeim.inf - INF ArmPkg/Drivers/CpuPei/CpuPei.inf - INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf - INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf - INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf - - INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf - - INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } - } - -[FV.CapsuleDispatchFv] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf - -[FV.SystemFirmwareUpdateCargo] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid - FD = D05 - } - - FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid - FV = CapsuleDispatchFv - } - - FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid - Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini - } - -[FmpPayload.FmpPayloadSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 -IMAGE_TYPE_ID = 7978365d-7978-45fd-ad77-b27693cfe85b # PcdSystemFmpCapsuleImageTypeIdGuid -IMAGE_INDEX = 0x1 -HARDWARE_INSTANCE = 0x0 -MONOTONIC_COUNT = 0x1 -CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 - - FV = SystemFirmwareUpdateCargo - -[Capsule.D05FirmwareUpdateCapsuleFmpPkcs7] -CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid -CAPSULE_HEADER_SIZE = 0x20 -CAPSULE_HEADER_INIT_VERSION = 0x1 - - FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7 - -!include Silicon/Hisilicon/Hisilicon.fdf.inc - diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc deleted file mode 100644 index 210141d019cbab5af253fc6c41841752a0f8958c..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc +++ /dev/null @@ -1,75 +0,0 @@ -/** @file - System Firmware descriptor. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include - -#define PACKAGE_VERSION 0xFFFFFFFF -#define PACKAGE_VERSION_STRING L"Unknown" - -#define CURRENT_FIRMWARE_VERSION 0x00000002 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002" -#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 - -#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd') -#define IMAGE_ID_STRING L"ARMPlatformFd" - -// PcdSystemFmpCapsuleImageTypeIdGuid -#define IMAGE_TYPE_ID_GUID { 0x7978365d, 0x7978, 0x45fd, { 0xad, 0x77, 0xb2, 0x76, 0x93, 0xcf, 0xe8, 0x5b } } - -typedef struct { - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; - // real string data - CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE_ID_STRING)]; - CHAR16 VersionNameStr[ARRAY_SIZE (CURRENT_FIRMWARE_VERSION_STRING)]; - CHAR16 PackageVersionNameStr[ARRAY_SIZE (PACKAGE_VERSION_STRING)]; -} IMAGE_DESCRIPTOR; - -IMAGE_DESCRIPTOR mImageDescriptor = -{ - { - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, - sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), - sizeof (IMAGE_DESCRIPTOR), - PACKAGE_VERSION, // PackageVersion - OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName - 1, // ImageIndex; - {0x0}, // Reserved - IMAGE_TYPE_ID_GUID, // ImageTypeId; - IMAGE_ID, // ImageId; - OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; - CURRENT_FIRMWARE_VERSION, // Version; - OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; - {0x0}, // Reserved2 - FixedPcdGet32 (PcdFdSize), // Size; - IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | - IMAGE_ATTRIBUTE_RESET_REQUIRED | - IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported; - IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | - IMAGE_ATTRIBUTE_RESET_REQUIRED | - IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting; - 0x0, // Compatibilities; - LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; - 0x00000000, // LastAttemptVersion; - 0, // LastAttemptStatus; - {0x0}, // Reserved3 - 0, // HardwareInstance; - }, - // real string data - {IMAGE_ID_STRING}, - {CURRENT_FIRMWARE_VERSION_STRING}, - {PACKAGE_VERSION_STRING}, -}; - -VOID* CONST ReferenceAcpiTable = &mImageDescriptor; diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf deleted file mode 100644 index 67568145740265c5ecb22f7599b00f140577a945..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ /dev/null @@ -1,44 +0,0 @@ -## @file -# System Firmware descriptor. -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = SystemFirmwareDescriptor - FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = SystemFirmwareDescriptorPeimEntry - -[Sources] - SystemFirmwareDescriptorPei.c - SystemFirmwareDescriptor.aslc - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - SignedCapsulePkg/SignedCapsulePkg.dec - -[LibraryClasses] - DebugLib - PcdLib - PeimEntryPoint - PeiServicesLib - -[FixedPcd] - gArmTokenSpaceGuid.PcdFdSize - -[Pcd] - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor - -[Depex] - TRUE diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c deleted file mode 100644 index 77f631d5d6f149960b600875721ce50006e65ae0..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c +++ /dev/null @@ -1,64 +0,0 @@ -/** @file - System Firmware descriptor producer. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -/** - Entrypoint for SystemFirmwareDescriptor PEIM. - - @param[in] FileHandle Handle of the file being invoked. - @param[in] PeiServices Describes the list of possible PEI Services. - - @retval EFI_SUCCESS PPI successfully installed. -**/ -EFI_STATUS -EFIAPI -SystemFirmwareDescriptorPeimEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; - UINTN Size; - UINTN Index; - UINT32 AuthenticationStatus; - - // - // Search RAW section. - // - - Index = 0; - while (TRUE) { - Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus); - if (EFI_ERROR (Status)) { - // Should not happen, must something wrong in FDF. - DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n")); - return EFI_NOT_FOUND; - } - if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) { - break; - } - Index++; - } - - DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length)); - - Size = Descriptor->Length; - PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); - - return EFI_SUCCESS; -} diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c deleted file mode 100644 index 05aefc90f7894c5fb8b4d35c550297f4990fe95a..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c +++ /dev/null @@ -1,58 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -VOID -QResetAp ( - VOID - ) -{ - MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); - (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); - - if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartUpBSP (); - } -} - - -EFI_STATUS -EFIAPI -EarlyConfigEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - DEBUG((DEBUG_INFO,"SMMU CONFIG.........")); - (VOID)SmmuConfigForBios(); - DEBUG((DEBUG_INFO,"Done\n")); - - DEBUG((DEBUG_INFO,"AP CONFIG.........")); - (VOID)QResetAp(); - DEBUG((DEBUG_INFO,"Done\n")); - - DEBUG((DEBUG_INFO,"MN CONFIG.........")); - (VOID)MN_CONFIG(); - DEBUG((DEBUG_INFO,"Done\n")); - - return EFI_SUCCESS; -} - diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf deleted file mode 100644 index c42d0dd6cd74d4e9cda2b12801f55887b39c3a70..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf +++ /dev/null @@ -1,48 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = EarlyConfigPeimD05 - FILE_GUID = 13525B94-06F0-41AC-8CAF-724B149FD259 - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = EarlyConfigEntry - -[Sources.common] - EarlyConfigPeimD05.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - ArmLib - CacheMaintenanceLib - DebugLib - IoLib - PcdLib - PeimEntryPoint - PlatformSysCtrlLib - -[Pcd] - gHisiTokenSpaceGuid.PcdMailBoxAddress - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable - -[Depex] -## As we will clean mailbox in this module, need to wait memory init complete - gEfiPeiMemoryDiscoveredPpiGuid - -[BuildOptions] - diff --git a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/BoardFeatureD05.c deleted file mode 100644 index 0746ff3230c5c0d8f94af6deb044ea519e0965a6..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/BoardFeatureD05.c +++ /dev/null @@ -1,218 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -I2C_DEVICE gRtcDevice = { - .Socket = 0, - .Port = 4, - .DeviceType = DEVICE_TYPE_SPD, - .SlaveDeviceAddress = 0x68 -}; - -SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = { - {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} -}; - -SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = { - {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} -}; - -SERDES_PARAM gSerdesParamNA = { - .Hilink0Mode = EmHilink0Hccs1X8Width16, - .Hilink1Mode = EmHilink1Hccs0X8Width16, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Sas1X4, - .Hilink6Mode = 0x0, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParamNB = { - .Hilink0Mode = EmHilink0Pcie1X8, - .Hilink1Mode = EmHilink1Pcie0X8, - .Hilink2Mode = EmHilink2Sas0X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2, - .Hilink6Mode = 0xF, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParamS1NA = { - .Hilink0Mode = EmHilink0Hccs1X8Width16, - .Hilink1Mode = EmHilink1Hccs0X8Width16, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Sas1X4, - .Hilink6Mode = 0x0, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParamS1NB = { - .Hilink0Mode = EmHilink0Pcie1X8, - .Hilink1Mode = EmHilink1Pcie0X8, - .Hilink2Mode = EmHilink2Sas0X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2, - .Hilink6Mode = 0xF, - .UseSsc = 0, -}; - - -EFI_STATUS -OemGetSerdesParam ( - OUT SERDES_PARAM *ParamA, - OUT SERDES_PARAM *ParamB, - IN UINT32 SocketId - ) -{ - if (ParamA == NULL || ParamB == NULL) { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - if (SocketId == 0) { - (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA)); - (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB)); - } else { - (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA)); - (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB)); - } - - return EFI_SUCCESS; -} - -VOID -OemPcieResetAndOffReset ( - VOID - ) -{ - return; -} - -SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { - // PCIe0 Slot 1 - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0001, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - - // PCIe0 Slot 4 - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0004, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - } -}; - - -UINT8 -OemGetPcieSlotNumber ( - VOID - ) -{ - return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); -} - -EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { - {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, - - {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} -}; - -EFI_HII_HANDLE -EFIAPI -OemGetPackages ( - ) -{ - return HiiAddPackages ( - &gEfiCallerIdGuid, - NULL, - HisiOemMiscLibHi1616EvbStrings, - NULL, - NULL - ); -} - - diff --git a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/BoardFeatureD05Strings.uni b/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/BoardFeatureD05Strings.uni deleted file mode 100644 index 8b36905f0fd79068a343cbee115ef50495f32d61..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/BoardFeatureD05Strings.uni +++ /dev/null @@ -1,50 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2016, Hisilicon Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// --*/ - -/=# - -#langdef en-US "English" - -// -// Begin English Language Strings -// -#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" - -// -// DIMM Device Locator strings - -#string STR_LEMON_C10_DIMM_000 #language en-US "J5" -#string STR_LEMON_C10_DIMM_001 #language en-US "J6" -#string STR_LEMON_C10_DIMM_002 #language en-US "J7" -#string STR_LEMON_C10_DIMM_010 #language en-US "J8" -#string STR_LEMON_C10_DIMM_011 #language en-US "J9" -#string STR_LEMON_C10_DIMM_012 #language en-US "J10" -#string STR_LEMON_C10_DIMM_020 #language en-US "J11" -#string STR_LEMON_C10_DIMM_021 #language en-US "J12" -#string STR_LEMON_C10_DIMM_022 #language en-US "J13" -#string STR_LEMON_C10_DIMM_030 #language en-US "J14" -#string STR_LEMON_C10_DIMM_031 #language en-US "J15" -#string STR_LEMON_C10_DIMM_032 #language en-US "J16" -#string STR_LEMON_C10_DIMM_100 #language en-US "J17" -#string STR_LEMON_C10_DIMM_101 #language en-US "J18" -#string STR_LEMON_C10_DIMM_102 #language en-US "J19" -#string STR_LEMON_C10_DIMM_110 #language en-US "J20" -#string STR_LEMON_C10_DIMM_111 #language en-US "J21" -#string STR_LEMON_C10_DIMM_112 #language en-US "J22" -#string STR_LEMON_C10_DIMM_120 #language en-US "J23" -#string STR_LEMON_C10_DIMM_121 #language en-US "J24" -#string STR_LEMON_C10_DIMM_122 #language en-US "J25" -#string STR_LEMON_C10_DIMM_130 #language en-US "J26" -#string STR_LEMON_C10_DIMM_131 #language en-US "J27" -#string STR_LEMON_C10_DIMM_132 #language en-US "J28" - -// -// End English Language Strings -// - diff --git a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/HisiOemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/HisiOemMiscLibD05.inf deleted file mode 100644 index b635dde51f7d4ef4276a34ad438f7c33691cb285..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/HisiOemMiscLibD05.inf +++ /dev/null @@ -1,50 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = HisiOemMiscLibHi1616Evb - FILE_GUID = 751C7627-D5F8-499C-AEEEE-C87858759612 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = HisiOemMiscLib - -[Sources.common] - BoardFeatureD05.c - BoardFeatureD05Strings.uni - OemMiscLibD05.c - -[Packages] - ArmPkg/ArmPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseMemoryLib - PcdLib - TimerLib - -[BuildOptions] - -[Ppis] - gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES - -[Pcd] - gHisiTokenSpaceGuid.PcdIsMPBoot - gHisiTokenSpaceGuid.PcdSocketMask - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable - -[FixedPcd.common] - -[Guids] - -[Protocols] - diff --git a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/OemMiscLibD05.c deleted file mode 100644 index 4cd50c868f8ff1e856f691ff4fa6e037644d869b..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Library/HisiOemMiscLibD05/OemMiscLibD05.c +++ /dev/null @@ -1,125 +0,0 @@ -/** @file -* -* Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define OEM_SINGLE_SOCKET 1 -#define OEM_DUAL_SOCKET 2 - -REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { - {67,0,0,0}, - {225,0,0,3}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF} -}; - -REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = { - {0x79,0,0,0}, - {0xFF,0xFF,0xFF,1}, - {0xC1,0,0,2}, - {0xF9,0,0,3}, - {0xFF,0xFF,0xFF,4}, - {0x11,0,0,5}, - {0x31,0,0,6}, - {0x21,0,0,7} -}; - -VOID -GetPciDidVid ( - REPORT_PCIEDIDVID2BMC *Report - ) -{ - if (OemIsMpBoot ()) { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P)); - } else { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport)); - } -} - -BOOLEAN OemIsSocketPresent (UINTN Socket) -{ - if (PcdGet32(PcdSocketMask) & (1 << Socket)) { - return TRUE; - } else { - return FALSE; - } -} - - -UINTN OemGetSocketNumber (VOID) -{ - - if(!OemIsMpBoot()) { - return OEM_SINGLE_SOCKET; - } - - return OEM_DUAL_SOCKET; -} - - -UINTN OemGetDdrChannel (VOID) -{ - return 4; -} - - -UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) -{ - return 2; -} - -VOID CoreSelectBoot(VOID) -{ - if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartUpBSP (); - } - - return; -} - -BOOLEAN OemIsMpBoot() -{ - return PcdGet32(PcdIsMPBoot); -} - -VOID OemLpcInit(VOID) -{ - LpcInit(); - return; -} - -UINT32 OemIsWarmBoot(VOID) -{ - return 0; -} - -VOID OemBiosSwitch(UINT32 Master) -{ - (VOID)Master; - return; -} - -BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) -{ - return TRUE; -} - diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c deleted file mode 100644 index 18d2bf2f9838d43d593554a5b201e009a29d7548..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ /dev/null @@ -1,257 +0,0 @@ -/** @file - - Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2016, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include - -UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000}, - {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}}; -UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000}, - {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}}; -UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000}, - {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}}; -UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040}, - {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}}; - -PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { - {// HostBridge 0 - /* Port 0 */ - { - 0, //Segment - PCI_HB0RB0_ECAM_BASE, //ecam - 0x80, //BusBase - 0x87, //BusLimit - PCI_HB0RB0_IO_BASE, //IoBase - (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit - PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB0_PCI_BASE),//RbPciBar - PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 1 */ - { - 1, //Segment - PCI_HB0RB1_ECAM_BASE,//ecam - 0x90, //BusBase - 0x97, //BusLimit - (PCI_HB0RB1_IO_BASE), //IoBase - (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit - PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB1_PCI_BASE), //RbPciBar - PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 2 */ - { - 2, //Segment - PCI_HB0RB2_ECAM_BASE, - 0xF8, //BusBase - 0xFF, //BusLimit - (PCI_HB0RB2_IO_BASE), //IOBase - (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit - PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB2_PCI_BASE), //RbPciBar - PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit - }, - - /* Port 3 */ - { - 3, //Segment - PCI_HB0RB3_ECAM_BASE, - 0xb0, //BusBase - 0xb7, //BusLimit - (PCI_HB0RB3_IO_BASE), //IoBase - (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit - PCI_HB0RB3_CPUMEMREGIONBASE, - PCI_HB0RB3_CPUIOREGIONBASE, - (PCI_HB0RB3_PCI_BASE), //RbPciBar - PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 4 */ - { - 4, //Segment - PCI_HB0RB4_ECAM_BASE, //ecam - 0x88, //BusBase - 0x8f, //BusLimit - PCI_HB0RB4_IO_BASE, //IoBase - (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit - PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB4_PCI_BASE), //RbPciBar - PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 5 */ - { - 5, //Segment - PCI_HB0RB5_ECAM_BASE,//ecam - 0x78, //BusBase - 0x7F, //BusLimit - (PCI_HB0RB5_IO_BASE), //IoBase - (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit - PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB5_PCI_BASE), //RbPciBar - PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 6 */ - { - 6, //Segment - PCI_HB0RB6_ECAM_BASE, - 0xC0, //BusBase - 0xC7, //BusLimit - (PCI_HB0RB6_IO_BASE), //IOBase - (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit - PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB6_PCI_BASE), //RbPciBar - PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit - }, - - /* Port 7 */ - { - 7, //Segment - PCI_HB0RB7_ECAM_BASE, - 0x90, //BusBase - 0x97, //BusLimit - (PCI_HB0RB7_IO_BASE), //IoBase - (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit - PCI_HB0RB7_CPUMEMREGIONBASE, - PCI_HB0RB7_CPUIOREGIONBASE, - (PCI_HB0RB7_PCI_BASE), //RbPciBar - PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase - PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit - } - }, -{// HostBridge 1 - /* Port 0 */ - { - 8, //Segment - PCI_HB1RB0_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit - PCI_HB1RB0_IO_BASE, //IoBase - (PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit - PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB0_PCI_BASE), //RbPciBar - PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 1 */ - { - 9, //Segment - PCI_HB1RB1_ECAM_BASE, - 0x90, //BusBase - 0x97, //BusLimit - PCI_HB1RB1_IO_BASE, //IoBase - (PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit - PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB1_PCI_BASE), //RbPciBar - PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 2 */ - { - 0xa, //Segment - PCI_HB1RB2_ECAM_BASE, - 0x10, //BusBase - 0x1f, //BusLimit - PCI_HB1RB2_IO_BASE, //IoBase - (PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit - PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB2_PCI_BASE), //RbPciBar - PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit - }, - - /* Port 3 */ - { - 0xb, //Segment - PCI_HB1RB3_ECAM_BASE, - 0xb0, //BusBase - 0xb7, //BusLimit - PCI_HB1RB3_IO_BASE, //IoBase - (PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit - PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB3_PCI_BASE), //RbPciBar - PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 4 */ - { - 0xc, //Segment - PCI_HB1RB4_ECAM_BASE, - 0x20, //BusBase - 0x2f, //BusLimit - PCI_HB1RB4_IO_BASE, //IoBase - (PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit - PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB4_PCI_BASE), //RbPciBar - PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 5 */ - { - 0xd, //Segment - PCI_HB1RB5_ECAM_BASE, - 0x30, //BusBase - 0x3f, //BusLimit - PCI_HB1RB5_IO_BASE, //IoBase - (PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit - PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB5_PCI_BASE), //RbPciBar - PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit - }, - /* Port 6 */ - { - 0xe, //Segment - PCI_HB1RB6_ECAM_BASE, - 0xa8, //BusBase - 0xaf, //BusLimit - PCI_HB1RB6_IO_BASE, //IoBase - (PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit - PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB6_PCI_BASE), //RbPciBar - PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB6_PCIREGION_BASE + PCI_HB1RB6_PCIREGION_SIZE - 1 //PciRegionlimit - }, - - /* Port 7 */ - { - 0xf, //Segment - PCI_HB1RB7_ECAM_BASE, - 0xb8, //BusBase - 0xbf, //BusLimit - PCI_HB1RB7_IO_BASE, //IoBase - (PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit - PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase - PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB1RB7_PCI_BASE), //RbPciBar - PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit - } - - } -}; - diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf deleted file mode 100644 index e20d350cd5914cced2aecaa5aae9577c800bcb3a..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf +++ /dev/null @@ -1,178 +0,0 @@ -## @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2016, Linaro Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = PlatformPciLib - FILE_GUID = B94B8A3A-AD7D-4F26-B140-1E699682176B - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - -[Sources] - PlatformPciLib.c - -[Packages] - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - PcdLib - -[FixedPcd] - gHisiTokenSpaceGuid.PcdHb1BaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize - gHisiTokenSpaceGuid.PciHb0Rb0Base - gHisiTokenSpaceGuid.PciHb0Rb1Base - gHisiTokenSpaceGuid.PciHb0Rb2Base - gHisiTokenSpaceGuid.PciHb0Rb3Base - gHisiTokenSpaceGuid.PciHb0Rb4Base - gHisiTokenSpaceGuid.PciHb0Rb5Base - gHisiTokenSpaceGuid.PciHb0Rb6Base - gHisiTokenSpaceGuid.PciHb0Rb7Base - gHisiTokenSpaceGuid.PciHb1Rb0Base - gHisiTokenSpaceGuid.PciHb1Rb1Base - gHisiTokenSpaceGuid.PciHb1Rb2Base - gHisiTokenSpaceGuid.PciHb1Rb3Base - gHisiTokenSpaceGuid.PciHb1Rb4Base - gHisiTokenSpaceGuid.PciHb1Rb5Base - gHisiTokenSpaceGuid.PciHb1Rb6Base - gHisiTokenSpaceGuid.PciHb1Rb7Base - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress - - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase - gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase - - gHisiTokenSpaceGuid.PcdHb0Rb0IoBase - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize - gHisiTokenSpaceGuid.PcdHb0Rb1IoBase - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize - gHisiTokenSpaceGuid.PcdHb0Rb3IoBase - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize - gHisiTokenSpaceGuid.PcdHb0Rb4IoBase - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize - gHisiTokenSpaceGuid.PcdHb0Rb5IoBase - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize - gHisiTokenSpaceGuid.PcdHb0Rb6IoBase - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize - gHisiTokenSpaceGuid.PcdHb0Rb7IoBase - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize - gHisiTokenSpaceGuid.PcdHb1Rb0IoBase - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize - gHisiTokenSpaceGuid.PcdHb1Rb1IoBase - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize - gHisiTokenSpaceGuid.PcdHb1Rb2IoBase - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize - gHisiTokenSpaceGuid.PcdHb1Rb3IoBase - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize - gHisiTokenSpaceGuid.PcdHb1Rb4IoBase - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize - gHisiTokenSpaceGuid.PcdHb1Rb5IoBase - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize - gHisiTokenSpaceGuid.PcdHb1Rb6IoBase - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize - gHisiTokenSpaceGuid.PcdHb1Rb7IoBase - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize - diff --git a/Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini deleted file mode 100644 index af7d57fd6ed14981546402dec5453f2517821a14..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Head] -NumOfUpdate = 3 -NumOfRecovery = 0 -Update0 = SysFvMain -Update1 = SysCustom -Update2 = SysNvRam - -[SysFvMain] -FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x00000000 # Base address offset on flash -Length = 0x003C0000 # Length -ImageOffset = 0x00000000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - -[SysCustom] -FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x003F0000 # Base address offset on flash -Length = 0x00010000 # Length -ImageOffset = 0x003F0000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - -[SysNvRam] -FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam -AddressType = 0 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x003C0000 # Base address offset on flash -Length = 0x00020000 # Length -ImageOffset = 0x003C0000 # Image offset of this SystemFirmware image -FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid - diff --git a/Platform/Hisilicon/D06/D06.dec b/Platform/Hisilicon/D06/D06.dec deleted file mode 100644 index 64607fed0ea9b77955c539e1e16cdadb0c626edd..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/D06.dec +++ /dev/null @@ -1,23 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -# -# D06 Package -# -# -# - -[Defines] - DEC_SPECIFICATION = 0x0001001A - PACKAGE_NAME = D06Pkg - PACKAGE_GUID = B46F75D7-3864-450D-86D9-A0346A882232 - PACKAGE_VERSION = 0.1 - -[Includes] - Include diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc deleted file mode 100644 index 54e85fff093105037f7df01989b9852ee828cef5..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/D06.dsc +++ /dev/null @@ -1,429 +0,0 @@ -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - PLATFORM_NAME = D06 - PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6 - PLATFORM_VERSION = 0.1 - DSC_SPECIFICATION = 0x0001001A - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 - BUILD_TARGETS = NOOPT|DEBUG|RELEASE - SKUID_IDENTIFIER = DEFAULT - FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf - - # - # Network definition - # - DEFINE NETWORK_TLS_ENABLE = FALSE - DEFINE NETWORK_VLAN_ENABLE = FALSE - DEFINE NETWORK_IP6_ENABLE = FALSE - DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE - -!include Silicon/Hisilicon/Hisilicon.dsc.inc -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses.common] - ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf - - - I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf - TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf - IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf - - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - - CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf - - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf - RtcHelperLib|Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.inf - RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf - HisiOemMiscLib|Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/HisiOemMiscLibD06.inf - OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf - PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf - - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf - - # USB Requirements - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - - LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf - OemNicLib|Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf - PciPlatformLib|Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf - -[LibraryClasses.common.SEC] - ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf - - -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf - -[BuildOptions] - GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1620/Include - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - - ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. - # It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE - gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE -[PcdsDynamicExDefault.common.DEFAULT] - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 - gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89} - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55} - - -[PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdCoreCount|48 - - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 - - - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xA0E88000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 - - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 - - # Size of the region used by UEFI in permanent memory (Reserved 64MB) - gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 - - gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 - - gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 - - ## Serial Terminal - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x94080000 - gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x400094080000 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - - gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000 - - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 - - gHisiTokenSpaceGuid.PcdIsMPBoot|1 - gHisiTokenSpaceGuid.PcdSocketMask|0x3 - !ifdef $(FIRMWARE_VER) - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" - !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 19.02 for Hisilicon D06" - !endif - - gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" - - gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"19.02" - - gHisiTokenSpaceGuid.PcdSystemProductName|L"D06" - gHisiTokenSpaceGuid.PcdSystemVersion|L"VER.A" - gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D06" - gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" - - gHisiTokenSpaceGuid.PcdCPUInfo|L"Hisilicon 1620" - - # TA - gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 - gArmTokenSpaceGuid.PcdGicDistributorBase|0xAE000000 - gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xAE100000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x9B000000 - - gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 - - - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } - gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x94010000 - gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 - - gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x80000000 - gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0x204000000 - - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x94000000 - - ## 2+1 - gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 - - gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 - - gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000 - - gHisiTokenSpaceGuid.PcdNORFlashBase|0x80000000 - gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000 - - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 - gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000 - - # PCIe ECAM Access BaseAddress - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16 - - gHisiTokenSpaceGuid.Pcdsoctype|0x1620 - - # SMBIOS 3.0 only - # BIT0 set indicates 32-bit entry point and table are produced.
- # BIT1 set indicates 64-bit entry point and table are produced.
- gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 - - # - # ACPI Table Version - # - # BIT 1 - EFI_ACPI_TABLE_VERSION_1_0B.
- # BIT 2 - EFI_ACPI_TABLE_VERSION_2_0.
- # BIT 3 - EFI_ACPI_TABLE_VERSION_3_0.
- # BIT 4 - EFI_ACPI_TABLE_VERSION_4_0.
- # BIT 5 - EFI_ACPI_TABLE_VERSION_5_0.
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 - - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 - -################################################################################ -# -# Components Section - list of all EDK II Modules needed by this Platform -# -################################################################################ -[Components.common] - - # - # SEC - # - - # - # PEI Phase modules - # - ArmPlatformPkg/Sec/Sec.inf - MdeModulePkg/Core/Pei/PeiMain.inf - MdeModulePkg/Universal/PCD/Pei/Pcd.inf - - ArmPlatformPkg/PlatformPei/PlatformPeim.inf - - ArmPkg/Drivers/CpuPei/CpuPei.inf - MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf - MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf - MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - - Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf - Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf - - Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - } - - # - # DXE - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf - } - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - - # - # Architectural Protocols - # - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf - - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - - MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { - - CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf - } - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf - - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - ArmPkg/Drivers/ArmGicDxe/ArmGicV3Dxe.inf - - ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - # - #ACPI - # - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf { - - NULL|Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf - } - - Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf - Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - - Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf - Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf - # - # Usb Support - # - MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - # - #network - # -!include NetworkPkg/Network.dsc.inc - - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - # - # FAT filesystem + GPT/MBR partitioning - # - - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf - } - # - # Bds - # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf - Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf - Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf - Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf - - #PCIe Support - Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf - PciHostBridgeLib|Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf - } - - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - - # - # Memory test - # - MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { - - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf - } - - MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf - - # - # UEFI application (Shell Embedded Boot Loader) - # - ShellPkg/Application/Shell/Shell.inf { - - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf -!if $(NETWORK_IP6_ENABLE) == TRUE - NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf -!endif - -!if $(INCLUDE_DP) == TRUE - NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf -!endif #$(INCLUDE_DP) - - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 - } -!if $(INCLUDE_TFTP_COMMAND) == TRUE - ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { - - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - } -!endif #$(INCLUDE_TFTP_COMMAND) - diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf deleted file mode 100644 index 0c98ffa337428c4c4bc9105a3db3df5833735bd8..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/D06.fdf +++ /dev/null @@ -1,399 +0,0 @@ -# -# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. -# Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[DEFINES] - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ -[FD.D06] - -BaseAddress = 0x204800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. - -Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device -ErasePolarity = 1 - -# This one is tricky, it must be: BlockSize * NumBlocks = Size -BlockSize = 0x00010000 -NumBlocks = 0x40 - -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# -################################################################################ - -0x00000000|0x00100000 -gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize -FILE = Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv - -0x00100000|0x00280000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV = FVMAIN_COMPACT - -0x00380000|0x00020000 -gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base -FILE = Platform/Hisilicon/D06/bl1.bin -0x003A0000|0x00020000 -FILE = Platform/Hisilicon/D06/fip.bin - -0x003C0000|0x0000e000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -DATA = { - ## This is the EFI_FIRMWARE_VOLUME_HEADER - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - # FileSystemGuid: gEfiSystemNvDataFvGuid = - 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, - 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, - # FvLength: 0x20000 - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - #Signature "_FVH" #Attributes - 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, - #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision - 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, - #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - #Blockmap[1]: End - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - ## This is the VARIABLE_STORE_HEADER - #Signature: gEfiVariableGuid = - # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} - 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, - 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, - #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 - 0xB8, 0xdF, 0x00, 0x00, - #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 - 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -0x003CE000|0x00002000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -#NV_FTW_WORKING -DATA = { - # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = - 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, - 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, - # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved - 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, - # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 - 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -0x003D0000|0x00010000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - -0x003E0000|0x00010000 - -0x003F0000|0x00010000 -FILE = Platform/Hisilicon/D06/CustomData.Fv - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ - -[FV.FvMain] -BlockSize = 0x40 -NumBlocks = 0 # This FV gets compressed so make it just big enough -FvAlignment = 16 # FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - } - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - INF Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.inf - INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF Platform/Hisilicon/D06/Drivers/SFC/SfcDxeDriver.inf - - INF Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf - INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf - INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # Multiple Console IO support - # - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - INF EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf - - INF ArmPkg/Drivers/ArmGicDxe/ArmGicV3Dxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - - # - # Usb Support - # - - - INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - - INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf - INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - INF Platform/Hisilicon/D06/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf - INF Platform/Hisilicon/D06/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf - INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf - INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf - INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf - INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf - INF Platform/Hisilicon/D06/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf - INF Platform/Hisilicon/D06/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf - INF Platform/Hisilicon/D06/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf - - # - #ACPI - # - INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf - - INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf - INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - INF Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf - - INF Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf - - # - #Network - # -!include NetworkPkg/Network.fdf.inc - - # - # PCI Support - # - INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf - INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf - INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - INF Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.inf - INF Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.inf - - # VGA Driver - # - INF Platform/Hisilicon/D06/Drivers/Sm750Dxe/UefiSmi.inf - INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf - INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - - INF Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - - # - # Build Shell from latest source code instead of prebuilt binary - # - INF ShellPkg/Application/Shell/Shell.inf - - INF MdeModulePkg/Application/UiApp/UiApp.inf - # - # Bds - # - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - -[FV.FVMAIN_COMPACT] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - APRIORI PEI { - INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf - } - INF ArmPlatformPkg/Sec/Sec.inf - INF MdeModulePkg/Core/Pei/PeiMain.inf - INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf - - INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf - INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf - - INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf - - INF Platform/Hisilicon/D06/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf - INF Platform/Hisilicon/D06/MemoryInitPei/MemoryInitPeim.inf - INF ArmPkg/Drivers/CpuPei/CpuPei.inf - INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf - INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf - INF Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf - - INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf - - INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } - } -[FV.CapsuleDispatchFv] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf - -[FV.SystemFirmwareUpdateCargo] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid - FD = D06 - } - - FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid - FV = CapsuleDispatchFv - } - - FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid - Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini - } - -[FmpPayload.FmpPayloadSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 -IMAGE_TYPE_ID = df8fe8d1-e937-45b8-9691-c4b5e183874e # PcdSystemFmpCapsuleImageTypeIdGuid -IMAGE_INDEX = 0x1 -HARDWARE_INSTANCE = 0x0 -MONOTONIC_COUNT = 0x1 -CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 - - FV = SystemFirmwareUpdateCargo - -[Capsule.D06FirmwareUpdateCapsuleFmpPkcs7] -CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid -CAPSULE_HEADER_SIZE = 0x20 -CAPSULE_HEADER_INIT_VERSION = 0x1 - - FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7 - - -!include Silicon/Hisilicon/Hisilicon.fdf.inc - diff --git a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h deleted file mode 100644 index 40bd87e5c810cf2c59246ea5800b3bb20118bbc2..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h +++ /dev/null @@ -1,19 +0,0 @@ -/** @file -* -* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __OEM_NIC_CONFIG_H__ -#define __OEM_NIC_CONFIG_H__ - -#include -#include -#include -#include -#include -#include -#endif diff --git a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c deleted file mode 100644 index 4a26d811f429ed0ec8e04ff4cc2c28e5354d70b6..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c +++ /dev/null @@ -1,65 +0,0 @@ -/** @file -* -* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include - - -EFI_STATUS -EFIAPI OemGetMac2P ( - IN OUT EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ) -{ - OemGetMac (Mac, Port); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI OemSetMac2P ( - IN EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ) -{ - OemSetMac (Mac, Port); - - return EFI_SUCCESS; -} - -HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = { - .GetMac = OemGetMac2P, - .SetMac = OemSetMac2P, -}; - - -EFI_STATUS -EFIAPI -OemNicConfigEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gHisiBoardNicProtocolGuid, - EFI_NATIVE_INTERFACE, - &mHisiBoardNicProtocol2P - ); - - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", - __func__, __LINE__, Status)); - return Status; - } - - return EFI_SUCCESS; -} - diff --git a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf deleted file mode 100644 index ebc7e7791ec36351e4a62a34f4476a46c2d563c1..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf +++ /dev/null @@ -1,37 +0,0 @@ -#/** @file -# -# Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016-2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = OemNicConfigPangea - FILE_GUID = edc95319-ebe9-4c38-96af-1d203fb85231 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = OemNicConfigEntry - -[Sources.common] - OemNicConfig2P.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[Protocols] - gHisiBoardNicProtocolGuid ##Produce - -[LibraryClasses] - DebugLib - IoLib - OemNicLib - UefiBootServicesTableLib - UefiDriverEntryPoint - -[Depex] - TRUE diff --git a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc deleted file mode 100644 index 63ce44729276035bb3e6516a7dfb4dab202cd3a3..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc +++ /dev/null @@ -1,75 +0,0 @@ -/** @file - System Firmware descriptor. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include - -#define PACKAGE_VERSION 0xFFFFFFFF -#define PACKAGE_VERSION_STRING L"Unknown" - -#define CURRENT_FIRMWARE_VERSION 0x00000003 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000003" -#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000003 - -#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd') -#define IMAGE_ID_STRING L"ARMPlatformFd" - -// PcdSystemFmpCapsuleImageTypeIdGuid -#define IMAGE_TYPE_ID_GUID { 0xdf8fe8d1, 0xe937, 0x45b8, { 0x96, 0x91, 0xc4, 0xb5, 0xe1, 0x83, 0x87, 0x4e } } - -typedef struct { - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; - // real string data - CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE_ID_STRING)]; - CHAR16 VersionNameStr[ARRAY_SIZE (CURRENT_FIRMWARE_VERSION_STRING)]; - CHAR16 PackageVersionNameStr[ARRAY_SIZE (PACKAGE_VERSION_STRING)]; -} IMAGE_DESCRIPTOR; - -IMAGE_DESCRIPTOR mImageDescriptor = -{ - { - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, - sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), - sizeof (IMAGE_DESCRIPTOR), - PACKAGE_VERSION, // PackageVersion - OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName - 1, // ImageIndex; - {0x0}, // Reserved - IMAGE_TYPE_ID_GUID, // ImageTypeId; - IMAGE_ID, // ImageId; - OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; - CURRENT_FIRMWARE_VERSION, // Version; - OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; - {0x0}, // Reserved2 - FixedPcdGet32 (PcdFdSize), // Size; - IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | - IMAGE_ATTRIBUTE_RESET_REQUIRED | - IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported; - IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | - IMAGE_ATTRIBUTE_RESET_REQUIRED | - IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting; - 0x0, // Compatibilities; - LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; - 0x00000000, // LastAttemptVersion; - 0, // LastAttemptStatus; - {0x0}, // Reserved3 - 0, // HardwareInstance; - }, - // real string data - {IMAGE_ID_STRING}, - {CURRENT_FIRMWARE_VERSION_STRING}, - {PACKAGE_VERSION_STRING}, -}; - -VOID* CONST ReferenceAcpiTable = &mImageDescriptor; diff --git a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf deleted file mode 100644 index 67568145740265c5ecb22f7599b00f140577a945..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ /dev/null @@ -1,44 +0,0 @@ -## @file -# System Firmware descriptor. -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = SystemFirmwareDescriptor - FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = SystemFirmwareDescriptorPeimEntry - -[Sources] - SystemFirmwareDescriptorPei.c - SystemFirmwareDescriptor.aslc - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - SignedCapsulePkg/SignedCapsulePkg.dec - -[LibraryClasses] - DebugLib - PcdLib - PeimEntryPoint - PeiServicesLib - -[FixedPcd] - gArmTokenSpaceGuid.PcdFdSize - -[Pcd] - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor - -[Depex] - TRUE diff --git a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c deleted file mode 100644 index 77f631d5d6f149960b600875721ce50006e65ae0..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c +++ /dev/null @@ -1,64 +0,0 @@ -/** @file - System Firmware descriptor producer. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -/** - Entrypoint for SystemFirmwareDescriptor PEIM. - - @param[in] FileHandle Handle of the file being invoked. - @param[in] PeiServices Describes the list of possible PEI Services. - - @retval EFI_SUCCESS PPI successfully installed. -**/ -EFI_STATUS -EFIAPI -SystemFirmwareDescriptorPeimEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; - UINTN Size; - UINTN Index; - UINT32 AuthenticationStatus; - - // - // Search RAW section. - // - - Index = 0; - while (TRUE) { - Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus); - if (EFI_ERROR (Status)) { - // Should not happen, must something wrong in FDF. - DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n")); - return EFI_NOT_FOUND; - } - if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) { - break; - } - Index++; - } - - DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length)); - - Size = Descriptor->Length; - PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); - - return EFI_SUCCESS; -} diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c deleted file mode 100644 index 72f30ff0755027aaa36358ee61b6329777ed7a7f..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c +++ /dev/null @@ -1,101 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PERI_SUBCTRL_BASE (0x40000000) -#define MDIO_SUBCTRL_BASE (0x60000000) -#define PCIE2_SUBCTRL_BASE (0xA0000000) -#define PCIE0_SUBCTRL_BASE (0xB0000000) -#define ALG_BASE (0xD0000000) - -#define SC_BROADCAST_EN_REG (0x16220) -#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230) -#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234) -#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238) -#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C) -#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240) -#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C) -#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200) -#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0) -#define SC_TM_CLKEN0_REG (0x2050) - -#define SC_TM_CLKEN0_REG_VALUE (0x3) -#define SC_BROADCAST_EN_REG_VALUE (0x7) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260) -#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400) -#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7) -#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e) - -STATIC -VOID -QResetAp ( - VOID - ) -{ - MmioWrite64 (FixedPcdGet64 (PcdMailBoxAddress), 0x0); - (VOID)WriteBackInvalidateDataCacheRange ( - (VOID *)FixedPcdGet64 (PcdMailBoxAddress), - sizeof (UINT64) - ); - - //SCCL A - if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartUpBSP (); - } -} - - -EFI_STATUS -EFIAPI -EarlyConfigEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - DEBUG ((DEBUG_INFO,"SMMU CONFIG.........")); - (VOID)SmmuConfigForBios (); - DEBUG ((DEBUG_INFO,"Done\n")); - - DEBUG ((DEBUG_INFO,"AP CONFIG.........")); - (VOID)QResetAp (); - DEBUG ((DEBUG_INFO,"Done\n")); - - DEBUG ((DEBUG_INFO,"MN CONFIG.........")); - (VOID)MN_CONFIG (); - DEBUG ((DEBUG_INFO,"Done\n")); - - return EFI_SUCCESS; -} - diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf deleted file mode 100644 index 8eaec842c86d49eed7db632bc8daa987827b2492..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf +++ /dev/null @@ -1,45 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = EarlyConfigPeimD06 - FILE_GUID = FB8C65EB-0199-40C3-A82B-029921A9E9B3 - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = EarlyConfigEntry - -[Sources.common] - EarlyConfigPeimD06.c - -[Packages] - ArmPkg/ArmPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - ArmLib - CacheMaintenanceLib - DebugLib - IoLib - PcdLib - PeimEntryPoint - PlatformSysCtrlLib - -[Pcd] - gHisiTokenSpaceGuid.PcdMailBoxAddress - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable - -[Depex] -## As we will clean mailbox in this module, need to wait memory init complete - gEfiPeiMemoryDiscoveredPpiGuid diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h deleted file mode 100644 index e5adfb316fd7dce20fb1de9d0f951db562adce58..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @file - - Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2018, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __CPLDD06_H__ -#define __CPLDD06_H__ - -#define CPLD_BASE_ADDRESS 0x80000000 - -#define CPLD_BIOSINDICATE_FLAG 0x09 -#define CPLD_I2C_SWITCH_FLAG 0x17 -#define CPU_GET_I2C_CONTROL BIT2 -#define BMC_I2C_STATUS BIT3 - -#define CPLD_LOGIC_VERSION (0x4) -#define CPLD_LOGIC_COMPILE_YEAR (0x1) -#define CPLD_LOGIC_COMPILE_MONTH (0x2) -#define CPLD_LOGIC_COMPILE_DAY (0x3) - -#define CPLD_RISER_PRSNT_FLAG 0x40 -#define CPU1_RISER_PRESENT BIT6 -#define CPU0_RISER_PRESENT BIT7 -#define CPLD_RISER2_BOARD_ID 0x44 - -#define CPLD_X8_X8_X8_BOARD_ID 0x92 -#define CPLD_X16_X8_BOARD_ID 0x93 - -#define CPLD_CLOCK_FLAG 0xFD -#define CPLD_BOM_VER_FLAG 0x0B -#define CPLD_BOARD_REVISION_4TH 0x4 - -#endif /* __CPLDD06_H__ */ diff --git a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/BoardFeatureD06.c deleted file mode 100644 index b8a4003c80ff8509d0490e84d7ca558007bafcaa..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/BoardFeatureD06.c +++ /dev/null @@ -1,425 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -I2C_DEVICE gRtcDevice = { - .Socket = 0, - .Port = 5, - .DeviceType = DEVICE_TYPE_SPD, - .SlaveDeviceAddress = 0x68 -}; - -SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = -{ - {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} -}; - -SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = -{ - {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} -}; - -SERDES_PARAM gSerdesParamNA = { - .Hilink0Mode = EmHilink0Hccs1X8Width16, - .Hilink1Mode = EmHilink1Hccs0X8Width16, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Sas1X4, - .Hilink6Mode = 0x0, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParamNB = { - .Hilink0Mode = EmHilink0Pcie1X8, - .Hilink1Mode = EmHilink1Pcie0X8, - .Hilink2Mode = EmHilink2Sas0X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2, - .Hilink6Mode = 0xF, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParamS1NA = { - .Hilink0Mode = EmHilink0Hccs1X8Width16, - .Hilink1Mode = EmHilink1Hccs0X8Width16, - .Hilink2Mode = EmHilink2Pcie2X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Sas1X4, - .Hilink6Mode = 0x0, - .UseSsc = 0, -}; - -SERDES_PARAM gSerdesParamS1NB = { - .Hilink0Mode = EmHilink0Pcie1X8, - .Hilink1Mode = EmHilink1Pcie0X8, - .Hilink2Mode = EmHilink2Sas0X8, - .Hilink3Mode = 0x0, - .Hilink4Mode = 0xF, - .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2, - .Hilink6Mode = 0xF, - .UseSsc = 0, -}; - - -EFI_STATUS -OemGetSerdesParam ( - OUT SERDES_PARAM *ParamA, - OUT SERDES_PARAM *ParamB, - IN UINT32 SocketId - ) -{ - if (NULL == ParamA) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } if (NULL == ParamB) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - if (0 == SocketId) { - (VOID) CopyMem (ParamA, &gSerdesParamNA, sizeof (*ParamA)); - (VOID) CopyMem (ParamB, &gSerdesParamNB, sizeof (*ParamB)); - } else { - (VOID) CopyMem (ParamA, &gSerdesParamS1NA, sizeof (*ParamA)); - (VOID) CopyMem (ParamB, &gSerdesParamS1NB, sizeof (*ParamB)); - } - - return EFI_SUCCESS; -} - -VOID -OemPcieResetAndOffReset ( - VOID - ) -{ - return; -} - -SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { - // PCIe0 Slot 1 - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX16, // SlotType - SlotDataBusWidth16X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0001, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0002, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0003, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - - - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0004, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX16, // SlotType - SlotDataBusWidth16X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0005, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0006, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0007, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0008, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum - }, - - }; - -UINT8 -OemGetPcieSlotNumber ( - VOID - ) -{ - return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); -} - -EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { - {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_040), STRING_TOKEN(STR_LEMON_C10_DIMM_041)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_050), STRING_TOKEN(STR_LEMON_C10_DIMM_051)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_060), STRING_TOKEN(STR_LEMON_C10_DIMM_061)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_070), STRING_TOKEN(STR_LEMON_C10_DIMM_071)}}, - - {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_140), STRING_TOKEN(STR_LEMON_C10_DIMM_141)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_150), STRING_TOKEN(STR_LEMON_C10_DIMM_151)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_160), STRING_TOKEN(STR_LEMON_C10_DIMM_161)}, - {STRING_TOKEN(STR_LEMON_C10_DIMM_170), STRING_TOKEN(STR_LEMON_C10_DIMM_171)}} -}; - -EFI_HII_HANDLE -EFIAPI -OemGetPackages ( - VOID - ) -{ - return HiiAddPackages ( - &gEfiCallerIdGuid, - NULL, - HisiOemMiscLibStrings, - NULL, - NULL - ); -} - - diff --git a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/BoardFeatureD06Strings.uni b/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/BoardFeatureD06Strings.uni deleted file mode 100644 index 3696d1f11ef8dede0b153cbf572aef048c32e2be..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/BoardFeatureD06Strings.uni +++ /dev/null @@ -1,60 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// --*/ - -/=# - -#langdef en-US "English" - -// -// Begin English Language Strings -// -#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" - -// -// DIMM Device Locator strings - -// D06 -#string STR_LEMON_C10_DIMM_000 #language en-US "J5" -#string STR_LEMON_C10_DIMM_001 #language en-US "J6" -#string STR_LEMON_C10_DIMM_010 #language en-US "J7" -#string STR_LEMON_C10_DIMM_011 #language en-US "J8" -#string STR_LEMON_C10_DIMM_020 #language en-US "J9" -#string STR_LEMON_C10_DIMM_021 #language en-US "J10" -#string STR_LEMON_C10_DIMM_030 #language en-US "J11" -#string STR_LEMON_C10_DIMM_031 #language en-US "J12" -#string STR_LEMON_C10_DIMM_040 #language en-US "J13" -#string STR_LEMON_C10_DIMM_041 #language en-US "J14" -#string STR_LEMON_C10_DIMM_050 #language en-US "J15" -#string STR_LEMON_C10_DIMM_051 #language en-US "J16" -#string STR_LEMON_C10_DIMM_060 #language en-US "J17" -#string STR_LEMON_C10_DIMM_061 #language en-US "J18" -#string STR_LEMON_C10_DIMM_070 #language en-US "J19" -#string STR_LEMON_C10_DIMM_071 #language en-US "J20" -#string STR_LEMON_C10_DIMM_100 #language en-US "J21" -#string STR_LEMON_C10_DIMM_101 #language en-US "J22" -#string STR_LEMON_C10_DIMM_110 #language en-US "J23" -#string STR_LEMON_C10_DIMM_111 #language en-US "J24" -#string STR_LEMON_C10_DIMM_120 #language en-US "J25" -#string STR_LEMON_C10_DIMM_121 #language en-US "J26" -#string STR_LEMON_C10_DIMM_130 #language en-US "J27" -#string STR_LEMON_C10_DIMM_131 #language en-US "J28" -#string STR_LEMON_C10_DIMM_140 #language en-US "J29" -#string STR_LEMON_C10_DIMM_141 #language en-US "J30" -#string STR_LEMON_C10_DIMM_150 #language en-US "J31" -#string STR_LEMON_C10_DIMM_151 #language en-US "J32" -#string STR_LEMON_C10_DIMM_160 #language en-US "J33" -#string STR_LEMON_C10_DIMM_161 #language en-US "J34" -#string STR_LEMON_C10_DIMM_170 #language en-US "J35" -#string STR_LEMON_C10_DIMM_171 #language en-US "J36" - -// -// End English Language Strings -// - diff --git a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/HisiOemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/HisiOemMiscLibD06.inf deleted file mode 100644 index 01ff51feb9f28b94d36e387ca4b4284f0474a924..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/HisiOemMiscLibD06.inf +++ /dev/null @@ -1,44 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = HisiOemMiscLib - FILE_GUID = 3002911C-C160-4C46-93BB-782846673EEA - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = HisiOemMiscLib - -[Sources.common] - BoardFeatureD06.c - BoardFeatureD06Strings.uni - OemMiscLibD06.c - -[Packages] - ArmPkg/ArmPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Platform/Hisilicon/D06/D06.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseMemoryLib - CpldIoLib - IoLib - PcdLib - TimerLib - -[Ppis] - gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES - -[Pcd] - gHisiTokenSpaceGuid.PcdIsMPBoot - gHisiTokenSpaceGuid.PcdSocketMask - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable diff --git a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/OemMiscLibD06.c deleted file mode 100644 index 0e6e1b39a83ddbe4e85b35e34111e521a4992a24..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/HisiOemMiscLibD06/OemMiscLibD06.c +++ /dev/null @@ -1,226 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { - {67,0,0,0}, - {225,0,0,3}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF} -}; - -//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8) -REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = { - {0x01,0,0,0}, - {0x03,0,0,1}, - {0xFF,0xFF,0xFF,2}, - {0x81,0,0,3}, - {0x84,0,0,4}, - {0xFF,0xFF,0xFF,5} -}; - -//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8) -REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = { - {0x01,0,0,0}, - {0x03,0,0,1}, - {0xFF,0xFF,0xFF,2}, - {0xFF,0xFF,0xFF,3}, - {0x81,0,0,4}, - {0x85,0,0,5} -}; - -//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8) -REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = { - {0xFF,0xFF,0xFF,0}, - {0x01,0,0,1}, - {0x04,0,0,2}, - {0x81,0,0,3}, - {0x84,0,0,4}, - {0xFF,0xFF,0xFF,5} -}; - -//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8) -REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = { - {0xFF,0xFF,0xFF,0}, - {0x01,0,0,1}, - {0x04,0,0,2}, - {0xFF,0xFF,0xFF,3}, - {0x81,0,0,4}, - {0x85,0,0,5} -}; - -VOID -GetPciDidVid ( - REPORT_PCIEDIDVID2BMC *Report - ) -{ - UINT32 PresentStatus; - UINT32 CardType; - UINT8 Cpu0CardType = 0; - UINT8 Cpu1CardType = 0; - - PresentStatus = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG); - CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID); - - // Offset 0x40: Bit7 = 1 CPU0 Riser present - if ((PresentStatus & CPU0_RISER_PRESENT) != 0) { - Cpu0CardType = (UINT8) (PresentStatus >> 8); - } - - // Offset 0x40: Bit6 = 1 CPU1 Riser present - if ((PresentStatus & CPU1_RISER_PRESENT) != 0) { - Cpu1CardType = (UINT8)CardType; - } - - if (OemIsMpBoot ()) { - if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) { - if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type1, - sizeof (PcieDeviceToReport_2P_Type1)); - } else { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type2, - sizeof (PcieDeviceToReport_2P_Type2)); - } - } else { - if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type3, - sizeof (PcieDeviceToReport_2P_Type3)); - } else { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type4, - sizeof (PcieDeviceToReport_2P_Type4)); - } - } - } else { - (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, - sizeof (PcieDeviceToReport)); - } -} - - -// Right now we only support 1P -BOOLEAN -OemIsSocketPresent ( - UINTN Socket - ) -{ - UINT32 SocketMask = PcdGet32 (PcdSocketMask); - return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE); -} - - -UINTN -OemGetSocketNumber ( - VOID - ) -{ - if(!OemIsMpBoot ()) { - return 1; - } - - return MAX_PROCESSOR_SOCKETS; -} - - -UINTN -OemGetDdrChannel ( - VOID - ) -{ - return MAX_MEMORY_CHANNELS; -} - - -UINTN -OemGetDimmSlot ( - UINTN Socket, - UINTN Channel - ) -{ - return MAX_DIMM_PER_CHANNEL; -} - - -BOOLEAN -OemIsMpBoot ( - VOID - ) -{ - return PcdGet32 (PcdIsMPBoot); -} - -VOID -OemLpcInit ( - VOID - ) -{ - LpcInit (); - return; -} - -UINT32 -OemIsWarmBoot ( - VOID - ) -{ - return 0; -} - -VOID -OemBiosSwitch ( - UINT32 Master - ) -{ - (VOID)Master; - return; -} - -BOOLEAN -OemIsNeedDisableExpanderBuffer ( - VOID - ) -{ - return TRUE; -} - -UINTN OemGetCpuFreq (UINT8 Socket) -{ - UINT8 BoardRevision; - - BoardRevision = MmioRead8 (CPLD_BASE_ADDRESS + CPLD_BOM_VER_FLAG); - - // Board revision 4 and higher run at 2.5GHz - // Earlier revisions run at 2GHz - if (BoardRevision >= CPLD_BOARD_REVISION_4TH) { - return 2500000000; - } else { - return 2000000000; - } -} - -UINTN -OemGetHccsFreq ( - VOID - ) -{ - return HCCS_PLL_VALUE_2600; -} - diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c deleted file mode 100644 index 11e539f7ba2b1114bf46dcf754eb87ec09780680..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c +++ /dev/null @@ -1,390 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include - -#define CPU2_SFP2_100G_CARD_OFFSET 0x25 - -#define SOCKET1_NET_PORT_100G 1 -#define SOCKET0_NET_PORT_NUM 4 -#define SOCKET1_NET_PORT_NUM 2 - -#define CARD_PRESENT_100G (BIT7) -#define EEPROM_I2C_PORT 4 -#define EEPROM_PAGE_SIZE 0x40 -#define MAC_ADDR_LEN 6 -#define I2C_OFFSET_EEPROM_ETH0 (0xc00) -#define I2C_SLAVEADDR_EEPROM (0x52) - -#define SRAM_NIC_NCL1_OFFSET_ADDRESS 0xA0E87FE0 -#define SRAM_NIC_NCL2_OFFSET_ADDRESS 0xA0E87FE4 - -#pragma pack(1) -typedef struct { - UINT16 Crc16; - UINT16 MacLen; - UINT8 Mac[MAC_ADDR_LEN]; -} NIC_MAC_ADDRESS; -#pragma pack() - -ETH_PRODUCT_DESC gEthPdtDesc[ETH_MAX_PORT] = -{ - {TRUE, ETH_SPEED_10KM, ETH_FULL_DUPLEX, ETH_INVALID, ETH_INVALID}, - {TRUE, ETH_SPEED_10KM, ETH_FULL_DUPLEX, ETH_INVALID, ETH_INVALID}, - {FALSE, ETH_INVALID, ETH_INVALID, ETH_INVALID, ETH_INVALID}, - {FALSE, ETH_INVALID, ETH_INVALID, ETH_INVALID, ETH_INVALID}, - {TRUE, ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 0}, - {TRUE, ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 1}, - {FALSE, ETH_INVALID, ETH_INVALID, ETH_INVALID, ETH_INVALID}, - {FALSE, ETH_INVALID, ETH_INVALID, ETH_INVALID, ETH_INVALID} -}; - -UINT16 CrcTable16[256] = { - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, - 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, - 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, - 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, - 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, - 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, - 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, - 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, - 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, - 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, - 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, - 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, - 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, - 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, - 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, - 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, - 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, - 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, - 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, - 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, - 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, - 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, - 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, -}; - -UINT16 MakeCrcCheckSum ( - UINT8 *Buffer, - UINT32 Length - ) -{ - UINT16 StartCRC = 0; - - if (Length > SIZE_512KB) { - return 0; - } - - if (Buffer == NULL) { - return 0; - } - - while (Length) { - StartCRC = CrcTable16 [((UINT8) ((StartCRC >> 8) & 0xff)) ^ *(Buffer++)] ^ - ((UINT16) (StartCRC << 8)); - Length--; - } - - return StartCRC; -} - - -EFI_STATUS -OemGetMacE2prom( - IN UINT32 Port, - OUT UINT8 *Addr - ) -{ - I2C_DEVICE I2cDev = {0}; - EFI_STATUS Status; - UINT16 I2cOffset; - UINT16 Crc16; - NIC_MAC_ADDRESS MacDesc = {0}; - UINT16 RemainderMacOffset; - UINT16 LessSizeOfPage; - UINT32 I = 0; - - Status = I2CInit (0, EEPROM_I2C_PORT, Normal); - if (EFI_ERROR (Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", - __func__, __LINE__, Status)); - return Status; - } - - I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof (NIC_MAC_ADDRESS)); - - I2cDev.DeviceType = DEVICE_TYPE_E2PROM; - I2cDev.Port = EEPROM_I2C_PORT; - I2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; - I2cDev.Socket = 0; - RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; - LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; - //The length of NIC_MAC_ADDRESS is 10 bytes long, - //It surly less than EEPROM page size, so we could - //code as below, check the address whether across the page boundary, - //and split the data when across page boundary. - if (sizeof (NIC_MAC_ADDRESS) <= LessSizeOfPage) { - Status = I2CRead (&I2cDev, I2cOffset, sizeof (NIC_MAC_ADDRESS), (UINT8 *) &MacDesc); - } else { - Status = I2CRead (&I2cDev, I2cOffset, LessSizeOfPage, (UINT8 *) &MacDesc); - if (!EFI_ERROR (Status)) { - Status |= I2CRead ( - &I2cDev, - I2cOffset + LessSizeOfPage, - sizeof (NIC_MAC_ADDRESS) - LessSizeOfPage, - (UINT8 *) &MacDesc + LessSizeOfPage - ); - } - } - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", - __func__, __LINE__, Status)); - return Status; - } - - Crc16 = MakeCrcCheckSum ( - (UINT8 *)&(MacDesc.MacLen), - sizeof (MacDesc.MacLen) + sizeof (MacDesc.Mac) - ); - if ((Crc16 != MacDesc.Crc16) || (Crc16 == 0)) { - return EFI_NOT_FOUND; - } - - for (I = 0; I < MAC_ADDR_LEN; I++) { - Addr[I] = MacDesc.Mac[I]; - } - - return EFI_SUCCESS; -} - - -EFI_STATUS -OemSetMacE2prom ( - IN UINT32 Port, - IN UINT8 *Addr - ) -{ - I2C_DEVICE I2cDev = {0}; - EFI_STATUS Status; - UINT16 I2cOffset; - NIC_MAC_ADDRESS MacDesc = {0}; - UINT32 I; - UINT16 RemainderMacOffset; - UINT16 LessSizeOfPage; - - I = 0; - MacDesc.MacLen = MAC_ADDR_LEN; - - for (I = 0; I < MAC_ADDR_LEN; I++) { - MacDesc.Mac[I] = Addr[I]; - } - - MacDesc.Crc16 = MakeCrcCheckSum ( - (UINT8 *)&(MacDesc.MacLen), - sizeof (MacDesc.MacLen) + MAC_ADDR_LEN - ); - - Status = I2CInit (0, EEPROM_I2C_PORT, Normal); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", - __func__, __LINE__, Status)); - return Status; - } - - I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof (NIC_MAC_ADDRESS)); - - I2cDev.DeviceType = DEVICE_TYPE_E2PROM; - I2cDev.Port = EEPROM_I2C_PORT; - I2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; - I2cDev.Socket = 0; - RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; - LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; - //The length of NIC_MAC_ADDRESS is 10 bytes long, - //It surly less than EEPROM page size, so we could - //code as below, check the address whether across the page boundary, - //and split the data when across page boundary. - if (sizeof (NIC_MAC_ADDRESS) <= LessSizeOfPage) { - Status = I2CWrite ( - &I2cDev, - I2cOffset, - sizeof (NIC_MAC_ADDRESS), - (UINT8 *) &MacDesc - ); - } else { - Status = I2CWrite (&I2cDev, I2cOffset, LessSizeOfPage, (UINT8 *) &MacDesc); - if (!EFI_ERROR (Status)) { - Status |= I2CWrite ( - &I2cDev, - I2cOffset + LessSizeOfPage, - sizeof (NIC_MAC_ADDRESS) - LessSizeOfPage, - (UINT8 *) &MacDesc + LessSizeOfPage - ); - } - } - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", - __func__, __LINE__, Status)); - return Status; - } - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -OemGetMac ( - IN OUT EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ) -{ - EFI_STATUS Status; - - if (Mac == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Mac buffer is null!\n", - __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - Status = OemGetMacE2prom (Port, Mac->Addr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, - "[%a]:[%dL] Cannot get MAC from EEPROM, Status: %r; using default MAC.\n", - __func__, __LINE__, Status)); - - Mac->Addr[0] = 0xFF; - Mac->Addr[1] = 0xFF; - Mac->Addr[2] = 0xFF; - Mac->Addr[3] = 0xFF; - Mac->Addr[4] = 0xFF; - Mac->Addr[5] = 0xFF; - return EFI_SUCCESS; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -OemSetMac ( - IN EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ) -{ - EFI_STATUS Status; - - if (Mac == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Mac buffer is null!\n", - __func__, __LINE__)); - return EFI_INVALID_PARAMETER; - } - - Status = OemSetMacE2prom (Port, Mac->Addr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Set mac failed!\n", __func__, __LINE__)); - return Status; - } - - return EFI_SUCCESS; -} - -UINT32 -OemEthFindFirstSP ( - VOID - ) -{ - UINT32 I; - - for (I = 0; I < ETH_MAX_PORT; I++) { - if (gEthPdtDesc[I].Valid == TRUE) { - return I; - } - } - - return ETH_INVALID; -} - -ETH_PRODUCT_DESC * -OemEthInit ( - UINT32 port - ) -{ - return (ETH_PRODUCT_DESC *)(&(gEthPdtDesc[port])); -} - - -BOOLEAN -OemIsInitEth ( - UINT32 Port - ) -{ - return TRUE; -} - -EFI_STATUS -ConfigCDR ( - UINT32 Socket - ) -{ - return EFI_SUCCESS; -} - -UINT32 -OemGetNclConfOffset ( - UINT32 Socket - ) -{ - UINT32 ConfigurationOffset; - - if (Socket == 0) { - // For 1st socket, the NCL configuration offset is 0 - ConfigurationOffset = 0; - MmioWrite32 (SRAM_NIC_NCL1_OFFSET_ADDRESS, ConfigurationOffset); - return ConfigurationOffset; - } - - // For 2nd Socket - if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { - ConfigurationOffset = SIZE_128KB; - } else { - ConfigurationOffset = SIZE_64KB; - } - MmioWrite32 (SRAM_NIC_NCL2_OFFSET_ADDRESS, ConfigurationOffset); - return ConfigurationOffset; -} - -UINT32 -OemGetNetPortNum ( - UINT32 Socket - ) -{ - if (Socket == 0){ - return SOCKET0_NET_PORT_NUM; - } - - if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { - return SOCKET1_NET_PORT_100G; - } else { - return SOCKET1_NET_PORT_NUM; - } -} diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf deleted file mode 100644 index c42f5d6e6a2a4b9df93bbc4f9c53f9ee072c7540..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf +++ /dev/null @@ -1,29 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = OemNicLib - FILE_GUID = 520F872C-FFCF-4EF3-AC01-85BDB0816DCE - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = OemNicLib - -[Sources.common] - OemNicLib.c - -[Packages] - ArmPkg/ArmPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - CpldIoLib - I2CLib diff --git a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c deleted file mode 100644 index c44959b7f11209223bf606089952fe5eb7ebc4d6..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ /dev/null @@ -1,629 +0,0 @@ -/** @file - - Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2018, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include -#include -#include - -#define ENUM_HB_NUM 8 - -#define EFI_PCI_SUPPORT (EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ - EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ - EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \ - EFI_PCI_ATTRIBUTE_ISA_IO_16 | \ - EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ - EFI_PCI_ATTRIBUTE_VGA_IO_16 | \ - EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16) - -#define EFI_PCI_ATTRIBUTE EFI_PCI_SUPPORT - -#pragma pack(1) -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; -#pragma pack () - -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath [ENUM_HB_NUM] = { -//Host Bridge 0 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 0 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 2 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 2 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 4 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 4 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 5 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 5 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 6 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 6 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 8 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 8 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 10 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 10 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - -//Host Bridge 11 - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8)sizeof (ACPI_HID_DEVICE_PATH), - (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 11 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - } -}; - -STATIC PCI_ROOT_BRIDGE gRootBridge [ENUM_HB_NUM] = { -//Host Bridge 0 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 00, - 0x3F - }, - { // Io (32K) - 0, - 0x7FFF - }, - { // Mem (256M - 64K - 1) - 0xE0000000, - 0xEFFEFFFF - }, - { // MemAbove4G (8T + 256G) - 0x80000000000, - 0x83FFFFFFFFF - }, - { // PMem - 0xE0000000, - 0xEFFEFFFF - }, - { // PMemAbove4G - 0x80000000000, - 0x83FFFFFFFFF - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] - }, - - //Host Bridge 2 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0x7A, - 0x7A - }, - { // Io - MAX_UINT32, - 0 - }, - { // Mem - MAX_UINT32, - 0 - }, - { // MemAbove4G - 0x20c000000, - 0x20c1fffff - }, - { // PMem - MAX_UINT32, - 0 - }, - { // PMemAbove4G - MAX_UINT64, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] - }, - - //Host Bridge 4 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0x7C, - 0x7D - }, - { // Io - MAX_UINT32, - 0 - }, - { // Mem - MAX_UINT32, - 0 - }, - { // MemAbove4G - 0x120000000, - 0x13fffffff - }, - { // PMem - MAX_UINT32, - 0 - }, - { // PMemAbove4G - MAX_UINT64, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[2] - }, - - //Host Bridge 5 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0x74, - 0x76 - }, - { // Io - MAX_UINT32, - 0 - }, - { // Mem - 0xA2000000, - 0xA2ffffff - }, - { // MemAbove4G - 0x144000000, - 0x147ffffff - }, - { // PMem - MAX_UINT32, - 0 - }, - { // PMemAbove4G - MAX_UINT64, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[3] - }, - //Host Bridge 6 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0x80, - 0x9F - }, - { // Io (32K) - 0x0, - 0x7FFF - }, - { // Mem (256M - 64K -1) - 0xF0000000, - 0xFFFEFFFF - }, - { // MemAbove4G (8T + 256G) - 0x480000000000, - 0x483FFFFFFFFF - }, - { // PMem - 0xF0000000, - 0xFFFEFFFF - }, - { // PMemAbove4G - 0x480000000000, - 0x483FFFFFFFFF - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[4] - }, - - //Host Bridge 8 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0xBA, - 0xBA - }, - { // Io - MAX_UINT32, - 0 - }, - { // Mem - MAX_UINT32, - 0 - }, - { // MemAbove4G - 0x40020c000000, - 0x40020c1fffff - }, - { // PMem - MAX_UINT32, - 0 - }, - { // PMemAbove4G - MAX_UINT64, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[5] - }, - - //Host Bridge 10 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0xBC, - 0xBD - }, - { // Io - MAX_UINT32, - 0 - }, - { // Mem - MAX_UINT32, - 0 - }, - { // MemAbove4G - 0x400120000000, - 0x40013fffffff - }, - { // PMem - MAX_UINT32, - 0 - }, - { // PMemAbove4G - MAX_UINT64, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[6] - }, - - //Host Bridge 11 - { - 0, // Segment - EFI_PCI_SUPPORT, // Supports - EFI_PCI_ATTRIBUTE, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { // Bus - 0xB4, - 0xB6 - }, - { // Io - MAX_UINT32, - 0 - }, - { // Mem - 0xA3000000, - 0xA3ffffff - }, - { // MemAbove4G - 0x400144000000, - 0x400147ffffff - }, - { // PMem - MAX_UINT32, - 0 - }, - { // PMemAbove4G - MAX_UINT64, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[7] - } - -}; - -/** - Return all the root bridge instances in an array. - - @param Count Return the count of root bridge instances. - - @return All the root bridge instances in an array. - The array should be passed into PciHostBridgeFreeRootBridges() - when it's not used. -**/ -PCI_ROOT_BRIDGE * -EFIAPI -PciHostBridgeGetRootBridges ( - UINTN *Count - ) -{ - *Count = ENUM_HB_NUM; - - return gRootBridge; -} - -/** - Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). - - @param Bridges The root bridge instances array. - @param Count The count of the array. -**/ -VOID -EFIAPI -PciHostBridgeFreeRootBridges ( - PCI_ROOT_BRIDGE *Bridges, - UINTN Count - ) -{ - if (Bridges == NULL && Count == 0) { - return; - } - - do { - --Count; - FreePool (Bridges[Count].DevicePath); - } while (Count > 0); - - FreePool (Bridges); -} - -STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { - L"Mem", L"I/O", L"Bus" -}; - -/** - Inform the platform that the resource conflict happens. - - @param HostBridgeHandle Handle of the Host Bridge. - @param Configuration Pointer to PCI I/O and PCI memory resource - descriptors. The Configuration contains the resources - for all the root bridges. The resource for each root - bridge is terminated with END descriptor and an - additional END is appended indicating the end of the - entire resources. The resource descriptor field - values follow the description in - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL - .SubmitResources(). -**/ -VOID -EFIAPI -PciHostBridgeResourceConflict ( - EFI_HANDLE HostBridgeHandle, - VOID *Configuration - ) -{ - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; - UINTN RootBridgeIndex; - - DEBUG ((DEBUG_ERROR, "\n PciHostBridge: Resource conflict happens!\n")); - RootBridgeIndex = 0; - Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; - while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { - DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); - for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { - ASSERT (Descriptor->ResType < - ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) - ); - DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", - mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], - Descriptor->AddrLen, Descriptor->AddrRangeMax - )); - if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { - DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", - Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, - ((Descriptor->SpecificFlag & - EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE - ) != 0) ? L" (Prefetchable)" : L"" - )); - } - } - // - // Skip the END descriptor for root bridge - // - ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); - Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( - (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 - ); - } -} diff --git a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf deleted file mode 100644 index d8d2940344d81516aeaa0bad701cfbd5316a0964..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ /dev/null @@ -1,31 +0,0 @@ -## @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2018, Linaro Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = PciHostBridgeLib - FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER - -[Sources] - PciHostBridgeLib.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - BaseLib - DebugLib - DevicePathLib - MemoryAllocationLib - UefiBootServicesTableLib diff --git a/Platform/Hisilicon/HiKey/HiKey.dec b/Platform/Hisilicon/HiKey/HiKey.dec deleted file mode 100644 index 3164c4c223a19d75c7ac1877b8c88c7ee1a9ca7f..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKey.dec +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - DEC_SPECIFICATION = 0x0001001a - PACKAGE_NAME = HiKey - PACKAGE_GUID = d6db414d-ea67-4312-94d5-9c9e5b224d25 - PACKAGE_VERSION = 0.1 - -################################################################################ -# -# Include Section - list of Include Paths that are provided by this package. -# Comments are used for Keywords and Module Types. -# -# Supported Module Types: -# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION -# -################################################################################ -[Includes.common] - Include # Root include for the package - -[Guids.common] - gHiKeyTokenSpaceGuid = { 0x91148425, 0xcdd2, 0x4830, { 0x8b, 0xd0, 0xc6, 0x1c, 0x6d, 0xea, 0x36, 0x21 } } - -[PcdsFixedAtBuild.common] - gHiKeyTokenSpaceGuid.PcdAndroidBootDevicePath|L""|VOID*|0x00000001 - gHiKeyTokenSpaceGuid.PcdAndroidBootFile|{ 0x36, 0x8b, 0x73, 0x3a, 0xc5, 0xb9, 0x63, 0x47, 0xab, 0xbd, 0x6c, 0xbd, 0x4b, 0x25, 0xf9, 0xff }|VOID*|0x00000002 - gHiKeyTokenSpaceGuid.PcdAndroidFastbootFile|{ 0x2a, 0x50, 0x88, 0x95, 0x70, 0x53, 0xe3, 0x11, 0x86, 0x31, 0xd7, 0xc5, 0x95, 0x13, 0x64, 0xc8 }|VOID*|0x00000003 - gHiKeyTokenSpaceGuid.PcdSdBootDevicePath|L""|VOID*|0x00000004 diff --git a/Platform/Hisilicon/HiKey/HiKey.dsc b/Platform/Hisilicon/HiKey/HiKey.dsc deleted file mode 100644 index 52bac596d60f47a67b7e37627589cf9986ffb48e..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKey.dsc +++ /dev/null @@ -1,304 +0,0 @@ -# -# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - PLATFORM_NAME = HiKey - PLATFORM_GUID = 8edf1480-da5c-4857-bc02-7530bd8e7b7a - PLATFORM_VERSION = 0.2 - DSC_SPECIFICATION = 0x00010019 - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 - BUILD_TARGETS = NOOPT|DEBUG|RELEASE - SKUID_IDENTIFIER = DEFAULT - FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf - - DEFINE CONFIG_NO_DEBUGLIB = TRUE - - # - # Network definition - # - DEFINE NETWORK_SNP_ENABLE = FALSE - DEFINE NETWORK_IP6_ENABLE = FALSE - DEFINE NETWORK_TLS_ENABLE = FALSE - DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE - DEFINE NETWORK_ISCSI_ENABLE = FALSE - DEFINE NETWORK_VLAN_ENABLE = FALSE -!include Silicon/Hisilicon/Hisilicon.dsc.inc -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses.common] - ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf - - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - - PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf - - # UiApp dependencies - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf - RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf - - # USB Requirements - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - - # VariableRuntimeDxe Requirements - SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf - AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf - TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf - VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf - -[LibraryClasses.common.SEC] - PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf - ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf - HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf - MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf - MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf - PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf - -[BuildOptions] - GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Hisilicon/Hi6220/Include -I$(WORKSPACE)/Platform/Hisilicon/HiKey/Include - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - # If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. - # It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE - -[PcdsFixedAtBuild.common] - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 - - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha" - - # System Memory (1GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x3E000000 - - # HiKey Dual-Cluster profile - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 - gArmPlatformTokenSpaceGuid.PcdClusterCount|2 - - # - # ARM PrimeCell - # - - ## PL011 - Serial Terminal - DEFINE SERIAL_BASE = 0xF7113000 # UART3 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE) - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 - gArmPlatformTokenSpaceGuid.PL011UartInteger|10 - gArmPlatformTokenSpaceGuid.PL011UartFractional|26 - - ## PL031 RealTimeClock - gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000 - - # - # ARM General Interrupt Controller - # - gArmTokenSpaceGuid.PcdGicDistributorBase|0xF6801000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF6802000 - - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 - - # GUID of the UI app - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } - - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE - - gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 - - # - # DW MMC/SD card controller - # - gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xF723D000 - gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000 - gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE - - # - # - # Fastboot - # - gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1 - gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d - - # - # Android Loader - # - gHiKeyTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00D023F70000000000)/eMMC(0x0)/Ctrl(0x0)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)/\\EFI\\BOOT\\GRUBAA64.EFI" - gHiKeyTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)" - - # - # Make VariableRuntimeDxe work at emulated non-volatile variable mode. - # - gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE - -################################################################################ -# -# Components Section - list of all EDK II Modules needed by this Platform -# -################################################################################ -[Components.common] - # - # PEI Phase modules - # - ArmPlatformPkg/PeilessSec/PeilessSec.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - } - - MdeModulePkg/Core/Pei/PeiMain.inf - MdeModulePkg/Universal/PCD/Pei/Pcd.inf - - # - # DXE - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf - } - - # - # Architectural Protocols - # - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - ArmPkg/Drivers/ArmGicDxe/ArmGicV2Dxe.inf - ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - # - # GPIO - # - Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf - ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf - - # - # Virtual Keyboard - # - EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf - - Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf - - # - # MMC/SD - # - EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf - Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf - - # - # USB Host Support - # - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - - # - # USB Mass Storage Support - # - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - # - # USB Peripheral Support - # - EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf - - # - # Fastboot - # - EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf - - - # - # UEFI Network Stack - # -!include NetworkPkg/Network.dsc.inc - # - # AX88772 Ethernet Driver - # - Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - - # - # Bds - # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - ShellPkg/Application/Shell/Shell.inf { - - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf - OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 - } -!ifdef $(INCLUDE_TFTP_COMMAND) - ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) diff --git a/Platform/Hisilicon/HiKey/HiKey.fdf b/Platform/Hisilicon/HiKey/HiKey.fdf deleted file mode 100644 index 03d74380218481e7420a4dd9b7936877f0975fc3..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKey.fdf +++ /dev/null @@ -1,218 +0,0 @@ -# -# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ - -[FD.BL33_AP_UEFI] -BaseAddress = 0x35000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. -Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device -ErasePolarity = 1 - -# This one is tricky, it must be: BlockSize * NumBlocks = Size -BlockSize = 0x00001000 -NumBlocks = 0xF0 - -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# -################################################################################ - -0x00000000|0x000F0000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV = FVMAIN_COMPACT - - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ - -[FV.FvMain] -BlockSize = 0x40 -NumBlocks = 0 # This FV gets compressed so make it just big enough -FvAlignment = 8 # FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - } - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - # - # Multiple Console IO support - # - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - INF ArmPkg/Drivers/ArmGicDxe/ArmGicV2Dxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - # - # GPIO - # - INF Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf - INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf - - # - # Virtual Keyboard - # - INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf - - INF Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf - - # - # Multimedia Card Interface - # - INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf - INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf - - # - # USB Host Support - # - INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - - # - # USB Mass Storage Support - # - INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - # - # USB Peripheral Support - # - INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf - - # - # Fastboot - # - INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf - - # - # UEFI Network Stack - # -!include NetworkPkg/Network.fdf.inc - - # - # AX88772 Ethernet Driver for Apple Ethernet Adapter - # - INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # UEFI applications - # - INF ShellPkg/Application/Shell/Shell.inf -!ifdef $(INCLUDE_TFTP_COMMAND) - INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) - - # - # Bds - # - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - INF MdeModulePkg/Application/UiApp/UiApp.inf - -[FV.FVMAIN_COMPACT] -FvAlignment = 8 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF ArmPlatformPkg/PeilessSec/PeilessSec.inf - - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } - } - -!include Silicon/Hisilicon/Hisilicon.fdf.inc diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c deleted file mode 100644 index 47fbe02e53fee4abf15b5dc5c55c701234adcfe6..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c +++ /dev/null @@ -1,365 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "HiKeyDxe.h" - -STATIC -VOID -UartInit ( - IN VOID - ) -{ - UINT32 Val; - - /* make UART1 out of reset */ - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1); - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1); - /* make UART2 out of reset */ - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2); - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2); - /* make UART3 out of reset */ - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3); - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3); - /* make UART4 out of reset */ - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4); - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4); - - /* make DW_MMC2 out of reset */ - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2); - - /* enable clock for BT/WIFI */ - Val = MmioRead32 (PMUSSI_ONOFF8_REG) | PMUSSI_ONOFF8_EN_32KB; - MmioWrite32 (PMUSSI_ONOFF8_REG, Val); -} - -STATIC EMBEDDED_GPIO *mGpio; - -STATIC -VOID -MtcmosInit ( - IN VOID - ) -{ - UINT32 Data; - - /* enable MTCMOS for GPU */ - MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D); - do { - Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0); - } while ((Data & PW_EN0_G3D) == 0); -} - -EFI_STATUS -HiKeyInitPeripherals ( - IN VOID - ) -{ - UINT32 Data, Bits; - - /* make I2C0/I2C1/I2C2/SPI0 out of reset */ - Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | \ - PERIPH_RST3_SSP; - MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, Bits); - - do { - Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT3); - } while (Data & Bits); - - UartInit (); - /* MTCMOS -- Multi-threshold CMOS */ - MtcmosInit (); - - /* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */ - MmioWrite32 (IOCG_084_REG, 0); /* configure GPIO24 as nopull */ - MmioWrite32 (IOMG_080_REG, 0); /* configure GPIO24 as GPIO */ - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -CreatePlatformBootOptionFromPath ( - IN CHAR16 *PathStr, - IN CHAR16 *Description, - IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *BootOption - ) -{ - EFI_STATUS Status; - EFI_DEVICE_PATH *DevicePath; - - DevicePath = (EFI_DEVICE_PATH *)ConvertTextToDevicePath (PathStr); - ASSERT (DevicePath != NULL); - Status = EfiBootManagerInitializeLoadOption ( - BootOption, - LoadOptionNumberUnassigned, - LoadOptionTypeBoot, - LOAD_OPTION_ACTIVE, - Description, - DevicePath, - NULL, - 0 - ); - FreePool (DevicePath); - return Status; -} - -STATIC -EFI_STATUS -CreatePlatformBootOptionFromGuid ( - IN EFI_GUID *FileGuid, - IN CHAR16 *Description, - IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *BootOption - ) -{ - EFI_STATUS Status; - EFI_DEVICE_PATH *DevicePath; - EFI_DEVICE_PATH *TempDevicePath; - EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; - MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; - - Status = gBS->HandleProtocol ( - gImageHandle, - &gEfiLoadedImageProtocolGuid, - (VOID **) &LoadedImage - ); - ASSERT_EFI_ERROR (Status); - EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); - TempDevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle); - ASSERT (TempDevicePath != NULL); - DevicePath = AppendDevicePathNode ( - TempDevicePath, - (EFI_DEVICE_PATH_PROTOCOL *) &FileNode - ); - ASSERT (DevicePath != NULL); - Status = EfiBootManagerInitializeLoadOption ( - BootOption, - LoadOptionNumberUnassigned, - LoadOptionTypeBoot, - LOAD_OPTION_ACTIVE, - Description, - DevicePath, - NULL, - 0 - ); - FreePool (DevicePath); - return Status; -} - -STATIC -EFI_STATUS -GetPlatformBootOptionsAndKeys ( - OUT UINTN *BootCount, - OUT EFI_BOOT_MANAGER_LOAD_OPTION **BootOptions, - OUT EFI_INPUT_KEY **BootKeys - ) -{ - EFI_GUID *FileGuid; - CHAR16 *PathStr; - EFI_STATUS Status; - UINTN Size; - - Size = sizeof (EFI_BOOT_MANAGER_LOAD_OPTION) * HIKEY_BOOT_OPTION_NUM; - *BootOptions = (EFI_BOOT_MANAGER_LOAD_OPTION *)AllocateZeroPool (Size); - if (*BootOptions == NULL) { - DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootOptions\n")); - return EFI_OUT_OF_RESOURCES; - } - Size = sizeof (EFI_INPUT_KEY) * HIKEY_BOOT_OPTION_NUM; - *BootKeys = (EFI_INPUT_KEY *)AllocateZeroPool (Size); - if (*BootKeys == NULL) { - DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootKeys\n")); - Status = EFI_OUT_OF_RESOURCES; - goto Error; - } - - PathStr = (CHAR16 *)PcdGetPtr (PcdSdBootDevicePath); - ASSERT (PathStr != NULL); - Status = CreatePlatformBootOptionFromPath ( - PathStr, - L"Boot from SD", - &(*BootOptions)[0] - ); - ASSERT_EFI_ERROR (Status); - - PathStr = (CHAR16 *)PcdGetPtr (PcdAndroidBootDevicePath); - ASSERT (PathStr != NULL); - Status = CreatePlatformBootOptionFromPath ( - PathStr, - L"Grub", - &(*BootOptions)[1] - ); - ASSERT_EFI_ERROR (Status); - - FileGuid = PcdGetPtr (PcdAndroidBootFile); - ASSERT (FileGuid != NULL); - Status = CreatePlatformBootOptionFromGuid ( - FileGuid, - L"Android Boot", - &(*BootOptions)[2] - ); - ASSERT_EFI_ERROR (Status); - - FileGuid = PcdGetPtr (PcdAndroidFastbootFile); - ASSERT (FileGuid != NULL); - Status = CreatePlatformBootOptionFromGuid ( - FileGuid, - L"Android Fastboot", - &(*BootOptions)[3] - ); - ASSERT_EFI_ERROR (Status); - (*BootKeys)[3].ScanCode = SCAN_NULL; - (*BootKeys)[3].UnicodeChar = 'f'; - - *BootCount = 4; - - return EFI_SUCCESS; -Error: - FreePool (*BootOptions); - return Status; -} - -PLATFORM_BOOT_MANAGER_PROTOCOL mPlatformBootManager = { - GetPlatformBootOptionsAndKeys -}; - -EFI_STATUS -EFIAPI -VirtualKeyboardRegister ( - IN VOID - ) -{ - EFI_STATUS Status; - - Status = gBS->LocateProtocol ( - &gEmbeddedGpioProtocolGuid, - NULL, - (VOID **) &mGpio - ); - if (EFI_ERROR (Status)) { - return Status; - } - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -VirtualKeyboardReset ( - IN VOID - ) -{ - EFI_STATUS Status; - - if (mGpio == NULL) { - return EFI_INVALID_PARAMETER; - } - Status = mGpio->Set (mGpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT); - return Status; -} - -BOOLEAN -EFIAPI -VirtualKeyboardQuery ( - IN VIRTUAL_KBD_KEY *VirtualKey - ) -{ - EFI_STATUS Status; - UINTN Value = 0; - - if ((VirtualKey == NULL) || (mGpio == NULL)) { - return FALSE; - } - if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { - goto Done; - } else { - Status = mGpio->Get (mGpio, DETECT_J15_FASTBOOT, &Value); - if (EFI_ERROR (Status) || (Value != 0)) { - return FALSE; - } - } -Done: - VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE; - VirtualKey->Key.ScanCode = SCAN_NULL; - VirtualKey->Key.UnicodeChar = L'f'; - return TRUE; -} - -EFI_STATUS -EFIAPI -VirtualKeyboardClear ( - IN VIRTUAL_KBD_KEY *VirtualKey - ) -{ - if (VirtualKey == NULL) { - return EFI_INVALID_PARAMETER; - } - if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { - MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE); - WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4); - } - return EFI_SUCCESS; -} - -PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = { - VirtualKeyboardRegister, - VirtualKeyboardReset, - VirtualKeyboardQuery, - VirtualKeyboardClear -}; - -EFI_STATUS -EFIAPI -HiKeyEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - Status = HiKeyInitPeripherals (); - if (EFI_ERROR (Status)) { - return Status; - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gPlatformVirtualKeyboardProtocolGuid, - EFI_NATIVE_INTERFACE, - &mVirtualKeyboard - ); - if (EFI_ERROR (Status)) { - return Status; - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gPlatformBootManagerProtocolGuid, - EFI_NATIVE_INTERFACE, - &mPlatformBootManager - ); - return Status; -} diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h deleted file mode 100644 index 954f31e461dca3803f2ea8ec91f8162f5e44415f..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h +++ /dev/null @@ -1,20 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __HIKEYDXE_H__ -#define __HIKEYDXE_H__ - -#define DETECT_J15_FASTBOOT 24 // GPIO3_0 - -#define ADB_REBOOT_ADDRESS 0x05F01000 -#define ADB_REBOOT_BOOTLOADER 0x77665500 -#define ADB_REBOOT_NONE 0x77665501 - -#define HIKEY_BOOT_OPTION_NUM 4 - -#endif /* __HIKEYDXE_H__ */ diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf deleted file mode 100644 index 0181999a3bd03a9cc05f3eabfd48cbc6977532bf..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf +++ /dev/null @@ -1,50 +0,0 @@ -# -# Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2018, Linaro Ltd. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - INF_VERSION = 0x0001001a - BASE_NAME = HiKeyDxe - FILE_GUID = f567684b-1089-4214-8881-d64b20cbda2f - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = HiKeyEntryPoint - -[Sources.common] - HiKeyDxe.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Platform/Hisilicon/HiKey/HiKey.dec - -[LibraryClasses] - CacheMaintenanceLib - DebugLib - IoLib - UefiBootManagerLib - UefiLib - UefiDriverEntryPoint - -[Protocols] - gEfiDevicePathFromTextProtocolGuid - gEfiLoadedImageProtocolGuid - gEmbeddedGpioProtocolGuid - gPlatformBootManagerProtocolGuid - gPlatformVirtualKeyboardProtocolGuid - -[Pcd] - gHiKeyTokenSpaceGuid.PcdAndroidBootDevicePath - gHiKeyTokenSpaceGuid.PcdAndroidBootFile - gHiKeyTokenSpaceGuid.PcdAndroidFastbootFile - gHiKeyTokenSpaceGuid.PcdSdBootDevicePath - -[Guids] - gEfiEndOfDxeEventGroupGuid - -[Depex] - TRUE diff --git a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c deleted file mode 100644 index efdd76768b2e0abd31175d0bdac1e2a3582ebd1c..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c +++ /dev/null @@ -1,68 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include - -#include - -GPIO_CONTROLLER gGpioDevice[] = { - // - // { base address, gpio index, gpio count } - // - { 0xf8011000, 0, 8 }, // GPIO0 - { 0xf8012000, 8, 8 }, // GPIO1 - { 0xf8013000, 16, 8 }, // GPIO2 - { 0xf8014000, 24, 8 }, // GPIO3 - { 0xf7020000, 32, 8 }, // GPIO4 - { 0xf7021000, 40, 8 }, // GPIO5 - { 0xf7022000, 48, 8 }, // GPIO6 - { 0xf7023000, 56, 8 }, // GPIO7 - { 0xf7024000, 64, 8 }, // GPIO8 - { 0xf7025000, 72, 8 }, // GPIO9 - { 0xf7026000, 80, 8 }, // GPIO10 - { 0xf7027000, 88, 8 }, // GPIO11 - { 0xf7028000, 96, 8 }, // GPIO12 - { 0xf7029000, 104, 8 }, // GPIO13 - { 0xf702a000, 112, 8 }, // GPIO14 - { 0xf702b000, 120, 8 }, // GPIO15 - { 0xf702c000, 128, 8 }, // GPIO16 - { 0xf702d000, 136, 8 }, // GPIO17 - { 0xf702e000, 144, 8 }, // GPIO18 - { 0xf702f000, 152, 8 } // GPIO19 -}; - -PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { - // - // { global gpio count, gpio controller counter, GPIO_CONTROLLER } - // - 160, 20, gGpioDevice -}; - -EFI_STATUS -EFIAPI -HiKeyGpioEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_HANDLE Handle; - - // Install the Embedded Platform GPIO Protocol onto a new handle - Handle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces( - &Handle, - &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, - NULL - ); - if (EFI_ERROR(Status)) { - Status = EFI_OUT_OF_RESOURCES; - } - - return Status; -} diff --git a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf deleted file mode 100644 index 3564b076331ce34d237c03ec5976f729b251d2ba..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (c) 2018, Linaro. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - INF_VERSION = 0x0001001a - BASE_NAME = HiKeyGpio - FILE_GUID = b51a851c-7bf7-463f-b261-cfb158b7f699 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = HiKeyGpioEntryPoint - -[Sources.common] - HiKeyGpioDxe.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - DebugLib - UefiDriverEntryPoint - -[Protocols] - gPlatformGpioProtocolGuid - -[Depex] - TRUE diff --git a/Platform/Hisilicon/HiKey/Include/ArmPlatform.h b/Platform/Hisilicon/HiKey/Include/ArmPlatform.h deleted file mode 100644 index 6962da30a3ce44ceca2944145a370bd2587d84c5..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/Include/ArmPlatform.h +++ /dev/null @@ -1,20 +0,0 @@ -/** @file -* -* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __PLATFORM_H__ -#define __PLATFORM_H__ - -// -// We don't care about this value, but the PL031 driver depends on the macro -// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet() -// function, which just returns EFI_UNSUPPORTED. -// -// -#define SYS_CFG_RTC 0 - -#endif /* __PLATFORM_H__ */ diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c deleted file mode 100644 index 057d566bde67237e2df8b2d795ab246e60f24db7..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c +++ /dev/null @@ -1,138 +0,0 @@ -/** @file -* -* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include - -#include - -#include - -ARM_CORE_INFO mHiKeyInfoTable[] = { - { - // Cluster 0, Core 0 - 0x0, 0x0, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 0, Core 1 - 0x0, 0x1, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 0, Core 2 - 0x0, 0x2, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 0, Core 3 - 0x0, 0x3, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 0 - 0x1, 0x0, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 1 - 0x1, 0x1, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 2 - 0x1, 0x2, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 3 - 0x1, 0x3, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - } -}; - -/** - Return the current Boot Mode - - This function returns the boot reason on the platform - - @return Return the current Boot Mode of the platform - -**/ -EFI_BOOT_MODE -ArmPlatformGetBootMode ( - VOID - ) -{ - return BOOT_WITH_FULL_CONFIGURATION; -} - -/** - Initialize controllers that must setup in the normal world - - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim - in the PEI phase. - -**/ -RETURN_STATUS -ArmPlatformInitialize ( - IN UINTN MpId - ) -{ - return RETURN_SUCCESS; -} - -EFI_STATUS -PrePeiCoreGetMpCoreInfo ( - OUT UINTN *CoreCount, - OUT ARM_CORE_INFO **ArmCoreTable - ) -{ - // Only support one cluster - *CoreCount = sizeof(mHiKeyInfoTable) / sizeof(ARM_CORE_INFO); - *ArmCoreTable = mHiKeyInfoTable; - return EFI_SUCCESS; -} - -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; - -EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi - } -}; - -VOID -ArmPlatformGetPlatformPpiList ( - OUT UINTN *PpiListSize, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiList - ) -{ - *PpiListSize = sizeof(gPlatformPpiTable); - *PpiList = gPlatformPpiTable; -} diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S deleted file mode 100644 index ebc385443f7235aea258702d52c96395a7915eb0..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -#include -#include - -ASM_FUNC(ArmPlatformPeiBootAction) - ret diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf deleted file mode 100644 index 2a6ae8a4bb9fb2370b8bda772fa19415d48ada3b..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = HiKeyLib - FILE_GUID = 1f6c5192-f35c-462d-877c-8ee3227fff01 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformLib - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Platform/Hisilicon/HiKey/HiKey.dec - Silicon/Hisilicon/Hi6220/Hi6220.dec - -[LibraryClasses] - ArmLib - HobLib - IoLib - MemoryAllocationLib - SerialPortLib - -[Sources.common] - HiKey.c - HiKeyMem.c - -[Sources.AARCH64] - HiKeyHelper.S - -[Ppis] - gArmMpCoreInfoPpiGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmPrimaryCore - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c deleted file mode 100644 index 118c66942e3172dd350ac889549ccd133e333f07..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c +++ /dev/null @@ -1,194 +0,0 @@ -/** @file -* -* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include - -#include - -// The total number of descriptors, including the final "end-of-table" descriptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 - -// DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED - -#define HIKEY_EXTRA_SYSTEM_MEMORY_BASE 0x40000000 -#define HIKEY_EXTRA_SYSTEM_MEMORY_SIZE 0x40000000 - -STATIC struct HiKeyReservedMemory { - EFI_PHYSICAL_ADDRESS Offset; - EFI_PHYSICAL_ADDRESS Size; -} HiKeyReservedMemoryBuffer [] = { - { 0x05E00000, 0x00100000 }, // MCU - { 0x05F01000, 0x00001000 }, // ADB REBOOT "REASON" - { 0x06DFF000, 0x00001000 }, // MAILBOX - { 0x0740F000, 0x00001000 }, // MAILBOX - { 0x21F00000, 0x00100000 }, // PSTORE/RAMOOPS - { 0x3E000000, 0x02000000 } // TEE OS -}; - -STATIC -UINT64 -EFIAPI -HiKeyInitMemorySize ( - IN VOID - ) -{ - UINT32 Data; - UINT64 MemorySize; - - Data = MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP); - MemorySize = HIKEY_REGION_SIZE(Data); - return MemorySize; -} - -/** - Return the Virtual Memory Map of your platform - - This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. - - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- - Virtual Memory mapping. This array must be ended by a zero-filled - entry - -**/ -VOID -ArmPlatformGetVirtualMemoryMap ( - IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap - ) -{ - ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; - UINTN Index = 0, Count, ReservedTop; - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - EFI_PEI_HOB_POINTERS NextHob; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; - UINT64 ResourceLength; - EFI_PHYSICAL_ADDRESS ResourceTop; - UINT64 MemorySize, AdditionalMemorySize; - - MemorySize = HiKeyInitMemorySize (); - if (MemorySize == 0) { - MemorySize = PcdGet64 (PcdSystemMemorySize); - } - - ResourceAttributes = ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED - ); - - // Create initial Base Hob for system memory. - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - ResourceAttributes, - PcdGet64 (PcdSystemMemoryBase), - PcdGet64 (PcdSystemMemorySize) - ); - - NextHob.Raw = GetHobList (); - Count = sizeof (HiKeyReservedMemoryBuffer) / sizeof (struct HiKeyReservedMemory); - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) { - if (Index >= Count) { - break; - } - if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && - (HiKeyReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) && - ((HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size) <= - NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) { - ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; - ResourceLength = NextHob.ResourceDescriptor->ResourceLength; - ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; - ReservedTop = HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size; - - // Create the System Memory HOB for the reserved buffer - BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT, - HiKeyReservedMemoryBuffer[Index].Offset, - HiKeyReservedMemoryBuffer[Index].Size); - // Update the HOB - NextHob.ResourceDescriptor->ResourceLength = HiKeyReservedMemoryBuffer[Index].Offset - NextHob.ResourceDescriptor->PhysicalStart; - - // If there is some memory available on the top of the reserved memory then create a HOB - if (ReservedTop < ResourceTop) { - BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, - ResourceAttributes, - ReservedTop, - ResourceTop - ReservedTop); - } - Index++; - } - NextHob.Raw = GET_NEXT_HOB (NextHob); - } - - AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize); - if (AdditionalMemorySize >= SIZE_1GB) { - // Declared the additional memory - ResourceAttributes = - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED; - - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - ResourceAttributes, - HIKEY_EXTRA_SYSTEM_MEMORY_BASE, - HIKEY_EXTRA_SYSTEM_MEMORY_SIZE); - } - - ASSERT (VirtualMemoryMap != NULL); - - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); - if (VirtualMemoryTable == NULL) { - return; - } - - CacheAttributes = DDR_ATTRIBUTES_CACHED; - - Index = 0; - - // Hi6220 SOC peripherals - VirtualMemoryTable[Index].PhysicalBase = HI6220_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase = HI6220_PERIPH_BASE; - VirtualMemoryTable[Index].Length = HI6220_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - - // DDR - predefined 1GB size - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); - VirtualMemoryTable[Index].Attributes = CacheAttributes; - - // If DDR capacity is 2GB size, append a new entry to fill the gap. - if (AdditionalMemorySize >= SIZE_1GB) { - VirtualMemoryTable[++Index].PhysicalBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE; - VirtualMemoryTable[Index].VirtualBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE; - VirtualMemoryTable[Index].Length = HIKEY_EXTRA_SYSTEM_MEMORY_SIZE; - VirtualMemoryTable[Index].Attributes = CacheAttributes; - } - - // End of Table - VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; - - ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - - *VirtualMemoryMap = VirtualMemoryTable; -} diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dec b/Platform/Hisilicon/HiKey960/HiKey960.dec deleted file mode 100644 index 1273c28ed07bb24f87f1b3bd9dfb61d98998306e..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960.dec +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - DEC_SPECIFICATION = 0x0001001a - PACKAGE_NAME = HiKey960 - PACKAGE_GUID = 1892b5b5-d18d-47a3-8fab-e3ae6b4226b0 - PACKAGE_VERSION = 0.1 - -################################################################################ -# -# Include Section - list of Include Paths that are provided by this package. -# Comments are used for Keywords and Module Types. -# -# Supported Module Types: -# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION -# -################################################################################ -[Guids.common] - gHiKey960TokenSpaceGuid = { 0x99a14446, 0xaad7, 0xe460, {0xb4, 0xe5, 0x1f, 0x79, 0xaa, 0xa4, 0x93, 0xfd } } - -[PcdsFixedAtBuild.common] - gHiKey960TokenSpaceGuid.PcdAndroidBootDevicePath|L""|VOID*|0x00000001 - gHiKey960TokenSpaceGuid.PcdAndroidBootFile|{ 0x36, 0x8b, 0x73, 0x3a, 0xc5, 0xb9, 0x63, 0x47, 0xab, 0xbd, 0x6c, 0xbd, 0x4b, 0x25, 0xf9, 0xff }|VOID*|0x00000002 - gHiKey960TokenSpaceGuid.PcdAndroidFastbootFile|{ 0x2a, 0x50, 0x88, 0x95, 0x70, 0x53, 0xe3, 0x11, 0x86, 0x31, 0xd7, 0xc5, 0x95, 0x13, 0x64, 0xc8 }|VOID*|0x00000003 - gHiKey960TokenSpaceGuid.PcdSdBootDevicePath|L""|VOID*|0x00000004 diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc deleted file mode 100644 index ca332eb880c30c8f83c21d29cb1cf6bdc0fe6305..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ /dev/null @@ -1,282 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - PLATFORM_NAME = HiKey960 - PLATFORM_GUID = bd1a557e-4423-466a-a462-38439588fd37 - PLATFORM_VERSION = 0.2 - DSC_SPECIFICATION = 0x00010019 - OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES = AARCH64 - BUILD_TARGETS = NOOPT|DEBUG|RELEASE - SKUID_IDENTIFIER = DEFAULT - FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf - - DEFINE CONFIG_NO_DEBUGLIB = TRUE - - # - # Network definition - # - DEFINE NETWORK_SNP_ENABLE = FALSE - DEFINE NETWORK_IP6_ENABLE = FALSE - DEFINE NETWORK_TLS_ENABLE = FALSE - DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE - DEFINE NETWORK_ISCSI_ENABLE = FALSE - DEFINE NETWORK_VLAN_ENABLE = FALSE -!include Silicon/Hisilicon/Hisilicon.dsc.inc -!include MdePkg/MdeLibs.dsc.inc - -[LibraryClasses.common] - ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf - - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf - - # UiApp dependencies - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf - - SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf - RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf - - # USB Requirements - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - - # Network Libraries - UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf - # VariableRuntimeDxe Requirements - SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf - AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf - TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf - VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf - -[LibraryClasses.common.SEC] - PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf - ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf - HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf - MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf - MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf - PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. - # It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE - -[PcdsFixedAtBuild.common] - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 - - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha" - - # System Memory (3GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0xC0000000 - - # HiKey960 Dual-Cluster profile - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 - gArmPlatformTokenSpaceGuid.PcdClusterCount|2 - - # - # ARM PrimeCell - # - - ## PL011 - Serial Terminal - DEFINE SERIAL_BASE = 0xFFF32000 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE) - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 - gArmPlatformTokenSpaceGuid.PL011UartInteger|10 - gArmPlatformTokenSpaceGuid.PL011UartFractional|26 - - ## PL031 RealTimeClock - gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xFFF05000 - - # - # ARM General Interrupt Controller - # - gArmTokenSpaceGuid.PcdGicDistributorBase|0xE82B1000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE82B2000 - - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 - - # GUID of the UI app - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } - - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE - - gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 - - # - # - # Fastboot - # - gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1 - gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d - - # - # Android Loader - # - gHiKey960TokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00003BFF0000000000)/UFS(0x0,0x3)/HD(7,GPT,D3340696-9B95-4C64-8DF6-E6D4548FBA41,0x12100,0x4000)/\\EFI\\BOOT\\GRUBAA64.EFI" - gHiKey960TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00F037FF0000000000)/SD(0x0)" - - # - # Make VariableRuntimeDxe work at emulated non-volatile variable mode. - # - gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE - -################################################################################ -# -# Components Section - list of all EDK II Modules needed by this Platform -# -################################################################################ -[Components.common] - # - # PEI Phase modules - # - ArmPlatformPkg/PeilessSec/PeilessSec.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - } - - # - # DXE - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf - } - - # - # Architectural Protocols - # - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - ArmPkg/Drivers/ArmGicDxe/ArmGicV2Dxe.inf - ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - # - # GPIO - # - Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf - ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf - - # - # Virtual Keyboard - # - EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf - - Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf - - # - # USB Host Support - # - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - - # - # USB Mass Storage Support - # - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - # - # USB Peripheral Support - # - EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf - - # - # Fastboot - # - EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf - - - # - # UEFI Network Stack - # -!include NetworkPkg/Network.dsc.inc - # - # FAT filesystem + GPT/MBR partitioning - # - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - - # - # Bds - # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - MdeModulePkg/Application/UiApp/UiApp.inf { - - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - ShellPkg/Application/Shell/Shell.inf { - - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf - OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 - } -!ifdef $(INCLUDE_TFTP_COMMAND) - ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf deleted file mode 100644 index 6900160848a50d0f1eca7dfa93997be897f94366..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ /dev/null @@ -1,206 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ - -[FD.BL33_AP_UEFI] -BaseAddress = 0x1AC98000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. -Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device -ErasePolarity = 1 - -# This one is tricky, it must be: BlockSize * NumBlocks = Size -BlockSize = 0x00001000 -NumBlocks = 0xF0 - -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# -################################################################################ - -0x00000000|0x000F0000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV = FVMAIN_COMPACT - - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ - -[FV.FvMain] -BlockSize = 0x40 -NumBlocks = 0 # This FV gets compressed so make it just big enough -FvAlignment = 8 # FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - } - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - # - # Multiple Console IO support - # - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - - INF ArmPkg/Drivers/ArmGicDxe/ArmGicV2Dxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - - # - # GPIO - # - INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf - INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf - - # - # Virtual Keyboard - # - INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf - - INF Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf - - # - # USB Host Support - # - INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - - # - # USB Mass Storage Support - # - INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - # - # USB Peripheral Support - # - INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf - - # - # Fastboot - # - INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf - - # - # UEFI Network Stack - # -!include NetworkPkg/Network.fdf.inc - # - # FAT filesystem + GPT/MBR partitioning - # - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # UEFI applications - # - INF ShellPkg/Application/Shell/Shell.inf -!ifdef $(INCLUDE_TFTP_COMMAND) - INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) - - # - # Bds - # - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - INF MdeModulePkg/Application/UiApp/UiApp.inf - -[FV.FVMAIN_COMPACT] -FvAlignment = 8 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF ArmPlatformPkg/PeilessSec/PeilessSec.inf - - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } - } - -!include Silicon/Hisilicon/Hisilicon.fdf.inc diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c deleted file mode 100644 index 8e94bec41c4d7e655e8f5a54d3de1ef3a5dec8f2..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c +++ /dev/null @@ -1,461 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "HiKey960Dxe.h" - -STATIC EMBEDDED_GPIO *mGpio; - -STATIC -VOID -InitSdCard ( - IN VOID - ) -{ - UINT32 Data; - - // - // LDO16 - // 000: 1.75V, 001: 1.8V, 010: 2.4V, 011: 2.6V, 100: 2.7V, - // 101: 2.85V, 110: 2.95V, 111: 3.0V. - // - Data = MmioRead32 (PMIC_LDO16_VSET_REG) & LDO16_VSET_MASK; - Data |= 6; - MmioWrite32 (PMIC_LDO16_VSET_REG, Data); - MmioOr32 (PMIC_LDO16_ONOFF_ECO_REG, LDO16_ONOFF_ECO_LDO16_ENABLE); - // - // wait regulator stable - // - MicroSecondDelay (100); - - // - // LDO9 - // 000: 1.75V, 001: 1.8V, 010: 1.825V, 011: 2.8V, 100: 2.85V, - // 101: 2.95V, 110: 3.0V, 111: 3.3V. - // - Data = MmioRead32 (PMIC_LDO9_VSET_REG) & LDO9_VSET_MASK; - Data |= 5; - MmioWrite32 (PMIC_LDO9_VSET_REG, Data); - MmioOr32 (PMU_REG_BASE + (0x6a << 2), 2); - // - // wait regulator stable - // - MicroSecondDelay (100); - - // - // GPIO203 - // - MmioWrite32 (IOMG_AO_REG_BASE + (24 << 2), 0); // GPIO function - - // - // SD pinmux - // - MmioWrite32 (IOMG_MMC0_000_REG, IOMG_FUNC1); // SD_CLK - MmioWrite32 (IOMG_MMC0_001_REG, IOMG_FUNC1); // SD_CMD - MmioWrite32 (IOMG_MMC0_002_REG, IOMG_FUNC1); // SD_DATA0 - MmioWrite32 (IOMG_MMC0_003_REG, IOMG_FUNC1); // SD_DATA1 - MmioWrite32 (IOMG_MMC0_004_REG, IOMG_FUNC1); // SD_DATA2 - MmioWrite32 (IOMG_MMC0_005_REG, IOMG_FUNC1); // SD_DATA3 - MmioWrite32 (IOCG_MMC0_000_REG, IOCG_DRIVE (15)); // SD_CLK float with 32mA - MmioWrite32 (IOCG_MMC0_001_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_CMD - MmioWrite32 (IOCG_MMC0_002_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA0 - MmioWrite32 (IOCG_MMC0_003_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA1 - MmioWrite32 (IOCG_MMC0_004_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA2 - MmioWrite32 (IOCG_MMC0_005_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA3 - - // - // SC_SEL_SD: - // 0xx: 3.2MHz, 100: PPLL0, 101: PPLL1, 11x: PPLL2. - // SC_DIV_SD: - // divider = value + 1 - // - do { - MmioOr32 ( - CRG_CLKDIV4, - CLKDIV4_SC_SEL_SD (7) | - (CLKDIV4_SC_SEL_SD_MASK << CLKDIV4_SC_MASK_SHIFT) - ); - Data = MmioRead32 (CRG_CLKDIV4) & CLKDIV4_SC_SEL_SD_MASK; - } while (Data != CLKDIV4_SC_SEL_SD (7)); - - // - // Unreset SD controller - // - MmioWrite32 (CRG_PERRSTDIS4, PERRSTEN4_SD); - do { - Data = MmioRead32 (CRG_PERRSTSTAT4); - } while ((Data & PERRSTEN4_SD) == PERRSTEN4_SD); - // - // Enable SD controller clock - // - MmioOr32 (CRG_PEREN0, PEREN0_GT_HCLK_SD); - MmioOr32 (CRG_PEREN4, PEREN4_GT_CLK_SD); - do { - Data = MmioRead32 (CRG_PERCLKEN4); - } while ((Data & PEREN4_GT_CLK_SD) != PEREN4_GT_CLK_SD); -} - -VOID -InitPeripherals ( - IN VOID - ) -{ - // - // Enable FPLL0 - // - MmioOr32 (SCTRL_SCFPLLCTRL0, SCTRL_SCFPLLCTRL0_FPLL0_EN); - - InitSdCard (); - - // - // Enable wifi clock - // - MmioOr32 (PMIC_HARDWARE_CTRL0, PMIC_HARDWARE_CTRL0_WIFI_CLK); - MmioOr32 (PMIC_OSC32K_ONOFF_CTRL, PMIC_OSC32K_ONOFF_CTRL_EN_32K); -} - -/** - Notification function of the event defined as belonging to the - EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in - the entry point of the driver. - - This function is called when an event belonging to the - EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an - event is signalled once at the end of the dispatching of all - drivers (end of the so called DXE phase). - - @param[in] Event Event declared in the entry point of the driver whose - notification function is being invoked. - @param[in] Context NULL -**/ -STATIC -VOID -OnEndOfDxe ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - UINT32 BootMode; - VOID *RecoveryStr; - VOID *SwitchStr; - - BootMode = MmioRead32 (SCTRL_BAK_DATA0) & BOOT_MODE_MASK; - if (BootMode == BOOT_MODE_RECOVERY) { - RecoveryStr = "WARNING: CAN NOT BOOT KERNEL IN RECOVERY MODE!\r\n"; - SwitchStr = "Switch to normal boot mode, then reboot to boot kernel.\r\n"; - SerialPortWrite (RecoveryStr, AsciiStrLen (RecoveryStr)); - SerialPortWrite (SwitchStr, AsciiStrLen (SwitchStr)); - } -} - -STATIC -EFI_STATUS -CreatePlatformBootOptionFromPath ( - IN CHAR16 *PathStr, - IN CHAR16 *Description, - IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *BootOption - ) -{ - EFI_STATUS Status; - EFI_DEVICE_PATH *DevicePath; - - DevicePath = (EFI_DEVICE_PATH *)ConvertTextToDevicePath (PathStr); - ASSERT (DevicePath != NULL); - Status = EfiBootManagerInitializeLoadOption ( - BootOption, - LoadOptionNumberUnassigned, - LoadOptionTypeBoot, - LOAD_OPTION_ACTIVE, - Description, - DevicePath, - NULL, - 0 - ); - FreePool (DevicePath); - return Status; -} - -STATIC -EFI_STATUS -CreatePlatformBootOptionFromGuid ( - IN EFI_GUID *FileGuid, - IN CHAR16 *Description, - IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *BootOption - ) -{ - EFI_STATUS Status; - EFI_DEVICE_PATH *DevicePath; - EFI_DEVICE_PATH *TempDevicePath; - EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; - MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; - - Status = gBS->HandleProtocol ( - gImageHandle, - &gEfiLoadedImageProtocolGuid, - (VOID **) &LoadedImage - ); - ASSERT_EFI_ERROR (Status); - EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); - TempDevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle); - ASSERT (TempDevicePath != NULL); - DevicePath = AppendDevicePathNode ( - TempDevicePath, - (EFI_DEVICE_PATH_PROTOCOL *) &FileNode - ); - ASSERT (DevicePath != NULL); - Status = EfiBootManagerInitializeLoadOption ( - BootOption, - LoadOptionNumberUnassigned, - LoadOptionTypeBoot, - LOAD_OPTION_ACTIVE, - Description, - DevicePath, - NULL, - 0 - ); - FreePool (DevicePath); - return Status; -} - -STATIC -EFI_STATUS -GetPlatformBootOptionsAndKeys ( - OUT UINTN *BootCount, - OUT EFI_BOOT_MANAGER_LOAD_OPTION **BootOptions, - OUT EFI_INPUT_KEY **BootKeys - ) -{ - EFI_GUID *FileGuid; - CHAR16 *PathStr; - EFI_STATUS Status; - UINTN Size; - - Size = sizeof (EFI_BOOT_MANAGER_LOAD_OPTION) * HIKEY960_BOOT_OPTION_NUM; - *BootOptions = (EFI_BOOT_MANAGER_LOAD_OPTION *)AllocateZeroPool (Size); - if (*BootOptions == NULL) { - DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootOptions\n")); - return EFI_OUT_OF_RESOURCES; - } - Size = sizeof (EFI_INPUT_KEY) * HIKEY960_BOOT_OPTION_NUM; - *BootKeys = (EFI_INPUT_KEY *)AllocateZeroPool (Size); - if (*BootKeys == NULL) { - DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootKeys\n")); - Status = EFI_OUT_OF_RESOURCES; - goto Error; - } - - PathStr = (CHAR16 *)PcdGetPtr (PcdSdBootDevicePath); - ASSERT (PathStr != NULL); - Status = CreatePlatformBootOptionFromPath ( - PathStr, - L"Boot from SD", - &(*BootOptions)[0] - ); - ASSERT_EFI_ERROR (Status); - - PathStr = (CHAR16 *)PcdGetPtr (PcdAndroidBootDevicePath); - ASSERT (PathStr != NULL); - Status = CreatePlatformBootOptionFromPath ( - PathStr, - L"Grub", - &(*BootOptions)[1] - ); - ASSERT_EFI_ERROR (Status); - - FileGuid = PcdGetPtr (PcdAndroidBootFile); - ASSERT (FileGuid != NULL); - Status = CreatePlatformBootOptionFromGuid ( - FileGuid, - L"Android Boot", - &(*BootOptions)[2] - ); - ASSERT_EFI_ERROR (Status); - - FileGuid = PcdGetPtr (PcdAndroidFastbootFile); - ASSERT (FileGuid != NULL); - Status = CreatePlatformBootOptionFromGuid ( - FileGuid, - L"Android Fastboot", - &(*BootOptions)[3] - ); - ASSERT_EFI_ERROR (Status); - (*BootKeys)[3].ScanCode = SCAN_NULL; - (*BootKeys)[3].UnicodeChar = 'f'; - - *BootCount = 4; - - return EFI_SUCCESS; -Error: - FreePool (*BootOptions); - return Status; -} - -PLATFORM_BOOT_MANAGER_PROTOCOL mPlatformBootManager = { - GetPlatformBootOptionsAndKeys -}; - -EFI_STATUS -EFIAPI -VirtualKeyboardRegister ( - IN VOID - ) -{ - EFI_STATUS Status; - - Status = gBS->LocateProtocol ( - &gEmbeddedGpioProtocolGuid, - NULL, - (VOID **) &mGpio - ); - if (EFI_ERROR (Status)) { - return Status; - } - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -VirtualKeyboardReset ( - IN VOID - ) -{ - EFI_STATUS Status; - - if (mGpio == NULL) { - return EFI_INVALID_PARAMETER; - } - // - // Configure GPIO68 as GPIO function - // - MmioWrite32 (0xe896c108, 0); - Status = mGpio->Set (mGpio, DETECT_SW_FASTBOOT, GPIO_MODE_INPUT); - return Status; -} - -BOOLEAN -EFIAPI -VirtualKeyboardQuery ( - IN VIRTUAL_KBD_KEY *VirtualKey - ) -{ - EFI_STATUS Status; - UINTN Value = 0; - - if ((VirtualKey == NULL) || (mGpio == NULL)) { - return FALSE; - } - if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { - goto Done; - } else { - Status = mGpio->Get (mGpio, DETECT_SW_FASTBOOT, &Value); - if (EFI_ERROR (Status) || (Value != 0)) { - return FALSE; - } - } -Done: - VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE; - VirtualKey->Key.ScanCode = SCAN_NULL; - VirtualKey->Key.UnicodeChar = L'f'; - return TRUE; -} - -EFI_STATUS -EFIAPI -VirtualKeyboardClear ( - IN VIRTUAL_KBD_KEY *VirtualKey - ) -{ - if (VirtualKey == NULL) { - return EFI_INVALID_PARAMETER; - } - if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { - MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE); - WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4); - } - return EFI_SUCCESS; -} - -PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = { - VirtualKeyboardRegister, - VirtualKeyboardReset, - VirtualKeyboardQuery, - VirtualKeyboardClear -}; - -EFI_STATUS -EFIAPI -HiKey960EntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_EVENT EndOfDxeEvent; - - InitPeripherals (); - - // - // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. - // The "OnEndOfDxe()" function is declared as the call back function. - // It will be called at the end of the DXE phase when an event of the - // same group is signalled to inform about the end of the DXE phase. - // Install the INSTALL_FDT_PROTOCOL protocol. - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - OnEndOfDxe, - NULL, - &gEfiEndOfDxeEventGroupGuid, - &EndOfDxeEvent - ); - if (EFI_ERROR (Status)) { - return Status; - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gPlatformVirtualKeyboardProtocolGuid, - EFI_NATIVE_INTERFACE, - &mVirtualKeyboard - ); - if (EFI_ERROR (Status)) { - return Status; - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gPlatformBootManagerProtocolGuid, - EFI_NATIVE_INTERFACE, - &mPlatformBootManager - ); - return Status; -} diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h deleted file mode 100644 index 0629fa4a8117b55bfb85cb3a236d50b29dc4dfd3..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h +++ /dev/null @@ -1,25 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __HIKEY960DXE_H__ -#define __HIKEY960DXE_H__ - -#define ADB_REBOOT_ADDRESS 0x32100000 -#define ADB_REBOOT_BOOTLOADER 0x77665500 -#define ADB_REBOOT_NONE 0x77665501 - -#define DETECT_SW_FASTBOOT 68 // GPIO8_4 - -#define HIKEY960_BOOT_OPTION_NUM 4 - -enum { - BOOT_MODE_RECOVERY = 0, - BOOT_MODE_MASK = 1, -}; - -#endif /* __HIKEY960DXE_H__ */ diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf deleted file mode 100644 index 5e1c52b84b830f26ee26730a5f883cd7af85dcef..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf +++ /dev/null @@ -1,53 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - INF_VERSION = 0x0001001a - BASE_NAME = HiKey960Dxe - FILE_GUID = 6d824b2c-640e-4643-b9f2-9c09e8bff429 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = HiKey960EntryPoint - -[Sources.common] - HiKey960Dxe.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Platform/Hisilicon/HiKey960/HiKey960.dec - Silicon/Hisilicon/Hi3660/Hi3660.dec - -[LibraryClasses] - BaseMemoryLib - CacheMaintenanceLib - DxeServicesTableLib - IoLib - PcdLib - TimerLib - UefiBootManagerLib - UefiDriverEntryPoint - UefiLib - -[Protocols] - gEfiDevicePathFromTextProtocolGuid - gEfiLoadedImageProtocolGuid - gEmbeddedGpioProtocolGuid - gPlatformBootManagerProtocolGuid - gPlatformVirtualKeyboardProtocolGuid - -[Pcd] - gHiKey960TokenSpaceGuid.PcdAndroidBootDevicePath - gHiKey960TokenSpaceGuid.PcdAndroidBootFile - gHiKey960TokenSpaceGuid.PcdAndroidFastbootFile - gHiKey960TokenSpaceGuid.PcdSdBootDevicePath - -[Guids] - gEfiEndOfDxeEventGroupGuid - -[Depex] - TRUE diff --git a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c deleted file mode 100644 index 74f10bf9e6b5fdd870e4db3fd564ff8861fbd57c..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c +++ /dev/null @@ -1,77 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include - -#include - -GPIO_CONTROLLER gGpioDevice[] = { - // - // { base address, gpio index, gpio count } - // - { 0xe8a0b000, 0, 8 }, // GPIO0 - { 0xe8a0c000, 8, 8 }, // GPIO1 - { 0xe8a0d000, 16, 8 }, // GPIO2 - { 0xe8a0e000, 24, 8 }, // GPIO3 - { 0xe8a0f000, 32, 8 }, // GPIO4 - { 0xe8a10000, 40, 8 }, // GPIO5 - { 0xe8a11000, 48, 8 }, // GPIO6 - { 0xe8a12000, 56, 8 }, // GPIO7 - { 0xe8a13000, 64, 8 }, // GPIO8 - { 0xe8a14000, 72, 8 }, // GPIO9 - { 0xe8a15000, 80, 8 }, // GPIO10 - { 0xe8a16000, 88, 8 }, // GPIO11 - { 0xe8a17000, 96, 8 }, // GPIO12 - { 0xe8a18000, 104, 8 }, // GPIO13 - { 0xe8a19000, 112, 8 }, // GPIO14 - { 0xe8a1a000, 120, 8 }, // GPIO15 - { 0xe8a1b000, 128, 8 }, // GPIO16 - { 0xe8a1c000, 136, 8 }, // GPIO17 - { 0xff3b4000, 144, 8 }, // GPIO18 - { 0xff3b5000, 152, 8 }, // GPIO19 - { 0xe8a1f000, 160, 8 }, // GPIO20 - { 0xe8a20000, 168, 8 }, // GPIO21 - { 0xfff0b000, 176, 8 }, // GPIO22 - { 0xfff0c000, 184, 8 }, // GPIO23 - { 0xfff0d000, 192, 8 }, // GPIO24 - { 0xfff0e000, 200, 8 }, // GPIO25 - { 0xfff0f000, 208, 8 }, // GPIO26 - { 0xfff10000, 216, 8 }, // GPIO27 - { 0xfff1d000, 224, 8 }, // GPIO28 -}; - -PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { - // - // { global gpio count, gpio controller count, GPIO_CONTROLLER } - // - 232, 29, gGpioDevice -}; - -EFI_STATUS -EFIAPI -HiKey960GpioEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_HANDLE Handle; - - // Install the Embedded Platform GPIO Protocol onto a new handle - Handle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces( - &Handle, - &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, - NULL - ); - if (EFI_ERROR(Status)) { - Status = EFI_OUT_OF_RESOURCES; - } - - return Status; -} diff --git a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf deleted file mode 100644 index 9fe2d2fe52db50dfae74a37db4e592156323812a..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2018, Linaro. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - INF_VERSION = 0x0001001a - BASE_NAME = HiKey960GpioDxe - FILE_GUID = 6aa12592-7e36-4aec-acf8-2ac2fd13815c - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = HiKey960GpioEntryPoint - -[Sources] - HiKey960GpioDxe.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - -[Protocols] - gPlatformGpioProtocolGuid - -[Depex] - TRUE diff --git a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960.c b/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960.c deleted file mode 100644 index d7f65420a59315dab53ab4353847d89f8c77b98b..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960.c +++ /dev/null @@ -1,136 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include - -#include - -ARM_CORE_INFO mHiKey960InfoTable[] = { - { - // Cluster 0, Core 0 - 0x0, 0x0, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 0, Core 1 - 0x0, 0x1, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 0, Core 2 - 0x0, 0x2, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 0, Core 3 - 0x0, 0x3, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 0 - 0x1, 0x0, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 1 - 0x1, 0x1, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 2 - 0x1, 0x2, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - }, - { - // Cluster 1, Core 3 - 0x1, 0x3, - - // MP Core MailBox Set/Get/Clear Addresses and Clear Value - (UINT64)0xFFFFFFFF - } -}; - -/** - Return the current Boot Mode - - This function returns the boot reason on the platform - - @return Return the current Boot Mode of the platform - -**/ -EFI_BOOT_MODE -ArmPlatformGetBootMode ( - VOID - ) -{ - return BOOT_WITH_FULL_CONFIGURATION; -} - -/** - Initialize controllers that must setup in the normal world - - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim - in the PEI phase. - -**/ -RETURN_STATUS -ArmPlatformInitialize ( - IN UINTN MpId - ) -{ - return RETURN_SUCCESS; -} - -EFI_STATUS -PrePeiCoreGetMpCoreInfo ( - OUT UINTN *CoreCount, - OUT ARM_CORE_INFO **ArmCoreTable - ) -{ - // Only support one cluster - *CoreCount = sizeof(mHiKey960InfoTable) / sizeof(ARM_CORE_INFO); - *ArmCoreTable = mHiKey960InfoTable; - return EFI_SUCCESS; -} - -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; - -EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi - } -}; - -VOID -ArmPlatformGetPlatformPpiList ( - OUT UINTN *PpiListSize, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiList - ) -{ - *PpiListSize = sizeof(gPlatformPpiTable); - *PpiList = gPlatformPpiTable; -} diff --git a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Helper.S b/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Helper.S deleted file mode 100644 index e0bd8ed95305338aa52f943ac05c1dac1a023614..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Helper.S +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -#include -#include - -.text -.align 3 - -ASM_FUNC(ArmPlatformPeiBootAction) - ret diff --git a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf b/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf deleted file mode 100644 index 5ccf4a11d5e2999be123477bfa14feb907b09d95..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = HiKey960Lib - FILE_GUID = 28873463-debb-4573-8382-1036f74bfcca - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformLib - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - -[LibraryClasses] - ArmLib - HobLib - IoLib - MemoryAllocationLib - SerialPortLib - -[Sources.common] - HiKey960.c - HiKey960Helper.S - HiKey960Mem.c - -[Ppis] - gArmMpCoreInfoPpiGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmPrimaryCore - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c b/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c deleted file mode 100644 index 68ca76688e0216890b9ac91d1697b0fca4acacdc..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c +++ /dev/null @@ -1,157 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include - -// The total number of descriptors, including the final "end-of-table" descriptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 - -// DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED - -#define HI3660_PERIPH_BASE 0xE0000000 -#define HI3660_PERIPH_SZ 0x20000000 - -#define HIKEY960_EXTRA_SYSTEM_MEMORY_BASE 0x0000000100000000 -#define HIKEY960_EXTRA_SYSTEM_MEMORY_SIZE 0x0000000020000000 - -#define HIKEY960_MEMORY_SIZE 0x0000000100000000 - -STATIC struct HiKey960ReservedMemory { - EFI_PHYSICAL_ADDRESS Offset; - EFI_PHYSICAL_ADDRESS Size; -} HiKey960ReservedMemoryBuffer [] = { - { 0x1AC00000, 0x00098000 }, // ARM-TF reserved - { 0x32000000, 0x00100000 }, // PSTORE/RAMOOPS - { 0x32100000, 0x00001000 }, // ADB REBOOT "REASON" - { 0x3E000000, 0x02000000 }, // TEE OS - { 0x89B80000, 0x00100000 }, // MCU Code reserved - { 0x89C80000, 0x00040000 } // MCU reserved -}; - -/** - Return the Virtual Memory Map of your platform - - This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. - - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- - Virtual Memory mapping. This array must be ended by a zero-filled - entry - -**/ -VOID -ArmPlatformGetVirtualMemoryMap ( - IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap - ) -{ - ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; - UINTN Index = 0, Count, ReservedTop; - EFI_PEI_HOB_POINTERS NextHob; - UINT64 ResourceLength; - EFI_PHYSICAL_ADDRESS ResourceTop; - - ResourceAttributes = ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED - ); - - // Create initial Base Hob for system memory. - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - ResourceAttributes, - PcdGet64 (PcdSystemMemoryBase), - PcdGet64 (PcdSystemMemorySize) - ); - - NextHob.Raw = GetHobList (); - Count = sizeof (HiKey960ReservedMemoryBuffer) / sizeof (struct HiKey960ReservedMemory); - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) - { - if (Index >= Count) - break; - if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && - (HiKey960ReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) && - ((HiKey960ReservedMemoryBuffer[Index].Offset + HiKey960ReservedMemoryBuffer[Index].Size) <= - NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) - { - ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; - ResourceLength = NextHob.ResourceDescriptor->ResourceLength; - ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; - ReservedTop = HiKey960ReservedMemoryBuffer[Index].Offset + HiKey960ReservedMemoryBuffer[Index].Size; - - // Create the System Memory HOB for the reserved buffer - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT, - HiKey960ReservedMemoryBuffer[Index].Offset, - HiKey960ReservedMemoryBuffer[Index].Size - ); - // Update the HOB - NextHob.ResourceDescriptor->ResourceLength = HiKey960ReservedMemoryBuffer[Index].Offset - - NextHob.ResourceDescriptor->PhysicalStart; - - // If there is some memory available on the top of the reserved memory then create a HOB - if (ReservedTop < ResourceTop) - { - BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, - ResourceAttributes, - ReservedTop, - ResourceTop - ReservedTop); - } - Index++; - } - NextHob.Raw = GET_NEXT_HOB (NextHob); - } - - ASSERT (VirtualMemoryMap != NULL); - - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( - EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS) - ); - if (VirtualMemoryTable == NULL) { - return; - } - - CacheAttributes = DDR_ATTRIBUTES_CACHED; - - Index = 0; - - // DDR - 3.0GB section - VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); - VirtualMemoryTable[Index].Attributes = CacheAttributes; - - // Hi3660 SOC peripherals - VirtualMemoryTable[++Index].PhysicalBase = HI3660_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase = HI3660_PERIPH_BASE; - VirtualMemoryTable[Index].Length = HI3660_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - - // End of Table - VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; - - ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - - *VirtualMemoryMap = VirtualMemoryTable; -} diff --git a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c deleted file mode 100644 index 667dbe8456d988025b341b0f5168e6937de1c311..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ /dev/null @@ -1,295 +0,0 @@ -/** @file - PCI Host Bridge Library instance for Hisilicon D0x - - Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - -#pragma pack(1) -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; -#pragma pack () - -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A03), // PCI - 0 - }, { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } -}; - -STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate = { - 0, // Segment - 0, // Supports - 0, // Attributes - TRUE, // DmaAbove4G - FALSE, // NoExtendedConfigSpace - FALSE, // ResourceAssigned - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - { - // Bus - 0, - 0 - }, { - // Io - 0, - 0, - 0 - }, { - // Mem - MAX_UINT64, - 0, - 0 - }, { - // MemAbove4G - MAX_UINT64, - 0, - 0 - }, { - // PMem - MAX_UINT64, - 0, - 0 - }, { - // PMemAbove4G - MAX_UINT64, - 0, - 0 - }, - (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath -}; - -STATIC -EFI_STATUS -ConstructRootBridge ( - PCI_ROOT_BRIDGE *Bridge, - PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture - ) -{ - EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; - CopyMem (Bridge, &mRootBridgeTemplate, sizeof *Bridge); - Bridge->Segment = Appeture->Segment; - Bridge->Bus.Base = Appeture->BusBase; - Bridge->Bus.Limit = Appeture->BusLimit; - Bridge->Io.Base = Appeture->IoBase; - // According to UEFI 2.7, device address = host address + translation - Bridge->Io.Translation = Appeture->IoBase - Appeture->CpuIoRegionBase; - // IoLimit is actually an address in CPU view - // TODO: improve the definition of PCI_ROOT_BRIDGE_RESOURCE_APPETURE - Bridge->Io.Limit = Appeture->IoLimit + Bridge->Io.Translation; - if (Appeture->PciRegionBase > MAX_UINT32) { - Bridge->MemAbove4G.Base = Appeture->PciRegionBase; - Bridge->MemAbove4G.Limit = Appeture->PciRegionLimit; - Bridge->MemAbove4G.Translation = Appeture->PciRegionBase - Appeture->CpuMemRegionBase; - } else { - Bridge->Mem.Base = Appeture->PciRegionBase; - Bridge->Mem.Limit = Appeture->PciRegionLimit; - Bridge->Mem.Translation = Appeture->PciRegionBase - Appeture->CpuMemRegionBase; - } - - DevicePath = AllocateCopyPool(sizeof mEfiPciRootBridgeDevicePath, &mEfiPciRootBridgeDevicePath); - if (DevicePath == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] AllocatePool failed!\n", __func__, __LINE__)); - return EFI_OUT_OF_RESOURCES; - } - - DevicePath->AcpiDevicePath.UID = Bridge->Segment; - Bridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; - return EFI_SUCCESS; -} - -/** - Return all the root bridge instances in an array. - - @param Count Return the count of root bridge instances. - - @return All the root bridge instances in an array. - The array should be passed into PciHostBridgeFreeRootBridges() - when it's not used. -**/ -PCI_ROOT_BRIDGE * -EFIAPI -PciHostBridgeGetRootBridges ( - UINTN *Count - ) -{ - EFI_STATUS Status; - UINTN Loop1; - UINTN Loop2; - UINT32 PcieRootBridgeMask; - UINTN RootBridgeCount = 0; - PCI_ROOT_BRIDGE *Bridges; - - // Set default value to 0 in case we got any error. - *Count = 0; - - - if (!OemIsMpBoot()) - { - PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask); - } - else - { - PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P); - } - - for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) { - if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) { - continue; - } - - for (Loop2 = 0; Loop2 < PCIE_MAX_ROOTBRIDGE; Loop2++) { - if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) { - continue; - } - RootBridgeCount++; - } - } - - Bridges = AllocatePool (RootBridgeCount * sizeof *Bridges); - if (Bridges == NULL) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - AllocatePool failed!\n", __func__, __LINE__)); - return NULL; - } - - for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) { - if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) { - continue; - } - - for (Loop2 = 0; Loop2 < PCIE_MAX_ROOTBRIDGE; Loop2++) { - if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) { - continue; - } - Status = ConstructRootBridge (&Bridges[*Count], &mResAppeture[Loop1][Loop2]); - if (EFI_ERROR (Status)) { - continue; - } - (*Count)++; - } - } - - if (*Count == 0) { - FreePool (Bridges); - return NULL; - } - return Bridges; -} - -/** - Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). - - @param Bridges The root bridge instances array. - @param Count The count of the array. -**/ -VOID -EFIAPI -PciHostBridgeFreeRootBridges ( - PCI_ROOT_BRIDGE *Bridges, - UINTN Count - ) -{ - UINTN Index; - - for (Index = 0; Index < Count; Index++) { - FreePool (Bridges[Index].DevicePath); - } - - if (Bridges != NULL) { - FreePool (Bridges); - } -} - -STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { - L"Mem", L"I/O", L"Bus" -}; - -/** - Inform the platform that the resource conflict happens. - - @param HostBridgeHandle Handle of the Host Bridge. - @param Configuration Pointer to PCI I/O and PCI memory resource - descriptors. The Configuration contains the resources - for all the root bridges. The resource for each root - bridge is terminated with END descriptor and an - additional END is appended indicating the end of the - entire resources. The resource descriptor field - values follow the description in - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL - .SubmitResources(). -**/ -VOID -EFIAPI -PciHostBridgeResourceConflict ( - EFI_HANDLE HostBridgeHandle, - VOID *Configuration - ) -{ - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; - UINTN RootBridgeIndex; - DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); - - RootBridgeIndex = 0; - Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; - while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { - DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); - for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { - ASSERT (Descriptor->ResType < - ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) - ); - DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", - mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], - Descriptor->AddrLen, Descriptor->AddrRangeMax - )); - if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { - DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", - Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, - ((Descriptor->SpecificFlag & - EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE - ) != 0) ? L" (Prefetchable)" : L"" - )); - } - } - // - // Skip the END descriptor for root bridge - // - ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); - Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( - (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 - ); - } -} diff --git a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf deleted file mode 100644 index fb9baf4072050633ac0f815afebbf9bfca67382d..0000000000000000000000000000000000000000 --- a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ /dev/null @@ -1,45 +0,0 @@ -## @file -# PCI Host Bridge Library instance for Hisilicon D0x -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x0001000A - BASE_NAME = PciHostBridgeLib - FILE_GUID = e5c91e8a-0b2b-11e8-9533-286ed489ee9b - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER - -# -# The following information is for reference only and not required by the build -# tools. -# -# VALID_ARCHITECTURES = AARCH64 ARM -# - -[Sources] - PciHostBridgeLib.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - DevicePathLib - HisiOemMiscLib - MemoryAllocationLib - -[Pcd] - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P diff --git a/REVIEWERS b/REVIEWERS index 16caaf3f181d2d07364e9e12b185be8f6b93635f..c3468c9111781242cebd8ec8639aabb63a8fd007 100644 --- a/REVIEWERS +++ b/REVIEWERS @@ -23,11 +23,6 @@ /Features/Ext4Pkg/** @mhaeuser -# Hisilicon -# Add Wenyi Xie -/Platform/Hisilicon/** @ardbiesheuvel -/Silicon/Hisilicon/** @ardbiesheuvel - /Features/Intel/** @lgao4 /Features/Intel/Debugging/** @lgao4 /Features/Intel/OutOfBandManagement/IpmiFeaturePkg/** @lgao4 diff --git a/Readme.md b/Readme.md index 792e27e5184319eb3253a7878767910d3293e9e5..64d70fcd500f7539108401b081627c2ef329f642 100644 --- a/Readme.md +++ b/Readme.md @@ -258,13 +258,6 @@ they will be documented with the platform. ## BeagleBoard * [BeagleBoard](Platform/BeagleBoard/BeagleBoardPkg) -## Hisilicon -* [D03](Platform/Hisilicon/D03) -* [D05](Platform/Hisilicon/D05) -* [D06](Platform/Hisilicon/D06) -* [HiKey](Platform/Hisilicon/HiKey) -* [HiKey960](Platform/Hisilicon/HiKey960) - ## Intel ### [Minimum Platforms](Platform/Intel/Readme.md) * [Kaby Lake](Platform/Intel/KabylakeOpenBoardPkg) diff --git a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c deleted file mode 100644 index 34a1dc9fa3cd135585c34f6b1634b71e75bf4487..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ /dev/null @@ -1,86 +0,0 @@ -/** @file - - Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.
- Copyright (c) 2015 - 2020, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "UpdateDsdt.h" - -EFI_EVENT mUpdateAcpiDsdtTableEvent; - -VOID -EFIAPI -UpdateAcpiDsdt ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; - EFI_STATUS Status; - - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID**)&AcpiTableProtocol - ); - - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, " Unable to locate ACPI table protocol\n")); - return; - } - - Status = UpdateAcpiDsdtTable (); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, " UpdateAcpiDsdtTable Failed, Status = %r\n", Status)); - } - - gBS->CloseEvent (Event); - return; -} - -EFI_STATUS -EFIAPI -AcpiPlatformEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - // - // Register notify function - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - UpdateAcpiDsdt, - NULL, - &gEfiEventReadyToBootGuid, - &mUpdateAcpiDsdtTableEvent - ); - - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Create ReadyToBoot event for UpdateAcpiDsdt failed.\n")); - } else { - DEBUG ((DEBUG_INFO, "Create ReadyToBoot event for UpdateAcpiDsdt success.\n")); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf deleted file mode 100644 index efb7ff3c00caa0db773116a8f1269ca2d97492d6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ /dev/null @@ -1,67 +0,0 @@ -## @file -# -# Copyright (c) 2014, Applied Micro Curcuit Corp. All rights reserved.
-# Copyright (c) 2015 - 2020, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015, Linaro Limited. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AcpiPlatform - FILE_GUID = e0829681-e9fa-4117-a8d7-84efadff863d - MODULE_TYPE = DXE_DRIVER - #MODULE_TYPE = UEFI_APPLICATION - VERSION_STRING = 1.0 - ENTRY_POINT = AcpiPlatformEntryPoint - -[Sources] - AcpiPlatform.c - UpdateDsdt.c - -[Packages] - MdePkg/MdePkg.dec - ShellPkg/ShellPkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiLib - PcdLib - BaseMemoryLib - DebugLib - MemoryAllocationLib - UefiBootServicesTableLib - UefiDriverEntryPoint - #UefiApplicationEntryPoint - -[Guids] - gShellVariableGuid # ALWAYS_CONSUMED - gArmMpCoreInfoGuid - -[Protocols] - gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED - gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED - gHisiBoardNicProtocolGuid # PROTOCOL ALWAYS_CONSUMED - gHisiSasConfigProtocolGuid - -[FeaturePcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol - -[Pcd] - -[FixedPcd] - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision - -[Depex] - TRUE - diff --git a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/UpdateDsdt.c b/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/UpdateDsdt.c deleted file mode 100644 index 389280964ae6c94def39a6019b23a6db28bc0e37..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/UpdateDsdt.c +++ /dev/null @@ -1,656 +0,0 @@ -/** @file - - Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.
- Copyright (c) 2015 - 2020, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - This driver is called to initialize the FW part of the PHY in preparation - for the OS. - -**/ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -// Turn on debug message by enabling below define -//#define ACPI_DEBUG - -#ifdef ACPI_DEBUG -#define DBG(arg...) DEBUG((DEBUG_ERROR,## arg)) -#else -#define DBG(arg...) -#endif - -#define EFI_ACPI_MAX_NUM_TABLES 20 -#define DSDT_SIGNATURE 0x54445344 - -#define ACPI_ETH_MAC_KEY "local-mac-address" -#define ACPI_ETH_SAS_KEY "sas-addr" - -#define PREFIX_VARIABLE_NAME L"MAC" -#define PREFIX_VARIABLE_NAME_COMPAT L"RGMII_MAC" -#define ADDRESS_MAX_LEN 30 - -CHAR8 *mHisiAcpiDevId[] = {"HISI00C1","HISI00C2","HISI0162"}; - -typedef enum { - DsdtDeviceUnknown, - DsdtDeviceLan, - DsdtDeviceSas -} DSDT_DEVICE_TYPE; - -STATIC -EFI_STATUS -GetEnvMac( - IN UINTN MacNextID, - IN OUT UINT8 *MacBuffer - ) -{ - EFI_MAC_ADDRESS Mac; - EFI_STATUS Status; - HISI_BOARD_NIC_PROTOCOL *OemNic = NULL; - - Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __func__, __LINE__, Status)); - return Status; - } - - Status = OemNic->GetMac(&Mac, MacNextID); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] GetMac failed %r\n", __func__, __LINE__, Status)); - return Status; - } - - CopyMem (MacBuffer, &Mac, 6); - DEBUG((DEBUG_ERROR, "Port %d MAC %02x:%02x:%02x:%02x:%02x:%02x\n", - MacNextID, - MacBuffer[0], - MacBuffer[1], - MacBuffer[2], - MacBuffer[3], - MacBuffer[4], - MacBuffer[5] - )); - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -GetSasAddress ( - IN UINT8 Index, - IN OUT UINT8 *SasAddrBuffer - ) -{ - EFI_STATUS Status; - HISI_SAS_CONFIG_PROTOCOL *HisiSasConf; - - if (SasAddrBuffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - Status = gBS->LocateProtocol (&gHisiSasConfigProtocolGuid, NULL, (VOID **)&HisiSasConf); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Locate Sas Config Protocol failed %r\n", Status)); - SasAddrBuffer[0] = 0x00; - SasAddrBuffer[1] = 0x00; - SasAddrBuffer[2] = 0x00; - SasAddrBuffer[3] = 0x00; - SasAddrBuffer[4] = 0x00; - SasAddrBuffer[5] = 0x00; - SasAddrBuffer[6] = 0x00; - SasAddrBuffer[7] = Index; - return Status; - } - - return HisiSasConf->GetAddr (Index, SasAddrBuffer); -} - -STATIC -EFI_STATUS -UpdateAddressInOption ( - IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - IN EFI_ACPI_HANDLE ChildHandle, - IN UINTN DevNextID, - IN DSDT_DEVICE_TYPE FoundDev - ) -{ - EFI_STATUS Status; - EFI_ACPI_DATA_TYPE DataType; - CONST VOID *Buffer; - UINTN DataSize; - UINTN Count; - EFI_ACPI_HANDLE CurrentHandle; - UINT8 *AddressBuffer; - UINT8 AddressByte; - - AddressByte = 0; - AddressBuffer = AllocateZeroPool (ADDRESS_MAX_LEN); - if (AddressBuffer == NULL) { - DEBUG ((DEBUG_ERROR, "%a:%d AllocateZeroPool failed\n", __FILE__, __LINE__)); - return EFI_OUT_OF_RESOURCES; - } - - switch (FoundDev) { - case DsdtDeviceLan: - //Update the MAC - Status = GetEnvMac (DevNextID, AddressBuffer); - AddressByte = 6; - break; - case DsdtDeviceSas: - //Update SAS Address. - Status = GetSasAddress (DevNextID, AddressBuffer); - AddressByte = 8; - break; - default: - Status = EFI_INVALID_PARAMETER; - } - if (EFI_ERROR (Status)) { - FreePool (AddressBuffer); - return Status; - } - - for (Count = 0; Count < AddressByte; Count++) { - Status = AcpiTableProtocol->GetOption (CurrentHandle, 1, &DataType, &Buffer, &DataSize); - if (EFI_ERROR (Status)) { - break; - } - - if (DataType != EFI_ACPI_DATA_TYPE_UINT) - break; - - // only need one byte. - // FIXME: Assume the CPU is little endian - Status = AcpiTableProtocol->SetOption ( - CurrentHandle, - 1, - AddressBuffer + Count, - sizeof(UINT8)); - if (EFI_ERROR (Status)) { - break; - } - - Status = AcpiTableProtocol->GetChild (ChildHandle, &CurrentHandle); - if (EFI_ERROR (Status) || CurrentHandle == NULL) { - break; - } - } - - FreePool (AddressBuffer); - return Status; -} - -STATIC -EFI_STATUS -UpdateAddressInPackage ( - IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - IN EFI_ACPI_HANDLE ChildHandle, - IN UINTN Level, - IN OUT BOOLEAN *Found, - IN UINTN DevNextID, - IN DSDT_DEVICE_TYPE FoundDev - ) -{ - // ASL template for ethernet driver: -/* - * Name (_DSD, Package () { - * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - * Package () { - * Package (2) {"mac-address", Package (6) { 00, 11, 22, 33, 44, 55 }} - * Package (2) {"phy-channel", 0}, - * Package (2) {"phy-mode", "rgmii"}, - * Package (2) {"max-transfer-unit", 0x5dc}, // MTU of 1500 - * Package (2) {"max-speed", 0x3e8}, // 1000 Mbps - * } - * }) - */ - EFI_STATUS Status; - EFI_ACPI_DATA_TYPE DataType; - CONST UINT8 *Data; - CONST VOID *Buffer; - UINTN DataSize; - EFI_ACPI_HANDLE CurrentHandle; - EFI_ACPI_HANDLE NextHandle; - EFI_ACPI_HANDLE Level1Handle; - - DBG("In Level:%d\n", Level); - Level1Handle = NULL; - Status = EFI_SUCCESS; - for (CurrentHandle = NULL; ;) { - Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle); - if (Level == 1) { - Level1Handle = CurrentHandle; - } - if (Level != 3 && (EFI_ERROR(Status) || CurrentHandle == NULL)) - break; - - Status = AcpiTableProtocol->GetOption(CurrentHandle, 0, &DataType, &Buffer, &DataSize); - Data = Buffer; - DBG("_DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n", - DataSize, Data[0], DataSize > 1 ? Data[1] : 0); - - if (Level < 2 && Data[0] != AML_PACKAGE_OP) - continue; - - if (Level == 2 && Data[0] == AML_STRING_PREFIX) { - Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) - break; - - DBG(" _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n", - DataSize, Data[0], DataSize > 1 ? Data[1] : 0); - - Data = Buffer; - if ((DataType != EFI_ACPI_DATA_TYPE_STRING) || - ((AsciiStrCmp ((CHAR8 *) Data, ACPI_ETH_MAC_KEY) != 0) && - (AsciiStrCmp ((CHAR8 *) Data, ACPI_ETH_SAS_KEY) != 0))) { - ChildHandle = Level1Handle; - continue; - } - - DBG("_DSD Key Type %d. Found address key\n", DataType); - - // - // We found the node. - // - *Found = TRUE; - continue; - } - - if (Level == 3 && *Found) { - Status = UpdateAddressInOption (AcpiTableProtocol, ChildHandle, DevNextID, FoundDev); - break; - } - - if (Level > 3) - break; - - //Search next package - AcpiTableProtocol->Open((VOID *) Buffer, &NextHandle); - Status = UpdateAddressInPackage ( - AcpiTableProtocol, - NextHandle, - Level + 1, - Found, - DevNextID, - FoundDev); - AcpiTableProtocol->Close(NextHandle); - if (!EFI_ERROR(Status)) - break; - } - - return Status; -} - -STATIC -EFI_STATUS -SearchReplacePackageAddress ( - IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - IN EFI_ACPI_HANDLE ChildHandle, - IN UINTN DevNextID, - IN DSDT_DEVICE_TYPE FoundDev - ) -{ - BOOLEAN Found = FALSE; - UINTN Level = 0; - - return UpdateAddressInPackage (AcpiTableProtocol, ChildHandle, Level, - &Found, DevNextID, FoundDev); -} - -EFI_STATUS -GetDeviceInfo ( - EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - EFI_ACPI_HANDLE ChildHandle, - UINTN *DevID, - DSDT_DEVICE_TYPE *FoundDev - ) -{ - EFI_STATUS Status; - EFI_ACPI_DATA_TYPE DataType; - CHAR8 Data[5]; - CONST VOID *Buffer; - UINTN DataSize; - - // Get NameString - Status = AcpiTableProtocol->GetOption (ChildHandle, 1, &DataType, &Buffer, &DataSize); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a:%d] Get NameString failed: %r\n", __func__, __LINE__, Status)); - return Status; - } - - CopyMem (Data, Buffer, 4); - DBG("Size %p Data %02x %02x %02x %02x\n", DataSize, Data[0], Data[1], Data[2], Data[3]); - - Data[4] = '\0'; - if ((DataSize != 4) || - (Data[3] > '9' || Data[3] < '0')) { - DEBUG ((DEBUG_ERROR, "The NameString %a is not ETHn or SASn\n", Data)); - return EFI_INVALID_PARAMETER; - } - - if (AsciiStrnCmp ("ETH", Data, 3) == 0) { - *FoundDev = DsdtDeviceLan; - } else if (AsciiStrnCmp ("SAS", Data, 3) == 0) { - *FoundDev = DsdtDeviceSas; - } else { - DEBUG ((DEBUG_ERROR, "[%a:%d] The NameString %a is not ETHn or SASn\n", - __func__, __LINE__, Data)); - return EFI_INVALID_PARAMETER; - } - - *DevID = Data[3] - '0'; - return EFI_SUCCESS; -} - -EFI_STATUS ProcessDSDTDevice ( - EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - EFI_ACPI_HANDLE ChildHandle) -{ - EFI_STATUS Status; - EFI_ACPI_DATA_TYPE DataType; - CONST UINT8 *Data; - CONST VOID *Buffer; - UINTN DataSize; - EFI_ACPI_HANDLE DevHandle; - DSDT_DEVICE_TYPE FoundDev = DsdtDeviceUnknown; - UINTN DevNextID; - BOOLEAN HisiAcpiDevNotFound; - UINTN Index; - - Status = AcpiTableProtocol->GetOption(ChildHandle, 0, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) - return EFI_SUCCESS; - - Data = Buffer; - // - // Skip all non-device type - // - if (DataSize != 2 || Data[0] != AML_EXT_OP || Data[1] != AML_EXT_DEVICE_OP) - return EFI_SUCCESS; - - // - // Walk the device type node - // - for (DevHandle = NULL; ; ) { - Status = AcpiTableProtocol->GetChild(ChildHandle, &DevHandle); - if (EFI_ERROR(Status) || DevHandle == NULL) - break; - - // - // Search for _HID with Device ID - // - Status = AcpiTableProtocol->GetOption(DevHandle, 0, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) - break; - - Data = Buffer; - DBG("Data Type 0x%02X %02X\n", Data[0], DataSize > 1 ? Data[1] : 0); - if (DataSize == 1 && Data[0] == AML_NAME_OP) { - Status = AcpiTableProtocol->GetOption(DevHandle, 1, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) - break; - - Data = Buffer; - if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) { - if (AsciiStrnCmp((CHAR8 *) Data, "_HID", 4) == 0) { - EFI_ACPI_HANDLE ValueHandle; - - Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) - break; - - if (DataType != EFI_ACPI_DATA_TYPE_CHILD) - continue; - - AcpiTableProtocol->Open((VOID *) Buffer, &ValueHandle); - Status = AcpiTableProtocol->GetOption(ValueHandle, 1, &DataType, &Buffer, &DataSize); - - Data = Buffer; - DBG("[%a:%d] - _HID = %a\n", __func__, __LINE__, Data); - - if (EFI_ERROR(Status) || - DataType != EFI_ACPI_DATA_TYPE_STRING) { - AcpiTableProtocol->Close (ValueHandle); - FoundDev = DsdtDeviceUnknown; - continue; - } - - HisiAcpiDevNotFound = TRUE; - for (Index = 0; Index < ARRAY_SIZE (mHisiAcpiDevId); Index++) { - if (AsciiStrCmp ((CHAR8 *)Data, mHisiAcpiDevId[Index]) == 0) { - HisiAcpiDevNotFound = FALSE; - break; - } - } - if (HisiAcpiDevNotFound) { - AcpiTableProtocol->Close (ValueHandle); - FoundDev = DsdtDeviceUnknown; - continue; - } - - DBG("Found device\n"); - AcpiTableProtocol->Close(ValueHandle); - Status = GetDeviceInfo (AcpiTableProtocol, ChildHandle, &DevNextID, &FoundDev); - if (EFI_ERROR (Status)) { - continue; - } - } else if ((FoundDev != DsdtDeviceUnknown) && AsciiStrnCmp((CHAR8 *) Data, "_DSD", 4) == 0) { - // - // Patch DSD data - // - EFI_ACPI_HANDLE PkgHandle; - Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) - break; - - if (DataType != EFI_ACPI_DATA_TYPE_CHILD) - continue; - - // - // Open package data - // - AcpiTableProtocol->Open((VOID *) Buffer, &PkgHandle); - Status = AcpiTableProtocol->GetOption(PkgHandle, 0, &DataType, &Buffer, &DataSize); - - Data = Buffer; - DBG("_DSD Subnode Store Op Code 0x%02X %02X\n", - Data[0], DataSize > 1 ? Data[1] : 0); - - // - // Walk the _DSD node - // - if (DataSize == 1 && Data[0] == AML_PACKAGE_OP) { - Status = SearchReplacePackageAddress (AcpiTableProtocol, PkgHandle, DevNextID, FoundDev); - } - - AcpiTableProtocol->Close(PkgHandle); - } else if (AsciiStrnCmp ((CHAR8 *) Data, "_ADR", 4) == 0) { - Status = AcpiTableProtocol->GetOption (DevHandle, 2, &DataType, &Buffer, &DataSize); - if (EFI_ERROR (Status)) { - break; - } - - if (DataType != EFI_ACPI_DATA_TYPE_CHILD) { - continue; - } - - Status = GetDeviceInfo (AcpiTableProtocol, ChildHandle, &DevNextID, &FoundDev); - - if (EFI_ERROR (Status)) { - continue; - } - } - } - } else if ((DataSize == 2) && (Data[0] == AML_EXT_OP) && (Data[1] == AML_EXT_DEVICE_OP)) { - ProcessDSDTDevice (AcpiTableProtocol, DevHandle); - } - } - - return EFI_SUCCESS; -} - - -BOOLEAN -IsSbScope ( - EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - EFI_ACPI_HANDLE ChildHandle - ) -{ - EFI_STATUS Status; - EFI_ACPI_DATA_TYPE DataType; - CONST UINT8 *Data; - CONST VOID *Buffer; - UINTN DataSize; - - Status = AcpiTableProtocol->GetOption (ChildHandle, 0, &DataType, &Buffer, &DataSize); - if (EFI_ERROR(Status)) return FALSE; - - Data = Buffer; - if (DataSize != 1 || Data[0] != AML_SCOPE_OP) { - return FALSE; - } - - return TRUE; -} - -EFI_STATUS ProcessDSDTChild( - EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - EFI_ACPI_HANDLE ChildHandle) -{ - EFI_STATUS Status; - EFI_ACPI_HANDLE DevHandle; - - // Check Scope(_SB) at first - if (!IsSbScope (AcpiTableProtocol, ChildHandle)) { - return ProcessDSDTDevice (AcpiTableProtocol, ChildHandle); - } - - for (DevHandle = NULL; ; ) { - Status = AcpiTableProtocol->GetChild (ChildHandle, &DevHandle); - if (EFI_ERROR(Status) || DevHandle == NULL) { - break; - } - - ProcessDSDTDevice (AcpiTableProtocol, DevHandle); - } - - return EFI_SUCCESS; -} - -static EFI_STATUS ProcessDSDT( - EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol, - EFI_ACPI_HANDLE TableHandle) -{ - EFI_STATUS Status; - EFI_ACPI_HANDLE ChildHandle; - // - // Parse table for device type - DBG ("[%a:%d] - TableHandle=%p\n", __func__, __LINE__, TableHandle); - for (ChildHandle = NULL; ; ) { - Status = AcpiTableProtocol->GetChild(TableHandle, &ChildHandle); - DBG ("[%a:%d] - Child=%p, %r\n", __func__, __LINE__, ChildHandle, Status); - if (EFI_ERROR(Status)) - break; - if (ChildHandle == NULL) - break; - - ProcessDSDTChild(AcpiTableProtocol, ChildHandle); - } - - return EFI_SUCCESS; -} - -STATIC -VOID -AcpiCheckSum ( - IN OUT EFI_ACPI_SDT_HEADER *Table - ) -{ - UINTN ChecksumOffset; - UINT8 *Buffer; - - ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); - Buffer = (UINT8 *)Table; - - // - // set checksum to 0 first - // - Buffer[ChecksumOffset] = 0; - - // - // Update checksum value - // - Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Table->Length); -} - -EFI_STATUS -UpdateAcpiDsdtTable ( - VOID - ) -{ - EFI_STATUS Status; - EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol; - EFI_ACPI_SDT_HEADER *Table; - EFI_ACPI_TABLE_VERSION TableVersion; - UINTN TableKey; - EFI_ACPI_HANDLE TableHandle; - UINTN i; - - DEBUG ((DEBUG_ERROR, "Updating Ethernet MAC in ACPI DSDT...\n")); - - // - // Find the AcpiTable protocol - Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol); - if (EFI_ERROR(Status)) { - DBG("Unable to locate ACPI table protocol\n"); - return EFI_SUCCESS; - } - - // - // Search for DSDT Table - for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) { - Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey); - if (EFI_ERROR(Status)) - break; - if (Table->Signature != DSDT_SIGNATURE) - continue; - - Status = AcpiTableProtocol->OpenSdt(TableKey, &TableHandle); - if (EFI_ERROR(Status)) - break; - - ProcessDSDT(AcpiTableProtocol, TableHandle); - - AcpiTableProtocol->Close(TableHandle); - AcpiCheckSum (Table); - } - - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/UpdateDsdt.h b/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/UpdateDsdt.h deleted file mode 100644 index 246eb929e307b16d90e1ee3bacaecec0972a9ef9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/AcpiPlatformDxe/UpdateDsdt.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * - * Copyright (c) 2014, Applied Micro Circuits Corporation - * Copyright (c) 2020, Hisilicon Limited. All rights reserved. - * Copyright (c) 2015, Linaro Limited. All rights reserved. - * Author: Loc Ho - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - */ -#ifndef UPDATE_DSDT_H_ -#define UPDATE_DSDT_H_ - -EFI_STATUS UpdateAcpiDsdtTable (VOID); - -#endif - diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c deleted file mode 100644 index 622cc642664335ab09186a25a6e1a0574e8cd46d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c +++ /dev/null @@ -1,103 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "FlashFvbDxe.h" - -// -// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks -// -EFI_STATUS -EFIAPI -FlashBlockIoReadBlocks ( - IN EFI_BLOCK_IO_PROTOCOL* This, - IN UINT32 MediaId, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - OUT VOID* Buffer -) -{ - FLASH_INSTANCE* Instance; - EFI_STATUS Status; - - Instance = INSTANCE_FROM_BLKIO_THIS(This); - - DEBUG ((DEBUG_INFO, "FlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer)); - - if ( !This->Media->MediaPresent ) - { - Status = EFI_NO_MEDIA; - } - else if ( This->Media->MediaId != MediaId ) - { - Status = EFI_MEDIA_CHANGED; - } - else - { - Status = FlashReadBlocks (Instance, Lba, BufferSizeInBytes, Buffer); - } - - return Status; -} - -// -// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks -// -EFI_STATUS -EFIAPI -FlashBlockIoWriteBlocks ( - IN EFI_BLOCK_IO_PROTOCOL* This, - IN UINT32 MediaId, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - IN VOID* Buffer -) -{ - FLASH_INSTANCE* Instance; - EFI_STATUS Status; - - Instance = INSTANCE_FROM_BLKIO_THIS(This); - - DEBUG ((DEBUG_INFO, "FlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer)); - - if ( !This->Media->MediaPresent ) - { - Status = EFI_NO_MEDIA; - } - else if ( This->Media->MediaId != MediaId ) - { - Status = EFI_MEDIA_CHANGED; - } - else if ( This->Media->ReadOnly ) - { - Status = EFI_WRITE_PROTECTED; - } - else - { - Status = FlashWriteBlocks (Instance, Lba, BufferSizeInBytes, Buffer); - } - - return Status; -} - -// -// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks -// -EFI_STATUS -EFIAPI -FlashBlockIoFlushBlocks ( - IN EFI_BLOCK_IO_PROTOCOL* This -) -{ - // No Flush required for the NOR Flash driver - // because cache operations are not permitted. - - // Nothing to do so just return without error - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c deleted file mode 100644 index cb5965668fae82720ca02019e283711a0a456bba..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ /dev/null @@ -1,1237 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on files under ArmPlatformPkg/Drivers/NorFlashDxe/ -**/ - -#include "FlashFvbDxe.h" -STATIC EFI_EVENT mFlashFvbVirtualAddrChangeEvent; -STATIC UINTN mFlashNvStorageVariableBase; - - -// -// Global variable declarations -// - -FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] = -{ - { - // UEFI Variable Services non-volatile storage - FixedPcdGet64 (PcdSFCMEM0BaseAddress), - FixedPcdGet64 (PcdFlashNvStorageVariableBase64), - 0x20000, - SIZE_64KB, - {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}} - } - -}; - -FLASH_INSTANCE** mFlashInstances; - -FLASH_INSTANCE mFlashInstanceTemplate = -{ - FLASH_SIGNATURE, // Signature - NULL, // Handle ... NEED TO BE FILLED - - FALSE, // Initialized - NULL, // Initialize - - 0, // DeviceBaseAddress ... NEED TO BE FILLED - 0, // RegionBaseAddress ... NEED TO BE FILLED - 0, // Size ... NEED TO BE FILLED - 0, // StartLba - - { - EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision - NULL, // Media ... NEED TO BE FILLED - NULL, //NorFlashBlockIoReset - FlashBlockIoReadBlocks, - FlashBlockIoWriteBlocks, - FlashBlockIoFlushBlocks - }, // BlockIoProtocol - - { - 0, // MediaId ... NEED TO BE FILLED - FALSE, // RemovableMedia - TRUE, // MediaPresent - FALSE, // LogicalPartition - FALSE, // ReadOnly - FALSE, // WriteCaching; - SIZE_64KB, // BlockSize ... NEED TO BE FILLED - 4, // IoAlign - 0, // LastBlock ... NEED TO BE FILLED - 0, // LowestAlignedLba - 1, // LogicalBlocksPerPhysicalBlock - }, //Media; - - FALSE, // SupportFvb ... NEED TO BE FILLED - { - FvbGetAttributes, - FvbSetAttributes, - FvbGetPhysicalAddress, - FvbGetBlockSize, - FvbRead, - FvbWrite, - FvbEraseBlocks, - NULL, //ParentHandle - }, // FvbProtoccol; - - { - { - { - HARDWARE_DEVICE_PATH, - HW_VENDOR_DP, - {(UINT8)(sizeof(VENDOR_DEVICE_PATH)), - (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)}, - }, - { 0x0, 0x0, 0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }}, // GUID ... NEED TO BE FILLED - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - {sizeof (EFI_DEVICE_PATH_PROTOCOL), - 0} - } - } // DevicePath -}; - -HISI_SPI_FLASH_PROTOCOL* mFlash; - -/// -/// The Firmware Volume Block Protocol is the low-level interface -/// to a firmware volume. File-level access to a firmware volume -/// should not be done using the Firmware Volume Block Protocol. -/// Normal access to a firmware volume must use the Firmware -/// Volume Protocol. Typically, only the file system driver that -/// produces the Firmware Volume Protocol will bind to the -/// Firmware Volume Block Protocol. -/// - -/** - Initialises the FV Header and Variable Store Header - to support variable operations. - - @param[in] Ptr - Location to initialise the headers - -**/ -EFI_STATUS -InitializeFvAndVariableStoreHeaders ( - IN FLASH_INSTANCE* Instance -) -{ - EFI_STATUS Status; - VOID* Headers; - UINTN HeadersLength; - EFI_FIRMWARE_VOLUME_HEADER* FirmwareVolumeHeader; - VARIABLE_STORE_HEADER* VariableStoreHeader; - - if (!Instance->Initialized && Instance->Initialize) - { - Instance->Initialize (Instance); - } - - HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER); - Headers = AllocateZeroPool(HeadersLength); - - // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous. - ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet64(PcdFlashNvStorageFtwWorkingBase64)); - ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet64(PcdFlashNvStorageFtwSpareBase64)); - - // Check if the size of the area is at least one block size - ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0)); - ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0)); - ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); - - // Ensure the Variable area Base Addresses are aligned on a block size boundaries - ASSERT((UINT32)PcdGet64(PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize == 0); - ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize == 0); - ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize == 0); - - // - // EFI_FIRMWARE_VOLUME_HEADER - // - FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers; - CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid); - FirmwareVolumeHeader->FvLength = - PcdGet32(PcdFlashNvStorageVariableSize) + - PcdGet32(PcdFlashNvStorageFtwWorkingSize) + - PcdGet32(PcdFlashNvStorageFtwSpareSize); - FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE; - FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) ( - EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled - EFI_FVB2_READ_STATUS | // Reads are currently enabled - EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY - EFI_FVB2_MEMORY_MAPPED | // It is memory mapped - EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1') - EFI_FVB2_WRITE_STATUS | // Writes are currently enabled - EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled - ); - FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY); - FirmwareVolumeHeader->Revision = EFI_FVH_REVISION; - FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1; - FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize; - FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0; - FirmwareVolumeHeader->BlockMap[1].Length = 0; - FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength); - - // - // VARIABLE_STORE_HEADER - // - VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + (UINTN)FirmwareVolumeHeader->HeaderLength); - CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid); - VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength; - VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED; - VariableStoreHeader->State = VARIABLE_STORE_HEALTHY; - - // Install the combined super-header in the NorFlash - Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers); - - FreePool (Headers); - return Status; -} - -/** - Check the integrity of firmware volume header. - - @param[in] FwVolHeader - A pointer to a firmware volume header - - @retval EFI_SUCCESS - The firmware volume is consistent - @retval EFI_NOT_FOUND - The firmware volume has been corrupted. - -**/ -EFI_STATUS -ValidateFvHeader ( - IN FLASH_INSTANCE* Instance -) -{ - UINT16 Checksum; - EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader; - VARIABLE_STORE_HEADER* VariableStoreHeader; - UINTN VariableStoreLength; - UINTN FvLength; - - FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress; - - FvLength = PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + - PcdGet32(PcdFlashNvStorageFtwSpareSize); - - // - // Verify the header revision, header signature, length - // Length of FvBlock cannot be 2**64-1 - // HeaderLength cannot be an odd number - // - if ( (FwVolHeader->Revision != EFI_FVH_REVISION) - || (FwVolHeader->Signature != EFI_FVH_SIGNATURE) - || (FwVolHeader->FvLength != FvLength) - ) - { - DEBUG ((DEBUG_ERROR, "ValidateFvHeader: No Firmware Volume header present\n")); - return EFI_NOT_FOUND; - } - - // Check the Firmware Volume Guid - if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) - { - DEBUG ((DEBUG_ERROR, "ValidateFvHeader: Firmware Volume Guid non-compatible\n")); - return EFI_NOT_FOUND; - } - - // Verify the header checksum - Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength); - if (Checksum != 0) - { - DEBUG ((DEBUG_ERROR, "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n", Checksum)); - return EFI_NOT_FOUND; - } - - VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + (UINTN)FwVolHeader->HeaderLength); - - // Check the Variable Store Guid - if ( CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) == FALSE ) - { - DEBUG ((DEBUG_ERROR, "ValidateFvHeader: Variable Store Guid non-compatible\n")); - return EFI_NOT_FOUND; - } - - VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength; - if (VariableStoreHeader->Size != VariableStoreLength) - { - DEBUG ((DEBUG_ERROR, "ValidateFvHeader: Variable Store Length does not match\n")); - return EFI_NOT_FOUND; - } - - return EFI_SUCCESS; -} - -/** - The FvbGetAttributes() function retrieves the attributes and - current settings of the block. - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. - - @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and - current settings are returned. - Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER. - - @retval EFI_SUCCESS The firmware volume attributes were returned. - - **/ -EFI_STATUS -EFIAPI -FvbGetAttributes( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - OUT EFI_FVB_ATTRIBUTES_2* Attributes -) -{ - EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; - FLASH_INSTANCE* Instance; - - Instance = INSTANCE_FROM_FVB_THIS(This); - - FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) ( - - EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled - EFI_FVB2_READ_STATUS | // Reads are currently enabled - EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY - EFI_FVB2_MEMORY_MAPPED | // It is memory mapped - EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1') - - ); - - // Check if it is write protected - if (Instance->Media.ReadOnly != TRUE) - { - - FlashFvbAttributes = FlashFvbAttributes | - EFI_FVB2_WRITE_STATUS | // Writes are currently enabled - EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled - } - - *Attributes = FlashFvbAttributes; - - return EFI_SUCCESS; -} - -/** - The FvbSetAttributes() function sets configurable firmware volume attributes - and returns the new settings of the firmware volume. - - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. - - @param Attributes On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2 - that contains the desired firmware volume settings. - On successful return, it contains the new settings of - the firmware volume. - Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER. - - @retval EFI_SUCCESS The firmware volume attributes were returned. - - @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities - as declared in the firmware volume header. - - **/ -EFI_STATUS -EFIAPI -FvbSetAttributes( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN OUT EFI_FVB_ATTRIBUTES_2* Attributes -) -{ - DEBUG ((DEBUG_ERROR, "FvbSetAttributes(0x%X) is not supported\n", *Attributes)); - return EFI_UNSUPPORTED; -} - -/** - The GetPhysicalAddress() function retrieves the base address of - a memory-mapped firmware volume. This function should be called - only for memory-mapped firmware volumes. - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. - - @param Address Pointer to a caller-allocated - EFI_PHYSICAL_ADDRESS that, on successful - return from GetPhysicalAddress(), contains the - base address of the firmware volume. - - @retval EFI_SUCCESS The firmware volume base address was returned. - - @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. - - **/ -EFI_STATUS -EFIAPI -FvbGetPhysicalAddress ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - OUT EFI_PHYSICAL_ADDRESS* Address -) -{ - - if(NULL == Address) - { - return EFI_UNSUPPORTED; - }; - - *Address = mFlashNvStorageVariableBase; - return EFI_SUCCESS; -} - -/** - The GetBlockSize() function retrieves the size of the requested - block. It also returns the number of additional blocks with - the identical size. The GetBlockSize() function is used to - retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). - - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. - - @param Lba Indicates the block for which to return the size. - - @param BlockSize Pointer to a caller-allocated UINTN in which - the size of the block is returned. - - @param NumberOfBlocks Pointer to a caller-allocated UINTN in - which the number of consecutive blocks, - starting with Lba, is returned. All - blocks in this range have a size of - BlockSize. - - - @retval EFI_SUCCESS The firmware volume base address was returned. - - @retval EFI_INVALID_PARAMETER The requested LBA is out of range. - - **/ -EFI_STATUS -EFIAPI -FvbGetBlockSize ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN EFI_LBA Lba, - OUT UINTN* BlockSize, - OUT UINTN* NumberOfBlocks -) -{ - EFI_STATUS Status; - FLASH_INSTANCE* Instance; - - Instance = INSTANCE_FROM_FVB_THIS(This); - - if (Lba > Instance->Media.LastBlock) - { - Status = EFI_INVALID_PARAMETER; - } - else - { - // This is easy because in this platform each NorFlash device has equal sized blocks. - *BlockSize = (UINTN) Instance->Media.BlockSize; - *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1); - - - Status = EFI_SUCCESS; - } - - return Status; -} - -STATIC -EFI_STATUS -EFIAPI -FvbReset( - IN EFI_BLOCK_IO_PROTOCOL *This, - IN BOOLEAN ExtendedVerification -) -{ - return EFI_SUCCESS; -} - - -/** - Reads the specified number of bytes into a buffer from the specified block. - - The Read() function reads the requested number of bytes from the - requested block and stores them in the provided buffer. - Implementations should be mindful that the firmware volume - might be in the ReadDisabled state. If it is in this state, - the Read() function must return the status code - EFI_ACCESS_DENIED without modifying the contents of the - buffer. The Read() function must also prevent spanning block - boundaries. If a read is requested that would span a block - boundary, the read must read up to the boundary but not - beyond. The output parameter NumBytes must be set to correctly - indicate the number of bytes actually read. The caller must be - aware that a read may be partially completed. - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. - - @param Lba The starting logical block index from which to read. - - @param Offset Offset into the block at which to begin reading. - - @param NumBytes Pointer to a UINTN. - At entry, *NumBytes contains the total size of the buffer. - At exit, *NumBytes contains the total number of bytes read. - - @param Buffer Pointer to a caller-allocated buffer that will be used - to hold the data that is read. - - @retval EFI_SUCCESS The firmware volume was read successfully, and contents are - in Buffer. - - @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. - On output, NumBytes contains the total number of bytes - returned in Buffer. - - @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state. - - @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read. - - **/ -EFI_STATUS -EFIAPI -FvbRead ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN EFI_LBA Lba, - IN UINTN Offset, - IN OUT UINTN* NumBytes, - IN OUT UINT8* Buffer -) -{ - EFI_STATUS Status; - UINTN BlockSize; - FLASH_INSTANCE* Instance; - - UINTN StartAddress; - UINTN ReadAddress; - - Instance = INSTANCE_FROM_FVB_THIS(This); - - if (!Instance->Initialized && Instance->Initialize) - { - if (EfiAtRuntime ()) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Initialize at runtime is not supported!\n", __func__, __LINE__)); - return EFI_UNSUPPORTED; - } - - Instance->Initialize(Instance); - } - - Status = EFI_SUCCESS; - - // Cache the block size to avoid de-referencing pointers all the time - BlockSize = Instance->Media.BlockSize; - - // The read must not span block boundaries. - // We need to check each variable individually because adding two large values together overflows. - if ((Offset >= BlockSize) || - (*NumBytes > BlockSize) || - ((Offset + *NumBytes) > BlockSize)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", __func__, __LINE__, Offset, *NumBytes, BlockSize )); - return EFI_BAD_BUFFER_SIZE; - } - - // We must have some bytes to read - if (*NumBytes == 0) - { - return EFI_BAD_BUFFER_SIZE; - } - - // Get the address to start reading from - StartAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, - Lba, - BlockSize - ); - ReadAddress = StartAddress - Instance->DeviceBaseAddress + Offset; - - Status = mFlash->Read(mFlash, (UINT32)ReadAddress, Buffer, *NumBytes); - if (EFI_SUCCESS != Status) - { - // Return one of the pre-approved error statuses - Status = EFI_DEVICE_ERROR; - return Status; - } - - - return Status; -} - -/** - Writes the specified number of bytes from the input buffer to the block. - - The Write() function writes the specified number of bytes from - the provided buffer to the specified block and offset. If the - firmware volume is sticky write, the caller must ensure that - all the bits of the specified range to write are in the - EFI_FVB_ERASE_POLARITY state before calling the Write() - function, or else the result will be unpredictable. This - unpredictability arises because, for a sticky-write firmware - volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY - state but cannot flip it back again. Before calling the - Write() function, it is recommended for the caller to first call - the EraseBlocks() function to erase the specified block to - write. A block erase cycle will transition bits from the - (NOT)EFI_FVB_ERASE_POLARITY state back to the - EFI_FVB_ERASE_POLARITY state. Implementations should be - mindful that the firmware volume might be in the WriteDisabled - state. If it is in this state, the Write() function must - return the status code EFI_ACCESS_DENIED without modifying the - contents of the firmware volume. The Write() function must - also prevent spanning block boundaries. If a write is - requested that spans a block boundary, the write must store up - to the boundary but not beyond. The output parameter NumBytes - must be set to correctly indicate the number of bytes actually - written. The caller must be aware that a write may be - partially completed. All writes, partial or otherwise, must be - fully flushed to the hardware before the Write() service - returns. - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. - - @param Lba The starting logical block index to write to. - - @param Offset Offset into the block at which to begin writing. - - @param NumBytes The pointer to a UINTN. - At entry, *NumBytes contains the total size of the buffer. - At exit, *NumBytes contains the total number of bytes actually written. - - @param Buffer The pointer to a caller-allocated buffer that contains the source for the write. - - @retval EFI_SUCCESS The firmware volume was written successfully. - - @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary. - On output, NumBytes contains the total number of bytes - actually written. - - @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state. - - @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be written. - - - **/ -EFI_STATUS -EFIAPI -FvbWrite ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN EFI_LBA Lba, - IN UINTN Offset, - IN OUT UINTN* NumBytes, - IN UINT8* Buffer -) -{ - EFI_STATUS Status; - UINTN BlockSize; - FLASH_INSTANCE* Instance; - UINTN BlockAddress; - UINTN WriteAddress; - - Instance = INSTANCE_FROM_FVB_THIS(This); - if (NULL == Instance) - { - return EFI_INVALID_PARAMETER; - - } - - if (!Instance->Initialized && Instance->Initialize) - { - if (EfiAtRuntime ()) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Initialize at runtime is not supported!\n", __func__, __LINE__)); - return EFI_UNSUPPORTED; - } - - Instance->Initialize(Instance); - } - - Status = EFI_SUCCESS; - - // Detect WriteDisabled state - if (Instance->Media.ReadOnly == TRUE) - { - DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Can not write: Device is in WriteDisabled state.\n")); - // It is in WriteDisabled state, return an error right away - return EFI_ACCESS_DENIED; - } - - // Cache the block size to avoid de-referencing pointers all the time - BlockSize = Instance->Media.BlockSize; - - // The write must not span block boundaries. - // We need to check each variable individually because adding two large values together overflows. - if ( ( Offset >= BlockSize ) || - ( *NumBytes > BlockSize ) || - ( (Offset + *NumBytes) > BlockSize ) ) - { - DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize )); - return EFI_BAD_BUFFER_SIZE; - } - - // We must have some bytes to write - if (*NumBytes == 0) - { - DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize )); - return EFI_BAD_BUFFER_SIZE; - } - - BlockAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, BlockSize); - WriteAddress = BlockAddress - Instance->DeviceBaseAddress + Offset; - - Status = mFlash->Write(mFlash, (UINT32)WriteAddress, (UINT8*)Buffer, *NumBytes); - if (EFI_SUCCESS != Status) - { - DEBUG((DEBUG_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status)); - return Status; - } - - return Status; - -} - -/** - Erases and initialises a firmware volume block. - - The EraseBlocks() function erases one or more blocks as denoted - by the variable argument list. The entire parameter list of - blocks must be verified before erasing any blocks. If a block is - requested that does not exist within the associated firmware - volume (it has a larger index than the last block of the - firmware volume), the EraseBlocks() function must return the - status code EFI_INVALID_PARAMETER without modifying the contents - of the firmware volume. Implementations should be mindful that - the firmware volume might be in the WriteDisabled state. If it - is in this state, the EraseBlocks() function must return the - status code EFI_ACCESS_DENIED without modifying the contents of - the firmware volume. All calls to EraseBlocks() must be fully - flushed to the hardware before the EraseBlocks() service - returns. - - @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL - instance. - - @param ... The variable argument list is a list of tuples. - Each tuple describes a range of LBAs to erase - and consists of the following: - - An EFI_LBA that indicates the starting LBA - - A UINTN that indicates the number of blocks to erase. - - The list is terminated with an EFI_LBA_LIST_TERMINATOR. - For example, the following indicates that two ranges of blocks - (5-7 and 10-11) are to be erased: - EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR); - - @retval EFI_SUCCESS The erase request successfully completed. - - @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state. - - @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written. - The firmware device may have been partially erased. - - @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do - not exist in the firmware volume. - - **/ -EFI_STATUS -EFIAPI -FvbEraseBlocks ( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - ... -) -{ - EFI_STATUS Status; - VA_LIST Args; - UINTN BlockAddress; // Physical address of Lba to erase - EFI_LBA StartingLba; // Lba from which we start erasing - UINTN NumOfLba; // Number of Lba blocks to erase - FLASH_INSTANCE* Instance; - - Instance = INSTANCE_FROM_FVB_THIS(This); - - Status = EFI_SUCCESS; - - // Detect WriteDisabled state - if (Instance->Media.ReadOnly == TRUE) - { - // Firmware volume is in WriteDisabled state - return EFI_ACCESS_DENIED; - } - - // Before erasing, check the entire list of parameters to ensure all specified blocks are valid - VA_START (Args, This); - do - { - // Get the Lba from which we start erasing - StartingLba = VA_ARG (Args, EFI_LBA); - - // Have we reached the end of the list? - if (StartingLba == EFI_LBA_LIST_TERMINATOR) - { - //Exit the while loop - break; - } - - // How many Lba blocks are we requested to erase? - NumOfLba = VA_ARG (Args, UINT32); - - // All blocks must be within range - if ((NumOfLba == 0) || ((Instance->StartLba + StartingLba + NumOfLba - 1) > Instance->Media.LastBlock)) - { - VA_END (Args); - Status = EFI_INVALID_PARAMETER; - goto EXIT; - } - } - while (TRUE); - VA_END (Args); - - // - // To get here, all must be ok, so start erasing - // - VA_START (Args, This); - do - { - // Get the Lba from which we start erasing - StartingLba = VA_ARG (Args, EFI_LBA); - - // Have we reached the end of the list? - if (StartingLba == EFI_LBA_LIST_TERMINATOR) - { - // Exit the while loop - break; - } - - // How many Lba blocks are we requested to erase? - NumOfLba = VA_ARG (Args, UINT32); - - // Go through each one and erase it - while (NumOfLba > 0) - { - - // Get the physical address of Lba to erase - BlockAddress = GET_BLOCK_ADDRESS ( - Instance->RegionBaseAddress, - Instance->StartLba + StartingLba, - Instance->Media.BlockSize - ); - - // Erase it - - Status = FlashUnlockAndEraseSingleBlock (Instance, BlockAddress); - if (EFI_ERROR(Status)) - { - VA_END (Args); - Status = EFI_DEVICE_ERROR; - goto EXIT; - } - - // Move to the next Lba - StartingLba++; - NumOfLba--; - } - } - while (TRUE); - VA_END (Args); - -EXIT: - return Status; -} - -EFI_STATUS -EFIAPI -FvbInitialize ( - IN FLASH_INSTANCE* Instance -) -{ - EFI_STATUS Status; - UINT32 FvbNumLba; - - Instance->Initialized = TRUE; - mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64); - - // Set the index of the first LBA for the FVB - Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) / Instance->Media.BlockSize; - - // Determine if there is a valid header at the beginning of the Flash - Status = ValidateFvHeader (Instance); - if (EFI_ERROR(Status)) - { - // There is no valid header, so time to install one. - // Erase all the Flash that is reserved for variable storage - FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + (UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize; - Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR); - if (EFI_ERROR(Status)) - { - return Status; - } - - // Install all appropriate headers - Status = InitializeFvAndVariableStoreHeaders (Instance); - if (EFI_ERROR(Status)) - { - return Status; - } - } - return Status; -} - - -EFI_STATUS -FlashPlatformGetDevices ( - OUT FLASH_DESCRIPTION** FlashDevices, - OUT UINT32* Count -) -{ - if ((FlashDevices == NULL) || (Count == NULL)) - { - return EFI_INVALID_PARAMETER; - } - - *FlashDevices = mFlashDevices; - *Count = FLASH_DEVICE_COUNT; - - return EFI_SUCCESS; -} - - -EFI_STATUS -FlashCreateInstance ( - IN UINTN FlashDeviceBase, - IN UINTN FlashRegionBase, - IN UINTN FlashSize, - IN UINT32 MediaId, - IN UINT32 BlockSize, - IN BOOLEAN SupportFvb, - IN CONST GUID* FlashGuid, - OUT FLASH_INSTANCE** FlashInstance -) -{ - EFI_STATUS Status; - FLASH_INSTANCE* Instance; - - if (FlashInstance == NULL) - { - return EFI_INVALID_PARAMETER; - } - - Instance = AllocateRuntimeCopyPool (sizeof(FLASH_INSTANCE), &mFlashInstanceTemplate); - if (Instance == NULL) - { - return EFI_INVALID_PARAMETER; - } - - Instance->DeviceBaseAddress = FlashDeviceBase; - Instance->RegionBaseAddress = FlashRegionBase; - Instance->Size = FlashSize; - - Instance->BlockIoProtocol.Media = &Instance->Media; - Instance->BlockIoProtocol.Reset = FvbReset; - Instance->Media.MediaId = MediaId; - Instance->Media.BlockSize = BlockSize; - Instance->Media.LastBlock = (FlashSize / BlockSize) - 1; - - CopyGuid (&Instance->DevicePath.Vendor.Guid, FlashGuid); - - if (SupportFvb) - { - Instance->SupportFvb = TRUE; - Instance->Initialize = FvbInitialize; - - Status = gBS->InstallMultipleProtocolInterfaces ( - &Instance->Handle, - &gEfiDevicePathProtocolGuid, &Instance->DevicePath, - &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, - &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol, - NULL - ); - - if (EFI_ERROR(Status)) - { - FreePool(Instance); - return Status; - } - } - else - { - Instance->Initialized = TRUE; - - Status = gBS->InstallMultipleProtocolInterfaces ( - &Instance->Handle, - &gEfiDevicePathProtocolGuid, &Instance->DevicePath, - &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, - NULL - ); - if (EFI_ERROR(Status)) - { - FreePool(Instance); - return Status; - } - } - - *FlashInstance = Instance; - return Status; -} - -EFI_STATUS -FlashUnlockSingleBlockIfNecessary ( - IN FLASH_INSTANCE* Instance, - IN UINTN BlockAddress -) -{ - return EFI_SUCCESS; -} - - -EFI_STATUS -FlashEraseSingleBlock ( - IN FLASH_INSTANCE* Instance, - IN UINTN BlockAddress -) -{ - EFI_STATUS Status; - UINTN EraseAddress; - - Status = EFI_SUCCESS; - EraseAddress = BlockAddress - Instance->DeviceBaseAddress; - - Status = mFlash->Erase(mFlash, (UINT32)EraseAddress, Instance->Media.BlockSize); - if (EFI_SUCCESS != Status) - { - DEBUG((DEBUG_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status)); - return Status; - } - - return EFI_SUCCESS; -} - -/** - * The following function presumes that the block has already been unlocked. - **/ -EFI_STATUS -FlashUnlockAndEraseSingleBlock ( - IN FLASH_INSTANCE* Instance, - IN UINTN BlockAddress -) -{ - EFI_STATUS Status; - UINTN Index; - - Index = 0; - // The block erase might fail a first time (SW bug ?). Retry it ... - do - { - // Unlock the block if we have to - Status = FlashUnlockSingleBlockIfNecessary (Instance, BlockAddress); - if (!EFI_ERROR(Status)) - { - Status = FlashEraseSingleBlock (Instance, BlockAddress); - } - Index++; - } - while ((Index < FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED)); - - if (Index == FLASH_ERASE_RETRY) - { - DEBUG((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress, Index)); - } - - return Status; -} - -EFI_STATUS -FlashWriteBlocks ( - IN FLASH_INSTANCE* Instance, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - IN VOID* Buffer -) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINTN BlockAddress; - UINT32 NumBlocks; - UINTN WriteAddress; - - // The buffer must be valid - if (Buffer == NULL) - { - return EFI_INVALID_PARAMETER; - } - - if (Instance->Media.ReadOnly == TRUE) - { - return EFI_WRITE_PROTECTED; - } - - // We must have some bytes to read - if (BufferSizeInBytes == 0) - { - return EFI_BAD_BUFFER_SIZE; - } - - // The size of the buffer must be a multiple of the block size - if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) - { - return EFI_BAD_BUFFER_SIZE; - } - - // All blocks must be within the device - NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ; - if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL]ERROR - Write will exceed last block.\n", __func__, __LINE__ )); - return EFI_INVALID_PARAMETER; - } - - BlockAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, Instance->Media.BlockSize); - - WriteAddress = BlockAddress - Instance->DeviceBaseAddress; - - Status = mFlash->Write(mFlash, (UINT32)WriteAddress, (UINT8*)Buffer, BufferSizeInBytes); - if (EFI_SUCCESS != Status) - { - DEBUG((DEBUG_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status)); - return Status; - } - - return Status; -} - -EFI_STATUS -FlashReadBlocks ( - IN FLASH_INSTANCE* Instance, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - OUT VOID* Buffer -) -{ - UINT32 NumBlocks; - UINTN StartAddress; - UINTN ReadAddress; - EFI_STATUS Status; - - // The buffer must be valid - if (Buffer == NULL) - { - return EFI_INVALID_PARAMETER; - } - - // We must have some bytes to read - if (BufferSizeInBytes == 0) - { - return EFI_BAD_BUFFER_SIZE; - } - - // The size of the buffer must be a multiple of the block size - if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) - { - return EFI_BAD_BUFFER_SIZE; - } - - // All blocks must be within the device - NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ; - if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) - { - DEBUG((DEBUG_ERROR, "FlashReadBlocks: ERROR - Read will exceed last block\n")); - return EFI_INVALID_PARAMETER; - } - - // Get the address to start reading from - StartAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, - Lba, - Instance->Media.BlockSize - ); - - - ReadAddress = StartAddress - Instance->DeviceBaseAddress; - - Status = mFlash->Read(mFlash, (UINT32)ReadAddress, Buffer, BufferSizeInBytes); - if (EFI_SUCCESS != Status) - { - DEBUG((DEBUG_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status)); - return Status; - } - - return EFI_SUCCESS; -} - -VOID -EFIAPI -FlashFvbVirtualNotifyEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EfiConvertPointer (0x0, (VOID**)&mFlash); - EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase); - return; -} - -EFI_STATUS -EFIAPI -FlashFvbInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE* SystemTable -) -{ - EFI_STATUS Status; - UINT32 Index; - FLASH_DESCRIPTION* FlashDevices; - UINT32 FlashDeviceCount; - BOOLEAN ContainVariableStorage; - - - Status = FlashPlatformGetDevices (&FlashDevices, &FlashDeviceCount); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Fail to get Flash devices\n", __func__, __LINE__)); - return Status; - } - - mFlashInstances = AllocatePool ((UINT32)(sizeof(FLASH_INSTANCE*) * FlashDeviceCount)); - - Status = gBS->LocateProtocol (&gHisiSpiFlashProtocolGuid, NULL, (VOID*) &mFlash); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Status=%r\n", __func__, __LINE__, Status)); - return Status; - } - - for (Index = 0; Index < FlashDeviceCount; Index++) - { - // Check if this Flash device contain the variable storage region - ContainVariableStorage = - (FlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) && - ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size); - - Status = FlashCreateInstance ( - FlashDevices[Index].DeviceBaseAddress, - FlashDevices[Index].RegionBaseAddress, - FlashDevices[Index].Size, - Index, - FlashDevices[Index].BlockSize, - ContainVariableStorage, - &FlashDevices[Index].Guid, - &mFlashInstances[Index] - ); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Fail to create instance for Flash[%d]\n", __func__, __LINE__, Index)); - } - } - // - // Register for the virtual address change event - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_NOTIFY, - FlashFvbVirtualNotifyEvent, - NULL, - &gEfiEventVirtualAddressChangeGuid, - &mFlashFvbVirtualAddrChangeEvent - ); - ASSERT_EFI_ERROR (Status); - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h deleted file mode 100644 index 47df349112f726e7a843028fcebd8b4d633a5872..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h +++ /dev/null @@ -1,222 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef __FLASH_FVB_DXE_H__ -#define __FLASH_FVB_DXE_H__ - - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - - -#define FLASH_ERASE_RETRY 10 -#define FLASH_DEVICE_COUNT 1 - -// Device access macros -// These are necessary because we use 2 x 16bit parts to make up 32bit data -typedef struct -{ - UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA) - UINTN RegionBaseAddress; // Start address of one single region - UINTN Size; - UINTN BlockSize; - EFI_GUID Guid; -} FLASH_DESCRIPTION; - -#define GET_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) ) - -#define FLASH_SIGNATURE SIGNATURE_32('s', 'p', 'i', '0') -#define INSTANCE_FROM_FVB_THIS(a) CR(a, FLASH_INSTANCE, FvbProtocol, FLASH_SIGNATURE) -#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, FLASH_INSTANCE, BlockIoProtocol, FLASH_SIGNATURE) - -typedef struct _FLASH_INSTANCE FLASH_INSTANCE; - -typedef EFI_STATUS (*FLASH_INITIALIZE) (FLASH_INSTANCE* Instance); - -typedef struct -{ - VENDOR_DEVICE_PATH Vendor; - EFI_DEVICE_PATH_PROTOCOL End; -} FLASH_DEVICE_PATH; - -struct _FLASH_INSTANCE -{ - UINT32 Signature; - EFI_HANDLE Handle; - - BOOLEAN Initialized; - FLASH_INITIALIZE Initialize; - - UINTN DeviceBaseAddress; - UINTN RegionBaseAddress; - UINTN Size; - EFI_LBA StartLba; - - EFI_BLOCK_IO_PROTOCOL BlockIoProtocol; - EFI_BLOCK_IO_MEDIA Media; - - BOOLEAN SupportFvb; - EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; - - FLASH_DEVICE_PATH DevicePath; -}; - - -// -// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks -// -EFI_STATUS -EFIAPI -FlashBlockIoReadBlocks ( - IN EFI_BLOCK_IO_PROTOCOL* This, - IN UINT32 MediaId, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - OUT VOID* Buffer -); - -// -// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks -// -EFI_STATUS -EFIAPI -FlashBlockIoWriteBlocks ( - IN EFI_BLOCK_IO_PROTOCOL* This, - IN UINT32 MediaId, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - IN VOID* Buffer -); - -// -// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks -// -EFI_STATUS -EFIAPI -FlashBlockIoFlushBlocks ( - IN EFI_BLOCK_IO_PROTOCOL* This -); - - -// -// FvbHw.c -// - -EFI_STATUS -EFIAPI -FvbInitialize ( - IN FLASH_INSTANCE* Instance -); - -EFI_STATUS -EFIAPI -FvbGetAttributes( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - OUT EFI_FVB_ATTRIBUTES_2* Attributes -); - -EFI_STATUS -EFIAPI -FvbSetAttributes( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN OUT EFI_FVB_ATTRIBUTES_2* Attributes -); - -EFI_STATUS -EFIAPI -FvbGetPhysicalAddress( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - OUT EFI_PHYSICAL_ADDRESS* Address -); - -EFI_STATUS -EFIAPI -FvbGetBlockSize( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN EFI_LBA Lba, - OUT UINTN* BlockSize, - OUT UINTN* NumberOfBlocks -); - -EFI_STATUS -EFIAPI -FvbRead( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN EFI_LBA Lba, - IN UINTN Offset, - IN OUT UINTN* NumBytes, - IN OUT UINT8* Buffer -); - -EFI_STATUS -EFIAPI -FvbWrite( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - IN EFI_LBA Lba, - IN UINTN Offset, - IN OUT UINTN* NumBytes, - IN UINT8* Buffer -); - -EFI_STATUS -EFIAPI -FvbEraseBlocks( - IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, - ... -); - -// -// FlashFvbDxe.c -// - -EFI_STATUS -FlashUnlockAndEraseSingleBlock ( - IN FLASH_INSTANCE* Instance, - IN UINTN BlockAddress -); - -EFI_STATUS -FlashWriteBlocks ( - IN FLASH_INSTANCE* Instance, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - IN VOID* Buffer -); - -EFI_STATUS -FlashReadBlocks ( - IN FLASH_INSTANCE* Instance, - IN EFI_LBA Lba, - IN UINTN BufferSizeInBytes, - OUT VOID* Buffer -); - -#endif diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf deleted file mode 100644 index 3600e101b6006556b4778ad016abe5cafc467da6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf +++ /dev/null @@ -1,65 +0,0 @@ -#/** @file -# -# Copyright (c) 2011-2015, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = FlashFvbDxe - FILE_GUID = 93E34C7E-B50E-11DF-9223-2443DFD72085 - MODULE_TYPE = DXE_RUNTIME_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = FlashFvbInitialize - -[Sources.common] - FlashFvbDxe.c - FlashBlockIoDxe.c - - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Platform/ARM/ARM.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - IoLib - BaseLib - DebugLib - HobLib - UefiLib - UefiDriverEntryPoint - UefiBootServicesTableLib - UefiRuntimeLib - -[Guids] - gEfiEventVirtualAddressChangeGuid - gEfiSystemNvDataFvGuid - gEfiVariableGuid - -[Protocols] - gEfiBlockIoProtocolGuid - gEfiDevicePathProtocolGuid - gEfiFirmwareVolumeBlockProtocolGuid - gHisiSpiFlashProtocolGuid - -[Pcd.common] - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - - gPlatformArmTokenSpaceGuid.PcdNorFlashCheckBlockLocked - gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress - -[Depex] - gHisiSpiFlashProtocolGuid - -[BuildOptions] diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c deleted file mode 100644 index 3c80ab57ef386ce378a829f8633b77b2c4113842..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c +++ /dev/null @@ -1,273 +0,0 @@ -/** @file - Sample ACPI Platform Driver - - Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include "UpdateAcpiTable.h" - -/** - Locate the first instance of a protocol. If the protocol requested is an - FV protocol, then it will return the first FV that contains the ACPI table - storage file. - - @param Instance Return pointer to the first instance of the protocol - - @return EFI_SUCCESS The function completed successfully. - @return EFI_NOT_FOUND The protocol could not be located. - @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. - -**/ -EFI_STATUS -LocateFvInstanceWithTables ( - OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance - ) -{ - EFI_STATUS Status; - EFI_HANDLE *HandleBuffer; - UINTN NumberOfHandles; - EFI_FV_FILETYPE FileType; - UINT32 FvStatus; - EFI_FV_FILE_ATTRIBUTES Attributes; - UINTN Size; - UINTN Index; - EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance; - - FvStatus = 0; - - // - // Locate protocol. - // - Status = gBS->LocateHandleBuffer ( - ByProtocol, - &gEfiFirmwareVolume2ProtocolGuid, - NULL, - &NumberOfHandles, - &HandleBuffer - ); - if (EFI_ERROR (Status)) { - // - // Defined errors at this time are not found and out of resources. - // - return Status; - } - - - - // - // Looking for FV with ACPI storage file - // - - for (Index = 0; Index < NumberOfHandles; Index++) { - // - // Get the protocol on this handle - // This should not fail because of LocateHandleBuffer - // - Status = gBS->HandleProtocol ( - HandleBuffer[Index], - &gEfiFirmwareVolume2ProtocolGuid, - (VOID**) &FvInstance - ); - ASSERT_EFI_ERROR (Status); - - // - // See if it has the ACPI storage file - // - Status = FvInstance->ReadFile ( - FvInstance, - (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile), - NULL, - &Size, - &FileType, - &Attributes, - &FvStatus - ); - - // - // If we found it, then we are done - // - if (Status == EFI_SUCCESS) { - *Instance = FvInstance; - break; - } - } - - // - // Our exit status is determined by the success of the previous operations - // If the protocol was found, Instance already points to it. - // - - // - // Free any allocated buffers - // - gBS->FreePool (HandleBuffer); - - return Status; -} - - -/** - This function calculates and updates an UINT8 checksum. - - @param Buffer Pointer to buffer to checksum - @param Size Number of bytes to checksum - -**/ -VOID -AcpiPlatformChecksum ( - IN UINT8 *Buffer, - IN UINTN Size - ) -{ - UINTN ChecksumOffset; - - ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); - - // - // Set checksum to 0 first - // - Buffer[ChecksumOffset] = 0; - - // - // Update checksum value - // - Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); -} - - -/** - Entrypoint of Acpi Platform driver. - - @param ImageHandle - @param SystemTable - - @return EFI_SUCCESS - @return EFI_LOAD_ERROR - @return EFI_OUT_OF_RESOURCES - -**/ -EFI_STATUS -EFIAPI -AcpiPlatformEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_ACPI_TABLE_PROTOCOL *AcpiTable; - EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; - INTN Instance; - EFI_ACPI_COMMON_HEADER *CurrentTable; - UINTN TableHandle; - UINT32 FvStatus; - UINTN TableSize; - UINTN Size; - EFI_STATUS TableStatus; - EFI_ACPI_DESCRIPTION_HEADER *TableHeader; - - Instance = 0; - CurrentTable = NULL; - TableHandle = 0; - - // - // Find the AcpiTable protocol - // - Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable); - if (EFI_ERROR (Status)) { - return EFI_ABORTED; - } - - // - // Locate the firmware volume protocol - // - Status = LocateFvInstanceWithTables (&FwVol); - if (EFI_ERROR (Status)) { - return EFI_ABORTED; - } - // - // Read tables from the storage file. - // - while (Status == EFI_SUCCESS) { - - Status = FwVol->ReadSection ( - FwVol, - (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile), - EFI_SECTION_RAW, - Instance, - (VOID**) &CurrentTable, - &Size, - &FvStatus - ); - if (!EFI_ERROR(Status)) { - // - // Add the table - // - TableHeader = (EFI_ACPI_DESCRIPTION_HEADER*) (CurrentTable); - //Update specfic Acpi Table - //If the Table is updated failed, doesn't install it, - //go to find next section. - TableStatus = UpdateAcpiTable(TableHeader); - if (TableStatus == EFI_SUCCESS) { - TableHandle = 0; - - TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; - ASSERT (Size >= TableSize); - - // - // Checksum ACPI table - // - AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize); - - // - // Install ACPI table - // - Status = AcpiTable->InstallAcpiTable ( - AcpiTable, - CurrentTable, - TableSize, - &TableHandle - ); - } - // - // Free memory allocated by ReadSection - // - gBS->FreePool (CurrentTable); - - if (EFI_ERROR(Status)) { - return EFI_ABORTED; - } - - // - // Increment the instance - // - Instance++; - CurrentTable = NULL; - } - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gHisiInstalledAcpiProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Install protocol %r\n", Status)); - } - - return Status; -} - diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni deleted file mode 100644 index 668e5dbfd158caa696ffd1ddb5a57e368a4de94f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni +++ /dev/null @@ -1,16 +0,0 @@ -// /** @file -// Sample ACPI Platform Driver -// -// Sample ACPI Platform Driver -// -// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// **/ - - -#string STR_MODULE_ABSTRACT #language en-US "Sample ACPI Platform Driver" - -#string STR_MODULE_DESCRIPTION #language en-US "Sample ACPI Platform Driver" - diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf deleted file mode 100644 index a5812fc7ac6b1ddf2492245a268511593f6a1702..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf +++ /dev/null @@ -1,58 +0,0 @@ -## @file -# Sample ACPI Platform Driver -# -# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AcpiPlatform - MODULE_UNI_FILE = AcpiPlatform.uni - FILE_GUID = cb933912-df8f-4305-b1f9-7b44fa11395c - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = AcpiPlatformEntryPoint - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = IA32 X64 IPF EBC -# - -[Sources] - AcpiPlatform.c - UpdateAcpiTable.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiLib - DxeServicesLib - PcdLib - BaseMemoryLib - DebugLib - HobLib - UefiBootServicesTableLib - UefiDriverEntryPoint - -[Protocols] - gEfiAcpiTableProtocolGuid ## CONSUMES - gHisiInstalledAcpiProtocolGuid ## CONSUMES - -[Guids] - gHisiEfiMemoryMapGuid - gOemConfigGuid - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES - -[Depex] - gEfiAcpiTableProtocolGuid AND gEfiVariableWriteArchProtocolGuid - -[UserExtensions.TianoCore."ExtraFiles"] - AcpiPlatformExtra.uni diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni deleted file mode 100644 index 7a60a8434d909583f62da5e4bbc0ac899c944766..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni +++ /dev/null @@ -1,14 +0,0 @@ -// /** @file -// AcpiPlatform Localized Strings and Content -// -// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// **/ - -#string STR_PROPERTIES_MODULE_NAME -#language en-US -"ACPI Platform Sample DXE Driver" - - diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c deleted file mode 100644 index 72fcf741582a6997789fec48a08895ade0bfb10c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c +++ /dev/null @@ -1,218 +0,0 @@ -/** @file - Copyright (c) 2016, Hisilicon Limited. All rights reserved. - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET) - -#define FIELD_IORT_NODE_OFFSET 40 - -typedef enum { - NodeTypeIts = 0, - NodeTypeNameComponent, - NodeTypePciRC, - NodeTypeSmmuV1, - NodeTypeSmmuV3, - NodeTypePMCG -} IORT_NODE_TYPE; - -#pragma pack(1) -typedef struct { - UINT8 Type; - UINT16 Length; - UINT8 Revision; - UINT32 Reserved; - UINT32 IdMapNumber; - UINT32 IdArrayOffset; -} IORT_NODE_HEAD; -#pragma pack() - -BOOLEAN -IsIortWithSmmu ( - IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader - ) -{ - UINT32 *NodeOffset; - UINT32 NextOffset; - IORT_NODE_HEAD *Node; - - NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET); - NextOffset = *NodeOffset; - - while (NextOffset < TableHeader->Length) { - Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset); - NextOffset += Node->Length; - - if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) { - return TRUE; - } - } - - return FALSE; -} - -EFI_STATUS -SelectIort ( - IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader - ) -{ - EFI_STATUS Status; - UINTN Size; - OEM_CONFIG_DATA Configuration; - - Configuration.EnableSmmu = 0; - Size = sizeof (OEM_CONFIG_DATA); - Status = gRT->GetVariable ( - OEM_CONFIG_NAME, - &gOemConfigGuid, - NULL, - &Size, - &Configuration - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get OemConfig variable (%r).\n", Status)); - } - - Status = EFI_SUCCESS; - if (IsIortWithSmmu (TableHeader)) { - if (!Configuration.EnableSmmu) { - Status = EFI_ABORTED; - } - } else { - if (Configuration.EnableSmmu) { - Status = EFI_ABORTED; - } - } - DEBUG ((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n", - Configuration.EnableSmmu, Status)); - - return Status; -} - -STATIC -VOID -RemoveUnusedMemoryNode ( - IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table, - IN UINTN MemoryNodeNum -) -{ - UINTN CurrPtr, NewPtr; - - if (MemoryNodeNum >= EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT) { - return; - } - - CurrPtr = (UINTN) &(Table->Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]); - NewPtr = (UINTN) &(Table->Memory[MemoryNodeNum]); - - CopyMem ((VOID *)NewPtr, (VOID *)CurrPtr, (UINTN)Table + Table->Header.Header.Length - CurrPtr); - - Table->Header.Header.Length -= CurrPtr - NewPtr; - - return; -} - -STATIC -EFI_STATUS -UpdateSrat ( - IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table - ) -{ - UINT8 Skt = 0; - UINTN Index = 0; - VOID *HobList; - GBL_INTERFACE *Gbl_Data; - UINTN Base; - UINTN Size; - UINT8 NodeId; - UINT32 ScclInterleaveEn; - UINTN MemoryNode = 0; - - DEBUG((DEBUG_INFO, "SRAT: Updating SRAT memory information.\n")); - - HobList = GetHobList(); - if (HobList == NULL) { - return EFI_UNSUPPORTED; - } - Gbl_Data = (GBL_INTERFACE*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList); - if (Gbl_Data == NULL) { - DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n")); - return EFI_NOT_FOUND; - } - Gbl_Data = GET_GUID_HOB_DATA(Gbl_Data); - for(Skt = 0; Skt < MAX_SOCKET; Skt++) { - for(Index = 0; Index < MAX_NUM_PER_TYPE; Index++) { - NodeId = Gbl_Data->NumaInfo[Skt][Index].NodeId; - Base = Gbl_Data->NumaInfo[Skt][Index].Base; - Size = Gbl_Data->NumaInfo[Skt][Index].Length; - DEBUG((DEBUG_INFO, "Skt %d Index %d: NodeId = %d, Base = 0x%lx, Size = 0x%lx\n", Skt, Index, NodeId, Base, Size)); - if (Size > 0) { - Table->Memory[MemoryNode].ProximityDomain = NodeId; - Table->Memory[MemoryNode].AddressBaseLow = Base; - Table->Memory[MemoryNode].AddressBaseHigh = Base >> 32; - Table->Memory[MemoryNode].LengthLow = Size; - Table->Memory[MemoryNode].LengthHigh = Size >> 32; - MemoryNode = MemoryNode + 1; - } - } - ScclInterleaveEn = Gbl_Data->NumaInfo[Skt][0].ScclInterleaveEn; - DEBUG((DEBUG_INFO, "ScclInterleaveEn = %d\n", ScclInterleaveEn)); - //update gicc structure - if (ScclInterleaveEn != 0) { - DEBUG((DEBUG_INFO, "SRAT: Updating SRAT Gicc information.\n")); - for (Index = CORECOUNT (Skt); Index < CORECOUNT (Skt + 1); Index++) { - Table->Gicc[Index].ProximityDomain = Skt * NODE_IN_SOCKET; - } - } - } - - //remove invalid memory node - RemoveUnusedMemoryNode (Table, MemoryNode); - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -UpdateSlit ( - IN OUT EFI_ACPI_DESCRIPTION_HEADER *Table - ) -{ - return EFI_SUCCESS; -} - -EFI_STATUS -UpdateAcpiTable ( - IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader -) -{ - EFI_STATUS Status = EFI_SUCCESS; - - switch (TableHeader->Signature) { - - case EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE: - Status = UpdateSrat ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) TableHeader); - break; - - case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: - Status = UpdateSlit (TableHeader); - break; - case EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE: - Status = SelectIort (TableHeader); - break; - } - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h deleted file mode 100644 index ef515a78b0b6b7a66842064ae483a954bfd8ec0b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h +++ /dev/null @@ -1,10 +0,0 @@ -/** @file - Copyright (c) 2016, Hisilicon Limited. All rights reserved. - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -EFI_STATUS -UpdateAcpiTable ( - IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader -); - diff --git a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c b/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c deleted file mode 100644 index bbcbe95ab053d7684e4b908504c03709224214f2..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c +++ /dev/null @@ -1,156 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include "NorFlashHw.h" - - -#define COMMAND_TYPE1 0x1 -#define COMMAND_TYPE2 0x2 -#define COMMAND_TYPE3 0x4 -#define COMMAND_TYPE4 0x8 -#define COMMAND_TYPE5 0x10 - - -NOR_FLASH_INFO_TABLE gFlashInfo[]= -{ - - {//S29GL512m - 0x00010001, - 0x227E227E, - 0x22232223, - 0x22012201, - 1, - 0x20000000, - 0x20000, - 0x0010, - COMMAND_TYPE1 - }, - {//S29GL1g - 0x00010001, - 0x227E227E, - 0x22282228, - 0x22012201, - 1, - 0x40000000, - 0x20000, - 0x0020, - COMMAND_TYPE1 - }, - {//M29ew512m - 0x00890089, - 0x227E227E, - 0x22232223, - 0x22012201, - 1, - 0x20000000, - 0x20000, - 0x0010, - COMMAND_TYPE1 - }, - {//M29EW2g - 0x00890089, - 0x227E227E, - 0x22482248, - 0x22012201, - 1, - 0x80000000, - 0x20000, - 0x0020, - COMMAND_TYPE1 - }, - { - 0x00890089, - 0x227E227E, - 0x22282228, - 0x22012201, - 1, - 0x10000000, - 0x20000, - 0x0020, - COMMAND_TYPE1 - }, - { - 0x00890089, - 0x227E227E, - 0x22282228, - 0x22012201, - 2, - 0x10000000, - 0x20000, - 0x0020, - COMMAND_TYPE1 - } -}; - - - -FLASH_COMMAND_RESET gFlashCommandReset[]= -{ - { - COMMAND_TYPE1, - (0x00F000F0) - } - -}; - - -FLASH_COMMAND_ID gFlashCommandId[]= -{ - { - COMMAND_TYPE1, - (0x0555), - (0x00AA00AA), - (0x02AA), - (0x00550055), - (0x0555), - (0x00900090), - (0x0000), - - (0x0001), - (0x000E), - (0x000F) - } -}; - - -FLASH_COMMAND_WRITE gFlashCommandWrite[]= -{ - { - COMMAND_TYPE1, - (0x0555), - (0x00AA00AA), - (0x02AA), - (0x00550055), - (0x00250025), - (0x00290029) - } - -}; - - -FLASH_COMMAND_ERASE gFlashCommandErase[]= -{ - { - COMMAND_TYPE1, - (0x0555), - (0x00AA00AA), - (0x02AA), - (0x00550055), - (0x0555), - (0x00800080), - (0x0555), - (0x00AA00AA), - (0x02AA), - (0x00550055), - (0x00300030) - } - -}; - diff --git a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c b/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c deleted file mode 100644 index 6eaf3e3387a7f17c2358582c0aba8cf01a8be93a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c +++ /dev/null @@ -1,588 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include "NorFlashHw.h" - - -EFI_STATUS Erase( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT32 Length - ); - -EFI_STATUS Write( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT8 *Buffer, - UINT32 ulLength - ); - -EFI_STATUS Read( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN OUT UINT8 *Buffer, - IN UINT32 ulLen - ); - -UNI_NOR_FLASH_PROTOCOL gUniNorFlash = { - Erase, - Write, - Read -}; - - -EFI_STATUS -EFIAPI Read( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN OUT UINT8 *Buffer, - IN UINT32 ulLen - ) -{ - UINT32 index; - UINT64 ullAddr; - UINT32 ullCnt = 0; - UINT32 *puiBuffer32 = NULL; - UINT32 *puiDst32 = NULL; - UINT8 *pucBuffer8 = NULL; - UINT8 *pucDst8 = NULL; - - if (Offset + ulLen > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Exceed the flash scope!\n", __func__,__LINE__)); - return EFI_INVALID_PARAMETER; - } - if (0 == ulLen) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Length is Zero!\n", __func__,__LINE__)); - return EFI_INVALID_PARAMETER; - } - if (NULL == Buffer) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Buffer is NULL!\n", __func__,__LINE__)); - return EFI_BAD_BUFFER_SIZE; - } - - - ullAddr = gIndex.Base + Offset; - - pucBuffer8 = (UINT8 *)Buffer; - pucDst8 = (UINT8 *)((UINTN)ullAddr); - - - if (ulLen < FOUR_BYTE_UNIT) - { - for(index = 0; index< ulLen; index++) - { - *pucBuffer8++ = *pucDst8++; - } - } - else - { - - ullCnt = Offset % FOUR_BYTE_UNIT; - ullCnt = FOUR_BYTE_UNIT - ullCnt; - - for(index = 0; index < ullCnt; index++) - { - *pucBuffer8++ = *pucDst8++; - } - - ulLen -= ullCnt; - - puiBuffer32 = (UINT32 *)pucBuffer8; - puiDst32 = (UINT32 *)pucDst8; - ullCnt = ulLen / FOUR_BYTE_UNIT; - - for(index = 0; index < ullCnt; index++) - { - *puiBuffer32++ = *puiDst32++; - } - - ullCnt = ulLen % FOUR_BYTE_UNIT; - pucBuffer8 = (UINT8 *)puiBuffer32; - pucDst8 = (UINT8 *)puiDst32; - - for(index = 0; index < ullCnt; index++) - { - *pucBuffer8++ = *pucDst8++; - } - } - - return EFI_SUCCESS; -} - - - -static EFI_STATUS WriteAfterErase_Fill( - IN const UINT32 Offset, - IN const UINT8 *Buffer, - IN const UINT32 Length - ) -{ - EFI_STATUS Status; - UINT32 Loop; - UINT32 DataOffset; - UINT32 NewOffset; - UINT8 *NewDataUnit; - - UINT32 FlashUnitLength; - - FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum; - - if (0 == Length) - { - return EFI_SUCCESS; - } - if ((Offset % FlashUnitLength + Length) > FlashUnitLength) - { - DEBUG ((DEBUG_INFO, "[%a]:[%dL]:Exceed the Flash Size!\n", __func__,__LINE__)); - return EFI_UNSUPPORTED; - } - - - Status = gBS->AllocatePool(EfiBootServicesData, FlashUnitLength, (VOID *)&NewDataUnit); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Allocate Pool failed, %r!\n", __func__,__LINE__, Status)); - return Status; - } - - - NewOffset = Offset - (Offset % FlashUnitLength); - - gBS->CopyMem((VOID *)NewDataUnit, (VOID *)(UINTN)(gIndex.Base + NewOffset), FlashUnitLength); - - DataOffset = Offset % FlashUnitLength; - for (Loop = 0; Loop < Length; Loop ++) - { - NewDataUnit[(UINT32)(DataOffset + Loop)] = Buffer[Loop]; - } - - Status = BufferWrite(NewOffset, (void *)NewDataUnit, FlashUnitLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:BufferWrite %r!\n", __func__,__LINE__, Status)); - return Status; - } - - (void)gBS->FreePool((VOID *)NewDataUnit); - return Status; -} - - -static EFI_STATUS WriteAfterErase_Final( - IN UINT32 Offset, - IN UINT8 *Buffer, - IN UINT32 Length - ) -{ - EFI_STATUS Status; - UINT32 Loop; - UINT32 FlashUnitLength; - - FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum; - - if (0 == Length) - { - return EFI_SUCCESS; - } - - if (0 != (Offset % FlashUnitLength)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: Offset must be a multiple of 0x%x!\n", __func__,__LINE__,FlashUnitLength)); - return EFI_UNSUPPORTED; - } - - - Loop = Length / FlashUnitLength; - while (Loop --) - { - Status = BufferWrite(Offset, (void *)Buffer, FlashUnitLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:BufferWrite Failed: %r!\n", __func__,__LINE__, Status)); - return EFI_DEVICE_ERROR; - } - Offset += FlashUnitLength; - Buffer += FlashUnitLength; - } - - - Length = Length % FlashUnitLength; - if (Length) - { - Status = WriteAfterErase_Fill(Offset, Buffer, Length); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:WriteAfterErase_Fill failed,%r!\n", __func__,__LINE__, Status)); - return Status; - } - } - - return EFI_SUCCESS; -} - -EFI_STATUS -WriteAfterErase( - UINT32 TempBase, - UINT32 Offset, - UINT8 *Buffer, - UINT32 Length - ) -{ - EFI_STATUS Status; - UINT32 FlashUnitLength; - - FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum; - - if (0 == Length) - { - return EFI_SUCCESS; - } - - - if (Offset % FlashUnitLength) - { - UINT32 TempLength; - - - TempLength = FlashUnitLength - (Offset % FlashUnitLength); - if (TempLength > Length) - { - TempLength = Length; - } - Status = WriteAfterErase_Fill(Offset, Buffer, TempLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %r!\n", __func__,__LINE__, Status)); - return Status; - } - - Offset += TempLength; - Length -= TempLength; - Buffer += TempLength; - - //Desc:if Offset >= gOneFlashSize,modify base - if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize)) - { - TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize; - gIndex.Base = TempBase; - Offset = 0; - } - } - - - Status = WriteAfterErase_Final(Offset, Buffer, Length); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %r!\n", __func__,__LINE__, Status)); - return Status; - } - - return EFI_SUCCESS; -} - - -EFI_STATUS -FlashSectorErase( - UINT32 TempBase, - UINT32 Offset, - UINT32 Length - ) -{ - EFI_STATUS Status; - UINT32 SectorOffset; - UINT8 *StaticBuffer; - UINT8 *Buffer; - UINT32 TempOffset; - UINT32 TempLength; - UINT32 LeftLength; - - - if (0 == Length) - { - return EFI_SUCCESS; - } - - LeftLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)); - if (LeftLength < Length) - { - return EFI_UNSUPPORTED; - } - - - SectorOffset = Offset - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)); - - Status = gBS->AllocatePool(EfiBootServicesData, gFlashInfo[gIndex.InfIndex].BlockSize * (UINTN)gFlashInfo[gIndex.InfIndex].ParallelNum, (VOID *)&StaticBuffer); - if (EFI_ERROR(Status)) - { - return Status; - } - - Buffer = StaticBuffer; - - gBS->CopyMem((VOID *)Buffer, (VOID *)(UINTN)(TempBase + SectorOffset), - (gFlashInfo[gIndex.InfIndex].BlockSize * (UINTN)gFlashInfo[gIndex.InfIndex].ParallelNum)); - - - Status = SectorErase(TempBase, SectorOffset); - if (EFI_ERROR(Status)) - { - goto DO; - } - - - TempOffset = SectorOffset; - TempLength = Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum); - - Status = WriteAfterErase(TempBase, TempOffset, Buffer, TempLength); - if (EFI_ERROR(Status)) - { - goto DO; - } - - - Buffer = Buffer + TempLength + Length; - TempOffset = Offset + Length; - TempLength = SectorOffset + (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum) - TempOffset; - - Status = WriteAfterErase(TempBase, TempOffset, Buffer, TempLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %r!\n", __func__,__LINE__,Status)); - goto DO; - } - - (void)gBS->FreePool((VOID *)StaticBuffer); - return EFI_SUCCESS; - -DO: - (void)gBS->FreePool((VOID *)StaticBuffer); - return Status; -} - - -EFI_STATUS -EFIAPI Erase( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT32 Length - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINT32 Sectors; - UINT32 TempLength; - UINT32 TempBase; - UINT32 Loop; - - - if (Offset + Length > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Exceed the Flash Size!\n", __func__,__LINE__)); - return EFI_ABORTED; - } - if (0 == Length) - { - return EFI_SUCCESS; - } - - - Sectors = ((Offset + Length - 1) / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - (Offset / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) + 1; - TempBase = gIndex.Base; - - //if Offset >= gOneFlashSize,modify base - if(0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize)) - { - TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize * (Offset/gFlashInfo[gIndex.InfIndex].SingleChipSize); - Offset = Offset - (Offset & gFlashInfo[gIndex.InfIndex].SingleChipSize); - } - - for (Loop = 0; Loop <= Sectors; Loop ++) - { - - TempLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)); - - - if (TempLength > Length) - { - TempLength = Length; - } - - Status = FlashSectorErase(TempBase, Offset, TempLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: FlashErase One Sector Error, Status = %r!\n", __func__,__LINE__,Status)); - return Status; - } - - Offset += TempLength; - - //if Offset >= gOneFlashSize,modify base - if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize)) - { - TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize; - Offset = 0; - } - Length -= TempLength; - } - - return Status; -} - - -EFI_STATUS -EFIAPI Write( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT8 *Buffer, - UINT32 ulLength - ) -{ - EFI_STATUS Status; - UINT32 TempLength; - UINT32 TempBase; - UINT32 Loop; - UINT32 Sectors; - - if((Offset + ulLength) > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Exceed the Flash Size!\n", __func__,__LINE__)); - return EFI_INVALID_PARAMETER; - } - if (0 == ulLength) - { - return EFI_SUCCESS; - } - - - Sectors = ((Offset + ulLength - 1) / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - (Offset / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) + 1; - TempBase = gIndex.Base; - - //if Offset >= gOneFlashSize,modify base - if(0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize)) - { - TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize * (Offset/gFlashInfo[gIndex.InfIndex].SingleChipSize); - Offset = Offset - (Offset & gFlashInfo[gIndex.InfIndex].SingleChipSize); - } - - for (Loop = 0; Loop <= Sectors; Loop ++) - { - - TempLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)); - - - if (TempLength > ulLength) - { - TempLength = ulLength; - } - - - if (TRUE == IsNeedToWrite(TempBase, Offset, Buffer, TempLength)) - { - Status = FlashSectorErase(TempBase, Offset, TempLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:FlashErase One Sector Error, Status = %r!\n", __func__,__LINE__,Status)); - return Status; - } - - - Status = WriteAfterErase(TempBase, Offset, Buffer, TempLength); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:WriteAfterErase Status = %r!\n", __func__,__LINE__,Status)); - return Status; - } - } - - Offset += TempLength; - Buffer += TempLength; - - //if Offset >= gOneFlashSize,modify base - if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize)) - { - TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize; - Offset = 0; - } - ulLength -= TempLength; - } - - return EFI_SUCCESS; -} - - -VOID SetFlashAttributeToUncache(VOID) -{ - EFI_CPU_ARCH_PROTOCOL *gCpu = NULL; - EFI_STATUS Status; - - Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "LocateProtocol gEfiCpuArchProtocolGuid Status = %r !\n", Status)); - } - - Status = gCpu->SetMemoryAttributes( - gCpu, - PcdGet64(PcdNORFlashBase), - PcdGet32(PcdNORFlashCachableSize), - EFI_MEMORY_UC - ); - - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "gCpu->SetMemoryAttributes Status = %r !\n", Status)); - } - -} - -EFI_STATUS -EFIAPI InitializeFlash ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable) -{ - EFI_STATUS Status; - - - gIndex.Base = (UINT32)PcdGet64(PcdNORFlashBase); - - SetFlashAttributeToUncache(); - Status = FlashInit(gIndex.Base); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Init Flash Error !\n")); - return Status; - } - else - { - DEBUG((DEBUG_ERROR, "Init Flash OK!\n")); - } - - Status = gBS->InstallProtocolInterface ( - &ImageHandle, - &gUniNorFlashProtocolGuid, - EFI_NATIVE_INTERFACE, - &gUniNorFlash); - if(EFI_SUCCESS != Status) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Install Protocol Interface %r!\n", __func__,__LINE__,Status)); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf b/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf deleted file mode 100644 index e64c2e597ec71dd7c514eb0de2442f5f6cef7123..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf +++ /dev/null @@ -1,58 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = NorFlashDxe - FILE_GUID = E29977F9-20A4-4551-B0EC-BCE246592E73 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = InitializeFlash - -[Sources.common] - NorFlashDxe.c - NorFlashHw.c - NorFlashConfig.c - -[Packages] - ArmPlatformPkg/ArmPlatformPkg.dec - MdePkg/MdePkg.dec - ArmPkg/ArmPkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiBootServicesTableLib - UefiDriverEntryPoint - DebugLib - BaseLib - DebugLib - IoLib - SerialPortLib - ArmLib - CacheMaintenanceLib - UefiLib - PrintLib - PcdLib - - DxeServicesTableLib -[Guids] - -[Protocols] - gUniNorFlashProtocolGuid - gEfiCpuArchProtocolGuid - -[Pcd] - gHisiTokenSpaceGuid.PcdNORFlashBase - gHisiTokenSpaceGuid.PcdNORFlashCachableSize - - -[Depex] - TRUE - diff --git a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c b/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c deleted file mode 100644 index f30f5cf39c015231ba4b63d8a488c9fa2b556672..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c +++ /dev/null @@ -1,622 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include "NorFlashHw.h" - - -BOOLEAN gFlashBusy = FALSE; -FLASH_INDEX gIndex = { - 0, - 0, - 0, - 0, - 0, - 0 -}; - - -UINT32 PortReadData ( - UINT32 Index, - UINT32 FlashAddr - ) -{ - - switch (gFlashInfo[Index].ParallelNum) - { - case 2: - return MmioRead32 (FlashAddr); - case 1: - return MmioRead16 (FlashAddr); - - default: - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:illegal PortWidth!\n", __func__,__LINE__)); - return 0xffffffff; - } -} - -EFI_STATUS -PortWriteData ( - UINT32 Index, - UINT32 FlashAddr, - UINT32 InputData - ) -{ - - switch (gFlashInfo[Index].ParallelNum) - { - case 2: - MmioWrite32 (FlashAddr, InputData); - break; - case 1: - MmioWrite16 (FlashAddr, InputData); - break; - default: - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:illegal PortWidth!\n", __func__,__LINE__)); - return EFI_DEVICE_ERROR; - } - return EFI_SUCCESS; -} - -UINT32 PortAdjustData( - UINT32 Index, - UINT32 ulInputData - ) -{ - - switch (gFlashInfo[Index].ParallelNum) - { - case 2: - return ulInputData; - case 1: - return (0x0000ffff & ulInputData ); - default: - DEBUG((DEBUG_ERROR,"[FLASH_S29GL256N_PortAdjustData]: Error--illegal g_ulFlashS29Gl256NPortWidth!\n\r")); - return 0xffffffff; - } -} - - -EFI_STATUS GetCommandIndex( - UINT32 Index - ) -{ - UINT32 CommandCount = 0; - UINT32 i; - UINT8 Flag = 1; - - CommandCount = sizeof(gFlashCommandReset) / sizeof(FLASH_COMMAND_RESET); - for(i = 0;i < CommandCount; i ++ ) - { - if(gFlashInfo[Index].CommandType & gFlashCommandReset[i].CommandType) - { - Flag = 0; - gIndex.ReIndex = i; - break; - } - } - - if(Flag) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Can not Get Reset Command!\n", __func__,__LINE__)); - return EFI_DEVICE_ERROR; - } - - CommandCount = sizeof(gFlashCommandId) / sizeof(FLASH_COMMAND_ID); - for(Flag = 1,i = 0;i < CommandCount; i ++ ) - { - if(gFlashInfo[Index].CommandType & gFlashCommandId[i].CommandType) - { - Flag = 0; - gIndex.IdIndex = i; - break; - } - } - - if(Flag) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Can not Get ID Command!\n", __func__,__LINE__)); - return EFI_DEVICE_ERROR; - } - - CommandCount = sizeof(gFlashCommandWrite) / sizeof(FLASH_COMMAND_WRITE); - for(Flag = 1, i = 0;i < CommandCount; i ++ ) - { - if(gFlashInfo[Index].CommandType & gFlashCommandWrite[i].CommandType) - { - Flag = 0; - gIndex.WIndex = i; - break; - } - } - - if(Flag) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Can not Get Write Command!\n", __func__,__LINE__)); - return EFI_DEVICE_ERROR; - } - - CommandCount = sizeof(gFlashCommandErase) / sizeof(FLASH_COMMAND_ERASE); - for(Flag = 1, i = 0;i < CommandCount; i ++ ) - { - if(gFlashInfo[Index].CommandType & gFlashCommandErase[i].CommandType) - { - Flag = 0; - gIndex.WIndex = i; - break; - } - } - - if(Flag) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Can not Get Erase Command!\n", __func__,__LINE__)); - return EFI_DEVICE_ERROR; - } - - return EFI_SUCCESS; -} - - -VOID FlashReset(UINT32 Base) -{ - (VOID)PortWriteData(gIndex.InfIndex, Base, gFlashCommandReset[gIndex.ReIndex].ResetData); - (void)gBS->Stall(20000); -} - - -void GetManufacturerID(UINT32 Index, UINT32 Base, UINT8 *pbyData) -{ - - UINT32 dwAddr; - - FlashReset(Base); - - dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep1 << gFlashInfo[Index].ParallelNum); - (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep1); - - dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep2 << gFlashInfo[Index].ParallelNum); - (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep2); - - dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep3 << gFlashInfo[Index].ParallelNum); - (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep3); - - *pbyData = (UINT8)PortReadData(Index, Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddress << gFlashInfo[Index].ParallelNum)); - - FlashReset(Base); //must reset to return to the read mode -} - - -EFI_STATUS FlashInit(UINT32 Base) -{ - UINT32 FlashCount = 0; - UINT32 i = 0; - EFI_STATUS Status; - UINT8 Flag = 1; - UINT32 TempData = 0; - UINT32 TempDev1 = 0; - UINT32 TempDev2 = 0; - UINT32 TempDev3 = 0; - UINT32 dwAddr; - - FlashCount = sizeof(gFlashInfo) / sizeof(NOR_FLASH_INFO_TABLE); - for(;i < FlashCount; i ++ ) - { - - Status = GetCommandIndex(i); - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Get Command Index %r!\n", __func__,__LINE__, Status)); - return Status; - } - - FlashReset(Base); - - dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep1 << gFlashInfo[i].ParallelNum); - (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep1); - - dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep2 << gFlashInfo[i].ParallelNum); - (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep2); - - dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep3 << gFlashInfo[i].ParallelNum); - (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep3); - //Get manufacture ID - TempData = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddress << gFlashInfo[i].ParallelNum)); - - //Get Device Id - TempDev1 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress1 << gFlashInfo[i].ParallelNum)); - TempDev2 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress2 << gFlashInfo[i].ParallelNum)); - TempDev3 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress3 << gFlashInfo[i].ParallelNum)); - DEBUG ((DEBUG_ERROR, "[cdtest]manufactor ID 0x%x!\n",TempData)); - DEBUG ((DEBUG_ERROR, "[cdtest]Device ID 1 0x%x!\n",TempDev1)); - DEBUG ((DEBUG_ERROR, "[cdtest]Device ID 2 0x%x!\n",TempDev2)); - DEBUG ((DEBUG_ERROR, "[cdtest]Device ID 3 0x%x!\n",TempDev3)); - - FlashReset(Base); - - - if((0xffffffff != TempData) - && (PortAdjustData(i, gFlashInfo[i].ManufacturerID) == TempData)) - { - if((0xffffffff != TempDev1) - && (PortAdjustData(i, gFlashInfo[i].DeviceID1) == TempDev1)) - { - if((0xffffffff != TempDev2) - && (PortAdjustData(i, gFlashInfo[i].DeviceID2) == TempDev2)) - { - if((0xffffffff != TempDev3) - && (PortAdjustData(i, gFlashInfo[i].DeviceID3) == TempDev3)) - { - Flag = 0; - gIndex.InfIndex = i; - break; - } - } - } - } - } - - if(Flag) - { - return EFI_DEVICE_ERROR; - } - - return EFI_SUCCESS; -} - - -static BOOLEAN width8IsAll( - const UINT64 Base, - const UINT64 Offset, - const UINT64 Length, - const UINT8 Value -) -{ - UINT64 NewAddr = Base + Offset; - UINT64 NewLength = Length; - while (NewLength --) - { - if (*(UINT8 *)(UINTN)NewAddr == Value) - { - NewAddr ++; - continue; - } - else - { - return FALSE; - } - } - return TRUE; -} - - - -EFI_STATUS BufferWriteCommand(UINTN Base, UINTN Offset, void *pData) -{ - UINT32 dwCommAddr; - UINT32 *pdwData; - UINT16 *pwData; - UINT32 dwLoop; - UINT32 ulWriteWordCount; - UINT32 dwAddr; - - if(gFlashBusy) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL]:Flash is busy!\n", __func__,__LINE__)); - return EFI_NOT_READY; - } - gFlashBusy = TRUE; - - if(2 == gFlashInfo[gIndex.InfIndex].ParallelNum) - { - pdwData = (UINT32 *)pData; - - dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep1); - - dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep2); - - //dwAddr = Base + (Offset << gFlashInfo[gIndex.InfIndex].ParallelNum); - dwAddr = (UINT32)Base + Offset; - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep3); - - - ulWriteWordCount = ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << 16) | (gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, ulWriteWordCount); - - - for (dwLoop = 0; dwLoop < gFlashInfo[gIndex.InfIndex].BufferProgramSize; dwLoop ++) - { - dwCommAddr = (UINT32)Base + (UINT32)Offset + (dwLoop << gFlashInfo[gIndex.InfIndex].ParallelNum); - MmioWrite32 (dwCommAddr, *pdwData); - pdwData ++; - } - - dwAddr = (UINT32)Base + (UINT32)Offset + ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramtoFlash); - - - - } - else - { - pwData = (UINT16 *)pData; - - dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep1); - - dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep2); - - //dwAddr = Base + (Offset << gFlashInfo[gIndex.InfIndex].ParallelNum); - dwAddr = (UINT32)Base + Offset; - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep3); - - - ulWriteWordCount = gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1; - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, ulWriteWordCount); - - - for (dwLoop = 0; dwLoop < gFlashInfo[gIndex.InfIndex].BufferProgramSize; dwLoop ++) - { - dwCommAddr = (UINT32)Base + (UINT32)Offset + (dwLoop << gFlashInfo[gIndex.InfIndex].ParallelNum); - MmioWrite16 (dwCommAddr, *pwData); - pwData ++; - } - - dwAddr = (UINT32)Base + (UINT32)Offset + ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramtoFlash); - - } - - (void)gBS->Stall(200); - - gFlashBusy = FALSE; - return EFI_SUCCESS; - -} - - -EFI_STATUS SectorEraseCommand(UINTN Base, UINTN Offset) -{ - UINT32 dwAddr; - - if(gFlashBusy) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL]:Flash is busy!\n", __func__,__LINE__)); - return EFI_NOT_READY; - } - - gFlashBusy = TRUE; - - dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep1); - - dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep2); - - dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep3 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep3); - - dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep4 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep4); - - dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep5 << gFlashInfo[gIndex.InfIndex].ParallelNum); - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep5); - - dwAddr = (UINT32)Base + Offset; - (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep6); - - (void)gBS->Stall(500000); - - gFlashBusy = FALSE; - return EFI_SUCCESS; -} - - -EFI_STATUS CompleteCheck(UINT32 Base, UINT32 Offset, void *pData, UINT32 Length) -{ - UINT32 dwTestAddr; - UINT32 dwTestData; - UINT32 dwTemp = 0; - UINT32 dwTemp1 = 0; - UINT32 i; - UINT32 dwTimeOut = 3000000; - - if(gFlashBusy) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL]:Flash is busy!\n", __func__,__LINE__)); - return EFI_NOT_READY; - } - gFlashBusy = TRUE; - - if(2 == gFlashInfo[gIndex.InfIndex].ParallelNum) - { - dwTestAddr = Base + Offset + Length - sizeof(UINT32); - dwTestData = *((UINT32 *)((UINT8 *)pData + Length - sizeof(UINT32))); - - while(dwTimeOut--) - { - dwTemp1 = MmioRead32 (dwTestAddr); - if (dwTestData == dwTemp1) - { - dwTemp = MmioRead32 (dwTestAddr); - dwTemp1 = MmioRead32 (dwTestAddr); - if ((dwTemp == dwTemp1) && (dwTestData == dwTemp1)) - { - gFlashBusy = FALSE; - return EFI_SUCCESS; - } - } - - (void)gBS->Stall(1); - } - - if((UINT16)(dwTemp1 >> 16) != (UINT16)(dwTestData >> 16)) - { - DEBUG((DEBUG_ERROR, "CompleteCheck ERROR: chip1 address %x, buffer %x, flash %x!\n", Offset, dwTestData, dwTemp1)); - } - if((UINT16)(dwTemp1) != (UINT16)(dwTestData)) - { - DEBUG((DEBUG_ERROR, "CompleteCheck ERROR: chip2 address %x, buffer %x, flash %x!\n", Offset, dwTestData, dwTemp1)); - } - } - else - { - dwTestAddr = Base + Offset + Length - sizeof(UINT16); - dwTestData = *((UINT16 *)((UINT8 *)pData + Length - sizeof(UINT16))); - - while(dwTimeOut--) - { - dwTemp1 = MmioRead16 (dwTestAddr); - if (dwTestData == dwTemp1) - { - dwTemp = MmioRead16 (dwTestAddr); - dwTemp1 = MmioRead16 (dwTestAddr); - if ((dwTemp == dwTemp1) && (dwTestData == dwTemp1)) - { - gFlashBusy = FALSE; - return EFI_SUCCESS; - } - } - - (void)gBS->Stall(1); - } - } - - for(i = 0; i < 5; i ++) - { - DEBUG((DEBUG_ERROR, "CompleteCheck ERROR: flash %x\n",PortReadData(gIndex.InfIndex, dwTestAddr))); - } - - FlashReset(Base); - - gFlashBusy = FALSE; - DEBUG((DEBUG_ERROR, "CompleteCheck ERROR: timeout address %x, buffer %x, flash %x\n", Offset, dwTestData, dwTemp1)); - return EFI_TIMEOUT; -} - -EFI_STATUS IsNeedToWrite( - IN UINT32 Base, - IN UINT32 Offset, - IN UINT8 *Buffer, - IN UINT32 Length - ) -{ - UINTN NewAddr = Base + Offset; - UINT8 FlashData = 0; - UINT8 BufferData = 0; - - for(; Length > 0; Length --) - { - BufferData = *Buffer; - //lint -epn -e511 - FlashData = *(UINT8 *)NewAddr; - if (BufferData != FlashData) - { - return TRUE; - } - NewAddr ++; - Buffer ++; - } - - return FALSE; -} - - -EFI_STATUS BufferWrite(UINT32 Offset, void *pData, UINT32 Length) -{ - EFI_STATUS Status; - UINT32 dwLoop; - UINT32 Retry = 3; - - if (FALSE == IsNeedToWrite(gIndex.Base, Offset, (UINT8 *)pData, Length)) - { - return EFI_SUCCESS; - } - - do - { - (void)BufferWriteCommand(gIndex.Base, Offset, pData); - Status = CompleteCheck(gIndex.Base, Offset, pData, Length); - - - if (EFI_SUCCESS == Status) - { - for (dwLoop = 0; dwLoop < Length; dwLoop ++) - { - if (*(UINT8 *)(UINTN)(gIndex.Base + Offset + dwLoop) != *((UINT8 *)pData + dwLoop)) - { - DEBUG((DEBUG_ERROR, "Flash_WriteUnit ERROR: address %x, buffer %x, flash %x\n", Offset, *((UINT8 *)pData + dwLoop), *(UINT8 *)(UINTN)(gIndex.Base + Offset + dwLoop))); - Status = EFI_ABORTED; - continue; - } - } - } - else - { - DEBUG((DEBUG_ERROR, "Flash_WriteUnit ERROR: complete check failed, %r\n", Status)); - continue; - } - } while ((Retry--) && EFI_ERROR(Status)); - - return Status; -} - - -EFI_STATUS SectorErase(UINT32 Base, UINT32 Offset) -{ - UINT8 gTemp[FLASH_MAX_UNIT]; - UINT64 dwLoop = FLASH_MAX_UNIT - 1; - UINT32 Retry = 3; - EFI_STATUS Status; - - do - { - gTemp[dwLoop] = 0xFF; - }while (dwLoop --); - - do - { - (void)SectorEraseCommand(Base, Offset); - Status = CompleteCheck(Base, Offset, (void *)gTemp, FLASH_MAX_UNIT); - - - if (EFI_SUCCESS == Status) - { - - if (width8IsAll(Base,Offset - (Offset % gFlashInfo[gIndex.InfIndex].BlockSize), gFlashInfo[gIndex.InfIndex].BlockSize, 0xFF)) - { - return EFI_SUCCESS; - } - else - { - DEBUG((DEBUG_ERROR, "Flash_SectorErase ERROR: not all address equal 0xFF\n")); - - Status = EFI_ABORTED; - continue; - } - } - else - { - DEBUG((DEBUG_ERROR, "Flash_SectorErase ERROR: complete check failed, %r\n", Status)); - continue; - } - }while ((Retry--) && EFI_ERROR(Status)); - - if(Retry) - { - //do nothing for pclint - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h b/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h deleted file mode 100644 index 93c696ef19d6516303c372344767a2a406226f94..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _NOR_FLASH_HW_H_ -#define _NOR_FLASH_HW_H_ - -#include - - -#define FOUR_BYTE_UNIT 4 -#define FLASH_MAX_UNIT 4 - -#define FLASH_DEVICE_NUM 0x10 - - - -typedef struct { - UINT32 ManufacturerID; - UINT32 DeviceID1; - UINT32 DeviceID2; - UINT32 DeviceID3; - UINT8 ParallelNum; - UINT32 SingleChipSize; - UINT32 BlockSize; - UINT32 BufferProgramSize; - UINT32 CommandType; -}NOR_FLASH_INFO_TABLE; - -/*Define Command Address And Data*/ -/*reset*/ -typedef struct { - UINT32 CommandType; - UINT32 ResetData; -}FLASH_COMMAND_RESET; - -/*manufacture ID & Device ID*/ -typedef struct { - UINT32 CommandType; - UINT32 ManuIDAddressStep1; - UINT32 ManuIDDataStep1; - UINT32 ManuIDAddressStep2; - UINT32 ManuIDDataStep2; - UINT32 ManuIDAddressStep3; - UINT32 ManuIDDataStep3; - UINT32 ManuIDAddress; - - UINT32 DeviceIDAddress1; - UINT32 DeviceIDAddress2; - UINT32 DeviceIDAddress3; -}FLASH_COMMAND_ID; - -/*Write Buffer*/ -typedef struct { - UINT32 CommandType; - UINT32 BufferProgramAddressStep1; - UINT32 BufferProgramDataStep1; - UINT32 BufferProgramAddressStep2; - UINT32 BufferProgramDataStep2; - UINT32 BufferProgramDataStep3; - UINT32 BufferProgramtoFlash; -}FLASH_COMMAND_WRITE; - -/*erase*/ -typedef struct { - UINT32 CommandType; - UINT32 SectorEraseAddressStep1; - UINT32 SectorEraseDataStep1; - UINT32 SectorEraseAddressStep2; - UINT32 SectorEraseDataStep2; - UINT32 SectorEraseAddressStep3; - UINT32 SectorEraseDataStep3; - UINT32 SectorEraseAddressStep4; - UINT32 SectorEraseDataStep4; - UINT32 SectorEraseAddressStep5; - UINT32 SectorEraseDataStep5; - UINT32 SectorEraseDataStep6; -}FLASH_COMMAND_ERASE; - - -typedef struct { - UINT32 Base; - UINT32 InfIndex; - UINT32 ReIndex; - UINT32 IdIndex; - UINT32 WIndex; - UINT32 EIndex; -}FLASH_INDEX; - - -extern EFI_STATUS FlashInit(UINT32 Base); -extern EFI_STATUS SectorErase(UINT32 Base, UINT32 Offset); -extern EFI_STATUS BufferWrite(UINT32 Offset, void *pData, UINT32 Length); -extern EFI_STATUS IsNeedToWrite(UINT32 Base, UINT32 Offset, UINT8 *Buffer, UINT32 Length); - - -extern NOR_FLASH_INFO_TABLE gFlashInfo[FLASH_DEVICE_NUM]; -extern FLASH_COMMAND_RESET gFlashCommandReset[FLASH_DEVICE_NUM]; -extern FLASH_COMMAND_ID gFlashCommandId[FLASH_DEVICE_NUM]; -extern FLASH_COMMAND_WRITE gFlashCommandWrite[FLASH_DEVICE_NUM]; -extern FLASH_COMMAND_ERASE gFlashCommandErase[FLASH_DEVICE_NUM]; -extern FLASH_INDEX gIndex; - - -#endif diff --git a/Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.c b/Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.c deleted file mode 100644 index f1077a0ccb4c1ff2412ba5287d7c67802f8e86ea..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.c +++ /dev/null @@ -1,476 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -// -// Global variables for Option ROMs -// -#define NULL_ROM_FILE_GUID \ - { \ - 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} \ - } - -#define SAS_OPTION_ROM_FILE_GUID \ -{ 0xb47533c7, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xdb}} - -#define SAS3108_OPTION_ROM_FILE_GUID \ -{ 0xb47533c8, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xd8}} - -#define INVALID 0xBD - - -typedef struct { - EFI_HANDLE PciPlatformHandle; - EFI_PCI_PLATFORM_PROTOCOL PciPlatform; -} PCI_PLATFORM_PRIVATE_DATA; - - -#define MAX_ROM_NUMBER 2 - - -typedef struct { - EFI_GUID FileName; - UINTN Segment; - UINTN Bus; - UINTN Device; - UINTN Function; - UINT16 VendorId; - UINT16 DeviceId; -} PCI_OPTION_ROM_TABLE; - -typedef struct { - UINTN RomSize; - VOID *RomBase; -} OPTION_ROM_INFO; - -PCI_PLATFORM_PRIVATE_DATA *mPciPrivateData = NULL; - -PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = { - { - SAS_OPTION_ROM_FILE_GUID, - 0, - 2, - 0, - 0, - 0x1000, - 0x0097 - }, - { - SAS3108_OPTION_ROM_FILE_GUID, - 0, - 1, - 0, - 0, - 0x1000, - 0x005D - }, - - // - // End of OptionROM Entries - // - { - NULL_ROM_FILE_GUID, // Guid - 0, // Segment - 0, // Bus Number - 0, // Device Number - 0, // Function Number - 0xffff, // Vendor ID - 0xffff // Device ID - } -}; - -/*++ - - Routine Description: - - Perform Platform initialization first in PciPlatform. - - Arguments: - - Returns: - - VOID. - ---*/ -VOID -EFIAPI -PciInitPlatform ( - VOID - ); - -/*++ - - Routine Description: - - Perform Platform initialization by the phase indicated. - - Arguments: - - HostBridge - The associated PCI host bridge handle. - Phase - The phase of the PCI controller enumeration. - ChipsetPhase - Defines the execution phase of the PCI chipset driver. - - Returns: - ---*/ -VOID -EFIAPI -PhaseNotifyPlatform ( - IN EFI_HANDLE HostBridge, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, - IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase - ); - -EFI_STATUS -EFIAPI -GetPlatformPolicy ( - IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, - OUT EFI_PCI_PLATFORM_POLICY *PciPolicy - ) -/*++ - -Routine Description: - - Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. - -Arguments: - - This - The pointer to the Protocol itself. - PciPolicy - the returned Policy. - -Returns: - - EFI_UNSUPPORTED - Function not supported. - EFI_INVALID_PARAMETER - Invalid PciPolicy value. - ---*/ -{ - if (PciPolicy == NULL) { - return EFI_INVALID_PARAMETER; - } - - return EFI_UNSUPPORTED; -} - -EFI_STATUS -GetRawImage ( - IN EFI_GUID *NameGuid, - IN OUT VOID **Buffer, - IN OUT UINTN *Size - ) -/*++ - -Routine Description: - - Get an indicated image in raw sections. - -Arguments: - - NameGuid - NameGuid of the image to get. - Buffer - Buffer to store the image get. - Size - size of the image get. - -Returns: - - EFI_NOT_FOUND - Could not find the image. - EFI_LOAD_ERROR - Error occurred during image loading. - EFI_SUCCESS - Image has been successfully loaded. - ---*/ -{ - EFI_STATUS Status; - EFI_HANDLE *HandleBuffer; - UINTN HandleCount; - UINTN Index; - EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; - UINT32 AuthenticationStatus; - - Status = gBS->LocateHandleBuffer ( - ByProtocol, - &gEfiFirmwareVolume2ProtocolGuid, - NULL, - &HandleCount, - &HandleBuffer - ); - if (EFI_ERROR (Status) || HandleCount == 0) { - return EFI_NOT_FOUND; - } - // - // Find desired image in all Fvs - // - for (Index = 0; Index < HandleCount; Index++) { - Status = gBS->HandleProtocol ( - HandleBuffer[Index], - &gEfiFirmwareVolume2ProtocolGuid, - (VOID **)&Fv - ); - if (EFI_ERROR (Status)) { - return EFI_LOAD_ERROR; - } - // - // Try a raw file - // - *Buffer = NULL; - *Size = 0; - Status = Fv->ReadSection ( - Fv, - NameGuid, - EFI_SECTION_RAW, - 0, - Buffer, - Size, - &AuthenticationStatus - ); - - if (!EFI_ERROR (Status)) { - break; - } - } - - if (Index >= HandleCount) { - return EFI_NOT_FOUND; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -GetPciRom ( - IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, - IN EFI_HANDLE PciHandle, - OUT VOID **RomImage, - OUT UINTN *RomSize - ) -/*++ - -Routine Description: - - Return a PCI ROM image for the onboard device represented by PciHandle. - -Arguments: - - This - Protocol instance pointer. - PciHandle - PCI device to return the ROM image for. - RomImage - PCI Rom Image for onboard device. - RomSize - Size of RomImage in bytes. - -Returns: - - EFI_SUCCESS - RomImage is valid. - EFI_NOT_FOUND - No RomImage. - ---*/ -{ - EFI_STATUS Status; - EFI_PCI_IO_PROTOCOL *PciIo; - UINT16 VendorId; - UINT16 DeviceId; - UINTN TableIndex; - UINTN RomImageNumber; - OPTION_ROM_INFO OptionRominfo[MAX_ROM_NUMBER]; - - Status = gBS->HandleProtocol ( - PciHandle, - &gEfiPciIoProtocolGuid, - (VOID **) &PciIo - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, 1, &VendorId); - (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OFFSET, 1, &DeviceId); - - // - // Loop through table of video option rom descriptions - // - RomImageNumber = 0; - for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) { - // - // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable - // - if ((VendorId != mPciOptionRomTable[TableIndex].VendorId) - || (DeviceId != mPciOptionRomTable[TableIndex].DeviceId) - ) - { - continue; - } - - Status = GetRawImage ( - &mPciOptionRomTable[TableIndex].FileName, - &(OptionRominfo[RomImageNumber].RomBase), - &(OptionRominfo[RomImageNumber].RomSize) - ); - - if (EFI_ERROR (Status)) { - continue; - } else { - RomImageNumber++; - if (RomImageNumber == MAX_ROM_NUMBER) { - break; - } - } - } - - if (RomImageNumber == 0) { - - return EFI_NOT_FOUND; - - } else { - *RomImage = OptionRominfo[RomImageNumber - 1].RomBase; - *RomSize = OptionRominfo[RomImageNumber - 1].RomSize; - - if (RomImageNumber > 1) { - // - // More than one OPROM have been found! - // - - } - - return EFI_SUCCESS; - } -} - -EFI_STATUS -EFIAPI -PlatformPrepController ( - IN EFI_PCI_PLATFORM_PROTOCOL *This, - IN EFI_HANDLE HostBridge, - IN EFI_HANDLE RootBridge, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, - IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase - ) -/*++ - -Routine Description: - - The PlatformPrepController() function can be used to notify the platform driver so that - it can perform platform-specific actions. No specific actions are required. - Several notification points are defined at this time. More synchronization points may be - added as required in the future. The PCI bus driver calls the platform driver twice for - every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver - is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has - been notified. - This member function may not perform any error checking on the input parameters. It also - does not return any error codes. If this member function detects any error condition, it - needs to handle those errors on its own because there is no way to surface any errors to - the caller. - -Arguments: - - This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. - HostBridge - The associated PCI host bridge handle. - RootBridge - The associated PCI root bridge handle. - PciAddress - The address of the PCI device on the PCI bus. - Phase - The phase of the PCI controller enumeration. - ChipsetPhase - Defines the execution phase of the PCI chipset driver. - -Returns: - - EFI_SUCCESS - The function completed successfully. - EFI_UNSUPPORTED - Not supported. - ---*/ -{ - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -PhaseNotify ( - IN EFI_PCI_PLATFORM_PROTOCOL *This, - IN EFI_HANDLE HostBridge, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, - IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase - ) -/*++ - -Routine Description: - - Perform initialization by the phase indicated. - -Arguments: - - This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. - HostBridge - The associated PCI host bridge handle. - Phase - The phase of the PCI controller enumeration. - ChipsetPhase - Defines the execution phase of the PCI chipset driver. - -Returns: - - EFI_SUCCESS - Must return with success. - ---*/ -{ - PhaseNotifyPlatform (HostBridge, Phase, ChipsetPhase); - - return EFI_SUCCESS; -} - -EFI_STATUS -PciPlatformDriverEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -/*++ - -Routine Description: - Main Entry point of the Pci Platform Driver. - -Arguments: - - ImageHandle - Handle to the image. - SystemTable - Handle to System Table. - -Returns: - - EFI_STATUS - Status of the function calling. - ---*/ -{ - EFI_STATUS Status; - PCI_PLATFORM_PRIVATE_DATA *PciPrivateData; - - PciInitPlatform (); - - PciPrivateData = AllocateZeroPool (sizeof (PCI_PLATFORM_PRIVATE_DATA)); - mPciPrivateData = PciPrivateData; - - mPciPrivateData->PciPlatform.PlatformNotify = PhaseNotify; - mPciPrivateData->PciPlatform.PlatformPrepController = PlatformPrepController; - mPciPrivateData->PciPlatform.GetPlatformPolicy = GetPlatformPolicy; - mPciPrivateData->PciPlatform.GetPciRom = GetPciRom; - - // - // Install on a new handle - // - Status = gBS->InstallMultipleProtocolInterfaces ( - &mPciPrivateData->PciPlatformHandle, - &gEfiPciPlatformProtocolGuid, - &mPciPrivateData->PciPlatform, - NULL - ); - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf b/Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf deleted file mode 100644 index f965ebbd4571641e805fbbc05b4fd4061d34d404..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf +++ /dev/null @@ -1,48 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[defines] - INF_VERSION = 0x00010005 - BASE_NAME = PciPlatform - FILE_GUID = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = PciPlatformDriverEntry - -[sources.common] - PciPlatform.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiLib - BaseLib - DebugLib - ArmLib - IoLib - MemoryAllocationLib - PciPlatformLib - -[Protocols] - gEfiPciPlatformProtocolGuid - gEfiFirmwareVolume2ProtocolGuid - gEfiPciIoProtocolGuid - -[Pcd] - -[FixedPcd] - -[Depex] - TRUE - diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c deleted file mode 100644 index 2220dc5e923a04d63a3ae81d852a1a8d835beee9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c +++ /dev/null @@ -1,100 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define SAS0BusAddr 0xc3000000 -#define SAS1BusAddr 0xa2000000 -#define SAS2BusAddr 0xa3000000 - -#define SAS0ResetAddr 0xc0000000 -#define SAS1ResetAddr 0xa0000000 -#define SAS2ResetAddr 0xa0000000 - -typedef struct { - UINTN Signature; - EFI_HANDLE Handle; - HISI_PLATFORM_SAS_PROTOCOL SasPlatformProtocol; -} SAS_PLATFORM_INSTANCE; - - -STATIC HISI_PLATFORM_SAS_PROTOCOL mSasPlatformProtocol[] = { - { - 0, - FALSE, - SAS0BusAddr, - SAS0ResetAddr - }, - { - 1, - TRUE, - SAS1BusAddr, - SAS1ResetAddr - }, - { - 2, - FALSE, - SAS2BusAddr, - SAS2ResetAddr - } -}; - -EFI_STATUS -EFIAPI -SasPlatformInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - UINTN Loop; - SAS_PLATFORM_INSTANCE *PrivateData; - EFI_STATUS Status; - - for (Loop = 0; Loop < ARRAY_SIZE (mSasPlatformProtocol); Loop++) { - if (mSasPlatformProtocol[Loop].Enable != TRUE) { - continue; - } - PrivateData = AllocateZeroPool (sizeof(SAS_PLATFORM_INSTANCE)); - if (PrivateData == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - PrivateData->SasPlatformProtocol = mSasPlatformProtocol[Loop]; - - Status = gBS->InstallMultipleProtocolInterfaces ( - &PrivateData->Handle, - &gHisiPlatformSasProtocolGuid, - &PrivateData->SasPlatformProtocol, - NULL - ); - if (EFI_ERROR (Status)) { - FreePool (PrivateData); - DEBUG ((DEBUG_ERROR, - "[%a]:[%dL] InstallProtocolInterface fail. %r\n", - __func__, - __LINE__, - Status)); - continue; - } - } - - DEBUG ((DEBUG_INFO, "sas platform init driver Ok!!!\n")); - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf deleted file mode 100644 index 1c4d5dac10c946fa552c120eee73f1d6e9c69b41..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf +++ /dev/null @@ -1,39 +0,0 @@ -#/** @file -# -# Copyright (c) 2017, Hisilicon Limited. All rights reserved. -# Copyright (c) 2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = SasPlatform - FILE_GUID = 67B9CDE8-257D-44f9-9DE7-39DE866E3539 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = SasPlatformInitialize - -[Sources] - SasPlatform.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - DxeServicesTableLib - UefiBootServicesTableLib - UefiDriverEntryPoint - UefiLib - -[Protocols] - gHisiPlatformSasProtocolGuid - -[Depex] - TRUE diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c deleted file mode 100644 index b2efe6b03ed6508e6e8b63fdad5d4039bad77c4e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c +++ /dev/null @@ -1,1042 +0,0 @@ -/** @file - - Copyright (c) 2016 Linaro Ltd. - Copyright (c) 2016 Hisilicon Limited. - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define READ_REG32(Base, Offset) MmioRead32 ((Base) + (Offset)) -#define WRITE_REG32(Base, Offset, Val) MmioWrite32 ((Base) + (Offset), (Val)) - -#define PHY_READ_REG32(Base, Offset, phy) MmioRead32 ((Base) + (Offset) + 0x400 * (phy)) -#define PHY_WRITE_REG32(Base, Offset, phy, Val) MmioWrite32 ((Base) + (Offset) + 0x400 * (phy), (Val)) - -#define DLVRY_QUEUE_ENABLE 0x0 -#define IOST_BASE_ADDR_LO 0x8 -#define IOST_BASE_ADDR_HI 0xc -#define ITCT_BASE_ADDR_LO 0x10 -#define ITCT_BASE_ADDR_HI 0x14 -#define BROKEN_MSG_ADDR_LO 0x18 -#define BROKEN_MSG_ADDR_HI 0x1c -#define PHY_CONTEXT 0x20 -#define PHY_PORT_NUM_MA 0x28 -#define HGC_TRANS_TASK_CNT_LIMIT 0x38 -#define AXI_AHB_CLK_CFG 0x3c -#define HGC_SAS_TXFAIL_RETRY_CTRL 0x84 -#define HGC_GET_ITV_TIME 0x90 -#define DEVICE_MSG_WORK_MODE 0x94 -#define I_T_NEXUS_LOSS_TIME 0xa0 -#define BUS_INACTIVE_LIMIT_TIME 0xa8 -#define REJECT_TO_OPEN_LIMIT_TIME 0xac -#define CFG_AGING_TIME 0xbc -#define HGC_DFX_CFG2 0xc0 -#define FIS_LIST_BADDR_L 0xc4 -#define CFG_1US_TIMER_TRSH 0xcc -#define CFG_SAS_CONFIG 0xd4 -#define INT_COAL_EN 0x1bc -#define OQ_INT_COAL_TIME 0x1c0 -#define OQ_INT_COAL_CNT 0x1c4 -#define ENT_INT_COAL_TIME 0x1c8 -#define ENT_INT_COAL_CNT 0x1cc -#define OQ_INT_SRC 0x1d0 -#define OQ_INT_SRC_MSK 0x1d4 -#define ENT_INT_SRC1 0x1d8 -#define ENT_INT_SRC2 0x1dc -#define ENT_INT_SRC_MSK1 0x1e0 -#define ENT_INT_SRC_MSK2 0x1e4 -#define SAS_ECC_INTR_MSK 0x1ec -#define HGC_ERR_STAT_EN 0x238 -#define DLVRY_Q_0_BASE_ADDR_LO 0x260 -#define DLVRY_Q_0_BASE_ADDR_HI 0x264 -#define DLVRY_Q_0_DEPTH 0x268 -#define DLVRY_Q_0_WR_PTR 0x26c -#define DLVRY_Q_0_RD_PTR 0x270 -#define COMPL_Q_0_BASE_ADDR_LO 0x4e0 -#define COMPL_Q_0_BASE_ADDR_HI 0x4e4 -#define COMPL_Q_0_DEPTH 0x4e8 -#define COMPL_Q_0_WR_PTR 0x4ec -#define COMPL_Q_0_RD_PTR 0x4f0 -#define AXI_CFG 0x5100 - -#define PORT_BASE 0x800 -#define PHY_CFG (PORT_BASE + 0x0) -#define PHY_CFG_ENA_OFF 0 -#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) -#define PHY_CFG_DC_OPT_OFF 2 -#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) -#define PROG_PHY_LINK_RATE (PORT_BASE + 0xc) -#define PHY_CTRL (PORT_BASE + 0x14) -#define PHY_CTRL_RESET BIT0 -#define PHY_RATE_NEGO (PORT_BASE + 0x30) -#define PHY_PCN (PORT_BASE + 0x44) -#define SL_TOUT_CFG (PORT_BASE + 0x8c) -#define SL_CONTROL (PORT_BASE + 0x94) -#define SL_CONTROL_NOTIFY_EN BIT0 -#define TX_ID_DWORD0 (PORT_BASE + 0x9c) -#define TX_ID_DWORD1 (PORT_BASE + 0xa0) -#define TX_ID_DWORD2 (PORT_BASE + 0xa4) -#define TX_ID_DWORD3 (PORT_BASE + 0xa8) -#define TX_ID_DWORD4 (PORT_BASE + 0xaC) -#define TX_ID_DWORD5 (PORT_BASE + 0xb0) -#define TX_ID_DWORD6 (PORT_BASE + 0xb4) -#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) -#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) -#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) -#define DONE_RECEIVED_TIME (PORT_BASE + 0x12c) -#define CON_CFG_DRIVER (PORT_BASE + 0x130) -#define PHY_CONFIG2 (PORT_BASE + 0x1a8) -#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3 -#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF) -#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) -#define CHL_INT0 (PORT_BASE + 0x1b0) -#define CHL_INT0_PHYCTRL_NOTRDY BIT0 -#define CHL_INT1 (PORT_BASE + 0x1b4) -#define CHL_INT2 (PORT_BASE + 0x1b8) -#define CHL_INT2_SL_PHY_ENA BIT6 -#define CHL_INT0_MSK (PORT_BASE + 0x1bc) -#define CHL_INT0_MSK_PHYCTRL_NOTRDY BIT0 -#define CHL_INT1_MSK (PORT_BASE + 0x1c0) -#define CHL_INT2_MSK (PORT_BASE + 0x1c4) -#define DMA_TX_STATUS (PORT_BASE + 0x2d0) -#define DMA_TX_STATUS_BUSY BIT0 -#define DMA_RX_STATUS (PORT_BASE + 0x2e8) -#define DMA_RX_STATUS_BUSY BIT0 - -#define QUEUE_CNT 32 -#define QUEUE_SLOTS 256 -#define SLOT_ENTRIES 8192 -#define PHY_CNT 8 -#define MAX_ITCT_ENTRIES 1 - -// Completion header -#define CMPLT_HDR_IPTT_OFF 0 -#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) - -#define BIT(x) (1 << x) - -// HW dma structures -// Delivery queue header -// dw0 -#define CMD_HDR_RESP_REPORT_OFF 5 -#define CMD_HDR_RESP_REPORT_MSK 0x20 -#define CMD_HDR_TLR_CTRL_OFF 6 -#define CMD_HDR_TLR_CTRL_MSK 0xc0 -#define CMD_HDR_PORT_OFF 17 -#define CMD_HDR_PORT_MSK 0xe0000 -#define CMD_HDR_PRIORITY_OFF 27 -#define CMD_HDR_PRIORITY_MSK 0x8000000 -#define CMD_HDR_MODE_OFF 28 -#define CMD_HDR_MODE_MSK 0x10000000 -#define CMD_HDR_CMD_OFF 29 -#define CMD_HDR_CMD_MSK 0xe0000000 -// dw1 -#define CMD_HDR_VERIFY_DTL_OFF 10 -#define CMD_HDR_VERIFY_DTL_MSK 0x400 -#define CMD_HDR_SSP_FRAME_TYPE_OFF 13 -#define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000 -#define CMD_HDR_DEVICE_ID_OFF 16 -#define CMD_HDR_DEVICE_ID_MSK 0xffff0000 -// dw2 -#define CMD_HDR_CFL_OFF 0 -#define CMD_HDR_CFL_MSK 0x1ff -#define CMD_HDR_MRFL_OFF 15 -#define CMD_HDR_MRFL_MSK 0xff8000 -#define CMD_HDR_FIRST_BURST_OFF 25 -#define CMD_HDR_FIRST_BURST_MSK 0x2000000 -// dw3 -#define CMD_HDR_IPTT_OFF 0 -#define CMD_HDR_IPTT_MSK 0xffff -// dw6 -#define CMD_HDR_DATA_SGL_LEN_OFF 16 -#define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000 - -// Completion header -#define CMPLT_HDR_IPTT_OFF 0 -#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) -#define CMPLT_HDR_CMD_CMPLT_MSK BIT17 -#define CMPLT_HDR_ERR_RCRD_XFRD_MSK BIT18 -#define CMPLT_HDR_RSPNS_XFRD_MSK BIT19 -#define CMPLT_HDR_IO_CFG_ERR_MSK BIT27 - -#define SENSE_DATA_PRES 26 - -#define SGE_LIMIT 0x10000 -#define upper_32_bits(n) ((UINT32)(((n) >> 16) >> 16)) -#define lower_32_bits(n) ((UINT32)(n)) -#define MAX_TARGET_ID 4 - -// Generic HW DMA host memory structures -struct hisi_sas_cmd_hdr { - UINT32 dw0; - UINT32 dw1; - UINT32 dw2; - UINT32 transfer_tags; - UINT32 data_transfer_len; - UINT32 first_burst_num; - UINT32 sg_len; - UINT32 dw7; - UINT64 cmd_table_addr; - UINT64 sts_buffer_addr; - UINT64 prd_table_addr; - UINT64 dif_prd_table_addr; -}; - -struct hisi_sas_complete_hdr { - UINT32 data; -}; - -struct hisi_sas_iost { - UINT64 qw0; - UINT64 qw1; - UINT64 qw2; - UINT64 qw3; -}; - -struct hisi_sas_itct { - UINT64 qw0; - UINT64 sas_addr; - UINT64 qw2; - UINT64 qw3; - UINT64 qw4; - UINT64 qw_sata_ncq0_3; - UINT64 qw_sata_ncq7_4; - UINT64 qw_sata_ncq11_8; - UINT64 qw_sata_ncq15_12; - UINT64 qw_sata_ncq19_16; - UINT64 qw_sata_ncq23_20; - UINT64 qw_sata_ncq27_24; - UINT64 qw_sata_ncq31_28; - UINT64 qw_non_ncq_iptt; - UINT64 qw_rsvd0; - UINT64 qw_rsvd1; -}; - -struct hisi_sas_breakpoint { - UINT8 data[128]; -}; - -struct hisi_sas_sge { - UINT64 addr; - UINT32 page_ctrl_0; - UINT32 page_ctrl_1; - UINT32 data_len; - UINT32 data_off; -}; - -struct hisi_sas_sge_page { - struct hisi_sas_sge sg[512]; -}; - -struct hisi_sas_cmd { - UINT8 cmd[128]; -}; - -struct hisi_sas_sts { -UINT32 status[260]; -}; - -struct hisi_sas_slot { - BOOLEAN used; -}; - -struct hisi_hba { - struct hisi_sas_cmd_hdr *cmd_hdr[QUEUE_CNT]; - struct hisi_sas_complete_hdr *complete_hdr[QUEUE_CNT]; - struct hisi_sas_sge_page *sge[QUEUE_CNT]; - struct hisi_sas_sts *status_buf[QUEUE_CNT]; - struct hisi_sas_cmd *command_table[QUEUE_CNT]; - struct hisi_sas_iost *iost; - struct hisi_sas_itct *itct; - struct hisi_sas_breakpoint *breakpoint; - struct hisi_sas_slot *slots; - UINT32 base; - int queue; - int port_id; - UINT32 LatestTargetId; - UINT64 LatestLun; -}; - -#pragma pack (1) -typedef struct { - VENDOR_DEVICE_PATH Vendor; - UINT64 PhysBase; - EFI_DEVICE_PATH_PROTOCOL End; -} SAS_V1_TRANSPORT_DEVICE_PATH; -#pragma pack () - -typedef struct { - UINT32 Signature; - EFI_EXT_SCSI_PASS_THRU_MODE ExtScsiPassThruMode; - EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru; - SAS_V1_TRANSPORT_DEVICE_PATH *DevicePath; - struct hisi_hba *hba; - EFI_EVENT TimerEvent; -} SAS_V1_INFO; - -#define SAS_DEVICE_SIGNATURE SIGNATURE_32 ('S','A','S','0') -#define SAS_FROM_PASS_THRU(a) CR (a, SAS_V1_INFO, ExtScsiPassThru, SAS_DEVICE_SIGNATURE) - -STATIC EFI_STATUS prepare_cmd ( - struct hisi_hba *hba, - EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet - ) -{ - struct hisi_sas_slot *slot; - struct hisi_sas_cmd_hdr *hdr; - struct hisi_sas_sge_page *sge; - struct hisi_sas_sts *sts; - struct hisi_sas_cmd *cmd; - EFI_SCSI_SENSE_DATA *SensePtr = Packet->SenseData; - VOID *Buffer = NULL; - UINTN BufferSize = 0; - int queue = hba->queue; - UINT32 r, w = 0, slot_idx = 0; - UINT32 base = hba->base; - UINT8 *p; - EFI_PHYSICAL_ADDRESS BufferAddress; - EFI_STATUS Status = EFI_SUCCESS; - VOID *BufferMap = NULL; - DMA_MAP_OPERATION DmaOperation = MapOperationBusMasterCommonBuffer; - - while (1) { - w = READ_REG32(base, DLVRY_Q_0_WR_PTR + (queue * 0x14)); - r = READ_REG32(base, DLVRY_Q_0_RD_PTR + (queue * 0x14)); - slot_idx = queue * QUEUE_SLOTS + w; - slot = &hba->slots[slot_idx]; - if (slot->used || (r == (w+1) % QUEUE_SLOTS)) { - queue = (queue + 1) % QUEUE_CNT; - if (queue == hba->queue) { - DEBUG ((DEBUG_ERROR, "could not find free slot\n")); - return EFI_NOT_READY; - } - continue; - } - break; - } - - hdr = &hba->cmd_hdr[queue][w]; - cmd = &hba->command_table[queue][w]; - sts = &hba->status_buf[queue][w]; - sge = &hba->sge[queue][w]; - - ZeroMem (cmd, sizeof (struct hisi_sas_cmd)); - ZeroMem (sts, sizeof (struct hisi_sas_sts)); - if (SensePtr) - ZeroMem (SensePtr, sizeof (EFI_SCSI_SENSE_DATA)); - - slot->used = TRUE; - hba->queue = (queue + 1) % QUEUE_CNT; - - // Only consider ssp - hdr->dw0 = (1 << CMD_HDR_RESP_REPORT_OFF) | - (0x2 << CMD_HDR_TLR_CTRL_OFF) | - (hba->port_id << CMD_HDR_PORT_OFF) | - (1 << CMD_HDR_MODE_OFF) | - (1 << CMD_HDR_CMD_OFF); - hdr->dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF; - hdr->dw1 |= 0 << CMD_HDR_DEVICE_ID_OFF; - hdr->dw2 = 0x83000d; - hdr->transfer_tags = slot_idx << CMD_HDR_IPTT_OFF; - - if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) { - Buffer = Packet->InDataBuffer; - BufferSize = Packet->InTransferLength; - if (Buffer) { - hdr->dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF; - DmaOperation = MapOperationBusMasterWrite; - } - } else if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_WRITE) { - Buffer = Packet->OutDataBuffer; - BufferSize = Packet->OutTransferLength; - if (Buffer) { - DmaOperation = MapOperationBusMasterRead; - hdr->dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF; - } - } else { - hdr->dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF; - } - - hdr->data_transfer_len = BufferSize; - hdr->cmd_table_addr = (UINT64)cmd; - hdr->sts_buffer_addr = (UINT64)sts; - - CopyMem (&cmd->cmd[36], Packet->Cdb, Packet->CdbLength); - - if (Buffer != NULL) { - struct hisi_sas_sge *sg; - UINT32 remain, len, pos = 0, i = 0; - - Status = DmaMap (DmaOperation, Buffer, &BufferSize, &BufferAddress, &BufferMap); - if (EFI_ERROR (Status)) { - return Status; - } - remain = len = BufferSize; - - while (remain) { - if (len > SGE_LIMIT) - len = SGE_LIMIT; - sg = &sge->sg[i]; - sg->addr = (UINT64)(BufferAddress + pos); - sg->page_ctrl_0 = sg->page_ctrl_1 = 0; - sg->data_len = len; - sg->data_off = 0; - remain -= len; - pos += len; - len = remain; - i++; - } - - hdr->prd_table_addr = (UINT64)sge; - hdr->sg_len = i << CMD_HDR_DATA_SGL_LEN_OFF; - } - - // Ensure descriptor effective before start dma - MemoryFence(); - - // Start dma - WRITE_REG32(base, DLVRY_Q_0_WR_PTR + queue * 0x14, ++w % QUEUE_SLOTS); - - // Wait for dma complete - while (slot->used) { - if (READ_REG32(base, OQ_INT_SRC) & BIT(queue)) { - struct hisi_sas_complete_hdr *complete_hdr; - UINT32 data, rd; - rd = READ_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue)); - - complete_hdr = &hba->complete_hdr[queue][rd]; - data = complete_hdr->data; - - // Check whether dma transfer error - if ((data & CMPLT_HDR_ERR_RCRD_XFRD_MSK) && - !(data & CMPLT_HDR_RSPNS_XFRD_MSK)) { - DEBUG ((DEBUG_VERBOSE, "sas retry data=0x%x\n", data)); - DEBUG ((DEBUG_VERBOSE, "sts[0]=0x%x\n", sts->status[0])); - DEBUG ((DEBUG_VERBOSE, "sts[1]=0x%x\n", sts->status[1])); - DEBUG ((DEBUG_VERBOSE, "sts[2]=0x%x\n", sts->status[2])); - Status = EFI_NOT_READY; - // wait 1 second and retry, some disk need long time to be ready - // and ScsiDisk treat retry over 3 times as error - MicroSecondDelay(1000000); - } - // Update read point - WRITE_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue), w); - // Clear int - WRITE_REG32(base, OQ_INT_SRC, BIT(queue)); - slot->used = FALSE; - break; - } - // Wait for status change in polling - NanoSecondDelay (100); - } - - if (BufferMap) - DmaUnmap (BufferMap); - - p = (UINT8 *)&sts->status[0]; - if (p[SENSE_DATA_PRES]) { - // Disk not ready normal return for ScsiDiskTestUnitReady do next try - SensePtr->Sense_Key = EFI_SCSI_SK_NOT_READY; - SensePtr->Addnl_Sense_Code = EFI_SCSI_ASC_NOT_READY; - SensePtr->Addnl_Sense_Code_Qualifier = EFI_SCSI_ASCQ_IN_PROGRESS; - // wait 1 second for disk spin up, refer drivers/scsi/sd.c - MicroSecondDelay(1000000); - } - return Status; -} - -STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat) -{ - int i, j; - UINT32 val, base = hba->base; - - // Reset - for (i = 0; i < PHY_CNT; i++) { - UINT32 phy_ctrl = PHY_READ_REG32(base, PHY_CTRL, i); - - phy_ctrl |= PHY_CTRL_RESET; - PHY_WRITE_REG32(base, PHY_CTRL, i, phy_ctrl); - } - // spec says safe to wait 50us after reset - MicroSecondDelay(50); - - // Ensure DMA tx & rx idle - for (i = 0; i < PHY_CNT; i++) { - UINT32 dma_tx_status, dma_rx_status; - - for (j = 0; j < 100; j++) { - dma_tx_status = PHY_READ_REG32(base, DMA_TX_STATUS, i); - dma_rx_status = PHY_READ_REG32(base, DMA_RX_STATUS, i); - - if (!(dma_tx_status & DMA_TX_STATUS_BUSY) && - !(dma_rx_status & DMA_RX_STATUS_BUSY)) - break; - - // Wait for status change in polling - NanoSecondDelay (100); - } - } - - // Ensure axi bus idle - for (j = 0; j < 100; j++) { - UINT32 axi_status = READ_REG32(base, AXI_CFG); - if (axi_status == 0) - break; - - // Wait for status change in polling - NanoSecondDelay (100); - } - - plat->Init(plat); - - WRITE_REG32(base, DLVRY_QUEUE_ENABLE, 0xffffffff); - WRITE_REG32(base, HGC_TRANS_TASK_CNT_LIMIT, 0x11); - WRITE_REG32(base, DEVICE_MSG_WORK_MODE, 0x1); - WRITE_REG32(base, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff); - WRITE_REG32(base, HGC_ERR_STAT_EN, 0x401); - WRITE_REG32(base, CFG_1US_TIMER_TRSH, 0x64); - WRITE_REG32(base, HGC_GET_ITV_TIME, 0x1); - WRITE_REG32(base, I_T_NEXUS_LOSS_TIME, 0x64); - WRITE_REG32(base, BUS_INACTIVE_LIMIT_TIME, 0x2710); - WRITE_REG32(base, REJECT_TO_OPEN_LIMIT_TIME, 0x1); - WRITE_REG32(base, CFG_AGING_TIME, 0x7a12); - WRITE_REG32(base, HGC_DFX_CFG2, 0x9c40); - WRITE_REG32(base, FIS_LIST_BADDR_L, 0x2); - WRITE_REG32(base, INT_COAL_EN, 0xc); - WRITE_REG32(base, OQ_INT_COAL_TIME, 0x186a0); - WRITE_REG32(base, OQ_INT_COAL_CNT, 1); - WRITE_REG32(base, ENT_INT_COAL_TIME, 0x1); - WRITE_REG32(base, ENT_INT_COAL_CNT, 0x1); - WRITE_REG32(base, OQ_INT_SRC, 0xffffffff); - WRITE_REG32(base, ENT_INT_SRC1, 0xffffffff); - WRITE_REG32(base, ENT_INT_SRC_MSK1, 0); - WRITE_REG32(base, ENT_INT_SRC2, 0xffffffff); - WRITE_REG32(base, ENT_INT_SRC_MSK2, 0); - WRITE_REG32(base, SAS_ECC_INTR_MSK, 0); - WRITE_REG32(base, AXI_AHB_CLK_CFG, 0x2); - WRITE_REG32(base, CFG_SAS_CONFIG, 0x22000000); - - for (i = 0; i < PHY_CNT; i++) { - PHY_WRITE_REG32(base, PROG_PHY_LINK_RATE, i, 0x88a); - PHY_WRITE_REG32(base, PHY_CONFIG2, i, 0x7c080); - PHY_WRITE_REG32(base, PHY_RATE_NEGO, i, 0x415ee00); - PHY_WRITE_REG32(base, PHY_PCN, i, 0x80a80000); - PHY_WRITE_REG32(base, SL_TOUT_CFG, i, 0x7d7d7d7d); - PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 0x0); - PHY_WRITE_REG32(base, RXOP_CHECK_CFG_H, i, 0x1000); - PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 0); - PHY_WRITE_REG32(base, CON_CFG_DRIVER, i, 0x13f0a); - PHY_WRITE_REG32(base, CHL_INT_COAL_EN, i, 3); - PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 8); - } - - for (i = 0; i < QUEUE_CNT; i++) { - WRITE_REG32(base, DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), upper_32_bits((UINT64)(hba->cmd_hdr[i]))); - WRITE_REG32(base, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), lower_32_bits((UINT64)(hba->cmd_hdr[i]))); - WRITE_REG32(base, DLVRY_Q_0_DEPTH + (i * 0x14), QUEUE_SLOTS); - - WRITE_REG32(base, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), upper_32_bits((UINT64)(hba->complete_hdr[i]))); - WRITE_REG32(base, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), lower_32_bits((UINT64)(hba->complete_hdr[i]))); - WRITE_REG32(base, COMPL_Q_0_DEPTH + (i * 0x14), QUEUE_SLOTS); - } - - WRITE_REG32(base, ITCT_BASE_ADDR_LO, lower_32_bits((UINT64)(hba->itct))); - WRITE_REG32(base, ITCT_BASE_ADDR_HI, upper_32_bits((UINT64)(hba->itct))); - - WRITE_REG32(base, IOST_BASE_ADDR_LO, lower_32_bits((UINT64)(hba->iost))); - WRITE_REG32(base, IOST_BASE_ADDR_HI, upper_32_bits((UINT64)(hba->iost))); - - WRITE_REG32(base, BROKEN_MSG_ADDR_LO, lower_32_bits((UINT64)(hba->breakpoint))); - WRITE_REG32(base, BROKEN_MSG_ADDR_HI, upper_32_bits((UINT64)(hba->breakpoint))); - - for (i = 0; i < PHY_CNT; i++) { - // Clear interrupt status - val = PHY_READ_REG32(base, CHL_INT0, i); - PHY_WRITE_REG32(base, CHL_INT0, i, val); - val = PHY_READ_REG32(base, CHL_INT1, i); - PHY_WRITE_REG32(base, CHL_INT1, i, val); - val = PHY_READ_REG32(base, CHL_INT2, i); - PHY_WRITE_REG32(base, CHL_INT2, i, val); - - // Bypass chip bug mask abnormal intr - PHY_WRITE_REG32(base, CHL_INT0_MSK, i, 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY); - } - - // Init phy - for (i = 0; i < PHY_CNT; i++) { - PHY_WRITE_REG32(base, TX_ID_DWORD0, i, 0x10010e00); - PHY_WRITE_REG32(base, TX_ID_DWORD1, i, 0x16); - PHY_WRITE_REG32(base, TX_ID_DWORD2, i, 0x20880150); - PHY_WRITE_REG32(base, TX_ID_DWORD3, i, 0x16); - PHY_WRITE_REG32(base, TX_ID_DWORD4, i, 0x20880150); - PHY_WRITE_REG32(base, TX_ID_DWORD5, i, 0x0); - - val = PHY_READ_REG32(base, PHY_CFG, i); - val &= ~PHY_CFG_DC_OPT_MSK; - val |= 1 << PHY_CFG_DC_OPT_OFF; - PHY_WRITE_REG32(base, PHY_CFG, i, val); - - val = PHY_READ_REG32(base, PHY_CONFIG2, i); - val &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK; - PHY_WRITE_REG32(base, PHY_CONFIG2, i, val); - - val = PHY_READ_REG32(base, PHY_CFG, i); - val |= PHY_CFG_ENA_MSK; - PHY_WRITE_REG32(base, PHY_CFG, i, val); - } -} - -STATIC VOID sas_init(SAS_V1_INFO *SasV1Info, PLATFORM_SAS_PROTOCOL *plat) -{ - struct hisi_hba *hba = SasV1Info->hba; - int i, s; - - for (i = 0; i < QUEUE_CNT; i++) { - s = sizeof(struct hisi_sas_cmd_hdr) * QUEUE_SLOTS; - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->cmd_hdr[i]); - ASSERT (hba->cmd_hdr[i] != NULL); - ZeroMem (hba->cmd_hdr[i], s); - - s = sizeof(struct hisi_sas_complete_hdr) * QUEUE_SLOTS; - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->complete_hdr[i]); - ASSERT (hba->complete_hdr[i] != NULL); - ZeroMem (hba->complete_hdr[i], s); - - s = sizeof(struct hisi_sas_sts) * QUEUE_SLOTS; - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->status_buf[i]); - ASSERT (hba->status_buf[i] != NULL); - ZeroMem (hba->status_buf[i], s); - - s = sizeof(struct hisi_sas_cmd) * QUEUE_SLOTS; - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->command_table[i]); - ASSERT (hba->command_table[i] != NULL); - ZeroMem (hba->command_table[i], s); - - s = sizeof(struct hisi_sas_sge_page) * QUEUE_SLOTS; - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->sge[i]); - ASSERT (hba->sge[i] != NULL); - ZeroMem (hba->sge[i], s); - } - - s = SLOT_ENTRIES * sizeof(struct hisi_sas_iost); - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->iost); - ASSERT (hba->iost != NULL); - ZeroMem (hba->iost, s); - - s = SLOT_ENTRIES * sizeof(struct hisi_sas_breakpoint); - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->breakpoint); - ASSERT (hba->breakpoint != NULL); - ZeroMem (hba->breakpoint, s); - - s = MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct); - DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->itct); - ASSERT (hba->itct != NULL); - ZeroMem (hba->itct, s); - - hba->slots = AllocateZeroPool (SLOT_ENTRIES * sizeof(struct hisi_sas_slot)); - ASSERT (hba->slots != NULL); - - hisi_sas_v1_init(hba, plat); -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruFunction ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, - IN UINT8 *Target, - IN UINT64 Lun, - IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet, - IN EFI_EVENT Event OPTIONAL - ) -{ - SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This); - struct hisi_hba *hba = SasV1Info->hba; - - return prepare_cmd(hba, Packet); -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruGetNextTargetLun ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, - IN OUT UINT8 **Target, - IN OUT UINT64 *Lun - ) -{ - SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This); - struct hisi_hba *hba = SasV1Info->hba; - UINT8 ScsiId[TARGET_MAX_BYTES]; - UINT8 TargetId; - - if (*Target == NULL || Lun == NULL) { - return EFI_INVALID_PARAMETER; - } - - SetMem (ScsiId, TARGET_MAX_BYTES, 0xFF); - - TargetId = (*Target)[0]; - - if (TargetId == MAX_TARGET_ID) { - return EFI_NOT_FOUND; - } - - if (CompareMem(*Target, ScsiId, TARGET_MAX_BYTES) == 0) { - SetMem (*Target, TARGET_MAX_BYTES,0); - } else { - (*Target)[0] = (UINT8) (hba->LatestTargetId + 1); - } - - *Lun = 0; - - // - // Update the LatestTargetId. - // - hba->LatestTargetId = (*Target)[0]; - hba->LatestLun = *Lun; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruBuildDevicePath ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, - IN UINT8 *Target, - IN UINT64 Lun, - IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath - ) -{ - SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This); - - *DevicePath = DuplicateDevicePath ((EFI_DEVICE_PATH_PROTOCOL *)(SasV1Info->DevicePath)); - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruGetTargetLun ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, - IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, - OUT UINT8 **Target, - OUT UINT64 *Lun - ) -{ - return EFI_UNSUPPORTED; -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruResetChannel ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This - ) -{ - - return EFI_UNSUPPORTED; -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruResetTarget ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, - IN UINT8 *Target, - IN UINT64 Lun - ) -{ - - return EFI_UNSUPPORTED; -} - -STATIC -EFI_STATUS -EFIAPI -SasV1ExtScsiPassThruGetNextTarget ( - IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, - IN OUT UINT8 **Target - ) -{ - - return EFI_UNSUPPORTED; -} - -STATIC EFI_EXT_SCSI_PASS_THRU_PROTOCOL SasV1ExtScsiPassThruProtocolTemplate = { - NULL, - SasV1ExtScsiPassThruFunction, - SasV1ExtScsiPassThruGetNextTargetLun, - SasV1ExtScsiPassThruBuildDevicePath, - SasV1ExtScsiPassThruGetTargetLun, - SasV1ExtScsiPassThruResetChannel, - SasV1ExtScsiPassThruResetTarget, - SasV1ExtScsiPassThruGetNextTarget -}; - -EFI_STATUS -EFIAPI -SasDriverBindingSupported ( - IN EFI_DRIVER_BINDING_PROTOCOL *This, - IN EFI_HANDLE Controller, - IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath - ) -{ - PLATFORM_SAS_PROTOCOL *plat; - EFI_STATUS Status; - - Status = gBS->OpenProtocol ( - Controller, - &gPlatformSasProtocolGuid, - (VOID **) &plat, - This->DriverBindingHandle, - Controller, - EFI_OPEN_PROTOCOL_BY_DRIVER - ); - if (Status == EFI_ALREADY_STARTED) { - return EFI_SUCCESS; - } - if (EFI_ERROR (Status)) { - return Status; - } - - // - // Close the Sas Host used to perform the supported test - // - gBS->CloseProtocol ( - Controller, - &gPlatformSasProtocolGuid, - This->DriverBindingHandle, - Controller - ); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -SasDriverBindingStart ( - IN EFI_DRIVER_BINDING_PROTOCOL *This, - IN EFI_HANDLE Controller, - IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath - ) -{ - EFI_STATUS Status; - PLATFORM_SAS_PROTOCOL *plat; - SAS_V1_INFO *SasV1Info = NULL; - SAS_V1_TRANSPORT_DEVICE_PATH *DevicePath; - UINT32 val, base; - int i, phy_id = 0; - struct hisi_sas_itct *itct; - struct hisi_hba *hba; - - Status = gBS->OpenProtocol ( - Controller, - &gPlatformSasProtocolGuid, - (VOID **) &plat, - This->DriverBindingHandle, - Controller, - EFI_OPEN_PROTOCOL_BY_DRIVER - ); - - if (EFI_ERROR (Status)) { - if (Status == EFI_ALREADY_STARTED) { - return EFI_SUCCESS; - } - return Status; - } - - SasV1Info = AllocateZeroPool (sizeof (SAS_V1_INFO)); - ASSERT (SasV1Info); - SasV1Info->Signature = SAS_DEVICE_SIGNATURE; - - SasV1Info->hba = AllocateZeroPool (sizeof(struct hisi_hba)); - ASSERT (SasV1Info->hba); - hba = SasV1Info->hba; - base = hba->base = plat->BaseAddr; - - sas_init(SasV1Info, plat); - - // Wait for sas controller phyup happen - MicroSecondDelay(100000); - - for (i = 0; i < PHY_CNT; i++) { - val = PHY_READ_REG32(base, CHL_INT2, i); - - if (val & CHL_INT2_SL_PHY_ENA) { - phy_id = i; - } - } - - itct = &hba->itct[0]; //device_id = 0 - - hba->port_id = (READ_REG32(base, PHY_PORT_NUM_MA) >> (4 * phy_id)) & 0xf; - // Setup itct - itct->qw0 = 0x355; - itct->sas_addr = PHY_READ_REG32(base, RX_IDAF_DWORD3, phy_id); - itct->sas_addr = itct->sas_addr << 32 | PHY_READ_REG32(base, RX_IDAF_DWORD4, phy_id); - itct->qw2 = 0; - - // Clear phyup - PHY_WRITE_REG32(base, CHL_INT2, phy_id, CHL_INT2_SL_PHY_ENA); - val = PHY_READ_REG32(base, CHL_INT0, phy_id); - val &= ~CHL_INT0_PHYCTRL_NOTRDY; - PHY_WRITE_REG32(base, CHL_INT0, phy_id, val); - PHY_WRITE_REG32(base, CHL_INT0_MSK, phy_id, 0x3ce3ee); - - // Need notify - val = PHY_READ_REG32(base, SL_CONTROL, phy_id); - val |= SL_CONTROL_NOTIFY_EN; - PHY_WRITE_REG32(base, SL_CONTROL, phy_id, val); - // wait 100ms required for notify takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c - MicroSecondDelay(100000); - val = PHY_READ_REG32(base, SL_CONTROL, phy_id); - val &= ~SL_CONTROL_NOTIFY_EN; - PHY_WRITE_REG32(base, SL_CONTROL, phy_id, val); - - CopyMem (&SasV1Info->ExtScsiPassThru, &SasV1ExtScsiPassThruProtocolTemplate, sizeof (EFI_EXT_SCSI_PASS_THRU_PROTOCOL)); - SasV1Info->ExtScsiPassThruMode.AdapterId = 2; - SasV1Info->ExtScsiPassThruMode.Attributes = EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL | EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL; - SasV1Info->ExtScsiPassThruMode.IoAlign = 64; //cache line align - SasV1Info->ExtScsiPassThru.Mode = &SasV1Info->ExtScsiPassThruMode; - - DevicePath = (SAS_V1_TRANSPORT_DEVICE_PATH *)CreateDeviceNode ( - HARDWARE_DEVICE_PATH, - HW_VENDOR_DP, - sizeof (SAS_V1_TRANSPORT_DEVICE_PATH)); - ASSERT (DevicePath != NULL); - SasV1Info->DevicePath = DevicePath; - - CopyMem (&DevicePath->Vendor.Guid, &gPlatformSasProtocolGuid, sizeof (EFI_GUID)); - DevicePath->PhysBase = base; - SetDevicePathNodeLength (&DevicePath->Vendor, - sizeof (*DevicePath) - sizeof (DevicePath->End)); - SetDevicePathEndNode (&DevicePath->End); - - Status = gBS->InstallMultipleProtocolInterfaces ( - &Controller, - &gEfiDevicePathProtocolGuid, DevicePath, - &gEfiExtScsiPassThruProtocolGuid, &SasV1Info->ExtScsiPassThru, - NULL); - ASSERT_EFI_ERROR (Status); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -SasDriverBindingStop ( - IN EFI_DRIVER_BINDING_PROTOCOL *This, - IN EFI_HANDLE Controller, - IN UINTN NumberOfChildren, - IN EFI_HANDLE *ChildHandleBuffer - ) -{ - SAS_V1_INFO *SasV1Info; - EFI_STATUS Status; - EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsi; - int i, s; - - Status = gBS->OpenProtocol ( - Controller, - &gEfiExtScsiPassThruProtocolGuid, - (VOID **) &ExtScsi, - This->DriverBindingHandle, - Controller, - EFI_OPEN_PROTOCOL_GET_PROTOCOL - ); - if (EFI_ERROR (Status)) { - return Status; - } - - SasV1Info = SAS_FROM_PASS_THRU(ExtScsi); - - Status = gBS->UninstallMultipleProtocolInterfaces ( - Controller, - &gEfiDevicePathProtocolGuid, - SasV1Info->DevicePath, - &gEfiExtScsiPassThruProtocolGuid, - &SasV1Info->ExtScsiPassThru, - NULL); - if (!EFI_ERROR (Status)) { - gBS->CloseProtocol ( - Controller, - &gPlatformSasProtocolGuid, - This->DriverBindingHandle, - Controller - ); - - gBS->CloseEvent (SasV1Info->TimerEvent); - - for (i = 0; i < QUEUE_CNT; i++) { - s = sizeof(struct hisi_sas_cmd_hdr) * QUEUE_SLOTS; - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->cmd_hdr[i]); - s = sizeof(struct hisi_sas_complete_hdr) * QUEUE_SLOTS; - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->complete_hdr[i]); - s = sizeof(struct hisi_sas_sts) * QUEUE_SLOTS; - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->status_buf[i]); - s = sizeof(struct hisi_sas_cmd) * QUEUE_SLOTS; - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->command_table[i]); - s = sizeof(struct hisi_sas_sge_page) * QUEUE_SLOTS; - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->sge[i]); - } - - s = SLOT_ENTRIES * sizeof(struct hisi_sas_iost); - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->iost); - s = SLOT_ENTRIES * sizeof(struct hisi_sas_breakpoint); - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->breakpoint); - s = MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct); - DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->itct); - - FreePool (SasV1Info->hba->slots); - FreePool (SasV1Info->hba); - FreePool (SasV1Info); - return EFI_SUCCESS; - } - return Status; -} - -EFI_DRIVER_BINDING_PROTOCOL gSasDriverBinding = { - SasDriverBindingSupported, - SasDriverBindingStart, - SasDriverBindingStop, - 0xa, - NULL, - NULL -}; - -EFI_STATUS -SasV1Initialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - return EfiLibInstallDriverBindingComponentName2 ( - ImageHandle, - SystemTable, - &gSasDriverBinding, - ImageHandle, - NULL, - NULL - ); -} diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf deleted file mode 100644 index 01a6a9ad865236799063bac81234f567d59c9a57..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf +++ /dev/null @@ -1,39 +0,0 @@ -#/** @file -# -# Copyright (c) 2016 Linaro Ltd. -# Copyright (c) 2016 Hisilicon Limited. -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = SasV1Dxe - FILE_GUID = 2b235921-8405-4219-a461-972a3a60969c - MODULE_TYPE = UEFI_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = SasV1Initialize - - -[Sources.common] - SasV1Dxe.c - -[Packages] - ArmPkg/ArmPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - DmaLib - IoLib - MemoryAllocationLib - PcdLib - TimerLib - UefiDriverEntryPoint - UefiLib - -[Protocols] - gEfiExtScsiPassThruProtocolGuid - gPlatformSasProtocolGuid diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c deleted file mode 100644 index 24cdf84ee5b941cd4473762b8e2b82246c0830b5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c +++ /dev/null @@ -1,215 +0,0 @@ -/** @file -* -* Copyright (c) 2015 - 2020, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "AddSmbiosType9.h" - -extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[]; -extern UINT8 OemGetPcieSlotNumber (); - -VOID -EFIAPI -UpdateSmbiosType9Info ( - IN OUT SMBIOS_TABLE_TYPE9 *Type9Record -) -{ - EFI_STATUS Status; - UINTN HandleIndex; - EFI_HANDLE *HandleBuffer; - UINTN HandleCount; - EFI_PCI_IO_PROTOCOL *PciIo; - UINTN SegmentNumber; - UINTN BusNumber; - UINTN DeviceNumber; - UINTN FunctionNumber; - UINTN Index; - REPORT_PCIEDIDVID2BMC ReportPcieDidVid[PCIEDEVICE_REPORT_MAX]; - - GetPciDidVid ((VOID *)ReportPcieDidVid); - - Status = gBS->LocateHandleBuffer ( - ByProtocol, - &gEfiPciIoProtocolGuid, - NULL, - &HandleCount, - &HandleBuffer - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); - gBS->FreePool ((VOID *)HandleBuffer); - return; - } - - for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { - Status = gBS->HandleProtocol ( - HandleBuffer[HandleIndex], - &gEfiPciIoProtocolGuid, - (VOID **)&PciIo - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", __func__, __LINE__, Status)); - continue; - } - (VOID)PciIo->GetLocation (PciIo, &SegmentNumber, &BusNumber, &DeviceNumber, &FunctionNumber); - for (Index = 0; Index < sizeof(ReportPcieDidVid) / sizeof(REPORT_PCIEDIDVID2BMC); Index++) { - if (Type9Record->SlotID == ReportPcieDidVid[Index].Slot + 1) { - if ((BusNumber == ReportPcieDidVid[Index].Bus) && (DeviceNumber == ReportPcieDidVid[Index].Device)) { - DEBUG ((DEBUG_ERROR, "PCIe device plot in slot Seg %d bdf %d %d %d\r\n", - SegmentNumber, BusNumber, DeviceNumber, FunctionNumber)); - Type9Record->SegmentGroupNum = SegmentNumber; - Type9Record->BusNum = BusNumber; - Type9Record->DevFuncNum = (DeviceNumber << 3) | FunctionNumber; - Type9Record->CurrentUsage = SlotUsageInUse; - break; - } - } - } - } - - gBS->FreePool ((VOID *)HandleBuffer); - return; -} - -STATIC -VOID -EmptySmbiosType9 ( - EFI_SMBIOS_PROTOCOL *Smbios - ) -{ - EFI_STATUS Status; - EFI_SMBIOS_TYPE SmbiosType; - EFI_SMBIOS_HANDLE SmbiosHandle; - EFI_SMBIOS_TABLE_HEADER *Record; - - do { - SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - SmbiosType = EFI_SMBIOS_TYPE_SYSTEM_SLOTS; - Status = Smbios->GetNext (Smbios, &SmbiosHandle, &SmbiosType, &Record, NULL); - if (!EFI_ERROR (Status)) { - Status = Smbios->Remove (Smbios, SmbiosHandle); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Remove System Slot Failed. Status : %r\n", - __func__, __LINE__, Status)); - break; - } - } - } while (SmbiosHandle != SMBIOS_HANDLE_PI_RESERVED); - - return; -} - -STATIC -EFI_STATUS -AddSmbiosType9Record ( - EFI_SMBIOS_PROTOCOL *Smbios, - SMBIOS_TABLE_TYPE9 *Type9Record - ) -{ - EFI_STATUS Status; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE9 *SmbiosRecord; - CHAR8 *OptionalStrStart; - CHAR16 SlotDesignation[SMBIOS_STRING_MAX_LENGTH]; - UINTN SlotStrLen; - - SlotStrLen = UnicodeSPrint ( - SlotDesignation, - SMBIOS_STRING_MAX_LENGTH * 2, - L"PCIE Slot%d", - Type9Record->SlotID); - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9) + SlotStrLen + 1 + 1); - if (SmbiosRecord == NULL) { - DEBUG ((DEBUG_ERROR, "AllocateZeroPool Failed for SmbiosRecord.\n")); - return EFI_OUT_OF_RESOURCES; - } - - (VOID)CopyMem (SmbiosRecord, Type9Record, sizeof (SMBIOS_TABLE_TYPE9)); - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9); - OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); - Status = UnicodeStrToAsciiStrS (SlotDesignation, OptionalStrStart, SlotStrLen + 1); - ASSERT_EFI_ERROR (Status); - - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - Status = Smbios->Add (Smbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)SmbiosRecord); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Add Smbios Type09 Failed! %r\n", Status)); - } - - FreePool (SmbiosRecord); - return Status; -} - -STATIC -VOID -HandleSmbiosType9 ( - EFI_SMBIOS_PROTOCOL *Smbios - ) -{ - EFI_STATUS Status; - SMBIOS_TABLE_TYPE9 *Type9Record; - UINT8 RecordCount; - UINT8 Index; - - RecordCount = OemGetPcieSlotNumber (); - if (RecordCount == 0) { - return; - } - - EmptySmbiosType9 (Smbios); - Status = EFI_SUCCESS; - for (Index = 0; Index < RecordCount; Index++) { - if (gPcieSlotInfo[Index].Hdr.Type != EFI_SMBIOS_TYPE_SYSTEM_SLOTS) { - continue; - } - - Type9Record = &gPcieSlotInfo[Index]; - - UpdateSmbiosType9Info (Type9Record); - - Status = AddSmbiosType9Record (Smbios, Type9Record); - if (EFI_ERROR (Status)) { - break; - } - } - - return; -} - -EFI_STATUS -EFIAPI -AddSmbiosType9Entry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_SMBIOS_PROTOCOL *Smbios; - - Status = gBS->LocateProtocol ( - &gEfiSmbiosProtocolGuid, - NULL, - (VOID **) &Smbios - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] LocateProtocol Failed. Status : %r\n", - __func__, __LINE__, Status)); - return Status; - } - - HandleSmbiosType9 (Smbios); - - return Status; -} - diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h deleted file mode 100644 index 1f07c0e1f3644f834b89b68d0b20c7c80becf272..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _ADD_SMBIOS_TYPE9_H_ -#define _ADD_SMBIOS_TYPE9_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf deleted file mode 100644 index 279d8487cfe2459abd5b7519962f10e72a2f1324..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf +++ /dev/null @@ -1,44 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AddSmbiosType9 - FILE_GUID = 7AE6F104-66DF-48EF-B5A3-5050BF4908F0 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = AddSmbiosType9Entry - -[Sources] - AddSmbiosType9.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseMemoryLib - MemoryAllocationLib - DebugLib - UefiLib - UefiDriverEntryPoint - HisiOemMiscLib - -[Protocols] - gEfiSmbiosProtocolGuid - gEfiPciIoProtocolGuid - -[Guids] - -[Pcd] - -[Depex] - gEfiSmbiosProtocolGuid AND - gEfiPciIoProtocolGuid diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c deleted file mode 100644 index 81377657dd52d9f66a81e35bd03dc4c2cf623c8a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c +++ /dev/null @@ -1,762 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include "MemorySubClass.h" - -EFI_SMBIOS_PROTOCOL *mSmbios = NULL; -EFI_HII_HANDLE mHiiHandle; - -UINT8 mMaxSkt; -UINT8 mMaxCh; - -VOID -SmbiosGetManufacturer ( - IN UINT8 MfgIdLSB, - IN UINT8 MfgIdMSB, - OUT CHAR16 *Manufacturer -) -{ - UINT32 Index = 0; - - (VOID)StrCpyS(Manufacturer, SMBIOS_STRING_MAX_LENGTH - 1, L"Unknown"); - while (JEP106[Index].MfgIdLSB != 0xFF && JEP106[Index].MfgIdMSB != 0xFF ) - { - if (JEP106[Index].MfgIdLSB == MfgIdLSB && JEP106[Index].MfgIdMSB == MfgIdMSB) - { - (VOID)StrCpyS (Manufacturer, SMBIOS_STRING_MAX_LENGTH - 1, JEP106[Index].Name); - break; - } - Index++; - } -} - -VOID -SmbiosGetPartNumber ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm, - OUT CHAR16 *PartNumber - ) -{ - CHAR16 StringBuffer2[SMBIOS_STRING_MAX_LENGTH]; - UINT32 Index2; - - (VOID)StrCpyS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, L""); - if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3) - { - for (Index2 = 0; Index2 < SPD_MODULE_PART; Index2++) - { - UnicodeSPrint (StringBuffer2, SMBIOS_STRING_MAX_LENGTH - 1, L"%c", pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdModPart[Index2]); - (VOID)StrCatS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, StringBuffer2); - } - } - else - { - for (Index2 = 0; Index2 < SPD_MODULE_PART_DDR4; Index2++) - { - UnicodeSPrint (StringBuffer2, SMBIOS_STRING_MAX_LENGTH - 1, L"%c", pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdModPartDDR4[Index2]); - (VOID)StrCatS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, StringBuffer2); - } - } - - return; -} - -VOID -SmbiosGetSerialNumber ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm, - OUT CHAR16 *SerialNumber - ) -{ - UINT32 Temp; - - Temp = SwapBytes32 (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdSerialNum); - - UnicodeSPrint(SerialNumber, SMBIOS_STRING_MAX_LENGTH, L"0x%08x", Temp); - - return; -} - -BOOLEAN -IsDimmPresent ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm -) -{ - if (pGblData->Channel[Skt][Ch].Enabled == FALSE || - pGblData->Channel[Skt][Ch].Dimm[Dimm].Enabled == FALSE) - { - return FALSE; - } - else - { - return TRUE; - } -} - -UINT8 -SmbiosGetMemoryType ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm -) -{ - UINT8 MemoryType; - - if(!IsDimmPresent(pGblData, Skt, Ch, Dimm)) - { - return MemoryTypeUnknown; - } - - if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3) - { - MemoryType = MemoryTypeDdr3; - } - else if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR4) - { - MemoryType = MemoryTypeDdr4; - } - else - { - MemoryType = MemoryTypeUnknown; - } - - return MemoryType; -} - -VOID -SmbiosGetTypeDetail ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm, - IN OUT MEMORY_DEVICE_TYPE_DETAIL *TypeDetail -) -{ - if (NULL == TypeDetail) - { - return; - } - - if(!IsDimmPresent(pGblData, Skt, Ch, Dimm)) - { - TypeDetail->Unknown = 1; - return; - } - - switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].ModuleType) - { - case SPD_UDIMM: - TypeDetail->Unbuffered = 1; - break; - - case SPD_LRDIMM: - TypeDetail->LrDimm = 1; - break; - - case SPD_RDIMM: - TypeDetail->Registered = 1; - break; - - default: - TypeDetail->Unknown = 1; - break; - } -} - -VOID -SmbiosGetDimmVoltageInfo ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm, - IN OUT SMBIOS_TABLE_TYPE17 *Type17Record - -) -{ - if(!IsDimmPresent(pGblData, Skt, Ch, Dimm)) - { - return; - } - - if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3) - { - Type17Record->MinimumVoltage = 1250; - Type17Record->MaximumVoltage = 1500; - - switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdVdd) - { - case SPD_VDD_150: - Type17Record->ConfiguredVoltage = 1500; - break; - - case SPD_VDD_135: - Type17Record->ConfiguredVoltage = 1350; - break; - - case SPD_VDD_125: - Type17Record->ConfiguredVoltage = 1250; - break; - - default: - break; - } - } - else if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR4) - { - Type17Record->MinimumVoltage = 1200; - Type17Record->MaximumVoltage = 2000; - switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdVdd) - { - case SPD_VDD_120: - Type17Record->ConfiguredVoltage = 1200; - break; - - default: - break; - } - } -} - -VOID -SmbiosGetMemoryDevicesNumber ( - IN OUT UINT16 *NumberOfDevices -) -{ - UINT8 Skt, Ch, Dimm; - - for(Skt = 0; Skt < mMaxSkt; Skt++) - { - for(Ch = 0; Ch < mMaxCh; Ch++) - { - for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++) - { - (*NumberOfDevices)++; - } - } - } -} - -UINT8 -SmbiosGetPartitionWidth ( -) -{ - - UINT8 Skt, Ch, Dimm; - UINT8 PartitionWidth = 0; - - for(Skt = 0; Skt < mMaxSkt; Skt++) - { - for(Ch = 0; Ch < mMaxCh; Ch++) - { - for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++) - { - PartitionWidth++; - } - } - } - - return PartitionWidth; -} - -EFI_STATUS -SmbiosAddType16Table ( - IN GBL_INTERFACE *pGblData, - OUT EFI_SMBIOS_HANDLE *MemArraySmbiosHandle - ) -{ - EFI_STATUS Status; - UINT64 MemoryCapacity; - SMBIOS_TABLE_TYPE16 *Type16Record; - - UINT16 NumberOfMemoryDevices = 0; - - SmbiosGetMemoryDevicesNumber (&NumberOfMemoryDevices); - - MemoryCapacity = (UINT64) LShiftU64 (NumberOfMemoryDevices * MAX_DIMM_SIZE, 20); // GB to KB. - - // - // Type 16 SMBIOS Record - // - Type16Record = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1); - if (NULL == Type16Record) - { - return EFI_OUT_OF_RESOURCES; - } - - Type16Record->Hdr.Type = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY; - Type16Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE16); - Type16Record->Hdr.Handle = 0x0; - Type16Record->Location = MemoryArrayLocationSystemBoard; - Type16Record->Use = MemoryArrayUseSystemMemory; - Type16Record->MemoryErrorInformationHandle = 0xFFFE; - Type16Record->NumberOfMemoryDevices = NumberOfMemoryDevices; - - if(pGblData->EccEn) - { - Type16Record->MemoryErrorCorrection = MemoryErrorCorrectionSingleBitEcc; - } - else - { - Type16Record->MemoryErrorCorrection = MemoryErrorCorrectionNone; - } - - if (MemoryCapacity >= 0x80000000) - { - Type16Record->MaximumCapacity = 0x80000000; // in KB; - Type16Record->ExtendedMaximumCapacity = MemoryCapacity << 10; // Extended Max capacity should be stored in bytes. - } - else - { - Type16Record->MaximumCapacity = (UINT32)MemoryCapacity; // Max capacity should be stored in kilo bytes. - Type16Record->ExtendedMaximumCapacity = 0; - } - - *MemArraySmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - Status = mSmbios->Add (mSmbios, NULL, MemArraySmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type16Record); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type16 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(Type16Record); - return Status; -} - -EFI_STATUS -SmbiosAddType19Table ( - IN GBL_INTERFACE *pGblData, - IN EFI_SMBIOS_HANDLE MemArraySmbiosHandle - ) -{ - EFI_STATUS Status; - UINT32 MemInfoTotalMem; - UINT64 TotalMemorySize; - EFI_SMBIOS_HANDLE MemArrayMappedAddrSmbiosHandle; - SMBIOS_TABLE_TYPE19 *Type19Record; - - MemInfoTotalMem = pGblData->MemSize; // In MB - - if (MemInfoTotalMem == 0) - { - return EFI_NOT_FOUND; - } - - TotalMemorySize = (UINT64) LShiftU64 (MemInfoTotalMem, 10); // MB to KB. - - // - // Type 19 SMBIOS Record - // - Type19Record = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE19) + 1 + 1); - if (NULL == Type19Record) - { - return EFI_OUT_OF_RESOURCES; - } - - Type19Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS; - Type19Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE19); - Type19Record->Hdr.Handle = 0x0; - Type19Record->StartingAddress = 0x0; - Type19Record->EndingAddress = (UINT32) (TotalMemorySize - 1); // in KB; - Type19Record->MemoryArrayHandle = MemArraySmbiosHandle; - Type19Record->PartitionWidth = SmbiosGetPartitionWidth (); - Type19Record->ExtendedStartingAddress = 0x0; - Type19Record->ExtendedEndingAddress = 0x0; - - MemArrayMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - Status = mSmbios->Add (mSmbios, NULL, &MemArrayMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type19Record); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type19 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(Type19Record); - return Status; -} - - -EFI_STATUS -SmbiosAddType17Table ( - IN GBL_INTERFACE *pGblData, - IN UINT8 Skt, - IN UINT8 Ch, - IN UINT8 Dimm, - IN EFI_SMBIOS_HANDLE MemArraySmbiosHandle - ) -{ - EFI_STATUS Status; - SMBIOS_TABLE_TYPE17 *Type17Record; - EFI_SMBIOS_HANDLE MemDevSmbiosHandle; - UINTN TableSize; - - UINTN StringBufferSize; - EFI_STRING StringBuffer; - UINT16 MemInfoMemFreq; - UINT16 MemoryTotalWidth; - UINT16 MemoryDataWidth; - UINT16 MemoryDeviceSize; - UINT16 MemorySpeed; - UINT8 Attributes; - UINT32 MemoryDeviceExtendSize; - UINT16 CfgMemorySpeed; - - CHAR8 *OptionalStrStart; - UINTN DeviceLocatorStrLen; - UINTN BankLocatorStrLen; - UINTN ManufactureStrLen; - UINTN SerialNumberStrLen; - UINTN AssertTagStrLen; - UINTN PartNumberStrLen; - EFI_STRING DeviceLocatorStr; - EFI_STRING BankLocatorStr; - EFI_STRING ManufactureStr; - EFI_STRING SerialNumberStr; - EFI_STRING AssertTagStr; - EFI_STRING PartNumberStr; - EFI_STRING_ID DeviceLocator; - - Type17Record = NULL; - DeviceLocatorStr = NULL; - BankLocatorStr = NULL; - ManufactureStr = NULL; - SerialNumberStr = NULL; - AssertTagStr = NULL; - PartNumberStr = NULL; - - MemoryTotalWidth = 0; - MemoryDataWidth = 0; - MemoryDeviceSize = 0; - MemoryDeviceExtendSize = 0; - MemorySpeed = 0; - Attributes = 0; - CfgMemorySpeed = 0; - - // - // Allocate Buffers - // - StringBufferSize = (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH; - StringBuffer = AllocateZeroPool (StringBufferSize); - if(NULL == StringBuffer) - { - return EFI_OUT_OF_RESOURCES; - } - - - // - // Manufacture - // - ManufactureStr = AllocateZeroPool (StringBufferSize); - if(NULL == ManufactureStr) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_STR_BUF; - } - UnicodeSPrint(ManufactureStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM"); - - // - // SerialNumber - // - SerialNumberStr = AllocateZeroPool (StringBufferSize); - if(NULL == SerialNumberStr) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_STR_MAN; - } - UnicodeSPrint(SerialNumberStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM"); - - // - // AssetTag - // - AssertTagStr = AllocateZeroPool (StringBufferSize); - if(NULL == AssertTagStr) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_STR_SN; - } - UnicodeSPrint(AssertTagStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM"); - - // - // PartNumber - // - PartNumberStr = AllocateZeroPool (StringBufferSize); - if(NULL == PartNumberStr) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_STR_AST; - } - UnicodeSPrint(PartNumberStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM"); - - - if(IsDimmPresent(pGblData, Skt, Ch, Dimm)) - { - MemoryDataWidth = pGblData->Channel[Skt][Ch].Dimm[Dimm].PrimaryBusWidth; - MemoryTotalWidth = MemoryDataWidth + pGblData->Channel[Skt][Ch].Dimm[Dimm].ExtensionBusWidth; - - MemoryDeviceSize = pGblData->Channel[Skt][Ch].Dimm[Dimm].DimmSize; //in MB - MemoryDeviceExtendSize = 0; - - if (MemoryDeviceSize >= 0x7fff) - { - MemoryDeviceExtendSize = MemoryDeviceSize; // in MB - MemoryDeviceSize = 0x7fff; // max value - } - - MemInfoMemFreq = pGblData->Freq; - MemorySpeed = pGblData->Channel[Skt][Ch].Dimm[Dimm].DimmSpeed; - Attributes = pGblData->Channel[Skt][Ch].Dimm[Dimm].RankNum; - CfgMemorySpeed = MemInfoMemFreq; - - // - // Manufacturer - // - SmbiosGetManufacturer (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdMMfgId & 0xFF, - pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdMMfgId >> 8, - ManufactureStr - ); - - // - // SerialNumber - // - SmbiosGetSerialNumber(pGblData, Skt, Ch, Dimm, SerialNumberStr); - - // - // AssetTag - // - UnicodeSPrint(AssertTagStr, SMBIOS_STRING_MAX_LENGTH - 1, L"Unknown"); - - // - // PartNumber - // - SmbiosGetPartNumber(pGblData, Skt, Ch, Dimm, PartNumberStr); - } - - // - // DeviceLocator - // - DeviceLocatorStr = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH); - if(NULL == DeviceLocatorStr) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_STR_PN; - } - DeviceLocator = gDimmToDevLocator[Skt][Ch][Dimm]; - if (DeviceLocator != 0xFFFF) - { - UnicodeSPrint(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"DIMM%x%x%x ", Skt, Ch, Dimm); - StringBuffer = HiiGetPackageString (&gEfiCallerIdGuid, DeviceLocator, NULL); - (VOID)StrCatS(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, StringBuffer); - } - else - { - UnicodeSPrint(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"DIMM%x%x%x", Skt, Ch, Dimm); - } - DeviceLocatorStrLen = StrLen (DeviceLocatorStr); - - // - // BankLocator - // - BankLocatorStr = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH); - if(NULL == BankLocatorStr) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_STR_DEV; - } - UnicodeSPrint(BankLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"SOCKET %x CHANNEL %x DIMM %x", Skt, Ch, Dimm); - BankLocatorStrLen = StrLen (BankLocatorStr); - - ManufactureStrLen = StrLen (ManufactureStr); - SerialNumberStrLen = StrLen (SerialNumberStr); - AssertTagStrLen = StrLen (AssertTagStr); - PartNumberStrLen = StrLen (PartNumberStr); - - // - // Report Type 17 SMBIOS Record - // - TableSize = sizeof(SMBIOS_TABLE_TYPE17) + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1 + AssertTagStrLen + 1 + PartNumberStrLen + 1 + 1; - Type17Record = AllocateZeroPool (TableSize); - if(NULL == Type17Record) - { - Status = EFI_OUT_OF_RESOURCES; - goto FREE_BL; - } - - Type17Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE; - Type17Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17); - Type17Record->Hdr.Handle = 0; - Type17Record->MemoryArrayHandle = MemArraySmbiosHandle; - Type17Record->MemoryErrorInformationHandle = 0xFFFE; - Type17Record->TotalWidth = MemoryTotalWidth; - Type17Record->DataWidth = MemoryDataWidth; - Type17Record->Size = MemoryDeviceSize; // in MB - Type17Record->FormFactor = MemoryFormFactorDimm; - Type17Record->DeviceLocator = 1; - Type17Record->BankLocator = 2; - Type17Record->MemoryType = SmbiosGetMemoryType (pGblData, Skt, Ch, Dimm); - - Type17Record->TypeDetail.Synchronous = 1; - - SmbiosGetTypeDetail (pGblData, Skt, Ch, Dimm, &(Type17Record->TypeDetail)); - - Type17Record->Speed = MemorySpeed; // in MHZ - Type17Record->Manufacturer = 3; - Type17Record->SerialNumber = 4; - Type17Record->AssetTag = 5; - Type17Record->PartNumber = 6; - Type17Record->Attributes = Attributes; - Type17Record->ExtendedSize = MemoryDeviceExtendSize; - Type17Record->ConfiguredMemoryClockSpeed = CfgMemorySpeed; - // - // Add for smbios 2.8.0 - // - SmbiosGetDimmVoltageInfo (pGblData, Skt, Ch, Dimm, Type17Record); - - OptionalStrStart = (CHAR8 *) (Type17Record + 1); - Status = UnicodeStrToAsciiStrS (DeviceLocatorStr, OptionalStrStart, DeviceLocatorStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (BankLocatorStr, OptionalStrStart + DeviceLocatorStrLen + 1, BankLocatorStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ManufactureStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1, ManufactureStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (SerialNumberStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1, SerialNumberStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (AssertTagStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1, AssertTagStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (PartNumberStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1 + AssertTagStrLen + 1, PartNumberStrLen + 1); - ASSERT_EFI_ERROR (Status); - - MemDevSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - Status = mSmbios->Add (mSmbios, NULL, &MemDevSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type17Record); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type17 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool (Type17Record); - -FREE_BL: - FreePool (BankLocatorStr); - -FREE_STR_DEV: - FreePool (DeviceLocatorStr); - -FREE_STR_PN: - FreePool (PartNumberStr); - -FREE_STR_AST: - FreePool (AssertTagStr); - -FREE_STR_SN: - FreePool (SerialNumberStr); - -FREE_STR_MAN: - FreePool (ManufactureStr); - -FREE_STR_BUF: - FreePool (StringBuffer); - - return Status; -} - - -/** - Standard EFI driver point. This driver locates the MemoryConfigurationData Variable, - if it exists, add the related SMBIOS tables by PI SMBIOS protocol. - - @param ImageHandle Handle for the image of this driver - @param SystemTable Pointer to the EFI System Table - - @retval EFI_SUCCESS The data was successfully stored. - -**/ -EFI_STATUS -EFIAPI -MemorySubClassEntryPoint( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_SMBIOS_PROTOCOL *Smbios; - EFI_HOB_GUID_TYPE *GuidHob; - GBL_INTERFACE *pGblData; - EFI_SMBIOS_HANDLE MemArraySmbiosHandle; - UINT8 Skt, Ch, Dimm; - - GuidHob = GetFirstGuidHob(&gHisiEfiMemoryMapGuid); - if(NULL == GuidHob) - { - DEBUG((DEBUG_ERROR, "Could not get MemoryMap Guid hob. %r\n")); - return EFI_NOT_FOUND; - } - pGblData = (GBL_INTERFACE*) GET_GUID_HOB_DATA(GuidHob); - - // - // Locate dependent protocols - // - Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status)); - return Status; - } - mSmbios = Smbios; - - // - // Add our default strings to the HII database. They will be modified later. - // - mHiiHandle = OemGetPackages(); - if(NULL == mHiiHandle) - { - return EFI_OUT_OF_RESOURCES; - } - - mMaxSkt = OemGetSocketNumber(); - mMaxCh = OemGetDdrChannel(); - // Get DIMM slot number on Socket 0 Channel 0 - // TODO: Assume all channels have same slot number - - Status = SmbiosAddType16Table (pGblData, &MemArraySmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Smbios Add Type16 Table Failed. %r\n", Status)); - return Status; - } - - Status = SmbiosAddType19Table (pGblData, MemArraySmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Smbios Add Type19 Table Failed. %r\n", Status)); - return Status; - } - - for(Skt = 0; Skt < mMaxSkt; Skt++) - { - for(Ch = 0; Ch < mMaxCh; Ch++) - { - for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++) - { - Status = SmbiosAddType17Table (pGblData, Skt, Ch, Dimm, MemArraySmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Smbios Add Type17 Table Failed. %r\n", Status)); - } - } - } - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h deleted file mode 100644 index cd47eefc34287ec3eb16bf93a261a8c1a8f8b1d5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h +++ /dev/null @@ -1,71 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _MEMORY_SUBCLASS_DRIVER_H -#define _MEMORY_SUBCLASS_DRIVER_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -// -// This is the generated header file which includes whatever needs to be exported (strings + IFR) -// - -extern UINT8 MemorySubClassStrings[]; - -struct SPD_JEDEC_MANUFACTURER -{ - UINT8 MfgIdLSB; - UINT8 MfgIdMSB; - CHAR16 *Name; -}; - -struct SPD_JEDEC_MANUFACTURER JEP106[] = { - { 0, 0x10, L"NEC"}, - { 0, 0x2c, L"Micron"}, - { 0, 0x3d, L"Tektronix"}, - { 0, 0x97, L"TI"}, - { 0, 0xad, L"Hynix"}, - { 0, 0xb3, L"IDT"}, - { 0, 0xc1, L"Infineon"}, - { 0, 0xce, L"Samsung"}, - { 1, 0x94, L"Smart"}, - { 1, 0x98, L"Kingston"}, - { 2, 0xc8, L"Agilent"}, - { 2, 0xfe, L"Elpida"}, - { 3, 0x0b, L"Nanya"}, - { 4, 0x43, L"Ramaxel"}, - { 4, 0xb3, L"Inphi"}, - { 5, 0x51, L"Qimonda"}, - { 5, 0x57, L"AENEON"}, - { 0xFF, 0xFF, L""} -}; - - - -#endif diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf deleted file mode 100644 index 67b9af5a810d9e47ac33ad52262672c3a49ca93c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf +++ /dev/null @@ -1,52 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = MemorySubClass - FILE_GUID = 62194F1A-5A0D-4B33-9EF0-7D05C6CB923A - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = MemorySubClassEntryPoint - -[Sources] - MemorySubClassStrings.uni - MemorySubClass.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - HobLib - HiiLib - MemoryAllocationLib - BaseMemoryLib - BaseLib - DebugLib - PrintLib - PlatformSysCtrlLib - PcdLib - -[Protocols] - gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED - -[Pcd] - -[Guids] - gHisiEfiMemoryMapGuid - -[Depex] - gEfiSmbiosProtocolGuid - - diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni deleted file mode 100644 index cabc63cc99ff43bdcb4404e1447f0cebafcb7d6b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni +++ /dev/null @@ -1,24 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved. -// Copyright (c) 2015, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// --*/ - -/=# - -#langdef en-US "English" - -// -// Begin English Language Strings -// - -#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" - -// -// End English Language Strings -// - diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c deleted file mode 100644 index d0d43fa02926aac28d262b3d484d3cee9ee3d83d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ /dev/null @@ -1,727 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "ProcessorSubClass.h" - -EFI_HII_HANDLE mHiiHandle; - -EFI_SMBIOS_PROTOCOL *mSmbios; - -SMBIOS_TABLE_TYPE7 mSmbiosCacheTable[] = { - //L1 Instruction Cache - { - { //Header - EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type - sizeof(SMBIOS_TABLE_TYPE7), //Length - 0 //Handle - }, - 1, //SocketDesignation - 0, //CacheConfiguration - 0, //MaximumCacheSize - 48, //InstalledSize - { //SupportedSRAMType - 0 - }, - { //CurrentSRAMType - 0 - }, - 0, //CacheSpeed - CacheErrorParity, //ErrorCorrectionType - CacheTypeInstruction, //SystemCacheType - CacheAssociativity8Way //Associativity - }, - - //L1 Data Cache - { - { //Header - EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type - sizeof(SMBIOS_TABLE_TYPE7), //Length - 0 //Handle - }, - 1, //SocketDesignation - 0, //CacheConfiguration - 0, //MaximumCacheSize - 32, //InstalledSize - { //SupportedSRAMType - 0 - }, - { //CurrentSRAMType - 0 - }, - 0, //CacheSpeed - CacheErrorSingleBit, //ErrorCorrectionType - CacheTypeData, //SystemCacheType - CacheAssociativity8Way //Associativity - }, - - //L2 Cache - { - { //Header - EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type - sizeof(SMBIOS_TABLE_TYPE7), //Length - 0 //Handle - }, - 1, //SocketDesignation - 0, //CacheConfiguration - 0, //MaximumCacheSize - 4096, //InstalledSize - { //SupportedSRAMType - 0 - }, - { //CurrentSRAMType - 0 - }, - 0, //CacheSpeed - CacheErrorSingleBit, //ErrorCorrectionType - CacheTypeUnified, //SystemCacheType - CacheAssociativity8Way //Associativity - }, - - //L3 Cache - { - { //Header - EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type - sizeof(SMBIOS_TABLE_TYPE7), //Length - 0 //Handle - }, - 1, //SocketDesignation - 0, //CacheConfiguration - 0, //MaximumCacheSize - 16384, //InstalledSize - { //SupportedSRAMType - 0 - }, - { //CurrentSRAMType - 0 - }, - 0, //CacheSpeed - CacheErrorSingleBit, //ErrorCorrectionType - CacheTypeUnified, //SystemCacheType - CacheAssociativity16Way //Associativity - } -}; - -SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = { - //CPU0 - { - { //Header - EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type - sizeof(SMBIOS_TABLE_TYPE4), //Length - 0 //Handle - }, - 1, //Socket - CentralProcessor, //ProcessorType - ProcessorFamilyIndicatorFamily2, //ProcessorFamily - 2, //ProcessorManufacture - { //ProcessorId - { //Signature - 0 - }, - { //FeatureFlags - 0 - } - }, - 3, //ProcessorVersion - { //Voltage - 0 - }, - EXTERNAL_CLOCK, //ExternalClock - CPU_MAX_SPEED, //MaxSpeed - 0, //CurrentSpeed - 0, //Status - ProcessorUpgradeUnknown, //ProcessorUpgrade - 0xFFFF, //L1CacheHandle - 0xFFFF, //L2CacheHandle - 0xFFFF, //L3CacheHandle - 4, //SerialNumber - 5, //AssetTag - 6, //PartNumber - - 0, //CoreCount - 0, //EnabledCoreCount - 0, //ThreadCount - 0, //ProcessorCharacteristics - - ProcessorFamilyARM, //ProcessorFamily2 - - 0, //CoreCount2 - 0, //EnabledCoreCount2 - 0 //ThreadCount2 - }, - - //CPU1 - { - { //Header - EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type - sizeof(SMBIOS_TABLE_TYPE4), //Length - 0 //Handle - }, - 1, //Socket - CentralProcessor, //ProcessorType - ProcessorFamilyIndicatorFamily2, //ProcessorFamily - 2, //ProcessorManufacture - { //ProcessorId - { //Signature - 0 - }, - { //FeatureFlags - 0 - } - }, - 3, //ProcessorVersion - { //Voltage - 0 - }, - EXTERNAL_CLOCK, //ExternalClock - CPU_MAX_SPEED, //MaxSpeed - 0, //CurrentSpeed - 0, //Status - ProcessorUpgradeUnknown, //ProcessorUpgrade - 0xFFFF, //L1CacheHandle - 0xFFFF, //L2CacheHandle - 0xFFFF, //L3CacheHandle - 4, //SerialNumber - 5, //AssetTag - 6, //PartNumber - - 0, //CoreCount - 0, //EnabledCoreCount - 0, //ThreadCount - 0, //ProcessorCharacteristics - - ProcessorFamilyARM, //ProcessorFamily2 - - 0, //CoreCount2 - 0, //EnabledCoreCount2 - 0 //ThreadCount2 - } -}; - - -UINT16 -GetCpuFrequency ( - IN UINT8 ProcessorNumber -) -{ - return (UINT16)(PlatformGetCpuFreq(ProcessorNumber)/1000/1000); -} - -UINTN -GetCacheSocketStr ( - IN UINT8 CacheLevel, - OUT CHAR16 *CacheSocketStr - ) -{ - UINTN CacheSocketStrLen; - - if(CacheLevel == CPU_CACHE_L1_Instruction) - { - CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Instruction Cache", CacheLevel + 1); - } - else if(CacheLevel == CPU_CACHE_L1_Data) - { - CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Data Cache", CacheLevel); - } - else - { - CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Cache", CacheLevel); - } - - return CacheSocketStrLen; -} - -VOID -UpdateSmbiosCacheTable ( - IN UINT8 CacheLevel - ) -{ - UINT16 CoreCount; - UINT32 TotalSize; - UINT32 CacheSize; - UINT16 MaximumCacheSize; - UINT16 InstalledSize; - CACHE_CONFIGURATION CacheConfig; - CACHE_SRAM_TYPE_DATA CacheSramType = {0}; - - CoreCount = 16; // Default value is 16 Core - - // - // Set Cache Configuration - // - CacheConfig.Bits.Socketed = 0; // Not Socketed - CacheConfig.Bits.Reserved1 = 0; // - CacheConfig.Bits.Location = 0; // Internal - CacheConfig.Bits.Enable = 1; // Enabled - CacheConfig.Bits.Reserved2 = 0; - if(CacheLevel == CPU_CACHE_L1_Instruction || CacheLevel == CPU_CACHE_L1_Data) - { - CacheConfig.Bits.Level = 0; - CacheConfig.Bits.OperationalMode = 1; // Write Back - } - else - { - CacheConfig.Bits.Level = CacheLevel - 1; - CacheConfig.Bits.OperationalMode = 2; // Varies with Memory Address - } - - mSmbiosCacheTable[CacheLevel].CacheConfiguration = CacheConfig.Data; - - // - // Set Cache Size - // - CacheSize = mSmbiosCacheTable[CacheLevel].InstalledSize; - if (PACKAGE_16CORE != PlatformGetPackageType()) // 32 Core - { - CoreCount = CoreCount * 2; - - if (CacheLevel > 1) - { - CacheSize = CacheSize * 2; - } - } - - if(CacheLevel <= 1) - { - TotalSize = CacheSize * CoreCount; - } - else - { - TotalSize = CacheSize; - } - - if((TotalSize >> 15) == 0) // 1K granularity - { - MaximumCacheSize = (UINT16)TotalSize; - InstalledSize = (UINT16)TotalSize; - } - else // 64K granularity - { - MaximumCacheSize = (UINT16)(TotalSize >> 6); - InstalledSize = (UINT16)(TotalSize >> 6); - - // Set BIT15 to 1 - MaximumCacheSize |= BIT15; - InstalledSize |= BIT15; - } - - mSmbiosCacheTable[CacheLevel].MaximumCacheSize = MaximumCacheSize; - mSmbiosCacheTable[CacheLevel].InstalledSize = InstalledSize; - - // - // Set SRAM Type - // - CacheSramType.Synchronous = 1; - (VOID)CopyMem(&mSmbiosCacheTable[CacheLevel].SupportedSRAMType, &CacheSramType, sizeof(CACHE_SRAM_TYPE_DATA)); - (VOID)CopyMem(&mSmbiosCacheTable[CacheLevel].CurrentSRAMType, &CacheSramType, sizeof(CACHE_SRAM_TYPE_DATA)); -} - -/** - Add Type 7 SMBIOS Record for Cache Information. - - @param[in] ProcessorNumber Processor number of specified processor. - @param[out] L1CacheHandle Pointer to the handle of the L1 Cache SMBIOS record. - @param[out] L2CacheHandle Pointer to the handle of the L2 Cache SMBIOS record. - @param[out] L3CacheHandle Pointer to the handle of the L3 Cache SMBIOS record. - -**/ -EFI_STATUS -AddSmbiosCacheTypeTable ( - IN UINTN ProcessorNumber, - OUT EFI_SMBIOS_HANDLE *L1CacheHandle, - OUT EFI_SMBIOS_HANDLE *L2CacheHandle, - OUT EFI_SMBIOS_HANDLE *L3CacheHandle - ) -{ - EFI_STATUS Status; - SMBIOS_TABLE_TYPE7 *Type7Record; - EFI_SMBIOS_HANDLE SmbiosHandle; - UINTN TableSize; - UINT8 CacheLevel; - CHAR8 *OptionalStrStart; - EFI_STRING CacheSocketStr; - UINTN CacheSocketStrLen; - UINTN StringBufferSize; - - Status = EFI_SUCCESS; - - // - // Get Cache information - // - for(CacheLevel = 0; CacheLevel < MAX_CACHE_LEVEL; CacheLevel++) - { - Type7Record = NULL; - - if(mSmbiosCacheTable[CacheLevel].InstalledSize == 0) - { - continue; - } - - // - // Update Cache information - // - if (mSmbiosCacheTable[CacheLevel].MaximumCacheSize == 0) - { - UpdateSmbiosCacheTable (CacheLevel); - } - - StringBufferSize = sizeof(CHAR16) * SMBIOS_STRING_MAX_LENGTH; - CacheSocketStr = AllocateZeroPool(StringBufferSize); - if (CacheSocketStr == NULL) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - CacheSocketStrLen = GetCacheSocketStr (CacheLevel, CacheSocketStr); - - TableSize = sizeof(SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1; - Type7Record = AllocateZeroPool (TableSize); - if (Type7Record == NULL) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(Type7Record, &mSmbiosCacheTable[CacheLevel], sizeof (SMBIOS_TABLE_TYPE7)); - - OptionalStrStart = (CHAR8 *) (Type7Record + 1); - Status = UnicodeStrToAsciiStrS (CacheSocketStr, OptionalStrStart, CacheSocketStrLen + 1); - ASSERT_EFI_ERROR (Status); - - SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type7Record); - if (EFI_ERROR (Status)) - { - goto Exit; - } - - // Config L1/L2/L3 Cache Handle - switch(CacheLevel) - { - case CPU_CACHE_L1_Instruction: - case CPU_CACHE_L1_Data: - *L1CacheHandle = SmbiosHandle; - break; - case CPU_CACHE_L2: - *L2CacheHandle = SmbiosHandle; - break; - case CPU_CACHE_L3: - *L3CacheHandle = SmbiosHandle; - break; - default : - break; - } -Exit: - if(Type7Record != NULL) - { - FreePool (Type7Record); - } - if(CacheSocketStr != NULL) - { - FreePool (CacheSocketStr); - CacheSocketStr = NULL; - } - } - - return Status; -} - -/** - Add Type 4 SMBIOS Record for Processor Information. - - @param[in] ProcessorNumber Processor number of specified processor. - -**/ -EFI_STATUS -AddSmbiosProcessorTypeTable ( - IN UINTN ProcessorNumber - ) -{ - EFI_STATUS Status; - SMBIOS_TABLE_TYPE4 *Type4Record; - EFI_SMBIOS_HANDLE SmbiosHandle; - EFI_SMBIOS_HANDLE L1CacheHandle; - EFI_SMBIOS_HANDLE L2CacheHandle; - EFI_SMBIOS_HANDLE L3CacheHandle; - - CHAR8 *OptionalStrStart; - EFI_STRING_ID ProcessorManu; - EFI_STRING_ID ProcessorVersion; - EFI_STRING_ID SerialNumber; - EFI_STRING_ID AssetTag; - EFI_STRING_ID PartNumber; - EFI_STRING ProcessorSocketStr; - EFI_STRING ProcessorManuStr; - EFI_STRING ProcessorVersionStr; - EFI_STRING SerialNumberStr; - EFI_STRING AssetTagStr; - EFI_STRING PartNumberStr; - UINTN ProcessorSocketStrLen; - UINTN ProcessorManuStrLen; - UINTN ProcessorVersionStrLen; - UINTN SerialNumberStrLen; - UINTN AssetTagStrLen; - UINTN PartNumberStrLen; - UINTN StringBufferSize; - UINTN TotalSize; - - UINT8 Voltage; - UINT16 CoreCount; - UINT16 CoreEnabled; - UINT16 ThreadCount; - UINT16 CurrentSpeed; - PROCESSOR_STATUS_DATA ProcessorStatus = {{0}}; - PROCESSOR_CHARACTERISTICS_DATA ProcessorCharacteristics = {{0}}; - - CHAR16 *CpuVersion; - EFI_STRING_ID TokenToUpdate; - - UINT64 *ProcessorId; - Type4Record = NULL; - ProcessorManuStr = NULL; - ProcessorVersionStr = NULL; - SerialNumberStr = NULL; - AssetTagStr = NULL; - PartNumberStr = NULL; - - if(OemIsSocketPresent(ProcessorNumber)) //CPU is present - { - Voltage = BIT7 | 9; // 0.9V - - Status = AddSmbiosCacheTypeTable (ProcessorNumber, &L1CacheHandle, &L2CacheHandle, &L3CacheHandle); - if(EFI_ERROR(Status)) - { - return Status; - } - - CurrentSpeed = GetCpuFrequency(ProcessorNumber); - - CoreCount = PlatformGetCoreCount(); - CoreEnabled = CoreCount; - ThreadCount = CoreCount; - - CpuVersion = (CHAR16 *) PcdGetPtr (PcdCPUInfo); - if (StrLen(CpuVersion) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_PROCESSOR_VERSION); - HiiSetString (mHiiHandle, TokenToUpdate, CpuVersion, NULL); - } - - ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE); - ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION); - SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER); - AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG); - PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER); - - // Processor Status - ProcessorStatus.Bits.CpuStatus = 1; // CPU Enabled - ProcessorStatus.Bits.Reserved1 = 0; - ProcessorStatus.Bits.SocketPopulated = 1; // CPU Socket Populated - ProcessorStatus.Bits.Reserved2 = 0; - - // Processor Characteristics - ProcessorCharacteristics.Bits.Reserved = 0; - ProcessorCharacteristics.Bits.Capable64Bit = 1; // 64-bit Capable - ProcessorCharacteristics.Bits.Unknown = 0; - ProcessorCharacteristics.Bits.EnhancedVirtualization = 1; - ProcessorCharacteristics.Bits.HardwareThread = 0; - ProcessorCharacteristics.Bits.MultiCore = 1; - ProcessorCharacteristics.Bits.ExecuteProtection = 1; - ProcessorCharacteristics.Bits.PowerPerformanceControl = 1; - ProcessorCharacteristics.Bits.Reserved2 = 0; - } - else - { - Voltage = 0; - CurrentSpeed = 0; - CoreCount = 0; - CoreEnabled = 0; - ThreadCount = 0; - L1CacheHandle = 0xFFFF; - L2CacheHandle = 0xFFFF; - L3CacheHandle = 0xFFFF; - - ProcessorManu = STRING_TOKEN (STR_PROCESSOR_UNKNOWN); - ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_UNKNOWN); - SerialNumber = STRING_TOKEN (STR_PROCESSOR_UNKNOWN); - AssetTag = STRING_TOKEN (STR_PROCESSOR_UNKNOWN); - PartNumber = STRING_TOKEN (STR_PROCESSOR_UNKNOWN); - } - - // Processor Socket Designation - StringBufferSize = sizeof(CHAR16) * SMBIOS_STRING_MAX_LENGTH; - ProcessorSocketStr = AllocateZeroPool(StringBufferSize); - if (ProcessorSocketStr == NULL) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - ProcessorSocketStrLen = UnicodeSPrint (ProcessorSocketStr, StringBufferSize, L"CPU%02d", ProcessorNumber + 1); - - // Processor Manufacture - ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL); - ProcessorManuStrLen = StrLen (ProcessorManuStr); - - // Processor Version - ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL); - ProcessorVersionStrLen = StrLen (ProcessorVersionStr); - - // Serial Number - SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL); - SerialNumberStrLen = StrLen (SerialNumberStr); - - // Asset Tag - AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL); - AssetTagStrLen = StrLen (AssetTagStr); - - // Part Number - PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL); - PartNumberStrLen = StrLen (PartNumberStr); - - TotalSize = sizeof (SMBIOS_TABLE_TYPE4) + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1 + AssetTagStrLen + 1 + PartNumberStrLen + 1 + 1; - Type4Record = AllocateZeroPool (TotalSize); - if (Type4Record == NULL) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(Type4Record, &mSmbiosProcessorTable[ProcessorNumber], sizeof (SMBIOS_TABLE_TYPE4)); - - *(UINT8 *) &Type4Record->Voltage = Voltage; - Type4Record->CurrentSpeed = CurrentSpeed; - Type4Record->Status = ProcessorStatus.Data; - Type4Record->L1CacheHandle = L1CacheHandle; - Type4Record->L2CacheHandle = L2CacheHandle; - Type4Record->L3CacheHandle = L3CacheHandle; - Type4Record->CoreCount = CoreCount; - Type4Record->EnabledCoreCount = CoreEnabled; - Type4Record->ThreadCount = ThreadCount; - Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data; - - Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); - ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); - *ProcessorId = ArmReadMidr(); - - OptionalStrStart = (CHAR8 *) (Type4Record + 1); - Status = UnicodeStrToAsciiStrS (ProcessorSocketStr, OptionalStrStart, ProcessorSocketStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ProcessorManuStr, OptionalStrStart + ProcessorSocketStrLen + 1, ProcessorManuStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ProcessorVersionStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1, ProcessorVersionStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (SerialNumberStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1, SerialNumberStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (AssetTagStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1, AssetTagStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (PartNumberStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1 + AssetTagStrLen + 1, PartNumberStrLen + 1); - ASSERT_EFI_ERROR (Status); - - SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type4Record); - if (EFI_ERROR (Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - FreePool (Type4Record); - -Exit: - if(ProcessorSocketStr != NULL) - { - FreePool (ProcessorSocketStr); - } - if(ProcessorManuStr != NULL) - { - FreePool (ProcessorManuStr); - } - if(ProcessorVersionStr != NULL) - { - FreePool (ProcessorVersionStr); - } - if(SerialNumberStr != NULL) - { - FreePool (SerialNumberStr); - } - if(AssetTagStr != NULL) - { - FreePool (AssetTagStr); - } - if(PartNumberStr != NULL) - { - FreePool (PartNumberStr); - } - - return Status; -} - -/** - Standard EFI driver point. This driver locates the ProcessorConfigurationData Variable, - if it exists, add the related SMBIOS tables by PI SMBIOS protocol. - - @param ImageHandle Handle for the image of this driver - @param SystemTable Pointer to the EFI System Table - - @retval EFI_SUCCESS The data was successfully stored. - -**/ -EFI_STATUS -EFIAPI -ProcessorSubClassEntryPoint( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - UINT32 SocketIndex; - - // - // Locate dependent protocols - // - Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&mSmbios); - if (EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status)); - return Status; - } - - // - // Add our default strings to the HII database. They will be modified later. - // - mHiiHandle = HiiAddPackages ( - &gEfiCallerIdGuid, - NULL, - ProcessorSubClassStrings, - NULL, - NULL - ); - if (mHiiHandle == NULL) - { - return EFI_OUT_OF_RESOURCES; - } - - // - // Add SMBIOS tables for populated sockets. - // - for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) - { - if((SocketIndex == 1) && !OemIsMpBoot()) - { - break; - } - Status = AddSmbiosProcessorTypeTable (SocketIndex); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "Add Processor Type Table Failed! %r.\n", Status)); - return Status; - } - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h deleted file mode 100644 index 7ed6696a1f2308a0cd99ea54af34b81d3b32cc50..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _PROCESSOR_SUBCLASS_DRIVER_H -#define _PROCESSOR_SUBCLASS_DRIVER_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -// -// This is the generated header file which includes whatever needs to be exported (strings + IFR) -// - -extern UINT8 ProcessorSubClassStrings[]; - -#define CPU_CACHE_L1_Instruction 0 -#define CPU_CACHE_L1_Data 1 -#define CPU_CACHE_L2 2 -#define CPU_CACHE_L3 3 -#define MAX_CACHE_LEVEL 4 - -#define EXTERNAL_CLOCK 50 //50 MHz -#define CPU_MAX_SPEED 2100 //2.1G - -// -// Cache Info -// -typedef struct { - UINT16 InstalledSize; //In KB - CACHE_TYPE_DATA SystemCacheType; - CACHE_ASSOCIATIVITY_DATA Associativity; -} CACHE_INFO; - -// -// Cache Configuration -// -typedef union { - struct { - UINT16 Level :3; - UINT16 Socketed :1; - UINT16 Reserved1 :1; - UINT16 Location :2; - UINT16 Enable :1; - UINT16 OperationalMode :2; - UINT16 Reserved2 :6; - } Bits; - UINT16 Data; -}CACHE_CONFIGURATION; - -// -// Processor Characteristics -// -typedef union { - struct { - UINT16 Reserved :1; - UINT16 Unknown :1; - UINT16 Capable64Bit :1; - UINT16 MultiCore :1; - UINT16 HardwareThread :1; - UINT16 ExecuteProtection :1; - UINT16 EnhancedVirtualization :1; - UINT16 PowerPerformanceControl :1; - UINT16 Reserved2 :8; - } Bits; - UINT16 Data; -} PROCESSOR_CHARACTERISTICS_DATA; - -#endif diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf deleted file mode 100644 index 433720f12900b0ca07af0b69a57d0f0595993e3a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf +++ /dev/null @@ -1,57 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ProcessorSubClass - FILE_GUID = 9B25B1EA-0FD4-455D-A450-AD640C8A9C1B - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = ProcessorSubClassEntryPoint - -[Sources] - ProcessorSubClassStrings.uni - ProcessorSubClass.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - IoLib - HiiLib - MemoryAllocationLib - BaseMemoryLib - BaseLib - DebugLib - PrintLib - PcdLib - - PlatformSysCtrlLib - HisiOemMiscLib - -[Protocols] - gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED - -[Pcd] - gHisiTokenSpaceGuid.PcdCPUInfo - -[Guids] - - -[Depex] - gEfiSmbiosProtocolGuid - - diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni deleted file mode 100644 index e81b1403e4c913e0fe68358cf45742dc2df1ba8d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni +++ /dev/null @@ -1,26 +0,0 @@ -///// @file -// -// Copyright (c) 2015, Hisilicon Limited. All rights reserved. -// Copyright (c) 2015, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -///// - -/=# - -#langdef en-US "English" - -// -// Processor Information -// -#string STR_PROCESSOR_SOCKET_DESIGNATION #language en-US "Hisilicon PhosphorV660 Processor" -#string STR_PROCESSOR_MANUFACTURE #language en-US "Hisilicon" -#string STR_PROCESSOR_VERSION #language en-US "Hi1610ES" -#string STR_PROCESSOR_SERIAL_NUMBER #language en-US "To be filled by O.E.M." -#string STR_PROCESSOR_ASSET_TAG #language en-US "To be filled by O.E.M." -#string STR_PROCESSOR_PART_NUMBER #language en-US "To be filled by O.E.M." -#string STR_PROCESSOR_UNKNOWN #language en-US "Unknown" - - - diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h deleted file mode 100644 index 4692eb71334e9440651e97c2efd5d3ba590a1a12..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h +++ /dev/null @@ -1,219 +0,0 @@ -/**@file - -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - SmbiosMisc.h - -Abstract: - - Header file for the SmbiosMisc Driver. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#ifndef _SMBIOS_MISC_DRIVER_H -#define _SMBIOS_MISC_DRIVER_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -// -// Data table entry update function. -// -typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) ( - IN VOID *RecordData, - IN EFI_SMBIOS_PROTOCOL *Smbios - ); - - -// -// Data table entry definition. -// -typedef struct { - // - // intermediat input data for SMBIOS record - // - VOID *RecordData; - EFI_MISC_SMBIOS_DATA_FUNCTION *Function; -} EFI_MISC_SMBIOS_DATA_TABLE; - - -// -// Data Table extern definitions. -// -#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \ -extern NAME1 NAME2 ## Data; \ -extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function; - - -// -// Data Table entries -// - -#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \ -{ \ - & NAME1 ## Data, \ - NAME2 ## Function \ -} - - -// -// Global definition macros. -// -#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \ - NAME1 NAME2 ## Data - -#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \ - EFI_STATUS EFIAPI NAME2 ## Function( \ - IN VOID *RecordData, \ - IN EFI_SMBIOS_PROTOCOL *Smbios \ - ) - -// -// Data Table Array Entries -// -extern EFI_HII_HANDLE mHiiHandle; - -typedef struct _EFI_TYPE11_OEM_STRING{ - UINT8 Offset; - EFI_STRING_ID RefOemDefineString; -} EFI_TYPE11_OEM_STRING; - -typedef struct _EFI_TYPE12_SYSTEM_CONFIGURATION_OPTIONS_STRING{ - UINT8 Offset; - EFI_STRING_ID RefType12SystemConfigurationOptionsString; -} EFI_TYPE12_SYSTEM_CONFIGURATION_OPTIONS_STRING; - -typedef struct _EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{ - UINT8 *LanguageSignature; - EFI_STRING_ID InstallableLanguageLongString; - EFI_STRING_ID InstallableLanguageAbbreviateString; -} EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING; - -typedef struct _EFI_TYPE40_ADDITIONAL_INFORMATION_ENTRY{ - UINT8 RefType; - UINT8 RefOffset; - EFI_STRING_ID RefString; - UINT8 Value; -} EFI_TYPE40_ADDITIONAL_INFORMATION_ENTRY; - -typedef enum { - STRING, - DATA, -} OEM_DEFINE_TYPE; - -typedef struct { - OEM_DEFINE_TYPE Type; - UINTN Token; - UINTN DataSize; -} OEM_DEFINE_INFO_STRING; - -typedef struct { - OEM_DEFINE_TYPE Type; - UINTN DataAddress; - UINTN DataSize; -} OEM_DEFINE_INFO_DATA; - -typedef union { - OEM_DEFINE_INFO_STRING DefineString; - OEM_DEFINE_INFO_DATA DefineData; -} EFI_OEM_DEFINE_ARRAY; - -typedef struct _DMI_STRING_STRUCTURE { - UINT8 Type; - UINT8 Offset; - UINT8 Valid; - UINT16 Length; - UINT8 String[1]; // Variable length field -} DMI_STRING_STRUCTURE; - -typedef struct { - UINT8 Type; // The SMBIOS structure type - UINT8 FixedOffset; // The offset of the string reference - // within the structure's fixed data. -} DMI_UPDATABLE_STRING; - -EFI_STATUS -FindString ( - IN UINT8 Type, - IN UINT8 Offset, - IN EFI_STRING_ID TokenToUpdate -); - -EFI_STATUS -FindUuid ( - EFI_GUID *Uuid -); - -EFI_STATUS -StringToBiosVeriosn ( - IN EFI_STRING_ID BiosVersionToken, - OUT UINT8 *MajorVersion, - OUT UINT8 *MinorVersion -); - - -/** - Logs SMBIOS record. - - @param [in] Buffer Pointer to the data buffer. - @param [in] SmbiosHandle Pointer for retrieve handle. - -**/ -EFI_STATUS -LogSmbiosData ( - IN UINT8 *Buffer, - IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle - ); - -/** - Get Link Type Handle. - - @param [in] SmbiosType Get this Type from SMBIOS table - @param [out] HandleArray Pointer to Hadndler array with has been free by caller - @param [out] HandleCount Pointer to Hadndler Counter - -**/ -VOID -GetLinkTypeHandle( - IN UINT8 SmbiosType, - OUT UINT16 **HandleArray, - OUT UINTN *HandleCount - ); - -typedef enum { - ProductNameType01, - SerialNumType01, - UuidType01, - SystemManufacturerType01, - AssertTagType02, - SrNumType02, - BoardManufacturerType02, - AssetTagType03, - SrNumType03, - VersionType03, - ChassisTypeType03 , - ManufacturerType03, -} GET_INFO_BMC_OFFSET; - -VOID UpdateSmbiosInfo (IN EFI_HII_HANDLE mHiiHandle, IN EFI_STRING_ID TokenToUpdate, IN UINT8 Offset); -EFI_STATUS GetUuidType1 (IN OUT EFI_GUID *Uuid); -EFI_STATUS IpmiGetChassisType (IN OUT UINT8 *Type); -#endif diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c deleted file mode 100644 index 94f1f86c531cc6478f854a8092b341753bc81261..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c +++ /dev/null @@ -1,52 +0,0 @@ -/**@file - -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - SmbiosMiscDataTable.c - -Abstract: - - This file provide OEM to config SMBIOS Misc Type. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE0, MiscBiosVendor, MiscBiosVendor) - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer, MiscSystemManufacturer) - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer, MiscChassisManufacturer) - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer) - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages, MiscNumberOfInstallableLanguages) - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE32, MiscBootInformation, MiscBootInformation) - MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE38, MiscIpmiDeviceInformation, MiscIpmiDeviceInformation) - - -EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[] = { - // Type0 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor), - // Type1 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer), - // Type3 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer), - // Type2 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer), - // Type13 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscNumberOfInstallableLanguages, MiscNumberOfInstallableLanguages), - // Type32 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBootInformation, MiscBootInformation), - // Type38 - MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscIpmiDeviceInformation, MiscIpmiDeviceInformation), -}; - - -// -// Number of Data Table entries. -// -UINTN mSmbiosMiscDataTableEntries = - (sizeof mSmbiosMiscDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE); diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf deleted file mode 100644 index e574c7209d4f7e4b98a869191204eeb49d26df98..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ /dev/null @@ -1,101 +0,0 @@ -## @file -# Component description file for SmbiosMisc instance. -# -# Parses the MiscSubclassDataTable and reports any generated data to the DataHub. -# All .uni file who tagged with "ToolCode="DUMMY"" in following file list is included by -# MiscSubclassDriver.uni file, the StrGather tool will expand MiscSubclassDriver.uni file -# and parse all .uni file. -# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015, Linaro Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -# Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -## - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = SmbiosMiscDxe - FILE_GUID = EF0C99B6-B1D3-4025-9405-BF6A560FE0E0 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = SmbiosMiscEntryPoint - -[Sources] - SmbiosMisc.h - SmbiosMiscDataTable.c - SmbiosMiscEntryPoint.c - SmbiosMiscLibString.uni - ./Type00/MiscBiosVendorData.c - ./Type00/MiscBiosVendorFunction.c - ./Type01/MiscSystemManufacturerData.c - ./Type01/MiscSystemManufacturerFunction.c - ./Type02/MiscBaseBoardManufacturerData.c - ./Type02/MiscBaseBoardManufacturerFunction.c - ./Type03/MiscChassisManufacturerData.c - ./Type03/MiscChassisManufacturerFunction.c - ./Type13/MiscNumberOfInstallableLanguagesData.c - ./Type13/MiscNumberOfInstallableLanguagesFunction.c - ./Type32/MiscBootInformationData.c - ./Type32/MiscBootInformationFunction.c - ./Type38/MiscIpmiDeviceInformationData.c - ./Type38/MiscIpmiDeviceInformationFunction.c - - ./Type09/MiscSystemSlotDesignationData.c - ./Type09/MiscSystemSlotDesignationFunction.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - PcdLib - HiiLib - MemoryAllocationLib - DevicePathLib - BaseMemoryLib - BaseLib - DebugLib - HisiOemMiscLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - UefiDriverEntryPoint - UefiLib - HobLib - - IpmiCmdLib - - -[Protocols] - gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED - -[Pcd] - gArmTokenSpaceGuid.PcdFdSize - gHisiTokenSpaceGuid.PcdFirmwareVendor - gHisiTokenSpaceGuid.PcdBiosVersionString - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString - - gHisiTokenSpaceGuid.PcdSystemProductName - gHisiTokenSpaceGuid.PcdSystemVersion - gHisiTokenSpaceGuid.PcdBaseBoardProductName - gHisiTokenSpaceGuid.PcdBaseBoardVersion - gArmTokenSpaceGuid.PcdFdBaseAddress - - gHisiTokenSpaceGuid.PcdBiosVersionForBmc - - gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang - -[Guids] - gEfiGenericVariableGuid - gVersionInfoHobGuid - -[Depex] - gEfiSmbiosProtocolGuid - - diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c deleted file mode 100644 index 2f284bf505cd5775a47001a195f42a3be68d4754..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c +++ /dev/null @@ -1,188 +0,0 @@ -/**@file - -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - SmbiosMiscEntryPoint.c - -Abstract: - - This driver parses the mSmbiosMiscDataTable structure and reports - any generated data using SMBIOS protocol. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - -#define MAX_HANDLE_COUNT 0x10 - -EFI_HANDLE mImageHandle; -EFI_HII_HANDLE mHiiHandle; -EFI_SMBIOS_PROTOCOL *mSmbios = NULL; - -// -// Data Table Array -// -extern EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[]; -// -// Data Table Array Entries -// -extern UINTN mSmbiosMiscDataTableEntries; - -extern UINT8 SmbiosMiscDxeStrings[]; - - - -/** - Standard EFI driver point. This driver parses the mSmbiosMiscDataTable - structure and reports any generated data using SMBIOS protocol. - - @param ImageHandle Handle for the image of this driver - @param SystemTable Pointer to the EFI System Table - - @retval EFI_SUCCESS The data was successfully stored. - -**/ -EFI_STATUS -EFIAPI -SmbiosMiscEntryPoint( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - UINTN Index; - EFI_STATUS EfiStatus; - EFI_SMBIOS_PROTOCOL *Smbios; - - mImageHandle = ImageHandle; - - EfiStatus = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios); - if (EFI_ERROR(EfiStatus)) - { - DEBUG((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus)); - return EfiStatus; - } - - mSmbios = Smbios; - - mHiiHandle = HiiAddPackages ( - &gEfiCallerIdGuid, - mImageHandle, - SmbiosMiscDxeStrings, - NULL - ); - if(mHiiHandle == NULL) - { - return EFI_OUT_OF_RESOURCES; - } - - for (Index = 0; Index < mSmbiosMiscDataTableEntries; ++Index) - { - // - // If the entry have a function pointer, just log the data. - // - if (mSmbiosMiscDataTable[Index].Function != NULL) - { - EfiStatus = (*mSmbiosMiscDataTable[Index].Function)( - mSmbiosMiscDataTable[Index].RecordData, - Smbios - ); - - if (EFI_ERROR(EfiStatus)) - { - DEBUG((DEBUG_ERROR, "Misc smbios store error. Index=%d, ReturnStatus=%r\n", Index, EfiStatus)); - return EfiStatus; - } - } - } - - return EfiStatus; -} - - -/** - Logs SMBIOS record. - - @param Buffer The data for the fixed portion of the SMBIOS record. The format of the record is - determined by EFI_SMBIOS_TABLE_HEADER.Type. The size of the formatted area is defined - by EFI_SMBIOS_TABLE_HEADER.Length and either followed by a double-null (0x0000) or - a set of null terminated strings and a null. - @param SmbiosHandle A unique handle will be assigned to the SMBIOS record. - - @retval EFI_SUCCESS Record was added. - @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system resources. - -**/ -EFI_STATUS -LogSmbiosData ( - IN UINT8 *Buffer, - IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle - ) -{ - EFI_STATUS Status; - - *SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - - Status = mSmbios->Add ( - mSmbios, - NULL, - SmbiosHandle, - (EFI_SMBIOS_TABLE_HEADER *)Buffer - ); - - return Status; -} - - -VOID -GetLinkTypeHandle( - IN UINT8 SmbiosType, - OUT UINT16 **HandleArray, - OUT UINTN *HandleCount - ) -{ - EFI_STATUS Status; - EFI_SMBIOS_HANDLE SmbiosHandle; - EFI_SMBIOS_TABLE_HEADER *LinkTypeData = NULL; - - if(mSmbios == NULL) - return ; - - SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; - - *HandleArray = AllocateZeroPool(sizeof(UINT16) * MAX_HANDLE_COUNT); - if (*HandleArray == NULL) - { - DEBUG ((DEBUG_INFO, "HandleArray allocate memory resource failed.\n")); - return; - } - - *HandleCount = 0; - - while(1) - { - Status = mSmbios->GetNext( - mSmbios, - &SmbiosHandle, - &SmbiosType, - &LinkTypeData, - NULL - ); - - if(!EFI_ERROR(Status)) - { - (*HandleArray)[*HandleCount] = LinkTypeData->Handle; - (*HandleCount)++; - } - else - { - break; - } - } -} - diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni deleted file mode 100644 index 50d43930ad4b33833ddda08f359b3f625775a367..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni +++ /dev/null @@ -1,22 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2015, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -// --*/ - - -/=# - -#langdef en-US "English" - -#include "./Type00/MiscBiosVendor.uni" -#include "./Type01/MiscSystemManufacturer.uni" -#include "./Type02/MiscBaseBoardManufacturer.uni" -#include "./Type03/MiscChassisManufacturer.uni" -#include "./Type13/MiscNumberOfInstallableLanguages.uni" -#include "./Type09/MiscSystemSlotDesignation.uni" diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni deleted file mode 100644 index 13e7a2410b587a9e636ce5e30a0c55a7585b4d62..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni +++ /dev/null @@ -1,19 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2015, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -// --*/ - -/=# - -//#string STR_MISC_BIOS_VENDOR #language en-US "Bios Vendor" -#string STR_MISC_BIOS_VERSION #language en-US "Bios Version" -//#string STR_MISC_BIOS_RELEASE_DATE #language en-US "Bios Release Date" - -#string STR_MISC_BIOS_VENDOR #language en-US "Huawei Technologies Co., Ltd." -#string STR_MISC_BIOS_RELEASE_DATE #language en-US "01/01/1900" diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c deleted file mode 100644 index fc0201f0d71173fa76b0a592de72b8629b5b9ffb..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c +++ /dev/null @@ -1,99 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscBiosVendorData.c - -Abstract: - - This file provide OEM to define Smbios Type0 Data - -Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/ - -**/ - - -#include "SmbiosMisc.h" - - -// -// Static (possibly build generated) Bios Vendor data. -// -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = { - { //Hdr - EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type, - 0, // Length, - 0 // Handle - }, - 1, //Vendor - 2, //BiosVersion - 0xE000, //BiosSegment - 3, //BiosReleaseDate - 0, //BiosSize - { //BiosCharacteristics - 0, // Reserved :2 - 0, // Unknown :1 - 0, // BiosCharacteristicsNotSupported :1 - 0, // IsaIsSupported :1 - 0, // McaIsSupported :1 - 0, // EisaIsSupported :1 - 1, // PciIsSupported :1 - 0, // PcmciaIsSupported :1 - 0, // PlugAndPlayIsSupported :1 - 0, // ApmIsSupported :1 - 1, // BiosIsUpgradable :1 - 1, // BiosShadowingAllowed :1 - 0, // VlVesaIsSupported :1 - 0, // EscdSupportIsAvailable :1 - 1, // BootFromCdIsSupported :1 - 1, // SelectableBootIsSupported :1 - 0, // RomBiosIsSocketed :1 - 0, // BootFromPcmciaIsSupported :1 - 1, // EDDSpecificationIsSupported :1 - 1, // JapaneseNecFloppyIsSupported :1 - 1, // JapaneseToshibaFloppyIsSupported :1 - 1, // Floppy525_360IsSupported :1 - 1, // Floppy525_12IsSupported :1 - 1, // Floppy35_720IsSupported :1 - 1, // Floppy35_288IsSupported :1 - 0, // PrintScreenIsSupported :1 - 1, // Keyboard8042IsSupported :1 - 0, // SerialIsSupported :1 - 0, // PrinterIsSupported :1 - 1, // CgaMonoIsSupported :1 - 0, // NecPc98 :1 - 0 // ReservedForVendor :32 - }, - - { - 0x03, //BIOSCharacteristicsExtensionBytes[0] - // { //BiosReserved - // 1, // AcpiIsSupported :1 - // 1, // UsbLegacyIsSupported :1 - // 0, // AgpIsSupported :1 - // 0, // I20BootIsSupported :1 - // 0, // Ls120BootIsSupported :1 - // 0, // AtapiZipDriveBootIsSupported :1 - // 0, // Boot1394IsSupported :1 - // 0 // SmartBatteryIsSupported :1 - // }, - 0x0D //BIOSCharacteristicsExtensionBytes[1] - // { //SystemReserved - // 1, //BiosBootSpecIsSupported :1 - // 0, //FunctionKeyNetworkBootIsSupported :1 - // 1, //TargetContentDistributionEnabled :1 - // 1, //UefiSpecificationSupported :1 - // 0, //VirtualMachineSupported :1 - // 0 //ExtensionByte2Reserved :3 - // }, - }, - 0, //SystemBiosMajorRelease; - 0, //SystemBiosMinorRelease; - 0xFF, //EmbeddedControllerFirmwareMajorRelease; - 0xFF //EmbeddedControllerFirmwareMinorRelease; -}; diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c deleted file mode 100644 index 135f86baffc899a311a2dd3fb3f759d56a9584b2..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c +++ /dev/null @@ -1,255 +0,0 @@ -/** @file - - Copyright (c) 2009, Intel Corporation. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - -Module Name: - - MiscBiosVendorData.c - -Abstract: - - This driver parses the mMiscSubclassDataTable structure and reports - any generated data to the DataHub. - -Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/ - ---*/ - -// -#include "SmbiosMisc.h" -#include -#include - - -/** - Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k' - as the unit. - - @param Value Pointer to Base2_Data - - @retval - -**/ -UINT8 -Base2ToByteWith64KUnit ( - IN UINTN Value - ) -{ - UINT8 Size; - - Size = Value / SIZE_64KB + (Value % SIZE_64KB + SIZE_64KB - 1) / SIZE_64KB; - - return Size; -} - - -/** - -**/ -VOID * -GetBiosReleaseDate ( - ) -{ - CHAR16 *ReleaseDate = NULL; - VERSION_INFO *Version; - VOID *Hob; - - ReleaseDate = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH); - if(NULL == ReleaseDate) - { - return NULL; - } - - Hob = GetFirstGuidHob (&gVersionInfoHobGuid); - if (Hob == NULL) { - DEBUG ((DEBUG_ERROR, "[%a:%d] Version info HOB not found!\n", __func__, __LINE__)); - return NULL; - } - - Version = GET_GUID_HOB_DATA (Hob); - (VOID)UnicodeSPrintAsciiFormat( ReleaseDate, - (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH, - "%02d/%02d/%4d", - Version->BuildTime.Month, - Version->BuildTime.Day, - Version->BuildTime.Year - ); - - return ReleaseDate; -} - -VOID * -GetBiosVersion ( - ) -{ - VERSION_INFO *Version; - VOID *Hob; - - Hob = GetFirstGuidHob (&gVersionInfoHobGuid); - if (Hob == NULL) { - DEBUG ((DEBUG_ERROR, "[%a:%d] Version info HOB not found!\n", __func__, __LINE__)); - return NULL; - } - Version = GET_GUID_HOB_DATA (Hob); - return Version->String; -} - - -/** - This function makes boot time changes to the contents of the - MiscBiosVendor (Type 0). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor) -{ - CHAR8 *OptionalStrStart; - UINTN VendorStrLen; - UINTN VerStrLen; - UINTN DateStrLen; - UINTN BiosPhysicalSizeHexValue; - CHAR16 *Vendor; - CHAR16 *Version; - CHAR16 *ReleaseDate; - CHAR16 *Char16String; - EFI_STATUS Status; - EFI_STRING_ID TokenToUpdate; - EFI_STRING_ID TokenToGet; - SMBIOS_TABLE_TYPE0 *SmbiosRecord; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE0 *InputData; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) - { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE0 *)RecordData; - - Vendor = (CHAR16 *) PcdGetPtr (PcdFirmwareVendor); - if (StrLen(Vendor) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR); - HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL); - } - - Version = GetBiosVersion(); - if (StrLen (Version) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION); - HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); - } - else - { - Version = (CHAR16 *) PcdGetPtr (PcdBiosVersionForBmc); - if (StrLen (Version) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION); - HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); - } - else - { - Version = (CHAR16 *) PcdGetPtr (PcdBiosVersionString); - if (StrLen (Version) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION); - HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); - } - } - } - - Char16String = GetBiosReleaseDate (); - if (StrLen(Char16String) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); - HiiSetString (mHiiHandle, TokenToUpdate, Char16String, NULL); - } - - TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR); - Vendor = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - VendorStrLen = StrLen(Vendor); - - - TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION); - Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - VerStrLen = StrLen(Version); - - - TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); - ReleaseDate = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - DateStrLen = StrLen(ReleaseDate); - - // - // Now update the BiosPhysicalSize - // - BiosPhysicalSizeHexValue = FixedPcdGet32 (PcdFdSize); - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1); - if(NULL == SmbiosRecord) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0); - SmbiosRecord->BiosSegment = (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) / 0x10000); - SmbiosRecord->BiosSize = Base2ToByteWith64KUnit(BiosPhysicalSizeHexValue) - 1; - - OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); - Status = UnicodeStrToAsciiStrS (Vendor, OptionalStrStart, VendorStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (Version, OptionalStrStart + VendorStrLen + 1, VerStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ReleaseDate, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1, DateStrLen + 1); - ASSERT_EFI_ERROR (Status); - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - -Exit: - if(Vendor != NULL) - { - FreePool(Vendor); - } - - if(Version != NULL) - { - FreePool(Version); - } - - if(ReleaseDate != NULL) - { - FreePool(ReleaseDate); - } - - if(Char16String != NULL) - { - FreePool(Char16String); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni deleted file mode 100644 index c9af547a4630373df5bde565caf807817e58a172..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni +++ /dev/null @@ -1,21 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2015, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -// --*/ - -/=# - -#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Huawei Technologies Co., Ltd." -//#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "To be filled by O.E.M." -#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "PANGEA" -//#string STR_MISC_SYSTEM_VERSION #language en-US "To be filled by O.E.M." -#string STR_MISC_SYSTEM_VERSION #language en-US "V200R002" -#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "To be filled by O.E.M." -#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "To be filled by O.E.M." -#string STR_MISC_SYSTEM_FAMILY #language en-US "To be filled by O.E.M." diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c deleted file mode 100644 index c2ffb8a1319e4cc6c65ee434e02a080e7c3542fe..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c +++ /dev/null @@ -1,46 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscSystemManufacturerData.c - -Abstract: - - This file provide OEM to define Smbios Type1 Data - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ - -**/ - -/* Modify list -DATA AUTHOR REASON -*/ - -#include "SmbiosMisc.h" - - -// -// Static (possibly build generated) System Manufacturer data. -// -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type, - 0, // Length, - 0 // Handle - }, - 1, // Manufacturer - 2, // ProductName - 3, // Version - 4, // SerialNumber - { // Uuid - 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa, 0xbb, 0xcc} - }, - SystemWakeupTypePowerSwitch, // SystemWakeupType - 5, // SKUNumber, - 6 // Family -}; diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c deleted file mode 100644 index 1d297f2218d516c864b1463bcdcbeb122358475a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c +++ /dev/null @@ -1,194 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscSystemManufacturerFunction.c - -Abstract: - - This driver parses the mMiscSubclassDataTable structure and reports - any generated data to smbios. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ - -**/ - -#include "SmbiosMisc.h" - -/** - This function makes boot time changes to the contents of the - MiscSystemManufacturer (Type 1). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) -{ - CHAR8 *OptionalStrStart; - UINTN ManuStrLen; - UINTN VerStrLen; - UINTN PdNameStrLen; - UINTN SerialNumStrLen; - UINTN SKUNumStrLen; - UINTN FamilyStrLen; - EFI_STRING Manufacturer; - EFI_STRING ProductName; - EFI_STRING Version; - EFI_STRING SerialNumber; - EFI_STRING SKUNumber; - EFI_STRING Family; - EFI_STRING_ID TokenToGet; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE1 *SmbiosRecord; - SMBIOS_TABLE_TYPE1 *InputData; - EFI_STATUS Status; - EFI_STRING_ID TokenToUpdate; - CHAR16 *Product; - CHAR16 *pVersion; - - EFI_GUID Uuid; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) - { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE1 *)RecordData; - - Product = (CHAR16 *) PcdGetPtr (PcdSystemProductName); - if (StrLen(Product) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); - HiiSetString (mHiiHandle, TokenToUpdate, Product, NULL); - } - - pVersion = (CHAR16 *) PcdGetPtr (PcdSystemVersion); - if (StrLen(pVersion) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); - HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL); - } - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumType01); - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), SystemManufacturerType01); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); - Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - ManuStrLen = StrLen(Manufacturer); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); - ProductName = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - PdNameStrLen = StrLen(ProductName); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); - Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - VerStrLen = StrLen(Version); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); - SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - SerialNumStrLen = StrLen(SerialNumber); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); - SKUNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - SKUNumStrLen = StrLen(SKUNumber); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY); - Family = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - FamilyStrLen = StrLen(Family); - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 - + PdNameStrLen + 1 - + VerStrLen + 1 - + SerialNumStrLen + 1 - + SKUNumStrLen + 1 - + FamilyStrLen + 1 + 1); - - if (NULL == SmbiosRecord) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE1)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1); - - SmbiosRecord->Uuid = InputData->Uuid; - Status = GetUuidType1 (&Uuid); - if (!EFI_ERROR (Status)) - { - SmbiosRecord->Uuid = Uuid; - } - - OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); - Status = UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ProductName, OptionalStrStart + ManuStrLen + 1, PdNameStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (Version, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1, VerStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (SerialNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1, SerialNumStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (SKUNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1, SKUNumStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (Family, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1, FamilyStrLen + 1); - ASSERT_EFI_ERROR (Status); - - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - -Exit: - if(Manufacturer != NULL) - { - FreePool(Manufacturer); - } - - if(ProductName != NULL) - { - FreePool(ProductName); - } - - if(Version != NULL) - { - FreePool(Version); - } - - if(SerialNumber != NULL) - { - FreePool(SerialNumber); - } - - if(SKUNumber != NULL) - { - FreePool(SKUNumber); - } - - if(Family != NULL) - { - FreePool(Family); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni deleted file mode 100644 index 73ad967b158dcbcf17e5f3a62569d0172ef13a64..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni +++ /dev/null @@ -1,21 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2015, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -// --*/ - -/=# - -#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Huawei Technologies Co., Ltd." -//#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "To Be Filled By O.E.M." -#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "STL2SPCA" -//#string STR_MISC_BASE_BOARD_VERSION #language en-US "To Be Filled By O.E.M." -#string STR_MISC_BASE_BOARD_VERSION #language en-US "V200R002" -#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "To Be Filled By O.E.M." -#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "To Be Filled By O.E.M." -#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "To Be Filled By O.E.M." diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c deleted file mode 100644 index 87c35b64f02cb2fbd6bc7b6ec86098e381b135d7..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c +++ /dev/null @@ -1,50 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscBaseBoardManufacturerData.c - -Abstract: - - This file provide OEM to define Smbios Type2 Data - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - -// -// Static (possibly build generated) Chassis Manufacturer data. -// -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = { - { // Hdr - EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type, - 0, // Length, - 0 // Handle - }, - 1, // BaseBoardManufacturer - 2, // BaseBoardProductName - 3, // BaseBoardVersion - 4, // BaseBoardSerialNumber - 5, // BaseBoardAssetTag - { // FeatureFlag - 1, // Motherboard :1 - 0, // RequiresDaughterCard :1 - 0, // Removable :1 - 1, // Replaceable :1 - 0, // HotSwappable :1 - 0 // Reserved :3 - }, - 6, // BaseBoardChassisLocation - 0, // ChassisHandle; - BaseBoardTypeMotherBoard, // BoardType; - 0, // NumberOfContainedObjectHandles; - { - 0 - } // ContainedObjectHandles[1]; -}; diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c deleted file mode 100644 index 052b3465359777ee4d9032c20933386e06b5575a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c +++ /dev/null @@ -1,198 +0,0 @@ -/** @file - - Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscBaseBoardManufacturerFunction.c - -Abstract: - - This driver parses the mSmbiosMiscDataTable structure and reports - any generated data using SMBIOS protocol. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - - -/** - This function makes basic board manufacturer to the contents of the - Misc Base Board Manufacturer (Type 2). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer) -{ - CHAR8 *OptionalStrStart; - UINTN ManuStrLen; - UINTN ProductNameStrLen; - UINTN VerStrLen; - UINTN SerialNumStrLen; - UINTN AssetTagStrLen; - UINTN ChassisLocaStrLen; - UINTN HandleCount = 0; - UINT16 *HandleArray = NULL; - CHAR16 *BaseBoardManufacturer; - CHAR16 *BaseBoardProductName; - CHAR16 *Version; - EFI_STRING SerialNumber; - EFI_STRING AssetTag; - EFI_STRING ChassisLocation; - EFI_STRING_ID TokenToGet; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE2 *SmbiosRecord; - SMBIOS_TABLE_TYPE2 *InputData = NULL; - EFI_STATUS Status; - - EFI_STRING_ID TokenToUpdate; - //CHAR16 *ProductName; - //CHAR16 *pVersion; - //uniBIOS_y00216284_018_end 2015-1-13 09:08:22 - - // - // First check for invalid parameters. - // - if (RecordData == NULL) - { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE2*)RecordData; - - BaseBoardProductName = (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName); - if (StrLen(BaseBoardProductName) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); - HiiSetString (mHiiHandle, TokenToUpdate, BaseBoardProductName, NULL); - } - - Version = (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion); - if (StrLen(Version) > 0) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); - HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); - } - - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG), AssertTagType02); - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER), SrNumType02); - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER), BoardManufacturerType02); - - TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); - BaseBoardManufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - ManuStrLen = StrLen(BaseBoardManufacturer); - - TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); - BaseBoardProductName = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - ProductNameStrLen = StrLen(BaseBoardProductName); - - TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); - Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - VerStrLen = StrLen(Version); - - TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER); - SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - SerialNumStrLen = StrLen(SerialNumber); - - TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG); - AssetTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - AssetTagStrLen = StrLen(AssetTag); - - TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION); - ChassisLocation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - ChassisLocaStrLen = StrLen(ChassisLocation); - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE2) + ManuStrLen + 1 - + ProductNameStrLen + 1 - + VerStrLen + 1 - + SerialNumStrLen + 1 - + AssetTagStrLen + 1 - + ChassisLocaStrLen + 1 + 1); - if (NULL == SmbiosRecord) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2)); - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2); - - // - // Update Contained objects Handle - // - SmbiosRecord->NumberOfContainedObjectHandles = 0; - GetLinkTypeHandle(EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleArray, &HandleCount); - if(HandleCount) - { - SmbiosRecord->ChassisHandle = HandleArray[0]; - } - - FreePool(HandleArray); - - OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); - Status = UnicodeStrToAsciiStrS (BaseBoardManufacturer, OptionalStrStart, ManuStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (BaseBoardProductName, OptionalStrStart + ManuStrLen + 1, ProductNameStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (Version, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1, VerStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (SerialNumber, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1, SerialNumStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (AssetTag, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1, AssetTagStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ChassisLocation, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssetTagStrLen + 1, ChassisLocaStrLen + 1); - ASSERT_EFI_ERROR (Status); - - Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - -Exit: - if(BaseBoardManufacturer != NULL) - { - FreePool(BaseBoardManufacturer); - } - - if(BaseBoardProductName != NULL) - { - FreePool(BaseBoardProductName); - } - - if(Version != NULL) - { - FreePool(Version); - } - - if(SerialNumber != NULL) - { - FreePool(SerialNumber); - } - - if(AssetTag != NULL) - { - FreePool(AssetTag); - } - - if(ChassisLocation != NULL) - { - FreePool(ChassisLocation); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni deleted file mode 100644 index 5487375753737b08d1be3b6d9c3807f46566a7f5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni +++ /dev/null @@ -1,18 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2015, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -// --*/ - -/=# - -#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Huawei Technologies Co., Ltd." -#string STR_MISC_CHASSIS_VERSION #language en-US "To Be Filled By O.E.M." -#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "To Be Filled By O.E.M." -#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "To Be Filled By O.E.M." -#string STR_MISC_CHASSIS_SKU_NUMBER #language en-US "To Be Filled By O.E.M." diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c deleted file mode 100644 index 846e1287cbd948bf323bd4960163adabd075bd62..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c +++ /dev/null @@ -1,60 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscChassisManufacturerData.c - -Abstract: - - This file provide OEM to define Smbios Type3 Data - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ -/* Modify list -DATA AUTHOR REASON -*/ - -#include "SmbiosMisc.h" - - -// -// Static (possibly build generated) Chassis Manufacturer data. -// -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type, - 0, // Length, - 0 // Handle - }, - 1, // Manufactrurer - MiscChassisTypeMainServerChassis, // Type - 2, // Version - 3, // SerialNumber - 4, // AssetTag - ChassisStateSafe, // BootupState - ChassisStateSafe, // PowerSupplyState - ChassisStateSafe, // ThermalState - ChassisSecurityStatusNone, // SecurityState - { - 0, // OemDefined[0] - 0, // OemDefined[1] - 0, // OemDefined[2] - 0 // OemDefined[3] - }, - 2, // Height - 1, // NumberofPowerCords - 0, // ContainedElementCount - 0, // ContainedElementRecordLength - { // ContainedElements[0] - { - 0, // ContainedElementType - 0, // ContainedElementMinimum - 0 // ContainedElementMaximum - } - } -}; diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c deleted file mode 100644 index f8384a11d268c01385b73df26a000220b3f1ed81..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c +++ /dev/null @@ -1,198 +0,0 @@ -/** @file - -Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscChassisManufacturerFunction.c - -Abstract: - - This driver parses the mMiscSubclassDataTable structure and reports - any generated data to smbios. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ -/* Modify list -DATA AUTHOR REASON -*/ - -#include "SmbiosMisc.h" - -UINT8 -GetChassisType ( -) -{ - EFI_STATUS Status; - UINT8 ChassisType; - Status = IpmiGetChassisType(&ChassisType); - if (EFI_ERROR(Status)) - { - return 0; - } - - return ChassisType; -} - -/** - This function makes boot time changes to the contents of the - MiscChassisManufacturer (Type 3). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer) -{ - CHAR8 *OptionalStrStart; - UINTN ManuStrLen; - UINTN VerStrLen; - UINTN AssertTagStrLen; - UINTN SerialNumStrLen; - UINTN ChaNumStrLen; - EFI_STRING Manufacturer; - EFI_STRING Version; - EFI_STRING SerialNumber; - EFI_STRING AssertTag; - EFI_STRING ChassisSkuNumber; - EFI_STRING_ID TokenToGet; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE3 *SmbiosRecord; - SMBIOS_TABLE_TYPE3 *InputData; - EFI_STATUS Status; - - UINT8 ContainedElementCount; - CONTAINED_ELEMENT ContainedElements = {0}; - UINT8 ExtendLength = 0; - - UINT8 ChassisType; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) - { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE3 *)RecordData; - - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG), AssetTagType03); - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER), SrNumType03); - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_VERSION), VersionType03); - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER), ManufacturerType03); - - TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); - Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - ManuStrLen = StrLen(Manufacturer); - - TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION); - Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - VerStrLen = StrLen(Version); - - TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); - SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - SerialNumStrLen = StrLen(SerialNumber); - - TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); - AssertTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - AssertTagStrLen = StrLen(AssertTag); - - TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER); - ChassisSkuNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - ChaNumStrLen = StrLen(ChassisSkuNumber); - - ContainedElementCount = InputData->ContainedElementCount; - - if (ContainedElementCount > 1) - { - ExtendLength = (ContainedElementCount - 1) * sizeof (CONTAINED_ELEMENT); - } - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1 - + ManuStrLen + 1 - + VerStrLen + 1 - + SerialNumStrLen + 1 - + AssertTagStrLen + 1 - + ChaNumStrLen + 1 + 1); - if (NULL == SmbiosRecord) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE3)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1; - - ChassisType = GetChassisType (); - if (ChassisType != 0) - { - SmbiosRecord->Type = ChassisType; - } - - //ContainedElements - (VOID)CopyMem(SmbiosRecord + 1, &ContainedElements, ExtendLength); - - //ChassisSkuNumber - *((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = 5; - - OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1); - Status = UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (Version, OptionalStrStart + ManuStrLen + 1, VerStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (SerialNumber, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1, SerialNumStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (AssertTag, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1, AssertTagStrLen + 1); - ASSERT_EFI_ERROR (Status); - Status = UnicodeStrToAsciiStrS (ChassisSkuNumber, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen +1 + AssertTagStrLen + 1, ChaNumStrLen + 1); - ASSERT_EFI_ERROR (Status); - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - -Exit: - if(Manufacturer != NULL) - { - FreePool(Manufacturer); - } - - if(Version != NULL) - { - FreePool(Version); - } - - if(SerialNumber != NULL) - { - FreePool(SerialNumber); - } - - if(AssertTag != NULL) - { - FreePool(AssertTag); - } - - if(ChassisSkuNumber != NULL) - { - FreePool(ChassisSkuNumber); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni deleted file mode 100644 index 1983200ccf8eac4cec2fc9a958b0836a1b7c3607..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni +++ /dev/null @@ -1,17 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2016, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// --*/ - -/=# - -#langdef en-US "English" - -#string STR_MISC_SYSTEM_SLOT_DESIGNATION #language en-US "System Slot Designation" - - diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c deleted file mode 100644 index 71bff2d13847cfe1a9be8d2bf83f1ddb39cdc472..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c +++ /dev/null @@ -1,156 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-Copyright (c) 2016, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscSystemSlotDesignationData.c - -Abstract: - - This file provide OEM to define Smbios Type09 Data - -**/ - -#include "SmbiosMisc.h" - - -// -// Static (possibly build generated) Bios Vendor data. -// -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie0) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageOther, // SlotUsage - SlotLengthOther, // SlotLength - 0x0000, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x00, // BusNum - 0 // DevFuncNum -}; - -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie1) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageAvailable, // SlotUsage - SlotLengthOther, // SlotLength - 0x0001, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x40, // BusNum - 0 // DevFuncNum -}; - -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie2) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX8, // SlotType - SlotDataBusWidth8X, // SlotDataBusWidth - SlotUsageOther, // SlotUsage - SlotLengthOther, // SlotLength - 0x0002, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0x80, // BusNum - 0 // DevFuncNum -}; - -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie3) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, - 0, // Length, - 0 // Handle - }, - 1, // SlotDesignation - SlotTypePciExpressX4, // SlotType - SlotDataBusWidth4X, // SlotDataBusWidth - SlotUsageOther, // SlotUsage - SlotLengthOther, // SlotLength - 0x0003, // SlotId - { // SlotCharacteristics1 - 0, // CharacteristicsUnknown :1; - 0, // Provides50Volts :1; - 0, // Provides33Volts :1; - 0, // SharedSlot :1; - 0, // PcCard16Supported :1; - 0, // CardBusSupported :1; - 0, // ZoomVideoSupported :1; - 0 // ModemRingResumeSupported:1; - }, - { // SlotCharacteristics2 - 0, // PmeSignalSupported :1; - 0, // HotPlugDevicesSupported :1; - 0, // SmbusSignalSupported :1; - 0 // Reserved :5; - }, - 0x00, // SegmentGroupNum - 0xC0, // BusNum - 0 // DevFuncNum -}; - -/* eof - MiscSystemSlotsData.c */ diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c deleted file mode 100644 index bc78d9fa279abdd376c0b5fbe95cdbb4fac960c1..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ /dev/null @@ -1,196 +0,0 @@ -/** @file - BIOS system slot designator information boot time changes. - SMBIOS type 9. - - Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "SmbiosMisc.h" - -#include - -extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data; -extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie1Data; -extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie2Data; -extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie3Data; - -VOID -UpdateSlotDesignation ( - IN SMBIOS_TABLE_TYPE9 *InputData - ) -{ - EFI_STRING_ID TokenToUpdate; - CHAR16 *SlotDesignation; - UINTN DesignationStrLen; - - SlotDesignation = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH); - if (NULL == SlotDesignation) - { - return; - } - - if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) - { - UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE0"); - } - else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) - { - UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE1"); - } - else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) - { - UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE2"); - } - else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) - { - UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE3"); - } - - DesignationStrLen = StrLen (SlotDesignation); - - if (DesignationStrLen > 0 ) - { - TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_DESIGNATION); - HiiSetString (mHiiHandle, TokenToUpdate, SlotDesignation, NULL); - } - - FreePool (SlotDesignation); -} - -VOID -UpdateSlotUsage( - IN OUT SMBIOS_TABLE_TYPE9 *InputData - ) -{ - EFI_STATUS Status; - SERDES_PARAM SerdesParamA; - SERDES_PARAM SerdesParamB; - - Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __func__, __LINE__, Status)); - return; - } - - // - // PCIE0 - // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) - && SerdesParamA.Hilink1Mode == EmHilink1Pcie0X8) { - InputData->CurrentUsage = SlotUsageAvailable; - } - - // - // PCIE1 - // - if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) - { - if (SerdesParamA.Hilink0Mode == EmHilink0Pcie1X4Pcie2X4) { - InputData->SlotDataBusWidth = SlotDataBusWidth4X; - } - } - - // - // PCIE2 - // - if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) - { - if (SerdesParamA.Hilink0Mode == EmHilink0Pcie1X4Pcie2X4) { - InputData->SlotDataBusWidth = SlotDataBusWidth4X; - InputData->CurrentUsage = SlotUsageAvailable; - } else if (SerdesParamA.Hilink2Mode == EmHilink2Pcie2X8) { - InputData->CurrentUsage = SlotUsageAvailable; - } - } - - // - // PCIE3 - // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) - && SerdesParamA.Hilink5Mode == EmHilink5Pcie3X4) { - InputData->CurrentUsage = SlotUsageAvailable; - } -} - -/** - This function makes boot time changes to the contents of the - MiscSystemSlotDesignator structure (Type 9). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignation) -{ - CHAR8 *OptionalStrStart; - UINTN SlotDesignationStrLen; - EFI_STATUS Status; - EFI_STRING SlotDesignation; - EFI_STRING_ID TokenToGet; - SMBIOS_TABLE_TYPE9 *SmbiosRecord; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE9 *InputData = NULL; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) - { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE9 *)RecordData; - - UpdateSlotUsage (InputData); - - UpdateSlotDesignation (InputData); - - TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_DESIGNATION); - SlotDesignation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL); - SlotDesignationStrLen = StrLen(SlotDesignation); - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1); - if(NULL == SmbiosRecord) - { - Status = EFI_OUT_OF_RESOURCES; - goto Exit; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE9)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9); - - OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); - Status = UnicodeStrToAsciiStrS (SlotDesignation, OptionalStrStart, SlotDesignationStrLen + 1); - ASSERT_EFI_ERROR (Status); - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - - Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type09 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - -Exit: - if(SlotDesignation != NULL) - { - FreePool(SlotDesignation); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni deleted file mode 100644 index 559003369f21f8d711d2e49353587112c371883f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni +++ /dev/null @@ -1,43 +0,0 @@ -// *++ -// -// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
-// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-// Copyright (c) 2015, Linaro Limited. All rights reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -// --*/ - -/=# - -/=# -// -// Language String (Long Format) -// -#string STR_MISC_BIOS_LANGUAGES_ENG_LONG #language en-US "en|US|iso8859-1" -#string STR_MISC_BIOS_LANGUAGES_FRA_LONG #language en-US "fr|CA|iso8859-1" -#string STR_MISC_BIOS_LANGUAGES_CHN_LONG #language en-US "zh|TW|unicode" -#string STR_MISC_BIOS_LANGUAGES_JPN_LONG #language en-US "ja|JP|unicode" -#string STR_MISC_BIOS_LANGUAGES_ITA_LONG #language en-US "it|IT|iso8859-1" -#string STR_MISC_BIOS_LANGUAGES_SPA_LONG #language en-US "es|ES|iso8859-1" -#string STR_MISC_BIOS_LANGUAGES_GER_LONG #language en-US "de|DE|iso8859-1" -#string STR_MISC_BIOS_LANGUAGES_POR_LONG #language en-US "pt|PT|iso8859-1" - - -// -// Language String (Abbreviated Format) -// -#string STR_MISC_BIOS_LANGUAGES_ENG_ABBREVIATE #language en-US "enUS" -#string STR_MISC_BIOS_LANGUAGES_FRA_ABBREVIATE #language en-US "frCA" -#string STR_MISC_BIOS_LANGUAGES_CHN_ABBREVIATE #language en-US "zhTW" -#string STR_MISC_BIOS_LANGUAGES_JPN_ABBREVIATE #language en-US "jaJP" -#string STR_MISC_BIOS_LANGUAGES_ITA_ABBREVIATE #language en-US "itIT" -#string STR_MISC_BIOS_LANGUAGES_SPA_ABBREVIATE #language en-US "esES" -#string STR_MISC_BIOS_LANGUAGES_GER_ABBREVIATE #language en-US "deDE" -#string STR_MISC_BIOS_LANGUAGES_POR_ABBREVIATE #language en-US "ptPT" - -#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_ABBREVIATE #language en-US "zhCN" -#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_LONG #language en-US "zh|CN|unicode" - - diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c deleted file mode 100644 index 94d9d7f1f06d17201169842043408ae03b86ecbe..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c +++ /dev/null @@ -1,40 +0,0 @@ -/**@file - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscNumberOfInstallableLanguagesData.c - -Abstract: - - This file provide OEM to define Smbios Type13 Data - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - -// -// Static (possibly build generated) Bios Vendor data. -// - -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) = -{ - { // Hdr - EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type, - 0, // Length, - 0 // Handle - }, - 0, // InstallableLanguages - 0, // Flags - { - 0 // Reserved[15] - }, - 1 // CurrentLanguage -}; - -/* eof - MiscNumberOfInstallableLanguagesData.c */ diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c deleted file mode 100644 index 41f7904e3c69edecba72561c3d3705fcafd2bdf8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c +++ /dev/null @@ -1,157 +0,0 @@ -/** @file - -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -/* Modify list -DATA AUTHOR REASON -*/ - -#include "SmbiosMisc.h" - -/** - Get next language from language code list (with separator ';'). - - @param LangCode Input: point to first language in the list. On - Otput: point to next language in the list, or - NULL if no more language in the list. - @param Lang The first language in the list. - -**/ -VOID -EFIAPI -GetNextLanguage ( - IN OUT CHAR8 **LangCode, - OUT CHAR8 *Lang - ) -{ - UINTN Index; - CHAR8 *StringPtr; - - if(NULL == LangCode || NULL == *LangCode || NULL == Lang) { - return; - } - - Index = 0; - StringPtr = *LangCode; - while (StringPtr[Index] != 0 && StringPtr[Index] != ';') { - Index++; - } - - (VOID)CopyMem(Lang, StringPtr, Index); - Lang[Index] = 0; - - if (StringPtr[Index] == ';') { - Index++; - } - *LangCode = StringPtr + Index; -} - -/** - This function returns the number of supported languages on HiiHandle. - - @param HiiHandle The HII package list handle. - - @retval The number of supported languages. - -**/ -UINT16 -EFIAPI -GetSupportedLanguageNumber ( - IN EFI_HII_HANDLE HiiHandle - ) -{ - CHAR8 *Lang; - CHAR8 *Languages; - CHAR8 *LanguageString; - UINT16 LangNumber; - - Languages = HiiGetSupportedLanguages (HiiHandle); - if (Languages == NULL) { - return 0; - } - - LangNumber = 0; - Lang = AllocatePool (AsciiStrSize (Languages)); - if (Lang != NULL) { - LanguageString = Languages; - while (*LanguageString != 0) { - GetNextLanguage (&LanguageString, Lang); - LangNumber++; - } - FreePool (Lang); - } - FreePool (Languages); - return LangNumber; -} - - -/** - This function makes boot time changes to the contents of the - MiscNumberOfInstallableLanguages (Type 13). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscNumberOfInstallableLanguages) -{ - UINTN LangStrLen; - CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1]; - CHAR8 *OptionalStrStart; - EFI_STATUS Status; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE13 *SmbiosRecord; - SMBIOS_TABLE_TYPE13 *InputData = NULL;; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE13 *)RecordData; - - InputData->InstallableLanguages = GetSupportedLanguageNumber (mHiiHandle); - - // - // Try to check if current langcode matches with the langcodes in installed languages - // - ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1); - (VOID)AsciiStrCpyS(CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1, "en|US|iso8859-1"); - LangStrLen = AsciiStrLen(CurrentLang); - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1); - if(NULL == SmbiosRecord) { - return EFI_OUT_OF_RESOURCES; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE13)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13); - - OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); - (VOID)AsciiStrCpyS(OptionalStrStart, SMBIOS_STRING_MAX_LENGTH - 1, CurrentLang); - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - Status = LogSmbiosData((UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c deleted file mode 100644 index ac5b4350764efcf80c485b29a4fa3952de00589e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c +++ /dev/null @@ -1,42 +0,0 @@ -/**@file - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscBootInformationData.c - -Abstract: - - This driver parses the mMiscSubclassDataTable structure and reports - any generated data to the DataHub. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - -// -// Static (possibly build generated) Bios Vendor data. -// -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) = { - { // Hdr - EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type, - 0, // Length, - 0 // Handle - }, - { // Reserved[6] - 0, - 0, - 0, - 0, - 0, - 0 - }, - BootInformationStatusNoError // BootInformationStatus -}; - -/* eof - MiscBootInformationData.c */ diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c deleted file mode 100644 index b3c2cac64d66d404829bb8fead1ceddd9dcd1d80..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c +++ /dev/null @@ -1,68 +0,0 @@ -/** @file - boot information boot time changes. - SMBIOS type 32. - -Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ -/* Modify list -DATA AUTHOR REASON -*/ - -#include "SmbiosMisc.h" - -/** - This function makes boot time changes to the contents of the - MiscBootInformation (Type 32). - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ - -MISC_SMBIOS_TABLE_FUNCTION(MiscBootInformation) -{ - EFI_STATUS Status; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE32 *SmbiosRecord; - SMBIOS_TABLE_TYPE32 *InputData; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE32 *)RecordData; - - // - // Two zeros following the last string. - // - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1); - if(NULL == SmbiosRecord) { - return EFI_OUT_OF_RESOURCES; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE32)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32); - - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c deleted file mode 100644 index 33b9cb9ca44293e41090eed42f9898fa534c5ac8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c +++ /dev/null @@ -1,36 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscIpmiDeviceInformationData.c - -Abstract: - - This file provide OEM to define Smbios Type38 Data - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ - -#include "SmbiosMisc.h" - -MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE38, MiscIpmiDeviceInformation) = -{ - { // Header - EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION, // Type; - 0, // Length; - 0 // Handle; - }, - IPMIDeviceInfoInterfaceTypeUnknown, // InterfaceType - 0x00, // Ipmi Specification Revision - 0, // I2CSlaveAddress - 0xFF, // NvStorageDeviceAddress - 0x88, // BaseAddress - 0, // BaseAddressModifier/InterruptInfo - 0 // InterruptNumber -}; - diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c deleted file mode 100644 index f1275c0032e95a7aac1a42c31211dc2463e5f2d9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c +++ /dev/null @@ -1,81 +0,0 @@ -/*++ - -Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
-Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-Copyright (c) 2015, Linaro Limited. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - MiscIpmiDeviceInformationFunction.c - -Abstract: - - This driver parses the mMiscSubclassDataTable structure and reports - any generated data to smbios. - -Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ -**/ -/* Modify list -DATA AUTHOR REASON -*/ - -#include "SmbiosMisc.h" - -#include - -/** - This function makes the attributes of IPMI to the contents of the - MiscChassisManufacturer structure. - - @param RecordData Pointer to copy of RecordData from the Data Table. - - @retval EFI_SUCCESS All parameters were valid. - @retval EFI_UNSUPPORTED Unexpected RecordType value. - @retval EFI_INVALID_PARAMETER Invalid parameter was found. - -**/ -MISC_SMBIOS_TABLE_FUNCTION(MiscIpmiDeviceInformation) -{ - EFI_STATUS Status; - EFI_SMBIOS_HANDLE SmbiosHandle; - SMBIOS_TABLE_TYPE38 *SmbiosRecord; - SMBIOS_TABLE_TYPE38 *InputData = NULL; - - IPMI_INTERFACE_PROTOCOL *Ipmi; - - // - // First check for invalid parameters. - // - if (RecordData == NULL) { - return EFI_INVALID_PARAMETER; - } - - InputData = (SMBIOS_TABLE_TYPE38*)RecordData; - - SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE38) + 1 + 1); - if(NULL == SmbiosRecord) { - return EFI_OUT_OF_RESOURCES; - } - - (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE38)); - - SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE38); - - Status = gBS->LocateProtocol (&gIpmiInterfaceProtocolGuid, NULL, (VOID **)&Ipmi); - if (!EFI_ERROR (Status)) { - SmbiosRecord->InterfaceType = Ipmi->GetIpmiInterfaceType (Ipmi); - SmbiosRecord->BaseAddress = (UINT64)Ipmi->GetIpmiBaseAddress (Ipmi) | Ipmi->GetIpmiBaseAddressType (Ipmi); - SmbiosRecord->IPMISpecificationRevision = Ipmi->GetIpmiVersion (Ipmi); - } - // - // Now we have got the full smbios record, call smbios protocol to add this record. - // - Status = LogSmbiosData((UINT8*)SmbiosRecord, &SmbiosHandle); - if(EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "[%a]:[%dL] Smbios Type38 Table Log Failed! %r \n", __func__, __LINE__, Status)); - } - - FreePool(SmbiosRecord); - return Status; -} diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c deleted file mode 100644 index 2f08b328dfc91833581322d2cb52c4ab3f4014f5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c +++ /dev/null @@ -1,109 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -typedef struct { - UINTN Signature; - EFI_HANDLE Handle; - HISI_PLATFORM_SNP_PROTOCOL SnpPlatformProtocol; -} SNP_PLATFORM_INSTANCE; - -STATIC HISI_PLATFORM_SNP_PROTOCOL mSnpPlatformProtocol[] = { - { - 4, - 1 - }, - { - 5, - 1 - }, - { - 2, - 0 - }, - { - 3, - 0 - }, - { - 0, - 1 - }, - { - 1, - 1 - }, - { - 6, - 0 - }, - { - 7, - 0 - } -}; - - -EFI_STATUS -EFIAPI -SnpPlatformInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - UINTN Loop; - SNP_PLATFORM_INSTANCE *PrivateData; - EFI_STATUS Status; - - for (Loop = 0; Loop < ARRAY_SIZE (mSnpPlatformProtocol); Loop++) { - if(mSnpPlatformProtocol[Loop].Enable != 1) { - continue; - } - PrivateData = AllocateZeroPool (sizeof(SNP_PLATFORM_INSTANCE)); - if (PrivateData == NULL) { - DEBUG ((DEBUG_INFO,"SnpPlatformInitialize error 1\n")); - return EFI_OUT_OF_RESOURCES; - } - - - PrivateData->SnpPlatformProtocol = mSnpPlatformProtocol[Loop]; - - // - // Install the snp protocol, device path protocol - // - Status = gBS->InstallMultipleProtocolInterfaces ( - &PrivateData->Handle, - &gHisiSnpPlatformProtocolGuid, - &PrivateData->SnpPlatformProtocol, - NULL - ); - if (EFI_ERROR (Status)) { - FreePool (PrivateData); - DEBUG ((DEBUG_ERROR, "InstallProtocolInterface fail. %r\n", Status)); - continue; - } - } - - DEBUG ((DEBUG_INFO,"SnpPlatformInitialize succes!\n")); - - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf deleted file mode 100644 index 6f4f23b100e5889820a894bad1e81e42576f3806..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf +++ /dev/null @@ -1,40 +0,0 @@ -#/** @file -# -# Copyright (c) 2017, Hisilicon Limited. All rights reserved. -# Copyright (c) 2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = SnpPlatform - FILE_GUID = 102D8FC9-20A4-42eb-AC14-1C98BA5B17A8 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = SnpPlatformInitialize - -[Sources] - SnpPlatform.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - DxeServicesTableLib - MemoryAllocationLib - UefiBootServicesTableLib - UefiDriverEntryPoint - -[Protocols] - gHisiSnpPlatformProtocolGuid - -[Depex] - TRUE - diff --git a/Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c b/Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c deleted file mode 100644 index 955bf6b8da651ff5577eb3c09e9c02477b1776f6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c +++ /dev/null @@ -1,152 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -STATIC -EFI_STATUS -InstallFdtIntoConfigurationTable ( - IN VOID* FdtBlob, - IN UINTN FdtSize - ) -{ - EFI_STATUS Status; - - // Check the FDT header is valid. We only make this check in DEBUG mode in case the FDT header change on - // production device and this ASSERT() becomes not valid. - if(!(fdt_check_header (FdtBlob) == 0)) - { - DEBUG ((DEBUG_ERROR,"can not find FdtBlob \n")); - return EFI_INVALID_PARAMETER; - } - - // Ensure the Size of the Device Tree is smaller than the size of the read file - if(!((UINTN)fdt_totalsize (FdtBlob) <= FdtSize)) - { - DEBUG ((DEBUG_ERROR,"FdtBlob <= FdtSize \n")); - return EFI_INVALID_PARAMETER; - } - - // Install the FDT into the Configuration Table - Status = gBS->InstallConfigurationTable (&gFdtTableGuid, FdtBlob); - - return Status; -} - -EFI_STATUS -SetNvramSpace (VOID) -{ - EFI_STATUS Status; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0}; - - if (PcdGet64(PcdReservedNvramSize) == 0) { - return EFI_SUCCESS; - } - - Status = gDS->GetMemorySpaceDescriptor(PcdGet64(PcdReservedNvramBase),&desp); - if(EFI_ERROR(Status)){ - DEBUG ((DEBUG_ERROR,"get memory space error:--------- \n")); - return Status; - } - desp.Attributes |= EFI_MEMORY_RUNTIME | EFI_MEMORY_WB; - Status = gDS->SetMemorySpaceAttributes(PcdGet64(PcdReservedNvramBase),PcdGet64(PcdReservedNvramSize), desp.Attributes); - if(EFI_ERROR(Status)){ - DEBUG ((DEBUG_ERROR,"set memory space error:--------- \n")); - return Status; - } - - return EFI_SUCCESS; -} - - -EFI_STATUS -EFIAPI UpdateFdt ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable) -{ - INTN Error; - VOID* Fdt; - UINT32 Size; - UINTN NewFdtBlobSize; - UINTN NewFdtBlobBase; - EFI_STATUS Status = EFI_SUCCESS; - UINT32 Index = 0; - UINTN FDTConfigTable; - - (VOID) SetNvramSpace (); - - Fdt = (VOID*)(PcdGet64(FdtFileAddress)); - - - Error = fdt_check_header ((VOID*)(PcdGet64(FdtFileAddress))); - DEBUG ((DEBUG_ERROR,"fdtfileaddress:--------- 0x%lx\n",PcdGet64(FdtFileAddress))); - if (Error != 0) - { - DEBUG ((DEBUG_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error))); - return EFI_INVALID_PARAMETER; - } - - Size = (UINTN)fdt_totalsize ((VOID*)(PcdGet64(FdtFileAddress))); - NewFdtBlobSize = Size + ADD_FILE_LENGTH; - - Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); - if (EFI_ERROR (Status)) - { - return EFI_OUT_OF_RESOURCES; - } - - (VOID) CopyMem((VOID*)NewFdtBlobBase, Fdt, Size); - - Status = EFIFdtUpdate(NewFdtBlobBase); - if (EFI_ERROR (Status)) - { - DEBUG((DEBUG_ERROR, "%a(%d):EFIFdtUpdate Fail!\n", __func__,__LINE__)); - goto EXIT; - } - - - Status = InstallFdtIntoConfigurationTable ((VOID*)(UINTN)NewFdtBlobBase, NewFdtBlobSize); - DEBUG ((DEBUG_ERROR, "NewFdtBlobBase: 0x%lx NewFdtBlobSize:0x%lx\n",NewFdtBlobBase,NewFdtBlobSize)); - if (EFI_ERROR (Status)) - { - DEBUG ((DEBUG_ERROR, "installfdtconfiguration table fail():\n")); - goto EXIT; - } - - - for (Index = 0; Index < gST->NumberOfTableEntries; Index ++) - { - if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid))) - { - FDTConfigTable = (UINTN)gST->ConfigurationTable[Index].VendorTable; - DEBUG ((DEBUG_ERROR, "FDTConfigTable Address: 0x%lx\n",FDTConfigTable)); - break; - } - } - - return Status; - - EXIT: - - gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize)); - - return Status; - -} diff --git a/Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf b/Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf deleted file mode 100644 index 477373f4cbe024ed0fce162278e43ea3fbbfdc47..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +++ /dev/null @@ -1,56 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = UpdateFdtDxe - FILE_GUID = E29977F9-20A4-4551-B0EC-BCE246592E76 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = UpdateFdt - -[Sources.common] - UpdateFdtDxe.c - - -[Packages] - ArmPlatformPkg/ArmPlatformPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - -[LibraryClasses] - UefiBootServicesTableLib - MemoryAllocationLib - UefiDriverEntryPoint - DebugLib - BaseLib - FdtLib - PcdLib - FdtUpdateLib - DxeServicesTableLib - -[Guids] - gFdtTableGuid -[Protocols] - - gHisiBoardNicProtocolGuid - -[Pcd] - - gHisiTokenSpaceGuid.FdtFileAddress - gHisiTokenSpaceGuid.PcdReservedNvramSize - gHisiTokenSpaceGuid.PcdReservedNvramBase - - -[Depex] - gEfiGenericMemTestProtocolGuid diff --git a/Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c b/Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c deleted file mode 100644 index 2064a4821d8720adc48243d8edc7ea4d27219ae1..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c +++ /dev/null @@ -1,102 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -struct MonthDescription { - CONST CHAR8* MonthStr; - UINT32 MonthInt; -} gMonthDescription[] = { - { "Jan", 1 }, - { "Feb", 2 }, - { "Mar", 3 }, - { "Apr", 4 }, - { "May", 5 }, - { "Jun", 6 }, - { "Jul", 7 }, - { "Aug", 8 }, - { "Sep", 9 }, - { "Oct", 10 }, - { "Nov", 11 }, - { "Dec", 12 }, - { "???", 1 }, // Use 1 as default month -}; - -VOID GetReleaseTime (EFI_TIME *Time) -{ - CONST CHAR8 *ReleaseDate = __DATE__; - CONST CHAR8 *ReleaseTime = __TIME__; - UINTN i; - - for(i=0;i<12;i++) - { - if(0 == AsciiStrnCmp(ReleaseDate, gMonthDescription[i].MonthStr, 3)) - { - break; - } - } - Time->Month = gMonthDescription[i].MonthInt; - Time->Day = AsciiStrDecimalToUintn(ReleaseDate+4); - Time->Year = AsciiStrDecimalToUintn(ReleaseDate+7); - Time->Hour = AsciiStrDecimalToUintn(ReleaseTime); - Time->Minute = AsciiStrDecimalToUintn(ReleaseTime+3); - Time->Second = AsciiStrDecimalToUintn(ReleaseTime+6); - - return; -} - -EFI_STATUS -EFIAPI -VersionInfoEntry ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - CHAR8 Buffer[100]; - UINTN CharCount; - VERSION_INFO *VersionInfo; - EFI_TIME Time = {0}; - CONST CHAR16 *ReleaseString = - (CHAR16 *) FixedPcdGetPtr (PcdFirmwareVersionString); - - GetReleaseTime (&Time); - - CharCount = AsciiSPrint ( - Buffer, - sizeof (Buffer), - "\n\rBoot firmware (version %s built at %t)\n\r\n\r", - ReleaseString, - &Time - ); - SerialPortWrite ((UINT8 *) Buffer, CharCount); - - VersionInfo = BuildGuidHob (&gVersionInfoHobGuid, - sizeof (VERSION_INFO) - - sizeof (VersionInfo->String) + - StrSize (ReleaseString)); - if (VersionInfo == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%d] Build HOB failed!\n", __FILE__, __LINE__)); - return EFI_OUT_OF_RESOURCES; - } - - CopyMem (&VersionInfo->BuildTime, &Time, sizeof (EFI_TIME)); - CopyMem (VersionInfo->String, ReleaseString, StrSize (ReleaseString)); - - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf b/Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf deleted file mode 100644 index dfdda2f403e9c29657d554b2a867d29267758cd2..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf +++ /dev/null @@ -1,47 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = VersionInfoPeim - FILE_GUID = F414EE11-EEE3-4edc-8C12-0E80E446A849 - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - ENTRY_POINT = VersionInfoEntry - -[Sources.common] - VersionInfoPeim.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - PeimEntryPoint - PcdLib - DebugLib - HobLib - BaseLib - BaseMemoryLib - PrintLib - SerialPortLib - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString - -[Guids] - gVersionInfoHobGuid - -[Depex] - TRUE - -[BuildOptions] - diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c deleted file mode 100644 index 669992144a4cf4ce9b374c516f43f50853e46778..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c +++ /dev/null @@ -1,29 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include - -EFI_STATUS -EFIAPI -EhciVirtualPciIoInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - return RegisterNonDiscoverableMmioDevice ( - NonDiscoverableDeviceTypeEhci, - NonDiscoverableDeviceDmaTypeCoherent, - NULL, - NULL, - 1, - PlatformGetEhciBase (), - SIZE_4KB); -} diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf deleted file mode 100644 index e1f3707d4feb31b9a5f6c3fb39e59d850689bbe8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf +++ /dev/null @@ -1,33 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = VirtualEhciPciIo - FILE_GUID = CCC39A9C-33EC-4e5a-924B-2C5CD4CEF6A4 - MODULE_TYPE = UEFI_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = EhciVirtualPciIoInitialize - - -[Sources] - VirtualEhciPciIo.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - NonDiscoverableDeviceRegistrationLib - PlatformSysCtrlLib - UefiDriverEntryPoint diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c deleted file mode 100644 index 8417ff0425bc8ead98c31f1fd82e47725e55abeb..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c +++ /dev/null @@ -1,57 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include - -#include -#include - -VOID -EFIAPI -ExitBootServicesEventSmmu ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - DEBUG((DEBUG_INFO,"SMMU ExitBootServicesEvent\n")); -} - - -EFI_STATUS -EFIAPI -IoInitDxeEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable) -{ - EFI_STATUS Status; - EFI_EVENT Event = NULL; - - (VOID) EfiSerdesInitWrap (); - - SmmuConfigForOS (); - - Status = gBS->CreateEvent ( - EVT_SIGNAL_EXIT_BOOT_SERVICES, - TPL_CALLBACK, - ExitBootServicesEventSmmu, - NULL, - &Event - ); - - if (EFI_ERROR(Status)) - { - DEBUG ((DEBUG_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __func__, - __LINE__, Status)); - } - - return Status; -} - diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf deleted file mode 100644 index 30fd829bcdf15d8a849ecf9b7050b6ac9a30ccec..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf +++ /dev/null @@ -1,57 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = IoInitDxe - FILE_GUID = 28C9B7DE-AAD6-4E9B-811B-050AD3DAB9A3 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = IoInitDxeEntry - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = AARCH64 -# - -[Sources.common] - IoInitDxe.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiBootServicesTableLib - UefiDriverEntryPoint - DebugLib - BaseLib - PcdLib - CacheMaintenanceLib - SerdesLib - PlatformSysCtrlLib - -[Guids] - -[Protocols] - -[Pcd] - gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 - gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 - gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 - gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - -[Depex] - TRUE - diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c deleted file mode 100644 index 94f2182288f80ba5ae07401b42a8700f2e049961..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c +++ /dev/null @@ -1,159 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "PcieInit.h" -#include -#include -#include -#include - - -extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value); -extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port); -extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg); - -PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] = -{ - //Port 0 - { - 0x0, //Portindex - - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, //PortInfo - - }, - - //Port 1 - { - 0x1, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, - - //Port 2 - { - 0x2, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, - - //Port 3 - { - 0x3, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, - //Port 4 - { - 0x4, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, - //Port 5 - { - 0x5, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, - //Port 6 - { - 0x6, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, - //Port 7 - { - 0x7, //Portindex - { - PCIE_ROOT_COMPLEX, //PortType - PCIE_WITDH_X8, //PortWidth - PCIE_GEN3_0, //PortGen - }, - - }, -}; - -EFI_STATUS -PcieInitEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) - -{ - UINT32 Port; - EFI_STATUS Status = EFI_SUCCESS; - UINT32 HostBridgeNum = 0; - UINT32 soctype = 0; - UINT32 PcieRootBridgeMask; - - - if (!OemIsMpBoot()) - { - PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask); - } - else - { - PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P); - } - - soctype = PcdGet32(Pcdsoctype); - for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) { - for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) { - /* - Host Bridge may contain lots of root bridges. - Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges - PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits, - and each bit stands for this PCIe Port is enable or not - */ - if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) { - continue; - } - - Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]); - if(EFI_ERROR(Status)) - { - DEBUG((DEBUG_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port)); - } - - } - } - - - return EFI_SUCCESS; - -} - - diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h deleted file mode 100644 index 55928cd6e0fef26173dd1cfb0e643400db8949db..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h +++ /dev/null @@ -1,86 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __PCIE_INIT_H__ -#define __PCIE_INIT_H__ - -#include "PcieInitLib.h" -#include -#include -#include - -extern EFI_GUID gEfiPcieRootBridgeProtocolGuid; - -#define PCIE_LOG_ID 1 - -#define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k -#define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M -#define PCIE_IO_SPACE_SIZE 0x800000 //8M -#define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE) - -#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000 -#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0 -#define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1) - -#define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE) -#define PCIE_MEM_BASE_ADDR_HIGH 0x0 -#define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1) - -#define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1) -#define PCIE_IO_BASE_ADDR_HIGH 0x0 -#define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1) - -#define PCIE_INBOUND_BASE 0xD0000000 - - -#define PCIE_ALL_DMA_BASE (0x100000000) -#define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE) -#define PCIE0_ALL_DMA_SIZE (0x8000000) -#define PCIE0_ALL_BAR01_BASE (0x10000000) -#define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE) -#define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR) -#define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE) -#define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE) -#define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE) - - -#define PCIE0_REG_BASE (0xb0070000) -#define PCIE1_REG_BASE (0xb0080000) -#define PCIE2_REG_BASE (0xb0090000) -#define PCIE3_REG_BASE (0xb00a0000) - -#define PCIE_BASE_BAR (0xf0000000) -#define PCIE_BAR_SIZE (0x1000000) - - -#define PCIE_AXI_SIZE (0x1000000) -#define PCIE0_AXI_BASE (0xb3000000) -#define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE) -#define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE) -#define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE) - -#define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE) -#define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE) -#define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE) -#define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE) - - -#define PCIE0_TRANSLATE_BASE (0x30000000) -#define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE) -#define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE) -#define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE) - -#define PCIE0_BAR_BASE (PCIE0_AXI_BASE) -#define PCIE1_BAR_BASE (PCIE1_AXI_BASE) -#define PCIE2_BAR_BASE (PCIE2_AXI_BASE) -#define PCIE3_BAR_BASE (PCIE3_AXI_BASE) - - -#endif - diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf deleted file mode 100644 index 0a4c1aad307b114d332de4d1c906440d7259635f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ /dev/null @@ -1,56 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PcieInitDxe - FILE_GUID = 8EB6E216-BA47-4B30-B68A-2B371F7232A6 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = PcieInitEntry - -[Sources] - PcieInit.c - PcieInitLib.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - UefiLib - BaseLib - DebugLib - ArmLib - TimerLib - PcdLib - IoLib - HisiOemMiscLib - -[Protocols] - #gEfiPcieRootBridgeProtocolGuid - -[Pcd] - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P - gHisiTokenSpaceGuid.Pcdsoctype - gArmTokenSpaceGuid.PcdGicDistributorBase - -[FeaturePcd] - gHisiTokenSpaceGuid.PcdIsItsSupported - -[depex] - TRUE - - diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c deleted file mode 100644 index 68be165a22764aa0c73e7f667475958c00bc81b5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ /dev/null @@ -1,1254 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "PcieInitLib.h" -#include -#include -#include -#include -#include -#include -#include - -#define PCIE_SYS_REG_OFFSET 0x1000 - -static PCIE_INIT_CFG mPcieIntCfg; -UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; -UINT64 io_sub0_base = 0xa0000000; -UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; -#define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) -UINT32 loop_test_flag[4] = {0,0,0,0}; -UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR; -#define PcieMaxLanNum 8 -#define PCIE_PORT_NUM_IN_SICL 4 //SICL: Super IO Cluster - - -extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; -extern PCIE_IATU gastr_pcie_iatu_cfg; -extern PCIE_IATU_VA mPcieIatuTable; - -EFI_STATUS -EFIAPI -PciePortInit ( - IN UINT32 soctype, - IN UINT32 HostBridgeNum, - IN PCIE_DRIVER_CFG *PcieCfg - ); - -VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value) -{ - RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); - -} - -UINT32 PcieRegRead(UINT32 Port, UINTN Offset) -{ - UINT32 Value = 0; - - RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); - return Value; -} - -VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value) -{ - RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value); -} - -UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1) -{ - UINT32 Value = 0; - RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value); - return Value; -} - -VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode) -{ - u_sc_pcie0_clkreq pcie0; - u_sc_pcie1_clkreq pcie1; - u_sc_pcie2_clkreq pcie2; - u_sc_pcie3_clkreq pcie3; - - switch(Port) - { - case 0: - RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32); - pcie0.Bits.pcie0_apb_cfg_sel = Mode; - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32); - break; - case 1: - RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32); - pcie1.Bits.pcie1_apb_cfg_sel = Mode; - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32); - break; - case 2: - RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32); - pcie2.Bits.pcie2_apb_cfg_sel = Mode; - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32); - break; - case 3: - RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32); - pcie3.Bits.pcie3_apb_cfg_sel = Mode; - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32); - break; - default: - break; - } -} - -VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN On) -{ - UINT32 i; - UINT32 Lanenum; - UINT32 Value; - UINT32 Laneid; - UINT32 Loopcnt; - UINT32 Lockedcnt[PcieMaxLanNum] = {0}; - - Lanenum = 8; - if (0x1610 == soctype) - { - if (On) { - /* - * to valid the RX, firstly, we should check and make - * sure the RX lanes have been steadily locked. - */ - for (Loopcnt = 500 * Lanenum; Loopcnt > 0; Loopcnt--) { - Laneid = Loopcnt % Lanenum; - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value); - if (((Value >> 21) & 0x7) >= 4) - Lockedcnt[Laneid]++; - else - Lockedcnt[Laneid] = 0; - /* - * If we get a locked status above 8 times incessantly - * on anyone of the lanes, we get a stable lock. - */ - if (Lockedcnt[Laneid] >= 8) - break; - if (Laneid == (Lanenum - 1)) - MicroSecondDelay(500); - } - if (Loopcnt == 0) - DEBUG((DEBUG_ERROR, "pcs locked timeout!\n")); - for (i = 0; i < Lanenum; i++) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value); - Value &= (~BIT14); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); - } - } else { - for (i = 0; i < Lanenum; i++) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value); - Value |= BIT14; - Value &= (~BIT15); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); - } - } - } -} -/* - * The ltssm register is assigned in an asynchronous way, the value - * of register may not right in metastable state. - * Read the register twice to get stable value. - */ -VOID PcieGetLtssmValue ( - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN UINT32 *Value - ) -{ - UINT32 ValueA; - UINT32 ValueB = 0; - UINT32 Count; - - RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA); - ValueA = ValueA & PCIE_LTSSM_STATE_MASK; - - Count = 0; - while (Count < 2) { - - RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB); - ValueB = ValueB & PCIE_LTSSM_STATE_MASK; - - /* Get the same state in continuous two times*/ - if (ValueA == ValueB) { - break; - } - - //If the second value not equal to the first, we return the second one as the stable - ValueA = ValueB; - Count++; - } - - *Value = ValueB; - - return; - -} - -/* - * In some cases, the PCIe device may close part of lanes in - * config state of LTSSM, the hip06 RC should reconfig lane num - * and try to linkup again. - */ -VOID PcieReconfigLaneNum ( - IN UINT32 soctype, - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN PCIE_DRIVER_CFG *PcieCfg - ) -{ - EFI_STATUS Status; - UINT32 LtssmStatus; - UINT32 RegVal; - UINT32 LoopCnt = 0; - UINT32 LaneNumCnt = 0; - PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth; - - // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers - while (LoopCnt < 500) { - - /* - * The minimum lanenum is 1, no need to try any more. - */ - if (PortWidth <= 1) { - DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n")); - return; - } - - /* - * Check the lane num config state is normal or not. - */ - PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus); - if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) { - LaneNumCnt++; - } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { - PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus); - if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { - break; - } - } else { - LaneNumCnt = 0; - } - - /* - * The lane num config state is abnormal, need to reconfig - * the lane num and try to establish link again. - */ - if (LaneNumCnt > MAX_TRY_LINK_NUM) { - /* Disable LTSSM */ - RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); - RegVal &= ~(LTSSM_ENABLE); - RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); - /* - * Decrease the PortWidth and try to link again, - * the value of PortWidth 0xf (X8), 0x7(x4), 0x3(X2), 0x1(X1) - */ - PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1); - - Status = PciePortInit (soctype, HostBridgeNum, PcieCfg); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port)); - } - return; - } - - LoopCnt++; - /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted - * delay up to 1 ms before transitioning to Configuration.Lanenum.Accept. - * So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range. - */ - MicroSecondDelay (200); - } - - return ; -} - -EFI_STATUS -PcieEnableItssm ( - IN UINT32 soctype, - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN PCIE_DRIVER_CFG *PcieCfg - ) -{ - PCIE_CTRL_7_U pcie_ctrl7; - UINT32 Value = 0; - - if (Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - if (0x1610 == soctype) - { - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); - Value |= BIT11|BIT30|BIT31; - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); - (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); - PcieReconfigLaneNum (soctype, HostBridgeNum, Port, PcieCfg); - return EFI_SUCCESS; - } - else - { - PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); - - pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG); - pcie_ctrl7.Bits.pcie_linkdown_auto_rstn_enable = 0x1; - pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1; - PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32); - - PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); - - return EFI_SUCCESS; - } - -} - -EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - PCIE_CTRL_7_U pcie_ctrl7; - UINT32 Value = 0; - - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return PCIE_ERR_PARAM_INVALID; - } - - if (0x1610 == soctype) - { - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); - Value &= ~(BIT11); - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); - PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); - return EFI_SUCCESS; - } - else - { - PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); - - pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG); - pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0; - PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32); - - PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); - - return EFI_SUCCESS; - } - -} - - -EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed) -{ - PCIE_EP_PCIE_CAP12_U pcie_cap12; - - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG); - pcie_cap12.Bits.targetlinkspeed = Speed; - PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32); - - if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB || - mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP) - { - pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG); - pcie_cap12.Bits.targetlinkspeed = Speed; - PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32); - } - return EFI_SUCCESS; -} - -EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width) -{ - PCIE_EP_PORT_LOGIC4_U pcie_logic4; - PCIE_EP_PORT_LOGIC22_U logic22; - - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return PCIE_ERR_PARAM_INVALID; - } - - pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG); - pcie_logic4.Bits.linkmodeenable = Width; - pcie_logic4.Bits.crosslinkenable = 0; - pcie_logic4.Bits.fastlinkmode = 1; - PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32); - - logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG); - logic22.Bits.n_fts = 0xff; - if(Width == PCIE_WITDH_X1) - { - logic22.Bits.pre_determ_num_of_lane = 1; - } - else if(Width == PCIE_WITDH_X2) - { - logic22.Bits.pre_determ_num_of_lane = 2; - } - else - { - logic22.Bits.pre_determ_num_of_lane = 3; - } - PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32); - - if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB || - mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP) - { - pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG); - pcie_logic4.Bits.linkmodeenable = Width; - pcie_logic4.Bits.crosslinkenable = 0; - pcie_logic4.Bits.fastlinkmode = 1; - PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32); - - logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG); - logic22.Bits.n_fts = 0xff; - if(Width == PCIE_WITDH_X1) - { - logic22.Bits.pre_determ_num_of_lane = 1; - } - else if(Width == PCIE_WITDH_X2) - { - logic22.Bits.pre_determ_num_of_lane = 2; - } - else - { - logic22.Bits.pre_determ_num_of_lane = 3; - } - PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32); - } - return EFI_SUCCESS; -} - -EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width) -{ - PCIE_EP_PORT_LOGIC22_U logic22; - PCIE_EEP_PCI_CFG_HDR15_U hdr15; - UINT32 Value = 0; - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG); - Value &= ~(0x3f<<16); - - if(Width == PCIE_WITDH_X1) - { - Value |= (0x1 << 16); - } - else if(Width == PCIE_WITDH_X2) - { - Value |= (0x3 << 16); - } - else if(Width == PCIE_WITDH_X4) - { - Value |= (0x7 << 16); - } - else if(Width == PCIE_WITDH_X8) - { - Value |= (0xf << 16); - } - else - { - DEBUG((DEBUG_ERROR,"Width is not valid\n")); - } - - PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value); - - logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG); - if(Width == PCIE_WITDH_X1) - { - logic22.Bits.pre_determ_num_of_lane = 1; - } - else if(Width == PCIE_WITDH_X2) - { - logic22.Bits.pre_determ_num_of_lane = 2; - } - else if(Width == PCIE_WITDH_X4) - { - logic22.Bits.pre_determ_num_of_lane = 4; - } - else if(Width == PCIE_WITDH_X8) - { - logic22.Bits.pre_determ_num_of_lane = 8; - } - else - { - DEBUG((DEBUG_ERROR,"Width is not valid\n")); - } - - logic22.UInt32 |= (0x100<<8); - logic22.UInt32 |= (0x1<<17); - PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32); - - /* setup RC BARs */ - PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004); - PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000); - - /* setup interrupt pins */ - hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG); - hdr15.UInt32 &= 0xffff00ff; - hdr15.UInt32 |= 0x00000100; - PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32); - - /* setup bus numbers */ - Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG); - Value &= 0xff000000; - Value |= 0x00010100; - PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value); - - /* setup command register */ - Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG); - Value &= 0xffff0000; - Value |= 0x1|0x2|0x4|0x100; - PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value); - - return EFI_SUCCESS; -} - - -EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType) -{ - PCIE_CTRL_0_U str_pcie_ctrl_0; - - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - if (0x1610 == soctype) - { - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28); - } - else - { - PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); - - str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG); - if(PcieType == PCIE_END_POINT) - { - str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE; - } - else - { - str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC; - } - PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32); - - PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); - } - return EFI_SUCCESS; -} - -VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT8 i = 0; - UINT32 Value = 0; - if (0x1610 == soctype) - { - for (i = 0; i < PcieMaxLanNum; i++) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); - Value |= (1 << 20); //bit 20: rxvalid enable - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); - RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \ - CH_RXTX_STATUS_CFG_EN | CH_RXTX_STATUS_CFG); - } - PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); - } - else - { - if(Port<=2) - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0); - } - else - - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001); - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff); - } - } - return; -} - -VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value; - - if (0x1610 == soctype) - { - PcieRegWrite(Port, 0x890, 0x1c00); - } - else - PcieRegWrite(Port, 0x890, 0x1400); - PcieRegWrite(Port, 0x894, 0xfd7); - - PcieRegWrite(Port, 0x89c, 0x0); - PcieRegWrite(Port, 0x898, 0xfc00); - PcieRegWrite(Port, 0x89c, 0x1); - PcieRegWrite(Port, 0x898, 0xbd00); - PcieRegWrite(Port, 0x89c, 0x2); - PcieRegWrite(Port, 0x898, 0xccc0); - PcieRegWrite(Port, 0x89c, 0x3); - PcieRegWrite(Port, 0x898, 0x8dc0); - PcieRegWrite(Port, 0x89c, 0x4); - PcieRegWrite(Port, 0x898, 0xfc0); - PcieRegWrite(Port, 0x89c, 0x5); - PcieRegWrite(Port, 0x898, 0xe46); - PcieRegWrite(Port, 0x89c, 0x6); - PcieRegWrite(Port, 0x898, 0xdc8); - PcieRegWrite(Port, 0x89c, 0x7); - PcieRegWrite(Port, 0x898, 0xcb46); - PcieRegWrite(Port, 0x89c, 0x8); - PcieRegWrite(Port, 0x898, 0x8c07); - PcieRegWrite(Port, 0x89c, 0x9); - PcieRegWrite(Port, 0x898, 0xd0b); - PcieRegWrite(Port, 0x8a8, 0x103ff21); - if (0x1610 == soctype) - { - PcieRegWrite(Port, 0x164, 0x44444444); - PcieRegWrite(Port, 0x168, 0x44444444); - PcieRegWrite(Port, 0x16c, 0x44444444); - PcieRegWrite(Port, 0x170, 0x44444444); - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); - Value &= (~0x3f); - Value |= 0x5; - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); - - } - else - { - Value = PcieRegRead(Port, 0x80); - Value |= 0x80; - PcieRegWrite(Port, 0x80, Value); - - PcieRegWrite(Port, 0x184, 0x44444444); - PcieRegWrite(Port, 0x188, 0x44444444); - PcieRegWrite(Port, 0x18c, 0x44444444); - PcieRegWrite(Port, 0x190, 0x44444444); - } -} - - -EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 PortIndexInSicl; - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - if(PcieIsLinkUp(soctype, HostBridgeNum, Port)) - { - (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port); - } - - if (0x1610 == soctype) - { - PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; - if (PortIndexInSicl <= 2) { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3); - MicroSecondDelay(0x1000); - } - } - else - { - if(Port <= 2) - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1); - MicroSecondDelay(0x1000); - } - } - - return EFI_SUCCESS; -} - -EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 PortIndexInSicl; - if(Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - if(PcieIsLinkUp(soctype, HostBridgeNum, Port)) - { - (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port); - } - - if (0x1610 == soctype) - { - PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; - if (PortIndexInSicl <= 2) { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3); - MicroSecondDelay(0x1000); - } - } - else - { - if(Port <= 2) - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1); - MicroSecondDelay(0x1000); - } - } - - return EFI_SUCCESS; -} - -EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - u_sc_pcie_hilink_pcs_reset_req reset_req; - UINT32 PortIndexInSicl; - if (0x1610 == soctype) - { - PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32); - - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl)); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32); - //0x1000 microseconds delay comes from experiment and - //should be fairly enough for this operation. - MicroSecondDelay(0x1000); - } - else - { - if(Port <= 3) - { - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port); - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32); - - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port)); - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32); - MicroSecondDelay(0x1000); - } - } - return EFI_SUCCESS; -} - -EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - u_sc_pcie_hilink_pcs_reset_req reset_req; - UINT32 PortIndexInSicl; - if (0x1610 == soctype) - { - PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32); - - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl)); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32); - //0x1000 microseconds delay comes from experimenti - // and should be fairly enough for this operation. - MicroSecondDelay(0x1000); - } - else - { - if(Port <= 3) - { - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port); - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32); - - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port)); - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32); - MicroSecondDelay(0x1000); - } - } - - return EFI_SUCCESS; -} - -EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock) -{ - UINT32 reg_clock_disable; - UINT32 reg_clock_enable; - UINT32 PortIndexInSicl; - PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; - if (PortIndexInSicl == 3) { - reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG; - reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG; - } else { - reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl); - reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl); - } - - if (0x1610 == soctype) - { - if (Clock) - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7); - else - RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7); - } - else - { - if (Clock) - RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, 0x3); - else - RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, 0x3); - } - return EFI_SUCCESS; -} - -VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num) -{ - if (0x1610 == soctype) - { - UINT32 Value = 0; - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); - Value &= ~(0xff); - Value |= Num; - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); - } - return; -} - -VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value = 0; - if (0x1610 == soctype) - { - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); - Value |= BIT16; - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); - } - return; -} -EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value = 0; - if (0x1610 == soctype) - { - Value = PcieRegRead(Port, 0x120); - Value |= 1 << 25; - PcieRegWrite(Port,0x120, Value); - } - else - { - PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); - Value = PcieRegRead(Port, 0x1d0); - Value |= 1 << 12; - PcieRegWrite(Port,0x1d0, Value); - PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); - } - return EFI_SUCCESS; -} - -BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value = 0; - U_SC_PCIE0_SYS_STATE4 PcieStat; - if (0x1610 == soctype) - { - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32); - Value = PcieStat.UInt32; - if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE) - return TRUE; - return FALSE; - } - else - { - RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32); - Value = PcieStat.UInt32; - if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE) - return TRUE; - return FALSE; - } -} - -BOOLEAN PcieClockIsLock(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value = 0; - if (0x1610 == soctype) - { - RegRead( PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x504, Value); - return ((Value & 0x3) == 0x3); - } - else return TRUE; - -} - -VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) -{ - UINT32 Value = 0; - if (0x1610 == soctype) - { - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); - Value &= ~(0xf); - Value |= Spd; - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); - return; - } - return; -} - -VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data) -{ - UINT32 Value = 0; - { - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); - Value &= 0x0000ffff; - Value |= 0x06040000; - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); - return; - } -} - -VOID SysRegWrite(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg, UINTN Value) -{ - if (SocType == 0x1610) { - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value); - } else { - //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE - //in the same hostbridge. - RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value); - } -} - -void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value = 0; - UINT64 GicdSetSpiReg = PcdGet64 (PcdGicDistributorBase) + 0x40; - - if (FeaturePcdGet (PcdIsItsSupported)) { - //PCIE_SYS_CTRL24_REG is MSI Low address register - //PCIE_SYS_CTRL28_REG is MSI High addres register - SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]); - SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32); - } else { - SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, GicdSetSpiReg); - SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, GicdSetSpiReg >> 32); - } - RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); - Value |= (1 << 12); - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); - - return; -} - -UINT32 -SysRegRead ( - IN UINT32 SocType, - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN UINTN Reg - ) -{ - UINT32 Value; - if (SocType == 0x1610) { - RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value); - } else { - //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE - //in the same hostbridge. - RegRead (PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value); - } - return Value; -} - -VOID -DisableRcOptionRom ( - IN UINT32 Soctype, - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN PCIE_PORT_TYPE PcieType -) -{ - UINT32 Value = 0; - if (PcieType == PCIE_ROOT_COMPLEX) { - Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); - Value |= BIT2; //cs2 enable - SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); - - Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG); - Value &= ~BIT0; //disable option rom - SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value); - - Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); - Value &= ~BIT2; //cs2 disable - SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); - } - return; -} - -STATIC -VOID -PcieDbiCs2Enable ( - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN BOOLEAN Val - ) -{ - UINT32 RegVal; - - RegRead ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, - RegVal - ); - if (Val) { - RegVal = RegVal | BIT2; - /* BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/ - } else { - RegVal = RegVal & (~BIT2); - } - RegWrite ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, - RegVal - ); -} - -STATIC -BOOLEAN -PcieDBIReadOnlyWriteEnable ( - IN UINT32 HostBridgeNum, - IN UINT32 Port - ) -{ - UINT32 Val; - - RegRead ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, - Val - ); - if (Val == 0x1) { - return TRUE; - } else { - RegWrite ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, - 0x1 - ); - /* Delay 10us to make sure the PCIE device have enouph time to response. */ - MicroSecondDelay(10); - RegRead ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, - Val - ); - if (Val == 0x1) { - return TRUE; - } - } - DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n")); - return FALSE; -} - -STATIC -VOID -SwitchPcieASPMSupport ( - IN UINT32 HostBridgeNum, - IN UINT32 Port, - IN UINT8 Val - ) -{ - PCIE_EP_PCIE_CAP3_U PcieCap3; - - if (Port >= PCIE_MAX_ROOTBRIDGE) { - DEBUG ((DEBUG_ERROR, "Port is not valid\n")); - return; - } - if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) { - DEBUG ((DEBUG_INFO, "PcieDBI ReadOnly Reg do not Enable!!!\n")); - return; - } - PcieDbiCs2Enable (HostBridgeNum, Port, FALSE); - - RegRead ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, - PcieCap3.UInt32 - ); - PcieCap3.Bits.active_state_power_management = Val; - RegWrite ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, - PcieCap3.UInt32 - ); - RegRead ( - PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, - PcieCap3.UInt32 - ); - DEBUG ((DEBUG_INFO, - "ASPI active state power management: %d\n", - PcieCap3.Bits.active_state_power_management)); - - PcieDbiCs2Enable (HostBridgeNum, Port, TRUE); -} - -EFI_STATUS -EFIAPI -PciePortInit ( - IN UINT32 soctype, - IN UINT32 HostBridgeNum, - IN PCIE_DRIVER_CFG *PcieCfg - ) -{ - UINT16 Count = 0; - UINT32 PortIndex = PcieCfg->PortIndex; - - if (PortIndex >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - if (0x1610 == soctype) - { - mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex]; - DEBUG((DEBUG_INFO, "Soc type is 161x\n")); - } - else - { - mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex); - DEBUG((DEBUG_INFO, "Soc type is 660\n")); - } - - /* assert reset signals */ - (VOID)AssertPcieCoreReset(soctype, HostBridgeNum, PortIndex); - (VOID)AssertPciePcsReset(soctype, HostBridgeNum, PortIndex); - (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 0); - (VOID)DeassertPcieCoreReset(soctype, HostBridgeNum, PortIndex); - /* de-assert phy reset */ - (VOID)DeassertPciePcsReset(soctype, HostBridgeNum, PortIndex); - - /* de-assert core reset */ - (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 1); - - while (!PcieClockIsLock(soctype, HostBridgeNum, PortIndex)) { - MicroSecondDelay(1000); - Count++; - if (Count >= 50) { - DEBUG((DEBUG_ERROR, "HostBridge %d, Port %d PLL Lock failed\n", HostBridgeNum, PortIndex)); - return PCIE_ERR_LINK_OVER_TIME; - } - } - /* initialize phy */ - (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex); - - (VOID)PcieModeSet(soctype, HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType); - (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3); - (VOID)PciePortNumSet(soctype, HostBridgeNum, PortIndex, 0); - /* setup root complex */ - (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth); - - /* disable link up interrupt */ - (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex); - - /* disable ASPM */ - SwitchPcieASPMSupport (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE); - - /* Pcie Equalization*/ - (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); - - /* Disable RC Option Rom */ - DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); - /* assert LTSSM enable */ - (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); - - PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); - /* - * The default size of BAR0 in Hi1610 host bridge is 0x10000000, - * which will bring problem when most resource has been allocated - * to BAR0 in host bridge.However, we need not use BAR0 in host bridge - * in RC mode. Here we just disable it - */ - PcieRegWrite(PortIndex, 0x10, 0); - (VOID)PcieWriteOwnConfig(HostBridgeNum, PortIndex, 0xa, 0x0604); - /* check if the link is up or not */ - while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) { - MicroSecondDelay(1000); - Count++; - if (Count >= 1000) { - DEBUG((DEBUG_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex)); - return PCIE_ERR_LINK_OVER_TIME; - } - } - DEBUG((DEBUG_INFO, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex)); - - PcieRegWrite(PortIndex, 0x8BC, 0); - - return EFI_SUCCESS; -} - - - - -EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable) -{ - PCIE_SYS_CTRL20_U dbi_ro_enable; - - if (Port >= PCIE_MAX_ROOTBRIDGE) { - return EFI_INVALID_PARAMETER; - } - - PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); - dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG); - dbi_ro_enable.Bits.ro_sel = Enable; - PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32); - PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); - - return EFI_SUCCESS; - -} - -VOID PcieDelay(UINT32 dCount) -{ - volatile UINT32 *uwCnt = &dCount; - - while(*uwCnt > 0) - { - *uwCnt = *uwCnt - 1; - } - -} - diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h deleted file mode 100644 index 553caaa301815152c38288d6d54000ac38f89041..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ /dev/null @@ -1,243 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __PCIE_INIT_LIB_H__ -#define __PCIE_INIT_LIB_H__ - - -#include -#include -#include -#include -#include "PcieKernelApi.h" - -#define PCIE_AXI_SLAVE_BASE (0xb3000000) -#define PCIE_MAX_AXI_SIZE (0x1000000) -#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE) -#define PCIE_SMMU_BASE (0xb0040000) - - -#define PCIE_DMA_CHANNEL_NUM (2) -#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000) -#define PCIE_DMA_BURST_SIZE (0x80000000) - -#define PCIE_ADDR_BASE_OFFSET 0x46C00000 -#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST) -#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL - - - -#define PCIE_GIC_MSI_ITS_BASE (0xb7010040) -#define PCIE_INT_BASE (13824) -#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64) - -#define PCIE_NTB_MEM_SIZE (0x1000000) -#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K -#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M -#define PCIE_NTB_BAR45_SIZE (0x800000) - -#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0} -#define PCIE_IATU_INBOUND_MASK (0x80000000) -#define PCIE_IATU_INDEX_MASK (0x7f) -#define PCIE_IATU_TYPE_MASK (0x1f) -#define PCIE_IATU_EN (0x1 << 0) -#define PCIE_IATU_SHIFT_MODE (0x1 << 1) -#define PCIE_IATU_BAR_MODE (0x1 << 2) -#define PCIE_IATU_FUNC_MODE (0x1 << 3) -#define PCIE_IATU_AT_MODE (0x1 << 4) //AT mach mode -#define PCIE_IATU_ATTR_MODE (0x1 << 5) -#define PCIE_IATU_TD_MODE (0x1 << 6) //TD -#define PCIE_IATU_TC_MODE (0x1 << 7) // TC -#define PCIE_IATU_PREFETCH_MODE (0x1 << 8) -#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate - -#define PCIE_BAR_MASK_SIZE (0x800000) -#define PCIE_BAR_TYPE_32 (0) -#define PCIE_BAR_TYPE_64 (2) -#define PCIE_BAR_PREFETCH_MODE (1) - -#define PCS_SDS_CFG_REG 0x204 -#define SDS_CFG_STRIDE 0x4 -#define MUX_LOS_ALOS_REG_OFFSET 0x508 -#define MUX_CFG_STRIDE 0x4 -#define CH_RXTX_STATUS_CFG_EN BIT1 -#define CH_RXTX_STATUS_CFG BIT2 -#define RegWrite(addr,data) MmioWrite32((addr), (data)) -#define RegRead(addr,data) ((data) = MmioRead32 (addr)) - -#define PCIE_ASPM_DISABLE 0x0 -#define PCIE_ASPM_ENABLE 0x1 - -typedef struct tagPcieDebugInfo -{ - UINT32 pcie_rdma_start_cnt; - UINT32 pcie_wdma_start_cnt; - UINT64 pcie_wdma_transfer_len; - UINT64 pcie_rdma_transfer_len; - UINT32 pcie_rdma_fail_cnt; - UINT32 pcie_wdma_fail_cnt; -}pcie_debug_info_s; - - -#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF) -#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F) -#define bdf_2_f(bdf) ((bdf >> 0) & 0x7) -#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0)) - - - -typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved); - - -typedef struct { - UINT32 ViewPort; //iATU Viewport Register - UINT32 RegionCtrl1; //Region Control 1 Register - UINT32 RegionCtrl2; //Region Control 2 Register - UINT32 BaseLow; //Lower Base Address Register - UINT32 BaseHigh; //Upper Base Address Register - UINT32 Limit; //Limit Address Register - UINT32 TargetLow; //Lower Target Address Register - UINT32 TargetHigh; //Upper Target Address Register -} PCIE_IATU_VA; - -typedef enum { - PCIE_IATU_OUTBOUND = 0x0, - PCIE_IATU_INBOUND = 0x1, -} PCIE_IATU_DIR; - -typedef struct { - PCIE_IATU_DIR IatuType; - UINT64 IatuBase; - UINT64 IatuSize; - UINT64 IatuTarget; -} PCIE_IATU; - -typedef struct { - UINT32 IatuType; - UINT64 IatuBase; - UINT32 IatuLimit; - UINT64 IatuTarget; - UINT32 Valid; -} PCIE_IATU_HW; - -typedef struct { - UINT32 PortIndex; - PCIE_PORT_INFO PortInfo; - PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND]; - PCIE_IATU_HW InBound[PCIE_MAX_INBOUND]; -} PCIE_DRIVER_CFG; - -typedef enum { - PCIE_CONFIG_REG = 0x0, - PCIE_SYS_CONTROL = 0x1, -} PCIE_RW_MODE; - -typedef union { - PCIE_DRIVER_CFG PcieDevice; - PCIE_NTB_CFG NtbDevice; -} DRIVER_CFG_U; - -typedef struct { - VOID *MappedOutbound[PCIE_MAX_OUTBOUND]; - UINT32 OutboundType[PCIE_MAX_OUTBOUND]; - UINT32 OutboundEn[PCIE_MAX_OUTBOUND]; -} PCIE_MAPPED_IATU_ADDR; - -typedef struct { - BOOLEAN PortIsInitilized[PCIE_MAX_ROOTBRIDGE]; - DRIVER_CFG_U Dev[PCIE_MAX_ROOTBRIDGE]; - VOID *DmaResource[PCIE_MAX_ROOTBRIDGE]; - UINT32 DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM]; - VOID *RegResource[PCIE_MAX_ROOTBRIDGE]; - VOID *CfgResource[PCIE_MAX_ROOTBRIDGE]; -} PCIE_INIT_CFG; - -typedef enum { - PCIE_MMIO_IEP_CFG = 0x1000, - PCIE_MMIO_IEP_CTRL = 0x0, - PCIE_MMIO_EEP_CFG = 0x9000, - PCIE_MMIO_EEP_CTRL = 0x8000, -} NTB_MMIO_MODE; - -typedef struct tagPcieDmaDes -{ - UINT32 uwChanCtrl; - UINT32 uwLen; - UINT32 uwLocalLow; - UINT32 uwLocalHigh; - UINT32 uwTagetLow; - UINT32 uwTagetHigh; -}pcie_dma_des_s,*pcie_dma_des_ps; - -typedef enum { - PCIE_IATU_MEM, - PCIE_IATU_CFG = 0x4, - PCIE_IATU_IO -} PCIE_IATU_OUT_TYPE; - -typedef enum { - PCIE_PAYLOAD_128B = 0, - PCIE_PAYLOAD_256B, - PCIE_PAYLOAD_512B, - PCIE_PAYLOAD_1024B, - PCIE_PAYLOAD_2048B, - PCIE_PAYLOAD_4096B, - PCIE_RESERVED_PAYLOAD -} PCIE_PAYLOAD_SIZE; - -typedef struct tagPcieDfxInfo -{ - PCIE_EP_AER_CAP0_U aer_cap0; - PCIE_EP_AER_CAP1_U aer_cap1; - PCIE_EP_AER_CAP2_U aer_cap2; - PCIE_EP_AER_CAP3_U aer_cap3; - PCIE_EP_AER_CAP4_U aer_cap4; - PCIE_EP_AER_CAP5_U aer_cap5; - PCIE_EP_AER_CAP6_U aer_cap6; - UINT32 hdr_log0; - UINT32 hdr_log1; - UINT32 hdr_log2; - UINT32 hdr_log3; - PCIE_EP_AER_CAP11_U aer_cap11; - PCIE_EP_AER_CAP12_U aer_cap12; - PCIE_EP_AER_CAP13_U aer_cap13; - - PCIE_EP_PORTLOGIC62_U port_logic62; - PCIE_EP_PORTLOGIC64_U port_logic64; - PCIE_EP_PORTLOGIC66_U port_logic66; - PCIE_EP_PORTLOGIC67_U port_logic67; - PCIE_EP_PORTLOGIC69_U port_logic69; - PCIE_EP_PORTLOGIC75_U port_logic75; - PCIE_EP_PORTLOGIC76_U port_logic76; - PCIE_EP_PORTLOGIC77_U port_logic77; - PCIE_EP_PORTLOGIC79_U port_logic79; - PCIE_EP_PORTLOGIC80_U port_logic80; - PCIE_EP_PORTLOGIC81_U port_logic81; - PCIE_EP_PORTLOGIC87_U port_logic87; - - PCIE_CTRL_10_U pcie_ctrl10; - UINT32 slve_rerr_addr_low; - UINT32 slve_rerr_addr_up; - UINT32 slve_werr_addr_low; - UINT32 slve_werr_addr_up; - UINT32 pcie_state4; - UINT32 pcie_state5; -}PCIE_DFX_INFO_S; - -VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode); - -UINT32 PcieIsLinkDown(UINT32 Port); - -BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port); - -EFI_STATUS PcieWaitLinkUp(UINT32 Port); - -EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable); - -#endif diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h deleted file mode 100644 index 99e881efe754c152ec35c1165e5064a70146552d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h +++ /dev/null @@ -1,338 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __PCIE_KERNEL_API_H__ -#define __PCIE_KERNEL_API_H__ - -#define PCIE_MAX_OUTBOUND (6) -#define PCIE_MAX_INBOUND (4) -#define PCIE3_MAX_OUTBOUND (16) -#define PCIE3_MAX_INBOUND (16) - -#define PCIE_LINK_LOOP_CNT (0x1000) -#define PCIE_IATU_ADDR_MASK (0xFFFFF000) -#define PCIE_1M_ALIGN_SHIRFT (20) -#define PCIE_BDF_MASK (0xF0000FFF) -#define PCIE_BUS_SHIRFT (20) -#define PCIE_DEV_SHIRFT (15) -#define PCIE_FUNC_SHIRFT (12) - -#define PCIE_DBI_CS2_ENABLE (0x1) -#define PCIE_DBI_CS2_DISABLE (0x0) - -#define PCIE_DMA_CHANLE_READ (0x1) -#define PCIE_DMA_CHANLE_WRITE (0x0) - - -#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1) -#define PCIE_ERR_LINK_OVER_TIME EFIERR (2) -#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3) -#define PCIE_ERR_ALREADY_INIT EFIERR (4) -#define PCIE_ERR_PARAM_INVALID EFIERR (5) -#define PCIE_ERR_MEM_OPT_OVER EFIERR (6) -#define PCIE_ERR_NOT_INIT EFIERR (7) -#define PCIE_ERR_CFG_OPT_OVER EFIERR (8) -#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9) -#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10) -#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11) -#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12) -#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13) -#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14) -#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15) -#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16) -#define PCIE_ERR_DMA_ABORT EFIERR (17) -#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18) - -typedef enum { - PCIE_ROOT_COMPLEX, - PCIE_END_POINT, - PCIE_NTB_TO_NTB, - PCIE_NTB_TO_RP, -} PCIE_PORT_TYPE; - -typedef enum { - PCIE_GEN1_0 = 1, //PCIE 1.0 - PCIE_GEN2_0 = 2, //PCIE 2.0 - PCIE_GEN3_0 = 4 //PCIE 3.0 -} PCIE_PORT_GEN; - -typedef enum { - PCIE_WITDH_X1 = 0x1, - PCIE_WITDH_X2 = 0x3, - PCIE_WITDH_X4 = 0x7, - PCIE_WITDH_X8 = 0xf, - PCIE_WITDH_INVALID -} PCIE_PORT_WIDTH; - - -typedef struct { - PCIE_PORT_TYPE PortType; - PCIE_PORT_WIDTH PortWidth; - PCIE_PORT_GEN PortGen; - UINT8 PcieLinkUp; -} PCIE_PORT_INFO; - -typedef struct tagPciecfg_params -{ - UINT32 preemphasis; - UINT32 deemphasis; - UINT32 swing; - UINT32 balance; -}pcie_cfg_params_s; - -typedef enum { - PCIE_CORRECTABLE_ERROR = 0, - PCIE_NON_FATAL_ERROR, - PCIE_FATAL_ERROR, - PCIE_UNSUPPORTED_REQUEST_ERROR, - PCIE_ALL_ERROR -} PCIE_ERROR_TYPE; - -typedef union tagPcieDeviceStatus -{ - struct - { - UINT16 correctable_error : 1; - UINT16 non_fatal_error : 1; - UINT16 fatal_error : 1; - UINT16 unsupported_error : 1; - UINT16 aux_power : 1; - UINT16 transaction_pending : 1; - UINT16 reserved_6_15 : 10; - }Bits; - - UINT16 Value; -}pcie_device_status_u; - - -typedef union tagPcieUcAerStatus -{ - struct - { - UINT32 undefined : 1 ; /* [0] undefined */ - UINT32 reserved_1_3 : 3 ; /* reserved */ - UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */ - UINT32 reserved_5_11 : 7 ; /* reserved */ - UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */ - UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */ - UINT32 completion_time_out : 1 ; /* Completion Timeout Status */ - UINT32 compler_abort_status : 1 ; /* Completer Abort Status */ - UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */ - UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */ - UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/ - UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */ - UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */ - UINT32 reserved_21 : 1 ; /* reserved */ - UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */ - UINT32 reserved_23 : 1 ; /* reserved*/ - UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */ - UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */ - UINT32 reserved_26_31 : 1 ; /* reserved */ - }Bits; - - UINT32 Value; -}pcie_uc_aer_status_u; - -typedef union tagPcieCoAerStatus -{ - struct - { - UINT32 receiver_error_status : 1 ; /* Receiver Error Status */ - UINT32 reserved_1_5 : 5 ; /* Reserved */ - UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */ - UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */ - UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/ - UINT32 reserved_9_11 : 3 ; /* Reserved */ - UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */ - UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/ - UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/ - UINT32 reserved_15_31 : 1 ; /* Reserved */ - }Bits; - UINT32 Value; -}pcie_co_aer_status_u; - -typedef struct tagPcieAerStatus -{ - pcie_uc_aer_status_u uc_aer_status; - pcie_co_aer_status_u co_aer_status; -}pcie_aer_status_s; - - - -typedef struct tagPcieLoopTestResult -{ - UINT32 tx_pkts_cnt; - UINT32 rx_pkts_cnt; - UINT32 error_pkts_cnt; - UINT32 droped_pkts_cnt; - UINT32 push_cnt; - pcie_device_status_u device_status; - pcie_aer_status_s pcie_aer_status; -} pcie_loop_test_result_s; - -typedef struct tagPcieDmaChannelAttrs { - UINT32 dma_chan_en; - UINT32 dma_mode; - UINT32 channel_status; -}pcie_dma_channel_attrs_s; - -typedef enum tagPcieDmaChannelStatus -{ - PCIE_DMA_CS_RESERVED = 0, - PCIE_DMA_CS_RUNNING = 1, - PCIE_DMA_CS_HALTED = 2, - PCIE_DMA_CS_STOPPED = 3 -}pcie_dma_channel_status_e; - -typedef enum tagPcieDmaIntType{ - PCIE_DMA_INT_TYPE_DONE=0, - PCIE_DMA_INT_TYPE_ABORT, - PCIE_DMA_INT_ALL, - PCIE_DMA_INT_NONE -}pcie_dma_int_type_e; - -typedef enum tagPcieMulWinSize -{ - WIN_SIZE_4K = 0xc, - WIN_SIZE_8K, - WIN_SIZE_16K, - WIN_SIZE_32K, - WIN_SIZE_64K, - WIN_SIZE_128K, - WIN_SIZE_256K, - WIN_SIZE_512K, - WIN_SIZE_1M, - WIN_SIZE_2M, - WIN_SIZE_4M, - WIN_SIZE_8M, - WIN_SIZE_16M, - WIN_SIZE_32M, - WIN_SIZE_64M, - WIN_SIZE_128M, - WIN_SIZE_256M, - WIN_SIZE_512M, - WIN_SIZE_1G, - WIN_SIZE_2G, - WIN_SIZE_4G, - WIN_SIZE_8G, - WIN_SIZE_16G, - WIN_SIZE_32G, - WIN_SIZE_64G, - WIN_SIZE_128G, - WIN_SIZE_256G, - WIN_SIZE_512G = 0x27, -}pcie_mul_win_size_e; - -typedef struct tagPcieMultiCastCfg -{ - UINT64 multicast_base_addr; - pcie_mul_win_size_e base_addr_size; - UINT64 base_translate_addr; -}pcie_multicast_cfg_s; - -typedef enum tagPcieMode -{ - PCIE_EP_DEVICE = 0x0, - LEGACY_PCIE_EP_DEVICE = 0x1, - RP_OF_PCIE_RC = 0x4, - PCIE_INVALID = 0x100 -}pcie_mode_e; - -typedef struct{ - UINT32 PortIndex; - PCIE_PORT_INFO PortInfo; - UINT64 iep_bar01; /*iep bar 01*/ - UINT64 iep_bar23; - UINT64 iep_bar45; - UINT64 iep_bar01_xlat; - UINT64 iep_bar23_xlat; - UINT64 iep_bar45_xlat; - UINT64 iep_bar_lmt23; - UINT64 iep_bar_lmt45; /*bar limit*/ - UINT64 eep_bar01; - UINT64 eep_bar23; - UINT64 eep_bar45; - UINT64 eep_bar23_xlat; - UINT64 eep_bar45_xlat; - UINT64 eep_bar_lmt23; /*bar limit*/ - UINT64 eep_bar_lmt45; /*bar limit*/ -} PCIE_NTB_CFG; - -extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info); - -extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl); - -extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed); - -extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params); - -extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params); - - -extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control); - -extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute); - -extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status); - -extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type); - -extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type); - -extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel); - - -extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status); - -extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type); - - -extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size); - -extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size); - -extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num); - -extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg); - -extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell); - -extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type); - -extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type); - -extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result); -extern int pcie_port_reset(UINT32 Port); - -extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error); - -extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error); - -extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \ -pcie_device_status_u *pcie_stat); -extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap); - -extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status); -extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func); - -extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type); - - -extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type); - - -extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length); - -extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length); - -extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length); - -extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length); - -#endif diff --git a/Silicon/Hisilicon/Hi1610/Hi1610.dec b/Silicon/Hisilicon/Hi1610/Hi1610.dec deleted file mode 100644 index ac099ab11760e211affae4ea656c3340f66272c8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610.dec +++ /dev/null @@ -1,17 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - DEC_SPECIFICATION = 0x0001001A - PACKAGE_NAME = Hi1610Pkg - PACKAGE_GUID = 0063d37d-adab-47b4-9926-af83539ea167 - PACKAGE_VERSION = 0.1 - -[Includes] - Include diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf deleted file mode 100644 index 6c4674983c53be3b5b01c377e532d63322c17f8a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf +++ /dev/null @@ -1,50 +0,0 @@ -## @file -# -# ACPI table data and ASL sources required to boot the platform. -# -# Copyright (c) 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Hi1610AcpiTables - FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD - MODULE_TYPE = USER_DEFINED - VERSION_STRING = 1.0 - -[Sources] - Dsdt/DsdtHi1610.asl - Facs.aslc - Fadt.aslc - Gtdt.aslc - MadtHi1610.aslc - D03Mcfg.aslc - D03Iort.asl - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/Hi1610/Hi1610.dec - Silicon/Hisilicon/HisiPkg.dec - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdCoreCount - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl deleted file mode 100644 index 4101d86672cdaba26888ea49573f405bb239b215..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Intel ACPI Component Architecture - * iASL Compiler/Disassembler version 20151124-64 - * Copyright (c) 2015 Intel Corporation - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Template for [IORT] ACPI Table (static data table) - * Format: [ByteLength] FieldName : HexFieldValue - */ -[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 000002e4 -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "HIP06 " -[0004] Oem Revision : 00000000 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20151124 - -[0004] Node Count : 00000008 -[0004] Node Offset : 00000034 -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00 - -/* ITS 0, for dsa */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000000 - -/* mbi-gen dsa mbi0 - usb, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0017] Device Name : "\_SB_.MBI0" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040080 // device id -[0004] Output Reference : 00000034 // point to its dsa -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa mbi1 - sas1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI1" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa mbi2 - sas2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI2" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040040 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa mbi3 - dsa0, srv named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI3" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI4" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1c -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI5" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1d -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa mbi6 - dsa sas0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI6" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040900 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen mbi7 - RoCE named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI7" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1e -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* RC 0 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000000 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00000000 -[0004] ID Count : 00002000 -[0004] Output Base : 00000000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* RC 1 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000001 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 0000e000 -[0004] ID Count : 00002000 -[0004] Output Base : 0000e000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* RC 2 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000002 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00008000 -[0004] ID Count : 00002000 -[0004] Output Base : 00008000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc deleted file mode 100644 index 30e9878cda6abe6daa65161884599b9d9e33b92b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2016 Hisilicon Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - */ - -#include -#include "Hi1610Platform.h" - -#define ACPI_6_1_MCFG_VERSION 0x1 - -#pragma pack(1) -typedef struct -{ - UINT64 ullBaseAddress; - UINT16 usSegGroupNum; - UINT8 ucStartBusNum; - UINT8 ucEndBusNum; - UINT32 Reserved2; -}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; - -typedef struct -{ - EFI_ACPI_DESCRIPTION_HEADER Header; - UINT64 Reserved1; -}EFI_ACPI_6_1_MCFG_TABLE_CONFIG; - -typedef struct -{ - EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[3]; -}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; -#pragma pack() - -EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= -{ - { - { - EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_6_1_MCFG_VERSION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION - }, - 0x0000000000000000, //Reserved - }, - { - - { - 0xb0000000, //Base Address - 0x0, //Segment Group Number - 0x0, //Start Bus Number - 0x1f, //End Bus Number - 0x00000000, //Reserved - }, - { - 0xb0000000, //Base Address - 0x1, //Segment Group Number - 0xe0, //Start Bus Number - 0xff, //End Bus Number - 0x00000000, //Reserved - }, - { - 0xa0000000, //Base Address - 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x9f, //End Bus Number - 0x00000000, //Reserved - }, - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl deleted file mode 100644 index f98570aa346cfb9b7e8f59dc979d731c1b287195..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl +++ /dev/null @@ -1,82 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - // - // A57x16 Processor declaration - // - Device(CPU0) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - Device(CPU1) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - Device(CPU2) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - Device(CPU3) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - Device(CPU6) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - Device(CPU7) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } - Device(CPU8) { - Name(_HID, "ACPI0007") - Name(_UID, 8) - } - Device(CPU9) { - Name(_HID, "ACPI0007") - Name(_UID, 9) - } - Device(CP10) { - Name(_HID, "ACPI0007") - Name(_UID, 10) - } - Device(CP11) { - Name(_HID, "ACPI0007") - Name(_UID, 11) - } - Device(CP12) { - Name(_HID, "ACPI0007") - Name(_UID, 12) - } - Device(CP13) { - Name(_HID, "ACPI0007") - Name(_UID, 13) - } - Device(CP14) { - Name(_HID, "ACPI0007") - Name(_UID, 14) - } - Device(CP15) { - Name(_HID, "ACPI0007") - Name(_UID, 15) - } -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl deleted file mode 100644 index 0f28b19d529f57ca211df8a503bc8eaa6da79a35..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl +++ /dev/null @@ -1,29 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(COM0) { - Name(_HID, "HISI0031") //it is not 16550 compatible - Name(_UID, Zero) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x80300000, 0x1000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 200000000}, - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl deleted file mode 100644 index 59c886f6edc42f8f843f35c3ff053203e0589fdd..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ /dev/null @@ -1,685 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - Device (MDIO) - { - OperationRegion(CLKR, SystemMemory, 0x60000338, 8) - Field(CLKR, DWordAcc, NoLock, Preserve) { - CLKE, 1, // clock enable - , 31, - CLKD, 1, // clode disable - , 31, - } - OperationRegion(RSTR, SystemMemory, 0x60000A38, 8) - Field(RSTR, DWordAcc, NoLock, Preserve) { - RSTE, 1, // reset - , 31, - RSTD, 1, // de-reset - , 31, - } - - Name(_HID, "HISI0141") - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) - }) - - Method(_RST, 0, Serialized) { - Store (0x1, RSTE) - Sleep (10) - Store (0x1, CLKD) - Sleep (10) - Store (0x1, RSTD) - Sleep (10) - Store (0x1, CLKE) - Sleep (10) - } - } - - Device (DSF0) - { - OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) - Field(H3SR, DWordAcc, NoLock, Preserve) { - H3ST, 1, - , 31, //RESERVED - } - OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) - Field(H4SR, DWordAcc, NoLock, Preserve) { - H4ST, 1, - , 31, //RESERVED - } - // DSAF RESET - OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) - Field(DRER, DWordAcc, NoLock, Preserve) { - DRTE, 1, - , 31, //RESERVED - DRTD, 1, - , 31, //RESERVED - } - // NT RESET - OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) - Field(NRER, DWordAcc, NoLock, Preserve) { - NRTE, 1, - , 31, //RESERVED - NRTD, 1, - , 31, //RESERVED - } - // XGE RESET - OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) - Field(XRER, DWordAcc, NoLock, Preserve) { - XRTE, 31, - , 1, //RESERVED - XRTD, 31, - , 1, //RESERVED - } - - // GE RESET - OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) - Field(GRTR, DWordAcc, NoLock, Preserve) { - GR0E, 30, - , 2, //RESERVED - GR0D, 30, - , 2, //RESERVED - GR1E, 18, - , 14, //RESERVED - GR1D, 18, - , 14, //RESERVED - } - // PPE RESET - OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) - Field(PRTR, DWordAcc, NoLock, Preserve) { - PRTE, 10, - , 22, //RESERVED - PRTD, 10, - , 22, //RESERVED - } - - // RCB PPE COM RESET - OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) - Field(RRTR, DWordAcc, NoLock, Preserve) { - RRTE, 1, - , 31, //RESERVED - RRTD, 1, - , 31, //RESERVED - } - - // DSAF Channel RESET - OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8) - Field(DCRR, DWordAcc, NoLock, Preserve) { - DCRE, 1, - , 31, //RESERVED - DCRD, 1, - , 31, //RESERVED - } - - // RoCE RESET - OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8) - Field(RKRR, DWordAcc, NoLock, Preserve) { - RKRE, 1, - , 31, //RESERVED - RKRD, 1, - , 31, //RESERVED - } - - // RoCE Clock enable/disable - OperationRegion(RKCR, SystemMemory, 0xC0000328, 8) - Field(RKCR, DWordAcc, NoLock, Preserve) { - RCLE, 1, - , 31, //RESERVED - RCLD, 1, - , 31, //RESERVED - } - - // Hilink access sel cfg reg - OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) - Field(HSER, DWordAcc, NoLock, Preserve) { - HSEL, 2, // hilink_access_sel & hilink_access_wr_pul - , 30, // RESERVED - } - - // Serdes - OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) - Field(H4LR, DWordAcc, NoLock, Preserve) { - H4L0, 16, // port0 - , 16, //RESERVED - Offset (0x400), - H4L1, 16, // port1 - , 16, //RESERVED - Offset (0x800), - H4L2, 16, // port2 - , 16, //RESERVED - Offset (0xc00), - H4L3, 16, // port3 - , 16, //RESERVED - } - OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) - Field(H3LR, DWordAcc, NoLock, Preserve) { - H3L2, 16, // port4 - , 16, //RESERVED - Offset (0x400), - H3L3, 16, // port5 - , 16, //RESERVED - } - Name (_HID, "HISI00B2") - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) - Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"mode", "6port-16rss"}, - Package () {"buf-size", 4096}, - Package () {"desc-num", 1024}, - Package () {"interrupt-parent", Package() {\_SB.MBI3}}, - } - }) - - //reset XGE port - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XRST, 2, Serialized) { - ShiftLeft (0x2082082, Arg0, Local0) - Or (Local0, 0x1, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset XGE core - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XCRT, 2, Serialized) { - ShiftLeft (0x2080, Arg0, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset GE port - //Arg0 : GE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(GRST, 2, Serialized) { - If (LLessEqual (Arg0, 5)) { - //Service port - ShiftLeft (0x2082082, Arg0, Local0) - ShiftLeft (0x1, Arg0, Local1) - - If (LEqual (Arg1, 0)) { - Store(Local1, GR1E) - Store(Local0, GR0E) - } Else { - Store(Local0, GR0D) - Store(Local1, GR1D) - } - } - } - - //reset PPE port - //Arg0 : PPE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(PRST, 2, Serialized) { - ShiftLeft (0x1, Arg0, Local0) - If (LEqual (Arg1, 0)) { - Store(Local0, PRTE) - } Else { - Store(Local0, PRTD) - } - } - - //reset DSAF channels - //Arg0 : mask - //Arg1 : 0 reset, 1 de-reset - Method(DCRT, 2, Serialized) { - If (LEqual (Arg1, 0)) { - Store(Arg0, DCRE) - } Else { - Store(Arg0, DCRD) - } - } - - //reset RoCE - //Arg0 : 0 reset, 1 de-reset - Method(RRST, 1, Serialized) { - If (LEqual (Arg0, 0)) { - Store(0x1, RKRE) - } Else { - Store(0x1, RCLD) - Store(0x1, RKRD) - sleep(20) - Store(0x1, RCLE) - } - } - - // Set Serdes Loopback - //Arg0 : port - //Arg1 : 0 disable, 1 enable - Method(SRLP, 2, Serialized) { - ShiftLeft (Arg1, 10, Local0) - Switch (ToInteger(Arg0)) - { - case (0x0){ - Store (0, HSEL) - Store (H4L0, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L0) - } - case (0x1){ - Store (0, HSEL) - Store (H4L1, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L1) - } - case (0x2){ - Store (0, HSEL) - Store (H4L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L2) - } - case (0x3){ - Store (0, HSEL) - Store (H4L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L3) - } - case (0x4){ - Store (3, HSEL) - Store (H3L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L2) - } - case (0x5){ - Store (3, HSEL) - Store (H3L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L3) - } - } - } - - //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) - //Arg1 : port - //Arg2 : 0 disable, 1 enable - Method(DRST, 3, Serialized) - { - Switch (ToInteger(Arg0)) - { - //DSAF reset - case (0x1) - { - Store (Arg2, Local0) - If (LEqual (Local0, 0)) - { - Store (0x1, DRTE) - Store (0x1, NRTE) - Sleep (10) - Store (0x1, RRTE) - } - Else - { - Store (0x1, DRTD) - Store (0x1, NRTD) - Sleep (10) - Store (0x1, RRTD) - } - } - //Reset PPE port - case (0x2) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - PRST (Local0, Local1) - } - - //Reset XGE core - case (0x3) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XCRT (Local0, Local1) - } - //Reset XGE port - case (0x4) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XRST (Local0, Local1) - } - - //Reset GE port - case (0x5) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - GRST (Local0, Local1) - } - - //Reset DSAF Channels - case (0x6) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - DCRT (Local0, Local1) - } - - //Reset RoCE - case (0x7) - { - // Discarding Arg1 as it is always 0 - Store (Arg2, Local0) - RRST (Local0) - } - } - } - - // _DSM Device Specific Method - // - // Arg0: UUID Unique function identifier - // Arg1: Integer Revision Level - // Arg2: Integer Function Index - // 0 : Return Supported Functions bit mask - // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) - // Arg3[1] : port index in dsaf - // Arg3[2] : 0 reset, 1 cancle reset - // 2 : Set Serdes Loopback - // Arg3[0] : port - // Arg3[1] : 0 disable, 1 enable - // 3 : LED op set - // Arg3[0] : op type - // Arg3[1] : port - // Arg3[2] : para - // 4 : Get port type (GE or XGE) - // Arg3[0] : port index in dsaf - // Return : 0 GE, 1 XGE - // 5 : Get sfp status - // Arg3[0] : port index in dsaf - // Return : 0 no sfp, 1 have sfp - // Arg3: Package Parameters - Method (_DSM, 4, Serialized) - { - If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) - { - If (LEqual (Arg1, 0x00)) - { - Switch (ToInteger(Arg2)) - { - case (0x0) - { - Return (Buffer () {0x3F}) - } - - //Reset Sequence - case (0x1) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - Store (DeRefOf (Index (Arg3, 2)), Local2) - DRST (Local0, Local1, Local2) - } - - //Set Serdes Loopback - case (0x2) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - SRLP (Local0, Local1) - } - - //LED op set - case (0x3) - { - - } - - // Get port type (GE or XGE) - case (0x4) - { - Store (0, Local1) - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LLessEqual (Local0, 3)) - { - // mac0: Hilink4 Lane0 - // mac1: Hilink4 Lane1 - // mac2: Hilink4 Lane2 - // mac3: Hilink4 Lane3 - Store (H4ST, Local1) - } - ElseIf (LLessEqual (Local0, 5)) - { - // mac4: Hilink3 Lane2 - // mac5: Hilink3 Lane3 - Store (H3ST, Local1) - } - - Return (Local1) - } - - //Get sfp status - case (0x5) - { - - } - } - } - } - Return (Buffer() {0x00}) - } - Device (PRT0) - { - Name (_ADR, 0x0) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT1) - { - Name (_ADR, 0x1) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 1}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT4) - { - Name (_ADR, 0x4) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 4}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 0}, - Package () {"mdio-node", Package (){\_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - Device (PRT5) - { - Name (_ADR, 0x5) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 5}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 1}, - Package () {"mdio-node", Package (){\_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - } - Device (ETH4) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 4}, - } - }) - } - Device (ETH5) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 5}, - } - }) - } - Device (ETH0) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 0}, - } - }) - } - Device (ETH1) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 1}, - } - }) - } - Device (ROCE) { - Name(_HID, "HISI00D1") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}}, - Package () {"dsaf-handle", Package (){\_SB.DSF0}}, - Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes - Package () {"interrupt-names", Package() {"hns-roce-comp-0", - "hns-roce-comp-1", - "hns-roce-comp-2", - "hns-roce-comp-3", - "hns-roce-comp-4", - "hns-roce-comp-5", - "hns-roce-comp-6", - "hns-roce-comp-7", - "hns-roce-comp-8", - "hns-roce-comp-9", - "hns-roce-comp-10", - "hns-roce-comp-11", - "hns-roce-comp-12", - "hns-roce-comp-13", - "hns-roce-comp-14", - "hns-roce-comp-15", - "hns-roce-comp-16", - "hns-roce-comp-17", - "hns-roce-comp-18", - "hns-roce-comp-19", - "hns-roce-comp-20", - "hns-roce-comp-21", - "hns-roce-comp-22", - "hns-roce-comp-23", - "hns-roce-comp-24", - "hns-roce-comp-25", - "hns-roce-comp-26", - "hns-roce-comp-27", - "hns-roce-comp-28", - "hns-roce-comp-29", - "hns-roce-comp-30", - "hns-roce-comp-31", - "hns-roce-async", - "hns-roce-common"}}, - } - }) - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") - { - 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, - 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, - 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, - } - }) - Name (_PRS, ResourceTemplate (){ - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, - 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, - 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl deleted file mode 100644 index 044da507ae674742a58c132942d91c4800f6bb8a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ /dev/null @@ -1,291 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - // Mbi-gen pcie subsys - Device(MBI0) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} //OHCI: 640, EHCI 641 - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 2} - } - }) - } - - // Mbi-gen sas1 intc - Device(MBI1) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI2) { // Mbi-gen sas2 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, - } - - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI3) { // Mbi-gen dsa0 srv intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - -Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } -}) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 409} - } - }) - } -/* - Device(MBI4) { // Mbi-gen dsa1 dbg0 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI5) { // Mbi-gen dsa2 dbg1 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } -*/ - Device(MBI6) { // Mbi-gen dsa sas0 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ) - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, - } - }) - - - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - Device(MBI7) { // Mbi-gen roce intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name (_PRS, ResourceTemplate (){ - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, - 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, - 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, - } - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 34} - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl deleted file mode 100644 index 67e1d2b798f90d4f05ba9f3503632f67660ab6f4..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl +++ /dev/null @@ -1,274 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -//#include "ArmPlatform.h" -/* - See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 -*/ -#define PCI_OSC_SUPPORT() \ - Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ - Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ - Method(_OSC,4) { \ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ - /* Create DWord-adressable fields from the Capabilities Buffer */ \ - CreateDWordField(Arg3,0,CDW1) \ - CreateDWordField(Arg3,4,CDW2) \ - CreateDWordField(Arg3,8,CDW3) \ - /* Save Capabilities DWord2 & 3 */ \ - Store(CDW2,SUPP) \ - Store(CDW3,CTRL) \ - /* Only allow native hot plug control if OS supports: */ \ - /* ASPM */ \ - /* Clock PM */ \ - /* MSI/MSI-X */ \ - If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ - And(CTRL,0x1E,CTRL) \ - }\ - \ - /* Do not allow native PME, AER */ \ - /* Never allow SHPC (no SHPC controller in this system)*/ \ - And(CTRL,0x10,CTRL) \ - If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ - Or(CDW1,0x08,CDW1) \ - } \ - \ - If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ - Or(CDW1,0x10,CDW1) \ - } \ - \ - /* Update DWORD3 in the buffer */ \ - Store(CTRL,CDW3) \ - Return(Arg3) \ - } Else { \ - Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ - Return(Arg3) \ - } \ - } // End _OSC - -Scope(_SB) -{ - // PCIe Root bus - Device (PCI0) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x1f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb2000000, // Min Base Address pci address - 0xb7feffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xb7ff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - PCI_OSC_SUPPORT() - - Device (RES0) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) - }) - } - - } // Device(PCI0) - - Device (RES0) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x0) // Unique ID - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) - }) - } - - // PCIe Root bus - Device (PCI1) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 1) // Segment of this Root complex - Name(_BBN, 0xe0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0xe0, // AddressMinimum - Minimum Bus Number - 0xff, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb8000000, // Min Base Address pci address - 0xbdfeffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xbdff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - PCI_OSC_SUPPORT() - - Device (RES1) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x1) // Unique ID - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) - }) - } - - - } // Device(PCI1) - - Device (RES1) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) - }) - } - - // PCIe Root bus - Device (PCI2) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x9f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xaa000000, // Min Base Address - 0xaffeffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xafff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - PCI_OSC_SUPPORT() - - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) - }) - } - - } // Device(PCI2) - - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x2) // Unique ID - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) - }) - } - - Device (RESP) //reserve for ecam resource - { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f] - Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff] - Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f] - }) - } -} - diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl deleted file mode 100644 index b106a23a71e3ec8190533845785f7027ab6fbf14..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ /dev/null @@ -1,361 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - Device(SAS0) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" ) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {\_SB.MBI6}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x338), - CLK, 32, - CLKD, 32, - Offset (0xa60), - RST, 32, - DRST, 32, - Offset (0x5a30), - STS, 32, - } - - OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000) - Field (PHYS, DWordAcc, NoLock, Preserve) { - Offset (0x0014), - PHY0, 32, - Offset (0x0414), - PHY1, 32, - Offset (0x0814), - PHY2, 32, - Offset (0x0c14), - PHY3, 32, - Offset (0x1014), - PHY4, 32, - Offset (0x1414), - PHY5, 32, - Offset (0x1814), - PHY6, 32, - Offset (0x1c14), - PHY7, 32, - } - - OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) - Field (SYSR, DWordAcc, NoLock, Preserve) { - Offset (0xe014), - DIE4, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - Store(DIE4, local0) - If (LEqual (local0, 0)) { - /* 66MHZ */ - Store(0x0199B694, Local1) - Store(Local1, PHY0) - Store(Local1, PHY1) - Store(Local1, PHY2) - Store(Local1, PHY3) - Store(Local1, PHY4) - Store(Local1, PHY5) - Store(Local1, PHY6) - Store(Local1, PHY7) - } - } - } - - Device(SAS1) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {\_SB.MBI1}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - Package () {"hip06-sas-v2-quirk-amt", 1}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x318), - CLK, 32, - CLKD, 32, - Offset (0xa18), - RST, 32, - DRST, 32, - Offset (0x5a0c), - STS, 32, - } - - OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000) - Field (PHYS, DWordAcc, NoLock, Preserve) { - Offset (0x0014), - PHY0, 32, - Offset (0x0414), - PHY1, 32, - Offset (0x0814), - PHY2, 32, - Offset (0x0c14), - PHY3, 32, - Offset (0x1014), - PHY4, 32, - Offset (0x1414), - PHY5, 32, - Offset (0x1814), - PHY6, 32, - Offset (0x1c14), - PHY7, 32, - } - - OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) - Field (SYSR, DWordAcc, NoLock, Preserve) { - Offset (0xe014), - DIE4, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - Store(DIE4, local0) - If (LEqual (local0, 0)) { - /* 66MHZ */ - Store(0x0199B694, Local1) - Store(Local1, PHY0) - Store(Local1, PHY1) - Store(Local1, PHY2) - Store(Local1, PHY3) - Store(Local1, PHY4) - Store(Local1, PHY5) - Store(Local1, PHY6) - Store(Local1, PHY7) - } - } - } - - Device(SAS2) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {\_SB.MBI2}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 9}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x3a8), - CLK, 32, - CLKD, 32, - Offset (0xae0), - RST, 32, - DRST, 32, - Offset (0x5a70), - STS, 32, - } - - OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400) - Field (PHYS, DWordAcc, NoLock, Preserve) { - Offset (0x0014), - PHY0, 32, - Offset (0x0414), - PHY1, 32, - Offset (0x0814), - PHY2, 32, - Offset (0x0c14), - PHY3, 32, - Offset (0x1014), - PHY4, 32, - Offset (0x1414), - PHY5, 32, - Offset (0x1814), - PHY6, 32, - Offset (0x1c14), - PHY7, 32, - offset (0x2014), - PHY8, 32, - } - - OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) - Field (SYSR, DWordAcc, NoLock, Preserve) { - Offset (0xe014), - DIE4, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - Store(DIE4, local0) - If (LEqual (local0, 0)) { - /* 66MHZ */ - Store(0x0199B694, Local1) - Store(Local1, PHY0) - Store(Local1, PHY1) - Store(Local1, PHY2) - Store(Local1, PHY3) - Store(Local1, PHY4) - Store(Local1, PHY5) - Store(Local1, PHY6) - Store(Local1, PHY7) - Store(Local1, PHY8) - } - } - } - -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl deleted file mode 100644 index b890308657ca686dcf75568f2e8d261dd89cdf87..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ /dev/null @@ -1,130 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - Device (USB0) - { - Name (_HID, "PNP0D20") // _HID: Hardware ID - Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID - Name (_CCA, One) // _CCA: Cache Coherency Attribute - Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings - { - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, - 0xa7020000, // Address Base - 0x00010000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") - { - 641, //EHCI - } - }) - Return (RBUF) /* \_SB_.USB0._CRS.RBUF */ - } - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"interrupt-parent",Package() {\_SB.MBI0}} - } - }) - - Device (RHUB) - { - Name (_ADR, Zero) // _ADR: Address - Device (PRT1) - { - Name (_ADR, One) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - Zero, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0, - PLD_VerticalOffset = 0x0, - PLD_HorizontalOffset = 0x0) - - }) - } - - Device (PRT2) - { - Name (_ADR, 0x02) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT3) - { - Name (_ADR, 0x03) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT4) - { - Name (_ADR, 0x04) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - } - } -} - diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl deleted file mode 100644 index 40669052d04939721878bfa1fe34504fe33cd1ae..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl +++ /dev/null @@ -1,23 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -#include "Hi1610Platform.h" - -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_OEM_REVISION) { - include ("Lpc.asl") - include ("D03Mbig.asl") - include ("CPU.asl") - include ("D03Usb.asl") - include ("D03Hns.asl") - include ("D03Sas.asl") - include ("D03Pci.asl") -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl deleted file mode 100644 index 2ed1cb97a290087296a704094198f9e3db578712..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* -* Copyright (c) 2016 Hisilicon Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -// -// LPC -// - -Scope(_SB) { - Device (LPC0) { - Name (_HID, "HISI0191") // HiSi LPC - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) - }) - } - - Device (LPC0.IPMI) { - Name (_HID, "IPI0001") - Method (_IFT) { - Return (0x03) - } - Name (LORS, ResourceTemplate() { - QWordIO ( - ResourceConsumer, - MinNotFixed, // _MIF - MaxNotFixed, // _MAF - PosDecode, - EntireRange, - 0x0, // _GRA - 0xe4, // _MIN - 0x3fff, // _MAX - 0x0, // _TRA - 0x04, // _LEN - , , - BTIO - ) - }) - CreateQWordField (LORS, BTIO._MIN, CMIN) - CreateQWordField (LORS, BTIO._MAX, CMAX) - CreateQWordField (LORS, BTIO._LEN, CLEN) - - Method (_PRS, 0) { - Return (LORS) - } - - Method (_CRS, 0) { - Return (LORS) - } - Method (_SRS, 1) { - CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MIN, IMIN) - Store (IMIN, CMIN) - CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MAX, IMAX) - Store (IMAX, CMAX) - } - } - - Device (LPC0.CON0) { - Name (_HID, "HISI1031") - Name (_CID, "PNP0501") - Name (LORS, ResourceTemplate() { - QWordIO ( - ResourceConsumer, - MinNotFixed, // _MIF - MaxNotFixed, // _MAF - PosDecode, - EntireRange, - 0x0, // _GRA - 0x2F8, // _MIN - 0x3fff, // _MAX - 0x0, // _TRA - 0x08, // _LEN - , , - IO02 - ) - }) - CreateQWordField (LORS, IO02._MIN, CMIN) - CreateQWordField (LORS, IO02._MAX, CMAX) - CreateQWordField (LORS, IO02._LEN, CLEN) - - Method (_PRS, 0) { - Return (LORS) - } - - Method (_CRS, 0) { - Return (LORS) - } - Method (_SRS, 1) { - CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MIN, IMIN) - Store (IMIN, CMIN) - CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MAX, IMAX) - Store (IMAX, CMAX) - } - } -} diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc deleted file mode 100644 index 049364e6367c691f1c4f4509a37ae3cbea527644..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc +++ /dev/null @@ -1,61 +0,0 @@ -/** @file -* Firmware ACPI Control Structure (FACS) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include - -EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length - 0xA152, // UINT32 HardwareSignature - 0, // UINT32 FirmwareWakingVector - 0, // UINT32 GlobalLock - 0, // UINT32 Flags - 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; - { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] - EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] - 0, // UINT32 OspmFlags "Platform firmware must - // initialize this field to zero." - { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] - EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Facs; - diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc deleted file mode 100644 index 75714990cf8e1ffac0c8b97f64e362ee8d8be9e9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc +++ /dev/null @@ -1,86 +0,0 @@ -/** @file -* Fixed ACPI Description Table (FADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1610Platform.h" - -#include -#include - -EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { - ARM_ACPI_HEADER ( - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION - ), - 0, // UINT32 FirmwareCtrl - 0, // UINT32 Dsdt - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile - 0, // UINT16 SciInt - 0, // UINT32 SmiCmd - 0, // UINT8 AcpiEnable - 0, // UINT8 AcpiDisable - 0, // UINT8 S4BiosReq - 0, // UINT8 PstateCnt - 0, // UINT32 Pm1aEvtBlk - 0, // UINT32 Pm1bEvtBlk - 0, // UINT32 Pm1aCntBlk - 0, // UINT32 Pm1bCntBlk - 0, // UINT32 Pm2CntBlk - 0, // UINT32 PmTmrBlk - 0, // UINT32 Gpe0Blk - 0, // UINT32 Gpe1Blk - 0, // UINT8 Pm1EvtLen - 0, // UINT8 Pm1CntLen - 0, // UINT8 Pm2CntLen - 0, // UINT8 PmTmrLen - 0, // UINT8 Gpe0BlkLen - 0, // UINT8 Gpe1BlkLen - 0, // UINT8 Gpe1Base - 0, // UINT8 CstCnt - 0, // UINT16 PLvl2Lat - 0, // UINT16 PLvl3Lat - 0, // UINT16 FlushSize - 0, // UINT16 FlushStride - 0, // UINT8 DutyOffset - 0, // UINT8 DutyWidth - 0, // UINT8 DayAlrm - 0, // UINT8 MonAlrm - 0, // UINT8 Century - 0, // UINT16 IaPcBootArch - 0, // UINT8 Reserved1 - EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg - 0, // UINT8 ResetValue - EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision - 0, // UINT64 XFirmwareCtrl - 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg - 0 // UINT64 Hypervisor Vendor Identify -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc deleted file mode 100644 index 958d7c94e4600fc345b1ad43437181ea2bcd5a00..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc +++ /dev/null @@ -1,91 +0,0 @@ -/** @file -* Generic Timer Description Table (GTDT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1610Platform.h" - -#include -#include -#include - -#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT -#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE -#define GTDT_GLOBAL_FLAGS_LEVEL 0 - -// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer -#ifdef SYSTEM_TIMER_BASE_ADDRESS - #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) -#else - #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) - #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF -#endif - -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE -#define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY -#define GTDT_TIMER_ACTIVE_HIGH 0 -#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY - -#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ALWAYS_ON_CAPABILITY | GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) - -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; -} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; - -#pragma pack () - -EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { - { - ARM_ACPI_HEADER( - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION - ), - SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress - 0, // UINT32 Reserved - FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags - FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags - FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags - FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress -#ifdef notyet - PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset - }, - { - EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), - 0, 0, 0, 0), - EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) - 0, 0, 0, 0) - } -#else /* !notyet */ - 0, 0 - } -#endif - }; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Gtdt; - diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h deleted file mode 100644 index 1aed66daf923a1dc1a348dbb7a222b45a5e7bc89..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h +++ /dev/null @@ -1,21 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015-2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - - -#ifndef _HI1610_PLATFORM_H_ -#define _HI1610_PLATFORM_H_ - -#include - -#define HI1610_WATCHDOG_COUNT 2 - -#endif diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc deleted file mode 100644 index ee06c1516bc21632f9f1a046ac8a6e177c833e6e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc +++ /dev/null @@ -1,122 +0,0 @@ -/** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1610Platform.h" - -#include -#include -#include -#include -#include - -// Differs from Juno, we have another affinity level beyond cluster and core -// 0x20000 is only for socket 0 -#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) - -// -// Multiple APIC Description Table -// -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1]; -} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; - -#pragma pack () - -EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION - ), - // - // MADT specific fields - // - 0, // LocalApicAddress - 0, // Flags - }, - { - // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, - // GsivId, GicRBase, Mpidr) - // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v5.1). - // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses - // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0), - }, - - EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), - { - EFI_ACPI_6_1_GIC_ITS_INIT(0,0xC6000000), - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc deleted file mode 100644 index ec92dc9d328b66901642845aac9b318a6763766a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Contributors: - * Yi Li - yi.li@linaro.org -*/ - -#include -#include "Hi1610Platform.h" - -#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014 - -#pragma pack(1) -typedef struct { - UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; - -typedef struct { - EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; - EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; - -} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE; -#pragma pack() - -// -// System Locality Information Table -// Please modify all values in Slit.h only. -// -EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { - { - { - EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE), - EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION, - }, - // - // Beginning of SLIT specific fields - // - EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, - }, - { - {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0 - {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1 - {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2 - {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3 - {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4 - {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5 - {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6 - {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7 - {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8 - {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9 - {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10 - {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11 - {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12 - {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13 - {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14 - {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15 - {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16 - {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17 - {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18 - {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19 - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Slit; - diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc deleted file mode 100644 index ee0b11db6562f7427e5a0f72404529a1ebe200b3..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Contributors: - * Yi Li - yi.li@linaro.org - * - * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -*/ - -#include -#include "Hi1610Platform.h" -#include -#include - - -// -// Define the number of each table type. -// This is where the table layout is modified. -// -#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4 -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4 - - -#pragma pack(1) -typedef struct { - EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; - EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic; - EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2]; - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16]; -} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE; - -#pragma pack() - - -// -// Static Resource Affinity Table definition -// -EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = { - { - {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE), - EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION}, - /*Reserved*/ - 0x00000001, // Reserved to be 1 for backward compatibility - EFI_ACPI_RESERVED_QWORD - }, - /**/ - { - 0x00, // Subtable Type:Processor Local APIC/SAPIC Affinity - sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length - 0x00, //Proximity Domain Low(8) - 0x00, //Apic ID - 0x00000001, //Flags - 0x00, //Local Sapic EID - {0,0,0}, //Proximity Domain High(24) - 0x00000000, //ClockDomain - }, - // - // - // Memory Affinity - // - { - EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001), - EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001), - }, - - /*Processor Local x2APIC Affinity*/ - //{ - // 0x02, // Subtable Type:Processor Local x2APIC Affinity - // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE), - // {0,0}, //Reserved1 - // 0x00000000, //Proximity Domain - // 0x00000000, //Apic ID - // 0x00000001, //Flags - // 0x00000000, //Clock Domain - // {0,0,0,0}, //Reserved2 - //}, - - { - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15 - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Srat; - diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h deleted file mode 100644 index 9112c67af037333a1b49b5e116c1600fdaf67108..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h +++ /dev/null @@ -1,65 +0,0 @@ -/** @file -* -* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#ifndef _PLATFORM_ARCH_H_ -#define _PLATFORM_ARCH_H_ - -#define MAX_SOCKET 2 -#define MAX_DIE 4 -#define MAX_DDRC 2 -#define MAX_NODE (MAX_SOCKET * MAX_DIE) -#define MAX_CHANNEL 4 -#define MAX_DIMM 3 -#define MAX_RANK_CH 12 -#define MAX_RANK_DIMM 4 -#define MAX_DIMM_SIZE 32 // In GB -// Max NUMA node number for each node type -#define MAX_NUM_PER_TYPE 8 - -// for acpi -#define NODE_IN_SOCKET 2 -#define CORE_NUM_PER_SOCKET 32 -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10 -#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8 - -#define S1_BASE 0x40000000000 - -#define RASC_BASE (0x5000) -/* configuration register for Rank statistical information */ -#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) -/* configuration register for Sparing level */ -#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) - -// -// ACPI table information used to initialize tables. -// -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64 ('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long -#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 -#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32 ('I','N','T','L') -#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 - -// A macro to initialise the common header part of EFI ACPI tables as defined by -// EFI_ACPI_DESCRIPTION_HEADER structure. -#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ - Signature, /* UINT32 Signature */ \ - sizeof (Type), /* UINT32 Length */ \ - Revision, /* UINT8 Revision */ \ - 0, /* UINT8 Checksum */ \ - { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ - EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ - EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ - EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ - EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ - } - -#endif - diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c deleted file mode 100644 index ca305b1cb2a04965cf2c07915351734bdaeec7de..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c +++ /dev/null @@ -1,378 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define INVALID_CAPABILITY_00 0x00 -#define INVALID_CAPABILITY_FF 0xFF -#define PCI_CAPABILITY_POINTER_MASK 0xFC - -STATIC -UINT64 -GetPcieCfgAddress ( - UINT64 Ecam, - UINTN Bus, - UINTN Device, - UINTN Function, - UINTN Reg - ) -{ - return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg); -} - -STATIC -PCI_ROOT_BRIDGE_RESOURCE_APPETURE * -GetAppetureByRootBridgeIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridge - ) -{ - EFI_STATUS Status; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration = NULL; - UINTN Hb; - UINTN Rb; - - Status = RootBridge->Configuration ( - RootBridge, - (VOID **)&Configuration - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a:%d] RootBridgeIo->Configuration failed %r\n", - __func__, __LINE__, Status)); - return NULL; - }; - - while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { - if (Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) { - break; - } - Configuration++; - } - - if (Configuration->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) { - DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find bus descriptor\n", __func__, __LINE__)); - return NULL; - } - - for (Hb = 0; Hb < PCIE_MAX_HOSTBRIDGE; Hb++) { - for (Rb = 0; Rb < PCIE_MAX_ROOTBRIDGE; Rb++) { - if (RootBridge->SegmentNumber == mResAppeture[Hb][Rb].Segment && - Configuration->AddrRangeMin >= mResAppeture[Hb][Rb].BusBase && - Configuration->AddrRangeMax <= mResAppeture[Hb][Rb].BusLimit) { - return &mResAppeture[Hb][Rb]; - } - } - } - - DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find PCI appeture\n", __func__, __LINE__)); - return NULL; -} - -STATIC -VOID -SetAtuConfig0RW ( - PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private, - UINT32 Index - ) -{ - UINTN RbPciBase = Private->RbPciBar; - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; - UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); - - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); - - { - UINTN i; - for (i=0; i<0x20; i+=4) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __func__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -STATIC -VOID -SetAtuConfig1RW ( - PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private, - UINT32 Index - ) -{ - UINTN RbPciBase = Private->RbPciBar; - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; - UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); - - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); - - { - UINTN i; - for (i=0; i<0x20; i+=4) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __func__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -STATIC -VOID -SetAtuIoRW (UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index) -{ - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32)); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE); - - { - UINTN i; - for (i=0; i<0x20; i+=4) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __func__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -STATIC -VOID -SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index) -{ - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32)); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE); - - { - UINTN i; - for (i=0; i<0x20; i+=4) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __func__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -VOID -InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private) -{ - SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0); - SetAtuConfig0RW (Private, 1); - SetAtuConfig1RW (Private, 2); - SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); -} - -/*++ - -Routine Description: - - Perform Platform initialization first in PciPlatform. - -Arguments: - -Returns: - - VOID. - ---*/ -VOID -EFIAPI -PciInitPlatform ( - VOID - ) -{ - UINT32 Port; - UINT32 HostBridgeNum = 0; - - for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) { - for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) { - InitAtu (&mResAppeture[HostBridgeNum][Port]); - } - } - - return; -} - -STATIC -BOOLEAN -PcieCheckAriFwdEn ( - UINTN PciBaseAddr - ) -{ - UINT8 PciPrimaryStatus; - UINT8 CapabilityOffset; - UINT8 CapId; - UINT8 TempData; - - PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); - - if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { - CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); - CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; - - while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) { - CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); - if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { - break; - } - CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); - CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; - } - } else { - return FALSE; - } - - if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) { - return FALSE; - } - - TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + - EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); - TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; - - if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { - return TRUE; - } else { - return FALSE; - } -} - -VOID -EnlargeAtuConfig0 ( - IN EFI_HANDLE HostBridge - ) -{ - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc = NULL; - EFI_STATUS Status; - EFI_HANDLE RootBridgeHandle = NULL; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo = NULL; - PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture; - UINTN RbPciBase; - UINT64 MemLimit; - - DEBUG ((DEBUG_INFO, "In Enlarge RP iATU Config 0.\n")); - - Status = gBS->HandleProtocol ( - HostBridge, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, - (VOID **)&ResAlloc - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __func__, - __LINE__, Status)); - return; - } - - while (TRUE) { - Status = ResAlloc->GetNextRootBridge ( - ResAlloc, - &RootBridgeHandle - ); - if (EFI_ERROR (Status)) { - break; - } - Status = gBS->HandleProtocol ( - RootBridgeHandle, - &gEfiPciRootBridgeIoProtocolGuid, - (VOID **)&RootBridgeIo - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __func__, __LINE__, Status)); - // This should never happen so that it is a fatal error and we don't try - // to continue - break; - } - - Appeture = GetAppetureByRootBridgeIo (RootBridgeIo); - if (Appeture == NULL) { - DEBUG ((DEBUG_ERROR, "[%a:%d] Get appeture failed\n", __func__, - __LINE__)); - continue; - } - - RbPciBase = Appeture->RbPciBar; - // Those ARI FWD Enable Root Bridge, need enlarge iATU window. - if (PcieCheckAriFwdEn (RbPciBase)) { - MemLimit = GetPcieCfgAddress (Appeture->Ecam, Appeture->BusBase + 2, 0, 0, 0) - 1; - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); - } - } -} - -/*++ - -Routine Description: - - Perform Platform initialization by the phase indicated. - -Arguments: - - HostBridge - The associated PCI host bridge handle. - Phase - The phase of the PCI controller enumeration. - ChipsetPhase - Defines the execution phase of the PCI chipset driver. - -Returns: - ---*/ -VOID -EFIAPI -PhaseNotifyPlatform ( - IN EFI_HANDLE HostBridge, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, - IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase - ) -{ - switch (Phase) { - case EfiPciHostBridgeEndEnumeration: - // Only do once - if (ChipsetPhase == ChipsetEntry) { - DEBUG ((DEBUG_INFO, "PCI end enumeration platform hook\n")); - EnlargeAtuConfig0 (HostBridge); - } - break; - default: - break; - } - - return ; -} - diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf deleted file mode 100644 index d4fa50d19d6fedef86c4091419dff588dcbe0d0b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf +++ /dev/null @@ -1,37 +0,0 @@ -## @file -# PCI Segment Library for Hisilicon Hi1610/Hi1616 SoC with multiple RCs -# -# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
-# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
-# Copyright (c) 2018, Hisilicon Ltd. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = Hi161xPciPlatformLib - FILE_GUID = 22447df4-0baa-11e8-b6de-286ed489ee9b - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciPlatformLib - -[Sources] - Hi161xPciPlatformLib.c - -[Packages] - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - DebugLib - IoLib - PlatformPciLib - -[Protocols] - gEfiPciHostBridgeResourceAllocationProtocolGuid - gEfiPciIoProtocolGuid - gEfiPciRootBridgeIoProtocolGuid diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf deleted file mode 100644 index 72e32b14dc94886eb2d16dad1ac2d30155bf2b92..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf +++ /dev/null @@ -1,31 +0,0 @@ -## @file -# PCI Segment Library for Hisilicon Hi1610/Hi1616 SoC with multiple RCs -# -# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
-# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
-# Copyright (c) 2018, Hisilicon Ltd. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = Hi161xPciSegmentLib - FILE_GUID = 22447df4-0baa-11e8-b6de-286ed489ee9b - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciSegmentLib - -[Sources] - PciSegmentLib.c - -[Packages] - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - DebugLib - IoLib diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c deleted file mode 100644 index d756b6919369c27a4f7a2c6a7134343e06b64ce7..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c +++ /dev/null @@ -1,1496 +0,0 @@ -/** @file - PCI Segment Library for SynQuacer SoC with multiple RCs - - Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
- Copyright (c) 2017, Linaro, Ltd. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -#include -#include -#include -#include -#include - -typedef enum { - PciCfgWidthUint8 = 0, - PciCfgWidthUint16, - PciCfgWidthUint32, - PciCfgWidthMax -} PCI_CFG_WIDTH; - -/** - Assert the validity of a PCI Segment address. - A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63 - - @param A The address to validate. - @param M Additional bits to assert to be zero. - -**/ -#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ - ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) - -#define EXTRACT_PCIE_ADDRESS(Address, Segment, Bus, Device, Function, Register) \ -{ \ - (Segment) = (RShiftU64 (Address, 32) & 0xffff); \ - (Bus) = (((Address) >> 20) & 0xff); \ - (Device) = (((Address) >> 15) & 0x1f); \ - (Function) = (((Address) >> 12) & 0x07); \ - (Register) = ((Address) & 0xfff); \ -} - -STATIC -PCI_ROOT_BRIDGE_RESOURCE_APPETURE * -PciSegmentLibGetAppeture ( - IN UINT32 Segment - ) -{ - UINTN Hb; - UINTN Rb; - - for (Hb = 0; Hb < PCIE_MAX_HOSTBRIDGE; Hb++) { - for (Rb = 0; Rb < PCIE_MAX_ROOTBRIDGE; Rb++) { - if (Segment == mResAppeture[Hb][Rb].Segment) { - return &mResAppeture[Hb][Rb]; - } - } - } - - // Shouldn't reach here - ASSERT (FALSE); - return NULL; -} - -BOOLEAN PcieIsLinkUp (UINTN RbPciBar) -{ - UINT32 Value; - - Value = MmioRead32(RbPciBar + 0x131C); - if ((Value & 0x3F) == 0x11) { - return TRUE; - } - return FALSE; -} - - -STATIC -UINT32 -CpuMemoryServiceRead ( - IN UINT64 Address, - IN PCI_CFG_WIDTH Width - ) -{ - - UINT32 Uint32Buffer; - - // - // Select loop based on the width of the transfer - // - if (Width == PciCfgWidthUint8) { - Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3))); - return BitFieldRead32 (Uint32Buffer, (Address & 0x3) * 8, (Address & 0x3) * 8 + 7); - } else if (Width == PciCfgWidthUint16) { - if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) { - return 0xffff; - } - Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3))); - return BitFieldRead32 (Uint32Buffer, (Address & 0x3) * 8, (Address & 0x3) * 8 + 15); - } else if (Width == PciCfgWidthUint32) { - return MmioRead32 ((UINTN)Address); - } else { - return 0xffffffff; - } -} - -STATIC -UINT32 -CpuMemoryServiceWrite ( - IN UINT64 Address, - IN PCI_CFG_WIDTH Width, - IN UINT32 Data - ) -{ - - UINT32 Uint32Buffer; - - // - // Select loop based on the width of the transfer - // - if (Width == PciCfgWidthUint8) { - Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3))); - Uint32Buffer = BitFieldWrite32 (Uint32Buffer, (Address & 0x3) * 8, (Address & 0x3) * 8 + 7, Data); - MmioWrite32 ((UINTN)(Address & (~0x3)), Uint32Buffer); - } else if (Width == PciCfgWidthUint16) { - if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) { - return 0xffffffff; - } - Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3))); - Uint32Buffer = BitFieldWrite32 (Uint32Buffer, (Address & 0x3) * 8, (Address & 0x3) * 8 + 15, Data); - MmioWrite32 ((UINTN)(Address & (~0x3)), Uint32Buffer); - } else if (Width == PciCfgWidthUint32) { - MmioWrite32 ((UINTN)Address, Data); - } else { - return 0xffffffff; - } - return Data; -} -/** - Internal worker function to read a PCI configuration register. - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param Width The width of data to read - - @return The value read from the PCI configuration register. - -**/ -STATIC -UINT32 -PciSegmentLibReadWorker ( - IN UINT64 Address, - IN PCI_CFG_WIDTH Width - ) -{ - PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture; - UINT32 Segment; - UINT8 Bus; - UINT8 Device; - UINT8 Function; - UINT32 Register; - - UINT64 MmioAddress; - - EXTRACT_PCIE_ADDRESS (Address, Segment, Bus, Device, Function, Register); - Appeture = PciSegmentLibGetAppeture (Segment); - if (Appeture == NULL) { - return 0xffffffff; - } - - if (Bus == Appeture->BusBase) { - // ignore device > 0 or function > 0 on base bus - if (Device != 0 || Function != 0) { - return 0xffffffff; - } - MmioAddress = Appeture->RbPciBar + Register; - } else { - // Cannot read from device under root port when link is not up - if (Bus == Appeture->BusBase + 1 && !PcieIsLinkUp (Appeture->RbPciBar)) { - return 0xffffffff; - } - - MmioAddress = Appeture->Ecam + (UINT32)Address; - } - - return CpuMemoryServiceRead (MmioAddress, Width); -} - -/** - Internal worker function to writes a PCI configuration register. - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param Width The width of data to write - @param Data The value to write. - - @return The value written to the PCI configuration register. - -**/ -STATIC -UINT32 -PciSegmentLibWriteWorker ( - IN UINT64 Address, - IN PCI_CFG_WIDTH Width, - IN UINT32 Data - ) -{ - PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture; - UINT32 Segment; - UINT8 Bus; - UINT8 Device; - UINT8 Function; - UINT32 Register; - - UINT64 MmioAddress; - - EXTRACT_PCIE_ADDRESS (Address, Segment, Bus, Device, Function, Register); - Appeture = PciSegmentLibGetAppeture (Segment); - if (Appeture == NULL) { - return 0xffffffff; - } - - if (Bus == Appeture->BusBase) { - // ignore device > 0 or function > 0 on base bus - if (Device != 0 || Function != 0) { - return Data; - } - // Ignore writing to root port BAR registers, in case we get wrong BAR length - if ((Register & ~0x3) == 0x14 || (Register & ~0x3) == 0x10) { - return Data; - } - MmioAddress = Appeture->RbPciBar + Register; - } else { - // Cannot read from device under root port when link is not up - if (Bus == Appeture->BusBase + 1 && !PcieIsLinkUp (Appeture->RbPciBar)) { - return 0xffffffff; - } - MmioAddress = Appeture->Ecam + (UINT32)Address; - } - - return CpuMemoryServiceWrite (MmioAddress, Width, Data); -} - -/** - Register a PCI device so PCI configuration registers may be accessed after - SetVirtualAddressMap(). - - If any reserved bits in Address are set, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @retval RETURN_SUCCESS The PCI device was registered for runtime access. - @retval RETURN_UNSUPPORTED An attempt was made to call this function - after ExitBootServices(). - @retval RETURN_UNSUPPORTED The resources required to access the PCI device - at runtime could not be mapped. - @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to - complete the registration. - -**/ -RETURN_STATUS -EFIAPI -PciSegmentRegisterForRuntimeAccess ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); - return RETURN_UNSUPPORTED; -} - -/** - Reads an 8-bit PCI configuration register. - - Reads and returns the 8-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, - and Register. - - @return The 8-bit PCI configuration register specified by Address. - -**/ -UINT8 -EFIAPI -PciSegmentRead8 ( - IN UINT64 Address - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); - - return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); -} - -/** - Writes an 8-bit PCI configuration register. - - Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. - Value is returned. This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentWrite8 ( - IN UINT64 Address, - IN UINT8 Value - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); - - return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value); -} - -/** - Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, - performs a bitwise OR between the read result and the value specified by OrData, - and writes the result to the 8-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentOr8 ( - IN UINT64 Address, - IN UINT8 OrData - ) -{ - return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData)); -} - -/** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, - performs a bitwise AND between the read result and the value specified by AndData, - and writes the result to the 8-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - If any reserved bits in Address are set, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentAnd8 ( - IN UINT64 Address, - IN UINT8 AndData - ) -{ - return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData)); -} - -/** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, - followed a bitwise OR with another 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, - performs a bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and the value specified by OrData, - and writes the result to the 8-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentAndThenOr8 ( - IN UINT64 Address, - IN UINT8 AndData, - IN UINT8 OrData - ) -{ - return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData)); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in an 8-bit PCI configuration register. The bit field is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - - @return The value of the bit field read from the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentBitFieldRead8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of the - 8-bit register is returned. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentBitFieldWrite8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 Value - ) -{ - return PciSegmentWrite8 ( - Address, - BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value) - ); -} - -/** - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 8-bit port. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentBitFieldOr8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 OrData - ) -{ - return PciSegmentWrite8 ( - Address, - BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData) - ); -} - -/** - Reads a bit field in an 8-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 8-bit register. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentBitFieldAnd8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData - ) -{ - return PciSegmentWrite8 ( - Address, - BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData) - ); -} - -/** - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 8-bit port. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in both AndData and - OrData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciSegmentBitFieldAndThenOr8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData, - IN UINT8 OrData - ) -{ - return PciSegmentWrite8 ( - Address, - BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData) - ); -} - -/** - Reads a 16-bit PCI configuration register. - - Reads and returns the 16-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - - @return The 16-bit PCI configuration register specified by Address. - -**/ -UINT16 -EFIAPI -PciSegmentRead16 ( - IN UINT64 Address - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); - - return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); -} - -/** - Writes a 16-bit PCI configuration register. - - Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. - Value is returned. This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param Value The value to write. - - @return The parameter of Value. - -**/ -UINT16 -EFIAPI -PciSegmentWrite16 ( - IN UINT64 Address, - IN UINT16 Value - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); - - return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value); -} - -/** - Performs a bitwise OR of a 16-bit PCI configuration register with - a 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentOr16 ( - IN UINT64 Address, - IN UINT16 OrData - ) -{ - return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData)); -} - -/** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, - performs a bitwise AND between the read result and the value specified by AndData, - and writes the result to the 16-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentAnd16 ( - IN UINT64 Address, - IN UINT16 AndData - ) -{ - return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData)); -} - -/** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, - followed a bitwise OR with another 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, - performs a bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and the value specified by OrData, - and writes the result to the 16-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentAndThenOr16 ( - IN UINT64 Address, - IN UINT16 AndData, - IN UINT16 OrData - ) -{ - return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData)); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in a 16-bit PCI configuration register. The bit field is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - - @return The value of the bit field read from the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentBitFieldRead16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of the - 16-bit register is returned. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentBitFieldWrite16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 Value - ) -{ - return PciSegmentWrite16 ( - Address, - BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value) - ); -} - -/** - Reads the 16-bit PCI configuration register specified by Address, - performs a bitwise OR between the read result and the value specified by OrData, - and writes the result to the 16-bit PCI configuration register specified by Address. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentBitFieldOr16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 OrData - ) -{ - return PciSegmentWrite16 ( - Address, - BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData) - ); -} - -/** - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, - and writes the result back to the bit field in the 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, - performs a bitwise OR between the read result and the value specified by OrData, - and writes the result to the 16-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - Extra left bits in OrData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param StartBit The ordinal of the least significant bit in the bit field. - The ordinal of the least significant bit in a byte is bit 0. - @param EndBit The ordinal of the most significant bit in the bit field. - The ordinal of the most significant bit in a byte is bit 7. - @param AndData The value to AND with the read value from the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentBitFieldAnd16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData - ) -{ - return PciSegmentWrite16 ( - Address, - BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData) - ); -} - -/** - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in both AndData and - OrData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciSegmentBitFieldAndThenOr16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData, - IN UINT16 OrData - ) -{ - return PciSegmentWrite16 ( - Address, - BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData) - ); -} - -/** - Reads a 32-bit PCI configuration register. - - Reads and returns the 32-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, - and Register. - - @return The 32-bit PCI configuration register specified by Address. - -**/ -UINT32 -EFIAPI -PciSegmentRead32 ( - IN UINT64 Address - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); - - return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); -} - -/** - Writes a 32-bit PCI configuration register. - - Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. - Value is returned. This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, - Function, and Register. - @param Value The value to write. - - @return The parameter of Value. - -**/ -UINT32 -EFIAPI -PciSegmentWrite32 ( - IN UINT64 Address, - IN UINT32 Value - ) -{ - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); - - return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); -} - -/** - Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, - performs a bitwise OR between the read result and the value specified by OrData, - and writes the result to the 32-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentOr32 ( - IN UINT64 Address, - IN UINT32 OrData - ) -{ - return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); -} - -/** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, - performs a bitwise AND between the read result and the value specified by AndData, - and writes the result to the 32-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, - and Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentAnd32 ( - IN UINT64 Address, - IN UINT32 AndData - ) -{ - return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); -} - -/** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, - followed a bitwise OR with another 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, - performs a bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and the value specified by OrData, - and writes the result to the 32-bit PCI configuration register specified by Address. - The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Segment, Bus, Device, Function, - and Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentAndThenOr32 ( - IN UINT64 Address, - IN UINT32 AndData, - IN UINT32 OrData - ) -{ - return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in a 32-bit PCI configuration register. The bit field is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - - @return The value of the bit field read from the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentBitFieldRead32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of the - 32-bit register is returned. - - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentBitFieldWrite32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 Value - ) -{ - return PciSegmentWrite32 ( - Address, - BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value) - ); -} - -/** - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 32-bit port. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentBitFieldOr32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 OrData - ) -{ - return PciSegmentWrite32 ( - Address, - BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData) - ); -} - -/** - Reads a bit field in a 32-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 32-bit register. - - - Reads the 32-bit PCI configuration register specified by Address, performs a bitwise - AND between the read result and the value specified by AndData, and writes the result - to the 32-bit PCI configuration register specified by Address. The value written to - the PCI configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in AndData are stripped. - If any reserved bits in Address are set, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentBitFieldAnd32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData - ) -{ - return PciSegmentWrite32 ( - Address, - BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData) - ); -} - -/** - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 32-bit port. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in both AndData and - OrData are stripped. - - If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciSegmentBitFieldAndThenOr32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData, - IN UINT32 OrData - ) -{ - return PciSegmentWrite32 ( - Address, - BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData) - ); -} - -/** - Reads a range of PCI configuration registers into a caller supplied buffer. - - Reads the range of PCI configuration registers specified by StartAddress and - Size into the buffer specified by Buffer. This function only allows the PCI - configuration registers from a single PCI function to be read. Size is - returned. When possible 32-bit PCI configuration read cycles are used to read - from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit - and 16-bit PCI configuration read cycles may be used at the beginning and the - end of the range. - - If any reserved bits in StartAddress are set, then ASSERT(). - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). - If Size > 0 and Buffer is NULL, then ASSERT(). - - @param StartAddress The starting address that encodes the PCI Segment, Bus, - Device, Function and Register. - @param Size The size in bytes of the transfer. - @param Buffer The pointer to a buffer receiving the data read. - - @return Size - -**/ -UINTN -EFIAPI -PciSegmentReadBuffer ( - IN UINT64 StartAddress, - IN UINTN Size, - OUT VOID *Buffer - ) -{ - UINTN ReturnValue; - - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); - - if (Size == 0) { - return Size; - } - - ASSERT (Buffer != NULL); - - // - // Save Size for return - // - ReturnValue = Size; - - if ((StartAddress & BIT0) != 0) { - // - // Read a byte if StartAddress is byte aligned - // - *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); - StartAddress += sizeof (UINT8); - Size -= sizeof (UINT8); - Buffer = (UINT8*)Buffer + 1; - } - - if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { - // - // Read a word if StartAddress is word aligned - // - WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - while (Size >= sizeof (UINT32)) { - // - // Read as many double words as possible - // - WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); - StartAddress += sizeof (UINT32); - Size -= sizeof (UINT32); - Buffer = (UINT32*)Buffer + 1; - } - - if (Size >= sizeof (UINT16)) { - // - // Read the last remaining word if exist - // - WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - if (Size >= sizeof (UINT8)) { - // - // Read the last remaining byte if exist - // - *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); - } - - return ReturnValue; -} - - -/** - Copies the data in a caller supplied buffer to a specified range of PCI - configuration space. - - Writes the range of PCI configuration registers specified by StartAddress and - Size from the buffer specified by Buffer. This function only allows the PCI - configuration registers from a single PCI function to be written. Size is - returned. When possible 32-bit PCI configuration write cycles are used to - write from StartAdress to StartAddress + Size. Due to alignment restrictions, - 8-bit and 16-bit PCI configuration write cycles may be used at the beginning - and the end of the range. - - If any reserved bits in StartAddress are set, then ASSERT(). - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). - If Size > 0 and Buffer is NULL, then ASSERT(). - - @param StartAddress The starting address that encodes the PCI Segment, Bus, - Device, Function and Register. - @param Size The size in bytes of the transfer. - @param Buffer The pointer to a buffer containing the data to write. - - @return The parameter of Size. - -**/ -UINTN -EFIAPI -PciSegmentWriteBuffer ( - IN UINT64 StartAddress, - IN UINTN Size, - IN VOID *Buffer - ) -{ - UINTN ReturnValue; - - ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); - - if (Size == 0) { - return 0; - } - - ASSERT (Buffer != NULL); - - // - // Save Size for return - // - ReturnValue = Size; - - if ((StartAddress & BIT0) != 0) { - // - // Write a byte if StartAddress is byte aligned - // - PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); - StartAddress += sizeof (UINT8); - Size -= sizeof (UINT8); - Buffer = (UINT8*)Buffer + 1; - } - - if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { - // - // Write a word if StartAddress is word aligned - // - PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - while (Size >= sizeof (UINT32)) { - // - // Write as many double words as possible - // - PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); - StartAddress += sizeof (UINT32); - Size -= sizeof (UINT32); - Buffer = (UINT32*)Buffer + 1; - } - - if (Size >= sizeof (UINT16)) { - // - // Write the last remaining word if exist - // - PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - if (Size >= sizeof (UINT8)) { - // - // Write the last remaining byte if exist - // - PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); - } - - return ReturnValue; -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf deleted file mode 100644 index a617650244096ec24bfcacccbb697b2c8d3a52af..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf +++ /dev/null @@ -1,53 +0,0 @@ -## @file -# -# ACPI table data and ASL sources required to boot the platform. -# -# Copyright (c) 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under Hisilicon/Hi1610/Hi1610AcpiTables/ -# -## - -[Defines] - INF_VERSION = 0x00010019 - BASE_NAME = Hi1616AcpiTables - FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD - MODULE_TYPE = USER_DEFINED - VERSION_STRING = 1.0 - -[Sources] - Dsdt/DsdtHi1616.asl - Facs.aslc - Fadt.aslc - Gtdt.aslc - MadtHi1616.aslc - D05Mcfg.aslc - D05Iort.asl - D05Slit.aslc - D05Srat.aslc - D05Spcr.aslc - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/Hi1616/Hi1616.dec - Silicon/Hisilicon/HisiPkg.dec - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdCoreCount - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl deleted file mode 100644 index 472e461f9f07948b4588e23a052a50e0e41d7e1f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ /dev/null @@ -1,669 +0,0 @@ -/* - * Intel ACPI Component Architecture - * iASL Compiler/Disassembler version 20151124-64 - * Copyright (c) 2015 - 2016 Intel Corporation - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Template for [IORT] ACPI Table (static data table) - * Format: [ByteLength] FieldName : HexFieldValue - */ -[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 000002e4 -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "HIP07 " -[0004] Oem Revision : 00000000 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20151124 - -[0004] Node Count : 00000008 -[0004] Node Offset : 00000034 -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00 - -/* ITS 0, for peri a */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000000 -//4c -/* ITS 1, for peri b */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000001 -//64 -/* ITS 2, for dsa a */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000002 -//7c -/* ITS 3, for dsa b */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000003 -//94 -/*Sec CPU ITS 0, for peri a */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000004 -//ac -/* SEC CPU ITS 1, for peri b */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000005 -//c4 -/* SEC CPU ITS 2, for dsa a */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000006 -//dc -/* SEC CPU ITS 3, for dsa b */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000007 - - - -/* mbi-gen peri b, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI0" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 000120c7 //device id -[0004] Output Reference : 0000004C -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen1 dsa a, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI1" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040800 //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen mbi7 - RoCE named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI9" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1e -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen dsa a - usb named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI5" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040080 //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen1 dsa a, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI2" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040900 //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen1 pcie, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI3" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040000 //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen1 pcie, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI4" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040040 //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen1 alg a, i2c 0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI6" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040B0E //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen1 alg a, i2c 2 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI7" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040B10 //device id -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/*1P NA PCIe2 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000002 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 0000f800 -[0004] ID Count : 00000800 -[0004] Output Base : 0000f800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 -/* 1P NB PCIe0 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000004 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00008800 -[0004] ID Count : 00000800 -[0004] Output Base : 00008800 -[0004] Output Reference : 0000007c -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* 1P NB PCIe1 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000005 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00007800 -[0004] ID Count : 00000800 -[0004] Output Base : 00007800 -[0004] Output Reference : 0000007c -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* 1P NB PCIe2 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000006 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 0000c000 -[0004] ID Count : 00000800 -[0004] Output Base : 0000c000 -[0004] Output Reference : 0000007c -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 -/* 1P NB PCIe3 */ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000007 - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00009000 -[0004] ID Count : 00000800 -[0004] Output Base : 00009000 -[0004] Output Reference : 0000007c -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 -/* 2P NA PCIe2*/ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 0000000a - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00001000 -[0004] ID Count : 00001000 -[0004] Output Base : 00001000 -[0004] Output Reference : 000000c4 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* 2P NB PCIe0*/ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 0000000c - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00002000 -[0004] ID Count : 00001000 -[0004] Output Base : 00002000 -[0004] Output Reference : 000000dc -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - - /* 2P NB PCIe1*/ -[0001] Type : 02 -[0002] Length : 0038 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 0000000d - Memory Size Limit : 00 - Reserved : 00000000 - -[0004] Input base : 00003000 -[0004] ID Count : 00001000 -[0004] Output Base : 00003000 -[0004] Output Reference : 000000dc -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* mbi-gen1 P1 dsa a, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI8" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00044800 //device id -[0004] Output Reference : 000000c4 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc deleted file mode 100644 index 7190cc4db512a41f28606cc20d7fd2ddfc0e5c01..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2016 Hisilicon Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - */ - -#include -#include "Hi1616Platform.h" - -#define MCFG_VERSION 0x1 - -#pragma pack(1) -typedef struct -{ - UINT64 ullBaseAddress; - UINT16 usSegGroupNum; - UINT8 ucStartBusNum; - UINT8 ucEndBusNum; - UINT32 Reserved2; -}EFI_MCFG_CONFIG_STRUCTURE; - -typedef struct -{ - EFI_ACPI_DESCRIPTION_HEADER Header; - UINT64 Reserved1; -}EFI_MCFG_TABLE_CONFIG; - -typedef struct -{ - EFI_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_MCFG_CONFIG_STRUCTURE Config_Structure[8]; -}EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; -#pragma pack() - -EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= -{ - { - { - EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - MCFG_VERSION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION - }, - 0x0000000000000000, //Reserved - }, - { - //1p NA PCIe2 - { - 0xa0000000, //Base Address - 0x2, //Segment Group Number - 0xF8, //Start Bus Number - 0xFF, //End Bus Number - 0x00000000, //Reserved - }, - //1p NB PCIe0 - { - 0x8a0000000, //Base Address - 0x4, //Segment Group Number - 0x88, //Start Bus Number - 0x8f, //End Bus Number - 0x00000000, //Reserved - }, - //1p NB PCIe1 - { - 0x8b0000000, //Base Address - 0x5, //Segment Group Number - 0x78, //Start Bus Number - 0x7F, //End Bus Number - 0x00000000, //Reserved - }, - //1p NB PCIe2 - { - 0x8a0000000, //Base Address - 0x6, //Segment Group Number - 0xc0, //Start Bus Number - 0xc7, //End Bus Number - 0x00000000, //Reserved - }, - //1p NB PCIe3 - { - 0x8b0000000, //Base Address - 0x7, //Segment Group Number - 0x90, //Start Bus Number - 0x97, //End Bus Number - 0x00000000, //Reserved - }, - //2P NA PCIe2 - { - 0x64000000000, //Base Address - 0xa, //Segment Group Number - 0x10, //Start Bus Number - 0x1f, //End Bus Number - 0x00000000, //Reserved - }, - //2P NB PCIe0 - { - 0x74000000000, //Base Address - 0xc, //Segment Group Number - 0x20, //Start Bus Number - 0x2f, //End Bus Number - 0x00000000, //Reserved - }, - //2P NB PCIe1 - { - 0x78000000000, //Base Address - 0xd, //Segment Group Number - 0x30, //Start Bus Number - 0x3f, //End Bus Number - 0x00000000, //Reserved - }, - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc deleted file mode 100644 index d64cb19b325a0b927a06b91b4d5c6697886e50ed..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016 Linaro Limited - * Copyright (c) 2016 Hisilicon Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Contributors: - * Yi Li - yi.li@linaro.org -*/ - -#include -#include "Hi1616Platform.h" - -#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004 - -#pragma pack(1) -typedef struct { - UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_6_1_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; - -typedef struct { - EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; - EFI_ACPI_6_1_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; - -} EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE; -#pragma pack() - -// -// System Locality Information Table -// Please modify all values in Slit.h only. -// -EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { - { - { - EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE), - EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION, - }, - // - // Beginning of SLIT specific fields - // - EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, - }, - { - {{0x0A, 0x0F, 0x14, 0x14}}, //Locality 0 - {{0x0F, 0x0A, 0x14, 0x14}}, //Locality 1 - {{0x14, 0x14, 0x0A, 0x0F}}, //Locality 2 - {{0x14, 0x14, 0x0F, 0x0A}}, //Locality 3 - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Slit; diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc deleted file mode 100644 index eb13773e40eb697f8fa4ee361dab899d87ee507f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc +++ /dev/null @@ -1,75 +0,0 @@ -/** @file -* Serial Port Console Redirection Table (SPCR) -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016 Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include -#include -#include -#include -#include "Hi1616Platform.h" - -#define SPCR_FLOW_CONTROL_NONE 0 - -STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { - ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), - // UINT8 InterfaceType; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, - // UINT8 Reserved1[3]; - { - EFI_ACPI_RESERVED_BYTE, - EFI_ACPI_RESERVED_BYTE, - EFI_ACPI_RESERVED_BYTE - }, - // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; - ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), - // UINT8 InterruptType; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, - // UINT8 Irq; - 0, // Not used on ARM - // UINT32 GlobalSystemInterrupt; - 807, - // UINT8 BaudRate; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, - // UINT8 Parity; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, - // UINT8 StopBits; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, - // UINT8 FlowControl; - SPCR_FLOW_CONTROL_NONE, - // UINT8 TerminalType; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, - // UINT8 Reserved2; - EFI_ACPI_RESERVED_BYTE, - // UINT16 PciDeviceId; - 0xFFFF, - // UINT16 PciVendorId; - 0xFFFF, - // UINT8 PciBusNumber; - 0x00, - // UINT8 PciDeviceNumber; - 0x00, - // UINT8 PciFunctionNumber; - 0x00, - // UINT32 PciFlags; - 0x00000000, - // UINT8 PciSegment; - 0x00, - // UINT32 Reserved3; - EFI_ACPI_RESERVED_DWORD -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc deleted file mode 100644 index e61d840ed4475a4b82ea5bf179638f5d1a3bf289..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - * Copyright (c) 2016 Hisilicon Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Contributors: - * Yi Li - yi.li@linaro.org - * - * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -*/ - -#include -#include -#include -#include "Hi1616Platform.h" - - -// -// Static Resource Affinity Table definition -// -EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { - { - {EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, - sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE), - EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION}, - /*Reserved*/ - 0x00000001, // Reserved to be 1 for backward compatibility - EFI_ACPI_RESERVED_QWORD - }, - - // - // - // Memory Affinity - // - { - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - }, - - { - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63 - }, - { - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000000), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000001), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000002), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000003), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000004), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000005), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000006), - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000007) - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Srat; diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl deleted file mode 100644 index c11e02646e015838451d912bfdee79b84b02bc14..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl +++ /dev/null @@ -1,274 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - // - // A57x16 Processor declaration - // - Device(CPU0) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - Device(CPU1) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - Device(CPU2) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - Device(CPU3) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - Device(CPU6) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - Device(CPU7) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } - Device(CPU8) { - Name(_HID, "ACPI0007") - Name(_UID, 8) - } - Device(CPU9) { - Name(_HID, "ACPI0007") - Name(_UID, 9) - } - Device(CP10) { - Name(_HID, "ACPI0007") - Name(_UID, 10) - } - Device(CP11) { - Name(_HID, "ACPI0007") - Name(_UID, 11) - } - Device(CP12) { - Name(_HID, "ACPI0007") - Name(_UID, 12) - } - Device(CP13) { - Name(_HID, "ACPI0007") - Name(_UID, 13) - } - Device(CP14) { - Name(_HID, "ACPI0007") - Name(_UID, 14) - } - Device(CP15) { - Name(_HID, "ACPI0007") - Name(_UID, 15) - } - Device(CP16) { - Name(_HID, "ACPI0007") - Name(_UID, 16) - } - Device(CP17) { - Name(_HID, "ACPI0007") - Name(_UID, 17) - } - Device(CP18) { - Name(_HID, "ACPI0007") - Name(_UID, 18) - } - Device(CP19) { - Name(_HID, "ACPI0007") - Name(_UID, 19) - } - Device(CP20) { - Name(_HID, "ACPI0007") - Name(_UID, 20) - } - Device(CP21) { - Name(_HID, "ACPI0007") - Name(_UID, 21) - } - Device(CP22) { - Name(_HID, "ACPI0007") - Name(_UID, 22) - } - Device(CP23) { - Name(_HID, "ACPI0007") - Name(_UID, 23) - } - Device(CP24) { - Name(_HID, "ACPI0007") - Name(_UID, 24) - } - Device(CP25) { - Name(_HID, "ACPI0007") - Name(_UID, 25) - } - Device(CP26) { - Name(_HID, "ACPI0007") - Name(_UID, 26) - } - Device(CP27) { - Name(_HID, "ACPI0007") - Name(_UID, 27) - } - Device(CP28) { - Name(_HID, "ACPI0007") - Name(_UID, 28) - } - Device(CP29) { - Name(_HID, "ACPI0007") - Name(_UID, 29) - } - Device(CP30) { - Name(_HID, "ACPI0007") - Name(_UID, 30) - } - Device(CP31) { - Name(_HID, "ACPI0007") - Name(_UID, 31) - } - Device(CP32) { - Name(_HID, "ACPI0007") - Name(_UID, 32) - } - Device(CP33) { - Name(_HID, "ACPI0007") - Name(_UID, 33) - } - Device(CP34) { - Name(_HID, "ACPI0007") - Name(_UID, 34) - } - Device(CP35) { - Name(_HID, "ACPI0007") - Name(_UID, 35) - } - Device(CP36) { - Name(_HID, "ACPI0007") - Name(_UID, 36) - } - Device(CP37) { - Name(_HID, "ACPI0007") - Name(_UID, 37) - } - Device(CP38) { - Name(_HID, "ACPI0007") - Name(_UID, 38) - } - Device(CP39) { - Name(_HID, "ACPI0007") - Name(_UID, 39) - } - Device(CP40) { - Name(_HID, "ACPI0007") - Name(_UID, 40) - } - Device(CP41) { - Name(_HID, "ACPI0007") - Name(_UID, 41) - } - Device(CP42) { - Name(_HID, "ACPI0007") - Name(_UID, 42) - } - Device(CP43) { - Name(_HID, "ACPI0007") - Name(_UID, 43) - } - Device(CP44) { - Name(_HID, "ACPI0007") - Name(_UID, 44) - } - Device(CP45) { - Name(_HID, "ACPI0007") - Name(_UID, 45) - } - Device(CP46) { - Name(_HID, "ACPI0007") - Name(_UID, 46) - } - Device(CP47) { - Name(_HID, "ACPI0007") - Name(_UID, 47) - } - Device(CP48) { - Name(_HID, "ACPI0007") - Name(_UID, 48) - } - Device(CP49) { - Name(_HID, "ACPI0007") - Name(_UID, 49) - } - Device(CP50) { - Name(_HID, "ACPI0007") - Name(_UID, 50) - } - Device(CP51) { - Name(_HID, "ACPI0007") - Name(_UID, 51) - } - Device(CP52) { - Name(_HID, "ACPI0007") - Name(_UID, 52) - } - Device(CP53) { - Name(_HID, "ACPI0007") - Name(_UID, 53) - } - Device(CP54) { - Name(_HID, "ACPI0007") - Name(_UID, 54) - } - Device(CP55) { - Name(_HID, "ACPI0007") - Name(_UID, 55) - } - Device(CP56) { - Name(_HID, "ACPI0007") - Name(_UID, 56) - } - Device(CP57) { - Name(_HID, "ACPI0007") - Name(_UID, 57) - } - Device(CP58) { - Name(_HID, "ACPI0007") - Name(_UID, 58) - } - Device(CP59) { - Name(_HID, "ACPI0007") - Name(_UID, 59) - } - Device(CP60) { - Name(_HID, "ACPI0007") - Name(_UID, 60) - } - Device(CP61) { - Name(_HID, "ACPI0007") - Name(_UID, 61) - } - Device(CP62) { - Name(_HID, "ACPI0007") - Name(_UID, 62) - } - Device(CP63) { - Name(_HID, "ACPI0007") - Name(_UID, 63) - } -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl deleted file mode 100644 index d62645f398196652d2518b8980dd62c08782be81..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl +++ /dev/null @@ -1,21 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - Device(COM0) { - Name(_HID, "ARMH0011") - Name(_UID, Zero) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x602B0000, 0x1000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 807 } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl deleted file mode 100644 index bd8fd13dc7831e13ae3d3433f35da78a1ee0046c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ /dev/null @@ -1,1275 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2016, Hisilicon Limited. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - Device (MDIO) - { - OperationRegion(CLKR, SystemMemory, 0x60000550, 8) - Field(CLKR, DWordAcc, NoLock, Preserve) { - CLKE, 1, // clock enable - , 31, - CLKD, 1, // clode disable - , 31, - } - OperationRegion(RSTR, SystemMemory, 0x60000c40, 8) - Field(RSTR, DWordAcc, NoLock, Preserve) { - RSTE, 1, // reset - , 31, - RSTD, 1, // de-reset - , 31, - } - - Name(_HID, "HISI0141") - Name(_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) - }) - - Method(_RST, 0, Serialized) { - Store (0x1, RSTE) - Sleep (10) - Store (0x1, CLKD) - Sleep (10) - Store (0x1, RSTD) - Sleep (10) - Store (0x1, CLKE) - Sleep (10) - } - } - - Device (DSF0) - { - OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) - Field(H3SR, DWordAcc, NoLock, Preserve) { - H3ST, 1, - , 31, //RESERVED - } - OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) - Field(H4SR, DWordAcc, NoLock, Preserve) { - H4ST, 1, - , 31, //RESERVED - } - // DSAF RESET - OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) - Field(DRER, DWordAcc, NoLock, Preserve) { - DRTE, 1, - , 31, //RESERVED - DRTD, 1, - , 31, //RESERVED - } - // NT RESET - OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) - Field(NRER, DWordAcc, NoLock, Preserve) { - NRTE, 1, - , 31, //RESERVED - NRTD, 1, - , 31, //RESERVED - } - // XGE RESET - OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) - Field(XRER, DWordAcc, NoLock, Preserve) { - XRTE, 31, - , 1, //RESERVED - XRTD, 31, - , 1, //RESERVED - } - - // GE RESET - OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) - Field(GRTR, DWordAcc, NoLock, Preserve) { - GR0E, 30, - , 2, //RESERVED - GR0D, 30, - , 2, //RESERVED - GR1E, 18, - , 14, //RESERVED - GR1D, 18, - , 14, //RESERVED - } - // PPE RESET - OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) - Field(PRTR, DWordAcc, NoLock, Preserve) { - PRTE, 10, - , 22, //RESERVED - PRTD, 10, - , 22, //RESERVED - } - - // RCB PPE COM RESET - OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) - Field(RRTR, DWordAcc, NoLock, Preserve) { - RRTE, 1, - , 31, //RESERVED - RRTD, 1, - , 31, //RESERVED - } - - // DSAF Channel RESET - OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8) - Field(DCRR, DWordAcc, NoLock, Preserve) { - DCRE, 1, - , 31, //RESERVED - DCRD, 1, - , 31, //RESERVED - } - - // RoCE RESET - OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8) - Field(RKRR, DWordAcc, NoLock, Preserve) { - RKRE, 1, - , 31, //RESERVED - RKRD, 1, - , 31, //RESERVED - } - - // RoCE Clock enable/disable - OperationRegion(RKCR, SystemMemory, 0xC0000328, 8) - Field(RKCR, DWordAcc, NoLock, Preserve) { - RCLE, 1, - , 31, //RESERVED - RCLD, 1, - , 31, //RESERVED - } - - // Hilink access sel cfg reg - OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) - Field(HSER, DWordAcc, NoLock, Preserve) { - HSEL, 2, // hilink_access_sel & hilink_access_wr_pul - , 30, // RESERVED - } - - // Serdes - OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) - Field(H4LR, DWordAcc, NoLock, Preserve) { - H4L0, 16, // port0 - , 16, //RESERVED - Offset (0x400), - H4L1, 16, // port1 - , 16, //RESERVED - Offset (0x800), - H4L2, 16, // port2 - , 16, //RESERVED - Offset (0xc00), - H4L3, 16, // port3 - , 16, //RESERVED - } - OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) - Field(H3LR, DWordAcc, NoLock, Preserve) { - H3L2, 16, // port4 - , 16, //RESERVED - Offset (0x400), - H3L3, 16, // port5 - , 16, //RESERVED - } - OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100) - Field(HSFP, ByteAcc, NoLock, Preserve) { - Offset (0x2), - HSF0, 1, // port0 - , 7, //RESERVED - Offset (0x6), - HSF1, 1, // port1 - , 7, //RESERVED - } - Name (_HID, "HISI00B2") - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) - Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"mode", "6port-16rss"}, - Package () {"buf-size", 4096}, - Package () {"desc-num", 1024}, - } - }) - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } - Method (_STA, 0, NotSerialized) - { - Return(0x0F) - } - - //reset XGE port - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XRST, 2, Serialized) { - ShiftLeft (0x2082082, Arg0, Local0) - Or (Local0, 0x1, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset XGE core - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XCRT, 2, Serialized) { - ShiftLeft (0x2080, Arg0, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset GE port - //Arg0 : GE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(GRST, 2, Serialized) { - If (LLessEqual (Arg0, 5)) { - //Service port - ShiftLeft (0x2082082, Arg0, Local0) - ShiftLeft (0x1, Arg0, Local1) - - If (LEqual (Arg1, 0)) { - Store(Local1, GR1E) - Store(Local0, GR0E) - } Else { - Store(Local0, GR0D) - Store(Local1, GR1D) - } - } - } - - //reset PPE port - //Arg0 : PPE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(PRST, 2, Serialized) { - ShiftLeft (0x1, Arg0, Local0) - If (LEqual (Arg1, 0)) { - Store(Local0, PRTE) - } Else { - Store(Local0, PRTD) - } - } - - //reset DSAF channels - //Arg0 : mask - //Arg1 : 0 reset, 1 de-reset - Method(DCRT, 2, Serialized) { - If (LEqual (Arg1, 0)) { - Store(Arg0, DCRE) - } Else { - Store(Arg0, DCRD) - } - } - - //reset RoCE - //Arg0 : 0 reset, 1 de-reset - Method(RRST, 1, Serialized) { - If (LEqual (Arg0, 0)) { - Store(0x1, RKRE) - } Else { - Store(0x1, RCLD) - Store(0x1, RKRD) - sleep(20) - Store(0x1, RCLE) - } - } - - // Set Serdes Loopback - //Arg0 : port - //Arg1 : 0 disable, 1 enable - Method(SRLP, 2, Serialized) { - ShiftLeft (Arg1, 10, Local0) - Switch (ToInteger(Arg0)) - { - case (0x0){ - Store (0, HSEL) - Store (H4L0, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L0) - } - case (0x1){ - Store (0, HSEL) - Store (H4L1, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L1) - } - case (0x2){ - Store (0, HSEL) - Store (H4L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L2) - } - case (0x3){ - Store (0, HSEL) - Store (H4L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L3) - } - case (0x4){ - Store (3, HSEL) - Store (H3L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L2) - } - case (0x5){ - Store (3, HSEL) - Store (H3L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L3) - } - } - } - - //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE) - //Arg1 : port - //Arg2 : 0 disable, 1 enable - Method(DRST, 3, Serialized) - { - Switch (ToInteger(Arg0)) - { - //DSAF reset - case (0x1) - { - Store (Arg2, Local0) - If (LEqual (Local0, 0)) - { - Store (0x1, DRTE) - Store (0x1, NRTE) - Sleep (10) - Store (0x1, RRTE) - } - Else - { - Store (0x1, DRTD) - Store (0x1, NRTD) - Sleep (10) - Store (0x1, RRTD) - } - } - //Reset PPE port - case (0x2) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - PRST (Local0, Local1) - } - - //Reset XGE core - case (0x3) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XCRT (Local0, Local1) - } - //Reset XGE port - case (0x4) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XRST (Local0, Local1) - } - - //Reset GE port - case (0x5) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - GRST (Local0, Local1) - } - - //Reset DSAF Channels - case (0x6) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - DCRT (Local0, Local1) - } - - //Reset RoCE - case (0x7) - { - // Discarding Arg1 as it is always 0 - Store (Arg2, Local0) - RRST (Local0) - } - } - } - - // _DSM Device Specific Method - // - // Arg0: UUID Unique function identifier - // Arg1: Integer Revision Level - // Arg2: Integer Function Index - // 0 : Return Supported Functions bit mask - // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE) - // Arg3[1] : port index in dsaf - // Arg3[2] : 0 reset, 1 cancle reset - // 2 : Set Serdes Loopback - // Arg3[0] : port - // Arg3[1] : 0 disable, 1 enable - // 3 : LED op set - // Arg3[0] : op type - // Arg3[1] : port - // Arg3[2] : para - // 4 : Get port type (GE or XGE) - // Arg3[0] : port index in dsaf - // Return : 0 GE, 1 XGE - // 5 : Get sfp status - // Arg3[0] : port index in dsaf - // Return : 0 no sfp, 1 have sfp - // Arg3: Package Parameters - Method (_DSM, 4, Serialized) - { - If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) - { - If (LEqual (Arg1, 0x00)) - { - Switch (ToInteger(Arg2)) - { - case (0x0) - { - Return (Buffer () {0x3F}) - } - - //Reset Sequence - case (0x1) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - Store (DeRefOf (Index (Arg3, 2)), Local2) - DRST (Local0, Local1, Local2) - } - - //Set Serdes Loopback - case (0x2) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - SRLP (Local0, Local1) - } - - //LED op set - case (0x3) - { - - } - - // Get port type (GE or XGE) - case (0x4) - { - Store (0, Local1) - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LLessEqual (Local0, 3)) - { - // mac0: Hilink4 Lane0 - // mac1: Hilink4 Lane1 - // mac2: Hilink4 Lane2 - // mac3: Hilink4 Lane3 - Store (H4ST, Local1) - } - ElseIf (LLessEqual (Local0, 5)) - { - // mac4: Hilink3 Lane2 - // mac5: Hilink3 Lane3 - Store (H3ST, Local1) - } - - Return (Local1) - } - - //Get sfp status - case (0x5) - { - Store (1, Local1) //set no sfp default - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LEqual (Local0, 0)) - { - // port 0: - Store (HSF0, Local1) - } - ElseIf (LEqual (Local0, 1)) - { - // port 1 - Store (HSF1, Local1) - } - - XOr (Local1, 1, local1) - Return (Local1) - } - } - } - } - Return (Buffer() {0x00}) - } - Device (PRT0) - { - Name (_ADR, 0x0) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT1) - { - Name (_ADR, 0x1) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 1}, - Package () {"media-type", "fiber"}, - } - }) - } - - Device (PRT2) - { - Name (_ADR, 0x2) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 2}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT3) - { - Name (_ADR, 0x3) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 3}, - Package () {"media-type", "fiber"}, - } - }) - } - - Device (PRT4) - { - Name (_ADR, 0x4) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 4}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 0}, - Package () {"mdio-node", Package (){\_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - Device (PRT5) - { - Name (_ADR, 0x5) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 5}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 1}, - Package () {"mdio-node", Package (){\_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - } - Device (ETH4) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 4}, - } - }) - } - Device (ETH5) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 5}, - } - }) - } - Device (ETH0) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 0}, - } - }) - } - Device (ETH1) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 1}, - } - }) - } - - Device (ETH2) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 2}, - } - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0) - } - } - Device (ETH3) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 3}, - } - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0) - } - } - - Device (ROCE) { - Name(_HID, "HISI00D1") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}}, - Package () {"dsaf-handle", Package (){\_SB.DSF0}}, - Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes - Package () {"interrupt-names", Package() {"hns-roce-comp-0", - "hns-roce-comp-1", - "hns-roce-comp-2", - "hns-roce-comp-3", - "hns-roce-comp-4", - "hns-roce-comp-5", - "hns-roce-comp-6", - "hns-roce-comp-7", - "hns-roce-comp-8", - "hns-roce-comp-9", - "hns-roce-comp-10", - "hns-roce-comp-11", - "hns-roce-comp-12", - "hns-roce-comp-13", - "hns-roce-comp-14", - "hns-roce-comp-15", - "hns-roce-comp-16", - "hns-roce-comp-17", - "hns-roce-comp-18", - "hns-roce-comp-19", - "hns-roce-comp-20", - "hns-roce-comp-21", - "hns-roce-comp-22", - "hns-roce-comp-23", - "hns-roce-comp-24", - "hns-roce-comp-25", - "hns-roce-comp-26", - "hns-roce-comp-27", - "hns-roce-comp-28", - "hns-roce-comp-29", - "hns-roce-comp-30", - "hns-roce-comp-31", - "hns-roce-async", - "hns-roce-common"}}, - } - }) - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI9") - { - 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, - 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, - 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, - } - }) - } - - /* for p1 */ - Device (DSF1) - { - - OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4) - Field(H3SR, DWordAcc, NoLock, Preserve) { - H3ST, 1, - , 31, //RESERVED - } - OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4) - Field(H4SR, DWordAcc, NoLock, Preserve) { - H4ST, 1, - , 31, //RESERVED - } - // DSAF RESET - OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8) - Field(DRER, DWordAcc, NoLock, Preserve) { - DRTE, 1, - , 31, //RESERVED - DRTD, 1, - , 31, //RESERVED - } - // NT RESET - OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8) - Field(NRER, DWordAcc, NoLock, Preserve) { - NRTE, 1, - , 31, //RESERVED - NRTD, 1, - , 31, //RESERVED - } - // XGE RESET - OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8) - Field(XRER, DWordAcc, NoLock, Preserve) { - XRTE, 31, - , 1, //RESERVED - XRTD, 31, - , 1, //RESERVED - } - - // GE RESET - OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16) - Field(GRTR, DWordAcc, NoLock, Preserve) { - GR0E, 30, - , 2, //RESERVED - GR0D, 30, - , 2, //RESERVED - GR1E, 18, - , 14, //RESERVED - GR1D, 18, - , 14, //RESERVED - } - // PPE RESET - OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8) - Field(PRTR, DWordAcc, NoLock, Preserve) { - PRTE, 10, - , 22, //RESERVED - PRTD, 10, - , 22, //RESERVED - } - - // RCB PPE COM RESET - OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8) - Field(RRTR, DWordAcc, NoLock, Preserve) { - RRTE, 1, - , 31, //RESERVED - RRTD, 1, - , 31, //RESERVED - } - - // RCB_2X COM RESET - OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8) - Field(RBTR, DWordAcc, NoLock, Preserve) { - RBTE, 1, - , 31, //RESERVED - RBTD, 1, - , 31, //RESERVED - } - - // Hilink access sel cfg reg - OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4) - Field(HSER, DWordAcc, NoLock, Preserve) { - HSEL, 2, // hilink_access_sel & hilink_access_wr_pul - , 30, // RESERVED - } - - // Serdes - OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000) - Field(H4LR, DWordAcc, NoLock, Preserve) { - H4L0, 16, // port0 - , 16, //RESERVED - Offset (0x400), - H4L1, 16, // port1 - , 16, //RESERVED - Offset (0x800), - H4L2, 16, // port2 - , 16, //RESERVED - Offset (0xc00), - H4L3, 16, // port3 - , 16, //RESERVED - } - OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800) - Field(H3LR, DWordAcc, NoLock, Preserve) { - H3L2, 16, // port4 - , 16, //RESERVED - Offset (0x400), - H3L3, 16, // port5 - , 16, //RESERVED - } - - Name (_HID, "HISI00B2") - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400c5000000, // Min Base Address - 0x400c588ffff, // Max Base Address - 0x0, // Translate - 0x890000 // Length - ) - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400c7000000, // Min Base Address - 0x400c705ffff, // Max Base Address - 0x0, // Translate - 0x60000 // Length - ) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8") - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8") - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8") - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"mode", "6port-16rss"}, - Package () {"buf-size", 4096}, - Package () {"desc-num", 1024}, - } - }) - - //reset XGE port - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XRST, 2, Serialized) { - ShiftLeft (0x2082082, Arg0, Local0) - Or (Local0, 0x1, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset XGE core - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XCRT, 2, Serialized) { - ShiftLeft (0x2080, Arg0, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset GE port - //Arg0 : GE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(GRST, 2, Serialized) { - If (LLessEqual (Arg0, 5)) { - //Service port - ShiftLeft (0x2082082, Arg0, Local0) - ShiftLeft (0x1, Arg0, Local1) - - If (LEqual (Arg1, 0)) { - Store(Local1, GR1E) - Store(Local0, GR0E) - } Else { - Store(Local0, GR0D) - Store(Local1, GR1D) - } - } - } - - //reset PPE port - //Arg0 : PPE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(PRST, 2, Serialized) { - ShiftLeft (0x1, Arg0, Local0) - If (LEqual (Arg1, 0)) { - Store(Local0, PRTE) - } Else { - Store(Local0, PRTD) - } - } - - // Set Serdes Loopback - //Arg0 : port - //Arg1 : 0 disable, 1 enable - Method(SRLP, 2, Serialized) { - ShiftLeft (Arg1, 10, Local0) - Switch (ToInteger(Arg0)) - { - case (0x0){ - Store (0, HSEL) - Store (H4L0, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L0) - } - case (0x1){ - Store (0, HSEL) - Store (H4L1, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L1) - } - case (0x2){ - Store (0, HSEL) - Store (H4L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L2) - } - case (0x3){ - Store (0, HSEL) - Store (H4L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L3) - } - case (0x4){ - Store (3, HSEL) - Store (H3L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L2) - } - case (0x5){ - Store (3, HSEL) - Store (H3L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L3) - } - } - } - - //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) - //Arg1 : port - //Arg2 : 0 disable, 1 enable - Method(DRST, 3, Serialized) - { - Switch (ToInteger(Arg0)) - { - //DSAF reset - case (0x1) - { - Store (Arg2, Local0) - If (LEqual (Local0, 0)) - { - Store (0x1, DRTE) - Store (0x1, NRTE) - Sleep (10) - Store (0x1, RRTE) - Store (0x1, RBTE) - } - Else - { - Store (0x1, DRTD) - Store (0x1, NRTD) - Sleep (10) - Store (0x1, RRTD) - Store (0x1, RBTD) - } - } - //Reset PPE port - case (0x2) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - PRST (Local0, Local1) - } - - //Reset XGE core - case (0x3) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XCRT (Local0, Local1) - } - //Reset XGE port - case (0x4) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XRST (Local0, Local1) - } - - //Reset GE port - case (0x5) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - GRST (Local0, Local1) - } - } - } - - // _DSM Device Specific Method - // - // Arg0: UUID Unique function identifier - // Arg1: Integer Revision Level - // Arg2: Integer Function Index - // 0 : Return Supported Functions bit mask - // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) - // Arg3[1] : port index in dsaf - // Arg3[2] : 0 reset, 1 cancle reset - // 2 : Set Serdes Loopback - // Arg3[0] : port - // Arg3[1] : 0 disable, 1 enable - // 3 : LED op set - // Arg3[0] : op type - // Arg3[1] : port - // Arg3[2] : para - // 4 : Get port type (GE or XGE) - // Arg3[0] : port index in dsaf - // Return : 0 GE, 1 XGE - // 5 : Get sfp status - // Arg3[0] : port index in dsaf - // Return : 0 no sfp, 1 have sfp - // Arg3: Package Parameters - Method (_DSM, 4, Serialized) - { - If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) - { - If (LEqual (Arg1, 0x00)) - { - Switch (ToInteger(Arg2)) - { - case (0x0) - { - Return (Buffer () {0x3F}) - } - - //Reset Sequence - case (0x1) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - Store (DeRefOf (Index (Arg3, 2)), Local2) - DRST (Local0, Local1, Local2) - } - - //Set Serdes Loopback - case (0x2) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - SRLP (Local0, Local1) - } - - //LED op set - case (0x3) - { - - } - - // Get port type (GE or XGE) - case (0x4) - { - Store (0, Local1) - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LLessEqual (Local0, 3)) - { - // mac0: Hilink4 Lane0 - // mac1: Hilink4 Lane1 - // mac2: Hilink4 Lane2 - // mac3: Hilink4 Lane3 - Store (H4ST, Local1) - } - ElseIf (LLessEqual (Local0, 5)) - { - // mac4: Hilink3 Lane2 - // mac5: Hilink3 Lane3 - Store (H3ST, Local1) - } - - Return (Local1) - } - - //Get sfp status - case (0x5) - { - - } - } - } - } - Return (Buffer() {0x00}) - } - - Device (PRT6) - { - Name (_ADR, 0x6) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT7) - { - Name (_ADR, 0x7) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 1}, - Package () {"media-type", "fiber"}, - } - }) - } - } - - Device (ETH6) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF1}}, - Package () {"port-idx-in-ae", 0}, - } - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0) - } - } - Device (ETH7) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF1}}, - Package () {"port-idx-in-ae", 1}, - } - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0) - } - } - -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl deleted file mode 100644 index 9a21323a3b52f6544ceeebd6de33a78fcec3ecca..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl +++ /dev/null @@ -1,32 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(I2C2) { - Name(_HID, "HISI02A1") - Name(_CID, "APMC0D0F") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd0100000, 0x10000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") { 707 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 100000}, - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 0x9c2}, - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl deleted file mode 100644 index 3f4d396dadb2e91f84656d5cca52e5c0e763d9e1..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl +++ /dev/null @@ -1,426 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - // Mbi-gen peri b intc - Device(MBI0) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x60080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - Device(MBI1) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 409} - } - }) - } - - // Mbi-gen sas0 - Device(MBI2) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI3) { // Mbi-gen sas1 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - Device(MBI4) { // Mbi-gen sas2 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, - } - - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI5) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,} - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 2} - } - }) - } - - Device(MBI6) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - Device(MBI7) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd0080000, 0x10000) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - Device(MBI8) { - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400c0080000, // Min Base Address - 0x400c008ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - - Name(_PRS, ResourceTemplate() { - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 409} - } - }) - } -/* - Device(MBI4) { // Mbi-gen dsa1 dbg0 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI5) { // Mbi-gen dsa2 dbg1 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI6) { // Mbi-gen dsa sas0 intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } -*/ - Device(MBI9) { // Mbi-gen roce intc - Name(_HID, "HISI0152") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name (_PRS, ResourceTemplate (){ - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, - 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, - 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, - } - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 34} - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl deleted file mode 100644 index 91b6fe26e32938859aec1acc619c8f8345a4c0fd..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ /dev/null @@ -1,998 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */ - OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4) - Field (ECRA, AnyAcc, NoLock, Preserve) - { - VECA, 32, - } - - /* RBYV:Return by chip version - * the pcie device should be disable for chip's reason before EC, - * and the pcie device should be enable after EC for OS */ - Method (RBYV) - { - Store(VECA, local0) - And (local0, 0xFFF00, local1) - If (LEqual (local1, 0x10200)) { - Return (0xf) - } Else { - Return (0x0) - } - } - -/* - See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 -*/ -#define PCI_OSC_SUPPORT() \ - Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ - Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ - Method(_OSC,4) { \ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ - /* Create DWord-adressable fields from the Capabilities Buffer */ \ - CreateDWordField(Arg3,0,CDW1) \ - CreateDWordField(Arg3,4,CDW2) \ - CreateDWordField(Arg3,8,CDW3) \ - /* Save Capabilities DWord2 & 3 */ \ - Store(CDW2,SUPP) \ - Store(CDW3,CTRL) \ - /* Only allow native hot plug control if OS supports: */ \ - /* ASPM */ \ - /* Clock PM */ \ - /* MSI/MSI-X */ \ - If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ - And(CTRL,0x1E,CTRL) \ - }\ - \ - /* Do not allow native PME, AER */ \ - /* Never allow SHPC (no SHPC controller in this system)*/ \ - And(CTRL,0x10,CTRL) \ - If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ - Or(CDW1,0x08,CDW1) \ - } \ - \ - If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ - Or(CDW1,0x10,CDW1) \ - } \ - \ - /* Update DWORD3 in the buffer */ \ - Store(CTRL,CDW3) \ - Return(Arg3) \ - } Else { \ - Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ - Return(Arg3) \ - } \ - } // End _OSC - - // 1P NA PCIe2 - Device (PCI2) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0xF8) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0xF8, // AddressMinimum - Minimum Bus Number - 0xFF, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x8 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xa8000000, // Min Base Address - 0xaf7effff, // Max Base Address - 0x0, // Translate - 0x77f0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xaf7f0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } - } // Device(PCI2) - - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x2) // Unique ID - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - } - - Device (R1NA) // reserve 1p NA ECAM resource - { - Name (_HID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - } - - // 1p NB PCIe0 - Device (PCI4) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 4) // Segment of this Root complex - Name(_BBN, 0x88) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x88, // AddressMinimum - Minimum Bus Number - 0x8f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x8 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xa9000000, // Min Base Address - 0xabfeffff, // Max Base Address - 0x800000000, // Translate - 0x2ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x8abff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RES4) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0090000, // Min Base Address - 0x8a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x01) - } - } // Device(PCI4) - Device (RES4) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x4) // Unique ID - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //host bridge register space - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0090000, // Min Base Address - 0x8a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - - // 1P NB PCI1 - Device (PCI5) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x78) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x78, // AddressMinimum - Minimum Bus Number - 0x7f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x8 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb0000000, // Min Base Address - 0xb77effff, // Max Base Address - 0x800000000, // Translate - 0x77f0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x8b77f0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RES5) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0200000, // Min Base Address - 0x8a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x01) - } - } // Device(PCI5) - Device (RES5) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x5) // Unique ID - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //host bridge register space - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0200000, // Min Base Address - 0x8a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - - // 1P NB PCIe2 - Device (PCI6) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0x6) // Segment of this Root complex - Name(_BBN, 0xc0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0xc0, // AddressMinimum - Minimum Bus Number - 0xc7, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x8 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xac900000, // Min Base Address - 0xaffeffff, // Max Base Address - 0x800000000, // Translate - 0x36f0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x8afff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RES6) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00a0000, // Min Base Address - 0x8a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x01) - } - } // Device(PCI6) - Device (RES6) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x6) // Unique ID - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //host bridge register space - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00a0000, // Min Base Address - 0x8a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - // 1P NB PCIe3 - Device (PCI7) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0x7) // Segment of this Root complex - Name(_BBN, 0x90) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x90, // AddressMinimum - Minimum Bus Number - 0x97, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x8 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb9800000, // Min Base Address - 0xbffeffff, // Max Base Address - 0x800000000, // Translate - 0x67f0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x8bfff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RES7) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00b0000, // Min Base Address - 0x8a00bffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x01) - } - } // Device(PCI7) - Device (RES7) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0x7) // Unique ID - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //host bridge register space - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00b0000, // Min Base Address - 0x8a00bffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - - Device (R1NB) // reserve 1p NB ECAM resource - { - Name (_HID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //ECAM space for [bus 88-8f] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a8800000, // Min Base Address - 0x8a8ffffff, // Max Base Address - 0x0, // Translate - 0x800000 // Length - ) - QwordMemory ( //ECAM space for [bus 78-7f] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8b7800000, // Min Base Address - 0x8b7ffffff, // Max Base Address - 0x0, // Translate - 0x800000 // Length - ) - QwordMemory ( //ECAM space for [bus c0-c7] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8ac000000, // Min Base Address - 0x8ac7fffff, // Max Base Address - 0x0, // Translate - 0x800000 // Length - ) - QwordMemory ( //ECAM space for [bus 90-97] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8b9000000, // Min Base Address - 0x8b97fffff, // Max Base Address - 0x0, // Translate - 0x800000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - // 2P NA PCIe2 - Device (PCIa) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0xa) // Segment of this Root complex - Name(_BBN, 0x10) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x10, // AddressMinimum - Minimum Bus Number - 0x1f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x10 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0x40000000, // Min Base Address - 0xefffffff, // Max Base Address - 0x65000000000, // Translate - 0xb0000000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x67fffff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RESa) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x600a00a0000, // Min Base Address - 0x600a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } - } // Device(PCIa) - Device (RESa) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0xa) // Unique ID - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //host bridge register space - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x600a00a0000, // Min Base Address - 0x600a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - } - - Device (R2NA) //reserve for 2p NA ecam resource - { - Name (_HID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //ECAM space for [bus 10-1f] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x64001000000, // Min Base Address - 0x64001ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - } - // 2P NB PCIe0 - Device (PCIc) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0xc) // Segment of this Root complex - Name(_BBN, 0x20) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x20, // AddressMinimum - Minimum Bus Number - 0x2f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x10 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0x40000000, // Min Base Address - 0xefffffff, // Max Base Address - 0x75000000000, // Translate - 0xb0000000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x77fffff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RESc) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0090000, // Min Base Address - 0x700a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x03) - } - } // Device(PCIc) - - Device (RESc) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0xc) // Unique ID - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //host bridge register space - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0090000, // Min Base Address - 0x700a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - //2P NB PCIe1 - Device (PCId) - { - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0xd) // Segment of this Root complex - Name(_BBN, 0x30) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x30, // AddressMinimum - Minimum Bus Number - 0x3f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x10 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0x40000000, // Min Base Address - 0xefffffff, // Max Base Address - 0x79000000000, // Translate - 0xB0000000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0x7bfffff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - Device (RESd) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0200000, // Min Base Address - 0x700a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } - PCI_OSC_SUPPORT() - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x03) - } - } // Device(PCId) - Device (RESd) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_UID, 0xd) // Unique ID - Name (_CRS, ResourceTemplate (){ //host bridge register space - QwordMemory ( - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0200000, // Min Base Address - 0x700a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } - - Device (R2NB) //reserve for 2p NB ecam resource - { - Name (_HID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( //ECAM space for [bus 20-2f] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x74002000000, // Min Base Address - 0x74002ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length - ) - QwordMemory ( //ECAM space for [bus 30-3f] - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x78003000000, // Min Base Address - 0x78003ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length - ) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (RBYV()) - } - } -} - diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl deleted file mode 100644 index 9e7256ff5554f146fb155ae99565bb135f7c2c47..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ /dev/null @@ -1,261 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - Device(SAS0) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x338), - CLK, 32, - CLKD, 32, - Offset (0xa60), - RST, 32, - DRST, 32, - Offset (0x5a30), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } - Method (_STA, 0, NotSerialized) - { - Return (0x0) - } - } - - Device(SAS1) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") - { - 64,65,66,67,68, - 69,70,71,72,73, - 74,75,76,77,78, - 79,80,81,82,83, - 84,85,86,87,88, - 89,90,91,92,93, - 94,95,96,97,98, - 99,100,101,102,103, - 104,105,106,107,108, - 109,110,111,112,113, - 114,115,116,117,118, - 119,120,121,122,123, - 124,125,126,127,128, - 129,130,131,132,133, - 134,135,136,137,138, - 139,140,141,142,143, - 144,145,146,147,148, - 149,150,151,152,153, - 154,155,156,157,158, - 159, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - Package () {"hip06-sas-v2-quirk-amt", 1}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x318), - CLK, 32, - CLKD, 32, - Offset (0xa18), - RST, 32, - DRST, 32, - Offset (0x5a0c), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } - Method (_STA, 0, NotSerialized) - { - Return(0x0F) - } - } - Device(SAS2) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI4") - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4") - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x3a8), - CLK, 32, - CLKD, 32, - Offset (0xae0), - RST, 32, - DRST, 32, - Offset (0x5a70), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } - Method (_STA, 0, NotSerialized) - { - Return (0x0) - } - } - -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl deleted file mode 100644 index 39feb146c7324efac2929ea74062fda5f9afbf96..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl +++ /dev/null @@ -1,121 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - Device (USB0) - { - Name (_HID, "PNP0D20") // _HID: Hardware ID - Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID - Name (_CCA, One) // _CCA: Cache Coherency Attribute - Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings - { - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, - 0xa7020000, // Address Base - 0x00010000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI5") - { - 641, - } - }) - Return (RBUF) /* \_SB_.USB0._CRS.RBUF */ - } - - Device (RHUB) - { - Name (_ADR, Zero) // _ADR: Address - Device (PRT1) - { - Name (_ADR, One) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - Zero, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0, - PLD_VerticalOffset = 0x0, - PLD_HorizontalOffset = 0x0) - }) - } - - Device (PRT2) - { - Name (_ADR, 0x02) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT3) - { - Name (_ADR, 0x03) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT4) - { - Name (_ADR, 0x04) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - } - } -} - diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl deleted file mode 100644 index 061bf9235a2e1f4a2d735369f74d5fcacaee1570..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl +++ /dev/null @@ -1,25 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -#include "Hi1616Platform.h" - -DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_OEM_REVISION) { - include ("Lpc.asl") - include ("D05Mbig.asl") - include ("Com.asl") - include ("CPU.asl") - include ("D05I2c.asl") - include ("D05Usb.asl") - include ("D05Hns.asl") - include ("D05Sas.asl") - include ("D05Pci.asl") -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl deleted file mode 100644 index 2ed1cb97a290087296a704094198f9e3db578712..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* -* Copyright (c) 2016 Hisilicon Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -// -// LPC -// - -Scope(_SB) { - Device (LPC0) { - Name (_HID, "HISI0191") // HiSi LPC - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) - }) - } - - Device (LPC0.IPMI) { - Name (_HID, "IPI0001") - Method (_IFT) { - Return (0x03) - } - Name (LORS, ResourceTemplate() { - QWordIO ( - ResourceConsumer, - MinNotFixed, // _MIF - MaxNotFixed, // _MAF - PosDecode, - EntireRange, - 0x0, // _GRA - 0xe4, // _MIN - 0x3fff, // _MAX - 0x0, // _TRA - 0x04, // _LEN - , , - BTIO - ) - }) - CreateQWordField (LORS, BTIO._MIN, CMIN) - CreateQWordField (LORS, BTIO._MAX, CMAX) - CreateQWordField (LORS, BTIO._LEN, CLEN) - - Method (_PRS, 0) { - Return (LORS) - } - - Method (_CRS, 0) { - Return (LORS) - } - Method (_SRS, 1) { - CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MIN, IMIN) - Store (IMIN, CMIN) - CreateQWordField (Arg0, \_SB.LPC0.IPMI.BTIO._MAX, IMAX) - Store (IMAX, CMAX) - } - } - - Device (LPC0.CON0) { - Name (_HID, "HISI1031") - Name (_CID, "PNP0501") - Name (LORS, ResourceTemplate() { - QWordIO ( - ResourceConsumer, - MinNotFixed, // _MIF - MaxNotFixed, // _MAF - PosDecode, - EntireRange, - 0x0, // _GRA - 0x2F8, // _MIN - 0x3fff, // _MAX - 0x0, // _TRA - 0x08, // _LEN - , , - IO02 - ) - }) - CreateQWordField (LORS, IO02._MIN, CMIN) - CreateQWordField (LORS, IO02._MAX, CMAX) - CreateQWordField (LORS, IO02._LEN, CLEN) - - Method (_PRS, 0) { - Return (LORS) - } - - Method (_CRS, 0) { - Return (LORS) - } - Method (_SRS, 1) { - CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MIN, IMIN) - Store (IMIN, CMIN) - CreateQWordField (Arg0, \_SB.LPC0.CON0.IO02._MAX, IMAX) - Store (IMAX, CMAX) - } - } -} diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc deleted file mode 100644 index 556de4ea191b16300da22400381fc223acdc0aeb..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc +++ /dev/null @@ -1,61 +0,0 @@ -/** @file -* Firmware ACPI Control Structure (FACS) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include - -EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length - 0xA152, // UINT32 HardwareSignature - 0, // UINT32 FirmwareWakingVector - 0, // UINT32 GlobalLock - 0, // UINT32 Flags - 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; - { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] - EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] - 0, // UINT32 OspmFlags "Platform firmware must - // initialize this field to zero." - { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] - EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Facs; - diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc deleted file mode 100644 index c59e5e774acae1af85292a036a0208627e84bd84..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc +++ /dev/null @@ -1,86 +0,0 @@ -/** @file -* Fixed ACPI Description Table (FADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1616Platform.h" - -#include -#include - -EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { - ARM_ACPI_HEADER ( - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION - ), - 0, // UINT32 FirmwareCtrl - 0, // UINT32 Dsdt - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile - 0, // UINT16 SciInt - 0, // UINT32 SmiCmd - 0, // UINT8 AcpiEnable - 0, // UINT8 AcpiDisable - 0, // UINT8 S4BiosReq - 0, // UINT8 PstateCnt - 0, // UINT32 Pm1aEvtBlk - 0, // UINT32 Pm1bEvtBlk - 0, // UINT32 Pm1aCntBlk - 0, // UINT32 Pm1bCntBlk - 0, // UINT32 Pm2CntBlk - 0, // UINT32 PmTmrBlk - 0, // UINT32 Gpe0Blk - 0, // UINT32 Gpe1Blk - 0, // UINT8 Pm1EvtLen - 0, // UINT8 Pm1CntLen - 0, // UINT8 Pm2CntLen - 0, // UINT8 PmTmrLen - 0, // UINT8 Gpe0BlkLen - 0, // UINT8 Gpe1BlkLen - 0, // UINT8 Gpe1Base - 0, // UINT8 CstCnt - 0, // UINT16 PLvl2Lat - 0, // UINT16 PLvl3Lat - 0, // UINT16 FlushSize - 0, // UINT16 FlushStride - 0, // UINT8 DutyOffset - 0, // UINT8 DutyWidth - 0, // UINT8 DayAlrm - 0, // UINT8 MonAlrm - 0, // UINT8 Century - 0, // UINT16 IaPcBootArch - 0, // UINT8 Reserved1 - EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg - 0, // UINT8 ResetValue - EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision - 0, // UINT64 XFirmwareCtrl - 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg - 0 // UINT64 Hypervisor Vendor Identify -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc deleted file mode 100644 index df8f266d9ae8a73213d095fecdd4136d8b5f2d53..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc +++ /dev/null @@ -1,78 +0,0 @@ -/** @file -* Generic Timer Description Table (GTDT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include -#include -#include -#include "Hi1616Platform.h" - -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE -#define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY -#define GTDT_TIMER_ACTIVE_HIGH 0 -#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY - -#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ALWAYS_ON_CAPABILITY | GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) - -// Generic watchdog address for SCCL (Super CPU cluster) A and SCCL B on Hi1616. -// Watchdogs on socket 1 are not mapped to SPI interrupts so we can't describe -// them in GTDT. -#define GENERIC_WATCHDOG_CONTROL_BASE_SCCL_A 0x40500000 -#define GENERIC_WATCHDOG_REFRESH_BASE_SCCL_A 0x40600000 -#define GENERIC_WATCHDOG_CONTROL_BASE_SCCL_B 0x60500000 -#define GENERIC_WATCHDOG_REFRESH_BASE_SCCL_B 0x60600000 - -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT]; -} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; - -#pragma pack () - -EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { - { - ARM_ACPI_HEADER( - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION - ), - 0xFFFFFFFFFFFFFFFF, // UINT64 CntControl Base PhysicalAddress - 0, // UINT32 Reserved - FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags - FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags - FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags - FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress - HI1616_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset - }, - { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - GENERIC_WATCHDOG_REFRESH_BASE_SCCL_A, GENERIC_WATCHDOG_CONTROL_BASE_SCCL_A, 400, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - GENERIC_WATCHDOG_REFRESH_BASE_SCCL_B, GENERIC_WATCHDOG_CONTROL_BASE_SCCL_B, 496, 0) - } - }; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Gtdt; - diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h deleted file mode 100644 index f94dd4e42ae35f6accf2f8cc33dc12427de9ab7a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - - -#ifndef _HI1610_PLATFORM_H_ -#define _HI1610_PLATFORM_H_ - -#include -#include - -#define HI1616_WATCHDOG_COUNT 2 -#define HI1616_GIC_STRUCTURE_COUNT 64 - -#define HI1616_MPID_TA_BASE 0x10000 -#define HI1616_MPID_TB_BASE 0x30000 -#define HI1616_MPID_TA_2_BASE 0x50000 -#define HI1616_MPID_TB_2_BASE 0x70000 - -// Differs from Juno, we have another affinity level beyond cluster and core -#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (HI1616_MPID_TA_BASE | ((ClusterId) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (HI1616_MPID_TB_BASE | ((ClusterId) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (HI1616_MPID_TA_2_BASE | ((ClusterId) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (HI1616_MPID_TB_2_BASE | ((ClusterId) << 8) | (CoreId)) - -// -// Multiple APIC Description Table -// -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[HI1616_GIC_STRUCTURE_COUNT]; - EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8]; -} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; - -#pragma pack () - -#endif diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc deleted file mode 100644 index f74f0bbe85356f8a400e0fad268e55f15aee1f1b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc +++ /dev/null @@ -1,255 +0,0 @@ -/** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - - -#include -#include -#include -#include -#include -#include "Hi1616Platform.h" - -EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION - ), - // - // MADT specific fields - // - 0, // LocalApicAddress - 0, // Flags - }, - { - // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, - // GsivId, GicRBase, Mpidr) - // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v6.1). - // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses - // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */, 0), - }, - - EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4), - { - EFI_ACPI_6_1_GIC_ITS_INIT(0,0x4C000000), //peri a - EFI_ACPI_6_1_GIC_ITS_INIT(1,0x6C000000), //peri b - EFI_ACPI_6_1_GIC_ITS_INIT(2,0xC6000000), //dsa a - EFI_ACPI_6_1_GIC_ITS_INIT(3,0x8C6000000), //dsa b - EFI_ACPI_6_1_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a - EFI_ACPI_6_1_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b - EFI_ACPI_6_1_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a - EFI_ACPI_6_1_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Hisilicon/Hi1616/Hi1616.dec b/Silicon/Hisilicon/Hi1616/Hi1616.dec deleted file mode 100644 index 7371b0d3e302a0d26683e47eeea637993f1c09dd..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/Hi1616.dec +++ /dev/null @@ -1,17 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - DEC_SPECIFICATION = 0x0001001A - PACKAGE_NAME = Hi1616Pkg - PACKAGE_GUID = 8a64c436-bcd6-4850-9de3-f9c922bb815a - PACKAGE_VERSION = 0.1 - -[Includes] - Include diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h deleted file mode 100644 index ec58cb9129442ec2d86b36e1993431acdfb3ea84..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h +++ /dev/null @@ -1,65 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#ifndef _PLATFORM_ARCH_H_ -#define _PLATFORM_ARCH_H_ - -#define MAX_SOCKET 2 -#define MAX_DIE 4 -#define MAX_DDRC 2 -#define MAX_NODE (MAX_SOCKET * MAX_DIE) -#define MAX_CHANNEL 4 -#define MAX_DIMM 3 -#define MAX_RANK_CH 12 -#define MAX_RANK_DIMM 4 -#define MAX_DIMM_SIZE 32 // In GB -// Max NUMA node number for each node type -#define MAX_NUM_PER_TYPE 8 - -#define RASC_BASE (0x5000) -/* configuration register for Rank statistical information */ -#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) -/* configuration register for Sparing level */ -#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) - -// for acpi -#define NODE_IN_SOCKET 2 -#define CORE_NUM_PER_SOCKET 32 -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10 -#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8 - -#define S1_BASE 0x40000000000 - -// -// ACPI table information used to initialize tables. -// -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64 ('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long -#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 -#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32 ('I','N','T','L') -#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 - -// A macro to initialise the common header part of EFI ACPI tables as defined by -// EFI_ACPI_DESCRIPTION_HEADER structure. -#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ - Signature, /* UINT32 Signature */ \ - sizeof (Type), /* UINT32 Length */ \ - Revision, /* UINT8 Revision */ \ - 0, /* UINT8 Checksum */ \ - { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ - EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ - EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ - EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ - EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ - } - -#endif - diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c deleted file mode 100644 index 6ec849abad81ffdf8ccd3694627e3b28061583dc..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c +++ /dev/null @@ -1,523 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ -* -**/ - -#include "Pptt.h" - -EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL; -EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL; - -EFI_ACPI_DESCRIPTION_HEADER mPpttHeader = - ARM_ACPI_HEADER ( - EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_DESCRIPTION_HEADER, - EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION - ); - -EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] = -{ - {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0, 0, 0, 0} -}; - -EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO]; - - -STATIC -VOID -InitCacheInfo ( - VOID - ) -{ - UINT8 Index; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes; - CSSELR_DATA CsselrData; - CCSIDR_DATA CcsidrData; - - for (Index = 0; Index < PPTT_CACHE_NO; Index++) { - CsselrData.Data = 0; - CcsidrData.Data = 0; - SetMem ( - &Type1Attributes, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES), - 0 - ); - - if (Index == 0) { //L1I - CsselrData.Bits.InD = 1; - CsselrData.Bits.Level = 0; - Type1Attributes.CacheType = 1; - } else if (Index == 1) { - Type1Attributes.CacheType = 0; - CsselrData.Bits.Level = Index - 1; - } else { - Type1Attributes.CacheType = 2; - CsselrData.Bits.Level = Index - 1; - } - - CcsidrData.Data = ReadCCSIDR (CsselrData.Data); - - if (CcsidrData.Bits.Wa == 1) { - Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE; - if (CcsidrData.Bits.Ra == 1) { - Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE; - } - } - - if (CcsidrData.Bits.Wt == 1) { - Type1Attributes.WritePolicy = 1; - } - DEBUG ((DEBUG_INFO, - "[Acpi PPTT] Level = %x!CcsidrData = %x!\n", - CsselrData.Bits.Level, - CcsidrData.Data)); - - mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE; - mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE); - mPpttCacheType1[Index].Reserved[0] = 0; - mPpttCacheType1[Index].Reserved[1] = 0; - mPpttCacheType1[Index].Flags.SizePropertyValid = 1; - mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1; - mPpttCacheType1[Index].Flags.AssociativityValid = 1; - mPpttCacheType1[Index].Flags.AllocationTypeValid = 1; - mPpttCacheType1[Index].Flags.CacheTypeValid = 1; - mPpttCacheType1[Index].Flags.WritePolicyValid = 1; - mPpttCacheType1[Index].Flags.LineSizeValid = 1; - mPpttCacheType1[Index].Flags.Reserved = 0; - mPpttCacheType1[Index].NextLevelOfCache = 0; - - if (Index != PPTT_CACHE_NO - 1) { - mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1; - mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1; - mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4)); - mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \ - mPpttCacheType1[Index].Associativity * \ - mPpttCacheType1[Index].NumberOfSets; - CopyMem ( - &mPpttCacheType1[Index].Attributes, - &Type1Attributes, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES) - ); - } else { - // L3 cache - mPpttCacheType1[Index].Size = 0x1000000; // 16m - mPpttCacheType1[Index].NumberOfSets = 0x2000; - mPpttCacheType1[Index].Associativity = 0x10; // CacheAssociativity16Way - SetMem ( - &mPpttCacheType1[Index].Attributes, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES), - 0x0A - ); - mPpttCacheType1[Index].LineSize = 0x80; // 128byte - } - } -} - -STATIC -EFI_STATUS -AddCoreTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo, - IN UINT32 ProcessorId - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; - UINT32 *PrivateResource; - UINT8 Index; - - if (*PpttTableLengthRemain < - (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Flags.AcpiProcessorIdValid = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID; - PpttType0->Parent= Parent; - PpttType0->AcpiProcessorId = ProcessorId; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - - *PpttTableLengthRemain -= (UINTN)PpttType0->Length; - PpttTable->Length += PpttType0->Length; - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - - // Add cache type structure - for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) { - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType1, - &mPpttCacheType1[Index], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) - ); - *PpttTableLengthRemain -= PpttType1->Length; - PpttTable->Length += PpttType1->Length; - } - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -AddClusterTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; - UINT32 *PrivateResource; - - if ((*PpttTableLengthRemain) < - (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Parent= Parent; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - - *PpttTableLengthRemain -= PpttType0->Length; - PpttTable->Length += PpttType0->Length; - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - - // Add cache type structure - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType1, - &mPpttCacheType1[2], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) - ); - *PpttTableLengthRemain -= PpttType1->Length; - PpttTable->Length += PpttType1->Length; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -AddScclTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; - UINT32 *PrivateResource; - - if (*PpttTableLengthRemain < - (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Parent= Parent; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - - *PpttTableLengthRemain -= PpttType0->Length; - PpttTable->Length += PpttType0->Length; - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - - // Add cache type structure - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType1, - &mPpttCacheType1[3], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) - ); - *PpttTableLengthRemain -= PpttType1->Length; - PpttTable->Length += PpttType1->Length; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -AddSocketTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2; - UINT32 *PrivateResource; - UINT8 Index; - - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Flags.PhysicalPackage = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID; - PpttType0->Parent= Parent; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - PpttTable->Length += PpttType0->Length; - - *PpttTableLengthRemain -= PpttType0->Length; - if (*PpttTableLengthRemain < ResourceNo * 4) { - return EFI_OUT_OF_RESOURCES; - } - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - DEBUG ((DEBUG_INFO, - "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n", - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID))); - - for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) { - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType2, - &mPpttSocketType2[Index], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID) - ); - *PpttTableLengthRemain -= PpttType2->Length; - PpttTable->Length += PpttType2->Length; - } - - return EFI_SUCCESS; -} - -STATIC -VOID -GetApic ( - IN EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable, - IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN UINT32 PpttTableLengthRemain, - IN UINT32 Index1 -) -{ - UINT32 IndexSocket, IndexSccl, IndexCluster, IndexCore; - UINT32 SocketOffset, ScclOffset, ClusterOffset; - UINT32 Parent = 0; - UINT32 ResourceNo = 0; - - // Get APIC data - for (IndexSocket = 0; IndexSocket < PPTT_SOCKET_NO; IndexSocket++) { - SocketOffset = 0; - for (IndexSccl = 0; IndexSccl < PPTT_SCCL_NO; IndexSccl++) { - ScclOffset = 0; - for (IndexCluster = 0; IndexCluster < PPTT_CLUSTER_NO; IndexCluster++) { - ClusterOffset = 0; - for (IndexCore = 0; IndexCore < PPTT_CORE_NO; IndexCore++) { - if (ApicTable->GicInterfaces[Index1].AcpiProcessorUid != Index1) { - // This processor is unusable - DEBUG ((DEBUG_ERROR, "[Acpi PPTT] Please check MADT table for UID!\n")); - return; - } - if ((ApicTable->GicInterfaces[Index1].Flags & BIT0) == 0) { - // This processor is unusable - Index1++; - continue; - } - - if (SocketOffset == 0) { - // Add socket0 for type0 table - ResourceNo = PPTT_SOCKET_COMPONENT_NO; - SocketOffset = PpttTable->Length; - Parent = 0; - AddSocketTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo - ); - } - if (ScclOffset == 0) { - // Add socket0sccl0 for type0 table - ResourceNo = 1; - ScclOffset = PpttTable->Length; - Parent = SocketOffset; - AddScclTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo - ); - } - if (ClusterOffset == 0) { - // Add socket0sccl0ClusterId for type0 table - ResourceNo = 1; - ClusterOffset = PpttTable->Length ; - Parent = ScclOffset; - AddClusterTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo - ); - } - - // Add socket0sccl0ClusterIdCoreId for type0 table - ResourceNo = 2; - Parent = ClusterOffset; - AddCoreTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo, - Index1 - ); - - Index1++; - } - } - } - } - return ; -} - -STATIC -VOID -PpttSetAcpiTable ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - UINTN AcpiTableHandle; - EFI_STATUS Status; - UINT8 Checksum; - EFI_ACPI_SDT_HEADER *Table; - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable; - EFI_ACPI_TABLE_VERSION TableVersion; - EFI_ACPI_DESCRIPTION_HEADER *PpttTable; - UINTN TableKey; - UINT32 Index0, Index1; - UINT32 PpttTableLengthRemain = 0; - - gBS->CloseEvent (Event); - - InitCacheInfo (); - - PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN); - gBS->CopyMem ( - (VOID *)PpttTable, - &mPpttHeader, - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - ); - PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER); - - for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) { - Status = mAcpiSdtProtocol->GetAcpiTable ( - Index0, - &Table, - &TableVersion, - &TableKey - ); - if (EFI_ERROR (Status)) { - break; - } - - // Find APIC table - if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) { - break; - } - - } - - if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) { - ApicTable = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *)Table; - Index1 = 0; - - GetApic (ApicTable, PpttTable, PpttTableLengthRemain, Index1); - - Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length); - PpttTable->Checksum = Checksum; - - AcpiTableHandle = 0; - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - PpttTable, - PpttTable->Length, - &AcpiTableHandle); - } - - FreePool (PpttTable); - return ; -} - -EFI_STATUS -EFIAPI -PpttEntryPoint( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_EVENT ReadyToBootEvent; - - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID **)&mAcpiTableProtocol); - ASSERT_EFI_ERROR (Status); - - Status = gBS->LocateProtocol ( - &gEfiAcpiSdtProtocolGuid, - NULL, - (VOID **)&mAcpiSdtProtocol); - ASSERT_EFI_ERROR (Status); - - Status = EfiCreateEventReadyToBootEx ( - TPL_NOTIFY, - PpttSetAcpiTable, - NULL, - &ReadyToBootEvent - ); - ASSERT_EFI_ERROR (Status); - - DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n")); - - return Status; -} diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h deleted file mode 100644 index 29b260d619c587935fd1a4c5d608474c3450a1bb..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ -* -**/ - -#ifndef _PPTT_H_ -#define _PPTT_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../D05AcpiTables/Hi1616Platform.h" - -#define PPTT_VENDOR_ID SIGNATURE_32('H', 'I', 'S', 'I') - -#define EFI_ACPI_MAX_NUM_TABLES 20 - -#define PPTT_TABLE_MAX_LEN 0x6000 -#define PPTT_SOCKET_NO 0x2 -#define PPTT_SCCL_NO 0x2 -#define PPTT_CLUSTER_NO 0x4 -#define PPTT_CORE_NO 0x4 -#define PPTT_SOCKET_COMPONENT_NO 0x1 -#define PPTT_CACHE_NO 0x4 - -typedef union { - struct { - UINT32 InD :1; - UINT32 Level :3; - UINT32 Reserved :28; - } Bits; - UINT32 Data; -} CSSELR_DATA; - -typedef union { - struct { - UINT32 LineSize :3; - UINT32 Associativity :10; - UINT32 NumSets :15; - UINT32 Wa :1; - UINT32 Ra :1; - UINT32 Wb :1; - UINT32 Wt :1; - } Bits; - UINT32 Data; -} CCSIDR_DATA; - -#endif // _PPTT_H_ - diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf deleted file mode 100644 index 8f5fff2b105fce258b5a770764f67613b65f1125..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf +++ /dev/null @@ -1,42 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ -* -**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = AcpiPptt - FILE_GUID = AAB14F90-DC2E-4f33-A594-C7894A5B412D - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = PpttEntryPoint - -[Sources.common] - Pptt.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - ArmLib - BaseMemoryLib - DebugLib - HobLib - UefiDriverEntryPoint - UefiRuntimeServicesTableLib - -[Protocols] - gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED - gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED - -[Depex] - gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c deleted file mode 100644 index 69ba0c43ffdf15fb60e9d042fd5968f69514710e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c +++ /dev/null @@ -1,102 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "Apei.h" -#include -#include "Bert.h" -#include "Einj.h" -#include "Erst.h" -#include "Hest.h" - -EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL; -EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL; -APEI_TRUSTED_FIRMWARE_STRUCTURE *mApeiTrustedfirmwareData; - -EFI_STATUS -EFIAPI -ApeiEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable -) -{ - EFI_STATUS Status; - ARM_SMC_ARGS SmcRegs = {0}; - UINTN Size = sizeof (OEM_CONFIG_DATA); - OEM_CONFIG_DATA SetupData; - - Status = gRT->GetVariable ( - OEM_CONFIG_NAME, - &gOemConfigGuid, - NULL, - &Size, - &SetupData - ); - if (EFI_ERROR (Status)) { - SetupData.EnRasSupport = 1; - DEBUG ((DEBUG_ERROR, "[%a]GetVariable %r.Get default variable value\n", - __func__, Status)); - } - if (!SetupData.EnRasSupport) { - return EFI_ABORTED; - } - if (PcdGet64 (PcdTrustedFirmwareEnable) == 0) { - return EFI_ABORTED; - } - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID**)&mAcpiTableProtocol); - if (EFI_ERROR (Status)) { - return Status; - } - Status = gBS->LocateProtocol ( - &gEfiAcpiSdtProtocolGuid, - NULL, - (VOID**)&mAcpiSdtProtocol); - if (EFI_ERROR (Status)) { - return Status; - } - Status = gBS->AllocatePool ( - EfiReservedMemoryType, - sizeof (APEI_TRUSTED_FIRMWARE_STRUCTURE), - (VOID**)&mApeiTrustedfirmwareData - ); - if (EFI_ERROR (Status)) { - return Status; - } - gBS->SetMem ( - mApeiTrustedfirmwareData, - sizeof (APEI_TRUSTED_FIRMWARE_STRUCTURE), - 0 - ); - Status = EFI_SUCCESS; - Status |= OemInitBertTable (ImageHandle); - Status |= OemInitHestTable (ImageHandle); - Status |= OemInitErstTable (); - Status |= OemInitEinjTable (); - // smc call - DEBUG ((DEBUG_INFO, "[%a]:[%dL]: %r\n", __func__, __LINE__, Status)); - if (Status == EFI_SUCCESS) { - SmcRegs.Arg0 = PRIVATE_ARM_SMC_ID_APEI; - SmcRegs.Arg1 = (UINTN)mApeiTrustedfirmwareData; - ArmCallSmc (&SmcRegs); - } - DEBUG ((DEBUG_INFO, "Acpi Apei init done.\n")); - return EFI_SUCCESS; -} - - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h deleted file mode 100644 index d5e4a5d4c93a9ea90aadb7d9520354896336b11a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -#ifndef _APEI_H_ -#define _APEI_H_ - -#include -#include -#include - -#define EFI_ACPI_MAX_NUM_TABLES 20 -#define PRIVATE_ARM_SMC_ID_APEI 0x83000100 -#define PRIVATE_ARM_SMC_ID_APEI_S 0x83000101 - -typedef struct { - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *HestCorrectedErrorGhesV2; - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *HestFatalErrorGhesV2; - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *HestRecoverableErrorGhesV2; - EFI_PHYSICAL_ADDRESS HestTableAddress; - EFI_PHYSICAL_ADDRESS EinjTableAddress; - EFI_PHYSICAL_ADDRESS EinjDataStruct; - VOID *ErstContext; -} APEI_TRUSTED_FIRMWARE_STRUCTURE; - -extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; -extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; -extern APEI_TRUSTED_FIRMWARE_STRUCTURE *mApeiTrustedfirmwareData; - - -#endif // _APEI_H_ diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf deleted file mode 100644 index b4dc87b6bcdbc14b8eb5dca65db9814903acbadd..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf +++ /dev/null @@ -1,53 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -[defines] - INF_VERSION = 0x0001001A - BASE_NAME = AcpiApei - FILE_GUID = E9570C39-EF68-4fc6-B921-C1954A87CCD2 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = ApeiEntryPoint - -[sources.common] - Apei.c - Bert/Bert.c - Einj/Einj.c - Erst/Erst.c - Hest/Hest.c - ErrorSource/Ghes.c - OemApeiHi1620.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - ArmSmcLib - BaseMemoryLib - DebugLib - HobLib - TimerLib - UefiDriverEntryPoint - UefiRuntimeServicesTableLib - -[Guids] - gOemConfigGuid - -[Protocols] - gEfiAcpiSdtProtocolGuid - gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED - -[Pcd] - gHisiTokenSpaceGuid.PcdCpldBaseAddress - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable - -[Depex] - gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c deleted file mode 100644 index d8368c42af495672862d6f5f874aaa5ad93ccd5e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c +++ /dev/null @@ -1,85 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "Bert.h" -#include "ErrorSource/Ghes.h" -#include -#include -#include -#include -#include - -VOID -BertSetAcpiTable ( - IN BERT_CONTEXT *Context -) -{ - UINTN AcpiTableHandle; - EFI_STATUS Status; - if (Context == NULL) { - return; - } - EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER* Bert = Context->BertHeader; - Bert->Header.Checksum = CalculateCheckSum8 ((UINT8*)(Bert), Bert->Header.Length); - AcpiTableHandle = 0; - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - Bert, - Bert->Header.Length, - &AcpiTableHandle); - ASSERT_EFI_ERROR (Status); - return; -} - -BOOLEAN -BertAddGenericErrorData ( - IN EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER *Bert, - IN EFI_CPER_SECTION_TYPE TypeOfErrorData, - IN VOID *GenericErrorData, - IN UINT32 SizeOfGenericErrorData, - IN ERROR_SEVERITY ErrorSeverity, - IN BOOLEAN Correctable -) -{ - BOOLEAN Status = ErrorBlockAddErrorData ( - (VOID*)Bert->BootErrorRegion, - Bert->BootErrorRegionLength, - TypeOfErrorData, - GenericErrorData, - SizeOfGenericErrorData, - ErrorSeverity, - Correctable); - return Status; -} - -EFI_STATUS -BertHeaderCreator ( - IN BERT_CONTEXT *Context, - IN UINT32 ErrorBlockSize -) -{ - if (Context == NULL) { - return EFI_INVALID_PARAMETER; - } - Context->BertHeader = AllocateZeroPool (sizeof (EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER)); - Context->Block = AllocateReservedZeroPool (ErrorBlockSize); - Context->BlockSize = ErrorBlockSize; - *Context->BertHeader = (EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER) { - ARM_ACPI_HEADER ( - EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE, - EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER, - EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION - ), - Context->BlockSize, - (UINT64)Context->Block - }; - return EFI_SUCCESS; -} - - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h deleted file mode 100644 index 015fb8156a39936e1f99e3d350f6fa2264594bff..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _BERT_H_ -#define _BERT_H_ - -#include "Apei.h" -#include - -typedef struct _BERT_CONTEXT { - EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER *BertHeader; - VOID *Block; - UINT32 BlockSize; -} BERT_CONTEXT; - -EFI_STATUS -OemInitBertTable ( - IN EFI_HANDLE ImageHandle -); -VOID -BertSetAcpiTable ( - IN BERT_CONTEXT *Context -); -EFI_STATUS -BertHeaderCreator ( - BERT_CONTEXT *Context, - UINT32 ErrorBlockSize -); - - -#endif // _BERT_H_ diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c deleted file mode 100644 index c71022c61955f827b8608695b3f1a18b355f08ad..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c +++ /dev/null @@ -1,343 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -#include "Einj.h" -#include -#include -#include -#include -#include -#include "OemApeiHi1620.h" -#include - - -EINJ_TABLE mEinj = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE, - EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER, - EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION - ), - sizeof (EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER), - 0x0, - { - 0x0, - 0x0, - 0x0 - }, - EINJ_ACTION_NO - }, - { - { - // 0 EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION - EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION, - EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE, - EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - EINJ_BEGIN_OPERATION_VALUE, - EINJ_WRITE_MASK - }, - { - // 1 EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE - EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE, - EFI_ACPI_6_0_EINJ_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - EINJ_READ_MASK - }, - { - // 2 EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE - EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE, - EFI_ACPI_6_0_EINJ_WRITE_REGISTER, - EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - EINJ_WRITE_MASK - }, - { - // 3 EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE - EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE, - EFI_ACPI_6_0_EINJ_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - 0xFFFFFFFF - }, - { - // 4 EFI_ACPI_6_0_EINJ_END_OPERATION - EFI_ACPI_6_0_EINJ_END_OPERATION, - EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE, - EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - EINJ_END_OPERATION_VALUE, - 0xFFFFFFFF - }, - { - // 5 EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION - EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION, - EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE, - EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 32, - 0, - EFI_ACPI_6_0_DWORD, - GPIO1_BASE + GPIO_INT_MASK //0x40070008//0x4d000F00//GPIO0_BASE + GPIO0_SWPORT_DR_OFFSET - }, - 0, - 0xFFFFFFFF //BIT0 - }, - { - // 6 EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS - EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS, - EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0x01, - 0x01 - }, - { - // 7 EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS - EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS, - EFI_ACPI_6_0_EINJ_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - 0x3 - }, - { - // 8 EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS - EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS, - EFI_ACPI_6_0_EINJ_WRITE_REGISTER, - EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - 0xFFFFFF - }, - { - // 9 EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS - EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS, - EFI_ACPI_6_0_EINJ_WRITE_REGISTER, - EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - 0xFFFFFF - } - } -}; - -EINJ_TRIGGER_ERROR_ACTION mEinjTriggerErrorAction = { - { - sizeof (EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE), - 0, - sizeof (EINJ_TRIGGER_ERROR_ACTION), - EINJ_TRIGGER_ERROR_ACTION_NO - }, - { - { - EFI_ACPI_6_0_EINJ_TRIGGER_ERROR, - EFI_ACPI_6_0_EINJ_NOOP, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_DWORD, - 0 - }, - 0, - 0 - } - } -}; - - -VOID -EinjSetAcpiTable ( - EINJ_CONTEXT *Context -) -{ - UINTN AcpiTableHandle; - EFI_STATUS Status; - UINT8 Checksum; - EFI_ACPI_SDT_HEADER *Table; - EFI_ACPI_TABLE_VERSION TableVersion; - UINTN TableKey; - UINTN i; - - Context->EINJ->EinjTableHeader.Header.Length = sizeof (EINJ_TABLE); - Checksum = CalculateCheckSum8 ( - (UINT8*)(Context->EINJ), - Context->EINJ->EinjTableHeader.Header.Length); - Context->EINJ->EinjTableHeader.Header.Checksum = Checksum; - AcpiTableHandle = 0; - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - Context->EINJ, - Context->EINJ->EinjTableHeader.Header.Length, - &AcpiTableHandle - ); - for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) { - Status = mAcpiSdtProtocol->GetAcpiTable (i, &Table, &TableVersion, &TableKey); - if (EFI_ERROR (Status)) { - break; - } - if (Table->Signature != EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE) { - continue; - } - mApeiTrustedfirmwareData->EinjTableAddress = (EFI_PHYSICAL_ADDRESS)Table; - mApeiTrustedfirmwareData->EinjDataStruct = (EFI_PHYSICAL_ADDRESS)Context->EinjData; - } - ASSERT_EFI_ERROR (Status) ; -} -//V2 -EFI_STATUS -EinjHeaderCreator ( - EINJ_CONTEXT *Context -) -{ - EFI_STATUS Status; - EINJ_DATA_STRUCTURE *EinjData = NULL; - Status = gBS->AllocatePool ( - EfiReservedMemoryType, - sizeof (EINJ_DATA_STRUCTURE), - (VOID**)&EinjData - ); - if (EFI_ERROR (Status)) { - return Status; - } - gBS->SetMem ( - EinjData, - sizeof (EINJ_DATA_STRUCTURE), - 0 - ); - - DEBUG ((DEBUG_INFO, "EINJ EinjData is at 0x%X,size =0x%x\n", - EinjData, sizeof (EINJ_DATA_STRUCTURE))); - EinjData->TriggerErrorActionTablePtr = - (EINJ_TRIGGER_ERROR_ACTION*)(&(EinjData->TriggerErrorActionTable)); - gBS->CopyMem ( - EinjData->TriggerErrorActionTablePtr, - &mEinjTriggerErrorAction, - sizeof (EINJ_TRIGGER_ERROR_ACTION)); - EinjData->OperationBegin = 0; - EinjData->ErrorType = 0; - EinjData->ErrorCapabilities = 0xFFF; - EinjData->BusyStatus = 0; - EinjData->CommandStatus = 0; - mEinj.EinjInstructionEntry[0].RegisterRegion.Address = - (UINT64)(&(EinjData->OperationBegin)); - mEinj.EinjInstructionEntry[1].RegisterRegion.Address = - (UINT64)(&(EinjData->TriggerErrorActionTablePtr)); - mEinj.EinjInstructionEntry[2].RegisterRegion.Address = - (UINT64)(&(EinjData->ErrorType)); - mEinj.EinjInstructionEntry[3].RegisterRegion.Address = - (UINT64)(&(EinjData->ErrorCapabilities)); - mEinj.EinjInstructionEntry[4].RegisterRegion.Address = - (UINT64)(&(EinjData->OperationBegin)); - mEinj.EinjInstructionEntry[6].RegisterRegion.Address = - (UINT64)(&(EinjData->BusyStatus)); - mEinj.EinjInstructionEntry[7].RegisterRegion.Address = - (UINT64)(&(EinjData->CommandStatus)); - mEinj.EinjInstructionEntry[8].RegisterRegion.Address = - (UINT64)(&(EinjData->ErrorTypeWithAddress)); - mEinj.EinjInstructionEntry[9].RegisterRegion.Address = - (UINT64)(&(EinjData->Timing)); - EinjData->ErrorTypeWithAddress.VendorErrorTypeOffset = - (UINT32)((UINTN)&(EinjData->VendorErrorTypeExtension) - - (UINTN)&(EinjData->ErrorTypeWithAddress)); - Context->EinjData = EinjData; - Context->EINJ = &mEinj; - Context->ExecuteOperationEntry = &mEinj.EinjInstructionEntry[5]; - Context->GetErrorTypeEntry = &mEinj.EinjInstructionEntry[3]; - return EFI_SUCCESS; -} - - -EFI_STATUS -EinjConfigErrorInjectCapability ( - EINJ_CONTEXT* Context, - UINT32 BitsSupportedErrorType -) -{ - EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY* KeyEntry; - UINT32* EinjCapablity; - - KeyEntry = Context->GetErrorTypeEntry; - EinjCapablity = (UINT32*)KeyEntry->RegisterRegion.Address; - *EinjCapablity = BitsSupportedErrorType; - KeyEntry->Value = BitsSupportedErrorType; - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h deleted file mode 100644 index 67a8c8a10867ebd2232e41fcbbb166d8f75f561e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h +++ /dev/null @@ -1,140 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _EINJ_H_ -#define _EINJ_H_ - -#include "Apei.h" - -#define EINJ_ACTION_NO 10 -#define EINJ_BEGIN_OPERATION_VALUE 0xFFFF -#define EINJ_END_OPERATION_VALUE 0 -#define EINJ_WRITE_MASK 0xFFFFFFFF -#define EINJ_READ_VALUE 0xFFFF -#define EINJ_READ_MASK 0xFFFFFFFF - -#define EINJ_TRIGGER_ERROR_ACTION_NO 1 - -#define EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08 -#define EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS 0x09 - - -extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; -extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; -extern APEI_TRUSTED_FIRMWARE_STRUCTURE *mApeiTrustedfirmwareData; - -// -// Error Type Definition -// -#define EINJ_PROCESSOR_CORRECTABLE BIT0 -#define EINJ_PROCESSOR_UNCORRECTABLE_NONFATAL BIT1 -#define EINJ_PROCESSOR_UNCORRECTABLE_FATAL BIT2 -#define EINJ_MEMORY_CORRECTABLE BIT3 -#define EINJ_MEMORY_UNCORRECTABLE_NONFATAL BIT4 -#define EINJ_MEMORY_UNCORRECTABLE_FATAL BIT5 -#define EINJ_PCIE_CORRECTABLE BIT6 -#define EINJ_PCIE_UNCORRECTABLE_NONFATAL BIT7 -#define EINJ_PCIE_UNCORRECTABLE_FATAL BIT8 -#define EINJ_PLATFORM_CORRECTABLE BIT9 -#define EINJ_PLATFORM_UNCORRECTABLE_NONFATAL BIT10 -#define EINJ_PLATFORM_UNCORRECTABLE_FATAL BIT11 -#define EINJ_VENDOR_DEFINED_ERROR_TYPE BIT31 - -#define EINJ_PROCESSOR_APIC_VALID BIT0 -#define EINJ_MEMORY_ADDRESS_VALID BIT1 -#define EINJ_PCIE_SBDF_VALID BIT2 - -/// -/// EINJ Table -/// -typedef struct { - EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER EinjTableHeader; - EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY EinjInstructionEntry[EINJ_ACTION_NO]; -} EINJ_TABLE; - -typedef struct { - EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE TriggerErrorHeader; - EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY ErrorInstructionEntry[EINJ_TRIGGER_ERROR_ACTION_NO]; -} EINJ_TRIGGER_ERROR_ACTION; - -typedef struct { - UINT32 Reserved: 8; - UINT32 Function: 3; - UINT32 Device: 5; - UINT32 PrimaryOrDeviceBus: 8; - UINT32 Segment: 8; -} EINJ_PCIE_SBDF; - -typedef struct { - UINT32 ErrorType; - UINT32 VendorErrorTypeOffset; - UINT32 Flags; - UINT32 ApicId; - UINT64 MemAddress; - UINT64 MemAddressRange; - EINJ_PCIE_SBDF PcieSBDF; -} EINJ_SET_ERROR_TYPE_WITH_ADDRESS; - -typedef struct { - UINT32 Length; - UINT32 SBDF; - UINT16 VendorId; - UINT16 DeviceId; - UINT8 RevId; - UINT8 Reserved[3]; -} EINJ_VENDOR_ERROR_TYPE; - -typedef struct { - UINT64 OperationBegin; - UINT64 ErrorType; - UINT64 ErrorCapabilities; - UINT64 BusyStatus; - UINT64 CommandStatus; - UINT64 Timing; - EINJ_TRIGGER_ERROR_ACTION *TriggerErrorActionTablePtr; - EINJ_SET_ERROR_TYPE_WITH_ADDRESS ErrorTypeWithAddress; - EINJ_VENDOR_ERROR_TYPE VendorErrorTypeExtension; - EINJ_TRIGGER_ERROR_ACTION TriggerErrorActionTable; -} EINJ_DATA_STRUCTURE; - -// V2 -typedef struct _EINJ_CONTEXT { - EINJ_TABLE *EINJ; - EINJ_DATA_STRUCTURE *EinjData; - EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY *GetErrorTypeEntry; - EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY *ExecuteOperationEntry; -} EINJ_CONTEXT; - - -EFI_STATUS -InitEinjTable(VOID); -// Version2 -EFI_STATUS -EinjConfigErrorInjectCapability( - EINJ_CONTEXT *Context, - UINT32 BitsSupportedErrorType -); -EFI_STATUS -EinjHeaderCreator( - EINJ_CONTEXT *Context -); -/***OEM***/ -EFI_STATUS -OemInitEinjTable(VOID); -EFI_STATUS -OemEinjConfigExecuteOperationEntry( - EINJ_CONTEXT *Context -); -VOID -EinjSetAcpiTable( - EINJ_CONTEXT *Context -); - - -#endif // _EINJ_H_ diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c deleted file mode 100644 index 1b079c2ae54cbf959a00e14885311a89f151700d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c +++ /dev/null @@ -1,324 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include "Ghes.h" -#include -#include - -#define READ_ACK_PRESERVE 0xFFFFFFFE -#define READ_ACK_WRITE 0x1 - -EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE* -ErrorBlockInitial ( - VOID *Block, - UINT32 Severity -) -{ - EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE* BlockHeader = Block; - BlockHeader->BlockStatus = (EFI_ACPI_6_1_ERROR_BLOCK_STATUS) {0, 0, 0, 0, 0}; - BlockHeader->RawDataOffset = 0; - BlockHeader->RawDataLength = 0; - BlockHeader->DataLength = 0; - BlockHeader->ErrorSeverity = Severity; - return BlockHeader; -} - - -BOOLEAN -ErrorBlockUpdateStatusStructure ( - VOID *ErrorBlock -) -{ - if (ErrorBlock == NULL) { - return FALSE; - } - IN EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE *BlockHeader = ErrorBlock; - VOID *EntriesBegin = ErrorBlock + sizeof (EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE); - if (BlockHeader->BlockStatus.ErrorDataEntryCount == 0) { - gBS->SetMem (EntriesBegin, BlockHeader->DataLength, 0); - BlockHeader->RawDataLength = 0; - BlockHeader->RawDataOffset = 0; - BlockHeader->DataLength = 0; - } - return TRUE; -} - - -BOOLEAN -ErrorBlockAddErrorData ( - IN VOID *ErrorBlock, - IN UINT32 MaxBlockLength, - IN EFI_CPER_SECTION_TYPE TypeOfErrorData, - IN VOID *GenericErrorData, - IN UINT32 SizeOfGenericErrorData, - IN ERROR_SEVERITY ErrorSeverity, - IN BOOLEAN Correctable -) -{ - if (ErrorBlock == NULL || GenericErrorData == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]Invalid Param \n", __func__, __LINE__)); - return FALSE; - } - EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE* Entry; - EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE* BlockHeader = ErrorBlock; - EFI_ACPI_6_1_ERROR_BLOCK_STATUS* BlockStatus = &BlockHeader->BlockStatus; - (VOID)ErrorBlockUpdateStatusStructure (ErrorBlock); - UINT32 ExpectedNewDataLength = BlockHeader->DataLength + - sizeof (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE) + - SizeOfGenericErrorData; - if (sizeof (EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE) + ExpectedNewDataLength > - MaxBlockLength) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]Out of BlockSize \n", __func__, __LINE__)); - return FALSE; - } - // guid - EFI_GUID Guid; - switch (TypeOfErrorData) { - case PROCESSOR_GENERIC: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PROCESSOR_GENERIC_GUID; - break; - case PROCESSOR_ARM: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_ARM_GUID; - break; - case PLATFORM_MEMORY: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PLATFORM_MEMORY_GUID; - break; - case PLATFORM_MEMORY2: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PLATFORM_MEMORY2_GUID; - break; - case PCIE_EXPRESS: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PCIE_GUID; - break; - case FIRMWARE_ERROR: - Guid = (EFI_GUID)EFI_ERROR_SECTION_FW_ERROR_RECORD_GUID; - break; - case PCI_BUS: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PCI_PCIX_BUS_GUID; - break; - case PCI_COMPONENT: - Guid = (EFI_GUID)EFI_ERROR_SECTION_PCI_DEVICE_GUID; - break; - default: - return FALSE; - } - //Block Status - if (Correctable == TRUE) { - if (BlockStatus->CorrectableErrorValid == 0) { - BlockStatus->CorrectableErrorValid = 1; - } else { - BlockStatus->MultipleCorrectableErrors = 1; - } - } else { - if (BlockStatus->UncorrectableErrorValid == 0) { - BlockStatus->UncorrectableErrorValid = 1; - } else { - BlockStatus->MultipleUncorrectableErrors = 1; - } - } - BlockStatus->ErrorDataEntryCount++; - // Entry - Entry = (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE*)(ErrorBlock + - sizeof (EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE) + - BlockHeader->DataLength); - gBS->SetMem (Entry, sizeof (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE), 0); - gBS->CopyMem (&Entry->SectionType, &Guid, sizeof (EFI_GUID)); - Entry->ErrorSeverity = ErrorSeverity; - Entry->Revision = EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_REVISION; - Entry->ErrorDataLength = SizeOfGenericErrorData; - VOID* GenericErrorDataFollowEntry = (VOID*)Entry + - sizeof (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE); - gBS->CopyMem ( - GenericErrorDataFollowEntry, - GenericErrorData, - SizeOfGenericErrorData); - // BlockHeader - BlockHeader->RawDataOffset = 0; - BlockHeader->RawDataLength = 0; - BlockHeader->DataLength = ExpectedNewDataLength; - return TRUE; -} - -VOID -GhesV2Initial ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2, - UINT32 BlockLength -) -{ - if (GhesV2 == NULL) { - return; - } - *GhesV2 = (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE) { - .Type = EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_VERSION_2, - .SourceId = 0, - .RelatedSourceId = 0xFFFF, - .Flags = 0, - .Enabled = 1, - .NumberOfRecordsToPreAllocate = 1,//ERROR BLOCK - .MaxSectionsPerRecord = 1,// Num Entries(section) - .MaxRawDataLength = BlockLength, // Max Size Of a Raw Data - .ErrorStatusAddress = { - .AddressSpaceId = EFI_ACPI_6_1_SYSTEM_MEMORY, - .RegisterBitWidth = 64, - .RegisterBitOffset = 0, - .AccessSize = EFI_ACPI_6_1_QWORD, - .Address = 0 - }, - .NotificationStructure = { - .Type = EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV, - .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE), - .ConfigurationWriteEnable = {0, 0, 0, 0, 0, 0, 0} , - .PollInterval = 0, - .Vector = 0, - .SwitchToPollingThresholdValue = 0, - .SwitchToPollingThresholdWindow = 0, - .ErrorThresholdValue = 0, - .ErrorThresholdWindow = 0 - }, - .ErrorStatusBlockLength = BlockLength, - .ReadAckRegister = { - .AddressSpaceId = EFI_ACPI_6_1_SYSTEM_MEMORY, - .RegisterBitWidth = 64, - .RegisterBitOffset = 0, - .AccessSize = EFI_ACPI_6_1_QWORD, - .Address = 0 - }, - .ReadAckPreserve = READ_ACK_PRESERVE, - .ReadAckWrite = READ_ACK_WRITE - }; - return; -} - -VOID -GhesV2AddNotification ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *This, - UINT8 Type -) -{ - This->NotificationStructure = (EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE) { - .Type = Type, - .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE), - .ConfigurationWriteEnable = { - .Type = 0, - .PollInterval = 1, - .SwitchToPollingThresholdValue = 1, - .SwitchToPollingThresholdWindow = 1, - .ErrorThresholdValue = 1, - .ErrorThresholdWindow = 1 - }, - .PollInterval = 20, - .Vector = 0, - .SwitchToPollingThresholdValue = 0, - .SwitchToPollingThresholdWindow = 0, - .ErrorThresholdValue = 0, - .ErrorThresholdWindow = 0 - }; - return; -} - -EFI_STATUS -GhesV2LinkErrorBlock ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2, - GHES_REGISTER *Register, - VOID *ErrorBlock -) -{ - if (ErrorBlock == NULL || Register == NULL || GhesV2 == NULL) { - return EFI_INVALID_PARAMETER; - } - - Register->ErrorStatusBlockAddress = (UINTN)ErrorBlock; - GhesV2->ErrorStatusAddress.Address = (UINTN)&(Register->ErrorStatusBlockAddress); - Register->AckRegister = READ_ACK_WRITE; - GhesV2->ReadAckRegister.Address = (UINT64)&(Register->AckRegister); - return EFI_SUCCESS; -} - - -VOID GhesV1Initial ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *GhesV1, - UINT32 BlockLength -) -{ - if (GhesV1 == NULL) { - return; - } - *GhesV1 = (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE) { - .Type = EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR, - .SourceId = 0, - .RelatedSourceId = 0xFFFF, - .Flags = 0, - .Enabled = 1, - .NumberOfRecordsToPreAllocate = 1,//ERROR BLOCK - .MaxSectionsPerRecord = 1,// Num Entries(section) - .MaxRawDataLength = BlockLength, // Max Size Of a Raw Data - .ErrorStatusAddress = { - .AddressSpaceId = EFI_ACPI_6_1_SYSTEM_MEMORY, - .RegisterBitWidth = 64, - .RegisterBitOffset = 0, - .AccessSize = EFI_ACPI_6_1_QWORD, - .Address = 0 - }, - .NotificationStructure = { - .Type = EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV, - .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE), - .ConfigurationWriteEnable = {0, 0, 0, 0, 0, 0, 0}, - .PollInterval = 0, - .Vector = 0, - .SwitchToPollingThresholdValue = 0, - .SwitchToPollingThresholdWindow = 0, - .ErrorThresholdValue = 0, - .ErrorThresholdWindow = 0 - }, - .ErrorStatusBlockLength = BlockLength, - }; - return; -} - -VOID -GhesV1AddNotification ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This, - UINT8 Type -) -{ - This->NotificationStructure = (EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE) { - .Type = Type, - .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE), - .ConfigurationWriteEnable = { - .Type = 0, - .PollInterval = 1, - .SwitchToPollingThresholdValue = 1, - .SwitchToPollingThresholdWindow = 1, - .ErrorThresholdValue = 1, - .ErrorThresholdWindow = 1 - }, - .PollInterval = 20, - .Vector = 0, - .SwitchToPollingThresholdValue = 0, - .SwitchToPollingThresholdWindow = 0, - .ErrorThresholdValue = 0, - .ErrorThresholdWindow = 0 - }; - return; -} - -EFI_STATUS GhesV1LinkErrorBlock ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This, - UINT64 *ptrBlockAddress, - VOID *ErrorBlock -) -{ - if (ErrorBlock == NULL || ptrBlockAddress == NULL || This == NULL) { - return EFI_INVALID_PARAMETER; - } - *ptrBlockAddress = (UINTN)ErrorBlock; - This->ErrorStatusAddress.Address = (UINTN) ptrBlockAddress; - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h deleted file mode 100644 index 86854557a9128e29c9f560d763efe071107f8bf1..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h +++ /dev/null @@ -1,104 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef GENERIC_HARDWARE_ERROR_SOURCE -#define GENERIC_HARDWARE_ERROR_SOURCE -#include "Apei.h" - - -typedef struct { - UINT64 AckRegister; - UINT64 ErrorStatusBlockAddress; -} GHES_REGISTER; - -typedef enum { - PROCESSOR_GENERIC = 0, - PROCESSOR_IA32_X64 = 1, - PROCESSOR_IPF = 2, - PROCESSOR_ARM = 3, - PLATFORM_MEMORY = 4, - PLATFORM_MEMORY2 = 5, - PCIE_EXPRESS = 6, - FIRMWARE_ERROR = 7, - PCI_BUS = 8, - PCI_COMPONENT = 9 -} EFI_CPER_SECTION_TYPE; -typedef enum { - RECOVERABLE = 0, - FATAL = 1, - CORRECTED = 2, - NONE = 3 -} ERROR_SEVERITY; - -EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE* -ErrorBlockInitial( - VOID *Block, - UINT32 Severity -); -BOOLEAN ErrorBlockAddErrorData ( - IN VOID *ErrorBlock, - IN UINT32 MaxBlockLength, - IN EFI_CPER_SECTION_TYPE TypeOfErrorData, - IN VOID *GenericErrorData, - IN UINT32 SizeOfGenericErrorData, - IN ERROR_SEVERITY ErrorSeverity, - IN BOOLEAN Correctable -); -BOOLEAN ErrorBlockAddErrorData ( - IN VOID *ErrorBlock, - IN UINT32 MaxBlockLength, - IN EFI_CPER_SECTION_TYPE TypeOfErrorData, - IN VOID *GenericErrorData, - IN UINT32 SizeOfGenericErrorData, - IN ERROR_SEVERITY ErrorSeverity, - IN BOOLEAN Correctable -); - -VOID -GhesV2Initial ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2, - UINT32 BlockLength -); - -/** -@param type - one of HARDWARE_ERROR_NOTIFICATION Type, GSIV For ARM,and SCI for X86, - Notice: Windows OS hadn't support to GSIV, 20171026 -*/ -VOID -GhesV2AddNotification ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *This, - UINT8 Type -); - - -EFI_STATUS -GhesV2LinkErrorBlock ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2, - GHES_REGISTER *Register, - VOID *ErrorBlock -); -VOID -GhesV1Initial ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *GhesV1, - UINT32 BlockLength -); -VOID -GhesV1AddNotification ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This, - UINT8 Type -); -EFI_STATUS -GhesV1LinkErrorBlock ( - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This, - UINT64 *ptrBlockAddress, - VOID *ErrorBlock -); - - -#endif diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c deleted file mode 100644 index a2537bb84a894f3e1178e8d29d1e710e44f892aa..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c +++ /dev/null @@ -1,368 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -#include "Erst.h" -#include -#include -#include -#include -#include - -typedef struct { - EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER ErstTableHeader; - EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY ErstInstructionEntry[ERST_ACTION_NO]; -} ERST_TABLE; - -ERST_TABLE mErst = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE, - EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER, - EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION - ), - sizeof (EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER), - { - 0x0, - 0x0, - 0x0, - 0x0 - }, - ERST_ACTION_NO, - }, - { - { - // 0 EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION - EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION, - EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - ERST_BEGIN_WRITE_VALUE, - ERST_BEGIN_WRITE_MASK - }, - { - // 1 EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION - EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION, - EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - ERST_BEGIN_READ_VALUE, - ERST_BEGIN_READ_MASK - }, - { - // 2 EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION - EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION, - EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - ERST_BEGIN_CLEAR_VALUE, - ERST_BEGIN_CLEAR_MASK - }, - { - // 3 EFI_ACPI_6_0_ERST_END_OPERATION - EFI_ACPI_6_0_ERST_END_OPERATION, - EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE, - EFI_ACPI_6_0_ERST_PRESERVE_REGISTER, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - ERST_END_OPERATION_VALUE, - ERST_END_OPERATION_MASK - }, - { - // 4 EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET - EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET, - EFI_ACPI_6_0_ERST_WRITE_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // 5 EFI_ACPI_6_0_ERST_EXECUTE_OPERATION - EFI_ACPI_6_0_ERST_EXECUTE_OPERATION, - EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_DWORD, - 0x94730000 - }, - 0x0002, - 0x0002 - }, - { - // 6 EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS - EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS, - EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0x00000001, - 0x00000001 - }, - { - // 7 EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS - EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS, - EFI_ACPI_6_0_ERST_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // 8 EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER - EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER, - EFI_ACPI_6_0_ERST_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // 9 EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER - EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER, - EFI_ACPI_6_0_ERST_WRITE_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // A EFI_ACPI_6_0_ERST_GET_RECORD_COUNT - EFI_ACPI_6_0_ERST_GET_RECORD_COUNT, - EFI_ACPI_6_0_ERST_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // B EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION - EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION, - EFI_ACPI_6_0_ERST_WRITE_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // C RESERVED - 0x0C, - EFI_ACPI_6_0_ERST_WRITE_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // D EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE - EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE, - EFI_ACPI_6_0_ERST_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // E EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH - EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH, - EFI_ACPI_6_0_ERST_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - }, - { - // F EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES - EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES, - EFI_ACPI_6_0_ERST_READ_REGISTER, - 0, - 0, - { - EFI_ACPI_6_0_SYSTEM_MEMORY, - 64, - 0, - EFI_ACPI_6_0_QWORD, - 0 - }, - 0, - ERST_MASK - } - } -}; - -VOID -ErstSetAcpiTable ( - ERST_BOOT_CONTEXT *Context -) -{ - UINTN AcpiTableHandle; - EFI_STATUS Status; - UINT8 Checksum; - mErst.ErstTableHeader.Header.Length = sizeof (ERST_TABLE); - Checksum = CalculateCheckSum8 ((UINT8*)(&mErst), mErst.ErstTableHeader.Header.Length); - mErst.ErstTableHeader.Header.Checksum = Checksum; - AcpiTableHandle = 0; - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - &mErst, - mErst.ErstTableHeader.Header.Length, - &AcpiTableHandle - ); - ASSERT_EFI_ERROR (Status) ; -} - -EFI_STATUS -ErstHeaderCreator ( - ERST_BOOT_CONTEXT *Context, - UINT64 BufferSize,//ERST_DATASTORE_SIZE - VOID *NvRamAddrRange, - UINT64 NvRamAllRecordLength, - UINT64 NvRamAddrRangeLength -) -{ - EFI_STATUS Status = EFI_SUCCESS; - ERST_RT_CONTEXT *ErstRtCtx; - // - ErstRtCtx = AllocateReservedZeroPool (sizeof (ERST_RT_CONTEXT)); - ErstRtCtx->Operation = ERST_END_OPERATION; - ErstRtCtx->RecordOffset = 0; - ErstRtCtx->BusyStatus = 0; - ErstRtCtx->CommandStatus = 0; - ErstRtCtx->KeyRecordId = 0; - ErstRtCtx->MaxTimeOfExecuteOperation = MAX_UINT64; - ErstRtCtx->RecordCount = 0; - ErstRtCtx->ErrorLogAddressRange = (UINT64)AllocateReservedZeroPool (BufferSize); - ErstRtCtx->ErrorLogAddressRangeLength = BufferSize; - ErstRtCtx->ErrorLogAttributes = 0; - ErstRtCtx->NvRamLogAddrRange = NvRamAddrRange; - ErstRtCtx->NvRamLogAddrRangeLength = NvRamAddrRangeLength; - ErstRtCtx->NvRamRecordOffset = 0; - ErstRtCtx->NvRamNextVallidRecordId = MAX_UINT64; - ErstRtCtx->NvRamNextValidRecordOffset = 0; - ErstRtCtx->NvRamAllRecordLength = NvRamAllRecordLength; - mErst.ErstInstructionEntry[0].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation)); - mErst.ErstInstructionEntry[1].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation)); - mErst.ErstInstructionEntry[2].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation)); - mErst.ErstInstructionEntry[3].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation)); - mErst.ErstInstructionEntry[4].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->RecordOffset)); - mErst.ErstInstructionEntry[6].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->BusyStatus)); - mErst.ErstInstructionEntry[7].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->CommandStatus)); - mErst.ErstInstructionEntry[8].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->NvRamNextVallidRecordId)); - mErst.ErstInstructionEntry[9].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->KeyRecordId)); - mErst.ErstInstructionEntry[10].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->RecordCount)); - mErst.ErstInstructionEntry[11].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->DummyWrite)); - mErst.ErstInstructionEntry[12].RegisterRegion.Address = 0; - mErst.ErstInstructionEntry[13].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->ErrorLogAddressRange)); - mErst.ErstInstructionEntry[14].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->ErrorLogAddressRangeLength)); - mErst.ErstInstructionEntry[15].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->ErrorLogAttributes)); - Context->ErstHeader = (EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER*)&mErst; - Context->ExecuteOperationEntry = &(mErst.ErstInstructionEntry[5]); - Context->GetErrorLogAddrRangeAttributes = &(mErst.ErstInstructionEntry[15]); - Context->Rt = ErstRtCtx; - return Status; -}; - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h deleted file mode 100644 index f1c830e401cef4fcd92ddbf68b27ee7afe079d98..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h +++ /dev/null @@ -1,134 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _ERST_H_ -#define _ERST_H_ - -#include "Apei.h" - -#define ERST_STATUS_SUCCESS EFI_ACPI_6_1_ERST_STATUS_SUCCESS -#define ERST_STATUS_NOT_ENOUGH_SPACE EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE -#define ERST_STATUS_HARDWARE_NOT_AVAILABLE EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE -#define ERST_STATUS_FAILED EFI_ACPI_6_1_ERST_STATUS_FAILED -#define ERST_STATUS_RECORD_STORE_EMPTY EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY -#define ERST_STATUS_RECORD_NOT_FOUND EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND - -#define ERST_BEGIN_WRITE_VALUE 0x01 -#define ERST_BEGIN_WRITE_MASK 0xFFFFFFFFFFFFFFFF -#define ERST_BEGIN_READ_VALUE 0x02 -#define ERST_BEGIN_READ_MASK 0xFFFFFFFFFFFFFFFF -#define ERST_BEGIN_CLEAR_VALUE 0x03 -#define ERST_BEGIN_CLEAR_MASK 0xFFFFFFFFFFFFFFFF -#define ERST_END_OPERATION_VALUE 0x04 -#define ERST_END_OPERATION_MASK 0xFFFFFFFFFFFFFFFF -#define ERST_MASK 0xFFFFFFFFFFFFFFFF - -#define ERST_BEGIN_WRITE_OPERATION EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION -#define ERST_BEGIN_READ_OPERATION EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION -#define ERST_BEGIN_CLEAR_OPERATION EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION -#define ERST_END_OPERATION EFI_ACPI_6_1_ERST_END_OPERATION -#define ERST_BEGIN_DUMMY_WRITE_OPERATION EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION - -#define ERST_ACTION_NO 16 - -#define ERST_RECORD_FREE 0x00 -#define ERST_RECORD_INUSE 0x01 - -#define ERST_RECORD_STORE_IN_NVRAM 0 -#define ERST_RECORD_STORE_IN_MEM 1 -#define ERST_RECORD_STORE_IN_SPI_FLASH 2 - -#define ERST_LOG_ATTR_NVRAM 0x02 - -typedef struct { - UINT64 OperationId; - UINT64 RecordOffset; - UINT64 BusyStatus; - UINT64 CommandStatus; - UINT64 GetRecordId; - UINT64 SetRecordId; - UINT64 RecordCount; - UINT64 DummyWrite; - UINT64 Reserved; - UINT64 ErrorLogAddrRange; - UINT64 ErrorLogAddrRangeLength; - UINT64 ErrorLogAttributes; - UINT64 NvRamLogAddrNext; - UINT64 NvRamLogSizeRemain; -} ERST_DATA_STRUCTURE; - -typedef struct { - UINT16 Signature; - UINT16 Data0; - UINT16 Data1; - UINT8 Data2; - UINT8 Attributes; //0: free -} ERST_ERROR_RECORD_INFO; - -/// -/// ERST Table -/// - - - -typedef struct _ERST_CONTEXT { - UINT64 Operation; // WRITE,READ,CLEAR,END, - UINT64 DummyWrite; //DUMMY_WRITE_OPEATION - UINT64 RecordOffset; // Offset form the buffer(error log adress range) - UINT32 BusyStatus; - UINT32 CommandStatus; - UINT64 KeyRecordId; //OS Set the Record ID To Read/Write/Search - UINT64 MaxTimeOfExecuteOperation; - UINT64 RecordCount; // Num of Record In NVRAM - UINT64 ErrorLogAddressRange; // Address Of Range Top - UINT64 ErrorLogAddressRangeLength; // Address Of Range Top - UINT64 ErrorLogAttributes; - VOID *NvRamLogAddrRange; - UINT64 NvRamLogAddrRangeLength; - UINT64 NvRamRecordOffset; - UINT64 NvRamNextVallidRecordId; //Get RecordId entry - UINT64 NvRamNextValidRecordOffset; - UINT64 NvRamAllRecordLength; -} ERST_RT_CONTEXT; - -typedef struct _ERST_BOOT_CONTEXT { - EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER *ErstHeader; - EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY *ExecuteOperationEntry; - EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY *GetErrorLogAddrRangeAttributes; - ERST_RT_CONTEXT *Rt; -} ERST_BOOT_CONTEXT; - -extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; -extern APEI_TRUSTED_FIRMWARE_STRUCTURE *mApeiTrustedfirmwareData; - -EFI_STATUS -ErstHeaderCreator( - ERST_BOOT_CONTEXT *Context, - UINT64 BufferSize,//ERST_DATASTORE_SIZE - VOID *NvRamAddrRange, - UINT64 NvRamAllRecordLength, - UINT64 NvRamAddrRangeLength -); - -/***OEM***/ -EFI_STATUS -OemInitErstTable (VOID); - -EFI_STATUS -OemErstConfigExecuteOperationEntry ( - ERST_BOOT_CONTEXT *Context -); - -VOID -ErstSetAcpiTable ( - ERST_BOOT_CONTEXT *Context -); - - -#endif // _ERST_H_ diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c deleted file mode 100644 index 08213ace37c7b780166f788462ac03de3d99edcf..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c +++ /dev/null @@ -1,112 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include "ErrorSource/Ghes.h" -#include "Hest.h" -#include -#include -#include -#include -#include -#include - -EFI_STATUS HestAddErrorSourceDescriptor ( - IN OUT HEST_CONTEXT *Context, - IN VOID *ErrorSourceDescriptor, - IN UINT32 SizeOfDescriptor -) -{ - UINT16 *pSourceId; - VOID *Descriptor; - EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER *HestHeader; - - if ((Context == NULL) || (ErrorSourceDescriptor == NULL)) { - return EFI_INVALID_PARAMETER; - } - HestHeader = Context->HestHeader; - if (HestHeader->Header.Length + SizeOfDescriptor > Context->OccupiedMemorySize) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: Hest Size Too small\n", __func__, __LINE__)); - return EFI_BUFFER_TOO_SMALL; - } - Descriptor = (UINT8*)HestHeader + HestHeader->Header.Length; - gBS->CopyMem ((VOID*)Descriptor , ErrorSourceDescriptor, SizeOfDescriptor); - pSourceId = Descriptor + sizeof (UINT16); - *pSourceId = HestHeader->ErrorSourceCount; - HestHeader->Header.Length += SizeOfDescriptor; - HestHeader->ErrorSourceCount++; - Context->KeyErrorSource = Descriptor; - return EFI_SUCCESS; -} - -VOID -HestSetAcpiTable ( - IN HEST_CONTEXT *Context -) -{ - UINTN AcpiTableHandle; - EFI_STATUS Status; - UINT8 Checksum; - EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER *HestHeader; - EFI_ACPI_SDT_HEADER *Table; - EFI_ACPI_TABLE_VERSION TableVersion; - UINTN TableKey; - UINT32 Index; - if (Context == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: ERROR\n", __func__, __LINE__)); - return; - } - - HestHeader = Context->HestHeader; - Checksum = CalculateCheckSum8 ((UINT8*)(HestHeader), HestHeader->Header.Length); - HestHeader->Header.Checksum = Checksum; - AcpiTableHandle = 0; - // see AcpiTableProtocol.c InstallAcpiTable - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - HestHeader, - HestHeader->Header.Length, - &AcpiTableHandle); - for (Index = 0; Index < EFI_ACPI_MAX_NUM_TABLES; Index++) { - Status = mAcpiSdtProtocol->GetAcpiTable (Index, &Table, &TableVersion, &TableKey); - if (EFI_ERROR (Status)) { - break; - } - if (Table->Signature != EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE) { - continue; - } - mApeiTrustedfirmwareData->HestTableAddress = (EFI_PHYSICAL_ADDRESS)Table; - DEBUG ((DEBUG_INFO, "Acpi HestSetAcpiTable Table = 0x%x.\n", (EFI_PHYSICAL_ADDRESS)Table)); - } - DEBUG ((DEBUG_INFO, "[%a]:[%dL]:OUT %llx, IN %llx \n", __func__, __LINE__, - AcpiTableHandle, Context->HestHeader)); - return; -} - -EFI_STATUS -HestHeaderCreator ( - HEST_CONTEXT *Context, - UINT32 PreAllocatedHestSize -) -{ - if (PreAllocatedHestSize < sizeof (EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER)) { - return EFI_BUFFER_TOO_SMALL; - } - Context->HestHeader = AllocateReservedZeroPool (PreAllocatedHestSize); - *Context->HestHeader = (EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER) { - ARM_ACPI_HEADER ( - EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE, - EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER, - EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION - ), - 0x0 - }; - Context->KeyErrorSource = Context->HestHeader + 1; - Context->OccupiedMemorySize = PreAllocatedHestSize; - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h deleted file mode 100644 index 8bed751689fa6f7c6fd480a251a53f46be0fac5b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h +++ /dev/null @@ -1,53 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _HEST_H_ -#define _HEST_H_ - -#include "Apei.h" - - -typedef struct _HEST_CONTEXT { - EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER *HestHeader; // pointer to hest header - UINT32 OccupiedMemorySize; // allocated memory size for hest - VOID *KeyErrorSource; // key error source, valtile -} HEST_CONTEXT; - -EFI_STATUS -HestAddErrorSourceDescriptor ( - IN OUT HEST_CONTEXT *Context, - IN VOID *ErrorSourceDescriptor, - IN UINT32 SizeOfDescriptor -); -VOID -HestSetAcpiTable ( - IN HEST_CONTEXT *Context -); -EFI_STATUS -HestHeaderCreator ( - HEST_CONTEXT *Context, - UINT32 PreAllocatedHestSize -); - -/** -* OEM Interface declaration -* 1.Interface is not realized default -* 2.OEM should implement this interface -*/ -extern -VOID -OemHestInitialNotification (VOID); - -extern -EFI_STATUS -OemInitHestTable( - IN EFI_HANDLE ImageHandle -); - -#endif // _HEST_H_ diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c deleted file mode 100644 index 1316794f0e66f9f2e6107cd08e2f35c335b68dce..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c +++ /dev/null @@ -1,331 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include - -#include "Bert/Bert.h" -#include "Einj/Einj.h" -#include "ErrorSource/Ghes.h" -#include "Erst/Erst.h" -#include "Hest/Hest.h" -#include "OemApeiHi1620.h" - -VOID -GpioCombInit ( - UINTN Base, - UINT32 Pin -) -{ - UINT32 Val = MmioRead32 (Base + GPIO_INT_MASK); - MmioWrite32 (Base + GPIO_INT_MASK, Val | Pin); - Val = MmioRead32 (Base + GPIO_INT_EN); - MmioWrite32 (Base + GPIO_INT_EN, Val | Pin); - Val = MmioRead32 (Base + GPIO_SWPORT_DDR); - MmioWrite32 (Base + GPIO_SWPORT_DDR, Val & (~Pin)); - Val = MmioRead32 (Base + GPIO_INT_TYPE); - MmioWrite32 (Base + GPIO_INT_TYPE, Val & (~Pin)); - Val = MmioRead32 (Base + GPIO_INT_POLARITY); - MmioWrite32 (Base + GPIO_INT_POLARITY, Val | Pin); - Val = MmioRead32 (Base + GPIO_LS_SYNC); - MmioWrite32 (Base + GPIO_LS_SYNC, Val & (~Pin)); - MmioWrite32 (Base + GPIO_INT_COMB, 1); - return; -} -/************************************************ -*************** HEST *************** -************************************************/ - -/***************************************************************************** -* @param EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE* GhesV2,Vector of GhesV2 -* @param UINT8 NumOfGhesV2 -* @param_out -* @retval EFI_STATUS -*****************************************************************************/ -EFI_STATUS -GhesV2ContextForHest ( - IN EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE GhesV2[MAX_GHES], - IN UINT8 NumOfGhesV2 -) -{ - // ensuce the size is expected - if ((GhesV2 == NULL) || (NumOfGhesV2 != MAX_GHES)) { - return EFI_INVALID_PARAMETER; - } - - UINT8 NumOfBlockPerGhes = 1; - UINT8 Iter = 0; - UINT32 BlockMemorySize; - UINT32 ErrorSeverityArray[MAX_GHES] = { - EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE, - EFI_ACPI_6_2_ERROR_SEVERITY_FATAL, - EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED}; - VOID *ErrorBlockHead; - VOID *ErrorBlock; - VOID *BlockMemory; - GHES_REGISTER *GhesRegisters; - EFI_STATUS Status = EFI_SUCCESS; - - BlockMemorySize = MAX_GHES * - (sizeof (GHES_REGISTER) + NumOfBlockPerGhes * GENERIC_HARDWARE_ERROR_BLOCK_SIZE); - Status = gBS->AllocatePool ( - EfiReservedMemoryType, - BlockMemorySize, - &BlockMemory - ); - if (EFI_ERROR (Status)) { - return Status; - } - gBS->SetMem (BlockMemory, BlockMemorySize, 0); - GhesRegisters = BlockMemory; - ErrorBlockHead = BlockMemory + MAX_GHES * sizeof (GHES_REGISTER); - ErrorBlock = ErrorBlockHead; - for (Iter = 0; Iter < MAX_GHES; Iter++) { - GhesV2Initial (&GhesV2[Iter], GENERIC_HARDWARE_ERROR_BLOCK_SIZE); - GhesV2AddNotification (&GhesV2[Iter], EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV); - ErrorBlockInitial (ErrorBlock, ErrorSeverityArray[Iter]); - GhesV2LinkErrorBlock (&GhesV2[Iter], &GhesRegisters[Iter], ErrorBlock); - ErrorBlock += GhesV2[Iter].ErrorStatusBlockLength; - } - return EFI_SUCCESS; -} -/***************************************************************************** -* @param EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE* GhesV2,Vector of GhesV2 -* @param UINT8 NumOfGhesV2 -* @param_out -* @retval EFI_STATUS -*****************************************************************************/ - -EFI_STATUS -GhesV1ContextForHest ( - IN EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE GhesV1[MAX_GHES], - IN UINT8 NumOfGhesV1 -) -{ - // ensuce the size is expected - if ((GhesV1 == NULL) || (NumOfGhesV1 != MAX_GHES)) { - return EFI_INVALID_PARAMETER; - } - - UINT8 NumOfBlockPerGhes = 1; - UINT8 Iter = 0; - UINT32 BlockMemorySize = MAX_GHES * - (sizeof (UINT64) + NumOfBlockPerGhes * GENERIC_HARDWARE_ERROR_BLOCK_SIZE); - UINT32 ErrorSeverityArray[MAX_GHES] = { - EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE, - EFI_ACPI_6_2_ERROR_SEVERITY_FATAL, - EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED}; - VOID *ErrorBlockHead; - VOID *ErrorBlock; - VOID *BlockMemory; - UINT64 *ptrBlockAddress; - EFI_STATUS Status = EFI_SUCCESS; - Status = gBS->AllocatePool ( - EfiReservedMemoryType, - BlockMemorySize, - &BlockMemory - ); - if (EFI_ERROR (Status)) { - return Status; - } - gBS->SetMem (BlockMemory, BlockMemorySize, 0); - ptrBlockAddress = BlockMemory; - ErrorBlockHead = BlockMemory + MAX_GHES * sizeof (UINT64); - ErrorBlock = ErrorBlockHead; - for (Iter = 0; Iter < MAX_GHES; Iter++) { - GhesV1Initial (&GhesV1[Iter], GENERIC_HARDWARE_ERROR_BLOCK_SIZE); - GhesV1AddNotification (&GhesV1[Iter], EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV); - ErrorBlockInitial (ErrorBlock, ErrorSeverityArray[Iter]); - GhesV1LinkErrorBlock (&GhesV1[Iter], &ptrBlockAddress[Iter], ErrorBlock); - ErrorBlock += GhesV1[Iter].ErrorStatusBlockLength; - } - return EFI_SUCCESS; -} - -VOID -OemHestInitialNotification () -{ - // GPIO init - // use int_msk to simulate - UINTN Base = IOMUX_REG_BASE; - //GPIO9, in document 'PhosphorV680 Totemiomux' iomg051, - //Set GPIO9 to pad_ex_int1 - MmioWrite32 (Base + IOMG051, PAD_EX_INT1); - return; -} - -VOID -OemEinjInitialNotification () -{ - UINTN Base = IOMUX_REG_BASE; - //use TB_GPIO_PIN10 for EINJ - MmioWrite32 (Base + IOMG052, PAD_EX_INT1); - return; -} - -EFI_STATUS -OemInitHestTable ( - IN EFI_HANDLE ImageHandle -) -{ - EFI_STATUS Status = EFI_SUCCESS; - HEST_CONTEXT HestContext; - EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE GhesV2[MAX_GHES]; - Status = HestHeaderCreator (&HestContext, HEST_TABLE_SIZE); - if (EFI_ERROR (Status)) { - return Status; - } - Status = GhesV2ContextForHest(GhesV2, MAX_GHES); - if (EFI_ERROR (Status)) { - return Status; - } - Status |= HestAddErrorSourceDescriptor ( - &HestContext, - &GhesV2[0], - sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE) - ); - mApeiTrustedfirmwareData->HestRecoverableErrorGhesV2 = HestContext.KeyErrorSource; - Status |= HestAddErrorSourceDescriptor ( - &HestContext, - &GhesV2[1], - sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE) - ); - mApeiTrustedfirmwareData->HestFatalErrorGhesV2 = HestContext.KeyErrorSource; - Status |= HestAddErrorSourceDescriptor ( - &HestContext, - &GhesV2[2], - sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE) - ); - mApeiTrustedfirmwareData->HestCorrectedErrorGhesV2 = HestContext.KeyErrorSource; - OemHestInitialNotification (); - HestSetAcpiTable (&HestContext); - return Status; -} -/************************************************ -*************** BERT *************** -************************************************/ - -EFI_STATUS -OemInitBertTable ( - IN EFI_HANDLE ImageHandle -) -{ - BERT_CONTEXT Context; - BOOLEAN Status; - Status = BertHeaderCreator (&Context, BOOT_ERROR_REGION_SIZE); - if (EFI_ERROR (Status)) { - return Status; - } - ErrorBlockInitial (Context.Block, EFI_ACPI_6_2_ERROR_SEVERITY_NONE); - BertSetAcpiTable (&Context); - DEBUG ((DEBUG_INFO, "[%a]:[%dL]: %r\n", __func__, __LINE__, Status)); - return EFI_SUCCESS; -} -/************************************************ -*************** EINJ *************** -************************************************/ -EFI_STATUS -OemEinjConfigExecuteOperationEntry ( - EINJ_CONTEXT *Context -) -{ - EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY* KeyEntry = Context->ExecuteOperationEntry; - OemEinjInitialNotification (); - //use TB_GPIO_PIN10 for EINJ - KeyEntry->RegisterRegion.Address = PcdGet64 (PcdCpldBaseAddress) + CPLD_GPIO10_INT_OFFSET; - KeyEntry->Mask = CPLD_MASK; - KeyEntry->Value = CPLD_VALUE; - return EFI_SUCCESS; -} - -EFI_STATUS -OemInitEinjTable ( -) -{ - EFI_STATUS Status; - EINJ_CONTEXT Context; - Status = EinjHeaderCreator (&Context); - if (EFI_ERROR (Status)) { - return Status; - } - (VOID)EinjConfigErrorInjectCapability (&Context, 0xFFF);// TBD - (VOID)OemEinjConfigExecuteOperationEntry (&Context); - EinjSetAcpiTable (&Context); - DEBUG ((DEBUG_INFO, "[%a]:[%dL]: %d\n", __func__, __LINE__, Status)); - return EFI_SUCCESS; -} -/************************************************ -*************** ERST *************** -************************************************/ - -EFI_STATUS -OemErstConfigExecuteOperationEntry ( - ERST_BOOT_CONTEXT *Context -) -{ - EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY *KeyEntry; - KeyEntry = Context->ExecuteOperationEntry; - KeyEntry->RegisterRegion.Address = GPIO1_BASE + GPIO_INT_MASK; - KeyEntry->Value = 0x10; - KeyEntry->Mask = 0xFFFFFFFF; - GpioCombInit (GPIO1_BASE, 0xFFFF); - return EFI_SUCCESS; -} - -BOOLEAN -GetNvRamRegion ( - OUT VOID **NvRamAddrRange, - OUT UINT64 *NvRamAddrRangeLength -) -{ - UINT32 Store = ERST_RECORD_STORE_IN_MEM; - switch (Store) { - case (ERST_RECORD_STORE_IN_NVRAM): - break; - case (ERST_RECORD_STORE_IN_MEM): - * NvRamAddrRangeLength = ERST_DATASTORE_SIZE; - * NvRamAddrRange = AllocateReservedZeroPool (ERST_DATASTORE_SIZE); - break; - case (ERST_RECORD_STORE_IN_SPI_FLASH): - break; - default: - ; - } - return TRUE; -} - -/***OEM***/ -EFI_STATUS -OemInitErstTable ( -) -{ - EFI_STATUS Status = ERST_STATUS_SUCCESS; - ERST_BOOT_CONTEXT Context; - UINT64 BufferSize = ERST_DATASTORE_SIZE; - VOID *NvRamAddrRange; - UINT64 NvRamAddrRangeLength; - UINT64 NvRamAllRecordLength; - - GetNvRamRegion (&NvRamAddrRange, &NvRamAddrRangeLength); - NvRamAllRecordLength = 0; - Status = ErstHeaderCreator ( - &Context, - BufferSize, - NvRamAddrRange, - NvRamAllRecordLength, - NvRamAddrRangeLength); - OemErstConfigExecuteOperationEntry (&Context); - mApeiTrustedfirmwareData->ErstContext = (VOID*)Context.Rt; - ErstSetAcpiTable (&Context); - return Status; -}; diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h deleted file mode 100644 index fb62cab4e31a9e0d921e91d96158f78ee5d63bb8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef OEM_APEI_HI1620_H_H -#define OEM_APEI_HI1620_H_H -#define GPIO0_BASE 0x94100000 -#define GPIO1_BASE 0x94110000 -#define GPIO_INT_MASK 0x34 -#define GPIO_INT_EN 0x30 -#define GPIO_SWPORT_DDR 0x04 -#define GPIO_INT_TYPE 0x38 -#define GPIO_INT_POLARITY 0x3c -#define GPIO_LS_SYNC 0x60 -#define GPIO_INT_COMB 0xffc -#define IOMUX_REG_BASE 0x94190000 -#define IOMG051 0xCC -#define IOMG052 0xD0 -#define PAD_EX_INT1 0x4 -#define CPLD_GPIO10_INT_OFFSET 0xfc -#define CPLD_BASE_ADDR 0x80000000 -#define CPLD_MASK 0x01030000 -#define CPLD_VALUE 0x01020000 - -#define MAX_GHES 3 -#define GENERIC_HARDWARE_ERROR_BLOCK_SIZE 0x1000 -#define HEST_TABLE_SIZE 0x2000 -#define BOOT_ERROR_REGION_SIZE 0x1000 -#define GPIO_HEST_NOTIFIED_PIN BIT8 - -#define ERST_DATASTORE_SIZE 0x2000 -#endif diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c deleted file mode 100644 index 29537dc341cf80f04a848e16b7e868b8862ef59f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c +++ /dev/null @@ -1,58 +0,0 @@ -/** @file - - Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -RETURN_STATUS -EFIAPI -DebugSerialPortInitialize ( - VOID - ) -{ - UINT64 BaudRate; - UINT32 ReceiveFifoDepth; - EFI_PARITY_TYPE Parity; - UINT8 DataBits; - EFI_STOP_BITS_TYPE StopBits; - - BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate); - ReceiveFifoDepth = 0; // Use default FIFO depth - Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); - DataBits = FixedPcdGet8 (PcdUartDefaultDataBits); - StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits); - return PL011UartInitializePort ( - (UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase), - FixedPcdGet32 (PL011UartClkInHz), - &BaudRate, - &ReceiveFifoDepth, - &Parity, - &DataBits, - &StopBits - ); -} - -EFI_STATUS -SerialPortEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - Status = DebugSerialPortInitialize (); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "CPU1 TB serial port init ERROR: %r\n", Status)); - } - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf deleted file mode 100644 index 47f03c2014496e51465472ce038f12c9fb376709..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf +++ /dev/null @@ -1,42 +0,0 @@ -#/** @file -# -# Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = Pl011DebugSerialPortInitDxe - FILE_GUID = 16D53E86-7EA4-47bd-861F-511EA9B8ABE0 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = SerialPortEntry - -[Sources.common] - Pl011DebugSerialPortInitDxe.c - - -[Packages] - ArmPlatformPkg/ArmPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - UefiDriverEntryPoint - -[Pcd] - gArmPlatformTokenSpaceGuid.PL011UartClkInHz - gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits - -[Depex] - TRUE - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620.dec b/Silicon/Hisilicon/Hi1620/Hi1620.dec deleted file mode 100644 index 9134248efc2993c6b72272e172cc81618a7cfa3c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620.dec +++ /dev/null @@ -1,17 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - DEC_SPECIFICATION = 0x0001001A - PACKAGE_NAME = Hi1620Pkg - PACKAGE_GUID = 2553756f-07ca-45a2-b30b-a2fae452e7f6 - PACKAGE_VERSION = 0.1 - -[Includes] - Include diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf deleted file mode 100644 index 19e4aa3dab16c150e7f9a5b838555c63109b1c2c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf +++ /dev/null @@ -1,54 +0,0 @@ -## @file -# -# ACPI table data and ASL sources required to boot the platform. -# -# Copyright (c) 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = Hi1620AcpiTables - FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD - MODULE_TYPE = USER_DEFINED - VERSION_STRING = 1.0 - -[Sources] - Dsdt/DsdtHi1620.asl - Facs.aslc - Fadt.aslc - Gtdt.aslc - Hi1620Dbg2.aslc - Hi1620Iort.asl - Hi1620IortNoSmmu.asl - Hi1620Mcfg.aslc - Hi1620Slit.aslc - Hi1620Spcr.aslc - Hi1620Srat.aslc - MadtHi1620.aslc - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/Hi1620/Hi1620.dec - Silicon/Hisilicon/HisiPkg.dec - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdCoreCount - gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase - gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl deleted file mode 100644 index cbd8a693fc2342a1f462c8525076e4ad3de4934c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl +++ /dev/null @@ -1,403 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - // - // A57x16 Processor declaration - // - Device(CPU0) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - Device(CPU1) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - Device(CPU2) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - Device(CPU3) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - Device(CPU6) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - Device(CPU7) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } - Device(CPU8) { - Name(_HID, "ACPI0007") - Name(_UID, 8) - } - Device(CPU9) { - Name(_HID, "ACPI0007") - Name(_UID, 9) - } - Device(CP10) { - Name(_HID, "ACPI0007") - Name(_UID, 10) - } - Device(CP11) { - Name(_HID, "ACPI0007") - Name(_UID, 11) - } - Device(CP12) { - Name(_HID, "ACPI0007") - Name(_UID, 12) - } - Device(CP13) { - Name(_HID, "ACPI0007") - Name(_UID, 13) - } - Device(CP14) { - Name(_HID, "ACPI0007") - Name(_UID, 14) - } - Device(CP15) { - Name(_HID, "ACPI0007") - Name(_UID, 15) - } - Device(CP16) { - Name(_HID, "ACPI0007") - Name(_UID, 16) - } - Device(CP17) { - Name(_HID, "ACPI0007") - Name(_UID, 17) - } - Device(CP18) { - Name(_HID, "ACPI0007") - Name(_UID, 18) - } - Device(CP19) { - Name(_HID, "ACPI0007") - Name(_UID, 19) - } - Device(CP20) { - Name(_HID, "ACPI0007") - Name(_UID, 20) - } - Device(CP21) { - Name(_HID, "ACPI0007") - Name(_UID, 21) - } - Device(CP22) { - Name(_HID, "ACPI0007") - Name(_UID, 22) - } - Device(CP23) { - Name(_HID, "ACPI0007") - Name(_UID, 23) - } - Device(CP24) { - Name(_HID, "ACPI0007") - Name(_UID, 24) - } - Device(CP25) { - Name(_HID, "ACPI0007") - Name(_UID, 25) - } - Device(CP26) { - Name(_HID, "ACPI0007") - Name(_UID, 26) - } - Device(CP27) { - Name(_HID, "ACPI0007") - Name(_UID, 27) - } - Device(CP28) { - Name(_HID, "ACPI0007") - Name(_UID, 28) - } - Device(CP29) { - Name(_HID, "ACPI0007") - Name(_UID, 29) - } - Device(CP30) { - Name(_HID, "ACPI0007") - Name(_UID, 30) - } - Device(CP31) { - Name(_HID, "ACPI0007") - Name(_UID, 31) - } - Device(CP32) { - Name(_HID, "ACPI0007") - Name(_UID, 32) - } - Device(CP33) { - Name(_HID, "ACPI0007") - Name(_UID, 33) - } - Device(CP34) { - Name(_HID, "ACPI0007") - Name(_UID, 34) - } - Device(CP35) { - Name(_HID, "ACPI0007") - Name(_UID, 35) - } - Device(CP36) { - Name(_HID, "ACPI0007") - Name(_UID, 36) - } - Device(CP37) { - Name(_HID, "ACPI0007") - Name(_UID, 37) - } - Device(CP38) { - Name(_HID, "ACPI0007") - Name(_UID, 38) - } - Device(CP39) { - Name(_HID, "ACPI0007") - Name(_UID, 39) - } - Device(CP40) { - Name(_HID, "ACPI0007") - Name(_UID, 40) - } - Device(CP41) { - Name(_HID, "ACPI0007") - Name(_UID, 41) - } - Device(CP42) { - Name(_HID, "ACPI0007") - Name(_UID, 42) - } - Device(CP43) { - Name(_HID, "ACPI0007") - Name(_UID, 43) - } - Device(CP44) { - Name(_HID, "ACPI0007") - Name(_UID, 44) - } - Device(CP45) { - Name(_HID, "ACPI0007") - Name(_UID, 45) - } - Device(CP46) { - Name(_HID, "ACPI0007") - Name(_UID, 46) - } - Device(CP47) { - Name(_HID, "ACPI0007") - Name(_UID, 47) - } - - Device(CP48) { - Name(_HID, "ACPI0007") - Name(_UID, 48) - } - Device(CP49) { - Name(_HID, "ACPI0007") - Name(_UID, 49) - } - Device(CP50) { - Name(_HID, "ACPI0007") - Name(_UID, 50) - } - Device(CP51) { - Name(_HID, "ACPI0007") - Name(_UID, 51) - } - Device(CP52) { - Name(_HID, "ACPI0007") - Name(_UID, 52) - } - Device(CP53) { - Name(_HID, "ACPI0007") - Name(_UID, 53) - } - Device(CP54) { - Name(_HID, "ACPI0007") - Name(_UID, 54) - } - Device(CP55) { - Name(_HID, "ACPI0007") - Name(_UID, 55) - } - Device(CP56) { - Name(_HID, "ACPI0007") - Name(_UID, 56) - } - Device(CP57) { - Name(_HID, "ACPI0007") - Name(_UID, 57) - } - Device(CP58) { - Name(_HID, "ACPI0007") - Name(_UID, 58) - } - Device(CP59) { - Name(_HID, "ACPI0007") - Name(_UID, 59) - } - Device(CP60) { - Name(_HID, "ACPI0007") - Name(_UID, 60) - } - Device(CP61) { - Name(_HID, "ACPI0007") - Name(_UID, 61) - } - Device(CP62) { - Name(_HID, "ACPI0007") - Name(_UID, 62) - } - Device(CP63) { - Name(_HID, "ACPI0007") - Name(_UID, 63) - } - Device(CP64) { - Name(_HID, "ACPI0007") - Name(_UID, 64) - } - Device(CP65) { - Name(_HID, "ACPI0007") - Name(_UID, 65) - } - Device(CP66) { - Name(_HID, "ACPI0007") - Name(_UID, 66) - } - Device(CP67) { - Name(_HID, "ACPI0007") - Name(_UID, 67) - } - Device(CP68) { - Name(_HID, "ACPI0007") - Name(_UID, 68) - } - Device(CP69) { - Name(_HID, "ACPI0007") - Name(_UID, 69) - } - Device(CP70) { - Name(_HID, "ACPI0007") - Name(_UID, 70) - } - Device(CP71) { - Name(_HID, "ACPI0007") - Name(_UID, 71) - } - Device(CP72) { - Name(_HID, "ACPI0007") - Name(_UID, 72) - } - Device(CP73) { - Name(_HID, "ACPI0007") - Name(_UID, 73) - } - Device(CP74) { - Name(_HID, "ACPI0007") - Name(_UID, 74) - } - Device(CP75) { - Name(_HID, "ACPI0007") - Name(_UID, 75) - } - Device(CP76) { - Name(_HID, "ACPI0007") - Name(_UID, 76) - } - Device(CP77) { - Name(_HID, "ACPI0007") - Name(_UID, 77) - } - Device(CP78) { - Name(_HID, "ACPI0007") - Name(_UID, 78) - } - Device(CP79) { - Name(_HID, "ACPI0007") - Name(_UID, 79) - } - Device(CP80) { - Name(_HID, "ACPI0007") - Name(_UID, 80) - } - Device(CP81) { - Name(_HID, "ACPI0007") - Name(_UID, 81) - } - Device(CP82) { - Name(_HID, "ACPI0007") - Name(_UID, 82) - } - Device(CP83) { - Name(_HID, "ACPI0007") - Name(_UID, 83) - } - Device(CP84) { - Name(_HID, "ACPI0007") - Name(_UID, 84) - } - Device(CP85) { - Name(_HID, "ACPI0007") - Name(_UID, 85) - } - Device(CP86) { - Name(_HID, "ACPI0007") - Name(_UID, 86) - } - Device(CP87) { - Name(_HID, "ACPI0007") - Name(_UID, 87) - } - Device(CP88) { - Name(_HID, "ACPI0007") - Name(_UID, 88) - } - Device(CP89) { - Name(_HID, "ACPI0007") - Name(_UID, 89) - } - Device(CP90) { - Name(_HID, "ACPI0007") - Name(_UID, 90) - } - Device(CP91) { - Name(_HID, "ACPI0007") - Name(_UID, 91) - } - Device(CP92) { - Name(_HID, "ACPI0007") - Name(_UID, 92) - } - Device(CP93) { - Name(_HID, "ACPI0007") - Name(_UID, 93) - } - Device(CP94) { - Name(_HID, "ACPI0007") - Name(_UID, 94) - } - Device(CP95) { - Name(_HID, "ACPI0007") - Name(_UID, 95) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl deleted file mode 100644 index 06c39553792d8e05f14bcb9b6831e44c2f8b7121..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl +++ /dev/null @@ -1,23 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(COM0) { - Name(_HID, "ARMH0011") - Name(_UID, Zero) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x94080000, 0x1000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 141 } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl deleted file mode 100644 index 95e4d96c2704873859bbc7f1516f7cd0112bbe72..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl +++ /dev/null @@ -1,29 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -#include "Hi1620Platform.h" - -DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP08 ", EFI_ACPI_ARM_OEM_REVISION) { - include ("Com.asl") - include ("CPU.asl") - include ("Hi1620Pci.asl") - include ("Hi1620Mbig.asl") - include ("Hi1620Rde.asl") - include ("Hi1620Sec.asl") - include ("ipmi.asl") - include ("LpcUart_clk.asl") - include ("Hi1620Ged.asl") - include ("Hi1620Power.asl") - include ("Hi1620Apei.asl") - include ("Hi1620Mctp.asl") - include ("Pv680UncorePmu.asl") -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl deleted file mode 100644 index d9f2c5d149f90fb360d6f8867266b65ba7ff1ba0..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl +++ /dev/null @@ -1,87 +0,0 @@ -/** @file -* -* Copyright (c) 2018 Hisilicon Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -//Define a control method APEI -Scope(_SB) -{ - Device(GED2) { - Name(_HID, "ACPI0013") - Name(_UID, 2) - - Name (_CRS, ResourceTemplate () { - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) { - 122 - } - }) - - Method (_EVT, 0x1) { - Switch(ToInteger(Arg0)) { - Case(122) { - Notify (\_SB.ERRD, 0x80) - } - } - } - - Method (_STA, 0x0, NotSerialized) { - return (0xF); - } - } -} - -Device (\_SB.ERRD) -{ - Name (_HID, EISAID("PNP0C33")) - Name (_UID, 0) - Method (_STA, 0x0, NotSerialized) { - Return(0xF) - } -} - -Name(PWCP, Zero) // Platform-Wide Capability value. - -Scope (\_SB) { - Method (_OSC,4) { - // Create DWord-adressable for Arg3 First DWORD. - CreateDWordField(Arg3,0,CDW1) - - // Check for proper UUID - If (LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField (Arg3,4,TPD2) - - // Save Capabilities DWord2 - Store (TPD2, PWCP) - - // Set Bit[4]: APEI Support - Or (PWCP,0x10,PWCP) - - If (LNotEqual(Arg1,One)) {// Unknown revision - Or (CDW1,0x08,CDW1) - } - - // Update DWORD2 in the buffer - Store (PWCP,TPD2) - - Return (Arg3) - } - ElseIf (LEqual(Arg0, ToUUID("ed855e0c-6c90-47bf-a62a-26de0fc5ad5c"))) { // Check for WHEA GUID - CreateDWordField (Arg3,4,TPD3) - - Or (TPD3, 0x10, TPD3) //Set Bit[4]: APEI support. - - If (LNotEqual(Arg1,One)) {// Unknown revision - Or (CDW1,0x08,CDW1) - } - - return (Arg3) - } - Else { - Or (CDW1,4,CDW1) // Unrecognized UUID - Return (Arg3) - } - } // End _OSC -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl deleted file mode 100644 index 8e5ac845094c6168055893d2e1735476542ae9f9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl +++ /dev/null @@ -1,52 +0,0 @@ -/** @file -* -* Copyright (c) 2014, ARM Ltd. All rights reserved.
-* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
-* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -// -// Ged -// - -//Define a control method power button -Scope(_SB) -{ - OperationRegion(IOM1, SystemMemory, 0x941900C8, 0x4) - Field(IOM1, DWordAcc, NoLock, Preserve) { - IMX0, 32, - } - - Method (_INI) { - Store(IMX0, Local0) - And(Local0, 0xFFFFFFFC, Local0) - Or(Local0, 0x4, Local0) - Store(Local0, IMX0) - } - - Device(GED1) { - Name(_HID, "ACPI0013") - Name(_UID, 0) - - Name (_CRS, ResourceTemplate () { - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) { - 121 - } - }) - - Method (_STA, 0x0, NotSerialized) { - return (0xF); - } - - Method (_EVT, 0x1) { - Switch(ToInteger(Arg0)) { - Case(121) { - Notify (\_SB.PWRB, 0x80) - } - } - } - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl deleted file mode 100644 index 4253f504b1cb868473477e230ca2c44bbb1d770d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl +++ /dev/null @@ -1,1405 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(_SB) -{ - //This is for S0-TB-L3T0 PMU implementation - Device(MB30) { - Name(_HID, "HISI0152") - Name(_UID, 0x30) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-L3T1 PMU implementation - Device(MB31) { - Name(_HID, "HISI0152") - Name(_UID, 0x31) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-L3T2 PMU implementation - Device(MB32) { - Name(_HID, "HISI0152") - Name(_UID, 0x32) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-L3T3 PMU implementation - Device(MB33) { - Name(_HID, "HISI0152") - Name(_UID, 0x33) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-L3T4 PMU implementation - Device(MB34) { - Name(_HID, "HISI0152") - Name(_UID, 0x34) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-L3T5 PMU implementation - Device(MB35) { - Name(_HID, "HISI0152") - Name(_UID, 0x35) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-DDRC0 PMU implementation - Device(MB38) { - Name(_HID, "HISI0152") - Name(_UID, 0x38) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-DDRC1 PMU implementation - Device(MB39) { - Name(_HID, "HISI0152") - Name(_UID, 0x39) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-DDRC2 PMU implementation - Device(MB3A) { - Name(_HID, "HISI0152") - Name(_UID, 0x3A) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-DDRC3 PMU implementation - Device(MB3B) { - Name(_HID, "HISI0152") - Name(_UID, 0x3B) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-HHA0 PMU implementation - Device(MB3C) { - Name(_HID, "HISI0152") - Name(_UID, 0x3C) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TB-HHA1 PMU implementation - Device(MB3D) { - Name(_HID, "HISI0152") - Name(_UID, 0x3D) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xA8080000, - 0xA808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-L3T0 PMU implementation - Device(MB10) { - Name(_HID, "HISI0152") - Name(_UID, 0x10) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-L3T1 PMU implementation - Device(MB11) { - Name(_HID, "HISI0152") - Name(_UID, 0x11) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-L3T2 PMU implementation - Device(MB12) { - Name(_HID, "HISI0152") - Name(_UID, 0x12) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-L3T3 PMU implementation - Device(MB13) { - Name(_HID, "HISI0152") - Name(_UID, 0x13) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - - //This is for S0-TA-L3T4 PMU implementation - Device(MB14) { - Name(_HID, "HISI0152") - Name(_UID, 0x14) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-L3T5 PMU implementation - Device(MB15) { - Name(_HID, "HISI0152") - Name(_UID, 0x15) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-DDRC0 PMU implementation - Device(MB18) { - Name(_HID, "HISI0152") - Name(_UID, 0x18) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-DDRC1 PMU implementation - Device(MB19) { - Name(_HID, "HISI0152") - Name(_UID, 0x19) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-DDRC2 PMU implementation - Device(MB1A) { - Name(_HID, "HISI0152") - Name(_UID, 0x1A) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-DDRC3 PMU implementation - Device(MB1B) { - Name(_HID, "HISI0152") - Name(_UID, 0x1B) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-HHA0 PMU implementation - Device(MB1C) { - Name(_HID, "HISI0152") - Name(_UID, 0x1C) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S0-TA-HHA1 PMU implementation - Device(MB1D) { - Name(_HID, "HISI0152") - Name(_UID, 0x1D) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0xAC080000, - 0xAC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-L3T0 PMU implementation - Device(MB70) { - Name(_HID, "HISI0152") - Name(_UID, 0x70) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-L3T1 PMU implementation - Device(MB71) { - Name(_HID, "HISI0152") - Name(_UID, 0x71) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-L3T2 PMU implementation - Device(MB72) { - Name(_HID, "HISI0152") - Name(_UID, 0x72) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-L3T3 PMU implementation - Device(MB73) { - Name(_HID, "HISI0152") - Name(_UID, 0x73) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - - //This is for S1-TB-L3T4 PMU implementation - Device(MB74) { - Name(_HID, "HISI0152") - Name(_UID, 0x74) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-L3T5 PMU implementation - Device(MB75) { - Name(_HID, "HISI0152") - Name(_UID, 0x75) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-DDRC0 PMU implementation - Device(MB78) { - Name(_HID, "HISI0152") - Name(_UID, 0x78) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-DDRC1 PMU implementation - Device(MB79) { - Name(_HID, "HISI0152") - Name(_UID, 0x79) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-DDRC2 PMU implementation - Device(MB7A) { - Name(_HID, "HISI0152") - Name(_UID, 0x7A) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-DDRC3 PMU implementation - Device(MB7B) { - Name(_HID, "HISI0152") - Name(_UID, 0x7B) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-HHA0 PMU implementation - Device(MB7C) { - Name(_HID, "HISI0152") - Name(_UID, 0x7C) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TB-HHA1 PMU implementation - Device(MB7D) { - Name(_HID, "HISI0152") - Name(_UID, 0x7D) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000A8080000, - 0x4000A808ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-L3T0 PMU implementation - Device(MB50) { - Name(_HID, "HISI0152") - Name(_UID, 0x50) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-L3T1 PMU implementation - Device(MB51) { - Name(_HID, "HISI0152") - Name(_UID, 0x51) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-L3T2 PMU implementation - Device(MB52) { - Name(_HID, "HISI0152") - Name(_UID, 0x52) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-L3T3 PMU implementation - Device(MB53) { - Name(_HID, "HISI0152") - Name(_UID, 0x53) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - - //This is for S1-TA-L3T4 PMU implementation - Device(MB54) { - Name(_HID, "HISI0152") - Name(_UID, 0x54) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-L3T5 PMU implementation - Device(MB55) { - Name(_HID, "HISI0152") - Name(_UID, 0x55) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-DDRC0 PMU implementation - Device(MB58) { - Name(_HID, "HISI0152") - Name(_UID, 0x58) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-DDRC1 PMU implementation - Device(MB59) { - Name(_HID, "HISI0152") - Name(_UID, 0x59) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-DDRC2 PMU implementation - Device(MB5A) { - Name(_HID, "HISI0152") - Name(_UID, 0x5A) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-DDRC3 PMU implementation - Device(MB5B) { - Name(_HID, "HISI0152") - Name(_UID, 0x5B) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-HHA0 PMU implementation - Device(MB5C) { - Name(_HID, "HISI0152") - Name(_UID, 0x5C) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } - - //This is for S1-TA-HHA1 PMU implementation - Device(MB5D) { - Name(_HID, "HISI0152") - Name(_UID, 0x5D) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x4000AC080000, - 0x4000AC08ffff, - 0x0, - 0x10000 - ) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 1} - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl deleted file mode 100644 index 63573fc93a2ba3abd34c6537c42e8454522666dc..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ -Scope(_SB) -{ - Device(LOC0) { - Name(_HID, "HISI02F1") - Name(_UID, 0) - Name (_CRS, ResourceTemplate () { - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) - { - 488,489 - } - }) - } - - Device(MCT0) { - Name(_HID, "HISI0301") - Name(_UID, 0) - Name (_CRS, ResourceTemplate () { - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4") - { - 656 - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl deleted file mode 100644 index ab89cbec30332d59c066e4f9c6e1e2652132ea19..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ /dev/null @@ -1,1311 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -//#include "ArmPlatform.h" - -/* - See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 -*/ -#define PCI_OSC_SUPPORT() \ - Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ - Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ - Method(_OSC,4) { \ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ - /* Create DWord-adressable fields from the Capabilities Buffer */ \ - CreateDWordField(Arg3,0,CDW1) \ - CreateDWordField(Arg3,4,CDW2) \ - CreateDWordField(Arg3,8,CDW3) \ - /* Save Capabilities DWord2 & 3 */ \ - Store(CDW2,SUPP) \ - Store(CDW3,CTRL) \ - /* Only allow native hot plug control if OS supports: */ \ - /* ASPM */ \ - /* Clock PM */ \ - /* MSI/MSI-X */ \ - If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ - And(CTRL,0x1E,CTRL) \ - }\ - \ - /* Do not allow native PME, AER */ \ - /* Never allow SHPC (no SHPC controller in this system)*/ \ - And(CTRL,0x10,CTRL) \ - If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ - Or(CDW1,0x08,CDW1) \ - } \ - \ - If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ - Or(CDW1,0x10,CDW1) \ - } \ - \ - /* Update DWORD3 in the buffer */ \ - Store(CTRL,CDW3) \ - Return(Arg3) \ - } Else { \ - Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ - Return(Arg3) \ - } \ - } // End _OSC - -#define PCI_OSC_SUPPORT_HOTPLUG() \ - Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ - Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ - Method(_OSC,4) { \ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ - /* Create DWord-adressable fields from the Capabilities Buffer */ \ - CreateDWordField(Arg3,0,CDW1) \ - CreateDWordField(Arg3,4,CDW2) \ - CreateDWordField(Arg3,8,CDW3) \ - /* Save Capabilities DWord2 & 3 */ \ - Store(CDW2,SUPP) \ - Store(CDW3,CTRL) \ - /* Only allow native hot plug control if OS supports: */ \ - /* ASPM */ \ - /* Clock PM */ \ - /* MSI/MSI-X */ \ - If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ - And(CTRL,0x1E,CTRL) \ - }\ - \ - /* Always allow native PME, AER (no dependencies) */ \ - /* Never allow SHPC (no SHPC controller in this system)*/ \ - And(CTRL,0x1D,CTRL) \ - If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ - Or(CDW1,0x08,CDW1) \ - } \ - \ - If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ - Or(CDW1,0x10,CDW1) \ - } \ - \ - /* Update DWORD3 in the buffer */ \ - Store(CTRL,CDW3) \ - Return(Arg3) \ - } Else { \ - Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ - Return(Arg3) \ - } \ - } // End _OSC - -Scope(_SB) -{ - Device (PCI0) - { // PCI0 indicate host bridge 0 - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 0) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name (_BBN, 0x0) // Base Bus Number - Name (_CCA, 1) // cache coherence attribute - - Name (_PRT, Package (){ - // INTx configure for RP0, whoes device number is 0 - // For ESL/FPGA debug, we should modify this according to - // specific hardware configuration. - Package () {0xFFFF,0,0,640}, // INT_A - Package () {0xFFFF,1,0,641}, // INT_B - Package () {0xFFFF,2,0,642}, // INT_C - Package () {0xFFFF,3,0,643}, // INT_D - - // This is an example of RP1 INTx configure. Adding or not - // adding RPx INTx configure deponds on hardware board topology, - // if UEFI enables RPx, RPy, RPz... related INTx configure - // should be added - Package () {0x2FFFF,0,0,640}, // INT_A - Package () {0x2FFFF,1,0,641}, // INT_B - Package () {0x2FFFF,2,0,642}, // INT_C - Package () {0x2FFFF,3,0,643}, // INT_D - - Package () {0x4FFFF,0,0,640}, // INT_A - Package () {0x4FFFF,1,0,641}, // INT_B - Package () {0x4FFFF,2,0,642}, // INT_C - Package () {0x4FFFF,3,0,643}, // INT_D - - Package () {0x6FFFF,0,0,640}, // INT_A - Package () {0x6FFFF,1,0,641}, // INT_B - Package () {0x6FFFF,2,0,642}, // INT_C - Package () {0x6FFFF,3,0,643}, // INT_D - - Package () {0x8FFFF,0,0,640}, // INT_A - Package () {0x8FFFF,1,0,641}, // INT_B - Package () {0x8FFFF,2,0,642}, // INT_C - Package () {0x8FFFF,3,0,643}, // INT_D - - Package () {0xCFFFF,0,0,640}, // INT_A - Package () {0xCFFFF,1,0,641}, // INT_B - Package () {0xCFFFF,2,0,642}, // INT_C - Package () {0xCFFFF,3,0,643}, // INT_D - - Package () {0xEFFFF,0,0,640}, // INT_A - Package () {0xEFFFF,1,0,641}, // INT_B - Package () {0xEFFFF,2,0,642}, // INT_C - Package () {0xEFFFF,3,0,643}, // INT_D - - Package () {0x10FFFF,0,0,640}, // INT_A - Package () {0x10FFFF,1,0,641}, // INT_B - Package () {0x10FFFF,2,0,642}, // INT_C - Package () {0x10FFFF,3,0,643}, // INT_D - - Package () {0x12FFFF,0,0,640}, // INT_A - Package () {0x12FFFF,1,0,641}, // INT_B - Package () {0x12FFFF,2,0,642}, // INT_C - Package () {0x12FFFF,3,0,643}, // INT_D - }) - - Method (_CRS, 0, Serialized) { - // Method is defined in 19.6.82 in ACPI 6.0 spec - Name (RBUF, ResourceTemplate () { - // 19.3.3 in ACPI 6.0 spec - WordBusNumber ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x00, // AddressMinimum - Minimum Bus Number - 0x3f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x40 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit prefetch BAR windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x80000000000, // Min Base Address pci address - 0x83fffffffff, // Max Base Address - 0x0, // Translate - 0x4000000000 // Length, 256G - ) - QWordMemory ( // 32-bit non-prefetch BAR windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xe0000000, // Min Base Address pci address - 0xeffeffff, // Max Base Address - 0x0, // Translate - 0xfff0000 // Length, 256M - 64K - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xefff0000, // Translate - 0x10000 // Length, 64K - )} - ) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT_HOTPLUG () - - Method (_HPX, 0) { - Return (Package(2) { - Package(6) { // PCI Setting Record - 0x00, // Type 0 - 0x01, // Revision 1 - 0x08, // CacheLineSize in DWORDS - 0x40, // LatencyTimer in PCI clocks - 0x01, // Enable SERR (Boolean) - 0x01 // Enable PERR (Boolean) - }, - - Package(18){ // PCI-X Setting Record - 0x02, // Type 2 - 0x01, // Revision 1 - 0xFFFFFFFF, // Uncorrectable Error Mask Register AND Mask, Keep ->1 - 0x00000000, // Uncorrectable Error Mask Register OR Mask, keep ->0 - 0xFFFFFFFF, // Uncorrectable Error Severity Register AND Mask - 0x00000000, // Uncorrectable Error Severity Register OR Mask - 0xFFFFFFFF, // Correctable Error Mask Register AND Mask - 0x00000000, // Correctable Error Mask Register OR Mask - 0xFFFFFFFF, // Advanced Error Capabilities and Control Register AND Mask - 0x00000000, // Advanced Error Capabilities and Control Register OR Mask - 0xFFF7, // Device Control Register AND Mask - 0x0007, // Device Control Register OR Mask - 0xFFFF, // Link Control Register AND Mask - 0x0000, // Link Control Register OR Mask - 0xFFFFFFFF, // Secondary Uncorrectable Error Severity Register AND Mask - 0x00000000, // Secondary Uncorrectable Error Severity Register OR Mask - 0xFFFFFFFF, // Secondary Uncorrectable Error Mask Register AND Mask - 0x00000000 // Secondary Uncorrectable Error Mask Register OR Mask - } - }) - } - - Method (_STA, 0x0, NotSerialized) { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } -} // Device(PCI0) - - -Device (PCI1) -{ // PCI1 indicate host bridge 1 - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 1) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0x7b) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x7b, // AddressMinimum - Minimum Bus Number - 0x7b, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x1 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows, where to show this ?? - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x148800000, // Min Base Address pci address ?? - 0x148ffffff, // Max Base Address - 0x0, // Translate - 0x800000 // Length, 8M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } -} // Device(PCI1) - -Device (PCI2) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 2) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0x7a) // Base Bus Number - Name(_CCA, 1) // cache coherence attribute ?? - Name (_PRT, Package (){ - Package () {0xFFFF,0,0,640}, // INT_A - Package () {0xFFFF,1,0,641}, // INT_B - Package () {0xFFFF,2,0,642}, // INT_C - Package () {0xFFFF,3,0,643}, // INT_D - Package () {0x1FFFF,0,0,640}, // INT_A - Package () {0x1FFFF,1,0,641}, // INT_B - Package () {0x1FFFF,2,0,642}, // INT_C - Package () {0x1FFFF,3,0,643}, // INT_D - Package () {0x2FFFF,0,0,640}, // INT_A - Package () {0x2FFFF,1,0,641}, // INT_B - Package () {0x2FFFF,2,0,642}, // INT_C - Package () {0x2FFFF,3,0,643}, // INT_D - }) - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource // setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x7a, // AddressMinimum - Minimum Bus Number - 0x7a, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x1 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x20c000000, // Min Base Address pci address - 0x20c1fffff, // Max Base Address - 0x0, // Translate - 0x200000 // Length, 2M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method(_DMA, 0, Serialized) - { - Return (ResourceTemplate() - { - QWORDMemory( - ResourceConsumer, - PosDecode, // _DEC - MinFixed, // _MIF - MaxFixed, // _MAF - Prefetchable, // _MEM - ReadWrite, // _RW - 0, // _GRA - 0x00000000, // _MIN - 0xFFFFFFFF, // _MAX - 0x00000000, // _TRA - 0x100000000, // _LEN - , - , - , - ) - }) - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } -} - -Device (PCI3) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 3) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0x78) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x78, // AddressMinimum - Minimum Bus Number - 0x79, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x2 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x208000000, // Min Base Address pci address - 0x208ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length, 16M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } -} - -Device (PCI4) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 4) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0x7c) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x7c, // AddressMinimum - Minimum Bus Number - 0x7d, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x2 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x120000000, // Min Base Address pci address - 0x13fffffff, // Max Base Address - 0x0, // Translate - 0x20000000 // Length, 512M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } -} - -Device (PCI5) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 5) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0x74) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - - Name (_PRT, Package (){ - Package () {0x2FFFF,0,0,640}, // INT_A - Package () {0x2FFFF,1,0,641}, // INT_B - Package () {0x2FFFF,2,0,642}, // INT_C - Package () {0x2FFFF,3,0,643}, // INT_D - Package () {0x3FFFF,0,0,640}, // INT_A - Package () {0x3FFFF,1,0,641}, // INT_B - Package () {0x3FFFF,2,0,642}, // INT_C - Package () {0x3FFFF,3,0,643}, // INT_D - }) - - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x74, // AddressMinimum - Minimum Bus Number - 0x76, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x3 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x144000000, // Min Base Address pci address - 0x147ffffff, // Max Base Address - 0x0, // Translate - 0x4000000 // Length, 32M - ) - QWordMemory ( // 32-bit non-prefetch BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xa2000000, // Min Base Address pci address - 0xa2ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length, 16M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Device (SAS0) - { - Name (_ADR, 0x00020000) - Name (_DSD, Package () - { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 0x00, 0x00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0x140070000, 0x1000) - Field (CTL, DWordAcc, NoLock, Preserve) - { - Offset (0xa18), - RST, 32, - DRST, 32, - } - - OperationRegion (TXD, SystemMemory, 0xA2000000, 0x4000) - Field (TXD, DwordAcc, NoLock, Preserve) - { - Offset (0x2350), //port0 - ST00, 32, //0x2350 - ST01, 32, //0x2354 - ST02, 32, //0x2358 - ST03, 32, //0x235c - ST04, 32, //0x2360 - ST05, 32, //0x2364 - ST06, 32, //0x2368 - ST07, 32, //0x236c - Offset (0x2750), //port1 - ST10, 32, //0x2750 - ST11, 32, //0x2754 - ST12, 32, //0x2758 - ST13, 32, //0x275c - ST14, 32, //0x2760 - ST15, 32, //0x2764 - ST16, 32, //0x2768 - ST17, 32, //0x276c - Offset (0x2b50), //port2 - ST20, 32, //0x2b50 - ST21, 32, //0x2b54 - ST22, 32, //0x2b58 - ST23, 32, //0x2b5c - ST24, 32, //0x2b60 - ST25, 32, //0x2b64 - ST26, 32, //0x2b68 - ST27, 32, //0x2b6c - Offset (0x2f50), //port3 - ST30, 32, //0x2f50 - ST31, 32, //0x2f54 - ST32, 32, //0x2f58 - ST33, 32, //0x2f5c - ST34, 32, //0x2f60 - ST35, 32, //0x2f64 - ST36, 32, //0x2f68 - ST37, 32, //0x2f6c - Offset (0x3350), //port4 - ST40, 32, //0x3350 - ST41, 32, //0x3354 - ST42, 32, //0x3358 - ST43, 32, //0x335c - ST44, 32, //0x3360 - ST45, 32, //0x3364 - ST46, 32, //0x3368 - ST47, 32, //0x336c - Offset (0x3750),//port5 - ST50, 32, //0x3750 - ST51, 32, //0x3754 - ST52, 32, //0x3758 - ST53, 32, //0x375c - ST54, 32, //0x3760 - ST55, 32, //0x3764 - ST56, 32, //0x3768 - ST57, 32, //0x376c - Offset (0x3b50), //port6 - ST60, 32, //0x3b50 - ST61, 32, //0x3b54 - ST62, 32, //0x3b58 - ST63, 32, //0x3b5c - ST64, 32, //0x3b60 - ST65, 32, //0x3b64 - ST66, 32, //0x3b68 - ST67, 32, //0x3b6c - Offset (0x3f50), //port7 - ST70, 32, //0x3f50 - ST71, 32, //0x3f54 - ST72, 32, //0x3f58 - ST73, 32, //0x3f5c - ST74, 32, //0x3f60 - ST75, 32, //0x3f64 - ST76, 32, //0x3f68 - ST77, 32 //0x3f6c - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7FFFFFF, RST) - Sleep(1) - Store(0x7FFFFFF, DRST) - Sleep(1) - - //port0 - Store (0x8D04, ST00) - Sleep(1) - Store (0x8D04, ST01) - Sleep(1) - Store (0x8D04, ST02) - Sleep(1) - Store (0x8D04, ST03) - Sleep(1) - Store (0x8D04, ST05) - Sleep(1) - Store (0x8D04, ST06) - Sleep(1) - Store (0x8D04, ST07) - Sleep(1) - - //port1 - Store (0x8D04, ST10) - Sleep(1) - Store (0x8D04, ST11) - Sleep(1) - Store (0x8D04, ST12) - Sleep(1) - Store (0x8D04, ST13) - Sleep(1) - Store (0x8D04, ST15) - Sleep(1) - Store (0x8D04, ST16) - Sleep(1) - Store (0x8D04, ST17) - Sleep(1) - - //port2 - Store (0x8D04, ST20) - Sleep(1) - Store (0x8D04, ST21) - Sleep(1) - Store (0x8D04, ST22) - Sleep(1) - Store (0x8D04, ST23) - Sleep(1) - Store (0x8D04, ST25) - Sleep(1) - Store (0x8D04, ST26) - Sleep(1) - Store (0x8D04, ST27) - Sleep(1) - - //port3 - Store (0x8D04, ST30) - Sleep(1) - Store (0x8D04, ST31) - Sleep(1) - Store (0x8D04, ST32) - Sleep(1) - Store (0x8D04, ST33) - Sleep(1) - Store (0x8D04, ST35) - Sleep(1) - Store (0x8D04, ST36) - Sleep(1) - Store (0x8D04, ST37) - Sleep(1) - - //port4 - Store (0x8D04, ST40) - Sleep(1) - Store (0x8D04, ST41) - Sleep(1) - Store (0x8D04, ST42) - Sleep(1) - Store (0x8D04, ST43) - Sleep(1) - Store (0x8D04, ST45) - Sleep(1) - Store (0x8D04, ST46) - Sleep(1) - Store (0x8D04, ST47) - Sleep(1) - - //port5 - Store (0x8D04, ST50) - Sleep(1) - Store (0x8D04, ST51) - Sleep(1) - Store (0x8D04, ST52) - Sleep(1) - Store (0x8D04, ST53) - Sleep(1) - Store (0x8D04, ST55) - Sleep(1) - Store (0x8D04, ST56) - Sleep(1) - Store (0x8D04, ST57) - Sleep(1) - - //port6 - Store (0x8D04, ST60) - Sleep(1) - Store (0x8D04, ST61) - Sleep(1) - Store (0x8D04, ST62) - Sleep(1) - Store (0x8D04, ST63) - Sleep(1) - Store (0x8D04, ST65) - Sleep(1) - Store (0x8D04, ST66) - Sleep(1) - Store (0x8D04, ST67) - Sleep(1) - - //port7 - Store (0x8D04, ST70) - Sleep(1) - Store (0x8D04, ST71) - Sleep(1) - Store (0x8D04, ST72) - Sleep(1) - Store (0x8D04, ST73) - Sleep(1) - Store (0x8D04, ST75) - Sleep(1) - Store (0x8D04, ST76) - Sleep(1) - Store (0x8D04, ST77) - Sleep(1) - } - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x00) - } -} - -Device (PCI6) -{ // PCI0 indicate host bridge 0 - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 6) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - - Name (_PRT, Package (){ - // INTx configure for RP0, whoes device number is 0 - // For ESL/FPGA debug, we should modify this according to - // specific hardware configuration. - Package () {0xFFFF,0,0,640}, // INT_A - Package () {0xFFFF,1,0,641}, // INT_B - Package () {0xFFFF,2,0,642}, // INT_C - Package () {0xFFFF,3,0,643}, // INT_D - - // This is an example of RP1 INTx configure. Adding or not - // adding RPx INTx configure deponds on hardware board topology, - // if UEFI enables RPx, RPy, RPz... related INTx configure - // should be added - Package () {0x2FFFF,0,0,640}, // INT_A - Package () {0x2FFFF,1,0,641}, // INT_B - Package () {0x2FFFF,2,0,642}, // INT_C - Package () {0x2FFFF,3,0,643}, // INT_D - - Package () {0x4FFFF,0,0,640}, // INT_A - Package () {0x4FFFF,1,0,641}, // INT_B - Package () {0x4FFFF,2,0,642}, // INT_C - Package () {0x4FFFF,3,0,643}, // INT_D - - Package () {0x6FFFF,0,0,640}, // INT_A - Package () {0x6FFFF,1,0,641}, // INT_B - Package () {0x6FFFF,2,0,642}, // INT_C - Package () {0x6FFFF,3,0,643}, // INT_D - - Package () {0x8FFFF,0,0,640}, // INT_A - Package () {0x8FFFF,1,0,641}, // INT_B - Package () {0x8FFFF,2,0,642}, // INT_C - Package () {0x8FFFF,3,0,643}, // INT_D - - Package () {0xCFFFF,0,0,640}, // INT_A - Package () {0xCFFFF,1,0,641}, // INT_B - Package () {0xCFFFF,2,0,642}, // INT_C - Package () {0xCFFFF,3,0,643}, // INT_D - - Package () {0xEFFFF,0,0,640}, // INT_A - Package () {0xEFFFF,1,0,641}, // INT_B - Package () {0xEFFFF,2,0,642}, // INT_C - Package () {0xEFFFF,3,0,643}, // INT_D - - Package () {0x10FFFF,0,0,640}, // INT_A - Package () {0x10FFFF,1,0,641}, // INT_B - Package () {0x10FFFF,2,0,642}, // INT_C - Package () {0x10FFFF,3,0,643}, // INT_D - - Package () {0x12FFFF,0,0,640}, // INT_A - Package () {0x12FFFF,1,0,641}, // INT_B - Package () {0x12FFFF,2,0,642}, // INT_C - Package () {0x12FFFF,3,0,643}, // INT_D - }) - - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x9f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit prefetch BAR windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x480000000000, // Min Base Address pci address - 0x483fffffffff, // Max Base Address - 0x0, // Translate - 0x4000000000 // Length, 256G - ) - QWordMemory ( // 32-bit non-prefetch BAR windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xf0000000, // Min Base Address pci address - 0xfffeffff, // Max Base Address - 0x0, // Translate - 0xfff0000 // Length, 256M - 64K - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xffff0000, // Translate - 0x10000 // Length, 64K - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT_HOTPLUG () - - Method (_HPX, 0) { - Return (Package(2) { - Package(6) { // PCI Setting Record - 0x00, // Type 0 - 0x01, // Revision 1 - 0x08, // CacheLineSize in DWORDS - 0x40, // LatencyTimer in PCI clocks - 0x01, // Enable SERR (Boolean) - 0x01 // Enable PERR (Boolean) - }, - - Package(18){ // PCI-X Setting Record - 0x02, // Type 2 - 0x01, // Revision 1 - 0xFFFFFFFF, // Uncorrectable Error Mask Register AND Mask, Keep ->1 - 0x00000000, // Uncorrectable Error Mask Register OR Mask, keep ->0 - 0xFFFFFFFF, // Uncorrectable Error Severity Register AND Mask - 0x00000000, // Uncorrectable Error Severity Register OR Mask - 0xFFFFFFFF, // Correctable Error Mask Register AND Mask - 0x00000000, // Correctable Error Mask Register OR Mask - 0xFFFFFFFF, // Advanced Error Capabilities and Control Register AND Mask - 0x00000000, // Advanced Error Capabilities and Control Register OR Mask - 0xFFF7, // Device Control Register AND Mask - 0x0007, // Device Control Register OR Mask - 0xFFFF, // Link Control Register AND Mask - 0x0000, // Link Control Register OR Mask - 0xFFFFFFFF, // Secondary Uncorrectable Error Severity Register AND Mask - 0x00000000, // Secondary Uncorrectable Error Severity Register OR Mask - 0xFFFFFFFF, // Secondary Uncorrectable Error Mask Register AND Mask - 0x00000000 // Secondary Uncorrectable Error Mask Register OR Mask - } - }) - } - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } -} // Device(PCI6) - - -Device (PCI7) -{ // PCI1 indicate host bridge 1 - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 7) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0xbb) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0xbb, // AddressMinimum - Minimum Bus Number - 0xbb, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x1 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows, where to show this ?? - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x400148800000, // Min Base Address pci address ?? - 0x400148ffffff, // Max Base Address - 0x0, // Translate - 0x800000 // Length, 8M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } -} // Device(PCI7) - -Device (PCI8) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 8) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0xba) // Base Bus Number - Name(_CCA, 1) // cache coherence attribute ?? - Name (_PRT, Package (){ - Package () {0xFFFF,0,0,640}, // INT_A - Package () {0xFFFF,1,0,641}, // INT_B - Package () {0xFFFF,2,0,642}, // INT_C - Package () {0xFFFF,3,0,643}, // INT_D - Package () {0x1FFFF,0,0,640}, // INT_A - Package () {0x1FFFF,1,0,641}, // INT_B - Package () {0x1FFFF,2,0,642}, // INT_C - Package () {0x1FFFF,3,0,643}, // INT_D - Package () {0x2FFFF,0,0,640}, // INT_A - Package () {0x2FFFF,1,0,641}, // INT_B - Package () {0x2FFFF,2,0,642}, // INT_C - Package () {0x2FFFF,3,0,643}, // INT_D - }) - - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource // setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0xba, // AddressMinimum - Minimum Bus Number - 0xba, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x1 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x40020c000000, // Min Base Address pci address - 0x40020c1fffff, // Max Base Address - 0x0, // Translate - 0x200000 // Length, 2M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method(_DMA, 0, Serialized) - { - Return (ResourceTemplate() - { - QWORDMemory( - ResourceConsumer, - PosDecode, // _DEC - MinFixed, // _MIF - MaxFixed, // _MAF - Prefetchable, // _MEM - ReadWrite, // _RW - 0, // _GRA - 0x00000000, // _MIN - 0xFFFFFFFF, // _MAX - 0x00000000, // _TRA - 0x100000000, // _LEN - , - , - , - ) - }) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } -}// Device(PCI8) - -Device (PCI9) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 9) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0xb8) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource // setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0xb8, // AddressMinimum - Minimum Bus Number - 0xb9, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x2 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x400208000000, // Min Base Address pci address - 0x400208ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length, 16M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } -}// Device(PCI9) - -Device (PCIA) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 0xA) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0xbc) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0xbc, // AddressMinimum - Minimum Bus Number - 0xbd, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x2 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x400120000000, // Min Base Address pci address - 0x40013fffffff, // Max Base Address - 0x0, // Translate - 0x20000000 // Length, 512M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } -}// Device(PCIA) - -Device (PCIB) -{ - Name (_HID, "PNP0A08") // PCI Express Root Bridge - Name (_UID, 0xB) - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0xb4) // Base Bus Number ?? - Name(_CCA, 1) // cache coherence attribute ?? - - Name (_PRT, Package (){ - Package () {0x2FFFF,0,0,640}, // INT_A - Package () {0x2FFFF,1,0,641}, // INT_B - Package () {0x2FFFF,2,0,642}, // INT_C - Package () {0x2FFFF,3,0,643}, // INT_D - Package () {0x3FFFF,0,0,640}, // INT_A - Package () {0x3FFFF,1,0,641}, // INT_B - Package () {0x3FFFF,2,0,642}, // INT_C - Package () {0x3FFFF,3,0,643}, // INT_D - }) - - Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting - Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, - WordBusNumber ( // Bus numbers assigned to this root, - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - 0, // AddressGranularity - 0xb4, // AddressMinimum - Minimum Bus Number - 0xb6, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x3 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Prefetchable, - ReadWrite, - 0x0, // Granularity - 0x400144000000, // Min Base Address pci address - 0x400147ffffff, // Max Base Address - 0x0, // Translate - 0x4000000 // Length, 32M - ) - QWordMemory ( // 32-bit non-prefetch BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xa3000000, // Min Base Address pci address - 0xa3ffffff, // Max Base Address - 0x0, // Translate - 0x1000000 // Length, 16M - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS), this method return RBUF! - - PCI_OSC_SUPPORT () - - Method (_STA, 0x0, NotSerialized) - { - Return (0xf) - } - - Method (_PXM, 0, NotSerialized) - { - Return(0x02) - } -} - -Device (RESP) //reserve for ecam resource - { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xd0000000, 0x10000000) - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl deleted file mode 100644 index 721f85f76a8aaa29d41edf915611799862885982..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl +++ /dev/null @@ -1,22 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2016, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(PWRB) { - Name(_HID, "PNP0C0C") - Name(_UID, Zero) - Method(_STA, 0x0, NotSerialized) { - Return(0xF) - } - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl deleted file mode 100644 index d1d06b4790b6a509bf2a02442c2b5db85ddfb94d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl +++ /dev/null @@ -1,41 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(RDE0) { - Name(_HID, "HISI0201") - Name(_UID, 0) - Name(_CCA, 1) - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x209000000, - 0x209ffffff, - 0x0, - 0x01000000 - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") - { 586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601, - 602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617 - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl deleted file mode 100644 index 84b3ceaaca70c702f3c97f2f7826793a1f6931de..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl +++ /dev/null @@ -1,51 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2018, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(SEC0) { - Name (_HID, "HISI0200") - Name(_UID, 0) - Name(_CCA, 1) - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x141000000, - 0x141ffffff, - 0x0, - 0x01000000 - ) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") - { - 624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639, - 640,641,642,643,644,645,646,647,648,649,650,651,652,653,654,655 - } - }) - } - - Device(SEC1) { - Name(_HID, "HISI0200") - Name(_UID, 1) - Name (_CRS, ResourceTemplate () { - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) - { 466,467 - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl deleted file mode 100644 index d934831ab8c77f78832278d4e2998d637cac7252..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl +++ /dev/null @@ -1,243 +0,0 @@ -/** @file -* -* Copyright (c) 2018 Hisilicon Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -// -// GPIO -// - -//#include "ArmPlatform.h" -Scope(_SB) -{ -Device(GPO0) { - Name(_HID, "HISI0181") - Name(_ADR, 0) - Name(_UID, 0) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201120000, - 0x20112ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 476, - } - }) - - Device(PRTa) { - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"snps,nr-gpios", 32}, - } - }) - } -} - -/** -*I2C for 100k release -**/ -Device(I2C0) { - Name(_HID, "HISI02A2") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 1000}, - Package () {"clock-frequency", 100000}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201160000, - 0x20116ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 480, - } - }) -} - - -/** -*I2C for 100k vtof -**/ -Device(I2C2) { - Name(_HID, "HISI0182") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 1000}, - Package () {"clock-frequency", 100000}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201160000, - 0x20116ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 480, - } - }) -} - -/** -*I2C for 400k fpga -**/ -Device(I2C3) { - Name(_HID, "HISI0183") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"i2c-sda-falling-time-ns", 300}, - Package () {"i2c-scl-falling-time-ns", 100}, - Package () {"i2c-sda-hold-time-ns", 250}, - Package () {"clock-frequency", 400000}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201160000, - 0x20116ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 480, - } - }) -} - -Device(LPC) { - Name(_HID, "HISI0191") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - } - }) - - Name (_CRS, ResourceTemplate () { - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 484, - 490 - } - }) -} - -Device(NAD) { - Name(_HID, "HISI0192") - Name(_ADR, 0) - Name(_UID, 0) - Name(_CCA, 1) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"nand-bus-width", 8}, - Package () {"nand-ecc-mode", "hw"}, - Package () {"nand-ecc-strength", 24}, - Package () {"nand-ecc-step-size", 1024}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x206220000, - 0x20622ffff, - 0x0, - 0x10000 - ) - - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x206210000, - 0x20621ffff, - 0x0, - 0x10000 - ) - - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 483, - } - }) -} -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl deleted file mode 100644 index 1247184fec23c56a7caa36a286944bb1a8532452..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl +++ /dev/null @@ -1,243 +0,0 @@ -/** @file -* -* Copyright (c) 2018 Hisilicon Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -// -// GPIO -// - -//#include "ArmPlatform.h" -Scope(_SB) -{ - Device(GPO0) { - Name(_HID, "HISI0181") - Name(_ADR, 0) - Name(_UID, 0) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201120000, - 0x20112ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 476, - } - }) - - Device(PRTa) { - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"snps,nr-gpios", 32}, - } - }) - } - - } - -/** -*I2C for 400k release -**/ -Device(I2C1) { - Name(_HID, "HISI02A2") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"i2c-sda-falling-time-ns", 500}, - Package () {"i2c-scl-falling-time-ns", 100}, - Package () {"i2c-sda-hold-time-ns", 250}, - Package () {"clock-frequency", 400000}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201160000, - 0x20116ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 480, - } - }) -} - -/** -*I2C for 100k vtof -**/ -Device(I2C2) { - Name(_HID, "HISI0182") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 1000}, - Package () {"clock-frequency", 100000}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201160000, - 0x20116ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 480, - } - }) -} - -/** -*I2C for 400k fpga -**/ -Device(I2C3) { - Name(_HID, "HISI0183") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"i2c-sda-falling-time-ns", 300}, - Package () {"i2c-scl-falling-time-ns", 100}, - Package () {"i2c-sda-hold-time-ns", 250}, - Package () {"clock-frequency", 400000}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x201160000, - 0x20116ffff, - 0x0, - 0x10000 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 480, - } - }) -} - -Device(LPC) { - Name(_HID, "HISI0191") - Name(_ADR, 0) - Name(_UID, 0) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - } - }) - - Name (_CRS, ResourceTemplate () { - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 484, - 490 - } - }) -} - -Device(NAD) { - Name(_HID, "HISI0192") - Name(_ADR, 0) - Name(_UID, 0) - Name(_CCA, 1) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"nand-bus-width", 8}, - Package () {"nand-ecc-mode", "hw"}, - Package () {"nand-ecc-strength", 24}, - Package () {"nand-ecc-step-size", 1024}, - } - }) - - Name (_CRS, ResourceTemplate () { - //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000) - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x206220000, - 0x20622ffff, - 0x0, - 0x10000 - ) - - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x206210000, - 0x20621ffff, - 0x0, - 0x10000 - ) - - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,) - { - 483, - } - }) -} -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl deleted file mode 100644 index afdecf1db4f7b8d3ed197a16ba488ee265d87bf2..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl +++ /dev/null @@ -1,43 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2015, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - Device(UART) { - Name(_HID, "PNP0501") - Name(_UID, 0) - Name(_CCA, 1) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 1843200}, - } - }) - Name(_CRS, ResourceTemplate() { - QWordMemory ( - ResourceConsumer, - , - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, - 0x3f00003f8, - 0x3f00003ff, - 0x0, - 0x8 - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 } - }) - } -} - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl deleted file mode 100644 index 3f75108f5391fb839840ae4312a4b88929d05544..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl +++ /dev/null @@ -1,1652 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2017, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2017, Linaro Limited. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -Scope(_SB) -{ - // L3T0 for S0_TB(DieID:3) - Device (L300) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x90180000, // Min Base Address - 0x9018FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB30") - { - 832, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ccl-id", 0x00}, - } - }) - - } - // L3T1 for S0_TB(DieID:3) - Device (L301) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 1) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x90190000, // Min Base Address - 0x9019FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB31") - { - 833, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ccl-id", 0x01}, - } - }) - - } - - // L3T2 for S0_TB(DieID:3) - Device (L302) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 2) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x901A0000, // Min Base Address - 0x901AFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB32") - { - 834, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ccl-id", 0x02}, - } - }) - - } - - // L3T3 for S0_TB(DieID:3) - Device (L303) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 3) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x901B0000, // Min Base Address - 0x901BFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB33") - { - 835, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ccl-id", 0x03}, - } - }) - - } - // L3T4 for S0_TB(DieID:3) - Device (L304) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 4) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x901C0000, // Min Base Address - 0x901CFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB34") - { - 836, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ccl-id", 0x04}, - } - }) - - } - // L3T5 for S0_TB(DieID:3) - Device (L305) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 5) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x901D0000, // Min Base Address - 0x901DFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB35") - { - 837, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ccl-id", 0x05}, - } - }) - - } - - // DDRC0 for S0_TB(DieID:3) - Device (DDR0) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x94D20000, // Min Base Address - 0x94D2FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB38") - { - 844, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ch-id", 0x0}, - } - }) - - } - // DDRC1 for S0_TB(DieID:3) - Device (DDR1) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 1) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x94D30000, // Min Base Address - 0x94D3FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB39") - { - 845, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ch-id", 0x1}, - } - }) - - } - // DDRC2 for S0_TB(DieID:3) - Device (DDR2) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 2) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x94D40000, // Min Base Address - 0x94D4FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3A") - { - 846, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ch-id", 0x2}, - } - }) - - } - // DDRC3 for S0_TB(DieID:3) - Device (DDR3) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 3) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x94D50000, // Min Base Address - 0x94D5FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3B") - { - 847, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03}, - Package () {"hisilicon,ch-id", 0x3}, - } - }) - - } - - // HHA0 for S0_TB(DieID:3) - Device (HHA0) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 0) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x90120000, // Min Base Address - 0x9012FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3C") - { - 848, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03} - } - }) - } - - // HHA1 for S0_TB(DieID:3) - Device (HHA1) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 1) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x90130000, // Min Base Address - 0x9013FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3D") - { - 849, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x03} - } - }) - } - - // L3T0 for S0_TA(DieID:1) - Device (L308) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x08) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x98180000, // Min Base Address - 0x9818FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB10") - { - 832, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ccl-id", 0x00}, - } - }) - - } - // L3T1 for S0_TA(DieID:1) - Device (L309) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x09) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x98190000, // Min Base Address - 0x9819FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB11") - { - 833, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ccl-id", 0x01}, - } - }) - - } - - // L3T2 for S0_TA(DieID:1) - Device (L30A) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x0A) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x981A0000, // Min Base Address - 0x981AFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB12") - { - 834, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ccl-id", 0x02}, - } - }) - - } - - // L3T3 for S0_TA(DieID:1) - Device (L30B) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x0B) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x981B0000, // Min Base Address - 0x981BFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB13") - { - 835, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ccl-id", 0x03}, - } - }) - - } - // L3T4 for S0_TA(DieID:1) - Device (L30C) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x0C) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x981C0000, // Min Base Address - 0x981CFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB14") - { - 836, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ccl-id", 0x04}, - } - }) - - } - // L3T5 for S0_TA(DieID:1) - Device (L30D) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x0D) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x981D0000, // Min Base Address - 0x981DFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB15") - { - 837, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ccl-id", 0x05}, - } - }) - - } - - // DDRC0 for S0_TA(DieID:1) - Device (DDR4) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 4) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x9CD20000, // Min Base Address - 0x9CD2FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB18") - { - 844, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ch-id", 0x0}, - } - }) - - } - // DDRC1 for S0_TA(DieID:1) - Device (DDR5) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 5) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x9CD30000, // Min Base Address - 0x9CD3FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB19") - { - 845, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ch-id", 0x1}, - } - }) - - } - // DDRC2 for S0_TA(DieID:1) - Device (DDR6) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 6) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x9CD40000, // Min Base Address - 0x9CD4FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1A") - { - 846, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ch-id", 0x2}, - } - }) - - } - // DDRC3 for S0_TA(DieID:1) - Device (DDR7) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 7) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x9CD50000, // Min Base Address - 0x9CD5FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1B") - { - 847, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01}, - Package () {"hisilicon,ch-id", 0x3}, - } - }) - } - - // HHA0 for S0_TA(DieID:1) - Device (HHA2) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 2) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x98120000, // Min Base Address - 0x9812FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1C") - { - 848, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01} - } - }) - } - - // HHA1 for S0_TA(DieID:1) - Device (HHA3) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 3) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x98130000, // Min Base Address - 0x9813FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1D") - { - 849, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x01} - } - }) - } - - // It is the list PMU node of Socket1 - // L3T0 for S1_TB(DieID:7) - Device (L310) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x10) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400090180000, // Min Base Address - 0x40009018FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB70") - { - 832, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ccl-id", 0x00}, - } - }) - - } - // L3T1 for S1_TB(DieID:7) - Device (L311) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x11) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400090190000, // Min Base Address - 0x40009019FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB71") - { - 833, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ccl-id", 0x01}, - } - }) - - } - - // L3T2 for S1_TB(DieID:7) - Device (L312) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x12) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000901A0000, // Min Base Address - 0x4000901AFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB72") - { - 834, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ccl-id", 0x02}, - } - }) - - } - - // L3T3 for S1_TB(DieID:7) - Device (L313) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x13) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000901B0000, // Min Base Address - 0x4000901BFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB73") - { - 835, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ccl-id", 0x03}, - } - }) - - } - // L3T4 for S1_TB(DieID:7) - Device (L314) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x14) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000901C0000, // Min Base Address - 0x4000901CFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB74") - { - 836, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ccl-id", 0x04}, - } - }) - - } - // L3T5 for S1_TB(DieID:7) - Device (L315) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x15) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000901D0000, // Min Base Address - 0x4000901DFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB75") - { - 837, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ccl-id", 0x05}, - } - }) - - } - - // DDRC0 for S1_TB(DieID:7) - Device (DDR8) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 8) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400094D20000, // Min Base Address - 0x400094D2FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB78") - { - 844, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ch-id", 0x0}, - } - }) - - } - // DDRC1 for S1_TB(DieID:7) - Device (DDR9) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 9) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400094D30000, // Min Base Address - 0x400094D3FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB79") - { - 845, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ch-id", 0x1}, - } - }) - - } - // DDRC2 for S1_TB(DieID:7) - Device (DDRA) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0xA) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400094D40000, // Min Base Address - 0x400094D4FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7A") - { - 846, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ch-id", 0x2}, - } - }) - - } - // DDRC3 for S1_TB(DieID:7) - Device (DDRB) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0xB) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // DDRC address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400094D50000, // Min Base Address - 0x400094D5FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7B") - { - 847, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07}, - Package () {"hisilicon,ch-id", 0x3}, - } - }) - - } - - // HHA0 for S1_TB(DieID:7) - Device (HHA4) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 4) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400090120000, // Min Base Address - 0x40009012FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7C") - { - 848, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07} - } - }) - } - - // HHA1 for S1_TB(DieID:7) - Device (HHA5) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 5) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400090130000, // Min Base Address - 0x40009013FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7D") - { - 849, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x07} - } - }) - } - - // L3T0 for S1_TA(DieID:5) - Device (L318) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x18) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400098180000, // Min Base Address - 0x40009818FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB50") - { - 832, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ccl-id", 0x00}, - } - }) - - } - // L3T1 for S1_TA(DieID:5) - Device (L319) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x19) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400098190000, // Min Base Address - 0x40009819FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB51") - { - 833, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ccl-id", 0x01}, - } - }) - - } - - // L3T2 for S1_TA(DieID:5) - Device (L31A) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x1A) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000981A0000, // Min Base Address - 0x4000981AFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB52") - { - 834, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ccl-id", 0x02}, - } - }) - - } - - // L3T3 for S1_TA(DieID:5) - Device (L31B) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x1B) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000981B0000, // Min Base Address - 0x4000981BFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB53") - { - 835, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ccl-id", 0x03}, - } - }) - - } - // L3T4 for S1_TA(DieID:5) - Device (L31C) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x1C) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000981C0000, // Min Base Address - 0x4000981CFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB54") - { - 836, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ccl-id", 0x04}, - } - }) - - } - // L3T5 for S1_TA(DieID:5) - Device (L31D) { - Name (_HID, "HISI0213") // _HID: Hardware ID - Name (_UID, 0x1D) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x4000981D0000, // Min Base Address - 0x4000981DFFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB55") - { - 837, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ccl-id", 0x05}, - } - }) - - } - - // DDRC0 for S1_TA(DieID:5) - Device (DDRC) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0xC) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x40009CD20000, // Min Base Address - 0x40009CD2FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB58") - { - 844, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ch-id", 0x0}, - } - }) - - } - // DDRC1 for S1_TA(DieID:5) - Device (DDRD) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0xD) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x40009CD30000, // Min Base Address - 0x40009CD3FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB59") - { - 845, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ch-id", 0x1}, - } - }) - - } - // DDRC2 for S1_TA(DieID:5) - Device (DDRE) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0xE) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x40009CD40000, // Min Base Address - 0x40009CD4FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5A") - { - 846, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ch-id", 0x2}, - } - }) - - } - // DDRC3 for S1_TA(DieID:5) - Device (DDRF) { - Name (_HID, "HISI0233") // _HID: Hardware ID - Name (_UID, 0xF) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // L3T address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x40009CD50000, // Min Base Address - 0x40009CD5FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5B") - { - 847, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05}, - Package () {"hisilicon,ch-id", 0x3}, - } - }) - } - - // HHA0 for S1_TA(DieID:5) - Device (HHA6) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 6) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400098120000, // Min Base Address - 0x40009812FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5C") - { - 848, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05} - } - }) - } - // HHA1 for S0_TA(DieID:5) - Device (HHA7) { - Name (_HID, "HISI0243") // _HID: Hardware ID - Name (_UID, 7) // _UID: Unique ID - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // HHA address base - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400098130000, // Min Base Address - 0x40009813FFFF, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5D") - { - 849, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"hisilicon,scl-id", 0x05} - } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl deleted file mode 100644 index 07453326765f06e759bec3bbe8130a9a69819160..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl +++ /dev/null @@ -1,43 +0,0 @@ -/** @file -* -* Copyright (c) 2018 Hisilicon Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -// -// LPC -// - -Scope(_SB) { - Device (IPI0) { - Name (_HID, "IPI0001") - Name (_UID, 0) - Name (_STR, Unicode("IPMI_BT")) - Name(_CCA, 1) - //Name (_CID, "IPI0001") - Method (_IFT) { - Return (0x03) - } - Method (_SRV) { - Return (0x0200) // IPMI Spec Revision 2.0 - } - Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings - QWordMemory ( // BMC memory region - ResourceConsumer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0x3f00000e4, // Min Base Address - 0x3f00000e7, // Max Base Address - 0x0, // Translate - 0x4 // Length - ) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 } - }) - } -} diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc deleted file mode 100644 index 1fb43feb393b0acb288dcc687f1c0554d127b63f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc +++ /dev/null @@ -1,61 +0,0 @@ -/** @file -* Firmware ACPI Control Structure (FACS) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include - -EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length - 0xA152, // UINT32 HardwareSignature - 0, // UINT32 FirmwareWakingVector - 0, // UINT32 GlobalLock - 0, // UINT32 Flags - 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; - { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] - EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] - 0, // UINT32 OspmFlags "Platform firmware must - // initialize this field to zero." - { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] - EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Facs; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc deleted file mode 100644 index b5ce896085851fdff97ae54b903388896ea40ec3..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc +++ /dev/null @@ -1,85 +0,0 @@ -/** @file -* Fixed ACPI Description Table (FADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1620Platform.h" - -#include -#include - -EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { - ARM_ACPI_HEADER ( - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION - ), - 0, // UINT32 FirmwareCtrl - 0, // UINT32 Dsdt - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile - 0, // UINT16 SciInt - 0, // UINT32 SmiCmd - 0, // UINT8 AcpiEnable - 0, // UINT8 AcpiDisable - 0, // UINT8 S4BiosReq - 0, // UINT8 PstateCnt - 0, // UINT32 Pm1aEvtBlk - 0, // UINT32 Pm1bEvtBlk - 0, // UINT32 Pm1aCntBlk - 0, // UINT32 Pm1bCntBlk - 0, // UINT32 Pm2CntBlk - 0, // UINT32 PmTmrBlk - 0, // UINT32 Gpe0Blk - 0, // UINT32 Gpe1Blk - 0, // UINT8 Pm1EvtLen - 0, // UINT8 Pm1CntLen - 0, // UINT8 Pm2CntLen - 0, // UINT8 PmTmrLen - 0, // UINT8 Gpe0BlkLen - 0, // UINT8 Gpe1BlkLen - 0, // UINT8 Gpe1Base - 0, // UINT8 CstCnt - 0, // UINT16 PLvl2Lat - 0, // UINT16 PLvl3Lat - 0, // UINT16 FlushSize - 0, // UINT16 FlushStride - 0, // UINT8 DutyOffset - 0, // UINT8 DutyWidth - 0, // UINT8 DayAlrm - 0, // UINT8 MonAlrm - 0, // UINT8 Century - 0, // UINT16 IaPcBootArch - 0, // UINT8 Reserved1 - EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg - 0, // UINT8 ResetValue - EFI_ACPI_6_2_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision - 0, // UINT64 XFirmwareCtrl - 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc deleted file mode 100644 index e9f8e3f37dc9a28f510ff1b53714d0df027f93d7..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc +++ /dev/null @@ -1,81 +0,0 @@ -/** @file -* Generic Timer Description Table (GTDT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1620Platform.h" - -#include -#include -#include - -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE -#define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY -#define GTDT_TIMER_ACTIVE_HIGH 0 -#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF -#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY - -#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ALWAYS_ON_CAPABILITY | GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) - -#define GENERIC_WATCHDOG_CONTROL_BASE_CPU1_TOTEM_A 0x9C200000 -#define GENERIC_WATCHDOG_REFRESH_BASE_CPU1_TOTEM_A 0X9C210000 - -#define EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress, \ - ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags) \ - { \ - EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \ - EFI_ACPI_RESERVED_BYTE, RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \ - WatchdogTimerGSIV, WatchdogTimerFlags \ - } - -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1620_WATCHDOG_COUNT]; -} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES; - -#pragma pack () - -EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { - { - ARM_ACPI_HEADER( - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION - ), - SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress - 0, // UINT32 Reserved - FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags - FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags - FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags - FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress - HI1620_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset - }, - { - EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - GENERIC_WATCHDOG_REFRESH_BASE_CPU1_TOTEM_A, GENERIC_WATCHDOG_CONTROL_BASE_CPU1_TOTEM_A, 88, 1) - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Gtdt; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc deleted file mode 100644 index 886929ed7de70014310de3a32b0ffa4a30403402..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2018 Linaro Limited - * Copyright (c) 2018 Hisilicon Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * -*/ - -#include -#include -#include -#include -#include "Hi1620Platform.h" - -#define NUMBER_DEBUG_DEVICE_INFO 1 -#define NUMBER_OF_GENERIC_ADDRESS 1 -#define NAMESPACE_STRING_SIZE 12 -#define UART_LENGTH 0x1000 - -#pragma pack(1) - -typedef struct { - EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; - EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; - UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; - CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; -} EFI_ACPI_DBG2_DDI_STRUCT; - -typedef struct { - EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; - EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; -} EFI_ACPI_DEBUG_PORT_2_TABLE; - -#pragma pack() - -EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { - { - ARM_ACPI_HEADER( - EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, - EFI_ACPI_DEBUG_PORT_2_TABLE, - EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION - ), - OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), - NUMBER_DEBUG_DEVICE_INFO - }, - { - { - { - EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, - sizeof(EFI_ACPI_DBG2_DDI_STRUCT), - NUMBER_OF_GENERIC_ADDRESS, - NAMESPACE_STRING_SIZE, - OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), - 0, //OemDataLength - 0, //OemDataOffset - EFI_ACPI_DBG2_PORT_TYPE_SERIAL, - EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, - {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, - OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address), - OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), - }, - { - { - EFI_ACPI_6_1_SYSTEM_MEMORY, - 32, - 0, - EFI_ACPI_6_1_BYTE, - FixedPcdGet64 (PcdSerialDbgRegisterBase) - } - }, - { - UART_LENGTH - }, - "\\_SB.COM0" - } - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl deleted file mode 100644 index 5e27ce65b4d24cdbdfc2ea5f05c20e9b6024ce44..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl +++ /dev/null @@ -1,1981 +0,0 @@ -/* - * Intel ACPI Component Architecture - * iASL Compiler/Disassembler version 20151124-64 - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Template for [IORT] ACPI Table (static data table) - * Format: [ByteLength] FieldName : HexFieldValue - */ -[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 01c8 -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " // ? -[0008] Oem Table ID : "HIP08 " // ? -[0004] Oem Revision : 00000000 // ? -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 - -[0004] Node Count : 00000005 // ITS, SMMU and RC -[0004] Node Offset : 00000034 // ? -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00 - -/* 0x34 ITS, for PCIe */ -/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 // ? -[0004] Mapping Offset : 00000000 // ? - -[0004] ItsCount : 00000001 // ? -[0004] Identifiers : 00000000 // how to refer to MADT ? - -/* 0x4c SMMU for PCIe host bridge 0 and 1 */ -[0001] Type : 04 -[0002] Length : 0080 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000003 -[0004] Mapping Offset : 00000044 - -[0008] Base Address : 148000000 -[0004] Flags (decoded below) : 00000009 - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid : 1 -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000000 -[0004] Event GSIV : 00000000 -[0004] PRI GSIV : 00000000 -[0004] GERR GSIV : 00000000 -[0004] Sync GSIV : 00000000 -[0004] Proximity Domain : 00000000 -[0004] Device ID Mapping Index : 00000002 - -[0004] Input base : 00000000 -[0004] ID Count : 00004000 -[0004] Output Base : 00000000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00007b00 -[0004] ID Count : 00000100 -[0004] Output Base : 00007b00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00000000 //single mapping will ignore input base -[0004] ID Count : 00000001 -[0004] Output Base : 00007F01 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* 0xCC SMMU for PCIe host bridge 4 */ -[0001] Type : 04 -[0002] Length : 006C -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000044 - -[0008] Base Address : 100000000 -[0004] Flags (decoded below) : 00000009 - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid : 1 -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000000 -[0004] Event GSIV : 00000000 -[0004] PRI GSIV : 00000000 -[0004] GERR GSIV : 00000000 -[0004] Sync GSIV : 00000000 -[0004] Proximity Domain : 00000000 -[0004] Device ID Mapping Index : 0001 - -[0004] Input base : 00007c00 -[0004] ID Count : 00000200 -[0004] Output Base : 00007c00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00000000 //single mapping will ignore input base -[0004] ID Count : 00000001 -[0004] Output Base : 00007F03 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* 0x138 */ -/* SMMU for PCIe host bridge 5 */ -[0001] Type : 04 -[0002] Length : 006C -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000044 - -[0008] Base Address : 140000000 -[0004] Flags (decoded below) : 00000009 - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid : 1 -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000000 -[0004] Event GSIV : 00000000 -[0004] PRI GSIV : 00000000 -[0004] GERR GSIV : 00000000 -[0004] Sync GSIV : 00000000 -[0004] Proximity Domain : 00000000 -[0004] Device ID Mapping Index : 00000001 - -[0004] Input base : 00007400 -[0004] ID Count : 00000300 -[0004] Output Base : 00007400 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00000000 //single mapping will ignore input base -[0004] ID Count : 00000001 -[0004] Output Base : 00007F04 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -// Here for Chip1 SMMU settings -/* 0x1A4 SMMU for PCIe host bridge 6 and 7 */ -[0001] Type : 04 -[0002] Length : 0080 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000003 -[0004] Mapping Offset : 00000044 - -[0008] Base Address : 400148000000 -[0004] Flags (decoded below) : 00000009 - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid : 1 -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000000 -[0004] Event GSIV : 00000000 -[0004] PRI GSIV : 00000000 -[0004] GERR GSIV : 00000000 -[0004] Sync GSIV : 00000000 -[0004] Proximity Domain : 00000002 -[0004] Device ID Mapping Index : 00000002 - -[0004] Input base : 00008000 -[0004] ID Count : 00002000 -[0004] Output Base : 00008000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 0000bb00 -[0004] ID Count : 00000100 -[0004] Output Base : 0000bb00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00000000 //single mapping will ignore input base -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF01 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* 0x224 SMMU for PCIe host bridge 10 */ -[0001] Type : 04 -[0002] Length : 006C -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000044 - -[0008] Base Address : 400100000000 -[0004] Flags (decoded below) : 00000009 - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid : 1 -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000000 -[0004] Event GSIV : 00000000 -[0004] PRI GSIV : 00000000 -[0004] GERR GSIV : 00000000 -[0004] Sync GSIV : 00000000 -[0004] Proximity Domain : 00000002 -[0004] Device ID Mapping Index : 0001 - -[0004] Input base : 0000BC00 -[0004] ID Count : 00000200 -[0004] Output Base : 0000BC00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00000000 //single mapping will ignore input base -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF03 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* 0x290*/ -/* SMMU for PCIe host bridge 11 */ -[0001] Type : 04 -[0002] Length : 006C -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000044 - -[0008] Base Address : 400140000000 -[0004] Flags (decoded below) : 00000009 - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid : 1 -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000000 -[0004] Event GSIV : 00000000 -[0004] PRI GSIV : 00000000 -[0004] GERR GSIV : 00000000 -[0004] Sync GSIV : 00000000 -[0004] Proximity Domain : 00000002 -[0004] Device ID Mapping Index : 00000001 - -[0004] Input base : 0000B400 -[0004] ID Count : 00000300 -[0004] Output Base : 0000B400 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -[0004] Input base : 00000000 //single mapping will ignore input base -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF04 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/*0x2FC RC 0 */ -[0001] Type : 02 -[0002] Length : 00A0 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 0000000C -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 01 - Coherency : 1 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000000 // should match with above MCFG - Memory Size Limit : 00 - Reserved : 00000000 - -/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */ -[0004] Input base : 00000000 -[0004] ID Count : 00004000 // the number of IDs in range -[0004] Output Base : 00000000 -[0004] Output Reference : 0000004c -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */ -[0004] Input base : 00007b00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 00007b00 -[0004] Output Reference : 0000004c -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* host2 and host3 should no open smmu for chips smmu bug */ -/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */ -[0004] Input base : 00007a00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 00007a00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */ -[0004] Input base : 00007800 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 00007800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */ -[0004] Input base : 00007c00 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 00007c00 -[0004] Output Reference : 000000cc -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */ -[0004] Input base : 00007400 -[0004] ID Count : 00000300 // the number of IDs in range -[0004] Output Base : 00007400 -[0004] Output Reference : 00000138 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */ -[0004] Input base : 00008000 -[0004] ID Count : 00002000 // the number of IDs in range -[0004] Output Base : 00008000 -[0004] Output Reference : 000001A4 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */ -[0004] Input base : 0000BB00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 0000BB00 -[0004] Output Reference : 000001A4 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* host8 and host9 should no open smmu for chips smmu bug */ -/* BDF of pcie host 8 -> stream ID of pcie ITS */ -[0004] Input base : 0000BA00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 0000BA00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */ -[0004] Input base : 0000B800 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 0000B800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */ -[0004] Input base : 0000BC00 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 0000BC00 -[0004] Output Reference : 00000224 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */ -[0004] Input base : 0000B400 -[0004] ID Count : 00000300 // the number of IDs in range -[0004] Output Base : 0000B400 -[0004] Output Reference : 00000290 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB30" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD1 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB31" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD2 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB32" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD3 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB33" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD4 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB34" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD5 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB35" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD6 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB38" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FDD // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB39" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FDE // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FDF // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FC7 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FC8 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FC9 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB10" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F51 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB11" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F52 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB12" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F53 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB13" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F54 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB14" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F55 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB15" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F56 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB18" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F5D // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB19" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F5E // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F5F // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F47 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F48 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F49 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB70" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD1 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB71" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD2 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB72" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD3 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB73" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD4 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB74" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD5 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB75" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD6 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB78" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFDD // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB79" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFDE // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFDF // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFC7 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFC8 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFC9 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB50" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF51 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB51" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF52 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB52" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF53 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB53" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF54 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB54" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF55 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB55" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF56 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB58" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF5D // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB59" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF5E // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF5F // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF47 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF48 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF49 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - - -[320h 0800 1] Type : 01 -[321h 0801 2] Length : 0054 -[323h 0803 1] Revision : 00 -[324h 0804 4] Reserved : 00000000 -[328h 0808 4] Mapping Count : 00000001 -[32Ch 0812 4] Mapping Offset : 00000040 - -[330h 0816 4] Node Flags : 00000000 -[334h 0820 8] Memory Properties : [IORT Memory Access Properties] -[334h 0820 4] Cache Coherency : 00000000 -[338h 0824 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[339h 0825 2] Reserved : 0000 -[33Bh 0827 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[33Ch 0828 1] Memory Size Limit : 00 -[33Dh 0829 11] Device Name : "\_SB_.SEC0" -[348h 0840 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[34Ch 0844 4] Input base : 00000000 -[350h 0848 4] ID Count : 00000001 -[354h 0852 4] Output Base : 00000100 -[358h 0856 4] Output Reference : 00000138 -[35Ch 0860 4] Flags (decoded below) : 00000001 - Single Mapping : 1 -/* RDE device report++.*/ -[320h 0800 1] Type : 01 -[321h 0801 2] Length : 0054 -[323h 0803 1] Revision : 00 -[324h 0804 4] Reserved : 00000000 -[328h 0808 4] Mapping Count : 00000001 -[32Ch 0812 4] Mapping Offset : 00000040 - -[330h 0816 4] Node Flags : 00000000 -[334h 0820 8] Memory Properties : [IORT Memory Access Properties] -[334h 0820 4] Cache Coherency : 00000000 -[338h 0824 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[339h 0825 2] Reserved : 0000 -[33Bh 0827 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[33Ch 0828 1] Memory Size Limit : 00 -[33Dh 0829 11] Device Name : "\_SB_.RDE0" -[348h 0840 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[34Ch 0844 4] Input base : 00000000 -[350h 0848 4] ID Count : 00000001 -[354h 0852 4] Output Base : 00007f13 -[358h 0856 4] Output Reference : 00000034 -[35Ch 0860 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for MCTP, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI4" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F18 // MCTP device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl deleted file mode 100644 index ce56157b3a923acc2a1556aba02719e6a304dd0a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl +++ /dev/null @@ -1,1740 +0,0 @@ -/* - * Intel ACPI Component Architecture - * iASL Compiler/Disassembler version 20151124-64 - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Template for [IORT] ACPI Table (static data table) - * Format: [ByteLength] FieldName : HexFieldValue - */ -[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 01c8 -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " // ? -[0008] Oem Table ID : "HIP08 " // ? -[0004] Oem Revision : 00000000 // ? -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 - -[0004] Node Count : 00000005 // ITS, SMMU and RC -[0004] Node Offset : 00000034 // ? -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00 - -/* 0x34 ITS, for PCIe */ -/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 // ? -[0004] Mapping Offset : 00000000 // ? - -[0004] ItsCount : 00000001 // ? -[0004] Identifiers : 00000000 // how to refer to MADT ? - -/*0x4c RC 0 */ -[0001] Type : 02 -[0002] Length : 00A0 -[0001] Revision : 01 -[0004] Reserved : 00000000 -[0004] Mapping Count : 0000000C -[0004] Mapping Offset : 00000024 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000000 // should match with above MCFG - Memory Size Limit : 00 - Reserved : 00000000 - -/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */ -[0004] Input base : 00000000 -[0004] ID Count : 00004000 // the number of IDs in range -[0004] Output Base : 00000000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */ -[0004] Input base : 00007b00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 00007b00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */ -[0004] Input base : 00007a00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 00007a00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */ -[0004] Input base : 00007800 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 00007800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */ -[0004] Input base : 00007c00 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 00007c00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */ -[0004] Input base : 00007400 -[0004] ID Count : 00000300 // the number of IDs in range -[0004] Output Base : 00007400 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */ -[0004] Input base : 00008000 -[0004] ID Count : 00002000 // the number of IDs in range -[0004] Output Base : 00008000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */ -[0004] Input base : 0000BB00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 0000BB00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 8 -> stream ID of pcie ITS */ -[0004] Input base : 0000BA00 -[0004] ID Count : 00000100 // the number of IDs in range -[0004] Output Base : 0000BA00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */ -[0004] Input base : 0000B800 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 0000B800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */ -[0004] Input base : 0000BC00 -[0004] ID Count : 00000200 // the number of IDs in range -[0004] Output Base : 0000BC00 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */ -[0004] Input base : 0000B400 -[0004] ID Count : 00000300 // the number of IDs in range -[0004] Output Base : 0000B400 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* mbi-gen for S0-TB-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB30" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD1 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB31" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD2 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB32" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD3 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB33" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD4 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB34" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD5 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB35" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FD6 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB38" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FDD // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB39" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FDE // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FDF // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FC7 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FC8 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TB-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB3D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007FC9 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB10" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F51 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB11" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F52 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB12" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F53 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB13" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F54 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB14" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F55 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB15" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F56 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB18" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F5D // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB19" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F5E // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F5F // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F47 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F48 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S0-TA-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB1D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F49 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB70" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD1 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB71" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD2 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB72" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD3 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB73" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD4 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB74" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD5 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB75" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFD6 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB78" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFDD // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB79" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFDE // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFDF // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFC7 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFC8 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TB-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB7D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BFC9 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB50" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF51 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB51" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF52 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB52" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF53 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB53" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF54 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T4, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB54" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF55 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-L3T5, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB55" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF56 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB58" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF5D // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB59" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF5E // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5A" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF5F // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-DDRC3, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5B" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF47 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-HHA0, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5C" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF48 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for S1-TA-HHA1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MB5D" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 0000BF49 // PMU device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 - - -[320h 0800 1] Type : 01 -[321h 0801 2] Length : 0054 -[323h 0803 1] Revision : 00 -[324h 0804 4] Reserved : 00000000 -[328h 0808 4] Mapping Count : 00000001 -[32Ch 0812 4] Mapping Offset : 00000040 - -[330h 0816 4] Node Flags : 00000000 -[334h 0820 8] Memory Properties : [IORT Memory Access Properties] -[334h 0820 4] Cache Coherency : 00000000 -[338h 0824 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[339h 0825 2] Reserved : 0000 -[33Bh 0827 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[33Ch 0828 1] Memory Size Limit : 00 -[33Dh 0829 11] Device Name : "\_SB_.SEC0" -[348h 0840 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[34Ch 0844 4] Input base : 00000000 -[350h 0848 4] ID Count : 00000001 -[354h 0852 4] Output Base : 00000100 -[358h 0856 4] Output Reference : 00000034 -[35Ch 0860 4] Flags (decoded below) : 00000001 - Single Mapping : 1 -/* RDE device report++.*/ -[320h 0800 1] Type : 01 -[321h 0801 2] Length : 0054 -[323h 0803 1] Revision : 00 -[324h 0804 4] Reserved : 00000000 -[328h 0808 4] Mapping Count : 00000001 -[32Ch 0812 4] Mapping Offset : 00000040 - -[330h 0816 4] Node Flags : 00000000 -[334h 0820 8] Memory Properties : [IORT Memory Access Properties] -[334h 0820 4] Cache Coherency : 00000000 -[338h 0824 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[339h 0825 2] Reserved : 0000 -[33Bh 0827 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[33Ch 0828 1] Memory Size Limit : 00 -[33Dh 0829 11] Device Name : "\_SB_.RDE0" -[348h 0840 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[34Ch 0844 4] Input base : 00000000 -[350h 0848 4] ID Count : 00000001 -[354h 0852 4] Output Base : 00007f13 -[358h 0856 4] Output Reference : 00000034 -[35Ch 0860 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/* mbi-gen for MCTP, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "\_SB_.MBI4" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00007F18 // MCTP device id -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000001 - Single Mapping : 1 diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc deleted file mode 100644 index fb19344f11c80fe52d545547ebc730140d8f5d35..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018 Hisilicon Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - */ - -#include -#include "Hi1620Platform.h" - -#define MCFG_VERSION 0x1 - -#pragma pack(1) -typedef struct -{ - UINT64 ullBaseAddress; - UINT16 usSegGroupNum; - UINT8 ucStartBusNum; - UINT8 ucEndBusNum; - UINT32 Reserved2; -}EFI_MCFG_CONFIG_STRUCTURE; - -typedef struct -{ - EFI_ACPI_DESCRIPTION_HEADER Header; - UINT64 Reserved1; -}EFI_MCFG_TABLE_CONFIG; - -typedef struct -{ - EFI_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_MCFG_CONFIG_STRUCTURE Config_Structure; -}EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; -#pragma pack() - -EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= -{ - { - { - EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - MCFG_VERSION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION - }, - 0x0000000000000000, //Reserved - }, - { - 0xd0000000, //Base Address - 0x0, //Segment Group Number - 0x0, //Start Bus Number - 0xff, //End Bus Number - 0x00000000, //Reserved - } -}; - -VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h deleted file mode 100644 index c7c6093f0254541a3ca718ff036330193741dbbe..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h +++ /dev/null @@ -1,21 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015-2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - - -#ifndef _HI1620_PLATFORM_H_ -#define _HI1620_PLATFORM_H_ - -#include - -#define HI1620_WATCHDOG_COUNT 1 - -#endif diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc deleted file mode 100644 index 145828108aa69ee1447ab984ffdf02c20a88d982..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Contributors: - * Yi Li - yi.li@linaro.org -*/ - -#include -#include "Hi1620Platform.h" - -#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004 - -#pragma pack(1) -typedef struct { - UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_6_2_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; - -typedef struct { - EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; - EFI_ACPI_6_2_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; - -} EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE; -#pragma pack() - -// -// System Locality Information Table -// Please modify all values in Slit.h only. -// -EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { - { - { - EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE), - EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION, - }, - // - // Beginning of SLIT specific fields - // - EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, - }, - { - {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0 - {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1 - {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2 - {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3 - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Slit; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc deleted file mode 100644 index e97f78d2c111a39c73dab2f35f12d5ed00b86edb..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc +++ /dev/null @@ -1,75 +0,0 @@ -/** @file -* Serial Port Console Redirection Table (SPCR) -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016 Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include -#include -#include -#include -#include "Hi1620Platform.h" - -#define SPCR_FLOW_CONTROL_NONE 0 - -STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { - ARM_ACPI_HEADER (EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), - // UINT8 InterfaceType; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, - // UINT8 Reserved1[3]; - { - EFI_ACPI_RESERVED_BYTE, - EFI_ACPI_RESERVED_BYTE, - EFI_ACPI_RESERVED_BYTE - }, - // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress; - ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), - // UINT8 InterruptType; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, - // UINT8 Irq; - 0, // Not used on ARM - // UINT32 GlobalSystemInterrupt; - 141, - // UINT8 BaudRate; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, - // UINT8 Parity; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, - // UINT8 StopBits; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, - // UINT8 FlowControl; - SPCR_FLOW_CONTROL_NONE, - // UINT8 TerminalType; - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, - // UINT8 Reserved2; - EFI_ACPI_RESERVED_BYTE, - // UINT16 PciDeviceId; - 0xFFFF, - // UINT16 PciVendorId; - 0xFFFF, - // UINT8 PciBusNumber; - 0x00, - // UINT8 PciDeviceNumber; - 0x00, - // UINT8 PciFunctionNumber; - 0x00, - // UINT32 PciFlags; - 0x00000000, - // UINT8 PciSegment; - 0x00, - // UINT32 Reserved3; - EFI_ACPI_RESERVED_DWORD -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc deleted file mode 100644 index 6850e42a4b9b6d48c9d8a3cc4c68bf006f4287ca..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - *. All rights reserved. - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - * Contributors: - * Yi Li - yi.li@linaro.org - * - * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -*/ - -#include -#include "Hi1620Platform.h" -#include -#include - - -// -// Static Resource Affinity Table definition -// -EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { - { - {EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, - sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE), - EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION}, - /*Reserved*/ - 0x00000001, // Reserved to be 1 for backward compatibility - EFI_ACPI_RESERVED_QWORD - }, - - // - // - // Memory Affinity - // - { - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - }, - - { - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 - - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000003F,0x00000001,0x00000000), //GICC Affinity Processor 63 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000040,0x00000001,0x00000000), //GICC Affinity Processor 64 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000041,0x00000001,0x00000000), //GICC Affinity Processor 65 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000042,0x00000001,0x00000000), //GICC Affinity Processor 66 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000043,0x00000001,0x00000000), //GICC Affinity Processor 67 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000044,0x00000001,0x00000000), //GICC Affinity Processor 68 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000045,0x00000001,0x00000000), //GICC Affinity Processor 69 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000046,0x00000001,0x00000000), //GICC Affinity Processor 70 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000047,0x00000001,0x00000000), //GICC Affinity Processor 71 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000048,0x00000001,0x00000000), //GICC Affinity Processor 72 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000049,0x00000001,0x00000000), //GICC Affinity Processor 73 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000004A,0x00000001,0x00000000), //GICC Affinity Processor 74 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000004B,0x00000001,0x00000000), //GICC Affinity Processor 75 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000004C,0x00000001,0x00000000), //GICC Affinity Processor 76 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000004D,0x00000001,0x00000000), //GICC Affinity Processor 77 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000004E,0x00000001,0x00000000), //GICC Affinity Processor 78 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000004F,0x00000001,0x00000000), //GICC Affinity Processor 79 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000050,0x00000001,0x00000000), //GICC Affinity Processor 80 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000051,0x00000001,0x00000000), //GICC Affinity Processor 81 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000052,0x00000001,0x00000000), //GICC Affinity Processor 82 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000053,0x00000001,0x00000000), //GICC Affinity Processor 83 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000054,0x00000001,0x00000000), //GICC Affinity Processor 84 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000055,0x00000001,0x00000000), //GICC Affinity Processor 85 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000056,0x00000001,0x00000000), //GICC Affinity Processor 86 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000057,0x00000001,0x00000000), //GICC Affinity Processor 87 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000058,0x00000001,0x00000000), //GICC Affinity Processor 88 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000059,0x00000001,0x00000000), //GICC Affinity Processor 89 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000005A,0x00000001,0x00000000), //GICC Affinity Processor 90 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000005B,0x00000001,0x00000000), //GICC Affinity Processor 91 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000005C,0x00000001,0x00000000), //GICC Affinity Processor 92 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000005D,0x00000001,0x00000000), //GICC Affinity Processor 93 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000005E,0x00000001,0x00000000), //GICC Affinity Processor 94 - EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000005F,0x00000001,0x00000000), //GICC Affinity Processor 95 - }, - { - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000000), - // EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000001), - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Srat; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc deleted file mode 100644 index 416200d56b016c5911b5cb4125da8ca2e00c8100..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc +++ /dev/null @@ -1,369 +0,0 @@ -/** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Hi1620Platform.h" - -#include -#include -#include -#include -#include - -// Differs from Juno, we have another affinity level beyond cluster and core -// 0x20000 is only for socket 0 -#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId)) - -// -// Multiple APIC Description Table -// -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicITS[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT]; -} EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE; - -#pragma pack () - -EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION - ), - // - // MADT specific fields - // - 0, // LocalApicAddress - 0, // Flags - }, - { - // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, - // GsivId, GicRBase, Mpidr) - // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v5.1). - // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses - // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 16, 16, PLATFORM_GET_MPID_TA(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x500000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 17, 17, PLATFORM_GET_MPID_TA(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x540000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 18, 18, PLATFORM_GET_MPID_TA(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x580000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 19, 19, PLATFORM_GET_MPID_TA(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x5C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 20, 20, PLATFORM_GET_MPID_TA(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x600000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 21, 21, PLATFORM_GET_MPID_TA(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x640000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 22, 22, PLATFORM_GET_MPID_TA(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x680000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 23, 23, PLATFORM_GET_MPID_TA(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAE000000 + 0x6C0000 /* GicRBase */, 0), - - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 24, 24, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 25, 25, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 26, 26, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 27, 27, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 28, 28, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 29, 29, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 30, 30, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 31, 31, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 32, 32, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 33, 33, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 34, 34, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 35, 35, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 36, 36, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 37, 37, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 38, 38, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 39, 39, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 40, 40, PLATFORM_GET_MPID_TB(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x500000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 41, 41, PLATFORM_GET_MPID_TB(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x540000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 42, 42, PLATFORM_GET_MPID_TB(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x580000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 43, 43, PLATFORM_GET_MPID_TB(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x5C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 44, 44, PLATFORM_GET_MPID_TB(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x600000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 45, 45, PLATFORM_GET_MPID_TB(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x640000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 46, 46, PLATFORM_GET_MPID_TB(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x680000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 47, 47, PLATFORM_GET_MPID_TB(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0xAA000000 + 0x6C0000 /* GicRBase */, 0), - - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 48, 48, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 49, 49, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 50, 50, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 51, 51, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 52, 52, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 53, 53, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 54, 54, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 55, 55, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 56, 56, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 57, 57, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 58, 58, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 59, 59, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 60, 60, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 61, 61, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 62, 62, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 63, 63, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 64, 64, PLATFORM_GET_MPID_TA_2(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x500000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 65, 65, PLATFORM_GET_MPID_TA_2(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x540000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 66, 66, PLATFORM_GET_MPID_TA_2(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x580000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 67, 67, PLATFORM_GET_MPID_TA_2(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x5C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 68, 68, PLATFORM_GET_MPID_TA_2(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x600000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 69, 69, PLATFORM_GET_MPID_TA_2(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x640000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 70, 70, PLATFORM_GET_MPID_TA_2(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x680000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 71, 71, PLATFORM_GET_MPID_TA_2(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AE000000 + 0x6C0000 /* GicRBase */, 0), - - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 72, 72, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x100000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 73, 73, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x140000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 74, 74, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x180000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 75, 75, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x1C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 76, 76, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x200000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 77, 77, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x240000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 78, 78, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x280000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 79, 79, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x2C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 80, 80, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x300000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 81, 81, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x340000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 82, 82, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x380000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 83, 83, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x3C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 84, 84, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x400000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 85, 85, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x440000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 86, 86, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x480000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 87, 87, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x4C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 88, 88, PLATFORM_GET_MPID_TB_2(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x500000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 89, 89, PLATFORM_GET_MPID_TB_2(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x540000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 90, 90, PLATFORM_GET_MPID_TB_2(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x580000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 91, 91, PLATFORM_GET_MPID_TB_2(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x5C0000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 92, 92, PLATFORM_GET_MPID_TB_2(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x600000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 93, 93, PLATFORM_GET_MPID_TB_2(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x640000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 94, 94, PLATFORM_GET_MPID_TB_2(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x680000 /* GicRBase */, 0), - EFI_ACPI_6_1_GICC_STRUCTURE_INIT( - 95, 95, PLATFORM_GET_MPID_TB_2(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - 0x0, 0x0, 25, 0x4000AA000000 + 0x6C0000 /* GicRBase */, 0), - }, - - EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, 0xAE000000, 0, 0x4), - { - EFI_ACPI_6_1_GIC_ITS_INIT(0,0x202100000), //peri a -// EFI_ACPI_6_1_GIC_ITS_INIT(1,0x400202100000), //peri a - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr deleted file mode 100644 index 9bd4e775028ea033efa30a132228054ed02a0bea..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr +++ /dev/null @@ -1,148 +0,0 @@ -/** @file -* -* Memory Config form at Oem Config fromset. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -form formid = MEMORY_CONFIG_FORM_ID, - title = STRING_TOKEN(STR_MEMORY_CONFIG_FORM_TITLE); - - oneof varid = OEM_CONFIG_DATA.DdrDebugLevel, - prompt = STRING_TOKEN (STR_MEM_PRINT_LEVEL_PROMPT), - help = STRING_TOKEN (STR_MEM_PRINT_LEVEL_HELP), - option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_MINIMUM), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_MINMAX), value = 2, flags = RESET_REQUIRED; - option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_MAXIMUM), value = 3, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.DdrFreqLimit, - prompt = STRING_TOKEN(STR_XMP_DDR_FREQ_LIMIT_PROMPT), - help = STRING_TOKEN(STR_XMP_DDR_FREQ_LIMIT_HELP), - option text = STRING_TOKEN(STR_AUTO), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_DDR_FREQ_1333_STRING), value = 5, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_DDR_FREQ_1600_STRING), value = 7, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_DDR_FREQ_1866_STRING), value = 9, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_DDR_FREQ_2133_STRING), value = 11, flags = RESET_REQUIRED ; - option text = STRING_TOKEN(STR_DDR_FREQ_2400_STRING), value = 13, flags = RESET_REQUIRED ; - option text = STRING_TOKEN(STR_DDR_FREQ_2667_STRING), value = 15, flags = RESET_REQUIRED ; - option text = STRING_TOKEN(STR_DDR_FREQ_2933_STRING), value = 17, flags = RESET_REQUIRED ; - option text = STRING_TOKEN(STR_DDR_FREQ_3200_STRING), value = 19, flags = RESET_REQUIRED ; - endoneof; - - suppressif TRUE; - oneof varid = OEM_CONFIG_DATA.DdrRefreshSupport, - prompt = STRING_TOKEN(STR_DDR_REFRESH_SUPPORT_PROMPT), - help = STRING_TOKEN(STR_DDR_REFRESH_SUPPORT_HELP), - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - endoneof; - - suppressif ideqval OEM_CONFIG_DATA.DdrRefreshSupport == 0; - oneof varid = OEM_CONFIG_DATA.DdrRefreshRate, - prompt = STRING_TOKEN(STR_DDR_REFRESH_PROMPT), - help = STRING_TOKEN(STR_DDR_REFRESH_HELP), - option text = STRING_TOKEN(STR_32MS), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_64MS), value = 1, flags = RESET_REQUIRED; - endoneof; - endif; - - oneof varid = OEM_CONFIG_DATA.RankMargin, - prompt = STRING_TOKEN (STR_RMT_PROMPT), - help = STRING_TOKEN (STR_RMT_HELP), - option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED; - option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - suppressif ideqval OEM_CONFIG_DATA.RankMargin == 0; - oneof varid = OEM_CONFIG_DATA.RankMarginMode, - prompt = STRING_TOKEN (STR_RMTM_PROMPT), - help = STRING_TOKEN (STR_RMTM_HELP), - option text = STRING_TOKEN (STR_RMTM_SFC), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN (STR_RMTM_EXMBIST), value = 2, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED; - endoneof; - - numeric varid = OEM_CONFIG_DATA.rmtPatternLength, - prompt = STRING_TOKEN (STR_RMT_PATTERN_PROMPT), - help = STRING_TOKEN (STR_RMT_PATTERN_HELP), - flags = RESET_REQUIRED, - minimum = 1, - maximum = 32767, - step = 1, - default = RMT_PATTERN_LENGTH, - endnumeric; - - oneof varid = OEM_CONFIG_DATA.perbitmargin, - prompt = STRING_TOKEN (STR_PER_BIT_MARGIN_PROMPT), - help = STRING_TOKEN (STR_PER_BIT_MARGIN_HELP), - option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.CaMargin, - prompt = STRING_TOKEN (STR_CA_MARGINS_PROMPT), - help = STRING_TOKEN (STR_CA_MARGINS_HELP), - option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.CaVrefMarginOption, - prompt = STRING_TOKEN (STR_CAVREF_MARGINS_PROMPT), - help = STRING_TOKEN (STR_CAVREF_MARGINS_HELP), - option text = STRING_TOKEN (STR_CAVREF_MARGINS_OPTION0), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN (STR_CAVREF_MARGINS_OPTION2), value = 1, flags = RESET_REQUIRED; - endoneof; - endif; - - oneof varid = OEM_CONFIG_DATA.DieInterleaving, - prompt = STRING_TOKEN(STR_DIE_INTERLEAVING_PROMPT), - help = STRING_TOKEN(STR_DIE_INTERLEAVING_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.ChannelInterleaving, - prompt = STRING_TOKEN(STR_CHANNEL_INTERLEAVING_PROMPT), - help = STRING_TOKEN(STR_CHANNEL_INTERLEAVING_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - endoneof; - - oneof varid = OEM_CONFIG_DATA.RankInterleaving, - prompt = STRING_TOKEN(STR_RANK_INTERLEAVING_PROMPT), - help = STRING_TOKEN(STR_RANK_INTERLEAVING_HELP), - option text = STRING_TOKEN(STR_1WAY_STRING), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_2WAY_STRING), value = 2, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_4WAY_STRING), value = 4, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.NumaEn, - prompt = STRING_TOKEN(STR_NUMA_PROMPT), - help = STRING_TOKEN(STR_NUMA_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - endoneof; - - oneof varid = OEM_CONFIG_DATA.HwMemTest, - prompt = STRING_TOKEN (STR_MEM_TEST_PROMPT), - help = STRING_TOKEN (STR_MEM_TEST_HELP), - option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.EccSupport, - prompt = STRING_TOKEN (STR_ECC_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_ECC_SUPPORT_HELP), - option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN (STR_ECC_EN), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN (STR_SDEC_EN), value = 2, flags = RESET_REQUIRED; - endoneof; - endif; - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni deleted file mode 100644 index 025bb25a61423f5922e4743ce728c30afb8e6e10..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni +++ /dev/null @@ -1,97 +0,0 @@ -/** @file -* -* String definitions for the Memory Config. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -/=# - -#langdef en-US "English" - -#string STR_MEMORY_CONFIG_FORM_TITLE #language en-US "Memory Configuration" -#string STR_MEMORY_CONFIG_FORM_HELP #language en-US "Displays and provides option to change the Memory Settings" -#string STR_MEMORY_RAS_CONFIG_FORM_TITLE #language en-US "Memory RAS Configuration" -#string STR_MEMORY_RAS_CONFIG_FORM_HELP #language en-US "Displays and provides option to change the Ras Configuration" -#string STR_MEM_PRINT_LEVEL_PROMPT #language en-US "Memory Print Level" -#string STR_MEM_PRINT_LEVEL_HELP #language en-US "Memory Print Level Set. Disable: Do not print any MRC statement/ Minimum: Print the most important(High level) MRC statement/ Minmax: Print the Mid-important(Mid level) and most important MRC statement/ Maximum: Print all of the MRC statement" -#string STR_ENABLE #language en-US "Enabled" -#string STR_DISABLE #language en-US "Disabled" - -#string STR_MEM_PRINT_LEVEL_MINIMUM #language en-US "Minimum" -#string STR_MEM_PRINT_LEVEL_MINMAX #language en-US "Minmax" -#string STR_MEM_PRINT_LEVEL_MAXIMUM #language en-US "Maximum" -#string STR_MEM_PRINT_LEVEL_DISABLE #language en-US "Disable" - -#string STR_XMP_DDR_FREQ_LIMIT_PROMPT #language en-US "Memory Frequency" -#string STR_XMP_DDR_FREQ_LIMIT_HELP #language en-US "Maximum Memory Frequency Selections in Mhz. Do not select Reserved" -#string STR_AUTO #language en-US "Auto" -#string STR_DDR_FREQ_1333_STRING #language en-US "1333" -#string STR_DDR_FREQ_1600_STRING #language en-US "1600" -#string STR_DDR_FREQ_1866_STRING #language en-US "1866" -#string STR_DDR_FREQ_2133_STRING #language en-US "2133" -#string STR_DDR_FREQ_2400_STRING #language en-US "2400" -#string STR_DDR_FREQ_2600_STRING #language en-US "2600" -#string STR_DDR_FREQ_2667_STRING #language en-US "2667" -#string STR_DDR_FREQ_2800_STRING #language en-US "2800" -#string STR_DDR_FREQ_2933_STRING #language en-US "2993" -#string STR_DDR_FREQ_3000_STRING #language en-US "3000" -#string STR_DDR_FREQ_3200_STRING #language en-US "3200" - -#string STR_DDR_REFRESH_SUPPORT_PROMPT #language en-US "Custom Refresh Enable" -#string STR_DDR_REFRESH_SUPPORT_HELP #language en-US "Memory Custom Refresh Enable " -#string STR_DDR_REFRESH_PROMPT #language en-US "Custom Refresh Rate" -#string STR_DDR_REFRESH_HELP #language en-US "Memory Custom Refresh Rate " -#string STR_32MS #language en-US "32ms" -#string STR_64MS #language en-US "64ms" - -#string STR_RMT_PROMPT #language en-US "Rank Margin Tool" -#string STR_RMT_HELP #language en-US "Enable the rank margin tool to run after DDR memory training" -#string STR_RMTM_PROMPT #language en-US "Rank Margin Mode" -#string STR_RMTM_HELP #language en-US "Select test mode for rank margin test" -#string STR_RMTM_SFC #language en-US "SFC" -#string STR_RMTM_EXMBIST #language en-US "EXMBIST" -#string STR_RMT_PATTERN_PROMPT #language en-US "RMT Pattern Length" -#string STR_RMT_PATTERN_HELP #language en-US "Set the pattern length(1-32767) for the Rank Margin Tool" -#string STR_PER_BIT_MARGIN_PROMPT #language en-US "Per Bit Margin" -#string STR_PER_BIT_MARGIN_HELP #language en-US "Enables the logging from the serial port of DDR Per Bit Margin Data" -#string STR_CA_MARGINS_PROMPT #language en-US "CA Margin" -#string STR_CA_MARGINS_HELP #language en-US "Enables CA margin" -#string STR_CAVREF_MARGINS_PROMPT #language en-US "CAVref Margin" -#string STR_CAVREF_MARGINS_HELP #language en-US "CAVref margin Options" -#string STR_CAVREF_MARGINS_OPTION0 #language en-US "VDD/2^2 connected to QVrefVA and BVrefCA" -#string STR_CAVREF_MARGINS_OPTION2 #language en-US "Internally generated Vref connected to QVrefCA^3 VDD/2^2 connected to BVrefCA" - -#string STR_DIE_INTERLEAVING_PROMPT #language en-US "Die Interleaving" -#string STR_DIE_INTERLEAVING_HELP #language en-US "Select Die Interleaving setting" -#string STR_CHANNEL_INTERLEAVING_PROMPT #language en-US "Channel Interleaving" -#string STR_CHANNEL_INTERLEAVING_HELP #language en-US "Select Channel Interleaving setting" -#string STR_RANK_INTERLEAVING_PROMPT #language en-US "Rank Interleaving" -#string STR_RANK_INTERLEAVING_HELP #language en-US "Select Rank Interleaving setting" - -#string STR_1WAY_STRING #language en-US "1-way Interleave" -#string STR_2WAY_STRING #language en-US "2-way Interleave" -#string STR_3WAY_STRING #language en-US "3-way Interleave" -#string STR_4WAY_STRING #language en-US "4-way Interleave" -#string STR_6WAY_STRING #language en-US "6-way Interleave" -#string STR_8WAY_STRING #language en-US "8-way Interleave" - -#string STR_NUMA_PROMPT #language en-US "NUMA" -#string STR_NUMA_HELP #language en-US "Enable or Disable Non uniform Memory Access (NUMA)." - -#string STR_MEM_TEST_PROMPT #language en-US "Memory Test" -#string STR_MEM_TEST_HELP #language en-US "Enable/disable memory test during normal boot" - -#string STR_ECC_SUPPORT_PROMPT #language en-US "ECC/SDEC Support" -#string STR_ECC_SUPPORT_HELP #language en-US "Enable/disable DDR Ecc/SDEC Support" -#string STR_ECC_EN #language en-US "Ecc Enable" -#string STR_SDEC_EN #language en-US "SDEC Enable" - - - - - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr deleted file mode 100644 index 1abdc4696f83c8b6fff318930af58382b60533f9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr +++ /dev/null @@ -1,35 +0,0 @@ -/** @file -* -* Misc Config form at Oem Config fromset. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -form formid = MISC_CONFIG_FORM_ID, - title = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE); - - oneof varid = OEM_CONFIG_DATA.EnableSmmu, - prompt = STRING_TOKEN(STR_OEM_TABLE), - help = STRING_TOKEN(STR_OEM_CONFIG_HELP), - option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = 0; - option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = DEFAULT; - endoneof; - - oneof varid = OEM_CONFIG_DATA.EnableFdtTable, - prompt = STRING_TOKEN(STR_FDT_TABLE), - help = STRING_TOKEN(STR_FDT_CONFIG_HELP), - option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT; - option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = 0; - endoneof; - - oneof varid = OEM_CONFIG_DATA.EnableGOP, - prompt = STRING_TOKEN(STR_ENABLE_GOP_FRAME_BUFFER), - help = STRING_TOKEN(STR_ENABLE_GOP_FRAME_BUFFER_HELP), - option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT; - option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = 0; - endoneof; - -endform; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni deleted file mode 100644 index 98c946e0c8273456a06f05057513bfa4332bff24..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni +++ /dev/null @@ -1,21 +0,0 @@ -/** @file -* -* String definitions for the Misc Config form. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#langdef en-US "English" - -#string STR_OEM_TABLE #language en-US "Support Smmu" -#string STR_OEM_CONFIG_HELP #language en-US "Enable or Disable Smmu." -#string STR_FDT_TABLE #language en-US "Install DTB Table" -#string STR_FDT_CONFIG_HELP #language en-US "Enable or Disable Fdt Table." -#string STR_ENABLE_SPCR_TABLE #language en-US "Support SPCR" -#string STR_ENABLE_SPCR_HELP #language en-US "Enable or Disable SPCR Table." -#string STR_ENABLE_GOP_FRAME_BUFFER #language en-US "Support GOP FB for SM750" -#string STR_ENABLE_GOP_FRAME_BUFFER_HELP #language en-US "Enable or Disable GOP frame buffer for SM750." diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c deleted file mode 100644 index 4efebc17ee2c341db033f8aff2c765bdfcceea81..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ /dev/null @@ -1,357 +0,0 @@ -/** @file -The OEM config reference implementation - -Copyright (c) 2018, Hisilicon Limited. All rights reserved. -Copyright (c) 2018, Linaro Limited. All rights reserved. -SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "OemConfig.h" - -OEM_CONFIG_CALLBACK_DATA mOemConfigPrivate = { - OEM_CONFIG_CALLBACK_DATA_SIGNATURE, - NULL, - NULL, - { - OemExtractConfig, - OemRouteConfig, - OemCallback - } -}; - -HII_VENDOR_DEVICE_PATH mOemHiiVendorDevicePath = { - { - { - HARDWARE_DEVICE_PATH, - HW_VENDOR_DP, - { - (UINT8) (sizeof (VENDOR_DEVICE_PATH)), - (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) - } - }, - { 0x874c4dcb, 0x08ec, 0x4fe6, { 0xb5, 0x8e, 0x3a, 0x9e, 0x1c, 0x26, 0x70, 0xb9 } } - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - (UINT8) (END_DEVICE_PATH_LENGTH), - (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8) - } - } -}; - - - - - - -/** - This function allows a caller to extract the current configuration for one - or more named elements from the target driver. - - - @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. - @param Request A null-terminated Unicode string in format. - @param Progress On return, points to a character in the Request string. - Points to the string's null terminator if request was successful. - Points to the most recent '&' before the first failing name/value - pair (or the beginning of the string if the failure is in the - first name/value pair) if the request was not successful. - @param Results A null-terminated Unicode string in format which - has all values filled in for the names in the Request string. - String to be allocated by the called function. - - @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name. - @retval EFI_NOT_FOUND Routing data doesn't match any storage in this driver. - -**/ -EFI_STATUS -EFIAPI -OemExtractConfig ( - IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, - IN CONST EFI_STRING Request, - OUT EFI_STRING *Progress, - OUT EFI_STRING *Results - ) -{ - if (Progress == NULL || Results == NULL) { - return EFI_INVALID_PARAMETER; - } - *Progress = Request; - return EFI_NOT_FOUND; -} - -/** - This function processes the results of changes in configuration. - - @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. - @param Configuration A null-terminated Unicode string in format. - @param Progress A pointer to a string filled in with the offset of the most - recent '&' before the first failing name/value pair (or the - beginning of the string if the failure is in the first - name/value pair) or the terminating NULL if all was successful. - - @retval EFI_INVALID_PARAMETER Configuration is NULL. - @retval EFI_NOT_FOUND Routing data doesn't match any storage in this driver. - -**/ -EFI_STATUS -EFIAPI -OemRouteConfig ( - IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, - IN CONST EFI_STRING Configuration, - OUT EFI_STRING *Progress - ) -{ - if (Configuration == NULL || Progress == NULL) { - return EFI_INVALID_PARAMETER; - } - - *Progress = Configuration; - - return EFI_NOT_FOUND; -} - -/** - This function is invoked if user selected a interactive opcode from Device Manager's - Formset. If user set VBIOS, the new value is saved to EFI variable. - - @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. - @param Action Specifies the type of action taken by the browser. - @param QuestionId A unique value which is sent to the original exporting driver - so that it can identify the type of data to expect. - @param Type The type of value for the question. - @param Value A pointer to the data being sent to the original exporting driver. - @param ActionRequest On return, points to the action requested by the callback function. - - @retval EFI_SUCCESS The callback successfully handled the action. - @retval EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters. - -**/ -EFI_STATUS -EFIAPI -OemCallback ( - IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, - IN EFI_BROWSER_ACTION Action, - IN EFI_QUESTION_ID QuestionId, - IN UINT8 Type, - IN EFI_IFR_TYPE_VALUE *Value, - OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest - ) -{ - if (Action != EFI_BROWSER_ACTION_CHANGING) { - // - // Do nothing for other UEFI Action. Only do call back when data is changed. - // - return EFI_UNSUPPORTED; - } - if ((Value == NULL) || (ActionRequest == NULL)) { - return EFI_INVALID_PARAMETER; - } - - return EFI_SUCCESS; -} - -/** - Install Boot Manager Menu driver. - - @param ImageHandle The image handle. - @param SystemTable The system table. - - @retval EFI_SUCEESS Install Boot manager menu success. - @retval Other Return error status. - -**/ -EFI_STATUS -EFIAPI -OemConfigUiLibConstructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - OEM_CONFIG_DATA Configuration; - VOID *Hob; - VERSION_INFO *VersionInfo; - UINTN BufSize; - BOOLEAN Action; - EFI_STRING ConfigRequestHdr; - EFI_TIME Time = {0}; - CHAR16 TmpString[0x100] = {0}; - - mOemConfigPrivate.DriverHandle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces ( - &mOemConfigPrivate.DriverHandle, - &gEfiDevicePathProtocolGuid, - &mOemHiiVendorDevicePath, - &gEfiHiiConfigAccessProtocolGuid, - &mOemConfigPrivate.ConfigAccess, - NULL - ); - if (EFI_ERROR (Status)) { - return Status; - } - - // - // Publish our HII data. - // - mOemConfigPrivate.HiiHandle = HiiAddPackages ( - &gOemConfigGuid, - mOemConfigPrivate.DriverHandle, - OemConfigVfrBin, - OemConfigUiLibStrings, - NULL - ); - if (mOemConfigPrivate.HiiHandle == NULL) { - DEBUG ((DEBUG_ERROR, "%a Fail to Add Oem Hii Package.\n", __func__)); - return EFI_INVALID_PARAMETER; - } - // - //BIOS Build Time Init - // - Hob = GetFirstGuidHob (&gVersionInfoHobGuid); - if (Hob == NULL) { - DEBUG ((DEBUG_ERROR, "[%a]:[%d] Version information HOB not found!\n", - __FILE__, __LINE__)); - return EFI_NOT_FOUND; - } - VersionInfo = GET_GUID_HOB_DATA (Hob); - Time = VersionInfo->BuildTime; - UnicodeSPrint ( - TmpString, - sizeof (TmpString), - L"%02d/%02d/%04d %02d:%02d", - Time.Month, - Time.Day, - Time.Year, - Time.Hour, - Time.Minute - ); - HiiSetString ( - mOemConfigPrivate.HiiHandle, - STRING_TOKEN (STR_MISC_BIOS_BUILDTIME), - TmpString, - "en-US" - ); - // - // Check Oem Config Variable. - // - ConfigRequestHdr = HiiConstructConfigHdr ( - &gOemConfigGuid, - OEM_CONFIG_NAME, - mOemConfigPrivate.DriverHandle - ); - ZeroMem (&Configuration, sizeof (OEM_CONFIG_DATA)); - BufSize = sizeof (OEM_CONFIG_DATA); - Status = gRT->GetVariable ( - OEM_CONFIG_NAME, - &gOemConfigGuid, - NULL, - &BufSize, - &Configuration - ); - if (EFI_ERROR (Status)) { - Action = HiiSetToDefaults (ConfigRequestHdr, EFI_HII_DEFAULT_CLASS_STANDARD); - if (!Action) { - // - //Set the default value of the DDR option - // - Configuration.DdrDebugLevel = 0; - Configuration.DdrFreqLimit = 0; - Configuration.DdrRefreshSupport = 0; - Configuration.DdrRefreshRate = 0; - Configuration.RankMargin = 0; - Configuration.RankMarginMode = 2; - Configuration.rmtPatternLength = 256; - Configuration.perbitmargin = 0x0; - Configuration.CaMargin = 0x0; - Configuration.CaVrefMarginOption = 0x0; - Configuration.NumaEn = 1; - Configuration.HwMemTest = 0; - Configuration.DieInterleaving = 0; - Configuration.ChannelInterleaving = 1; - Configuration.RankInterleaving = 2; - Configuration.EccSupport = 0; - // - //Set the default value of the BMC option - // - Configuration.BmcWdtEnable = 0; - Configuration.BmcWdtTimeout = 15; - Configuration.BmcWdtAction = 1; - Configuration.OSWdtEnable = 0; - Configuration.OSWdtTimeout = 5; - Configuration.OSWdtAction = 1; - // - //Set the default value of the Misc option - // - Configuration.EnableSmmu = 1; - Configuration.EnableFdtTable = 0; - Configuration.EnableGOP = 0; - // - //Set the default value of the Ras option - // - Configuration.EnRasSupport = 1; - Configuration.EnPoison = 1; - Configuration.CheckAlgorithm = 0; - Configuration.PatrolScrub = 1; - Configuration.PatrolScrubDuration = 24; - Configuration.DemandScrubMode = 0; - Configuration.CorrectErrorThreshold = 0; - Configuration.AdvanceDeviceCorrection = 0; - Configuration.RankSparing = 0; - Configuration.FunnelPeriod = 0; - Configuration.DpcFeature = 0; - Configuration.EcrcFeature = 0; - Configuration.CompletionTimeout = 1; - Configuration.CompletionTimeoutValue = 0; - Configuration.HotPlug = 1; - Status = gRT->SetVariable ( - OEM_CONFIG_NAME, - &gOemConfigGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, - sizeof (OEM_CONFIG_DATA), - &Configuration - ); - } - } else { - Action = HiiValidateSettings (ConfigRequestHdr); - if (!Action) { - return EFI_INVALID_PARAMETER; - } - } - return EFI_SUCCESS; -} - -/** - Unloads the application and its installed protocol. - - @param ImageHandle Handle that identifies the image to be unloaded. - @param SystemTable The system table. - - @retval EFI_SUCCESS The image has been unloaded. -**/ -EFI_STATUS -EFIAPI -OemConfigUiLibDestructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - Status = gBS->UninstallMultipleProtocolInterfaces ( - mOemConfigPrivate.DriverHandle, - &gEfiDevicePathProtocolGuid, - &mOemHiiVendorDevicePath, - &gEfiHiiConfigAccessProtocolGuid, - &mOemConfigPrivate.ConfigAccess, - NULL - ); - - HiiRemovePackages (mOemConfigPrivate.HiiHandle); - - return Status; -} - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h deleted file mode 100644 index ea4dfc5b1a62d1fc997bc9da9da27642cefce72c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h +++ /dev/null @@ -1,136 +0,0 @@ -/** @file -The Oem config reference implement - -Copyright (c) 2018, Hisilicon Limited. All rights reserved. -Copyright (c) 2018, Linaro Limited. All rights reserved. -SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _OEM_CONFIG_H_ -#define _OEM_CONFIG_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "Library/OemConfigData.h" -#include -#include -#include -#include -#include -#include -#include - -// -// These are the VFR compiler generated data representing our VFR data. -// -extern UINT8 OemConfigVfrBin[]; - -// -// HII specific Vendor Device Path definition. -// -typedef struct { - VENDOR_DEVICE_PATH VendorDevicePath; - EFI_DEVICE_PATH_PROTOCOL End; -} HII_VENDOR_DEVICE_PATH; - -#define OEM_CONFIG_CALLBACK_DATA_SIGNATURE SIGNATURE_32 ('O', 'E', 'M', 'C') -typedef struct { - UINTN Signature; - EFI_HII_HANDLE HiiHandle; - EFI_HANDLE DriverHandle; - EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess; -} OEM_CONFIG_CALLBACK_DATA; - -/** - This function allows a caller to extract the current configuration for one - or more named elements from the target driver. - - - @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. - @param Request A null-terminated Unicode string in format. - @param Progress On return, points to a character in the Request string. - Points to the string's null terminator if request was successful. - Points to the most recent '&' before the first failing name/value - pair (or the beginning of the string if the failure is in the - first name/value pair) if the request was not successful. - @param Results A null-terminated Unicode string in format which - has all values filled in for the names in the Request string. - String to be allocated by the called function. - - @retval EFI_SUCCESS The Results is filled with the requested values. - @retval EFI_OUT_OF_RESOURCES Not enough memory to store the results. - @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name. - @retval EFI_NOT_FOUND Routing data doesn't match any storage in this driver. - -**/ -EFI_STATUS -EFIAPI -OemExtractConfig ( - IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, - IN CONST EFI_STRING Request, - OUT EFI_STRING *Progress, - OUT EFI_STRING *Results - ); - -/** - This function processes the results of changes in configuration. - - - @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. - @param Configuration A null-terminated Unicode string in format. - @param Progress A pointer to a string filled in with the offset of the most - recent '&' before the first failing name/value pair (or the - beginning of the string if the failure is in the first - name/value pair) or the terminating NULL if all was successful. - - @retval EFI_SUCCESS The Results is processed successfully. - @retval EFI_INVALID_PARAMETER Configuration is NULL. - @retval EFI_NOT_FOUND Routing data doesn't match any storage in this driver. - -**/ -EFI_STATUS -EFIAPI -OemRouteConfig ( - IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, - IN CONST EFI_STRING Configuration, - OUT EFI_STRING *Progress - ); - -/** - This function is invoked if user selected a interactive opcode from Device Manager's - Formset. If user set VBIOS, the new value is saved to EFI variable. - - @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. - @param Action Specifies the type of action taken by the browser. - @param QuestionId A unique value which is sent to the original exporting driver - so that it can identify the type of data to expect. - @param Type The type of value for the question. - @param Value A pointer to the data being sent to the original exporting driver. - @param ActionRequest On return, points to the action requested by the callback function. - - @retval EFI_SUCCESS The callback successfully handled the action. - @retval EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters. - -**/ -EFI_STATUS -EFIAPI -OemCallback ( - IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, - IN EFI_BROWSER_ACTION Action, - IN EFI_QUESTION_ID QuestionId, - IN UINT8 Type, - IN EFI_IFR_TYPE_VALUE *Value, - OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest - ); - -VOID GetReleaseTime (EFI_TIME *Time); -#endif diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h deleted file mode 100644 index 1e962de1ecaabd8c7a71ade97a6387aea9b4909b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h +++ /dev/null @@ -1,58 +0,0 @@ -/** @file - -Copyright (c) 2018, Hisilicon Limited. All rights reserved. -Copyright (c) 2018, Linaro Limited. All rights reserved. -SPDX-License-Identifier: BSD-2-Clause-Patent - -Module Name: - - OemConfigUi.h - -Abstract: - - NVData structure used by the OEM Config. - -Revision History: - - -**/ - -#ifndef _OEM_CONFIG_UI_H_ -#define _OEM_CONFIG_UI_H_ - -#include - -#define OEM_CONFIG_FORM_ID 1 -#define MEMORY_CONFIG_FORM_ID 2 -#define IBMC_CONFIG_FORM_ID 3 -#define PCIE_CONFIG_FORM_ID 4 -#define MISC_CONFIG_FORM_ID 5 -#define RAS_CONFIG_FORM_ID 6 - -#define VFR_FORMID_PCIE_SOCKET0 0x4100 -#define VFR_FORMID_PCIE_SOCKET1 0x4200 -#define VFR_FORMID_PCIE_PORT0 0x4000 -#define VFR_FORMID_PCIE_PORT1 0x4001 -#define VFR_FORMID_PCIE_PORT2 0x4002 -#define VFR_FORMID_PCIE_PORT3 0x4003 -#define VFR_FORMID_PCIE_PORT4 0x4004 -#define VFR_FORMID_PCIE_PORT5 0x4005 -#define VFR_FORMID_PCIE_PORT6 0x4006 -#define VFR_FORMID_PCIE_PORT7 0x4007 -#define VFR_FORMID_PCIE_PORT8 0x4008 -#define VFR_FORMID_PCIE_PORT9 0x4009 -#define VFR_FORMID_PCIE_PORT10 0x4010 -#define VFR_FORMID_PCIE_PORT11 0x4011 -#define VFR_FORMID_PCIE_PORT12 0x4012 -#define VFR_FORMID_PCIE_PORT13 0x4013 -#define VFR_FORMID_PCIE_PORT14 0x4014 -#define VFR_FORMID_PCIE_PORT15 0x4015 - -#define VFR_FORMID_MEMORY_RAS 0x6100 -#define VFR_FORMID_CORRECT_ERROR 0x6101 -#define VFR_FORMID_PCIE_RAS 0x6200 - -#define RMT_PATTERN_LENGTH 256 - - -#endif diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf deleted file mode 100644 index 73d0ab2a95eff9b9d9db7b538121d970792d1092..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf +++ /dev/null @@ -1,62 +0,0 @@ -## @file -# OEM config Library used by BDS -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = OemConfigUiLib - MODULE_UNI_FILE = OemConfigUiLib.uni - FILE_GUID = 32B373AC-00B6-471b-B3AE-6E4A4501F6BA - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = NULL|DXE_DRIVER UEFI_APPLICATION - CONSTRUCTOR = OemConfigUiLibConstructor - DESTRUCTOR = OemConfigUiLibDestructor - -[Sources] - iBMCConfig.hfr - iBMCConfig.uni - MemoryConfig.hfr - MemoryConfig.uni - MiscConfig.hfr - MiscConfig.uni - OemConfig.c - OemConfig.h - OemConfigUiLibStrings.uni - OemConfigVfr.vfr - PcieConfig.hfr - PcieConfigStrings.uni - PciePortConfig.hfr - RasConfig.hfr - RasConfig.uni - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - DevicePathLib - HiiLib - MemoryAllocationLib - PrintLib - UefiBootServicesTableLib - UefiHiiServicesLib - UefiRuntimeServicesTableLib - -[Guids] - gEfiHiiPlatformSetupFormsetGuid ## CONSUMES ## GUID (Indicate the formset class guid to be displayed) - gEfiIfrFrontPageGuid ## CONSUMES ## GUID (Indicate the formset in this library need to dispaly in which page) - gEfiIfrTianoGuid ## CONSUMES ## GUID (Extended IFR Guid Opcode) - gOemConfigGuid - gVersionInfoHobGuid - -[Protocols] - gEfiHiiConfigAccessProtocolGuid ## CONSUMES diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni deleted file mode 100644 index 5a285d62f0f869afcd1a756fd325c45fea216d48..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni +++ /dev/null @@ -1,18 +0,0 @@ -/** @file -* -* OEM Config Library used by UiApp -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#string STR_MODULE_ABSTRACT -#language en-US "OEM Config Library used by BDS" - -#string STR_MODULE_DESCRIPTION -#language en-US "OEM Config Library used by BDS" - - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni deleted file mode 100644 index 3e5896ebe2fc8107e9c4c7caa96bc50e91d2267e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni +++ /dev/null @@ -1,36 +0,0 @@ -/** @file -* -* String definitions for the OEM Config. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -/=# - -#langdef en-US "English" - -#string STR_EMPTY_STRING #language en-US "" -#string STR_BIOS_BUILDTIME_STRING #language en-US "Build Date" -#string STR_MISC_BIOS_BUILDTIME #language en-US "" -#string SYSTEM_TIME #language en-US "System Time" -#string SYSTEM_TIME_HELP #language en-US "System Time (HH:MM:SS)" -#string SYSTEM_DATE #language en-US "System Date" -#string SYSTEM_DATE_HELP #language en-US "System Date (MM/DD/YYYY) Use [ENTER],[TAB] or [SHIFT-TAB] to select a field. Use [+] or [-] to configure system Time." -#string STR_OEM_CONFIG #language en-US "Oem Config" -#string STR_ENABLED #language en-US "Enabled" -#string STR_DISABLED #language en-US "Disabled" -#string STR_MEMORY_CONFIG_FORM_TITLE #language en-US "Memory Config" -#string STR_MEMORY_CONFIG_FORM_HELP #language en-US "Display Memory DIMM information." -#string STR_PCIE_CONFIG_FORM_TITLE #language en-US "PCIe Config" -#string STR_PCIE_CONFIG_FORM_HELP #language en-US "Display PCIe information." -#string STR_MISC_CONFIG_FORM_TITLE #language en-US "MISC Config" -#string STR_MISC_CONFIG_FORM_HELP #language en-US "Include SMMU Support Enable and Change the boot manner of DTB/ACPI." -#string STR_IBMC_CONFIG_FORM_TITLE #language en-US "IBMC Config" -#string STR_IBMC_CONFIG_FORM_HELP #language en-US "Include IBMC WDT(Watchdog Timer) Config." -#string STR_RAS_CONFIG_FORM_TITLE #language en-US "RAS Config" -#string STR_RAS_CONFIG_FORM_HELP #language en-US "Displays and provides option to change the Ras Configuration" -#string STR_EXIT_STRING #language en-US "Press ESC to exit." diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr deleted file mode 100644 index 1c0f83d4ae48e5216f81ba8a1d4fc0be34924831..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ /dev/null @@ -1,83 +0,0 @@ -/** @file -* -* OEM Config formset. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -#include "OemConfigUi.h" -#include "Library/OemConfigData.h" - -formset - guid = gOemConfigGuid, - title = STRING_TOKEN(STR_OEM_CONFIG), - help = STRING_TOKEN(STR_OEM_CONFIG), - classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. - efivarstore OEM_CONFIG_DATA, - attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, - name = OemConfig, - guid = gOemConfigGuid; - - form formid = OEM_CONFIG_FORM_ID, - title = STRING_TOKEN(STR_OEM_CONFIG); - - grayoutif TRUE; - text - help = STRING_TOKEN(STR_EMPTY_STRING), - text = STRING_TOKEN(STR_BIOS_BUILDTIME_STRING), - text = STRING_TOKEN(STR_MISC_BIOS_BUILDTIME), - flags = 0, - key = 0; - endif; - - date - prompt = STRING_TOKEN(SYSTEM_DATE), - help = STRING_TOKEN(SYSTEM_DATE_HELP), - flags = 0x10, - default = 2017/1/1, - enddate; - - time - prompt = STRING_TOKEN(SYSTEM_TIME), - help = STRING_TOKEN(SYSTEM_TIME_HELP), - flags = 0x10, - endtime; - - subtitle text = STRING_TOKEN(STR_EMPTY_STRING); - - goto MEMORY_CONFIG_FORM_ID, - prompt = STRING_TOKEN(STR_MEMORY_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_MEMORY_CONFIG_FORM_HELP); - - goto IBMC_CONFIG_FORM_ID, - prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP); - - suppressif TRUE; - goto PCIE_CONFIG_FORM_ID, - prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif; - - goto MISC_CONFIG_FORM_ID, - prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_MISC_CONFIG_FORM_HELP); - - goto RAS_CONFIG_FORM_ID, - prompt = STRING_TOKEN(STR_RAS_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_RAS_CONFIG_FORM_HELP); - - subtitle text = STRING_TOKEN(STR_EMPTY_STRING); - subtitle text = STRING_TOKEN(STR_EXIT_STRING); - - endform; - -#include "MemoryConfig.hfr" -#include "iBMCConfig.hfr" -#include "PcieConfig.hfr" -#include "MiscConfig.hfr" -#include "RasConfig.hfr" -endformset; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr deleted file mode 100644 index 86da04639974996918fb8a3b703cc9e0310b158d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ /dev/null @@ -1,213 +0,0 @@ -/** @file -* -* PCIe Config form at Oem Config fromset. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -form formid = PCIE_CONFIG_FORM_ID, - title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE); - - goto VFR_FORMID_PCIE_SOCKET0, - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - goto VFR_FORMID_PCIE_SOCKET1, - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), - option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET0, - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); - - goto VFR_FORMID_PCIE_PORT2, - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT4, - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT5, - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT6, - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT7, - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET1, - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); - goto VFR_FORMID_PCIE_PORT10, - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT12, - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT13, - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); -endform; - -form formid = VFR_FORMID_PCIE_PORT0, - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); - #undef INDEX - #define INDEX 0 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT1, - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); - - #undef INDEX - #define INDEX 1 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT2, - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); - - #undef INDEX - #define INDEX 2 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT3, - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); - - #undef INDEX - #define INDEX 3 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT4, - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); - - #undef INDEX - #define INDEX 4 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT5, - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); - - #undef INDEX - #define INDEX 5 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT6, - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); - - #undef INDEX - #define INDEX 6 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT7, - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); - - #undef INDEX - #define INDEX 7 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT8, - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); - - #undef INDEX - #define INDEX 8 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT9, - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); - - #undef INDEX - #define INDEX 9 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT10, - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); - - #undef INDEX - #define INDEX 10 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT11, - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); - - #undef INDEX - #define INDEX 11 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT12, - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); - - #undef INDEX - #define INDEX 12 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT13, - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); - - #undef INDEX - #define INDEX 13 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT14, - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); - - #undef INDEX - #define INDEX 14 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT15, - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); - - #undef INDEX - #define INDEX 15 - #include "PciePortConfig.hfr" - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni deleted file mode 100644 index ade4ba3ae65324c08450b81911f42abb7033c1e1..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ /dev/null @@ -1,105 +0,0 @@ -/** @file -* -* String definitions for the PCIe Config form. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -/=# - -#langdef en-US "English" - -#string STR_BLANK_STRING #language en-US "" -#string STR_PCIE_CPU_PROMPT_HELP #language en-US "Press to config this CPU." -#string STR_PCIE_CPU_0_NULL_PROMPT #language en-US "" -#string STR_PCIE_CPU_0_PROMPT #language en-US "CPU 0 PCIE Configuration" -#string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" -#string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" -#string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - -#string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press to config this port." -#string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" -#string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0" -#string STR_PCIE_PORT_1_PROMPT #language en-US "CPU 0 Pcie - Port 1" -#string STR_PCIE_PORT_2_PROMPT #language en-US "CPU 0 Pcie - Port 2" -#string STR_PCIE_PORT_3_PROMPT #language en-US "CPU 0 Pcie - Port 3" -#string STR_PCIE_PORT_4_PROMPT #language en-US "CPU 0 Pcie - Port 4" -#string STR_PCIE_PORT_5_PROMPT #language en-US "CPU 0 Pcie - Port 5" -#string STR_PCIE_PORT_6_PROMPT #language en-US "CPU 0 Pcie - Port 6" -#string STR_PCIE_PORT_7_PROMPT #language en-US "CPU 0 Pcie - Port 7" -#string STR_PCIE_PORT_8_PROMPT #language en-US "CPU 1 Pcie - Port 0" -#string STR_PCIE_PORT_9_PROMPT #language en-US "CPU 1 Pcie - Port 1" -#string STR_PCIE_PORT_10_PROMPT #language en-US "CPU 1 Pcie - Port 2" -#string STR_PCIE_PORT_11_PROMPT #language en-US "CPU 1 Pcie - Port 3" -#string STR_PCIE_PORT_12_PROMPT #language en-US "CPU 1 Pcie - Port 4" -#string STR_PCIE_PORT_13_PROMPT #language en-US "CPU 1 Pcie - Port 5" -#string STR_PCIE_PORT_14_PROMPT #language en-US "CPU 1 Pcie - Port 6" -#string STR_PCIE_PORT_15_PROMPT #language en-US "CPU 1 Pcie - Port 7" - -#string STR_PCIE_PORT_ENABLE_PROMPT_0 #language en-US "PCI-E Port" -#string STR_PCIE_PORT_ENABLE_HELP #language en-US "Disable is used to disable the port and hide its CFG space." - -#string STR_LINK_STATUS #language en-US "PCI-E Port Link Status" -#string STR_LINK_STATUS_NG #language en-US "Link Training Error" -#string STR_LINK_STATUS_OK #language en-US "Link Up" -#string STR_MAXLINK_STATUS #language en-US "PCI-E Port Link Max" -#string STR_WIDTH1_STRING #language en-US "X1" -#string STR_WIDTH2_STRING #language en-US "X2" -#string STR_WIDTH4_STRING #language en-US "X4" -#string STR_WIDTH8_STRING #language en-US "X8" -#string STR_WIDTH16_STRING #language en-US "X16" -#string STR_WIDTH32_STRING #language en-US "X32" - -#string STR_PCIESPEED_STATUS #language en-US "PCI-E Port Link Speed" -#string STR_PCIE_LINK_SPEED1_STRING #language en-US "Gen 1 (2.5 GT/s)" -#string STR_PCIE_LINK_SPEED2_STRING #language en-US "Gen 2 (5 GT/s)" -#string STR_PCIE_LINK_SPEED3_STRING #language en-US "Gen 3 (8 GT/s)" - -#string STR_PCIE_PORT_DEEMPHASIS_PROMPT_0 #language en-US "PCI-E Port DeEmphasis" - -#string STR_PCIE_PORT_DEEMPHASIS_HELP #language en-US "De-Emphais control for this PCIe port." - -#string STR_35DB #language en-US "-3.5 dB" -#string STR_60DB #language en-US "-6.0 dB" - -#string STR_PCIE_PORT_ASPM_PROMPT_G #language en-US "PCI-E ASPM Support" - -#string STR_PCIE_GLOBAL_ASPM_HELP #language en-US "This option enables / disables the ASPM support for all downstream devices." -#string STR_PCIE_PORT_ASPM_HELP #language en-US "This option enables / disables the ASPM (L1) support for the downstream devices." - -#string STR_L0S_ONLY #language en-US "L0s Only" -#string STR_L0S_L1_BOTH #language en-US "L0s & L1 Both" -#string STR_L1_ONLY #language en-US "L1 Only" - -#string STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_PROMPT #language en-US "Max Payload Size" -#string STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_HELP #language en-US "Set Maxpayload size to 512B if possible" -// -// Common Strings -// -#string STR_AUTO #language en-US "Auto" -#string STR_X1 #language en-US "x1" -#string STR_X2 #language en-US "x2" -#string STR_X4 #language en-US "x4" -#string STR_X8 #language en-US "x8" -#string STR_X16 #language en-US "x16" - -#string STR_128B #language en-US "128B" -#string STR_256B #language en-US "256B" -#string STR_512B #language en-US "512B" -#string STR_1024B #language en-US "1024B" -#string STR_2048B #language en-US "2048B" -#string STR_4096B #language en-US "4096B" - -#string STR_CLEAR #language en-US "Clear" -#string STR_SET #language en-US "Set" - -#string STR_PCIE_PORT_LINK_SPEED_PROMPT_0 #language en-US "Link Speed" -#string STR_PCIE_PORT_LINK_SPEED_HELP #language en-US "Link Speed:Gen1(2.5 GT/s)/Gen2(5 GT/s)/Gen3(8 GT/s)/GEN 4 (16 gt/s)" -#string STR_PCIE_GEN1 #language en-US "Gen 1 (2.5 GT/s)" -#string STR_PCIE_GEN2 #language en-US "Gen 2 (5 GT/s)" -#string STR_PCIE_GEN3 #language en-US "Gen 3 (8 GT/s)" -#string STR_PCIE_GEN4 #language en-US "Gen 4 (16 GT/s)" diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr deleted file mode 100644 index 64f7a58798786b112b1a6e79cfbec2ee51822af8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr +++ /dev/null @@ -1,161 +0,0 @@ -/** @file -* -* PCIe Config form at Oem Config fromset. -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -oneof varid = OEM_CONFIG_DATA.PciePort[INDEX], - prompt = STRING_TOKEN(STR_PCIE_PORT_ENABLE_PROMPT_0), - help = STRING_TOKEN(STR_PCIE_PORT_ENABLE_HELP), - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; -endoneof; - -suppressif ideqval OEM_CONFIG_DATA.PciePort[INDEX] == 0x00; - oneof varid = OEM_CONFIG_DATA.PcieLinkSpeedPort[INDEX], - prompt = STRING_TOKEN(STR_PCIE_PORT_LINK_SPEED_PROMPT_0), - help = STRING_TOKEN(STR_PCIE_PORT_LINK_SPEED_HELP), - option text = STRING_TOKEN(STR_PCIE_GEN1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED; - option text = STRING_TOKEN(STR_PCIE_GEN2), value = 2, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_PCIE_GEN3), value = 3, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_PCIE_GEN4), value = 4, flags = RESET_REQUIRED; - endoneof; - - suppressif NOT ideqval OEM_CONFIG_DATA.PcieLinkSpeedPort[INDEX] == 2; - oneof varid = OEM_CONFIG_DATA.PcieLinkDeEmphasisPort[INDEX], - prompt = STRING_TOKEN(STR_PCIE_PORT_DEEMPHASIS_PROMPT_0), - help = STRING_TOKEN(STR_PCIE_PORT_DEEMPHASIS_HELP), - #if ( INDEX == 0) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 1) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 3) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 4) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 6) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 7) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 8) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 9) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 11) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 14) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 15) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED; - #endif - - #if ( INDEX == 2) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED ; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED| MANUFACTURING | DEFAULT; - #endif - - #if ( INDEX == 5) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - #endif - - #if ( INDEX == 10) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - #endif - - #if ( INDEX == 12) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - #endif - - #if ( INDEX == 13) - option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - #endif - - endoneof; - endif; - - grayoutif TRUE; - oneof varid = OEM_CONFIG_DATA.PcieLinkStatusPort[INDEX], - prompt = STRING_TOKEN(STR_LINK_STATUS), - help = STRING_TOKEN(STR_BLANK_STRING), - option text = STRING_TOKEN(STR_LINK_STATUS_NG), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_LINK_STATUS_OK), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.PcieLinkMaxPort[INDEX], - prompt = STRING_TOKEN(STR_MAXLINK_STATUS), - help = STRING_TOKEN(STR_BLANK_STRING), - option text = STRING_TOKEN(STR_WIDTH1_STRING), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_WIDTH2_STRING), value = 2, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_WIDTH4_STRING), value = 4, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_WIDTH8_STRING), value = 8, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - endoneof; - - suppressif NOT ideqval OEM_CONFIG_DATA.PcieLinkStatusPort[INDEX] == 1; - oneof varid = OEM_CONFIG_DATA.PcieLinkSpeedRateStatusPort[INDEX], - prompt = STRING_TOKEN(STR_PCIESPEED_STATUS), - help = STRING_TOKEN(STR_BLANK_STRING), - option text = STRING_TOKEN(STR_PCIE_LINK_SPEED1_STRING), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_PCIE_LINK_SPEED2_STRING), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_PCIE_LINK_SPEED3_STRING), value = 2, flags = RESET_REQUIRED; - endoneof; - endif; - endif; - - oneof varid = OEM_CONFIG_DATA.PcieMaxPayloadSizePort[INDEX], - prompt = STRING_TOKEN(STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_HELP), - option text = STRING_TOKEN(STR_128B), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_256B), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_512B), value = 2, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.PcieAspmPort[INDEX], - prompt = STRING_TOKEN (STR_PCIE_PORT_ASPM_PROMPT_G), - help = STRING_TOKEN (STR_PCIE_GLOBAL_ASPM_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT; - option text = STRING_TOKEN(STR_L0S_ONLY), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_L1_ONLY), value = 2, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_L0S_L1_BOTH), value = 3, flags = RESET_REQUIRED; - endoneof; - -endif; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr deleted file mode 100644 index 4321566039432178b8c13e5d2413adb4e36bc545..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr +++ /dev/null @@ -1,166 +0,0 @@ - ///** @file -// -// Memory RAS Config form. -// -// Copyright (c) 2018, Hisilicon Limited. All rights reserved. -// Copyright (c) 2018, Linaro Limited. All rights reserved. -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//**/ - form formid = RAS_CONFIG_FORM_ID, - title = STRING_TOKEN(STR_RAS_CONFIG_FORM_TITLE); - - oneof varid = OEM_CONFIG_DATA.EnRasSupport, - prompt = STRING_TOKEN(STR_SUPPORT_RAS_TITLE), - help = STRING_TOKEN(STR_SUPPORT_RAS_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - endoneof; - - suppressif TRUE; - goto VFR_FORMID_MEMORY_RAS, - prompt = STRING_TOKEN(STR_MEMORY_RAS_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_MEMORY_RAS_CONFIG_FORM_HELP); - - goto VFR_FORMID_PCIE_RAS, - prompt = STRING_TOKEN(STR_PCIE_RAS_CONFIG_FORM_TITLE), - help = STRING_TOKEN(STR_PCIE_RAS_CONFIG_FORM_HELP); - endif; - endform; - - form formid = VFR_FORMID_MEMORY_RAS, - title = STRING_TOKEN(STR_MEMORY_RAS_CONFIG_FORM_TITLE); - - oneof varid = OEM_CONFIG_DATA.CheckAlgorithm, - prompt = STRING_TOKEN(STR_CHECK_ALGORITHM_PROMPT), - help = STRING_TOKEN(STR_CHECK_ALGORITHM_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_ECC), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_SDEC), value = 2, flags = RESET_REQUIRED; - endoneof; - - grayoutif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0; - oneof varid = OEM_CONFIG_DATA.EnPoison, - prompt = STRING_TOKEN(STR_ENABLE_POISON_PROMPT), - help = STRING_TOKEN(STR_ENABLE_POISON_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.PatrolScrub, - prompt = STRING_TOKEN(STR_PATROL_SCRUB_PROMPT), - help = STRING_TOKEN(STR_PATROL_SCRUB_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - endoneof; - endif; - - grayoutif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0 OR ideqval OEM_CONFIG_DATA.PatrolScrub == 0; - numeric varid = OEM_CONFIG_DATA.PatrolScrubDuration, - prompt = STRING_TOKEN(STR_PATROL_SCRUB_DURATION_PROMPT), - help = STRING_TOKEN(STR_PATROL_SCRUB_DURATION_HELP), - flags = 0 | RESET_REQUIRED, - minimum = 0, - maximum = 24, - step = 1, - default = 24, - endnumeric; - endif; - - grayoutif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0; - oneof varid = OEM_CONFIG_DATA.DemandScrubMode, - prompt = STRING_TOKEN(STR_DEMAND_SCRUB_PROMPT), - help = STRING_TOKEN(STR_DEMAND_SCRUB_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - endif; - - suppressif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0 OR ideqval OEM_CONFIG_DATA.CheckAlgorithm == 1; - goto VFR_FORMID_CORRECT_ERROR, - prompt = STRING_TOKEN(STR_CORRECT_ERROR_FORM_TITLE), - help = STRING_TOKEN(STR_CORRECT_ERROR_FORM_HELP); - endif; - endform; - - - form formid = VFR_FORMID_CORRECT_ERROR, - title = STRING_TOKEN(STR_CORRECT_ERROR_FORM_TITLE); - - oneof varid = OEM_CONFIG_DATA.CorrectErrorThreshold, - prompt = STRING_TOKEN(STR_CORRECT_ERROR_THRESHOLD_PROMPT), - help = STRING_TOKEN(STR_CORRECT_ERROR_THRESHOLD_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_500), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_1000), value = 2, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_2000), value = 3, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.FunnelPeriod, - prompt = STRING_TOKEN(STR_FUNNEL_PERIOD_PROMPT), - help = STRING_TOKEN(STR_FUNNEL_PERIOD_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_30), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_60), value = 2, flags = RESET_REQUIRED; - endoneof; - - suppressif ideqval OEM_CONFIG_DATA.CorrectErrorThreshold == 0; - oneof varid = OEM_CONFIG_DATA.AdvanceDeviceCorrection , - prompt = STRING_TOKEN(STR_ADVANCE_DEVICE_CORRECTION_PROMPT), - help = STRING_TOKEN(STR_ADVANCE_DEVICE_CORRECTION_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_SR), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_MR), value = 2, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.RankSparing, - prompt = STRING_TOKEN(STR_RANK_SPARING_PROMPT), - help = STRING_TOKEN(STR_RANK_SPARING_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - endif; - endform; - - form formid = VFR_FORMID_PCIE_RAS, - title = STRING_TOKEN(STR_PCIE_RAS_CONFIG_FORM_TITLE); - - oneof varid = OEM_CONFIG_DATA.DpcFeature, - prompt = STRING_TOKEN(STR_DPC_FEARURE), - help = STRING_TOKEN(STR_DPC_FEARURE_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.EcrcFeature, - prompt = STRING_TOKEN(STR_ECRC_FEARURE), - help = STRING_TOKEN(STR_ECRC_FEARURE_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED; - endoneof; - - oneof varid = OEM_CONFIG_DATA.CompletionTimeout, - prompt = STRING_TOKEN(STR_COMPLETION_TIMEOUT), - help = STRING_TOKEN(STR_COMPLETION_TIMEOUT_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - endoneof; - - suppressif ideqval OEM_CONFIG_DATA.CompletionTimeout == 0; - oneof varid = OEM_CONFIG_DATA.CompletionTimeoutValue, - prompt = STRING_TOKEN(STR_COMPLETION_TIMEOUT_VALUE), - help = STRING_TOKEN(STR_COMPLETION_TIMEOUT_VALUE_HELP), - option text = STRING_TOKEN(STR_50US_TO_50MS), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - option text = STRING_TOKEN(STR_50US_TO_100US), value = 1, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_1MS_TO_10MS), value = 2, flags = RESET_REQUIRED; - endoneof; - endif; - - oneof varid = OEM_CONFIG_DATA.HotPlug, - prompt = STRING_TOKEN(STR_HOT_PLUG), - help = STRING_TOKEN(STR_HOT_PLUG_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; - endoneof; - endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni deleted file mode 100644 index 89d9ccd1ceacfd398fe08673dee770348b1b599f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni +++ /dev/null @@ -1,79 +0,0 @@ -// /** @file -// OEM Config Library used by UiApp -// -// -// Copyright (c) 2018, Hisilicon Limited. All rights reserved. -// Copyright (c) 2018, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// **/ -#langdef en-US "English" - -#string STR_SUPPORT_RAS_TITLE #language en-US "Support RAS" -#string STR_SUPPORT_RAS_HELP #language en-US "Support memory/PCIe/CPU RAS funtions." - -#string STR_MEMORY_RAS_CONFIG_FORM_TITLE #language en-US "Memory RAS Config" -#string STR_MEMORY_RAS_CONFIG_FORM_HELP #language en-US "Memory RAS Config" - -#string STR_PCIE_RAS_CONFIG_FORM_TITLE #language en-US "PCIe RAS Config" -#string STR_PCIE_RAS_CONFIG_FORM_HELP #language en-US "PCIe RAS Config" - -#string STR_CPU_RAS_CONFIG_FORM_TITLE #language en-US "CPU RAS Config" -#string STR_CPU_RAS_CONFIG_FORM_HELP #language en-US "CPU RAS Config" - -#string STR_ENABLE_POISON_PROMPT #language en-US "Poison" -#string STR_ENABLE_POISON_HELP #language en-US "Enable/Disable Poison flag" - -#string STR_CHECK_ALGORITHM_PROMPT #language en-US "Check Algorithm" -#string STR_CHECK_ALGORITHM_HELP #language en-US "Set the memory check algorithm" -#string STR_ECC #language en-US "ECC" -#string STR_SDEC #language en-US "SDEC" - -#string STR_PATROL_SCRUB_PROMPT #language en-US "Active Scrub" -#string STR_PATROL_SCRUB_HELP #language en-US "Enable/Disable Active Scrub" - -#string STR_PATROL_SCRUB_DURATION_PROMPT #language en-US "Active Scrub Interval" -#string STR_PATROL_SCRUB_DURATION_HELP #language en-US "Selects the number of hours (0-24) required to complete full scrub. A value of zero means auto!" - -#string STR_DEMAND_SCRUB_PROMPT #language en-US "Passive Scrub" -#string STR_DEMAND_SCRUB_HELP #language en-US "Enable/Disable Passive Scrub" - -#string STR_CORRECT_ERROR_FORM_TITLE #language en-US "Correct Error handle" -#string STR_CORRECT_ERROR_FORM_HELP #language en-US "Correctable error-related configuration" - -#string STR_CORRECT_ERROR_THRESHOLD_PROMPT #language en-US "Correct Error Threshold" -#string STR_CORRECT_ERROR_THRESHOLD_HELP #language en-US "Correctable error-related configuration" -#string STR_500 #language en-US "500" -#string STR_1000 #language en-US "1000" -#string STR_2000 #language en-US "2000" - -#string STR_FUNNEL_PERIOD_PROMPT #language en-US "Funnel Period(min)" -#string STR_FUNNEL_PERIOD_HELP #language en-US "Set the Funnel function time period" -#string STR_30 #language en-US "30" -#string STR_60 #language en-US "60" - -#string STR_ADVANCE_DEVICE_CORRECTION_PROMPT #language en-US "Advance Device Correction" -#string STR_ADVANCE_DEVICE_CORRECTION_HELP #language en-US "Configure the correctable error threshold alarm handling solution" -#string STR_SR #language en-US "SR" -#string STR_MR #language en-US "MR" - -#string STR_RANK_SPARING_PROMPT #language en-US "Rank Sparing" -#string STR_RANK_SPARING_HELP #language en-US "Enable/Disable Rank Sparing" - -#string STR_DPC_FEARURE #language en-US "DPC Feature" -#string STR_DPC_FEARURE_HELP #language en-US "Enable/Disable PCIE DPC(DownStream Port Containment) feature." - -#string STR_ECRC_FEARURE #language en-US "ECRC Feature" -#string STR_ECRC_FEARURE_HELP #language en-US "Enable/Disable ECRC check feature" -#string STR_COMPLETION_TIMEOUT #language en-US "Completion Timeout" -#string STR_COMPLETION_TIMEOUT_HELP #language en-US "Enable/Disable PCIE Completion Timeout feature." - -#string STR_COMPLETION_TIMEOUT_VALUE #language en-US "Completion Timeout Value" -#string STR_COMPLETION_TIMEOUT_VALUE_HELP #language en-US "Set the corresponding Completion Timeout value." - -#string STR_HOT_PLUG #language en-US "Hot-Plug" -#string STR_HOT_PLUG_HELP #language en-US "Enable/Disable PCIE Hot-plug feature." -#string STR_50US_TO_50MS #language en-US "50 us to 50 ms" -#string STR_50US_TO_100US #language en-US "50 us to 100 us" -#string STR_1MS_TO_10MS #language en-US "1 ms to 10 ms" diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr deleted file mode 100644 index 1832241d98f1c1da6694d909c8f27f383b5344a5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr +++ /dev/null @@ -1,75 +0,0 @@ - ///** @file -// -// IBMC Config form. -// -// Copyright (c) 2018, Hisilicon Limited. All rights reserved. -// Copyright (c) 2018, Linaro Limited. All rights reserved. -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//**/ - form formid = IBMC_CONFIG_FORM_ID, - title = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE); - - oneof - varid = OEM_CONFIG_DATA.BmcWdtEnable, - prompt = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER), - help = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = 0; - endoneof; - - suppressif ideqval OEM_CONFIG_DATA.BmcWdtEnable == 0; - numeric - varid = OEM_CONFIG_DATA.BmcWdtTimeout, - prompt = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_TIMEOUT), - help = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_TIMEOUT_C10_HELP), - minimum = 15, - maximum = 25, - step = 1, - default = 15, - endnumeric; - - oneof - varid = OEM_CONFIG_DATA.BmcWdtAction, - prompt = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_ACTION), - help = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_ACTION_HELP), - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_NO_ACTION), value = 0, flags = 0; - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_HARD_RESET), value = 1, flags = DEFAULT; - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_DOWN), value = 2, flags = 0; - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_CYCLE), value = 3, flags = 0; - endoneof; - endif; - - suppressif TRUE; - oneof - varid = OEM_CONFIG_DATA.OSWdtEnable, - prompt = STRING_TOKEN(STR_BMC_OS_WATCHDOG_TIMER), - help = STRING_TOKEN(STR_BMC_OS_WATCHDOG_TIMER_HELP), - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT; - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = 0; - endoneof; - endif; - - suppressif ideqval OEM_CONFIG_DATA.OSWdtEnable == 0; - numeric - varid = OEM_CONFIG_DATA.OSWdtTimeout, - prompt = STRING_TOKEN(STR_BMC_OS_WDT_TIMEOUT), - help = STRING_TOKEN(STR_BMC_OS_WDT_TIMEOUT_HELP), - minimum = 5, - maximum = 8, - step = 1, - default = 5, - endnumeric; - - oneof - varid = OEM_CONFIG_DATA.OSWdtAction, - prompt = STRING_TOKEN(STR_BMC_OS_WDT_ACTION), - help = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_ACTION_HELP), - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_NO_ACTION), value = 0, flags = 0; - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_HARD_RESET), value = 1, flags = DEFAULT; - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_DOWN), value = 2, flags = 0; - option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_CYCLE), value = 3, flags = 0; - endoneof; - endif; - - endform; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni deleted file mode 100644 index 5aad6bd0bdd643819984e525f5daf3c1d352b19b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni +++ /dev/null @@ -1,28 +0,0 @@ -// /** @file -// OEM Config Library used by UiApp -// -// -// Copyright (c) 2018, Hisilicon Limited. All rights reserved. -// Copyright (c) 2018, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// **/ -#langdef en-US "English" - -#string STR_BMC_WATCHDOG_TIMER #language en-US "iBMC WDT Support For POST" -#string STR_BMC_WATCHDOG_TIMER_HELP #language en-US "Enable/Disable iBMC watchdog timer at start of POST." -#string STR_BMC_WATCHDOG_TIMER_TIMEOUT #language en-US "iBMC WDT TimeOut For POST" -#string STR_BMC_WATCHDOG_TIMER_TIMEOUT_C10_HELP #language en-US "Enter the number of minutes the system firmware has to boot the OS before it takes the Timeout Action. Valid values are from 15 to 25 minutes." -#string STR_BMC_WATCHDOG_TIMER_ACTION #language en-US "iBMC WDT Action For POST" -#string STR_BMC_WATCHDOG_TIMER_ACTION_HELP #language en-US "Timeout Action Choices: No Action, Hard Reset, Power Down or Power Cycle" -#string STR_BMC_WATCHDOG_TIMER_NO_ACTION #language en-US "No Action" -#string STR_BMC_WATCHDOG_TIMER_HARD_RESET #language en-US "Hard Reset" -#string STR_BMC_WATCHDOG_TIMER_POWER_DOWN #language en-US "Power Down" -#string STR_BMC_WATCHDOG_TIMER_POWER_CYCLE #language en-US "Power Cycle" -#string STR_BMC_OS_WATCHDOG_TIMER #language en-US "iBMC WDT Support For OS" -#string STR_BMC_OS_WATCHDOG_TIMER_HELP #language en-US "Enable/Disable OS Watchdog Timer When OS Load" -#string STR_BMC_OS_WDT_TIMEOUT #language en-US "iBMC WDT TimeOut For OS" -#string STR_BMC_OS_WDT_TIMEOUT_HELP #language en-US "Enter the number of minutes the system firmware \n has to OS Load before it takes the Timeout Action. Valid values are from 5 to 8 minutes." -#string STR_BMC_OS_WDT_ACTION #language en-US "iBMC WDT Action For OS" - diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h deleted file mode 100644 index 0999ac60b57405f05397065e2d08169ce81f498e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h +++ /dev/null @@ -1,61 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#ifndef _PLATFORM_ARCH_H_ -#define _PLATFORM_ARCH_H_ - -#define MAX_SOCKET 2 -#define MAX_DIE 4 -#define MAX_DDRC 4 -#define MAX_NODE (MAX_SOCKET * MAX_DIE) -#define MAX_CHANNEL 8 -#define MAX_DIMM 2 -#define MAX_RANK_CH 8 -#define MAX_RANK_DIMM 4 -#define MAX_DIMM_SIZE 256 // In GB -// Max NUMA node number for each node type -#define MAX_NUM_PER_TYPE 8 - -#define RASC_BASE (0x1800) -#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x58) /* configuration register for Rank statistical information */ -#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xD4) /* configuration register for Sparing level */ - -// -// ACPI table information used to initialize tables. -// -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64 ('H','I','P','0','8',' ',' ',' ') // OEM table id 8 bytes long -#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 -#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32 ('H','I','S','I') -#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 - -// A macro to initialise the common header part of EFI ACPI tables as defined by -// EFI_ACPI_DESCRIPTION_HEADER structure. -#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ - Signature, /* UINT32 Signature */ \ - sizeof (Type), /* UINT32 Length */ \ - Revision, /* UINT8 Revision */ \ - 0, /* UINT8 Checksum */ \ - { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ - EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ - EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ - EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ - EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ - } - -// for acpi -#define NODE_IN_SOCKET 2 -#define CORE_NUM_PER_SOCKET 48 -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 16 -#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 1 - -#endif - diff --git a/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c b/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c deleted file mode 100644 index 80643b8165458e147a6ecc3b605d2c41414fae58..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c +++ /dev/null @@ -1,61 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include - - -/*++ - -Routine Description: - - Perform Platform initialization first in PciPlatform. - -Arguments: - -Returns: - - VOID. - ---*/ -VOID -EFIAPI -PciInitPlatform ( - VOID - ) -{ - return; -} - -/*++ - -Routine Description: - - Perform Platform initialization by the phase indicated. - -Arguments: - - HostBridge - The associated PCI host bridge handle. - Phase - The phase of the PCI controller enumeration. - ChipsetPhase - Defines the execution phase of the PCI chipset driver. - -Returns: - ---*/ -VOID -EFIAPI -PhaseNotifyPlatform ( - IN EFI_HANDLE HostBridge, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, - IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase - ) -{ - return; -} - diff --git a/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf b/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf deleted file mode 100644 index b0b2cb9b50d78669b1f814a457987e5f391a5d3e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf +++ /dev/null @@ -1,25 +0,0 @@ -## @file -# PCI Segment Library for Hisilicon Hi1610/Hi1616 SoC with multiple RCs -# -# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
-# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
-# Copyright (c) 2018, Hisilicon Ltd. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = Hi1620PciPlatformLib - FILE_GUID = 29ba30da-68bc-46a5-888f-c65dabb67fd8 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciPlatformLib - -[Sources] - Hi1620PciPlatformLib.c - -[Packages] - MdePkg/MdePkg.dec diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c deleted file mode 100644 index 6cf844f7c5508e66f8e6310a17113574eace9874..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c +++ /dev/null @@ -1,537 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ -* -**/ - -#include "Pptt.h" - -typedef EFI_ACPI_5_1_GIC_STRUCTURE ACPI_GIC_STRUCTURE; -typedef EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER ACPI_MADT_TABLE_HEADER; - -EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL; -EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL; - -EFI_ACPI_DESCRIPTION_HEADER mPpttHeader = - ARM_ACPI_HEADER ( - EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_DESCRIPTION_HEADER, - EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION - ); - -EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] = -{ - {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0, 0, 0, 0} -}; - -EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO]; - -STATIC UINT32 mSocketOffset[MAX_SOCKET]; -STATIC UINT32 mScclOffset[MAX_SCL]; -STATIC UINT32 mClusterOffset[MAX_SCL][MAX_CLUSTER_PER_SCL]; - -STATIC -VOID -InitCacheInfo ( - VOID - ) -{ - UINT8 Index; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes; - CSSELR_DATA CsselrData; - CCSIDR_DATA CcsidrData; - - for (Index = 0; Index < PPTT_CACHE_NO; Index++) { - CsselrData.Data = 0; - CcsidrData.Data = 0; - SetMem ( - &Type1Attributes, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES), - 0 - ); - - if (Index == 0) { //L1I - CsselrData.Bits.InD = 1; - CsselrData.Bits.Level = 0; - Type1Attributes.CacheType = 1; - } else if (Index == 1) { - Type1Attributes.CacheType = 0; - CsselrData.Bits.Level = Index - 1; - } else { - Type1Attributes.CacheType = 2; - CsselrData.Bits.Level = Index - 1; - } - - CcsidrData.Data = ReadCCSIDR (CsselrData.Data); - - if (CcsidrData.Bits.Wa == 1) { - Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE; - if (CcsidrData.Bits.Ra == 1) { - Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE; - } - } - - if (CcsidrData.Bits.Wt == 1) { - Type1Attributes.WritePolicy = 1; - } - DEBUG ((DEBUG_INFO, - "[Acpi PPTT] Level = %x!CcsidrData = %x!\n", - CsselrData.Bits.Level, - CcsidrData.Data)); - - mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE; - mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE); - mPpttCacheType1[Index].Reserved[0] = 0; - mPpttCacheType1[Index].Reserved[1] = 0; - mPpttCacheType1[Index].Flags.SizePropertyValid = 1; - mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1; - mPpttCacheType1[Index].Flags.AssociativityValid = 1; - mPpttCacheType1[Index].Flags.AllocationTypeValid = 1; - mPpttCacheType1[Index].Flags.CacheTypeValid = 1; - mPpttCacheType1[Index].Flags.WritePolicyValid = 1; - mPpttCacheType1[Index].Flags.LineSizeValid = 1; - mPpttCacheType1[Index].Flags.Reserved = 0; - mPpttCacheType1[Index].NextLevelOfCache = 0; - - if (Index != PPTT_CACHE_NO - 1) { - mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1; - mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1; - mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4)); - mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \ - mPpttCacheType1[Index].Associativity * \ - mPpttCacheType1[Index].NumberOfSets; - CopyMem ( - &mPpttCacheType1[Index].Attributes, - &Type1Attributes, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES) - ); - } else { - // L3 cache - mPpttCacheType1[Index].Size = 0x2000000; // 32MB - mPpttCacheType1[Index].NumberOfSets = 0x800; - mPpttCacheType1[Index].Associativity = 0x0F; // CacheAssociativity16Way - SetMem ( - &mPpttCacheType1[Index].Attributes, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES), - 0x0A - ); - mPpttCacheType1[Index].LineSize = 0x80; // 128byte - } - } -} - -STATIC -EFI_STATUS -AddCoreTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo, - IN UINT32 ProcessorId - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; - UINT32 *PrivateResource; - UINT8 Index; - UINT32 NextLevelCacheOffset; - - if (*PpttTableLengthRemain < - (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Flags.AcpiProcessorIdValid = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID; - PpttType0->Parent= Parent; - PpttType0->AcpiProcessorId = ProcessorId; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - - *PpttTableLengthRemain -= (UINTN)PpttType0->Length; - PpttTable->Length += PpttType0->Length; - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - - // Add cache type structure - for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) { - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType1, - &mPpttCacheType1[Index], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) - ); - *PpttTableLengthRemain -= PpttType1->Length; - PpttTable->Length += PpttType1->Length; - } - - NextLevelCacheOffset = *(PrivateResource - 1); - PrivateResource = (UINT32 *)(PpttType0 + 1); - // Set the next level to L2 for L1I and L1D - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *) PpttTable + *PrivateResource++); - PpttType1->NextLevelOfCache = NextLevelCacheOffset; - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *) PpttTable + *PrivateResource++); - PpttType1->NextLevelOfCache = NextLevelCacheOffset; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -AddClusterTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - - if ((*PpttTableLengthRemain) < - (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Parent= Parent; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - - *PpttTableLengthRemain -= PpttType0->Length; - PpttTable->Length += PpttType0->Length; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -AddScclTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; - UINT32 *PrivateResource; - - if (*PpttTableLengthRemain < - (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Parent= Parent; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - - *PpttTableLengthRemain -= PpttType0->Length; - PpttTable->Length += PpttType0->Length; - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - - // Add cache type structure - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType1, - &mPpttCacheType1[3], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) - ); - *PpttTableLengthRemain -= PpttType1->Length; - PpttTable->Length += PpttType1->Length; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -AddSocketTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN OUT UINT32 *PpttTableLengthRemain, - IN UINT32 Parent, - IN UINT32 ResourceNo - ) -{ - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; - EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2; - UINT32 *PrivateResource; - UINT8 Index; - - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)) { - return EFI_OUT_OF_RESOURCES; - } - PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable + - PpttTable->Length); - PpttType0->Type = 0; - SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); - PpttType0->Flags.PhysicalPackage = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID; - PpttType0->Parent= Parent; - PpttType0->NumberOfPrivateResources = ResourceNo; - PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + - ResourceNo * 4; - PpttTable->Length += PpttType0->Length; - - *PpttTableLengthRemain -= PpttType0->Length; - if (*PpttTableLengthRemain < ResourceNo * 4) { - return EFI_OUT_OF_RESOURCES; - } - PrivateResource = (UINT32 *)((UINT8 *)PpttType0 + - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)); - DEBUG ((DEBUG_INFO, - "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n", - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID))); - - for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) { - if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) { - return EFI_OUT_OF_RESOURCES; - } - *PrivateResource = PpttTable->Length; - PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable + - PpttTable->Length); - gBS->CopyMem ( - PpttType2, - &mPpttSocketType2[Index], - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID) - ); - *PpttTableLengthRemain -= PpttType2->Length; - PpttTable->Length += PpttType2->Length; - } - - return EFI_SUCCESS; -} - -STATIC -VOID -GetAffLvl ( - IN UINT64 Mpidr, - IN OUT UINT8 *Level3, - IN OUT UINT8 *Level2, - IN OUT UINT8 *Level1, - IN OUT UINT8 *Level0 - ) -{ - *Level3 = BitFieldRead64 (Mpidr, 32, 39); - *Level2 = BitFieldRead64 (Mpidr, 16, 23); - *Level1 = BitFieldRead64 (Mpidr, 8, 15); - *Level0 = BitFieldRead64 (Mpidr, 0, 7); -} - - -STATIC -VOID -GetApic ( - IN ACPI_MADT_TABLE_HEADER *ApicTable, - IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable, - IN UINT32 PpttTableLengthRemain -) -{ - UINT32 Parent = 0; - UINT32 ResourceNo = 0; - ACPI_GIC_STRUCTURE *Ptr; - UINT8 AffLvl3 = 0; - UINT8 AffLvl2 = 0; - UINT8 AffLvl1 = 0; - UINT8 AffLvl0 = 0; - UINTN SocketIndex; - - for (Ptr = (ACPI_GIC_STRUCTURE *) (ApicTable + 1); - (UINTN) Ptr < (UINTN) ApicTable + ApicTable->Header.Length; - Ptr = (ACPI_GIC_STRUCTURE *) ((UINTN) Ptr + Ptr->Length)) { - - // Avoid dead loop due to corrupted MADT - if (Ptr->Length == 0) { - DEBUG ((DEBUG_ERROR, "[%a:%d] - Invalid MADT sub structure at 0x%x\n", - __func__, __LINE__, (UINTN) Ptr - (UINTN) ApicTable)); - break; - } - - if (Ptr->Type != EFI_ACPI_5_1_GIC || - (Ptr->Flags & EFI_ACPI_5_1_GIC_ENABLED) == 0) { - continue; - } - GetAffLvl (Ptr->MPIDR, &AffLvl3, &AffLvl2, &AffLvl1, &AffLvl0); - // AffLvl3 is not used for Hi1620 - // And socket index is calculated by AffLvl2 - - SocketIndex = AffLvl2 / MAX_SCL_PER_SOCKET; - if (mSocketOffset[SocketIndex] == 0) { - //Add socket for type0 table - ResourceNo = PPTT_SOCKET_COMPONENT_NO; - mSocketOffset[SocketIndex] = PpttTable->Length; - Parent = 0; - AddSocketTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo - ); - } - - if (mScclOffset[AffLvl2] == 0) { - //Add SCCL for type0 table - ResourceNo = 1; - mScclOffset[AffLvl2] = PpttTable->Length ; - Parent = mSocketOffset[SocketIndex]; - AddScclTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo - ); - } - - if (mClusterOffset[AffLvl2][AffLvl1] == 0) { - // Add cluster for type0 table - // No private resource for cluster on Hi1620 - ResourceNo = 0; - mClusterOffset[AffLvl2][AffLvl1] = PpttTable->Length ; - Parent = mScclOffset[AffLvl2]; - AddClusterTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo - ); - } - - //Add core for type0 table - ResourceNo = 3; - Parent = mClusterOffset[AffLvl2][AffLvl1]; - AddCoreTable ( - PpttTable, - &PpttTableLengthRemain, - Parent, - ResourceNo, - Ptr->AcpiProcessorUid - ); - } -} - - -STATIC -VOID -PpttSetAcpiTable( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - UINTN AcpiTableHandle; - EFI_STATUS Status; - UINT8 Checksum; - EFI_ACPI_SDT_HEADER *Table; - ACPI_MADT_TABLE_HEADER *ApicTable; - EFI_ACPI_TABLE_VERSION TableVersion; - EFI_ACPI_DESCRIPTION_HEADER *PpttTable; - UINTN TableKey; - UINT32 Index0; - UINT32 PpttTableLengthRemain = 0; - - gBS->CloseEvent (Event); - - InitCacheInfo (); - - PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN); - gBS->CopyMem ( - (VOID *)PpttTable, - &mPpttHeader, - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - ); - PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER); - - for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) { - Status = mAcpiSdtProtocol->GetAcpiTable ( - Index0, - &Table, - &TableVersion, - &TableKey - ); - if (EFI_ERROR (Status)) { - break; - } - - // Find APIC table - if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) { - break; - } - - } - - if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) { - ApicTable = (ACPI_MADT_TABLE_HEADER *)Table; - - GetApic (ApicTable, PpttTable, PpttTableLengthRemain); - - Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length); - PpttTable->Checksum = Checksum; - - AcpiTableHandle = 0; - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - PpttTable, - PpttTable->Length, - &AcpiTableHandle); - } - - FreePool (PpttTable); - return ; -} - -EFI_STATUS -EFIAPI -PpttEntryPoint( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_EVENT ReadyToBootEvent; - - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID **)&mAcpiTableProtocol); - ASSERT_EFI_ERROR (Status); - - Status = gBS->LocateProtocol ( - &gEfiAcpiSdtProtocolGuid, - NULL, - (VOID **)&mAcpiSdtProtocol); - ASSERT_EFI_ERROR (Status); - - Status = EfiCreateEventReadyToBootEx ( - TPL_NOTIFY, - PpttSetAcpiTable, - NULL, - &ReadyToBootEvent - ); - ASSERT_EFI_ERROR (Status); - - DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n")); - - return Status; -} diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h deleted file mode 100644 index 3019ea0e11d3fdd8803d939c7048b41be76d6056..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h +++ /dev/null @@ -1,63 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ -* -**/ - -#ifndef _PPTT_H_ -#define _PPTT_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PPTT_VENDOR_ID SIGNATURE_32('H', 'I', 'S', 'I') - -#define EFI_ACPI_MAX_NUM_TABLES 20 - -#define MAX_SCL_PER_SOCKET MAX_DIE -#define MAX_SCL (MAX_SOCKET * MAX_SCL_PER_SOCKET) -#define MAX_CLUSTER_PER_SCL 8 - -#define PPTT_TABLE_MAX_LEN 0x6000 -#define PPTT_SOCKET_COMPONENT_NO 0x1 -#define PPTT_CACHE_NO 0x4 - -typedef union { - struct { - UINT32 InD :1; - UINT32 Level :3; - UINT32 Reserved :28; - } Bits; - UINT32 Data; -} CSSELR_DATA; - -typedef union { - struct { - UINT32 LineSize :3; - UINT32 Associativity :10; - UINT32 NumSets :15; - UINT32 Wa :1; - UINT32 Ra :1; - UINT32 Wb :1; - UINT32 Wt :1; - } Bits; - UINT32 Data; -} CCSIDR_DATA; - -#endif // _PPTT_H_ - diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf deleted file mode 100644 index 835e7557ea8b3ef9e4a2f9cd8940987ae098155a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf +++ /dev/null @@ -1,42 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ -* -**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = AcpiPptt - FILE_GUID = 65766562-49e7-11e8-817f-286ed489ee9b - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = PpttEntryPoint - -[Sources.common] - Pptt.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - ArmLib - BaseMemoryLib - DebugLib - HobLib - UefiDriverEntryPoint - UefiRuntimeServicesTableLib - -[Protocols] - gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED - gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED - -[Depex] - gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid - diff --git a/Silicon/Hisilicon/Hi3660/Hi3660.dec b/Silicon/Hisilicon/Hi3660/Hi3660.dec deleted file mode 100644 index f4ca0d785073c4c6675b2cfe34baef698976714c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi3660/Hi3660.dec +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - DEC_SPECIFICATION = 0x0001001a - PACKAGE_NAME = Hi3660 - PACKAGE_GUID = e457ba7c-faba-4dea-b274-f5962d016c79 - PACKAGE_VERSION = 0.1 - -################################################################################ -# -# Include Section - list of Include Paths that are provided by this package. -# Comments are used for Keywords and Module Types. -# -# Supported Module Types: -# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION -# -################################################################################ -[Includes.common] - Include # Root include for the package - -[Guids.common] - gHi3660TokenSpaceGuid = { 0x4abc73fa, 0x8a49, 0x4d2c, { 0x95, 0x44, 0x17, 0x87, 0x29, 0x06, 0x20, 0xb4 } } diff --git a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h deleted file mode 100644 index 7617191f526e3f1c7ccb007f7d18380fc65a8773..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h +++ /dev/null @@ -1,189 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __HI3660_H__ -#define __HI3660_H__ - -#define HKADC_SSI_REG_BASE 0xE82B8000 - -#define PCTRL_REG_BASE 0xE8A09000 - -#define PCTRL_CTRL3 (PCTRL_REG_BASE + 0x010) -#define PCTRL_CTRL24 (PCTRL_REG_BASE + 0x064) - -#define PCTRL_CTRL3_USB_TXCO_EN (1 << 1) -#define PCTRL_CTRL24_USB3PHY_3MUX1_SEL (1 << 25) - -#define SCTRL_REG_BASE 0xFFF0A000 - -#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) -#define SCTRL_SCFPLLCTRL0_FPLL0_EN (1 << 0) - -#define SCTRL_BAK_DATA0 (SCTRL_REG_BASE + 0x40C) - -#define USB3OTG_BC_REG_BASE 0xFF200000 - -#define USB3OTG_CTRL0 (USB3OTG_BC_REG_BASE + 0x000) -#define USB3OTG_CTRL2 (USB3OTG_BC_REG_BASE + 0x008) -#define USB3OTG_CTRL3 (USB3OTG_BC_REG_BASE + 0x00C) -#define USB3OTG_CTRL4 (USB3OTG_BC_REG_BASE + 0x010) -#define USB3OTG_CTRL6 (USB3OTG_BC_REG_BASE + 0x018) -#define USB3OTG_CTRL7 (USB3OTG_BC_REG_BASE + 0x01C) -#define USB3OTG_PHY_CR_STS (USB3OTG_BC_REG_BASE + 0x050) -#define USB3OTG_PHY_CR_CTRL (USB3OTG_BC_REG_BASE + 0x054) - -#define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN (1 << 15) -#define USB3OTG_CTRL2_TEST_POWERDOWN_SSP (1 << 1) -#define USB3OTG_CTRL2_TEST_POWERDOWN_HSP (1 << 0) -#define USB3OTG_CTRL3_VBUSVLDEXT (1 << 6) -#define USB3OTG_CTRL3_VBUSVLDEXTSEL (1 << 5) -#define USB3OTG_CTRL7_REF_SSP_EN (1 << 16) -#define USB3OTG_PHY_CR_DATA_OUT(x) (((x) & 0xFFFF) << 1) -#define USB3OTG_PHY_CR_ACK (1 << 0) -#define USB3OTG_PHY_CR_DATA_IN(x) (((x) & 0xFFFF) << 4) -#define USB3OTG_PHY_CR_WRITE (1 << 3) -#define USB3OTG_PHY_CR_READ (1 << 2) -#define USB3OTG_PHY_CR_CAP_DATA (1 << 1) -#define USB3OTG_PHY_CR_CAP_ADDR (1 << 0) - -#define PMU_REG_BASE 0xFFF34000 -#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x06b << 2)) -#define LDO9_VSET_MASK (7 << 0) - -#define PMIC_LDO16_ONOFF_ECO_REG (PMU_REG_BASE + (0x078 << 2)) -#define LDO16_ONOFF_ECO_LDO16_ENABLE BIT1 -#define LDO16_ONOFF_ECO_ECO_ENABLE BIT0 - -#define PMIC_LDO16_VSET_REG (PMU_REG_BASE + (0x079 << 2)) -#define LDO16_VSET_MASK (7 << 0) - -#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2)) -#define PMIC_OSC32K_ONOFF_CTRL (PMU_REG_BASE + (0x0CC << 2)) - -#define PMIC_HARDWARE_CTRL0_WIFI_CLK (1 << 5) -#define PMIC_OSC32K_ONOFF_CTRL_EN_32K (1 << 1) - - -#define CRG_REG_BASE 0xFFF35000 - -#define CRG_PEREN0 (CRG_REG_BASE + 0x000) -#define CRG_PEREN2 (CRG_REG_BASE + 0x020) -#define CRG_PERDIS2 (CRG_REG_BASE + 0x024) -#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028) -#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C) -#define CRG_PEREN4 (CRG_REG_BASE + 0x040) -#define CRG_PERDIS4 (CRG_REG_BASE + 0x044) -#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048) -#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C) -#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078) -#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C) -#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080) -#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084) -#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088) -#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C) -#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090) -#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094) -#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098) -#define CRG_CLKDIV4 (CRG_REG_BASE + 0x0B8) -#define CRG_ISOEN (CRG_REG_BASE + 0x144) -#define CRG_ISODIS (CRG_REG_BASE + 0x148) -#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C) - -#define PERI_UFS_BIT (1 << 12) -#define PERI_ARST_UFS_BIT (1 << 7) - -#define PEREN0_GT_HCLK_SD BIT30 - -#define PEREN2_HKADCSSI BIT24 - -#define PEREN4_GT_CLK_SD BIT17 -#define PEREN4_GT_ACLK_USB3OTG (1 << 1) -#define PEREN4_GT_CLK_USB3OTG_REF (1 << 0) - -#define PERRSTEN2_HKADCSSI BIT24 - -#define PERRSTEN4_SD BIT18 - -#define PERRSTEN4_USB3OTG_MUX (1 << 8) -#define PERRSTEN4_USB3OTG_AHBIF (1 << 7) -#define PERRSTEN4_USB3OTG_32K (1 << 6) -#define PERRSTEN4_USB3OTG (1 << 5) -#define PERRSTEN4_USB3OTGPHY_POR (1 << 3) - -#define PERISOEN_USB_REFCLK_ISO_EN (1 << 25) - -#define CLKDIV4_SC_SEL_SD_MASK (7 << 4) -#define CLKDIV4_SC_DIV_SD_MASK 0xf -#define CLKDIV4_SC_MASK_SHIFT 16 -#define CLKDIV4_SC_SEL_SD(x) (((x) & 0x7) << 4) -#define CLKDIV4_SC_DIV_SD(x) ((x) & 0xf) - -#define CRG_CLKDIV16_OFFSET 0x0E8 -#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9) -#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9) - -#define CRG_CLKDIV17_OFFSET 0x0EC -#define SC_DIV_UFS_PERIBUS (1 << 14) - -#define IOMG_MMC0_REG_BASE 0xFF37E000 -#define IOMG_MMC0_000_REG (IOMG_MMC0_REG_BASE + 0x000) -#define IOMG_MMC0_001_REG (IOMG_MMC0_REG_BASE + 0x004) -#define IOMG_MMC0_002_REG (IOMG_MMC0_REG_BASE + 0x008) -#define IOMG_MMC0_003_REG (IOMG_MMC0_REG_BASE + 0x00C) -#define IOMG_MMC0_004_REG (IOMG_MMC0_REG_BASE + 0x010) -#define IOMG_MMC0_005_REG (IOMG_MMC0_REG_BASE + 0x014) - -#define IOCG_MMC0_REG_BASE 0xFF37E800 -#define IOCG_MMC0_000_REG (IOCG_MMC0_REG_BASE + 0x000) -#define IOCG_MMC0_001_REG (IOCG_MMC0_REG_BASE + 0x004) -#define IOCG_MMC0_002_REG (IOCG_MMC0_REG_BASE + 0x008) -#define IOCG_MMC0_003_REG (IOCG_MMC0_REG_BASE + 0x00C) -#define IOCG_MMC0_004_REG (IOCG_MMC0_REG_BASE + 0x010) -#define IOCG_MMC0_005_REG (IOCG_MMC0_REG_BASE + 0x014) - -#define IOMG_AO_REG_BASE 0xFFF11000 -#define IOMG_AO_006_REG (IOMG_AO_REG_BASE + 0x018) - -#define IOMG_FUNC0 0 -#define IOMG_FUNC1 1 -#define IOCG_PULLUP BIT0 -#define IOCG_PULLDOWN BIT1 -#define IOCG_DRIVE(x) ((x) << 4) - -#define UFS_SYS_REG_BASE 0xFF3B1000 - -#define UFS_SYS_PSW_POWER_CTRL_OFFSET 0x004 -#define UFS_SYS_PHY_ISO_EN_OFFSET 0x008 -#define UFS_SYS_HC_LP_CTRL_OFFSET 0x00C -#define UFS_SYS_PHY_CLK_CTRL_OFFSET 0x010 -#define UFS_SYS_PSW_CLK_CTRL_OFFSET 0x014 -#define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET 0x018 -#define UFS_SYS_RESET_CTRL_EN_OFFSET 0x01C -#define UFS_SYS_MONITOR_HH_OFFSET 0x03C -#define UFS_SYS_UFS_SYSCTRL_OFFSET 0x05C -#define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET 0x060 -#define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET 0x064 - -#define BIT_UFS_PSW_ISO_CTRL (1 << 16) -#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) -#define BIT_UFS_REFCLK_ISO_EN (1 << 16) -#define BIT_UFS_PHY_ISO_CTRL (1 << 0) -#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) -#define BIT_SYSCTRL_PWR_READY (1 << 8) -#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) -#define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8) -#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) -#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) -#define MASK_UFS_CLK_GATE_BYPASS (0x3F) -#define BIT_SYSCTRL_LP_RESET_N (1 << 0) -#define BIT_UFS_REFCLK_SRC_SE1 (1 << 0) -#define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16) -#define MASK_UFS_DEVICE_RESET (1 << 16) -#define BIT_UFS_DEVICE_RESET (1 << 0) - -#endif /* __HI3660_H__ */ diff --git a/Silicon/Hisilicon/Hi6220/Hi6220.dec b/Silicon/Hisilicon/Hi6220/Hi6220.dec deleted file mode 100644 index cb49583355891b9912d2a681bcd26a1a9254092e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi6220/Hi6220.dec +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - DEC_SPECIFICATION = 0x00010019 - PACKAGE_NAME = HiKey - PACKAGE_GUID = 01be44a1-5ed3-47fc-8ecf-daa83344678c - PACKAGE_VERSION = 0.1 - -################################################################################ -# -# Include Section - list of Include Paths that are provided by this package. -# Comments are used for Keywords and Module Types. -# -# Supported Module Types: -# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION -# -################################################################################ -[Includes.common] - Include # Root include for the package - -[Guids.common] - gHi6220TokenSpaceGuid = { 0x47fc9a0e, 0x1796, 0x4d04, { 0xaf, 0x68, 0x2b, 0xcb, 0x0d, 0x40, 0x84, 0x09} } diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h deleted file mode 100644 index d3b2c795039f3ce31c9ea2858e2870558beb732f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h +++ /dev/null @@ -1,77 +0,0 @@ -/** @file -* -* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __HI6220_H__ -#define __HI6220_H__ - -/*********************************************************************************** -// Platform Memory Map -************************************************************************************/ - -// SOC peripherals (UART, I2C, I2S, USB, etc) -#define HI6220_PERIPH_BASE 0xF4000000 -#define HI6220_PERIPH_SZ 0x05800000 - -#define IOMG_BASE 0xF7010000 -#define IOMG_080_REG (IOMG_BASE + 0x140) - -#define IOCG_BASE 0xF7010800 -#define IOCG_084_REG (IOCG_BASE + 0x150) - -#define PERI_CTRL_BASE 0xF7030000 -#define SC_PERIPH_CTRL4 0x00C -#define CTRL4_FPGA_EXT_PHY_SEL BIT3 -#define CTRL4_PICO_SIDDQ BIT6 -#define CTRL4_PICO_OGDISABLE BIT8 -#define CTRL4_PICO_VBUSVLDEXT BIT10 -#define CTRL4_PICO_VBUSVLDEXTSEL BIT11 -#define CTRL4_OTG_PHY_SEL BIT21 - -#define SC_PERIPH_CTRL5 0x010 - -#define CTRL5_USBOTG_RES_SEL BIT3 -#define CTRL5_PICOPHY_ACAENB BIT4 -#define CTRL5_PICOPHY_BC_MODE BIT5 -#define CTRL5_PICOPHY_CHRGSEL BIT6 -#define CTRL5_PICOPHY_VDATSRCEND BIT7 -#define CTRL5_PICOPHY_VDATDETENB BIT8 -#define CTRL5_PICOPHY_DCDENB BIT9 -#define CTRL5_PICOPHY_IDDIG BIT10 - -#define SC_PERIPH_CTRL8 0x018 -#define SC_PERIPH_CLKEN0 0x200 -#define SC_PERIPH_CLKDIS0 0x204 -#define SC_PERIPH_CLKSTAT0 0x208 - -#define SC_PERIPH_RSTEN0 0x300 -#define SC_PERIPH_RSTDIS0 0x304 -#define SC_PERIPH_RSTSTAT0 0x308 - -#define RST0_USBOTG_BUS BIT4 -#define RST0_POR_PICOPHY BIT5 -#define RST0_USBOTG BIT6 -#define RST0_USBOTG_32K BIT7 - -#define EYE_PATTERN_PARA 0x7053348c - -#define MDDRC_AXI_BASE 0xF7120000 -#define AXI_REGION_MAP 0x100 -#define HIKEY_REGION_SIZE_MASK (7 << 8) -// (0 << 8) means 16MB, (7 << 8) means 2GB -#define HIKEY_REGION_SIZE(x) (1U << ((((x) & HIKEY_REGION_SIZE_MASK) >> 8) + 24)) - -#define AO_CTRL_BASE 0xF7800000 -#define SC_PW_MTCMOS_EN0 0x830 -#define SC_PW_MTCMOS_DIS0 0x834 -#define SC_PW_MTCMOS_STAT0 0x838 -#define SC_PW_MTCMOS_ACK_STAT0 0x83c -#define PW_EN0_G3D (1 << 1) - -#define PMUSSI_BASE 0xF8000000 - -#endif /* __HI6220_H__ */ diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h deleted file mode 100644 index c2e9d5dc9f4c33f7eca168a948b7619b1c03f9d6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __HI6220_REGS_PERI_H__ -#define __HI6220_REGS_PERI_H__ - -#define SC_PERIPH_CLKEN3 0x230 -#define SC_PERIPH_RSTEN3 0x330 -#define SC_PERIPH_RSTDIS0 0x304 -#define SC_PERIPH_RSTDIS3 0x334 -#define SC_PERIPH_RSTSTAT3 0x338 - -/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ -#define PERIPH_RST0_MMC2 (1 << 2) - -/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ -#define PERIPH_RST3_CSSYS (1 << 0) -#define PERIPH_RST3_I2C0 (1 << 1) -#define PERIPH_RST3_I2C1 (1 << 2) -#define PERIPH_RST3_I2C2 (1 << 3) -#define PERIPH_RST3_I2C3 (1 << 4) -#define PERIPH_RST3_UART1 (1 << 5) -#define PERIPH_RST3_UART2 (1 << 6) -#define PERIPH_RST3_UART3 (1 << 7) -#define PERIPH_RST3_UART4 (1 << 8) -#define PERIPH_RST3_SSP (1 << 9) -#define PERIPH_RST3_PWM (1 << 10) -#define PERIPH_RST3_BLPWM (1 << 11) -#define PERIPH_RST3_TSENSOR (1 << 12) -#define PERIPH_RST3_DAPB (1 << 18) -#define PERIPH_RST3_HKADC (1 << 19) -#define PERIPH_RST3_CODEC_SSI (1 << 20) -#define PERIPH_RST3_PMUSSI1 (1 << 22) - -#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) -#define PMUSSI_ONOFF8_REG (PMUSSI_BASE + (0x1c << 2)) -#define PMUSSI_ONOFF8_EN_32KB BIT6 - -#endif /* __HI6220_REGS_PERI_H__ */ diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec deleted file mode 100644 index e0339f093a9edcf4b2c342352c6713ef3cc9ef42..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/HisiPkg.dec +++ /dev/null @@ -1,282 +0,0 @@ -#/** @file -# -# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - DEC_SPECIFICATION = 0x00010005 - PACKAGE_NAME = HisiPkg - PACKAGE_GUID = c6013a10-758c-4c0d-bd07-e601e6721f86 - PACKAGE_VERSION = 0.1 - -[Includes] - Include - -[Ppis] - gIpmiInterfacePpiGuid = {0x28ae4d88, 0xb658, 0x46b9, {0xa0, 0xe7, 0xd4, 0x95, 0xe2, 0xe8, 0x97, 0xf}} - - - -[Protocols] - gUniNorFlashProtocolGuid = {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}} - gHisiSpiFlashProtocolGuid = {0x339132DC, 0xCED7, 0x4f84, {0xAA, 0xE7, 0x2E, 0xC4, 0xF9, 0x14, 0x38, 0x2F}} - - gHisiBoardNicProtocolGuid = {0xb5903955, 0x31e9, 0x4aaf, {0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66}} - gHisiBoardXgeStatusProtocolGuid = {0xa6b8ed0e, 0xd8cc, 0x4853, {0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97}} - gIpmiInterfaceProtocolGuid = {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}} - gBmcInfoProtocolGuid = {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, 0x3, 0xf6, 0x48, 0x0, 0xf5}} - gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}} - gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} - gHisiPlatformSasProtocolGuid = {0x20e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x6d}} - gHisiSnpPlatformProtocolGuid = {0x81321f27, 0xff58, 0x4a1d, {0x99, 0x97, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0x6f}} - gHisiInstalledAcpiProtocolGuid = {0x31505f6a, 0xe496, 0x4c7e, {0xba, 0xbb, 0x71, 0x7b, 0xe2, 0xc4, 0xb4, 0x59}} - gHisiSasConfigProtocolGuid = {0x3A236669, 0x6666, 0x4d04, {0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66}} - -[Guids] - gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}} - - gHisiEfiMemoryMapGuid = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}} - gOemConfigGuid = {0x42927b59, 0x58fc, 0x41be, {0x8f, 0x59, 0xd1, 0x7c, 0x02, 0x1a, 0x70, 0x13}} - gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}} - gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}} - gEfiHisiSocControllerGuid = {0xee369cc3, 0xa743, 0x5382, {0x75, 0x64, 0x53, 0xe4, 0x31, 0x19, 0x38, 0x35}} - -[LibraryClasses] - PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h - CpldIoLib|Include/Library/CpldIoLib.h - OemAddressMapLib|Include/Library/OemAddressMapLib.h - HisiOemMiscLib|Include/Library/HisiOemMiscLib.h - I2CLib|Include/Library/I2CLib.h - PlatformPciLib|Include/Library/PlatformPciLib.h - FdtUpdateLib|Include/Library/FdtUpdateLib.h - LpcLib|Include/Library/LpcLib.h - -[PcdsFixedAtBuild] - gHisiTokenSpaceGuid.PcdNORFlashBase|0x00000000|UINT64|0x01000008 - gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x1000000|UINT32|0x0100000c - - gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000|UINT32|0x01000010 - gHisiTokenSpaceGuid.PcdUartClkInHz|24000000|UINT32|0x0100001F - gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize|0x10000|UINT64|0x01000019 - - gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0|UINT64|0x00000047 - gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0|UINT64|0x00000046 - gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0|UINT64|0x00000048 - gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0|UINT64|0x00000049 - - gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0|UINT64|0x01000023 - gHisiTokenSpaceGuid.PcdCpldBaseAddress|0|UINT64|0x01000024 - gHisiTokenSpaceGuid.PcdMailBoxAddress|0|UINT64|0x01000025 - - gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0|UINT64|0x01000037 - gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0|UINT64|0x01000038 - - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0|UINT64|0x01000041 - - gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0|UINT64|0x01000042 - - gHisiTokenSpaceGuid.PcdFirmwareVendor|L"Huawei Corp."|VOID*|0x30000052 - gHisiTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053 - gHisiTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054 - gHisiTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000055 - gHisiTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000056 - gHisiTokenSpaceGuid.PcdCPUInfo|L""|VOID*|0x30000060 - gHisiTokenSpaceGuid.PcdBiosVersionString|L""|VOID*|0x00010069 - gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L""|VOID*|0x00010070 - - gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x0|UINT32|0x40000001 - - gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x0|UINT32|0x40000002 - gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x0|UINT64|0x40000003 - - gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x0|UINT32|0x40000004 - - gHisiTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x30006554 - - #FDT File Address - gHisiTokenSpaceGuid.FdtFileAddress|0x0|UINT64|0x40000005 - - #Reserved for NVRAM - gHisiTokenSpaceGuid.PcdReservedNvramBase|0x0|UINT64|0x40000006 - gHisiTokenSpaceGuid.PcdReservedNvramSize|0x0|UINT64|0x40000007 - - gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 - gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 - gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a - gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b - gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b - - gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c - gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d - - gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038 - - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0|UINT32|0x00000044 - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0|UINT32|0x00000045 - - gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000|UINT64|0x00000051 # 4T - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000052 - gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0|UINT64|0x00000053 - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000054 - gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0|UINT64|0x00000055 - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000056 - gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0|UINT64|0x00000057 - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000058 - gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0|UINT64|0x00000059 - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000152 - gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0|UINT64|0x00000153 - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000154 - gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0|UINT64|0x00000155 - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000156 - gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0|UINT64|0x00000157 - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000158 - gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0|UINT64|0x00000159 - - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000252 - gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0|UINT64|0x00000253 - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000254 - gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0|UINT64|0x00000255 - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000256 - gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0|UINT64|0x00000257 - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000258 - gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0|UINT64|0x00000259 - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000352 - gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0|UINT64|0x00000353 - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000354 - gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0|UINT64|0x00000355 - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000356 - gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0|UINT64|0x00000357 - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000358 - gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0|UINT64|0x00000359 - - gHisiTokenSpaceGuid.PciHb0Rb0Base|0|UINT64|0x0000005a - gHisiTokenSpaceGuid.PciHb0Rb1Base|0|UINT64|0x0000005b - gHisiTokenSpaceGuid.PciHb0Rb2Base|0|UINT64|0x0000005c - gHisiTokenSpaceGuid.PciHb0Rb3Base|0|UINT64|0x0000005d - gHisiTokenSpaceGuid.PciHb0Rb4Base|0|UINT64|0x0100005a - gHisiTokenSpaceGuid.PciHb0Rb5Base|0|UINT64|0x0100005b - gHisiTokenSpaceGuid.PciHb0Rb6Base|0|UINT64|0x0100005c - gHisiTokenSpaceGuid.PciHb0Rb7Base|0|UINT64|0x0100005d - gHisiTokenSpaceGuid.PciHb1Rb0Base|0|UINT64|0x0200005a - gHisiTokenSpaceGuid.PciHb1Rb1Base|0|UINT64|0x0200005b - gHisiTokenSpaceGuid.PciHb1Rb2Base|0|UINT64|0x0200005c - gHisiTokenSpaceGuid.PciHb1Rb3Base|0|UINT64|0x0200005d - gHisiTokenSpaceGuid.PciHb1Rb4Base|0|UINT64|0x0300005a - gHisiTokenSpaceGuid.PciHb1Rb5Base|0|UINT64|0x0300005b - gHisiTokenSpaceGuid.PciHb1Rb6Base|0|UINT64|0x0300005c - gHisiTokenSpaceGuid.PciHb1Rb7Base|0|UINT64|0x0300005d - - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0|UINT64|0x8000005a - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0|UINT64|0x8000005b - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0|UINT64|0x8000005c - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0|UINT64|0x8000005d - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0|UINT64|0x8000005e - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0|UINT64|0x8000005f - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0|UINT64|0x80000060 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0|UINT64|0x80000061 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0|UINT64|0x80000062 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0|UINT64|0x80000063 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0|UINT64|0x80000064 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0|UINT64|0x80000065 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0|UINT64|0x80000066 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0|UINT64|0x80000067 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0|UINT64|0x80000068 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0|UINT64|0x80000069 - - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0|UINT64|0x6000005a - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0|UINT64|0x6000005b - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0|UINT64|0x6000005c - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0|UINT64|0x6000005d - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0|UINT64|0x6000005e - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0|UINT64|0x6000005f - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0|UINT64|0x60000060 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0|UINT64|0x60000061 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0|UINT64|0x60000062 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0|UINT64|0x60000063 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0|UINT64|0x60000064 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0|UINT64|0x60000065 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0|UINT64|0x60000066 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0|UINT64|0x60000067 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0|UINT64|0x60000068 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0|UINT64|0x60000069 - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0|UINT64|0x7000005a - gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0|UINT64|0x7000005b - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0|UINT64|0x7000005c - gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0|UINT64|0x7000005d - gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0|UINT64|0x7000005e - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0|UINT64|0x7000005f - gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0|UINT64|0x70000060 - gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0|UINT64|0x70000061 - gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0|UINT64|0x70000062 - gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0|UINT64|0x70000063 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0|UINT64|0x70000064 - gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0|UINT64|0x70000065 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0|UINT64|0x70000066 - gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0|UINT64|0x70000067 - gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0|UINT64|0x70000068 - gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0|UINT64|0x70000069 - - gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0|UINT64|0x3000005a - gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0|UINT64|0x3000005b - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0|UINT64|0x3000005c - gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005d - gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0|UINT64|0x3000005e - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0|UINT64|0x30000070 - gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0|UINT64|0x30000061 - gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0|UINT64|0x30000062 - gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0|UINT64|0x30000063 - gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0|UINT64|0x30000064 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0|UINT64|0x30000065 - gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0|UINT64|0x30000066 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0|UINT64|0x30000067 - gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0|UINT64|0x30000068 - gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0|UINT64|0x30000069 - gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0|UINT64|0x3000006a - - gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0|UINT64|0x9000005a - gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0|UINT64|0x9000005b - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0|UINT64|0x9000005c - gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0|UINT64|0x9000005d - gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0|UINT64|0x9100005a - gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0|UINT64|0x9100005b - gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0|UINT64|0x9100005c - gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0|UINT64|0x9100005d - gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0|UINT64|0x9010005a - gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0|UINT64|0x9010005b - gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0|UINT64|0x9010005c - gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0|UINT64|0x9010005d - gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0|UINT64|0x9110005a - gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0|UINT64|0x9110005b - gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0|UINT64|0x9110005c - gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0|UINT64|0x9110005d - - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0|UINT64|0x2000005a - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0|UINT64|0x2000005b - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0|UINT64|0x2000005c - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0|UINT64|0x2000005d - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0|UINT64|0x2100005a - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0|UINT64|0x2100005b - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0|UINT64|0x2100005c - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0|UINT64|0x2100005d - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0|UINT64|0x2010005a - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0|UINT64|0x2010005b - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0|UINT64|0x2010005c - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0|UINT64|0x2010005d - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0|UINT64|0x2110005a - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0|UINT64|0x2110005b - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0|UINT64|0x2110005c - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d - - gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061 - gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056 - -[PcdsFeatureFlag] - gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065 - - - diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc deleted file mode 100644 index 2ace79dbd118918e7251e2ab4805eb4deabb6f54..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ /dev/null @@ -1,304 +0,0 @@ -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# - -[LibraryClasses.common] -!if $(TARGET) == RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!else - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf -!endif - DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf - - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf - BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf - SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf - SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf - CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf - ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.inf - - UefiLib|MdePkg/Library/UefiLib/UefiLib.inf - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf - UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf - UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - - UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - # - # Allow dynamic PCDs - # - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - - BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf - - # ARM Architectural Libraries - CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf - DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf - CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf - ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf - ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf - - ResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf - ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf - - # ARM PL011 UART Driver - PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf - PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf - - SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf - TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf - - UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - # - # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window - # in the debugger will show load and unload commands for symbols. You can cut and paste this - # into the command window to load symbols. We should be able to use a script to do this, but - # the version of RVD I have does not support scripts accessing system memory. - # - #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf - #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf - PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf - - DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf - DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf - - SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf - - TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf - AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf - - # BDS Libraries - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf - UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - - VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf - VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf - VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf - - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - - NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf - - FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf - RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf - IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf - BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf - EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf - IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf - PlatformFlashAccessLib|Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf - -[LibraryClasses.common.SEC] - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - -[LibraryClasses.common.PEI_CORE] - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf - PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf - - PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - -[LibraryClasses.common.PEIM] - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf - PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf - ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf - - PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf - - ## Fixed compile error after upgrade to 14.10 - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - -[LibraryClasses.common.DXE_CORE] - HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf - MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf - DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf - -[LibraryClasses.common.DXE_DRIVER] - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - -[LibraryClasses.common.UEFI_APPLICATION] - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - -[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION] - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf - -[LibraryClasses.common.UEFI_DRIVER] - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf - -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf -!ifndef CONFIG_NO_DEBUGLIB - DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf -!endif -!if $(TARGET) != RELEASE - DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf -!endif - VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf - -[LibraryClasses.AARCH64] - ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf - -[BuildOptions] - GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG - -[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] - GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 - GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE - - gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE - - gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE - -[PcdsFixedAtBuild.common] - # - # IO is mapped to memory space, so we use the same size of - # PcdPrePiCpuMemorySize - # - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 - gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 - gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 - gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 - gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 - gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 - gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 - - # DEBUG_ASSERT_ENABLED 0x01 - # DEBUG_PRINT_ENABLED 0x02 - # DEBUG_CODE_ENABLED 0x04 - # CLEAR_MEMORY_ENABLED 0x08 - # ASSERT_BREAKPOINT_ENABLED 0x10 - # ASSERT_DEADLOOP_ENABLED 0x20 -!if $(TARGET) == RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f -!endif - - # DEBUG_INIT 0x00000001 // Initialization - # DEBUG_WARN 0x00000002 // Warnings - # DEBUG_LOAD 0x00000004 // Load events - # DEBUG_FS 0x00000008 // EFI File system - # DEBUG_POOL 0x00000010 // Alloc & Free's - # DEBUG_PAGE 0x00000020 // Alloc & Free's - # DEBUG_INFO 0x00000040 // Verbose - # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers - # DEBUG_VARIABLE 0x00000100 // Variable - # DEBUG_BM 0x00000400 // Boot Manager - # DEBUG_BLKIO 0x00001000 // BlkIo Driver - # DEBUG_NET 0x00004000 // SNI Driver - # DEBUG_UNDI 0x00010000 // UNDI Driver - # DEBUG_LOADFILE 0x00020000 // UNDI Driver - # DEBUG_EVENT 0x00080000 // Event messages - # DEBUG_ERROR 0x80000000 // Error - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06 - - # - # Optional feature to help prevent EFI memory map fragments - # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob - # Values are in EFI Pages (4K). DXE Core will make sure that - # at least this much of each type of memory can be allocated - # from a single memory range. This way you only end up with - # maximum of two fragements for each type in the memory map - # (the memory used, and the free memory that was prereserved - # but not used). - # - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 - - # Set timer interrupt to be triggerred in 1ms to avoid missing - # serial terminal input characters. - gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 - gArmTokenSpaceGuid.PcdVFPEnabled|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 - -[PcdsDynamicHii.common.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout" - diff --git a/Silicon/Hisilicon/Hisilicon.fdf.inc b/Silicon/Hisilicon/Hisilicon.fdf.inc deleted file mode 100644 index 733f53c8022cb581ba88fd4d2db275516a6e5194..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Hisilicon.fdf.inc +++ /dev/null @@ -1,133 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -################################################################################ -# -# Rules are use with the [FV] section's module INF type to define -# how an FFS file is created for a given INF file. The following Rule are the default -# rules for the different module type. User can add the customized rules to define the -# content of the FFS file. -# -################################################################################ - - -############################################################################ -# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # -############################################################################ -# -#[Rule.Common.DXE_DRIVER] -# FILE DRIVER = $(NAMED_GUID) { -# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex -# COMPRESS PI_STD { -# GUIDED { -# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi -# UI STRING="$(MODULE_NAME)" Optional -# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) -# } -# } -# } -# -############################################################################ - -[Rule.Common.SEC] - FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -[Rule.Common.PEI_CORE] - FILE PEI_CORE = $(NAMED_GUID) { - TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING ="$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM] - FILE PEIM = $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM.BINARY] - FILE PEIM = $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - TE TE Align = Auto |.efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM.FMP_IMAGE_DESC] - FILE PEIM = $(NAMED_GUID) { - RAW BIN |.acpi - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.DXE_CORE] - FILE DXE_CORE = $(NAMED_GUID) { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.UEFI_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_RUNTIME_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.UEFI_APPLICATION] - FILE APPLICATION = $(NAMED_GUID) { - UI STRING ="$(MODULE_NAME)" Optional - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -[Rule.Common.UEFI_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_APPLICATION.BINARY] - FILE APPLICATION = $(NAMED_GUID) { - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.USER_DEFINED.ACPITABLE] - FILE FREEFORM = $(NAMED_GUID) { - RAW ACPI |.acpi - RAW ASL |.aml - } - diff --git a/Silicon/Hisilicon/Include/Guid/MemoryMapData.h b/Silicon/Hisilicon/Include/Guid/MemoryMapData.h deleted file mode 100644 index af7b6456a8cfcb6b1403371fa2660286330939bd..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Guid/MemoryMapData.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#ifndef _MEMORY_MAP_GUID_H_ -#define _MEMORY_MAP_GUID_H_ - -#define EFI_MEMORY_MAP_GUID \ - { \ - 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ - } - -extern EFI_GUID gHisiEfiMemoryMapGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Guid/VersionInfoHobGuid.h b/Silicon/Hisilicon/Include/Guid/VersionInfoHobGuid.h deleted file mode 100644 index 9eeb0a5f7482859cbee2944be97481efe8e98ac8..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Guid/VersionInfoHobGuid.h +++ /dev/null @@ -1,29 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _VERSION_INFO_HOB_GUID_H_ -#define _VERSION_INFO_HOB_GUID_H_ - -// {0E13A14C-859C-4f22-82BD-180EE14212BF} -#define VERSION_INFO_HOB_GUID \ - {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}} - -extern GUID gVersionInfoHobGuid; - -#pragma pack(1) - -typedef struct { - EFI_TIME BuildTime; - CHAR16 String[1]; -} VERSION_INFO; - -#pragma pack() - -#endif - diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h deleted file mode 100644 index ea2aa34c6da17a67b325874b8b54f4a7a3ea8e07..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#ifndef __ACPI_NEXT_LIB_H__ -#define __ACPI_NEXT_LIB_H__ - -#include - -/// -/// ITS Affinity Structure Definition -/// -#pragma pack(1) -typedef struct { - UINT8 Type; - UINT8 Length; - UINT32 ProximityDomain; - UINT16 Reserved; - UINT32 ItsHwId; -} EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE; -#pragma pack() - -#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ - { \ - EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ - GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\ - } - -#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \ - GicRBase, GicRlength) \ - { \ - EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ - GicRBase, GicRlength \ - } - -#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \ - ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ - { \ - 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ - ACPIProcessorUID, Flags, ClockDomain \ - } - -#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT( \ - ProximityDomain, ItsId) \ - { \ - 4, sizeof (EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE), ProximityDomain, \ - EFI_ACPI_RESERVED_WORD, ItsId \ - } - -#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ - ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ - { \ - 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ - AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \ - EFI_ACPI_RESERVED_QWORD \ - } - -#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ - GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \ - { \ - EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ - GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ - GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \ - } - -#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \ - { \ - EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ - GicDistHwId, GicDistBase, GicDistVector, GicVersion, \ - {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \ - } - - -#pragma pack(1) -// -// Define the number of each table type. -// This is where the table layout is modified. -// -#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT (MAX_SOCKET*CORE_NUM_PER_SOCKET) - -typedef struct { - EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; - EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]; - EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; - EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT]; -} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; - -#pragma pack() -#endif - diff --git a/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h b/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h deleted file mode 100644 index acee9c4477f65b44b6bfb4c5d3d6994787541e8d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h +++ /dev/null @@ -1,25 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _BMC_CONFIG_BOOT_LIB_H_ -#define _BMC_CONFIG_BOOT_LIB_H_ - -VOID -EFIAPI -RestoreBootOrder ( - VOID - ); - -VOID -EFIAPI -HandleBmcBootType ( - VOID - ); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/CpldIoLib.h b/Silicon/Hisilicon/Include/Library/CpldIoLib.h deleted file mode 100644 index c059d8fcd0d649ad18059106c1dd0c37de878fe7..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/CpldIoLib.h +++ /dev/null @@ -1,16 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _CPLD_IO_LIB_H_ -#define _CPLD_IO_LIB_H_ - -VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue); -UINT8 ReadCpldReg(UINTN ulRegAddr); - -#endif /* _CPLD_IO_LIB_H_ */ diff --git a/Silicon/Hisilicon/Include/Library/FdtUpdateLib.h b/Silicon/Hisilicon/Include/Library/FdtUpdateLib.h deleted file mode 100644 index ec58988a001a818fcb182ec70f50def45c78d52f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/FdtUpdateLib.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#ifndef _FDTUPDATELIB_H_ -#define _FDTUPDATELIB_H_ - -#define ADD_FILE_LENGTH 0x400 - -typedef struct -{ - UINT32 BaseHigh; - UINT32 BaseLow; - UINT32 LengthHigh; - UINT32 LengthLow; -}PHY_MEM_REGION; - -typedef struct -{ - UINT8 data0; - UINT8 data1; - UINT8 data2; - UINT8 data3; - UINT8 data4; - UINT8 data5; -}MAC_ADDRESS; - -extern EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr); - -#endif - - diff --git a/Silicon/Hisilicon/Include/Library/HisiOemMiscLib.h b/Silicon/Hisilicon/Include/Library/HisiOemMiscLib.h deleted file mode 100644 index bb040e61703b83a178a9651094059733eea9807a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/HisiOemMiscLib.h +++ /dev/null @@ -1,125 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef HISI_OEM_MISC_LIB_H_ -#define HISI_OEM_MISC_LIB_H_ - -#include - -#include -#include - -#define HCCS_PLL_VALUE_2600 0x52240681 -#define HCCS_PLL_VALUE_2800 0x52240701 -#define HCCS_PLL_VALUE_3000 0x52240781 - -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - - -#define PCIEDEVICE_REPORT_MAX 8 -#define MAX_PROCESSOR_SOCKETS MAX_SOCKET -#define MAX_MEMORY_CHANNELS MAX_CHANNEL -#define MAX_DIMM_PER_CHANNEL MAX_DIMM - -typedef struct _REPORT_PCIEDIDVID2BMC{ - UINTN Bus; - UINTN Device; - UINTN Function; - UINTN Slot; -}REPORT_PCIEDIDVID2BMC; -extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX]; -extern VOID GetPciDidVid (REPORT_PCIEDIDVID2BMC *Report); - -BOOLEAN OemIsSocketPresent (UINTN Socket); -VOID CoreSelectBoot(VOID); -VOID OemPcieResetAndOffReset(void); -extern I2C_DEVICE gRtcDevice; - -UINTN OemGetSocketNumber(VOID); -UINTN OemGetDdrChannel (VOID); -UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel); - -BOOLEAN OemIsMpBoot(); -UINT32 OemIsWarmBoot(); - -VOID OemBiosSwitch(UINT32 Master); -BOOLEAN OemIsNeedDisableExpanderBuffer(VOID); - -extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; -EFI_HII_HANDLE EFIAPI OemGetPackages (); -UINTN OemGetCpuFreq (UINT8 Socket); - -UINTN -OemGetHccsFreq ( - VOID - ); - -EFI_STATUS -OemGetSerdesParam ( - SERDES_PARAM *ParamA, - SERDES_PARAM *ParamB, - UINT32 SocketId - ); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h deleted file mode 100644 index 21f5c7482dbfa90b28ef5b081e1668d9849f296f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h +++ /dev/null @@ -1,694 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _HW_MEM_INIT_LIB_H_ -#define _HW_MEM_INIT_LIB_H_ - -#include - -#define I2C_CHANNEL 2 -#define MAX_I2C_DEV 6 - -#define SPD_MODULE_PART 18 -#define SPD_MODULE_PART_DDR4 20 - -#define NVRAM_ADDR 0x00D00000 - -typedef enum { - DDR_FREQ_AUTO = 0, - DDR_FREQ_800, - DDR_FREQ_1000, - DDR_FREQ_1066, - DDR_FREQ_1200, - DDR_FREQ_1333, - DDR_FREQ_1400, - DDR_FREQ_1600, - DDR_FREQ_1800, - DDR_FREQ_1866, - DDR_FREQ_2000, - DDR_FREQ_2133, - DDR_FREQ_2200, - DDR_FREQ_2400, - DDR_FREQ_2600, - DDR_FREQ_2666, - DDR_FREQ_2800, - DDR_FREQ_2933, - DDR_FREQ_3000, - DDR_FREQ_3200, - DDR_FREQ_MAX -} DDR_FREQUENCY_INDEX; - -struct baseMargin { - INT16 n; - INT16 p; -}; - -struct rankMargin { - struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH]; -}; - -typedef struct _NVRAM_RANK_DATA { - UINT16 MR0; - UINT16 MR1; - UINT16 MR2; - UINT16 MR3; - UINT16 MR4; - UINT16 MR5; - UINT16 MR6[9]; -} NVRAM_RANK_DATA; - -typedef struct _NVRAM_DIMM_DATA { - NVRAM_RANK_DATA Rank[MAX_RANK_DIMM]; -} NVRAM_DIMM_DATA; - - -typedef struct _NVRAM_CHANNEL_DATA { - NVRAM_DIMM_DATA Dimm[MAX_DIMM]; - UINT32 DDRC_CFG_ECC; - UINT32 DDRC_CFG_WORKMODE; - UINT32 DDRC_CFG_WORKMODE1; - UINT32 DDRC_CFG_WORKMODE2; - UINT32 DDRC_CFG_DDRMODE; - UINT32 DDRC_CFG_DIMM; - UINT32 DDRC_CFG_RNKVOL_0; - UINT32 DDRC_CFG_RNKVOL_1; - UINT32 DDRC_CFG_RNKVOL_2; - UINT32 DDRC_CFG_RNKVOL_3; - UINT32 DDRC_CFG_RNKVOL_4; - UINT32 DDRC_CFG_RNKVOL_5; - UINT32 DDRC_CFG_RNKVOL_6; - UINT32 DDRC_CFG_RNKVOL_7; - UINT32 DDRC_CFG_RNKVOL_8; - UINT32 DDRC_CFG_RNKVOL_9; - UINT32 DDRC_CFG_RNKVOL_10; - UINT32 DDRC_CFG_RNKVOL_11; - UINT32 DDRC_CFG_ODT_0; - UINT32 DDRC_CFG_ODT_1; - UINT32 DDRC_CFG_ODT_2; - UINT32 DDRC_CFG_ODT_3; - UINT32 DDRC_CFG_ODT_4; - UINT32 DDRC_CFG_ODT_5; - UINT32 DDRC_CFG_ODT_6; - UINT32 DDRC_CFG_ODT_7; - UINT32 DDRC_CFG_ODT_8; - UINT32 DDRC_CFG_ODT_9; - UINT32 DDRC_CFG_ODT_10; - UINT32 DDRC_CFG_ODT_11; - UINT32 DDRC_CFG_TIMING0; - UINT32 DDRC_CFG_TIMING1; - UINT32 DDRC_CFG_TIMING2; - UINT32 DDRC_CFG_TIMING3; - UINT32 DDRC_CFG_TIMING4; - UINT32 DDRC_CFG_TIMING5; - UINT32 DDRC_CFG_TIMING6; - UINT32 DDRC_CFG_TIMING7; - UINT32 DDRC_CFG_DFI_LAT0; - UINT32 DDRC_CFG_DFI_LAT1; - UINT32 DDRC_CFG_DDRPHY; - UINT32 Config[24]; - BOOLEAN Status; -} NVRAM_CHANNEL_DATA; - -typedef struct _NVRAM_DATA { - UINT32 NvramCrc; - NVRAM_CHANNEL_DATA Channel[MAX_SOCKET][MAX_CHANNEL]; - UINT32 DdrFreqIdx; - -} NVRAM_DATA; - -struct DDR_RANK_DATA { - BOOLEAN Enabled; -}; - -typedef struct _DDR_DIMM_DATA { - BOOLEAN Enabled; - UINT8 DramType; //Byte 2 - UINT8 ModuleType; //Byte 3 - UINT8 BankNum; //Byte 4 - UINT8 RowBits; //Byte 5 - UINT8 ColBits; //Byte 5 - UINT8 SpdVdd; //Byte 6 - UINT8 RankNum; //Byte 7 - UINT8 PrimaryBusWidth; //Byte 8 - UINT8 ExtensionBusWidth; //Byte 8 - UINT8 SpdModPart[SPD_MODULE_PART]; // Module Part Number - UINT8 SpdModPartDDR4[SPD_MODULE_PART_DDR4]; // Module Part Number DDR4 - UINT16 SpdMMfgId; // Module Mfg Id from SPD - UINT32 SpdSerialNum; - UINT32 RankSize; - UINT16 DimmSize; - UINT16 DimmSpeed; - UINT16 SpdMMDate; - struct DDR_RANK_DATA Rank[MAX_RANK_DIMM]; -} DDR_DIMM_DATA; - -typedef struct _DDR_CHANNEL_DATA { - BOOLEAN Enabled; - DDR_DIMM_DATA Dimm[MAX_DIMM]; - UINT8 CurrentDimmNum; -} DDR_CHANNEL_DATA; - -typedef struct _MEMORY_DATA { - UINT8 RascBypass; -} MEMORY_DATA; - -typedef struct _NUMAINFO_DATA { - UINT8 NodeId; - UINT64 Base; - UINT64 Length; - UINT32 ScclInterleaveEn; -} NUMAINFO_DATA; - - -typedef struct _GBL_DATA_INTERFACE { - DDR_CHANNEL_DATA Channel[MAX_SOCKET][MAX_CHANNEL]; - UINT32 DdrFreqIdx; - UINT32 Freq; - UINT32 EccEn; - UINT32 MemSize; - BOOLEAN SetupExist; - NVRAM_DATA NvRamData; - MEMORY_DATA MemData; - NUMAINFO_DATA NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE]; -} GBL_INTERFACE; - -typedef union { - struct { - UINT16 freqIndex:4; //Frequency Index; - UINT16 slot0:4; //Channel slot0 for DIMM - UINT16 slot1:4; //Channel slot1 for DIMM - UINT16 slot2:4; //Channel slot2 for DIMM - }Bits; - UINT16 Data; -}ODT_VALUE_INDEX; - -typedef union { - struct { - UINT8 RTTNom:3; - UINT8 reserved_3:1; - UINT8 RTTWr:2; - UINT8 reserved_6:2; - }Bits; - UINT8 Data; -}ODT_RTT_VALUE_DDR3; - -typedef union { - struct { - UINT8 RTTNom:3; - UINT8 RTTPark:3; - UINT8 RTTWr:2; - }Bits; - UINT8 Data; -}ODT_RTT_VALUE_DDR4; - -typedef union { - struct { - UINT16 tarDimm:2; // target DIMM - UINT16 tarRank:2; // target Rank - UINT16 slot0:4; // Channel slot0 for DIMM - UINT16 slot1:4; // Channel slot1 for DIMM - UINT16 slot2:4; // Channel slot2 for DIMM - }Bits; - UINT16 Data; -}ODT_ACTIVE_INDEX; - -struct ODT_VALUE_STRUCT_DDR3 { - UINT16 config; // ODT_VALUE_INDEX - UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; // ODT_VALUE_RTT_DDR3 -}; - -struct ODT_VALUE_STRUCT_DDR4 { - UINT16 config; - UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; -}; - -struct ODT_ACTIVE_STRUCT { - UINT16 config; // ODT config index - UINT16 actBits[2]; // WR :Bits[3;0] = D0_R[3:0] Bits[7:4] = D1_R[3:0] Bits[11:8] = D2_R[3:0] -}; - -// JEDEC manufacturer IDs from JEP-106 -#define MFGID_AENEON 0x5705 -#define MFGID_QIMONDA 0x5105 -#define MFGID_NEC 0x1000 -#define MFGID_IDT 0xB300 -#define MFGID_TI 0x9700 -#define MFGID_HYNIX 0xAD00 -#define MFGID_MICRON 0x2C00 -#define MFGID_INFINEON 0xC100 -#define MFGID_SAMSUNG 0xCE00 -#define MFGID_TEK 0x3D00 -#define MFGID_KINGSTON 0x9801 -#define MFGID_ELPIDA 0xFE02 -#define MFGID_SMART 0x9401 -#define MFGID_AGILENT 0xC802 -#define MFGID_NANYA 0x0B03 -#define MFGID_INPHI 0xB304 -#define MFGID_MONTAGE 0x3206 -#define MFGID_RAMAXEL 0x4304 - -// -// DDR3 frequencies 800 - 2667 -// DDR4 frequencies 1333 - 3200 -// -#define DDR_800 0 // tCK(ns)=2.5 -#define DDR_1000 1 // tCK(ns)=2.0 -#define DDR_1066 2 // tCK(ns)=1.875 -#define DDR_1200 3 // tCK(ns)=1.667 -#define DDR_1333 4 // tCK(ns)=1.5 -#define DDR_1400 5 // tCK(ns)=1.429 -#define DDR_1600 6 // tCK(ns)=1.25 -#define DDR_1800 7 // tCK(ns)=1.11 -#define DDR_1866 8 // tCK(ns)=1.07 -#define DDR_2000 9 // tCK(ns)=1.0 -#define DDR_2133 10 // tCK(ns)=0.9375 -#define DDR_2200 11 // tCK(ns)=0.909 -#define DDR_2400 12 // tCK(ns)=0.833 -#define DDR_2600 13 // tCK(ns)=0.769 -#define DDR_2666 14 // tCK(ns)=0.750 -#define DDR_2800 15 // tCK(ns)=0.714 -#define DDR_2933 16 // tCK(ns)=0.682 -#define DDR_3000 17 // tCK(ns)=0.667 -#define DDR_3200 18 // tCK(ns)=0.625 -#define DDR_MAX (DDR_3200) - -#define FREQUENCY_MTB_OFFSET 1000000 -#define FREQUENCY_FTB_OFFSET 1000 - -// -#define DDR_800_TCK_MIN 25000 -#define DDR_1000_TCK_MIN 20000 -#define DDR_1067_TCK_MIN 18750 -#define DDR_1200_TCK_MIN 16670 -#define DDR_1333_TCK_MIN 15000 -#define DDR_1400_TCK_MIN 14290 -#define DDR_1600_TCK_MIN 12500 -#define DDR_1800_TCK_MIN 11100 -#define DDR_1867_TCK_MIN 10710 -#define DDR_2000_TCK_MIN 10000 -#define DDR_2133_TCK_MIN 9380 -#define DDR_2200_TCK_MIN 9090 -#define DDR_2400_TCK_MIN 8330 -#define DDR_2600_TCK_MIN 7690 -#define DDR_2667_TCK_MIN 7500 -#define DDR_2800_TCK_MIN 7140 -#define DDR_2933_TCK_MIN 6820 -#define DDR_3000_TCK_MIN 6670 -#define DDR_3200_TCK_MIN 6250 - - -// -// Serial Presence Detect bytes (JEDEC revision 1.0) -// -#define SPD_SIZE 0 // Bytes used, Device size, CRC coverage -#define SPD_REVISION 1 // SPD Encoding Revision -#define SPD_KEY_BYTE 2 // DRAM Device Type - #define SPD_TYPE_DDR3 0x0B // DDR3 SDRAM - #define SPD_TYPE_DDR4 0x0C // DDR4 SDRAM -#define SPD_KEY_BYTE2 3 // Module Type and Thickness (RDIMM or UDIMM) - #define SPD_RDIMM 1 // Module type is RDIMM - #define SPD_UDIMM 2 // Module type is UDIMM - #define SPD_SODIMM 3 // Module type is SODIMM - #define SPD_MICRO_DIMM 4 // Module type is Micro-DIMM - #define SPD_LRDIMM_DDR4 4 // Module type is LRDIMM (DDR4) - #define SPD_MINI_RDIMM 5 // Module type is Mini-RDIMM - #define SPD_MINI_UDIMM 6 // Module type is Mini-UDIMM - #define SPD_MINI_CDIMM 7 // Module type is Mini-CDIMM - #define SPD_ECC_SO_UDIMM 9 // Module type is 72b-SO-UDIMM - #define SPD_ECC_SO_RDIMM 8 // Module type is 72b-SO-RDIMM - #define SPD_ECC_SO_CDIMM 10 // Module type is 72b-SO-CDIMM - #define SPD_LRDIMM 11 // Module type is LRDIMM - #define SPD_UDIMM_ECC 18 // Module type is UDIMM-ECC -#define SPD_SDRAM_BANKS 4 // SDRAM Density and number of internal banks - #define SPD_1Gb 2 // Total SDRAM Capacity 1 Gigabits - #define SPD_2Gb 3 // Total SDRAM Capacity 2 Gigabits - #define SPD_4Gb 4 // Total SDRAM Capacity 4 Gigabits - #define SPD_8Gb 5 // Total SDRAM Capacity 8 Gigabits - #define SPD_16Gb 6 // Total SDRAM Capacity 16 Gigabits - #define SPD_32Gb 7 // Total SDRAM Capacity 32 Gigabits -#define SPD_SDRAM_ADDR 5 // Number of Row and Column address bits - #define SPD_ROW_12 0 // 12 row bits - #define SPD_ROW_13 1 // 13 row bits - #define SPD_ROW_14 2 // 14 row bits - #define SPD_ROW_15 3 // 15 row bits - #define SPD_ROW_16 4 // 16 row bits - #define SPD_ROW_17 5 // 17 row bits - #define SPD_ROW_18 6 // 18 row bits - #define SPD_COL_9 0 // 9 colum bits - #define SPD_COL_10 1 // 10 colum bits - #define SPD_COL_11 2 // 11 colum bits - #define SPD_COL_12 3 // 12 colum bits -#define SPD_VDD_SUPPORT 6 // Vdd DIMM supports - #define SPD_VDD_150 0 // Module Supports 1.50V - #define SPD_VDD_135 BIT1 // Module Supports 1.35V - #define SPD_VDD_125 BIT2 // Module Supports 1.25V -#define SPD_MODULE_ORG_DDR3 7 // Number of Ranks and SDRAM device width -#define SPD_MODULE_ORG_DDR4 12 // DDR4 Module Organization - #define DEVICE_WIDTH_X4 0 // SDRAM device width = 4 bits - #define DEVICE_WIDTH_X8 1 // SDRAM device width = 8 bits - #define DEVICE_WIDTH_X16 2 // SDRAM device width = 16 bits - #define SPD_NUM_RANKS_1 0 - #define SPD_NUM_RANKS_2 1 - #define SPD_NUM_RANKS_4 3 - #define SPD_NUM_RANKS_8 4 -#define SPD_MEM_BUS_WID 8 // Width of SDRAM memory bus -#define SPD_FTB 9 // Timebase for fine grain timing calculations -#define SPD_MTB_DIVEND 10 // Medium Time Base Dividend -#define SPD_MTB_DIVISOR 11 // Medium Time Base Divisor -#define SPD_MIN_TCK 12 // Minimum cycle time (at max CL) - #define SPD_TCKMIN_800 20 // tCK(MTB)=20, tCK(ns)=2.5 - #define SPD_TCKMIN_1067 15 // tCK(MTB)=15, tCK(ns)=1.875 - #define SPD_TCKMIN_1333 12 // tCK(MTB)=12, tCK(ns)=1.5 - #define SPD_TCKMIN_1600 10 // tCK(MTB)=10, tCK(ns)=1.25 - #define SPD_TCKMIN_1867 9 // tCK(MTB)=9, tCK(ns)=1.07 - #define SPD_TCKMIN_2133 8 // tCK(MTB)=8, tCK(ns)=0.9375 - #define SPD_TCKMIN_2400 7 // tCK(MTB)=7, tCK(ns)=.833 -#define SPD_CAS_LT_SUP_LSB 14 // CAS Latencies Supported, Least Significant Byte -#define SPD_CAS_LT_SUP_MSB 15 // CAS Latencies Supported, Most Significant Byte -#define SPD_MIN_TAA 16 // Minimum CAS Latency Time (tAAmin) -#define SPD_MIN_TWR 17 // Minimum Write Recovery Time -#define SPD_MIN_TRCD 18 // Minimum RAS to CAS delay -#define SPD_MIN_TRRD 19 // Minimum Row active to row active delay -#define SPD_MIN_TRP 20 // Minimum Row Precharge time -#define SPD_EXT_TRC_TRAS 21 // Upper nibbles for min tRAS and tRC -#define SPD_MIN_TRAS 22 // Minimum Active to Precharge time -#define SPD_MIN_TRC 23 // Minimum Active to Active/Refresh time -#define SPD_MIN_TRFC_LSB 24 // Minimum Refresh Recovery time least-significant byte -#define SPD_MIN_TRFC_MSB 25 // Minimum Refresh Recovery time most-significant byte -#define SPD_MIN_TWTR 26 // Minimum Internal Write to Read command delay -#define SPD_MIN_TRTP 27 // Minimum Internal Read to Precharge command delay -#define SPD_UN_TFAW 28 // Upper Nibble for tFAW -#define SPD_MIN_TFAW 29 // Minimum Four Activate Window Delay Time (tFAWmin) -#define SPD_OD_SUP 30 // SDRAM Output Drivers Supported -#define SPD_RFSH_OPT 31 // SDRAM Refresh Options - #define ETR BIT0 // Bit location for Extended Temp Range - #define ETRR BIT1 // Bit location for Extended Temp Refresh Rate - #define ASR BIT2 // Bit location for Automatic Self Refresh - #define ODTS BIT3 // Bit location for On-die Thermal Sensor -#define SPD_DIMM_TS 32 // Module Temperature Sensor -#define SPD_SDRAM_TYPE 33 // SDRAM device type -#define SPD_FTB_TCK 34 // Fine Offset for SDRAM tCK -#define SPD_FTB_TAA 35 // Fine Offset for SDRAM tAA -#define SPD_FTB_TRCD 36 // Fine Offset for SDRAM tRCD -#define SPD_FTB_TRP 37 // Fine Offset for SDRAM tRP -#define SPD_FTB_TRC 38 // Fine Offset for SDRAM tRC -#define SPD_OPT_FEAT 41 // SDRAM Optional Features - #define SPD_PTRR BIT7 // Indicates if the DIMM is pTRR compliant - - // UDIMM specific bytes - // Applicable when Module Type (key byte 3) = 2, 3, 4, 6, or 8 - -#define SPD_ADDR_MAP_FECTD 63 // Address Mapping from Edge Connector to DRAM - - // RDIMM specific bytes - // Applicable when Module Type (key byte 3) = 1, 5, or 9 - -#define SPD_RDIMM_ATTR 63 // RDIMM module attributes -#define SPD_DIMM_HS 64 // Module Heat Spreader Solution -#define SPD_REG_VEN_LSB 65 // Register Vendor ID LSB -#define SPD_REG_VEN_MSB 66 // Register Vendor ID MSB -#define SPD_REG_REV 67 // Register Revision -#define SPD_CNTL_0 69 // Register Control Word 0 & 1 -#define SPD_CNTL_1 70 // Register Control Word 2 & 3 -#define SPD_CNTL_2 71 // Register Control Word 4 & 5 -#define SPD_CNTL_3 72 // Register Control Word 6 & 7 (reserved) -#define SPD_CNTL_4 73 // Register Control Word 8 & 9 (reserved) -#define SPD_CNTL_5 74 // Register Control Word 10 & 11 (reserved) -#define SPD_CNTL_6 75 // Register Control Word 12 & 13 (reserved) -#define SPD_CNTL_7 76 // Register Control Word 14 & 15 (reserved) - - // LRDIMM specific bytes - // Applicable when Module Type (key byte 3) = 0xB - // Based on DDR3 SPD 1.0 Document Release 2.1 draft, dated May 27, 2011 - -#define SPD_LRDIMM_ATTR 63 // LRDIMM module attributes -#define SPD_LRBUF_REV 64 // LR Buffer Revision -#define SPD_LRBUF_VEN_LSB 65 // LR Buffer Vendor ID LSB -#define SPD_LRBUF_VEN_MSB 66 // LR Buffer Vendor ID MSB -#define SPD_LR_F0_RC2_3 67 // LR Buffer Function 0, Control Word 2 & 3 -#define SPD_LR_F0_RC4_5 68 // LR Buffer Function 0, Control Word 4 & 5 -#define SPD_LR_F1_RC8_11 69 // LR Buffer Function 1, Control Word 8 & 11 -#define SPD_LR_F1_RC12_13 70 // LR Buffer Function 1, Control Word 12 & 13 -#define SPD_LR_F1_RC14_15 71 // LR Buffer Function 1, Control Word 14 & 15 - - // Speed bin 0 = 800 & 1066 -#define SPD_LR_SB0_MDQ_DS_ODT 72 // LR Buffer Function 3, Control Word 8 & 9 -#define SPD_LR_SB0_DR01_QODT_ACT 73 // LR Buffer Function 3 & 4, Control Word 10 & 11 -#define SPD_LR_SB0_DR23_QODT_ACT 74 // LR Buffer Function 5 & 6, Control Word 10 & 11 -#define SPD_LR_SB0_DR45_QODT_ACT 75 // LR Buffer Function 7 & 8, Control Word 10 & 11 -#define SPD_LR_SB0_DR67_QODT_ACT 76 // LR Buffer Function 9 & 10, Control Word 10 & 11 -#define SPD_LR_SB0_MR1_2_RTT 77 // LR Buffer SMBus offsets 0xC0 - 0xC7 - - // Speed bin 1 = 1333 & 1600 -#define SPD_LR_SB1_MDQ_DS_ODT 78 // LR Buffer Function 3, Control Word 8 & 9 -#define SPD_LR_SB1_DR01_QODT_ACT 79 // LR Buffer Function 3 & 4, Control Word 10 & 11 -#define SPD_LR_SB1_DR23_QODT_ACT 80 // LR Buffer Function 5 & 6, Control Word 10 & 11 -#define SPD_LR_SB1_DR45_QODT_ACT 81 // LR Buffer Function 7 & 8, Control Word 10 & 11 -#define SPD_LR_SB1_DR67_QODT_ACT 82 // LR Buffer Function 9 & 10, Control Word 10 & 11 -#define SPD_LR_SB1_MR1_2_RTT 83 // LR Buffer SMBus offsets 0xC0 - 0xC7 - - // Speed bin 2 = 1866 & 2133 -#define SPD_LR_SB2_MDQ_DS_ODT 84 // LR Buffer Function 3, Control Word 8 & 9 -#define SPD_LR_SB2_DR01_QODT_ACT 85 // LR Buffer Function 3 & 4, Control Word 10 & 11 -#define SPD_LR_SB2_DR23_QODT_ACT 86 // LR Buffer Function 5 & 6, Control Word 10 & 11 -#define SPD_LR_SB2_DR45_QODT_ACT 87 // LR Buffer Function 7 & 8, Control Word 10 & 11 -#define SPD_LR_SB2_DR67_QODT_ACT 88 // LR Buffer Function 9 & 10, Control Word 10 & 11 -#define SPD_LR_SB2_MR1_2_RTT 89 // LR Buffer SMBus offsets 0xC0 - 0xC7 - -#define SPD_LR_150_MIN_MOD_DELAY 90 // LR DIMM minimum DQ Read propagation delay at 1.5V -#define SPD_LR_150_MAX_MOD_DELAY 91 // LR DIMM maximum DQ Read propagation delay at 1.5V -#define SPD_LR_135_MIN_MOD_DELAY 92 // LR DIMM minimum DQ Read propagation delay at 1.35V -#define SPD_LR_135_MAX_MOD_DELAY 93 // LR DIMM maximum DQ Read propagation delay at 1.35V -#define SPD_LR_12x_MIN_MOD_DELAY 94 // LR DIMM minimum DQ Read propagation delay at 1.2xV -#define SPD_LR_12x_MAX_MOD_DELAY 95 // LR DIMM maximum DQ Read propagation delay at 1.2xV - -#define SPD_LR_PERS_BYTE_0 102 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_1 103 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_2 104 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_3 105 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_4 106 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_5 107 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_6 108 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_7 109 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_8 110 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_9 111 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_10 112 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_11 113 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_12 114 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_13 115 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTE_14 116 // LR DIMM Personality Byte -#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes - - // End module specific section - -#define SPD_MMID_LSB 117 // Module Manufacturer ID Code, Least Significant Byte -#define SPD_MMID_MSB 118 // Module Manufacturer ID Code, Mostst Significant Byte -#define SPD_MM_LOC 119 // Module Manufacturing Location -#define SPD_MM_DATE 120 // Module Manufacturing Date 120-121 -#define SPD_MODULE_SN 122 // Module Serial Number 122-125 -#define SPD_CRC_LSB 126 // LSB of 16-bit CRC -#define SPD_CRC_MSB 127 // MSB of 16-bit CRC - -#define SPD_MODULE_PN 128 // Module Part Number 128-145 -#define SPD_MODULE_RC 146 // Module Revision Code 146-147 -#define SPD_DRAM_MIDC_LSB 148 // DRAM Manufacturer ID Code, Least Significant Byte -#define SPD_DRAM_MIDC_MSB 149 // DRAM Manufacturer ID Code, Most Significant Byte -#ifdef MEM_NVDIMM_EN -#define SPD_NVDIMM_ID_N 174 // If NVDIMM value will be 'N' -#define SPD_NVDIMM_ID_V 175 // If NVDIMM value will be 'V' -#endif //MEM_NVDIMM_EN -#define SPD_BYTE_200 200 // Fixed value 0xBE - - // - // DDR4 Specific Bytes - // -#define SPD_SDRAM_TYPE_DDR4 6 // SDRAM Device Type (DDR4) -#define SPD_OPT_FEAT_DDR4 7 // SDRAM Optional Features (DDR4) - #define SPD_MAC_MASK BIT0 | BIT1 | BIT2 // Mask for Maximum Active Count field - #define SPD_TRR_IMMUNE BIT3 // Indicates this DIMM does not require DRAM Maintenance -#define SPD_RFSH_OPT_DDR4 8 // SDRAM Refresh Options (DDR4) -#define SPD_VDD_DDR4 11 // Vdd DIMM supports (DDR4) - #define SPD_VDD_120 3 // Module operable and endurant 1.20V -#define SPD_MODULE_ORG_DDR4 12 // Number of Ranks and SDRAM device width (DDR4) -#define SPD_MEM_BUS_WID_DDR4 13 // Width of SDRAM memory bus -#define SPD_DIMM_TS_DDR4 14 // Module Thermal Sensor -#define SPD_TB_DDR4 17 // Timebase [3:2] MTB, [1:0] FTB -#define SPD_MIN_TCK_DDR4 18 // Minimum cycle time - #define SPD_TCKMIN_DDR4_1600 10 // tCK(MTB)=10, tCK(ns)=1.25 - #define SPD_TCKMIN_DDR4_1866 9 // tCK(MTB)=9, tCK(ns)=1.071 - #define SPD_TCKMIN_DDR4_2133 8 // tCK(MTB)=8, tCK(ns)=.938 - #define SPD_TCKMIN_DDR4_2400 7 // tCK(MTB)=7, tCK(ns)=.833 -#define SPD_MAX_TCK_DDR4 19 // Maximum cycle time -#define SPD_CAS_LT_SUP_1_DDR4 20 // CAS Latencies Supported, first byte -#define SPD_CAS_LT_SUP_2_DDR4 21 // CAS Latencies Supported, second byte -#define SPD_CAS_LT_SUP_3_DDR4 22 // CAS Latencies Supported, third byte -#define SPD_CAS_LT_SUP_4_DDR4 23 // CAS Latencies Supported, fourth byte -#define SPD_MIN_TAA_DDR4 24 // Minimum CAS Latency Time (tAAmin) -#define SPD_MIN_TRCD_DDR4 25 // Minimum RAS to CAS delay -#define SPD_MIN_TRP_DDR4 26 // Minimum Row Precharge time -#define SPD_EXT_TRC_TRAS_DDR4 27 // Upper nibbles for min tRAS and tRC -#define SPD_MIN_TRAS_DDR4 28 // Minimum Active to Precharge time -#define SPD_MIN_TRC_DDR4 29 // Minimum Active to Active/Refresh time -#define SPD_MIN_TRFC1_LSB_DDR4 30 // Minimum Refresh Recovery time least-significant byte -#define SPD_MIN_TRFC1_MSB_DDR4 31 // Minimum Refresh Recovery time most-significant byte -#define SPD_MIN_TRFC2_LSB_DDR4 32 // Minimum Refresh Recovery time least-significant byte -#define SPD_MIN_TRFC2_MSB_DDR4 33 // Minimum Refresh Recovery time most-significant byte -#define SPD_MIN_TRFC3_LSB_DDR4 34 // Minimum Refresh Recovery time least-significant byte -#define SPD_MIN_TRFC3_MSB_DDR4 35 // Minimum Refresh Recovery time most-significant byte -#define SPD_TFAW_UPPER_DDR4 36 // Upper nibble for tFAW -#define SPD_MIN_TFAW_DDR4 37 // Minimum For Active Window Delay Time (tFAW) -#define SPD_MIN_TRRDS_DDR4 38 // Minimum Active to Active Delay Time tRRD_S Different Bank Group -#define SPD_MIN_TRRDL_DDR4 39 // Minimum Active to Active Delay Time tRRD_L Same Bank Group -#define SPD_MIN_TCCDL_DDR4 40 // Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group -#define SPD_FTB_TCCDL_DDR4 117 // Fine offset for tCCD_L -#define SPD_FTB_TRRDL_DDR4 118 // Fine offset for tRRD_L -#define SPD_FTB_TRRDS_DDR4 119 // Fine offset for tRRD_S -#define SPD_FTB_TRC_DDR4 120 // Fine offset for TRC -#define SPD_FTB_TRP_DDR4 121 // Fine offset for TRP -#define SPD_FTB_TRCD_DDR4 122 // Fine offset for TRCD -#define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA -#define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK -#define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK -#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM -#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM - -#define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte -#define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte -#define SPD_MM_LOC_DDR4 322 // Module Manufacturing Location -#define SPD_MM_DATE_DDR4 323 // Module Manufacturing Date 323-324 -#define SPD_MODULE_SN_DDR4 325 // Module Serial Number 325-328 -#define SPD_MODULE_PN_DDR4 329 // Module Part Number 329-348 -#define SPD_MODULE_RC_DDR4 349 // Module Revision Code -#define SPD_DRAM_MIDC_LSB_DDR4 350 // DRAM Manufacturer ID Code, Least Significant Byte -#define SPD_DRAM_MIDC_MSB_DDR4 351 // DRAM Manufacturer ID Code, Most Significant Byte -#define SPD_DRAM_REV_DDR4 352 // DRAM Revision ID -#define SPD_CRC_LSB_DDR4 382 // LSB of 16-bit CRC -#define SPD_CRC_MSB_DDR4 383 // MSB of 16-bit CRC - - // Begin DDR4 module specific section -#define SPD_MODULE_NH_DDR4 128 // Module Nominal Height -#define SPD_MODULE_MT_DDR4 129 // Module Maximum Thickness -#define SPD_REF_RAW_CARD_DDR4 130 // Reference Raw Card Used - - // UDIMM specific bytes - // Applicable when Module Type (key byte 3) = 2 -#define SPD_ADDR_MAP_FECTD_DDR4 131 // Address Mapping from Edge Connector to DRAM - - // RDIMM specific bytes - // Applicable when Module Type (key byte 3) = 1 -#define SPD_RDIMM_ATTR_DDR4 131 // RDIMM module attributes -#define SPD_DIMM_HS_DDR4 132 // Module Heat Spreader Solution -#define SPD_REG_VEN_LSB_DDR4 133 // Register Vendor ID LSB -#define SPD_REG_VEN_MSB_DDR4 134 // Register Vendor ID MSB -#define SPD_REG_REV_DDR4 135 // Register Revision -#define SPD_ADD_MAPPING_DDR4 136 // Address mapping from Reg to DRAM -#define SPD_REG_OD_CTL_DDR4 137 // Register Output Drive Strength for Control -#define SPD_REG_OD_CK_DDR4 138 // Register Output Drive Strength for Clock - - // LRDIMM specific bytes - // Applicable when Module Type (key byte 3) = 0x4 -#define SPD_LRDIMM_ATTR_DDR4 131 // LRDIMM module attributes -#define SPD_LRBUF_HS_DDR4 132 // LR Buffer Heat Spreader Solution -#define SPD_LRBUF_VEN_LSB_DDR4 133 // LR Buffer Vendor ID LSB -#define SPD_LRBUF_VEN_MSB_DDR4 134 // LR Buffer Vendor ID MSB -#define SPD_LRBUF_REV_DDR4 135 // LR Buffer Register Revision -#define SPD_LRBUF_DB_REV_DDR4 139 // LR Buffer Data Buffer Revision -#define SPD_LRBUF_DRAM_VREFDQ_R0_DDR4 140 // LR Buffer DRAM VrefDQ for Package Rank 0 -#define SPD_LRBUF_DRAM_VREFDQ_R1_DDR4 141 // LR Buffer DRAM VrefDQ for Package Rank 1 -#define SPD_LRBUF_DRAM_VREFDQ_R2_DDR4 142 // LR Buffer DRAM VrefDQ for Package Rank 2 -#define SPD_LRBUF_DRAM_VREFDQ_R3_DDR4 143 // LR Buffer DRAM VrefDQ for Package Rank 3 -#define SPD_LRBUF_DB_VREFDQ_DDR4 144 // LR Data Buffer VrefDQ for DRAM Interface -#define SPD_LRBUF_DB_DS_RTT_LE1866_DDR4 145 // LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866 -#define SPD_LRBUF_DB_DS_RTT_GT1866_LE2400_DDR4 146 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400 -#define SPD_LRBUF_DB_DS_RTT_GT2400_LE3200_DDR4 147 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200 -#define SPD_LRBUF_DRAM_DS_DDR4 148 // LR Buffer DRAM Drive Strength (for data rates <= 1866, 1866 < data rate <= 2400, and 2400 < data rate <= 3200) -#define SPD_LRBUF_DRAM_ODT_WR_NOM_LE1866_DDR4 149 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866 -#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT1866_LE2400_DDR4 150 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400 -#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT2400_LE3200_DDR4 151 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200 -#define SPD_LRBUF_DRAM_ODT_PARK_LE1866_DDR4 152 // LR Buffer DRAM ODT (RTT_PARK) for data rate <= 1866 -#define SPD_LRBUF_DRAM_ODT_PARK_GT1866_LE2400_DDR4 153 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 1866 and <= 2400 -#define SPD_LRBUF_DRAM_ODT_PARK_GT2400_LE3200_DDR4 154 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 2400 and <= 3200 - - // - // End DDR4 Specific Bytes - // -#define BANK0 0 -#define BANK1 BIT0 -#define BANK2 BIT1 -#define BANK3 BIT0 + BIT1 -#define BANK4 BIT2 -#define BANK5 BIT2 + BIT0 -#define BANK6 BIT2 + BIT1 -#define BANK7 BIT2 + BIT1 + BIT0 - -#define RDIMM_RC00 0x00 -#define RDIMM_RC01 0x01 -#define RDIMM_RC02 0x02 -#define RDIMM_RC03 0x03 -#define RDIMM_RC04 0x04 -#define RDIMM_RC05 0x05 -#define RDIMM_RC08 0x08 -#define RDIMM_RC09 0x09 -#define RDIMM_RC0A 0x0A -#define RDIMM_RC0B 0x0B -#define RDIMM_RC0C 0x0C -#define RDIMM_RC0D 0x0D -#define RDIMM_RC0E 0x0E -#define RDIMM_RC0F 0x0F -#define RDIMM_RC1x 0x10 -#define RDIMM_RC2x 0x20 -#define RDIMM_RC3x 0x30 -#define RDIMM_RC4x 0x40 -#define RDIMM_RC5x 0x50 -#define RDIMM_RC6x 0x60 -#define RDIMM_RC7x 0x70 -#define RDIMM_RC8x 0x80 -#define RDIMM_RC9x 0x90 -#define RDIMM_RCAx 0xA0 - -#define LRDIMM_BC00 0x00 -#define LRDIMM_BC01 0x01 -#define LRDIMM_BC02 0x02 -#define LRDIMM_BC03 0x03 -#define LRDIMM_BC04 0x04 -#define LRDIMM_BC05 0x05 -#define LRDIMM_BC06 0x06 -#define LRDIMM_BC07 0x07 -#define LRDIMM_BC08 0x08 -#define LRDIMM_BC09 0x09 -#define LRDIMM_BC0A 0x0A -#define LRDIMM_BC0B 0x0B -#define LRDIMM_BC0C 0x0C -#define LRDIMM_BC0E 0x0E - -#define LRDIMM_BC0x 0x00 -#define LRDIMM_BC1x 0x10 -#define LRDIMM_BC2x 0x20 -#define LRDIMM_BC3x 0x30 -#define LRDIMM_BC4x 0x40 -#define LRDIMM_BC5x 0x50 -#define LRDIMM_BC6x 0x60 -#define LRDIMM_BC7x 0x70 -#define LRDIMM_BC8x 0x80 -#define LRDIMM_BC9x 0x90 -#define LRDIMM_BCAx 0xA0 -#define LRDIMM_BCBx 0xB0 -#define LRDIMM_BCCx 0xC0 -#define LRDIMM_BCDx 0xD0 -#define LRDIMM_BCEx 0xE0 -#define LRDIMM_BCFx 0xF0 -#define LRDIMM_F0 0x0 -#define LRDIMM_F1 0x1 -#define LRDIMM_F5 0x5 -#define LRDIMM_F6 0x6 -#define LRDIMM_F7 0x7 -#define LRDIMM_F8 0x8 -#define LRDIMM_F9 0x9 - -#endif /* _HW_MEM_INIT_LIB_H_ */ diff --git a/Silicon/Hisilicon/Include/Library/I2CLib.h b/Silicon/Hisilicon/Include/Library/I2CLib.h deleted file mode 100644 index fc8b818e8dcc5896c3a33abbf95fd904d62ed808..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/I2CLib.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _I2C_LIB_H_ -#define _I2C_LIB_H_ - -//I2C0 or I2C1 -typedef enum { - DEVICE_TYPE_SPD = 0, - DEVICE_TYPE_E2PROM, - DEVICE_TYPE_CPLD_3BYTE_OPERANDS, - DEVICE_TYPE_CPLD_4BYTE_OPERANDS -}I2C_DEVICE_TYPE; - - -typedef enum { - Normal = 0, - Fast, - SPEED_MODE_MAX -}SPEED_MODE; - - -#define I2C_PORT_MAX 10 - - - -typedef struct { - UINT32 Socket; - UINT32 Port; - I2C_DEVICE_TYPE DeviceType; - UINT32 SlaveDeviceAddress; -}I2C_DEVICE; - - -UINTN -EFIAPI -I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode); - -EFI_STATUS -EFIAPI -I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf); - -EFI_STATUS -EFIAPI -I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf); - -EFI_STATUS -EFIAPI -I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf); - -EFI_STATUS -EFIAPI -I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf); - -EFI_STATUS -EFIAPI -I2CSdaConfig(UINT32 Socket, UINT32 Port); - - -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h deleted file mode 100644 index 1af44f92afdcf6cf7da7616b6a1d39943286ea5c..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ /dev/null @@ -1,78 +0,0 @@ -/** @file -* -* Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _OEM_CONFIG_DATA_H_ -#define _OEM_CONFIG_DATA_H_ - -#define PCIE_MAX_TOTAL_PORTS 16 -#define OEM_CONFIG_NAME L"OemConfig" -#define PLATFORM_SETUP_VARIABLE_FLAG (EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE) - -#pragma pack(1) -typedef struct { - /*Memory Config*/ - UINT8 DdrDebugLevel; - UINT8 DdrFreqLimit; - UINT8 DdrRefreshSupport; - UINT8 DdrRefreshRate; - UINT8 RankMargin; - UINT8 RankMarginMode; - UINT32 rmtPatternLength; - UINT8 perbitmargin; - UINT8 CaMargin; - UINT8 CaVrefMarginOption; - UINT8 NumaEn; - UINT8 HwMemTest; - UINT8 DieInterleaving; - UINT8 ChannelInterleaving; - UINT8 RankInterleaving; - UINT8 EccSupport; - /*iBMC Config*/ - UINT8 BmcWdtEnable; - UINT8 BmcWdtTimeout; - UINT8 BmcWdtAction; - UINT8 OSWdtEnable; - UINT8 OSWdtTimeout; - UINT8 OSWdtAction; - /*PCIe Config*/ - UINT8 PcieSRIOVSupport; - UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieLinkStatusPort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieLinkSpeedRateStatusPort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieLinkMaxPort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieMaxPayloadSizePort[PCIE_MAX_TOTAL_PORTS]; - UINT8 PcieAspmPort[PCIE_MAX_TOTAL_PORTS]; - /*Misc Config*/ - UINT8 EnableSmmu; - UINT8 EnableFdtTable; - UINT8 EnableGOP; - /*RAS Config*/ - UINT8 EnRasSupport; - UINT8 EnPoison; - UINT8 CheckAlgorithm; - UINT8 PatrolScrub; - UINT8 PatrolScrubDuration; - UINT8 DemandScrubMode; - UINT8 CorrectErrorThreshold; - UINT8 AdvanceDeviceCorrection; - UINT8 RankSparing; - UINT8 FunnelPeriod; - UINT8 DpcFeature; - UINT8 EcrcFeature; - UINT8 CompletionTimeout; - UINT8 CompletionTimeoutValue; - UINT8 HotPlug; - -} OEM_CONFIG_DATA; -#pragma pack() - -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemDevicePath.h b/Silicon/Hisilicon/Include/Library/OemDevicePath.h deleted file mode 100644 index 164dfafc43b4bcc29cdc7697d862cc50c60f3d58..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/OemDevicePath.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @file -* -* Copyright (c) 2015 - 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015 - 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _OEM_DEVICE_PATH_H_ -#define _OEM_DEVICE_PATH_H_ -#include - -typedef enum -{ - C_NIC = 1, - C_SATA = 2, - C_SAS = 3, - C_USB = 4, -} CONTROLLER_TYPE; - -typedef struct{ - VENDOR_DEVICE_PATH Vender; - UINT8 ControllerType; - UINT8 Socket; - UINT8 Port; -} EXT_VENDOR_DEVICE_PATH; - -typedef struct{ - UINT16 BootIndex; - UINT16 Port; -} SATADES; - -typedef struct{ - UINT16 BootIndex; - UINT16 ParentPortNumber; - UINT16 InterfaceNumber; -} USBDES; - -typedef struct{ - UINT16 BootIndex; - UINT16 Port; -} PXEDES; - -#endif - diff --git a/Silicon/Hisilicon/Include/Library/OemNicLib.h b/Silicon/Hisilicon/Include/Library/OemNicLib.h deleted file mode 100644 index e26154313ca1e8d6ebd7e05c35a0cb9e732873f4..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/OemNicLib.h +++ /dev/null @@ -1,51 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _OEM_NIC_LIB_H_ -#define _OEM_NIC_LIB_H_ - -#define ETH_MAX_PORT 8 -#define ETH_DEBUG_PORT0 6 -#define ETH_DEBUG_PORT1 7 - -#define ETH_SPEED_10M 6 -#define ETH_SPEED_100M 7 -#define ETH_SPEED_1000M 8 -#define ETH_SPEED_10KM 9 -#define ETH_HALF_DUPLEX 0 -#define ETH_FULL_DUPLEX 1 - -#define ETH_GDD_ID 0x001378e0 -#define ETH_PHY_BCM5241_ID 0x0143bc30 -#define ETH_PHY_MVL88E1145_ID 0x01410cd0 -#define ETH_PHY_MVL88E1119_ID 0x01410e80 -#define ETH_PHY_MVL88E1512_ID 0x01410dd0 -#define ETH_PHY_MVL88E1543_ID 0x01410ea0 -#define ETH_PHY_NLP3142_ID 0x00000412 - -#define ETH_INVALID 0xffffffff - -typedef struct { - UINT32 Valid; - UINT32 Speed; - UINT32 Duplex; - UINT32 PhyId; - UINT32 PhyAddr; -} ETH_PRODUCT_DESC; - -BOOLEAN OemIsInitEth (UINT32 Port); -UINT32 OemEthFindFirstSP (); -ETH_PRODUCT_DESC *OemEthInit (UINT32 port); -UINT32 GetCpu1FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type); -UINT32 GetCpu2FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type, UINT8 *Fiber100Ge); -EFI_STATUS EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); -EFI_STATUS EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemSetVirtualMapDesc.h b/Silicon/Hisilicon/Include/Library/OemSetVirtualMapDesc.h deleted file mode 100644 index 399a8f9927f49df32e5084d51018cd68d4076f06..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/OemSetVirtualMapDesc.h +++ /dev/null @@ -1,20 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _OEM_SET_VIRTUAL_MAP_DESC_H_ -#define _OEM_SET_VIRTUAL_MAP_DESC_H_ - - -UINTN OemSetVirtualMapDesc ( - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable, - ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes - ); - -#endif - diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h deleted file mode 100644 index 764818c7852815af1559d512bf8c2a66d71e4ce5..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h +++ /dev/null @@ -1,202 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _PLATFORM_PCI_LIB_H_ -#define _PLATFORM_PCI_LIB_H_ - -#define PCIE_MAX_HOSTBRIDGE 2 -#define PCIE_MAX_ROOTBRIDGE 8 -//The extern pcie addresses will be initialized by oemmisclib -extern UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; -extern UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; -extern UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; -extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; - - -#define PCI_HB0RB0_PCI_BASE FixedPcdGet64(PciHb0Rb0Base) -#define PCI_HB0RB1_PCI_BASE FixedPcdGet64(PciHb0Rb1Base) -#define PCI_HB0RB2_PCI_BASE FixedPcdGet64(PciHb0Rb2Base) -#define PCI_HB0RB3_PCI_BASE FixedPcdGet64(PciHb0Rb3Base) -#define PCI_HB0RB4_PCI_BASE FixedPcdGet64(PciHb0Rb4Base) -#define PCI_HB0RB5_PCI_BASE FixedPcdGet64(PciHb0Rb5Base) -#define PCI_HB0RB6_PCI_BASE FixedPcdGet64(PciHb0Rb6Base) -#define PCI_HB0RB7_PCI_BASE FixedPcdGet64(PciHb0Rb7Base) - -#define PCI_HB1RB0_PCI_BASE FixedPcdGet64(PciHb1Rb0Base) -#define PCI_HB1RB1_PCI_BASE FixedPcdGet64(PciHb1Rb1Base) -#define PCI_HB1RB2_PCI_BASE FixedPcdGet64(PciHb1Rb2Base) -#define PCI_HB1RB3_PCI_BASE FixedPcdGet64(PciHb1Rb3Base) -#define PCI_HB1RB4_PCI_BASE FixedPcdGet64(PciHb1Rb4Base) -#define PCI_HB1RB5_PCI_BASE FixedPcdGet64(PciHb1Rb5Base) -#define PCI_HB1RB6_PCI_BASE FixedPcdGet64(PciHb1Rb6Base) -#define PCI_HB1RB7_PCI_BASE FixedPcdGet64(PciHb1Rb7Base) - -#define PCI_HB0RB0_ECAM_BASE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB0_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize) -#define PCI_HB0RB1_ECAM_BASE FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB1_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceSize) -#define PCI_HB0RB2_ECAM_BASE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB2_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize) -#define PCI_HB0RB3_ECAM_BASE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB3_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize) -#define PCI_HB0RB4_ECAM_BASE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB4_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize) -#define PCI_HB0RB5_ECAM_BASE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB5_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize) -#define PCI_HB0RB6_ECAM_BASE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB6_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize) -#define PCI_HB0RB7_ECAM_BASE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress) -#define PCI_HB0RB7_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize) - -#define PCI_HB1RB0_ECAM_BASE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB0_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize) -#define PCI_HB1RB1_ECAM_BASE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB1_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize) -#define PCI_HB1RB2_ECAM_BASE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB2_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize) -#define PCI_HB1RB3_ECAM_BASE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB3_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize) -#define PCI_HB1RB4_ECAM_BASE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB4_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize) -#define PCI_HB1RB5_ECAM_BASE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB5_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize) -#define PCI_HB1RB6_ECAM_BASE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB6_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize) -#define PCI_HB1RB7_ECAM_BASE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress) -#define PCI_HB1RB7_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize) - -#define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress)) -#define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize)) -#define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress)) -#define PCI_HB0RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb1PciRegionSize)) -#define PCI_HB0RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb2PciRegionBaseAddress)) -#define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize)) -#define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress)) -#define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize)) -#define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress)) -#define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize)) -#define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress)) -#define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize)) -#define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress)) -#define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize)) -#define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress)) -#define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize)) - -#define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress)) -#define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize)) -#define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress)) -#define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize)) -#define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress)) -#define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize)) -#define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress)) -#define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize)) -#define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress)) -#define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize)) -#define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress)) -#define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize)) -#define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress)) -#define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize)) -#define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress)) -#define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize)) - - -#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase)) -#define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase)) -#define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase)) -#define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase)) -#define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase)) -#define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase)) -#define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase)) -#define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase)) - -#define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase)) -#define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase)) -#define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase)) -#define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase)) -#define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase)) -#define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase)) -#define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase)) -#define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase)) - - -#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase)) -#define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase)) -#define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase)) -#define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase)) -#define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase)) -#define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase)) -#define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase)) -#define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase)) - -#define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase)) -#define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase)) -#define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase)) -#define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase)) -#define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase)) -#define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase)) -#define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase)) -#define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase)) - - - -#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase)) -#define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase)) -#define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase)) -#define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase)) -#define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase)) -#define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase)) -#define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase)) -#define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase)) - -#define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase)) -#define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase)) -#define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase)) -#define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase)) -#define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase)) -#define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase)) -#define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase)) -#define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase)) - -#define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize)) -#define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize)) -#define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize)) -#define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize)) -#define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize)) -#define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize)) -#define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize)) -#define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize)) - -#define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize)) -#define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize)) -#define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize)) -#define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize)) -#define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize)) -#define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize)) -#define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize)) -#define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize)) - - - -typedef struct { - UINT32 Segment; - UINT64 Ecam; - UINT64 BusBase; - UINT64 BusLimit; - UINT64 IoBase; - UINT64 IoLimit; - UINT64 CpuMemRegionBase; - UINT64 CpuIoRegionBase; - UINT64 RbPciBar; - UINT64 PciRegionBase; - UINT64 PciRegionLimit; -} PCI_ROOT_BRIDGE_RESOURCE_APPETURE; - -extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; -#endif - diff --git a/Silicon/Hisilicon/Include/Library/RtcHelperLib.h b/Silicon/Hisilicon/Include/Library/RtcHelperLib.h deleted file mode 100644 index 39dbc969f7f93fe9e0d80ddd49175c856065f425..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Library/RtcHelperLib.h +++ /dev/null @@ -1,29 +0,0 @@ -/** @file - - Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef RTC_HELPER_LIB_H__ -#define RTC_HELPER_LIB_H__ - -// The delay is need for cpld and I2C. This is a empirical value. MemoryFence is no need. -#define RTC_DELAY_30_MS 30000 -// The delay is need for cpld and I2C. This is a empirical value. MemoryFence is no need. -#define RTC_DELAY_1000_MICROSECOND 1000 -// The delay is need for cpld and I2C. This is a empirical value. MemoryFence is no need. -#define RTC_DELAY_2_MICROSECOND 2 - -EFI_STATUS -SwitchRtcI2cChannelAndLock ( - VOID - ); - -VOID -ReleaseOwnershipOfRtc ( - VOID - ); - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h b/Silicon/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h deleted file mode 100644 index 5a1ffece810668513e3ada02b0b39b7a21a635d9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _HISI_BOARD_NIC_PROTOCOL_H_ -#define _HISI_BOARD_NIC_PROTOCOL_H_ - -#define HISI_BOARD_NIC_PROTOCOL_GUID \ - { 0xb5903955, 0x31e9, 0x4aaf, { 0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66 } } - -#define HISI_BOARD_XGE_STATUS_PROTOCOL_GUID \ - { 0xa6b8ed0e, 0xd8cc, 0x4853, { 0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97 } } - -typedef -EFI_STATUS -(EFIAPI *HISI_BOARD_NIC_GET_MAC_ADDRESS) ( - IN OUT EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ); - -typedef -EFI_STATUS -(EFIAPI *HISI_BOARD_NIC_SET_MAC_ADDRESS) ( - IN EFI_MAC_ADDRESS *Mac, - IN UINTN Port - ); - -typedef struct { - HISI_BOARD_NIC_GET_MAC_ADDRESS GetMac; - HISI_BOARD_NIC_SET_MAC_ADDRESS SetMac; -} HISI_BOARD_NIC_PROTOCOL; - -typedef -VOID -(*HISI_BOARD_FEEDBACK_XGE_STATUS) ( - BOOLEAN IsLinkup, - BOOLEAN IsActOK, - UINT32 port - ); - -typedef struct { - HISI_BOARD_FEEDBACK_XGE_STATUS FeedbackXgeStatus; -} HISI_BOARD_XGE_STATUS_PROTOCOL; - - -extern EFI_GUID gHisiBoardNicProtocolGuid; -extern EFI_GUID gHisiBoardXgeStatusProtocolGuid; - - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h b/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h deleted file mode 100644 index fbbb84aa8d1918147d4eb42bea506a19b7a9d3ce..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h +++ /dev/null @@ -1,24 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _HISI_PLATFORM_SAS_PROTOCOL_H_ -#define _HISI_PLATFORM_SAS_PROTOCOL_H_ - -typedef struct _HISI_PLATFORM_SAS_PROTOCOL HISI_PLATFORM_SAS_PROTOCOL; - -struct _HISI_PLATFORM_SAS_PROTOCOL { - UINT32 ControllerId; - BOOLEAN Enable; - UINT64 BaseAddr; - UINT64 ResetAddr; -}; - -extern EFI_GUID gHisiPlatformSasProtocolGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/HisiSasConfig.h b/Silicon/Hisilicon/Include/Protocol/HisiSasConfig.h deleted file mode 100644 index 21b5b5c7716ac557579b3c891121d13b2a385a68..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/HisiSasConfig.h +++ /dev/null @@ -1,43 +0,0 @@ -/** @file - - Copyright (c) 2020, Hisilicon Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef HISI_SAS_CONFIG_H_ -#define HISI_SAS_CONFIG_H_ - -typedef struct{ - UINT32 CtrlId; - BOOLEAN Enable; - UINT32 Bar32; - UINT64 ResetBase; - UINTN Segment; - UINTN Bus; - UINTN Device; - UINTN Fun; -} SAS_CONTROLLER_DATA; - -typedef -VOID * -(EFIAPI *HISI_SAS_GET_CONTROLLER_DATA) ( - VOID - ); - -typedef -EFI_STATUS -(EFIAPI *HISI_SAS_GET_ADDRESS) ( - IN UINT8 Index, - IN OUT UINT8 *SasAddrBuffer - ); - -typedef struct { - HISI_SAS_GET_ADDRESS GetAddr; - HISI_SAS_GET_CONTROLLER_DATA GetControllerData; -} HISI_SAS_CONFIG_PROTOCOL; - -extern EFI_GUID gHisiSasConfigProtocolGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h b/Silicon/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h deleted file mode 100644 index 2b430f04c418f7950882249efc3fa1a66d4bf68a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _HISI_SPI_FLASH_PROTOCOL_H_ -#define _HISI_SPI_FLASH_PROTOCOL_H_ - -typedef struct _HISI_SPI_FLASH_PROTOCOL HISI_SPI_FLASH_PROTOCOL; - -typedef -EFI_STATUS -(EFIAPI *HISI_SPI_FLASH_ERASE_INTERFACE) ( - IN HISI_SPI_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT32 ulLength - ); - -typedef -EFI_STATUS -(EFIAPI *HISI_SPI_FLASH_WRITE_INTERFACE) ( - IN HISI_SPI_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT8 *Buffer, - IN UINT32 ulLength - ); - -typedef -EFI_STATUS -(EFIAPI *HISI_SPI_FLASH_READ_INTERFACE) ( - IN HISI_SPI_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN OUT UINT8 *Buffer, - IN UINT32 ulLength - ); - -typedef -EFI_STATUS -(EFIAPI *HISI_SPI_FLASH_ERASE_WRITE_INTERFACE) ( - IN HISI_SPI_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT8 *Buffer, - IN UINT32 ulLength - ); - -struct _HISI_SPI_FLASH_PROTOCOL { - HISI_SPI_FLASH_ERASE_INTERFACE Erase; - HISI_SPI_FLASH_WRITE_INTERFACE Write; - HISI_SPI_FLASH_READ_INTERFACE Read; - HISI_SPI_FLASH_ERASE_WRITE_INTERFACE EraseWrite; -}; - -extern EFI_GUID gHisiSpiFlashProtocolGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h b/Silicon/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h deleted file mode 100644 index bb0ca4a088822495c738768fd6c316e05057554d..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h +++ /dev/null @@ -1,93 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _IPMI_INTERFACE_PROTOCOL_H_ -#define _IPMI_INTERFACE_PROTOCOL_H_ - -#define IPMI_INTERFACE_PROTOCOL_GUID \ - {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}} - -typedef struct _IPMI_INTERFACE_PROTOCOL IPMI_INTERFACE_PROTOCOL; - -// -// Structure to store IPMI Network Function, LUN and command -// -typedef struct { - UINT8 Lun : 2; - UINT8 NetFn : 6; - UINT8 Cmd; -} IPMI_CMD_HEADER; - -// -// System Interface Type -// -typedef enum { - IPMI_SYSTEM_INTERFACE_UNKNOWN, - IPMI_SYSTEM_INTERFACE_KCS, - IPMI_SYSTEM_INTERFACE_SMIC, - IPMI_SYSTEM_INTERFACE_BT, - IPMI_SYSTEM_INTERFACE_SSIF, - IPMI_SYSTEM_INTERFACE_MAX_TYPE -} IPMI_SYSTEM_INTERFACE_TYPE; - -// -// System Interface Address Type -// -typedef enum { - IPMI_MEMORY, - IPMI_IO, - IPMI_MAX_INTERFACE_ADDRESS_TYPE -} IPMI_INTERFACE_ADDRESS_TYPE; - -typedef -EFI_STATUS -(EFIAPI *IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD) ( - IN IPMI_INTERFACE_PROTOCOL *This, - IN IPMI_CMD_HEADER Request, - IN VOID *SendData OPTIONAL, - IN UINT8 SendLength, - OUT VOID *RecvData, - OUT UINT8 *RecvLength, - OUT UINT16 *StatusCodes OPTIONAL -); -typedef -IPMI_SYSTEM_INTERFACE_TYPE -(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE) ( - IN IPMI_INTERFACE_PROTOCOL *This -); -typedef -UINT16 -(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS) ( - IN IPMI_INTERFACE_PROTOCOL *This -); -typedef -IPMI_INTERFACE_ADDRESS_TYPE -(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE) ( - IN IPMI_INTERFACE_PROTOCOL *This -); -typedef -UINT8 -(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION) ( - IN IPMI_INTERFACE_PROTOCOL *This -); - -// -// Structure of IPMI_INTERFACE_PROTOCOL -// -struct _IPMI_INTERFACE_PROTOCOL{ - IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD ExecuteIpmiCmd; - IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE GetIpmiInterfaceType; - IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS GetIpmiBaseAddress; - IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE GetIpmiBaseAddressType; - IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION GetIpmiVersion; -} ; - -extern EFI_GUID gIpmiInterfaceProtocolGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/NorFlashProtocol.h b/Silicon/Hisilicon/Include/Protocol/NorFlashProtocol.h deleted file mode 100644 index 034212746644437f0e56bdaf5d8f84cdc41d3b74..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/NorFlashProtocol.h +++ /dev/null @@ -1,53 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#ifndef _NOR_FLASH_PROTOCOL_H_ -#define _NOR_FLASH_PROTOCOL_H_ - -#define UNI_NOR_FLASH_PROTOCOL_GUID \ - {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}} - -typedef struct _UNI_NOR_FLASH_PROTOCOL UNI_NOR_FLASH_PROTOCOL; - -typedef -EFI_STATUS -(EFIAPI *UNI_FLASH_ERASE_INTERFACE) ( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT32 Length - ); -typedef -EFI_STATUS -(EFIAPI *UNI_FLASH_WRITE_INTERFACE) ( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN UINT8 *Buffer, - UINT32 ulLength - ); - -typedef -EFI_STATUS -(EFIAPI *UNI_FLASH_READ_INTERFACE) ( - IN UNI_NOR_FLASH_PROTOCOL *This, - IN UINT32 Offset, - IN OUT UINT8 *Buffer, - IN UINT32 ulLen - ); - - -struct _UNI_NOR_FLASH_PROTOCOL { - UNI_FLASH_ERASE_INTERFACE Erase; - UNI_FLASH_WRITE_INTERFACE Write; - UNI_FLASH_READ_INTERFACE Read; -}; - -extern EFI_GUID gUniNorFlashProtocolGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h b/Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h deleted file mode 100644 index 54d25b5fbc6ed4f53a1ab5e83cac10e4cdf83513..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _PLATFORM_SAS_PROTOCOL_H_ -#define _PLATFORM_SAS_PROTOCOL_H_ - -#define PLATFORM_SAS_PROTOCOL_GUID \ - { \ - 0x40e9829f, 0x3a2c, 0x479a, 0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d \ - } - -typedef struct _PLATFORM_SAS_PROTOCOL PLATFORM_SAS_PROTOCOL; - -typedef -VOID -(EFIAPI * SAS_INIT) ( - IN PLATFORM_SAS_PROTOCOL *This -); - -struct _PLATFORM_SAS_PROTOCOL { - IN UINT64 BaseAddr; - SAS_INIT Init; -}; - -#endif diff --git a/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h b/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h deleted file mode 100644 index f8686f8ef886dbfd08c179dabcda1dcbe5db60f0..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _SNP_PLATFORM_PROTOCOL_H_ -#define _SNP_PLATFORM_PROTOCOL_H_ -#define HISI_SNP_PLATFORM_PROTOCOL_GUID \ - { \ - 0x81321f27, 0xff58, 0x4a1d, 0x99, 0x97, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0x6f \ - } - -typedef struct _HISI_PLATFORM_SNP_PROTOCOL HISI_PLATFORM_SNP_PROTOCOL; - -struct _HISI_PLATFORM_SNP_PROTOCOL { - UINT32 ControllerId; - UINT32 Enable; -}; - -extern EFI_GUID gHisiSnpPlatformProtocolGuid; - -#endif diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h deleted file mode 100644 index 9385393379639096b41458c6a5cff738172cbfa4..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ /dev/null @@ -1,16538 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef __PCIE_REG_OFFSET__ -#define __PCIE_REG_OFFSET__ - - - - -#define PCIE_EEP_PCI_CFG_HDR0_REG (0x0) -#define PCIE_EEP_PCI_CFG_HDR1_REG (0x4) -#define PCIE_EEP_PCI_CFG_HDR2_REG (0x8) -#define PCIE_EEP_PCI_CFG_HDR3_REG (0xC) -#define PCIE_EEP_PCI_CFG_HDR4_REG (0x10) -#define PCIE_EEP_PCI_CFG_HDR5_REG (0x14) -#define PCIE_EEP_PCI_CFG_HDR6_REG (0x18) -#define PCIE_EEP_PCI_CFG_HDR7_REG (0x1C) -#define PCIE_EEP_PCI_CFG_HDR8_REG (0x20) -#define PCIE_EEP_PCI_CFG_HDR9_REG (0x24) -#define PCIE_EEP_PCI_CFG_HDR10_REG (0x28) -#define PCIE_EEP_PCI_CFG_HDR11_REG (0x2C) -#define PCIE_EEP_PCI_CFG_HDR12_REG (0x30) -#define PCIE_EEP_PCI_CFG_HDR13_REG (0x34) -#define PCIE_EEP_PCI_CFG_HDR14_REG (0x38) -#define PCIE_EEP_PCI_CFG_HDR15_REG (0x3C) -#define PCIE_EEP_PCI_PM_CAP0_REG (0x40) -#define PCIE_EEP_PCI_PM_CAP1_REG (0x44) -#define PCIE_EEP_PCI_MSI_CAP0_REG (0x50) -#define PCIE_EEP_PCI_MSI_CAP1_REG (0x54) -#define PCIE_EEP_PCI_MSI_CAP2_REG (0x58) -#define PCIE_EEP_PCI_MSI_CAP3_REG (0x5C) -#define PCIE_EEP_PCIE_CAP0_REG (0x70) -#define PCIE_EEP_PCIE_CAP1_REG (0x74) -#define PCIE_EEP_PCIE_CAP2_REG (0x78) -#define PCIE_EEP_PCIE_CAP3_REG (0x7C) -#define PCIE_EEP_PCIE_CAP4_REG (0x80) -#define PCIE_EEP_PCIE_CAP5_REG (0x84) -#define PCIE_EEP_PCIE_CAP6_REG (0x88) -#define PCIE_EEP_PCIE_CAP7_REG (0x8C) -#define PCIE_EEP_PCIE_CAP8_REG (0x90) -#define PCIE_EEP_PCIE_CAP9_REG (0x94) -#define PCIE_EEP_PCIE_CAP10_REG (0x98) -#define PCIE_EEP_PCIE_CAP11_REG (0x9C) -#define PCIE_EEP_PCIE_CAP12_REG (0xA0) -#define PCIE_EEP_SLOT_CAP_REG (0xC0) -#define PCIE_EEP_AER_CAP0_REG (0x100) -#define PCIE_EEP_AER_CAP1_REG (0x104) -#define PCIE_EEP_AER_CAP2_REG (0x108) -#define PCIE_EEP_AER_CAP3_REG (0x10C) -#define PCIE_EEP_AER_CAP4_REG (0x110) -#define PCIE_EEP_AER_CAP5_REG (0x114) -#define PCIE_EEP_AER_CAP6_REG (0x118) -#define PCIE_EEP_AER_CAP7_REG (0x11C) -#define PCIE_EEP_AER_CAP8_REG (0x120) -#define PCIE_EEP_AER_CAP9_REG (0x124) -#define PCIE_EEP_AER_CAP10_REG (0x128) -#define PCIE_EEP_AER_CAP11_REG (0x12C) -#define PCIE_EEP_AER_CAP12_REG (0x130) -#define PCIE_EEP_AER_CAP13_REG (0x134) -#define PCIE_EEP_VC_CAP0_REG (0x140) -#define PCIE_EEP_VC_CAP1_REG (0x144) -#define PCIE_EEP_VC_CAP2_REG (0x148) -#define PCIE_EEP_VC_CAP3_REG (0x14C) -#define PCIE_EEP_VC_CAP4_REG (0x150) -#define PCIE_EEP_VC_CAP5_REG (0x154) -#define PCIE_EEP_VC_CAP6_REG (0x158) -#define PCIE_EEP_VC_CAP7_REG (0x15C) -#define PCIE_EEP_VC_CAP8_REG (0x160) -#define PCIE_EEP_VC_CAP9_REG (0x164) -#define PCIE_EEP_PORT_LOGIC0_REG (0x700) -#define PCIE_EEP_PORT_LOGIC1_REG (0x704) -#define PCIE_EEP_PORT_LOGIC2_REG (0x708) -#define PCIE_EEP_PORT_LOGIC3_REG (0x70C) -#define PCIE_EEP_PORT_LOGIC4_REG (0x710) -#define PCIE_EEP_PORT_LOGIC5_REG (0x714) -#define PCIE_EEP_PORT_LOGIC6_REG (0x718) -#define PCIE_EEP_PORT_LOGIC7_REG (0x71C) -#define PCIE_EEP_PORT_LOGIC8_REG (0x720) -#define PCIE_EEP_PORT_LOGIC9_REG (0x724) -#define PCIE_EEP_PORT_LOGIC10_REG (0x728) -#define PCIE_EEP_PORT_LOGIC11_REG (0x72C) -#define PCIE_EEP_PORT_LOGIC12_REG (0x730) -#define PCIE_EEP_PORT_LOGIC13_REG (0x734) -#define PCIE_EEP_PORT_LOGIC14_REG (0x738) -#define PCIE_EEP_PORT_LOGIC15_REG (0x73C) -#define PCIE_EEP_PORT_LOGIC16_REG (0x748) -#define PCIE_EEP_PORT_LOGIC17_REG (0x74C) -#define PCIE_EEP_PORT_LOGIC18_REG (0x750) -#define PCIE_EEP_PORT_LOGIC19_REG (0x7A8) -#define PCIE_EEP_PORT_LOGIC20_REG (0x7AC) -#define PCIE_EEP_PORT_LOGIC21_REG (0x7B0) -#define PCIE_EEP_PORT_LOGIC22_REG (0x80C) -#define PCIE_EEP_PORTLOGIC23_REG (0x810) -#define PCIE_EEP_PORTLOGIC24_REG (0x814) -#define PCIE_EEP_PORTLOGIC25_REG (0x818) -#define PCIE_EEP_PORTLOGIC26_REG (0x81C) -#define PCIE_EEP_PORTLOGIC27_REG (0x820) -#define PCIE_EEP_PORTLOGIC28_REG (0x824) -#define PCIE_EEP_PORTLOGIC29_REG (0x828) -#define PCIE_EEP_PORTLOGIC30_REG (0x82C) -#define PCIE_EEP_PORTLOGIC31_REG (0x830) -#define PCIE_EEP_PORTLOGIC32_REG (0x834) -#define PCIE_EEP_PORTLOGIC33_REG (0x838) -#define PCIE_EEP_PORTLOGIC34_REG (0x83C) -#define PCIE_EEP_PORTLOGIC35_REG (0x840) -#define PCIE_EEP_PORTLOGIC36_REG (0x844) -#define PCIE_EEP_PORTLOGIC37_REG (0x848) -#define PCIE_EEP_PORTLOGIC38_REG (0x84C) -#define PCIE_EEP_PORTLOGIC39_REG (0x850) -#define PCIE_EEP_PORTLOGIC40_REG (0x854) -#define PCIE_EEP_PORTLOGIC41_REG (0x858) -#define PCIE_EEP_PORTLOGIC42_REG (0x85C) -#define PCIE_EEP_PORTLOGIC43_REG (0x860) -#define PCIE_EEP_PORTLOGIC44_REG (0x864) -#define PCIE_EEP_PORTLOGIC45_REG (0x868) -#define PCIE_EEP_PORTLOGIC46_REG (0x86C) -#define PCIE_EEP_PORTLOGIC47_REG (0x870) -#define PCIE_EEP_PORTLOGIC48_REG (0x874) -#define PCIE_EEP_PORTLOGIC49_REG (0x878) -#define PCIE_EEP_PORTLOGIC50_REG (0x87C) -#define PCIE_EEP_PORTLOGIC51_REG (0x880) -#define PCIE_EEP_PORTLOGIC52_REG (0x884) -#define PCIE_EEP_PORTLOGIC53_REG (0x888) -#define PCIE_EEP_GEN3_CONTRL_REG (0x890) -#define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) -#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC) -#define PCIE_EEP_PORTLOGIC54_REG (0x900) -#define PCIE_EEP_PORTLOGIC55_REG (0x904) -#define PCIE_EEP_PORTLOGIC56_REG (0x908) -#define PCIE_EEP_PORTLOGIC57_REG (0x90C) -#define PCIE_EEP_PORTLOGIC58_REG (0x910) -#define PCIE_EEP_PORTLOGIC59_REG (0x914) -#define PCIE_EEP_PORTLOGIC60_REG (0x918) -#define PCIE_EEP_PORTLOGIC61_REG (0x91C) -#define PCIE_EEP_PORTLOGIC62_REG (0x97C) -#define PCIE_EEP_PORTLOGIC63_REG (0x980) -#define PCIE_EEP_PORTLOGIC64_REG (0x99C) -#define PCIE_EEP_PORTLOGIC65_REG (0x9A0) -#define PCIE_EEP_PORTLOGIC66_REG (0x9BC) -#define PCIE_EEP_PORTLOGIC67_REG (0x9C4) -#define PCIE_EEP_PORTLOGIC68_REG (0x9C8) -#define PCIE_EEP_PORTLOGIC69_REG (0x9CC) -#define PCIE_EEP_PORTLOGIC70_REG (0x9D0) -#define PCIE_EEP_PORTLOGIC71_REG (0x9D4) -#define PCIE_EEP_PORTLOGIC72_REG (0x9D8) -#define PCIE_EEP_PORTLOGIC73_REG (0x9DC) -#define PCIE_EEP_PORTLOGIC74_REG (0x9E0) -#define PCIE_EEP_PORTLOGIC75_REG (0xA00) -#define PCIE_EEP_PORTLOGIC76_REG (0xA10) -#define PCIE_EEP_PORTLOGIC77_REG (0xA18) -#define PCIE_EEP_PORTLOGIC78_REG (0xA1C) -#define PCIE_EEP_PORTLOGIC79_REG (0xA24) -#define PCIE_EEP_PORTLOGIC80_REG (0xA28) -#define PCIE_EEP_PORTLOGIC81_REG (0xA34) -#define PCIE_EEP_PORTLOGIC82_REG (0xA3C) -#define PCIE_EEP_PORTLOGIC83_REG (0xA40) -#define PCIE_EEP_PORTLOGIC84_REG (0xA44) -#define PCIE_EEP_PORTLOGIC85_REG (0xA48) -#define PCIE_EEP_PORTLOGIC86_REG (0xA6C) -#define PCIE_EEP_PORTLOGIC87_REG (0xA70) -#define PCIE_EEP_PORTLOGIC88_REG (0xA78) -#define PCIE_EEP_PORTLOGIC89_REG (0xA7C) -#define PCIE_EEP_PORTLOGIC90_REG (0xA80) -#define PCIE_EEP_PORTLOGIC91_REG (0xA84) -#define PCIE_EEP_PORTLOGIC92_REG (0xA88) -#define PCIE_EEP_PORTLOGIC93_REG (0xA8C) -#define PCIE_EEP_PORTLOGIC94_REG (0xA90) - -//pcie iatu internal registers define -#define IATU_OFFSET 0x700 -#define IATU_VIEW_POINT 0x200 -#define IATU_REGION_CTRL1 0x204 -#define IATU_REGION_CTRL2 0x208 -#define IATU_REGION_BASE_LOW 0x20C -#define IATU_REGION_BASE_HIGH 0x210 -#define IATU_REGION_BASE_LIMIT 0x214 -#define IATU_REGION_TARGET_LOW 0x218 -#define IATU_REGION_TARGET_HIGH 0x21C -#define IATU_SHIIF_MODE 0x90000000 -#define IATU_NORMAL_MODE 0x80000000 -#define IATU_CTRL1_TYPE_CONFIG0 0x4 -#define IATU_CTRL1_TYPE_CONFIG1 0x5 -#define IATU_CTRL1_TYPE_MEM 0 -#define IATU_CTRL1_TYPE_IO 2 - - -typedef union tagPipeLoopBack -{ - struct - { - UINT32 reserved : 31 ; - UINT32 pipe_loopback_enable : 1 ; - }Bits; - UINT32 UInt32; -}PCIE_PIPE_LOOPBACK_U; - -typedef union tagEepPciCfgHdr0 -{ - - struct - { - UINT32 vendor_id : 16 ; - UINT32 device_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR0_U; - - - -typedef union tagEepPciCfgHdr1 -{ - - struct - { - UINT32 io_space_enable : 1 ; - UINT32 memory_space_enable : 1 ; - UINT32 bus_master_enable : 1 ; - UINT32 specialcycleenable : 1 ; - UINT32 memory_write_and_invalidate : 1 ; - UINT32 vga_palette_snoop_enable : 1 ; - UINT32 parity_error_response : 1 ; - UINT32 idsel_stepping_waitcycle_control : 1 ; - UINT32 serr_enable : 1 ; - UINT32 fastback_to_backenable : 1 ; - UINT32 interrupt_disable : 1 ; - UINT32 Reserved_2 : 5 ; - UINT32 Reserved_1 : 3 ; - UINT32 intx_status : 1 ; - UINT32 capabilitieslist : 1 ; - UINT32 pcibus66mhzcapable : 1 ; - UINT32 Reserved_0 : 1 ; - UINT32 fastback_to_back : 1 ; - UINT32 masterdataparityerror : 1 ; - UINT32 devsel_timing : 2 ; - UINT32 signaled_target_abort : 1 ; - UINT32 received_target_abort : 1 ; - UINT32 received_master_abort : 1 ; - UINT32 signaled_system_error : 1 ; - UINT32 detected_parity_error : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR1_U; - -typedef union tagEepPciCfgHdr2 -{ - - struct - { - UINT32 revision_identification : 8 ; - UINT32 Reserved_3 : 8 ; - UINT32 sub_class : 8 ; - UINT32 baseclass : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR2_U; - - - -typedef union tagEepPciCfgHdr3 -{ - - struct - { - UINT32 cache_line_size : 8 ; - UINT32 mstr_lat_tmr : 8 ; - UINT32 multi_function_device : 7 ; - UINT32 hdr_type : 1 ; - UINT32 bist : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR3_U; - - - -typedef union tagEepPciCfgHdr4 -{ - - struct - { - UINT32 sbar01_space_inicator : 1 ; - UINT32 sbar01_type : 2 ; - UINT32 sbar01_prefetchable : 1 ; - UINT32 sbar01_lower : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR4_U; - - - -typedef union tagEepPciCfgHdr6 -{ - - struct - { - UINT32 sbar23_space_inicator : 1 ; - UINT32 sbar23_type : 2 ; - UINT32 sbar23_prefetchable : 1 ; - UINT32 Reserved_4 : 8 ; - UINT32 sbar23_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR6_U; - - - -typedef union tagEepPciCfgHdr8 -{ - - struct - { - UINT32 sbar45_space_inicator : 1 ; - UINT32 sbar45_type : 2 ; - UINT32 sbar45_prefetchable : 1 ; - UINT32 Reserved_5 : 8 ; - UINT32 sbar45_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR8_U; - - - -typedef union tagEepPciCfgHdr11 -{ - - struct - { - UINT32 subsystem_vendor_id : 16 ; - UINT32 subsystemid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR11_U; - - - -typedef union tagEepPciCfgHdr13 -{ - - struct - { - UINT32 capptr : 8 ; - UINT32 Reserved_6 : 24 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR13_U; - - - -typedef union tagEepPciCfgHdr15 -{ - - struct - { - UINT32 int_line : 8 ; - UINT32 int_pin : 8 ; - UINT32 Min_Grant : 8 ; - UINT32 Max_Latency : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_CFG_HDR15_U; - - - -typedef union tagEepPciMsiCap0 -{ - - struct - { - UINT32 msi_cap_id : 8 ; - UINT32 next_capability_pointer : 8 ; - UINT32 msi_enabled : 1 ; - UINT32 multiple_message_capable : 3 ; - UINT32 multiple_message_enabled : 3 ; - UINT32 msi_64_en : 1 ; - UINT32 pvm_en : 1 ; - UINT32 message_control_register : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_MSI_CAP0_U; - - - -typedef union tagEepPciMsiCap1 -{ - - struct - { - UINT32 Reserved_11 : 2 ; - UINT32 msi_addr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_MSI_CAP1_U; - - - -typedef union tagEepPciMsiCap3 -{ - - struct - { - UINT32 msi_data : 16 ; - UINT32 Reserved_12 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCI_MSI_CAP3_U; - - - -typedef union tagEepPcieCap0 -{ - - struct - { - UINT32 pcie_cap_id : 8 ; - UINT32 pcie_next_ptr : 8 ; - UINT32 pcie_capability_version : 4 ; - UINT32 device_port_type : 4 ; - UINT32 slot_implemented : 1 ; - UINT32 interrupt_message_number : 5 ; - UINT32 Reserved_13 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP0_U; - - - -typedef union tagEepPcieCap1 -{ - - struct - { - UINT32 max_payload_size_supported : 3 ; - UINT32 phantom_function_supported : 2 ; - UINT32 extended_tagEepfield_supported : 1 ; - UINT32 endpoint_l0sacceptable_latency : 3 ; - UINT32 endpoint_l1acceptable_latency : 3 ; - UINT32 undefined : 3 ; - UINT32 Reserved_16 : 3 ; - UINT32 captured_slot_power_limit_value : 8 ; - UINT32 captured_slot_power_limit_scale : 2 ; - UINT32 function_level_reset : 1 ; - UINT32 Reserved_15 : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP1_U; - - - -typedef union tagEepPcieCap2 -{ - - struct - { - UINT32 correctable_error_reporting_enable : 1 ; - UINT32 non_fatal_error_reporting_enable : 1 ; - UINT32 fatal_error_reporting_enable : 1 ; - UINT32 urenable : 1 ; - UINT32 enable_relaxed_ordering : 1 ; - UINT32 max_payload_size : 3 ; - UINT32 extended_tagEepfieldenable : 1 ; - UINT32 phantom_function_enable : 1 ; - UINT32 auxpowerpmenable : 1 ; - UINT32 enablenosnoop : 1 ; - UINT32 max_read_request_size : 3 ; - UINT32 Reserved_18 : 1 ; - UINT32 correctableerrordetected : 1 ; - UINT32 non_fatalerrordetected : 1 ; - UINT32 fatalerrordetected : 1 ; - UINT32 unsupportedrequestdetected : 1 ; - UINT32 auxpowerdetected : 1 ; - UINT32 transactionpending : 1 ; - UINT32 Reserved_17 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP2_U; - - - -typedef union tagEepPcieCap3 -{ - - struct - { - UINT32 max_link_speed : 4 ; - UINT32 max_link_width : 6 ; - UINT32 active_state_power_management : 2 ; - UINT32 l0s_exitlatency : 3 ; - UINT32 l1_exit_latency : 3 ; - UINT32 clock_power_management : 1 ; - UINT32 surprise_down_error_report_cap : 1 ; - UINT32 data_link_layer_active_report_cap : 1 ; - UINT32 link_bandwidth_noti_cap : 1 ; - UINT32 aspm_option_compliance : 1 ; - UINT32 Reserved_19 : 1 ; - UINT32 port_number : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP3_U; - - - - -typedef union tagEepPcieCap4 -{ - - struct - { - UINT32 active_state_power_management : 2 ; - UINT32 Reserved_22 : 1 ; - UINT32 rcb : 1 ; - UINT32 link_disable : 1 ; - UINT32 retrain_link : 1 ; - UINT32 common_clock_config : 1 ; - UINT32 extended_sync : 1 ; - UINT32 enable_clock_pwr_management : 1 ; - UINT32 hw_auto_width_disable : 1 ; - UINT32 link_bandwidth_management_int_en : 1 ; - UINT32 link_auto_bandwidth_int_en : 1 ; - UINT32 Reserved_21 : 4 ; - UINT32 current_link_speed : 4 ; - UINT32 negotiated_link_width : 6 ; - UINT32 Reserved_20 : 1 ; - UINT32 link_training : 1 ; - UINT32 slot_clock_configration : 1 ; - UINT32 data_link_layer_active : 1 ; - UINT32 link_bandwidth_management_status : 1 ; - UINT32 link_auto_bandwidth_status : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP4_U; - - - - -typedef union tagEepPcieCap5 -{ - - struct - { - UINT32 attentioonbuttonpresent : 1 ; - UINT32 powercontrollerpresent : 1 ; - UINT32 mrlsensorpresent : 1 ; - UINT32 attentionindicatorpresent : 1 ; - UINT32 powerindicatorpresent : 1 ; - UINT32 hot_plugsurprise : 1 ; - UINT32 hot_plugcapable : 1 ; - UINT32 slotpowerlimitvalue : 8 ; - UINT32 slotpowerlimitscale : 2 ; - UINT32 electromechanicalinterlockpresen : 1 ; - UINT32 no_cmd_complete_support : 1 ; - UINT32 phy_slot_number : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP5_U; - - - - -typedef union tagEepPcieCap6 -{ - - struct - { - UINT32 attentionbuttonpressedenable : 1 ; - UINT32 powerfaultdetectedenable : 1 ; - UINT32 mrlsensorchangedenable : 1 ; - UINT32 presencedetectchangedenable : 1 ; - UINT32 commandcompletedinterruptenable : 1 ; - UINT32 hot_pluginterruptenable : 1 ; - UINT32 attentionindicatorcontrol : 2 ; - UINT32 powerindicatorcontrol : 2 ; - UINT32 powercontrollercontrol : 1 ; - UINT32 electromechanicalinterlockcontrol : 1 ; - UINT32 datalinklayerstatechangedenable : 1 ; - UINT32 Reserved_23 : 3 ; - UINT32 attentionbuttonpressed : 1 ; - UINT32 powerfaultdetected : 1 ; - UINT32 mrlsensorchanged : 1 ; - UINT32 presencedetectchanged : 1 ; - UINT32 commandcompleted : 1 ; - UINT32 mrlsensorstate : 1 ; - UINT32 presencedetectstate : 1 ; - UINT32 electromechanicalinterlockstatus : 1 ; - UINT32 datalinklayerstatechanged : 1 ; - UINT32 slot_ctrl_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP6_U; - - - - -typedef union tagEepPcieCap7 -{ - - struct - { - UINT32 systemerroroncorrectableerrorenable : 1 ; - UINT32 systemerroronnon_fatalerrorenable : 1 ; - UINT32 systemerroronfatalerrorenable : 1 ; - UINT32 pmeinterruptenable : 1 ; - UINT32 crssoftwarevisibilityenable : 1 ; - UINT32 Reserved_24 : 11 ; - UINT32 crssoftwarevisibility : 1 ; - UINT32 root_cap : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP7_U; - - - - -typedef union tagEepPcieCap8 -{ - - struct - { - UINT32 pmerequesterid : 16 ; - UINT32 pmestatus : 1 ; - UINT32 pmepending : 1 ; - UINT32 root_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP8_U; - - - - -typedef union tagEepPcieCap9 -{ - - struct - { - UINT32 completiontimeoutrangessupported : 4 ; - UINT32 completiontimeoutdisablesupported : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoproutingsupported : 1 ; - UINT32 _2_bitatomicopcompletersupported : 1 ; - UINT32 _4_bitatomicopcompletersupported : 1 ; - UINT32 _28_bitcascompletersupported : 1 ; - UINT32 noro_enabledpr_prpassing : 1 ; - UINT32 Reserved_25 : 1 ; - UINT32 tphcompletersupported : 2 ; - UINT32 dev_cap2 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP9_U; - - - - -typedef union tagEepPcieCap10 -{ - - struct - { - UINT32 completiontimeoutvalue : 4 ; - UINT32 completiontimeoutdisable : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoprequesterenable : 1 ; - UINT32 atomicopegressblocking : 1 ; - UINT32 idorequestenable : 1 ; - UINT32 idocompletionenable : 1 ; - UINT32 dev_ctrl2 : 22 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP10_U; - - - - -typedef union tagEepPcieCap11 -{ - - struct - { - UINT32 Reserved_27 : 1 ; - UINT32 gen1_suport : 1 ; - UINT32 gen2_suport : 1 ; - UINT32 gen3_suport : 1 ; - UINT32 Reserved_26 : 4 ; - UINT32 crosslink_supported : 1 ; - UINT32 link_cap2 : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP11_U; - - - - -typedef union tagEepPcieCap12 -{ - - struct - { - UINT32 targetlinkspeed : 4 ; - UINT32 entercompliance : 1 ; - UINT32 hardwareautonomousspeeddisa : 1 ; - UINT32 selectablede_empha : 1 ; - UINT32 transmitmargin : 3 ; - UINT32 _entermodifiedcompliance : 1 ; - UINT32 compliancesos : 1 ; - UINT32 de_emphasislevel : 4 ; - UINT32 currentde_emphasislevel : 1 ; - UINT32 equalizationcomplete : 1 ; - UINT32 equalizationphase1successful : 1 ; - UINT32 equalizationphase2successful : 1 ; - UINT32 equalizationphase3successful : 1 ; - UINT32 linkequalizationrequest : 1 ; - UINT32 link_ctrl2_status2 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PCIE_CAP12_U; - - - - -typedef union tagEepSlotCap -{ - - struct - { - UINT32 slotnumberingcapabilitiesid : 8 ; - UINT32 nextcapabilitypointer : 8 ; - UINT32 add_incardslotsprovided : 5 ; - UINT32 firstinchassis : 1 ; - UINT32 Reserved_28 : 2 ; - UINT32 slot_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_SLOT_CAP_U; - - - - -typedef union tagEepAerCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 aer_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP0_U; - - - - -typedef union tagEepAerCap1 -{ - - struct - { - UINT32 Reserved_34 : 1 ; - UINT32 Reserved_33 : 3 ; - UINT32 datalinkprotocolerrorsta : 1 ; - UINT32 surprisedownerrorstatus : 1 ; - UINT32 Reserved_32 : 6 ; - UINT32 poisonedtlpstatu : 1 ; - UINT32 flowcontrolprotocolerrorst : 1 ; - UINT32 completiontimeouts : 1 ; - UINT32 completerabortstatus : 1 ; - UINT32 receiveroverflowstatus : 1 ; - UINT32 malformedtlpstatus : 1 ; - UINT32 ecrcerrorstatus : 1 ; - UINT32 ecrcerrorstat : 1 ; - UINT32 unsupportedrequesterrorstatus : 1 ; - UINT32 Reserved_31 : 3 ; - UINT32 atomicopegressblockedstatus : 1 ; - UINT32 uncorr_err_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP1_U; - - - - -typedef union tagEepAerCap2 -{ - - struct - { - UINT32 Reserved_38 : 1 ; - UINT32 Reserved_37 : 3 ; - UINT32 datalinkprotocolerrormask : 1 ; - UINT32 surprisedownerrormask : 1 ; - UINT32 Reserved_36 : 6 ; - UINT32 poisonedtlpmask : 1 ; - UINT32 flowcontrolprotocolerrormask : 1 ; - UINT32 completiontimeoutmask : 1 ; - UINT32 completerabortmask : 1 ; - UINT32 unexpectedcompletionmask : 1 ; - UINT32 receiveroverflowmask : 1 ; - UINT32 malformedtlpmask : 1 ; - UINT32 ecrcerrormask : 1 ; - UINT32 unsupportedrequesterrormask : 1 ; - UINT32 Reserved_35 : 3 ; - UINT32 atomicopegressblockedmask : 1 ; - UINT32 uncorr_err_mask : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP2_U; - - - - -typedef union tagEepAerCap3 -{ - - struct - { - UINT32 Reserved_42 : 1 ; - UINT32 Reserved_41 : 3 ; - UINT32 datalinkprotocolerrorsever : 1 ; - UINT32 surprisedownerrorseverity : 1 ; - UINT32 Reserved_40 : 6 ; - UINT32 poisonedtlpseverity : 1 ; - UINT32 flowcontrolprotocolerrorseveri : 1 ; - UINT32 completiontimeoutseverity : 1 ; - UINT32 completerabortseverity : 1 ; - UINT32 unexpectedcompletionseverity : 1 ; - UINT32 receiveroverflowseverity : 1 ; - UINT32 malformedtlpseverity : 1 ; - UINT32 ecrcerrorseverity : 1 ; - UINT32 unsupportedrequesterrorseverity : 1 ; - UINT32 Reserved_39 : 3 ; - UINT32 atomicopegressblockedseverity : 1 ; - UINT32 uncorr_err_ser : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP3_U; - - - - -typedef union tagEepAerCap4 -{ - - struct - { - UINT32 receivererrorstatus : 1 ; - UINT32 Reserved_44 : 5 ; - UINT32 badtlpstatus : 1 ; - UINT32 baddllpstatus : 1 ; - UINT32 replay_numrolloverstatus : 1 ; - UINT32 Reserved_43 : 3 ; - UINT32 replytimertimeoutstatus : 1 ; - UINT32 advisorynon_fatalerrorstatus : 1 ; - UINT32 corr_err_status : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP4_U; - - - - -typedef union tagEepAerCap5 -{ - - struct - { - UINT32 receivererrormask : 1 ; - UINT32 Reserved_46 : 5 ; - UINT32 badtlpmask : 1 ; - UINT32 baddllpmask : 1 ; - UINT32 replay_numrollovermask : 1 ; - UINT32 Reserved_45 : 3 ; - UINT32 replytimertimeoutmask : 1 ; - UINT32 advisorynon_fatalerrormask : 1 ; - UINT32 corr_err_mask : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP5_U; - - - - -typedef union tagEepAerCap6 -{ - - struct - { - UINT32 firsterrorpointer : 5 ; - UINT32 ecrcgenerationcapability : 1 ; - UINT32 ecrcgenerationenable : 1 ; - UINT32 ecrccheckcapable : 1 ; - UINT32 ecrccheckenable : 1 ; - UINT32 adv_cap_ctrl : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP6_U; - -typedef union tagGen3Ctrol -{ - struct - { - UINT32 reserved : 16 ; - UINT32 equalization_disable : 1 ; - UINT32 reserved2 : 15 ; - }Bits; - UINT32 UInt32; -}PCIE_GRN3_CONTRL; - - - - -typedef union tagEepAerCap11 -{ - - struct - { - UINT32 correctableerrorreportingenable : 1 ; - UINT32 non_fatalerrorreportingenable : 1 ; - UINT32 fatalerrorreportingenable : 1 ; - UINT32 root_err_cmd : 29 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP11_U; - - - - -typedef union tagEepAerCap12 -{ - - struct - { - UINT32 err_correceived : 1 ; - UINT32 multipleerr_correceived : 1 ; - UINT32 err_fatal_nonfatalreceived : 1 ; - UINT32 multipleerr_fatal_nonfatalreceived : 1 ; - UINT32 firstuncorrectablefatal : 1 ; - UINT32 non_fatalerrormessagesreceived : 1 ; - UINT32 fatalerrormessagesreceived : 1 ; - UINT32 Reserved_47 : 20 ; - UINT32 root_err_status : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP12_U; - - - - -typedef union tagEepAerCap13 -{ - - struct - { - UINT32 err_corsourceidentification : 16 ; - UINT32 err_src_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_AER_CAP13_U; - - - - -typedef union tagEepVcCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 vc_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP0_U; - - - - -typedef union tagEepVcCap1 -{ - - struct - { - UINT32 extendedvccount : 3 ; - UINT32 Reserved_50 : 1 ; - UINT32 lowpriorityextendedvccount : 3 ; - UINT32 Reserved_49 : 1 ; - UINT32 referenceclock : 2 ; - UINT32 portarbitrationtableentrysize : 2 ; - UINT32 vc_cap1 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP1_U; - - - - -typedef union tagEepVcCap2 -{ - - struct - { - UINT32 vcarbitrationcapability : 8 ; - UINT32 Reserved_51 : 16 ; - UINT32 vc_cap2 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP2_U; - - - - -typedef union tagEepVcCap3 -{ - - struct - { - UINT32 loadvcarbitrationtable : 1 ; - UINT32 vcarbitrationselect : 3 ; - UINT32 Reserved_53 : 12 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 Reserved_52 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP3_U; - - - - -typedef union tagEepVcCap4 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_56 : 6 ; - UINT32 Reserved_55 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_54 : 1 ; - UINT32 vc_res_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP4_U; - - - - -typedef union tagEepVcCap5 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_59 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselec : 3 ; - UINT32 Reserved_58 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_57 : 4 ; - UINT32 vc_res_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP5_U; - - - - -typedef union tagEepVcCap6 -{ - - struct - { - UINT32 Reserved_60 : 16 ; - UINT32 portarbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP6_U; - - - - -typedef union tagEepVcCap7 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_63 : 6 ; - UINT32 Reserved_62 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_61 : 1 ; - UINT32 vc_res_cap0 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP7_U; - - - - -typedef union tagEepVcCap8 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_66 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselect : 3 ; - UINT32 Reserved_65 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_64 : 4 ; - UINT32 vc_res_ctrl0 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP8_U; - - - - -typedef union tagEepVcCap9 -{ - - struct - { - UINT32 Reserved_67 : 16 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status0 : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_VC_CAP9_U; - - - - -typedef union tagEepPortLogic0 -{ - - struct - { - UINT32 ack_lat_timer : 16 ; - UINT32 replay_timer : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC0_U; - - - - -typedef union tagEepPortLogic2 -{ - - struct - { - UINT32 linknumber : 8 ; - UINT32 Reserved_70 : 7 ; - UINT32 forcelink : 1 ; - UINT32 linkstate : 6 ; - UINT32 Reserved_69 : 2 ; - UINT32 port_force_link : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC2_U; - - - - -typedef union tagEepPortLogic3 -{ - - struct - { - UINT32 ackfrequency : 8 ; - UINT32 n_fts : 8 ; - UINT32 commonclockn_fts : 8 ; - UINT32 l0sentrancelatency : 3 ; - UINT32 l1entrancelatency : 3 ; - UINT32 enteraspml1withoutreceiveinl0s : 1 ; - UINT32 ack_aspm : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC3_U; - - - - -typedef union tagEepPortLogic4 -{ - - struct - { - UINT32 vendorspecificdllprequest : 1 ; - UINT32 scrambledisable : 1 ; - UINT32 loopbackenable : 1 ; - UINT32 resetassert : 1 ; - UINT32 Reserved_73 : 1 ; - UINT32 dlllinkenable : 1 ; - UINT32 Reserved_72 : 1 ; - UINT32 fastlinkmode : 1 ; - UINT32 Reserved_71 : 8 ; - UINT32 linkmodeenable : 6 ; - UINT32 crosslinkenable : 1 ; - UINT32 crosslinkactive : 1 ; - UINT32 port_link_ctrl : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC4_U; - - - - -typedef union tagEepPortLogic5 -{ - - struct - { - UINT32 insertlaneskewfortransmit : 24 ; - UINT32 flowcontroldisable : 1 ; - UINT32 ack_nakdisable : 1 ; - UINT32 Reserved_74 : 5 ; - UINT32 lane_skew : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC5_U; - - - - -typedef union tagEepPortLogic6 -{ - - struct - { - UINT32 numberoftssymbols : 4 ; - UINT32 Reserved_76 : 4 ; - UINT32 numberofskpsymbols : 3 ; - UINT32 Reserved_75 : 3 ; - UINT32 timermodifierforreplaytimer : 5 ; - UINT32 timermodifierforack_naklatencytimer : 5 ; - UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; - UINT32 sym_num : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC6_U; - - - - -typedef union tagEepPortLogic7 -{ - - struct - { - UINT32 vc0posteddataqueuedepth : 11 ; - UINT32 Reserved_77 : 4 ; - UINT32 sym_timer : 1 ; - UINT32 maskfunctionmismatchfilteringfo : 1 ; - UINT32 maskpoisonedtlpfiltering : 1 ; - UINT32 maskbarmatchfiltering : 1 ; - UINT32 masktype1configurationrequestfiltering : 1 ; - UINT32 masklockedrequestfiltering : 1 ; - UINT32 masktagerrorrulesforreceivedcompletions : 1 ; - UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; - UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; - UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; - UINT32 maske_crcerror_filtering : 1 ; - UINT32 maske_crcerror_filtering_forcompletions : 1 ; - UINT32 message_control : 1 ; - UINT32 maskfilteringofreceived : 1 ; - UINT32 flt_mask1 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC7_U; - - - - -typedef union tagEepPortLogic8 -{ - - struct - { - UINT32 cx_flt_mask_venmsg0_drop : 1 ; - UINT32 cx_flt_mask_venmsg1_drop : 1 ; - UINT32 cx_flt_mask_dabort_4ucpl : 1 ; - UINT32 cx_flt_mask_handle_flush : 1 ; - UINT32 flt_mask2 : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC8_U; - - - - -typedef union tagEepPortLogic9 -{ - - struct - { - UINT32 amba_multi_outbound_decomp_np : 1 ; - UINT32 amba_obnp_ctrl : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC9_U; - - - - -typedef union tagEepPortLogic12 -{ - - struct - { - UINT32 transmitposteddatafccredits : 12 ; - UINT32 transmitpostedheaderfccredits : 8 ; - UINT32 tx_pfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC12_U; - - - - -typedef union tagEepPortLogic13 -{ - - struct - { - UINT32 transmitnon_posteddatafccredits : 12 ; - UINT32 transmitnon_postedheaderfccredits : 8 ; - UINT32 tx_npfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC13_U; - - - - -typedef union tagEepPortLogic14 -{ - - struct - { - UINT32 transmitcompletiondatafccredits : 12 ; - UINT32 transmitcompletionheaderfccredits : 8 ; - UINT32 tx_cplfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC14_U; - - - - -typedef union tagEepPortLogic15 -{ - - struct - { - UINT32 rx_tlp_fc_credit_not_retured : 1 ; - UINT32 tx_retry_buf_not_empty : 1 ; - UINT32 rx_queue_not_empty : 1 ; - UINT32 Reserved_79 : 13 ; - UINT32 fc_latency_timer_override_value : 13 ; - UINT32 Reserved_78 : 2 ; - UINT32 fc_latency_timer_override_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC15_U; - - - - -typedef union tagEepPortLogic16 -{ - - struct - { - UINT32 vc0posteddatacredits : 12 ; - UINT32 vc0postedheadercredits : 8 ; - UINT32 Reserved_81 : 1 ; - UINT32 vc0_postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemo : 1 ; - UINT32 Reserved_80 : 6 ; - UINT32 tlptypeorderingforvc0 : 1 ; - UINT32 rx_pque_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC16_U; - - - - -typedef union tagEepPortLogic17 -{ - - struct - { - UINT32 vc0non_posteddatacredits : 12 ; - UINT32 vc0non_postedheadercredits : 8 ; - UINT32 rx_npque_ctrl : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC17_U; - - - - -typedef union tagEepPortLogic18 -{ - - struct - { - UINT32 vco_comp_data_credits : 12 ; - UINT32 vc0_cpl_header_credt : 8 ; - UINT32 Reserved_83 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC18_U; - - - - -typedef union tagEepPortLogic19 -{ - - struct - { - UINT32 vco_posted_data_que_path : 14 ; - UINT32 Reserved_84 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 vc_pbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC19_U; - - - - -typedef union tagEepPortLogic20 -{ - - struct - { - UINT32 vco_np_data_que_depth : 14 ; - UINT32 Reserved_86 : 2 ; - UINT32 vco_np_header_que_depth : 10 ; - UINT32 vc_npbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC20_U; - - - - -typedef union tagEepPortLogic21 -{ - - struct - { - UINT32 vco_comp_data_queue_depth : 14 ; - UINT32 Reserved_88 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 Reserved_87 : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC21_U; - - - - -typedef union tagEepPortLogic22 -{ - - struct - { - UINT32 n_fts : 8 ; - UINT32 pre_determ_num_of_lane : 9 ; - UINT32 det_sp_change : 1 ; - UINT32 config_phy_tx_sw : 1 ; - UINT32 config_tx_comp_rcv_bit : 1 ; - UINT32 set_emp_level : 1 ; - UINT32 Reserved_89 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORT_LOGIC22_U; - - - - -typedef union tagEepPortlogic25 -{ - - struct - { - UINT32 remote_rd_req_size : 3 ; - UINT32 Reserved_92 : 5 ; - UINT32 remote_max_brd_tag : 8 ; - UINT32 Reserved_91 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC25_U; - - - - -typedef union tagEepPortlogic26 -{ - - struct - { - UINT32 resize_master_resp_compser : 1 ; - UINT32 axi_ctrl1 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC26_U; - - - - -typedef union tagEepPortlogic54 -{ - - struct - { - UINT32 region_index : 4 ; - UINT32 Reserved_93 : 27 ; - UINT32 iatu_view : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC54_U; - - - - -typedef union tagEepPortlogic55 -{ - - struct - { - UINT32 iatu1_type : 5 ; - UINT32 iatu1_tc : 3 ; - UINT32 iatu1_td : 1 ; - UINT32 iatu1_attr : 2 ; - UINT32 Reserved_97 : 5 ; - UINT32 iatu1_at : 2 ; - UINT32 Reserved_96 : 2 ; - UINT32 iatu1_id : 3 ; - UINT32 Reserved_95 : 9 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC55_U; - - - - -typedef union tagEepPortlogic56 -{ - - struct - { - UINT32 iatu2_type : 8 ; - UINT32 iatu2_bar_num : 3 ; - UINT32 Reserved_101 : 3 ; - UINT32 iatu2_tc_match_en : 1 ; - UINT32 iatu2_td_match_en : 1 ; - UINT32 iatu2_attr_match_en : 1 ; - UINT32 Reserved_100 : 1 ; - UINT32 iatu2_at_match_en : 1 ; - UINT32 iatu2_func_num_match_en : 1 ; - UINT32 iatu2_virtual_func_num_match_en : 1 ; - UINT32 message_code_match_en : 1 ; - UINT32 Reserved_99 : 2 ; - UINT32 iatu2_response_code : 2 ; - UINT32 Reserved_98 : 1 ; - UINT32 iatu2_fuzzy_type_match_mode : 1 ; - UINT32 iatu2_cfg_shift_mode : 1 ; - UINT32 iatu2_ivert_mode : 1 ; - UINT32 iatu2_match_mode : 1 ; - UINT32 iatu2_region_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC56_U; - - - - -typedef union tagEepPortlogic57 -{ - - struct - { - UINT32 iatu_start_low : 12 ; - UINT32 iatu_start_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC57_U; - - - - -typedef union tagEepPortlogic59 -{ - - struct - { - UINT32 iatu_limit_low : 12 ; - UINT32 iatu_limit_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC59_U; - - - - -typedef union tagEepPortlogic60 -{ - - struct - { - UINT32 xlated_addr_high : 12 ; - UINT32 xlated_addr_low : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC60_U; - - - - -typedef union tagEepPortlogic62 -{ - - struct - { - UINT32 dma_wr_eng_en : 1 ; - UINT32 dma_wr_ena : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC62_U; - - - - -typedef union tagEepPortlogic63 -{ - - struct - { - UINT32 wr_doorbell_num : 3 ; - UINT32 Reserved_103 : 28 ; - UINT32 dma_wr_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC63_U; - - - - -typedef union tagEepPortlogic64 -{ - - struct - { - UINT32 dma_read_eng_en : 1 ; - UINT32 Reserved_104 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC64_U; - - - - -typedef union tagEepPortlogic65 -{ - - struct - { - UINT32 rd_doorbell_num : 3 ; - UINT32 Reserved_106 : 28 ; - UINT32 dma_rd_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC65_U; - - - - -typedef union tagEepPortlogic66 -{ - - struct - { - UINT32 done_int_status : 8 ; - UINT32 Reserved_108 : 8 ; - UINT32 abort_int_status : 8 ; - UINT32 Reserved_107 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC66_U; - - - - -typedef union tagEepPortlogic67 -{ - - struct - { - UINT32 done_int_mask : 8 ; - UINT32 Reserved_111 : 8 ; - UINT32 abort_int_mask : 8 ; - UINT32 Reserved_110 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC67_U; - - - - -typedef union tagEepPortlogic68 -{ - - struct - { - UINT32 done_int_clr : 8 ; - UINT32 Reserved_114 : 8 ; - UINT32 abort_int_clr : 8 ; - UINT32 Reserved_113 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC68_U; - - - - -typedef union tagEepPortlogic69 -{ - - struct - { - UINT32 app_rd_err_det : 8 ; - UINT32 Reserved_116 : 8 ; - UINT32 ll_element_fetch_err_det : 8 ; - UINT32 Reserved_115 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC69_U; - - - - -typedef union tagEepPortlogic74 -{ - - struct - { - UINT32 dma_wr_c0_imwr_data : 16 ; - UINT32 dma_wr_c1_imwr_data : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC74_U; - - - - -typedef union tagEepPortlogic75 -{ - - struct - { - UINT32 wr_ch_ll_remote_abort_int_en : 8 ; - UINT32 Reserved_118 : 8 ; - UINT32 wr_ch_ll_local_abort_int_en : 8 ; - UINT32 Reserved_117 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC75_U; - - - - -typedef union tagEepPortlogic76 -{ - - struct - { - UINT32 done_int_status : 8 ; - UINT32 Reserved_121 : 8 ; - UINT32 abort_int_status : 8 ; - UINT32 Reserved_120 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC76_U; - - - - -typedef union tagEepPortlogic77 -{ - - struct - { - UINT32 done_int_mask : 8 ; - UINT32 Reserved_123 : 8 ; - UINT32 abort_int_mask : 8 ; - UINT32 dma_rd_int_mask : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC77_U; - - - - -typedef union tagEepPortlogic78 -{ - - struct - { - UINT32 done_int_clr : 8 ; - UINT32 Reserved_125 : 8 ; - UINT32 abort_int_clr : 8 ; - UINT32 dma_rd_int_clr : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC78_U; - - - - -typedef union tagEepPortlogic79 -{ - - struct - { - UINT32 app_wr_err_det : 8 ; - UINT32 Reserved_126 : 8 ; - UINT32 link_list_fetch_err_det : 8 ; - UINT32 dma_rd_err_low : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC79_U; - - - - -typedef union tagEepPortlogic80 -{ - - struct - { - UINT32 unspt_request : 8 ; - UINT32 completer_abort : 8 ; - UINT32 cpl_time_out : 8 ; - UINT32 data_poison : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC80_U; - - - - -typedef union tagEepPortlogic81 -{ - - struct - { - UINT32 remote_abort_int_en : 8 ; - UINT32 Reserved_128 : 8 ; - UINT32 local_abort_int_en : 8 ; - UINT32 dma_rd_ll_err_ena : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC81_U; - - - - -typedef union tagEepPortlogic86 -{ - - struct - { - UINT32 channel_dir : 3 ; - UINT32 Reserved_131 : 28 ; - UINT32 dma_ch_con_idx : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC86_U; - - - - -typedef union tagEepPortlogic87 -{ - - struct - { - UINT32 cycle_bit : 1 ; - UINT32 toggle_cycle_bit : 1 ; - UINT32 load_link_pointer : 1 ; - UINT32 local_int_en : 1 ; - UINT32 remote_int_en : 1 ; - UINT32 channel_status : 2 ; - UINT32 Reserved_135 : 1 ; - UINT32 consumer_cycle_state : 1 ; - UINT32 linked_list_en : 1 ; - UINT32 Reserved_134 : 2 ; - UINT32 func_num_dma : 5 ; - UINT32 Reserved_133 : 7 ; - UINT32 no_snoop : 1 ; - UINT32 ro : 1 ; - UINT32 td : 1 ; - UINT32 tc : 3 ; - UINT32 dma_ch_ctrl : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC87_U; - - - - -typedef union tagEepPortlogic93 -{ - - struct - { - UINT32 Reserved_137 : 2 ; - UINT32 dma_ll_ptr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EEP_PORTLOGIC93_U; - - - -#define PCIE_MEEP_SBAR23XLAT_LOWER_REG (0x0) -#define PCIE_MEEP_SBAR23XLAT_UPPER_REG (0x4) -#define PCIE_MEEP_SBAR45XLAT_LOWER_REG (0x8) -#define PCIE_MEEP_SBAR45XLAT_UPPER_REG (0xC) -#define PCIE_MEEP_SBAR23LMT_LOWER_REG (0x10) -#define PCIE_MEEP_SBAR23LMT_UPPER_REG (0x14) -#define PCIE_MEEP_SBAR45LMT_LOWER_REG (0x18) -#define PCIE_MEEP_SBAR45LMT_UPPER_REG (0x1C) -#define PCIE_MEEP_SDOORBELL_REG (0x20) -#define PCIE_MEEP_SDOORBELL_MASK_REG (0x24) -#define PCIE_MEEP_CBDF_SBDF_REG (0x28) -#define PCIE_MEEP_NTB_CNTL_REG (0x2C) -#define PCIE_MEEP_PCI_CFG_HDR0_REG (0x1000) -#define PCIE_MEEP_PCI_CFG_HDR1_REG (0x1004) -#define PCIE_MEEP_PCI_CFG_HDR2_REG (0x1008) -#define PCIE_MEEP_PCI_CFG_HDR3_REG (0x100C) -#define PCIE_MEEP_PCI_CFG_HDR4_REG (0x1010) -#define PCIE_MEEP_PCI_CFG_HDR5_REG (0x1014) -#define PCIE_MEEP_PCI_CFG_HDR6_REG (0x1018) -#define PCIE_MEEP_PCI_CFG_HDR7_REG (0x101C) -#define PCIE_MEEP_PCI_CFG_HDR8_REG (0x1020) -#define PCIE_MEEP_PCI_CFG_HDR9_REG (0x1024) -#define PCIE_MEEP_PCI_CFG_HDR10_REG (0x1028) -#define PCIE_MEEP_PCI_CFG_HDR11_REG (0x102C) -#define PCIE_MEEP_PCI_CFG_HDR12_REG (0x1030) -#define PCIE_MEEP_PCI_CFG_HDR13_REG (0x1034) -#define PCIE_MEEP_PCI_CFG_HDR14_REG (0x1038) -#define PCIE_MEEP_PCI_CFG_HDR15_REG (0x103C) -#define PCIE_MEEP_PCI_PM_CAP0_REG (0x1040) -#define PCIE_MEEP_PCI_PM_CAP1_REG (0x1044) -#define PCIE_MEEP_PCI_MSI_CAP0_REG (0x1050) -#define PCIE_MEEP_PCI_MSI_CAP1_REG (0x1054) -#define PCIE_MEEP_PCI_MSI_CAP2_REG (0x1058) -#define PCIE_MEEP_PCI_MSI_CAP3_REG (0x105C) -#define PCIE_MEEP_PCIE_CAP0_REG (0x1070) -#define PCIE_MEEP_PCIE_CAP1_REG (0x1074) -#define PCIE_MEEP_PCIE_CAP2_REG (0x1078) -#define PCIE_MEEP_PCIE_CAP3_REG (0x107C) -#define PCIE_MEEP_PCIE_CAP4_REG (0x1080) -#define PCIE_MEEP_PCIE_CAP5_REG (0x1084) -#define PCIE_MEEP_PCIE_CAP6_REG (0x1088) -#define PCIE_MEEP_PCIE_CAP7_REG (0x108C) -#define PCIE_MEEP_PCIE_CAP8_REG (0x1090) -#define PCIE_MEEP_PCIE_CAP9_REG (0x1094) -#define PCIE_MEEP_PCIE_CAP10_REG (0x1098) -#define PCIE_MEEP_PCIE_CAP11_REG (0x109C) -#define PCIE_MEEP_PCIE_CAP12_REG (0x10A0) -#define PCIE_MEEP_SLOT_CAP_REG (0x10C0) -#define PCIE_MEEP_AER_CAP0_REG (0x1100) -#define PCIE_MEEP_AER_CAP1_REG (0x1104) -#define PCIE_MEEP_AER_CAP2_REG (0x1108) -#define PCIE_MEEP_AER_CAP3_REG (0x110C) -#define PCIE_MEEP_AER_CAP4_REG (0x1110) -#define PCIE_MEEP_AER_CAP5_REG (0x1114) -#define PCIE_MEEP_AER_CAP6_REG (0x1118) -#define PCIE_MEEP_AER_CAP7_REG (0x11C) -#define PCIE_MEEP_AER_CAP8_REG (0x120) -#define PCIE_MEEP_AER_CAP9_REG (0x124) -#define PCIE_MEEP_AER_CAP10_REG (0x128) -#define PCIE_MEEP_AER_CAP11_REG (0x112C) -#define PCIE_MEEP_AER_CAP12_REG (0x1130) -#define PCIE_MEEP_AER_CAP13_REG (0x1134) -#define PCIE_MEEP_VC_CAP0_REG (0x1140) -#define PCIE_MEEP_VC_CAP1_REG (0x1144) -#define PCIE_MEEP_VC_CAP2_REG (0x1148) -#define PCIE_MEEP_VC_CAP3_REG (0x114C) -#define PCIE_MEEP_VC_CAP4_REG (0x1150) -#define PCIE_MEEP_VC_CAP5_REG (0x1154) -#define PCIE_MEEP_VC_CAP6_REG (0x1158) -#define PCIE_MEEP_VC_CAP7_REG (0x115C) -#define PCIE_MEEP_VC_CAP8_REG (0x1160) -#define PCIE_MEEP_VC_CAP9_REG (0x1164) -#define PCIE_MEEP_PORT_LOGIC0_REG (0x1700) -#define PCIE_MEEP_PORT_LOGIC1_REG (0x1704) -#define PCIE_MEEP_PORT_LOGIC2_REG (0x1708) -#define PCIE_MEEP_PORT_LOGIC3_REG (0x170C) -#define PCIE_MEEP_PORT_LOGIC4_REG (0x1710) -#define PCIE_MEEP_PORT_LOGIC5_REG (0x1714) -#define PCIE_MEEP_PORT_LOGIC6_REG (0x1718) -#define PCIE_MEEP_PORT_LOGIC7_REG (0x171C) -#define PCIE_MEEP_PORT_LOGIC8_REG (0x1720) -#define PCIE_MEEP_PORT_LOGIC9_REG (0x1724) -#define PCIE_MEEP_PORT_LOGIC10_REG (0x1728) -#define PCIE_MEEP_PORT_LOGIC11_REG (0x172C) -#define PCIE_MEEP_PORT_LOGIC12_REG (0x1730) -#define PCIE_MEEP_PORT_LOGIC13_REG (0x1734) -#define PCIE_MEEP_PORT_LOGIC14_REG (0x1738) -#define PCIE_MEEP_PORT_LOGIC15_REG (0x173C) -#define PCIE_MEEP_PORT_LOGIC16_REG (0x1748) -#define PCIE_MEEP_PORT_LOGIC17_REG (0x174C) -#define PCIE_MEEP_PORT_LOGIC18_REG (0x1750) -#define PCIE_MEEP_PORT_LOGIC19_REG (0x17A8) -#define PCIE_MEEP_PORT_LOGIC20_REG (0x17AC) -#define PCIE_MEEP_PORT_LOGIC21_REG (0x17B0) -#define PCIE_MEEP_PORT_LOGIC22_REG (0x180C) -#define PCIE_MEEP_PORTLOGIC23_REG (0x1810) -#define PCIE_MEEP_PORTLOGIC24_REG (0x1814) -#define PCIE_MEEP_PORTLOGIC25_REG (0x1818) -#define PCIE_MEEP_PORTLOGIC26_REG (0x181C) -#define PCIE_MEEP_PORTLOGIC27_REG (0x1820) -#define PCIE_MEEP_PORTLOGIC28_REG (0x1824) -#define PCIE_MEEP_PORTLOGIC29_REG (0x1828) -#define PCIE_MEEP_PORTLOGIC30_REG (0x182C) -#define PCIE_MEEP_PORTLOGIC31_REG (0x1830) -#define PCIE_MEEP_PORTLOGIC32_REG (0x1834) -#define PCIE_MEEP_PORTLOGIC33_REG (0x1838) -#define PCIE_MEEP_PORTLOGIC34_REG (0x183C) -#define PCIE_MEEP_PORTLOGIC35_REG (0x1840) -#define PCIE_MEEP_PORTLOGIC36_REG (0x1844) -#define PCIE_MEEP_PORTLOGIC37_REG (0x1848) -#define PCIE_MEEP_PORTLOGIC38_REG (0x184C) -#define PCIE_MEEP_PORTLOGIC39_REG (0x1850) -#define PCIE_MEEP_PORTLOGIC40_REG (0x1854) -#define PCIE_MEEP_PORTLOGIC41_REG (0x1858) -#define PCIE_MEEP_PORTLOGIC42_REG (0x185C) -#define PCIE_MEEP_PORTLOGIC43_REG (0x1860) -#define PCIE_MEEP_PORTLOGIC44_REG (0x1864) -#define PCIE_MEEP_PORTLOGIC45_REG (0x1868) -#define PCIE_MEEP_PORTLOGIC46_REG (0x186C) -#define PCIE_MEEP_PORTLOGIC47_REG (0x1870) -#define PCIE_MEEP_PORTLOGIC48_REG (0x1874) -#define PCIE_MEEP_PORTLOGIC49_REG (0x1878) -#define PCIE_MEEP_PORTLOGIC50_REG (0x187C) -#define PCIE_MEEP_PORTLOGIC51_REG (0x1880) -#define PCIE_MEEP_PORTLOGIC52_REG (0x1884) -#define PCIE_MEEP_PORTLOGIC53_REG (0x1888) -#define PCIE_MEEP_PORTLOGIC54_REG (0x1900) -#define PCIE_MEEP_PORTLOGIC55_REG (0x1904) -#define PCIE_MEEP_PORTLOGIC56_REG (0x908) -#define PCIE_MEEP_PORTLOGIC57_REG (0x190C) -#define PCIE_MEEP_PORTLOGIC58_REG (0x1910) -#define PCIE_MEEP_PORTLOGIC59_REG (0x1914) -#define PCIE_MEEP_PORTLOGIC60_REG (0x1918) -#define PCIE_MEEP_PORTLOGIC61_REG (0x191C) -#define PCIE_MEEP_PORTLOGIC62_REG (0x197C) -#define PCIE_MEEP_PORTLOGIC63_REG (0x1980) -#define PCIE_MEEP_PORTLOGIC64_REG (0x199C) -#define PCIE_MEEP_PORTLOGIC65_REG (0x19A0) -#define PCIE_MEEP_PORTLOGIC66_REG (0x19BC) -#define PCIE_MEEP_PORTLOGIC67_REG (0x19C4) -#define PCIE_MEEP_PORTLOGIC68_REG (0x19C8) -#define PCIE_MEEP_PORTLOGIC69_REG (0x19CC) -#define PCIE_MEEP_PORTLOGIC70_REG (0x19D0) -#define PCIE_MEEP_PORTLOGIC71_REG (0x19D4) -#define PCIE_MEEP_PORTLOGIC72_REG (0x19D8) -#define PCIE_MEEP_PORTLOGIC73_REG (0x19DC) -#define PCIE_MEEP_PORTLOGIC74_REG (0x19E0) -#define PCIE_MEEP_PORTLOGIC75_REG (0x1A00) -#define PCIE_MEEP_PORTLOGIC76_REG (0x1A10) -#define PCIE_MEEP_PORTLOGIC77_REG (0x1A18) -#define PCIE_MEEP_PORTLOGIC78_REG (0x1A1C) -#define PCIE_MEEP_PORTLOGIC79_REG (0x1A24) -#define PCIE_MEEP_PORTLOGIC80_REG (0x1A28) -#define PCIE_MEEP_PORTLOGIC81_REG (0x1A34) -#define PCIE_MEEP_PORTLOGIC82_REG (0x1A3C) -#define PCIE_MEEP_PORTLOGIC83_REG (0x1A40) -#define PCIE_MEEP_PORTLOGIC84_REG (0x1A44) -#define PCIE_MEEP_PORTLOGIC85_REG (0xA48) -#define PCIE_MEEP_PORTLOGIC86_REG (0xA6C) -#define PCIE_MEEP_PORTLOGIC87_REG (0x1A70) -#define PCIE_MEEP_PORTLOGIC88_REG (0x1A78) -#define PCIE_MEEP_PORTLOGIC89_REG (0x1A7C) -#define PCIE_MEEP_PORTLOGIC90_REG (0x1A80) -#define PCIE_MEEP_PORTLOGIC91_REG (0x1A84) -#define PCIE_MEEP_PORTLOGIC92_REG (0x1A88) -#define PCIE_MEEP_PORTLOGIC93_REG (0x1A8C) -#define PCIE_MEEP_PORTLOGIC94_REG (0x1A90) -#define PCIE_MEEP_PBAR23XLAT_LOWER_REG (0x8000) -#define PCIE_MEEP_PBAR23XLAT_UPPER_REG (0x8004) -#define PCIE_MEEP_PBAR45XLAT_LOWER_REG (0x8008) -#define PCIE_MEEP_PBAR45XLAT_UPPER_REG (0x800C) -#define PCIE_MEEP_PBAR23LMT_LOWER_REG (0x8010) -#define PCIE_MEEP_PBAR23LMT_UPPER_REG (0x8014) -#define PCIE_MEEP_PBAR45LMT_LOWER_REG (0x8018) -#define PCIE_MEEP_PBAR45LMT_UPPER_REG (0x801C) -#define PCIE_MEEP_PDOORBELL_REG (0x8020) -#define PCIE_MEEP_PDOORBELL_MASK_REG (0x8024) -#define PCIE_MEEP_B2B_BAR01XLAT_LOWER_REG (0x8028) -#define PCIE_MEEP_B2B_BAR01XLAT_UPPER_REG (0x802C) -#define PCIE_MEEP_B2B_DOORBELL_REG (0x8030) -#define PCIE_MEEP_SPAD0_REG (0x8038) -#define PCIE_MEEP_SPAD1_REG (0x803C) -#define PCIE_MEEP_SPAD2_REG (0x8040) -#define PCIE_MEEP_SPAD3_REG (0x8044) -#define PCIE_MEEP_SPAD4_REG (0x8048) -#define PCIE_MEEP_SPAD5_REG (0x804C) -#define PCIE_MEEP_SPAD6_REG (0x8050) -#define PCIE_MEEP_SPAD7_REG (0x8054) -#define PCIE_MEEP_SPAD8_REG (0x8058) -#define PCIE_MEEP_SPAD9_REG (0x805C) -#define PCIE_MEEP_SPAD10_REG (0x8060) -#define PCIE_MEEP_SPAD11_REG (0x8064) -#define PCIE_MEEP_SPAD12_REG (0x8068) -#define PCIE_MEEP_SPAD13_REG (0x806C) -#define PCIE_MEEP_SPAD14_REG (0x8070) -#define PCIE_MEEP_SPAD15_REG (0x8074) -#define PCIE_MEEP_SPAD16_REG (0x8078) -#define PCIE_MEEP_SPAD17_REG (0x807C) -#define PCIE_MEEP_SPAD18_REG (0x8080) -#define PCIE_MEEP_SPAD19_REG (0x8084) -#define PCIE_MEEP_SPAD20_REG (0x8088) -#define PCIE_MEEP_SPAD21_REG (0x808C) -#define PCIE_MEEP_SPAD22_REG (0x8090) -#define PCIE_MEEP_SPAD23_REG (0x8094) -#define PCIE_MEEP_SPAD24_REG (0x8098) -#define PCIE_MEEP_SPAD25_REG (0x809C) -#define PCIE_MEEP_SPAD26_REG (0x80A0) -#define PCIE_MEEP_SPAD27_REG (0x80A4) -#define PCIE_MEEP_SPAD28_REG (0x80A8) -#define PCIE_MEEP_SPAD29_REG (0x80AC) -#define PCIE_MEEP_SPAD30_REG (0x80B0) -#define PCIE_MEEP_SPAD31_REG (0x80B4) -#define PCIE_MEEP_PPD_REG (0x8138) -#define PCIE_MEEP_DEVICE_VENDOR_ID_REG (0x9000) -#define PCIE_MEEP_PCISTS_PCICMD_REG (0x9004) -#define PCIE_MEEP_CCR_RID_REG (0x9008) -#define PCIE_MEEP_PBAR01_BASE_LOWER_REG (0x9010) -#define PCIE_MEEP_PBAR01_BASE_UPPER_REG (0x9014) -#define PCIE_MEEP_PBAR23_BASE_LOWER_REG (0x9018) -#define PCIE_MEEP_PBAR23_BASE_UPPER_REG (0x901C) -#define PCIE_MEEP_PBAR45_BASE_LOWER_REG (0x9020) -#define PCIE_MEEP_PBAR45_BASE_UPPER_REG (0x9024) -#define PCIE_MEEP_CARDBUSCISPTR_REG (0x9028) -#define PCIE_MEEP_SUBSYSTEMID_REG (0x902C) -#define PCIE_MEEP_EXPANSIONROM_BASE_ADDR_REG (0x9030) -#define PCIE_MEEP_CAPPTR_REG (0x9034) -#define PCIE_MEEP_INTERRUPT_REG (0x903C) -#define PCIE_MEEP_MSI_CAPABILITY_REGISTER_REG (0x9050) -#define PCIE_MEEP_MSI_LOWER32_BITADDRESS_REG (0x9054) -#define PCIE_MEEP_MSI_UPPER32_BIT_ADDRESS_REG (0x9058) -#define PCIE_MEEP_MSI_DATA_REG (0x905C) -#define PCIE_MEEP_MSI_MASK_REG (0x9060) -#define PCIE_MEEP_MSI_PENDING_REG (0x9064) -#define PCIE_MEEP_PCIE_CAPABILITY_REGISTER_REG (0x9070) -#define PCIE_MEEP_DEVICE_CAPABILITIES_REGISTER_REG (0x9074) -#define PCIE_MEEP_DEVICE_STATUS_REGISTER_REG (0x9078) -#define PCIE_MEEP_LINK_CAPABILITY_REG (0x907C) -#define PCIE_MEEP_LINK_CONTROL_STATUS_REG (0x9080) -#define PCIE_MEEP_AER_CAP_HEADER_REG (0x9100) -#define PCIE_MEEP_UC_ERROR_STATUS_REG (0x9104) -#define PCIE_MEEP_UC_ERROR_MASK_REG (0x9108) -#define PCIE_MEEP_UC_ERROR_SEVERITY_REG (0x910C) -#define PCIE_MEEP_C_ERROR_STATUS_REG (0x9110) -#define PCIE_MEEP_C_ERROR_MASK_REG (0x9114) -#define PCIE_MEEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (0x9118) -#define PCIE_MEEP_HEADER_LOG_REGISTERS_1_REG (0x911C) -#define PCIE_MEEP_HEADER_LOG_REGISTERS_2_REG (0x9120) -#define PCIE_MEEP_HEADER_LOG_REGISTERS_3_REG (0x9124) -#define PCIE_MEEP_HEADER_LOG_REGISTERS_4_REG (0x9128) -#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_1_REG (0x9130) -#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_2_REG (0x9134) -#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_3_REG (0x9138) -#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_4_REG (0x913C) -#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x9700) -#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x9704) -#define PCIE_MEEP_NTB_IEP_BAR01_CTRL_REG (0x9708) -#define PCIE_MEEP_NTB_IEP_BAR23_CTRL_REG (0x970C) -#define PCIE_MEEP_NTB_IEP_BAR45_CTRL_REG (0x9710) -#define PCIE_MEEP_MSI_CTRL_ADDRESS_LOWER_REG (0x9714) -#define PCIE_MEEP_MSI_CTRL_ADDRESS_UPPER_REG (0x9718) -#define PCIE_MEEP_MSI_CTRL_INT_EN_REG (0x971C) -#define PCIE_MEEP_MSI_CTRL_INT0_MASK_REG (0x9720) -#define PCIE_MEEP_MSI_CTRL_INT_STATUS_REG (0x9724) -#define PCIE_MEEP_DBI_RO_WR_EN_REG (0x9728) -#define PCIE_MEEP_AXI_ERR_RESPONSE_REG (0x972C) - - - -typedef union tagMeepSbar23xlatLower -{ - - struct - { - UINT32 Reserved_0 : 12 ; - UINT32 sbar23xlat_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SBAR23XLAT_LOWER_U; - - - - -typedef union tagMeepSbar45xlatLower -{ - - struct - { - UINT32 Reserved_1 : 12 ; - UINT32 sbar45xlat_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SBAR45XLAT_LOWER_U; - - - - -typedef union tagMeepSbar23lmtLower -{ - - struct - { - UINT32 Reserved_2 : 12 ; - UINT32 sbar45limit_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SBAR23LMT_LOWER_U; - - - - -typedef union tagMeepSbar45lmtLower -{ - - struct - { - UINT32 Reserved_3 : 12 ; - UINT32 sbar45limit_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SBAR45LMT_LOWER_U; - - - - -typedef union tagMeepSbar45lmtUpper -{ - - struct - { - UINT32 Reserved_4 : 12 ; - UINT32 sbar45limit_upper : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SBAR45LMT_UPPER_U; - - - - -typedef union tagMeepCbdfSbdf -{ - - struct - { - UINT32 sfunc : 3 ; - UINT32 sdev : 5 ; - UINT32 sbus : 8 ; - UINT32 cap_sfunc : 3 ; - UINT32 cap_sdev : 5 ; - UINT32 cap_sbus : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_CBDF_SBDF_U; - - - - -typedef union tagMeepNtbCntl -{ - - struct - { - UINT32 s_link_disable : 1 ; - UINT32 Reserved_6 : 1 ; - UINT32 eep_shadow_en : 1 ; - UINT32 Reserved_5 : 29 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_NTB_CNTL_U; - - - - -typedef union tagMeepPciCfgHdr0 -{ - - struct - { - UINT32 vendor_id : 16 ; - UINT32 device_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR0_U; - - - - -typedef union tagMeepPciCfgHdr1 -{ - - struct - { - UINT32 io_space_enable : 1 ; - UINT32 memory_space_enable : 1 ; - UINT32 bus_master_enable : 1 ; - UINT32 specialcycleenable : 1 ; - UINT32 memory_write_and_invalidate : 1 ; - UINT32 vga_palette_snoop_enable : 1 ; - UINT32 parity_error_response : 1 ; - UINT32 idsel_stepping_waitcycle_control : 1 ; - UINT32 serr_enable : 1 ; - UINT32 fastback_to_backenable : 1 ; - UINT32 interrupt_disable : 1 ; - UINT32 Reserved_10 : 5 ; - UINT32 Reserved_9 : 3 ; - UINT32 intx_status : 1 ; - UINT32 capabilitieslist : 1 ; - UINT32 pcibus66mhzcapable : 1 ; - UINT32 Reserved_8 : 1 ; - UINT32 fastback_to_back : 1 ; - UINT32 masterdataparityerror : 1 ; - UINT32 devsel_timing : 2 ; - UINT32 signaled_target_abort : 1 ; - UINT32 received_target_abort : 1 ; - UINT32 received_master_abort : 1 ; - UINT32 signaled_system_error : 1 ; - UINT32 detected_parity_error : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR1_U; - - - - -typedef union tagMeepPciCfgHdr2 -{ - - struct - { - UINT32 revision_identification : 8 ; - UINT32 Reserved_11 : 8 ; - UINT32 sub_class : 8 ; - UINT32 baseclass : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR2_U; - - - - -typedef union tagMeepPciCfgHdr3 -{ - - struct - { - UINT32 cache_line_size : 8 ; - UINT32 mstr_lat_tmr : 8 ; - UINT32 multi_function_device : 7 ; - UINT32 hdr_type : 1 ; - UINT32 bist : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR3_U; - - - - -typedef union tagMeepPciCfgHdr4 -{ - - struct - { - UINT32 sbar01_space_inicator : 1 ; - UINT32 sbar01_type : 2 ; - UINT32 sbar01_prefetchable : 1 ; - UINT32 sbar01_lower : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR4_U; - - - - -typedef union tagMeepPciCfgHdr6 -{ - - struct - { - UINT32 sbar23_space_inicator : 1 ; - UINT32 sbar23_type : 2 ; - UINT32 sbar23_prefetchable : 1 ; - UINT32 Reserved_12 : 8 ; - UINT32 sbar23_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR6_U; - - - - -typedef union tagMeepPciCfgHdr8 -{ - - struct - { - UINT32 sbar45_space_inicator : 1 ; - UINT32 sbar45_type : 2 ; - UINT32 sbar45_prefetchable : 1 ; - UINT32 Reserved_13 : 8 ; - UINT32 sbar45_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR8_U; - - - - -typedef union tagMeepPciCfgHdr11 -{ - - struct - { - UINT32 subsystem_vendor_id : 16 ; - UINT32 subsystemid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR11_U; - - - - -typedef union tagMeepPciCfgHdr13 -{ - - struct - { - UINT32 cap_ptr : 8 ; - UINT32 Reserved_14 : 24 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR13_U; - - - - -typedef union tagMeepPciCfgHdr15 -{ - - struct - { - UINT32 int_line : 8 ; - UINT32 int_pin : 8 ; - UINT32 Min_Grant : 8 ; - UINT32 Max_Latency : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_CFG_HDR15_U; - - - - -typedef union tagMeepPciMsiCap0 -{ - - struct - { - UINT32 msi_cap_id : 8 ; - UINT32 next_capability_pointer : 8 ; - UINT32 msi_enabled : 1 ; - UINT32 multiple_message_capable : 3 ; - UINT32 multiple_message_enabled : 3 ; - UINT32 msi_64_en : 1 ; - UINT32 pvm : 1 ; - UINT32 Reserved_18 : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_MSI_CAP0_U; - - - - -typedef union tagMeepPciMsiCap1 -{ - - struct - { - UINT32 Reserved_20 : 2 ; - UINT32 msi_addr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_MSI_CAP1_U; - - - - -typedef union tagMeepPciMsiCap3 -{ - - struct - { - UINT32 msi_data : 16 ; - UINT32 Reserved_21 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCI_MSI_CAP3_U; - - - - -typedef union tagMeepPcieCap0 -{ - - struct - { - UINT32 pcie_cap_id : 8 ; - UINT32 pcie_next_ptr : 8 ; - UINT32 pcie_capability_version : 4 ; - UINT32 device_port_type : 4 ; - UINT32 slot_implemented : 1 ; - UINT32 interrupt_message_number : 5 ; - UINT32 Reserved_22 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP0_U; - - - - -typedef union tagMeepPcieCap1 -{ - - struct - { - UINT32 max_payload_size_supported : 3 ; - UINT32 phantom_function_supported : 2 ; - UINT32 extended_tagfield_supported : 1 ; - UINT32 endpoint_l0sacceptable_latency : 3 ; - UINT32 endpoint_l1acceptable_latency : 3 ; - UINT32 undefined : 3 ; - UINT32 Reserved_24 : 3 ; - UINT32 captured_slot_power_limit_value : 8 ; - UINT32 captured_slot_power_limit_scale : 2 ; - UINT32 function_level_reset : 1 ; - UINT32 dev_cap : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP1_U; - - - - -typedef union tagMeepPcieCap2 -{ - - struct - { - UINT32 correctable_error_reporting_enable : 1 ; - UINT32 non_fatal_error_reporting_enable : 1 ; - UINT32 fatal_error_reporting_enable : 1 ; - UINT32 urenable : 1 ; - UINT32 enable_relaxed_ordering : 1 ; - UINT32 max_payload_size : 3 ; - UINT32 extended_tagfieldenable : 1 ; - UINT32 phantom_function_enable : 1 ; - UINT32 auxpowerpmenable : 1 ; - UINT32 enablenosnoop : 1 ; - UINT32 max_read_request_size : 3 ; - UINT32 Reserved_26 : 1 ; - UINT32 correctableerrordetected : 1 ; - UINT32 non_fatalerrordetected : 1 ; - UINT32 fatalerrordetected : 1 ; - UINT32 unsupportedrequestdetected : 1 ; - UINT32 auxpowerdetected : 1 ; - UINT32 transactionpending : 1 ; - UINT32 Reserved_25 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP2_U; - - - - -typedef union tagMeepPcieCap3 -{ - - struct - { - UINT32 max_link_speed : 4 ; - UINT32 max_link_width : 6 ; - UINT32 active_state_power_management : 2 ; - UINT32 l0s_exitlatency : 3 ; - UINT32 l1_exit_latency : 3 ; - UINT32 clock_power_management : 1 ; - UINT32 surprise_down_error_report_cap : 1 ; - UINT32 data_link_layer_active_report_cap : 1 ; - UINT32 link_bandwidth_noti_cap : 1 ; - UINT32 aspm_option_compliance : 1 ; - UINT32 Reserved_27 : 1 ; - UINT32 port_number : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP3_U; - - - - -typedef union tagMeepPcieCap4 -{ - - struct - { - UINT32 active_state_power_management : 2 ; - UINT32 Reserved_30 : 1 ; - UINT32 rcb : 1 ; - UINT32 link_disable : 1 ; - UINT32 retrain_link : 1 ; - UINT32 common_clock_config : 1 ; - UINT32 extended_sync : 1 ; - UINT32 enable_clock_pwr_management : 1 ; - UINT32 hw_auto_width_disable : 1 ; - UINT32 link_bandwidth_management_int_en : 1 ; - UINT32 link_auto_bandwidth_int_en : 1 ; - UINT32 Reserved_29 : 4 ; - UINT32 current_link_speed : 4 ; - UINT32 negotiated_link_width : 6 ; - UINT32 Reserved_28 : 1 ; - UINT32 link_training : 1 ; - UINT32 slot_clock_configration : 1 ; - UINT32 data_link_layer_active : 1 ; - UINT32 link_bandwidth_management_status : 1 ; - UINT32 link_auto_bandwidth_status : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP4_U; - - - - -typedef union tagMeepPcieCap5 -{ - - struct - { - UINT32 attentionbuttonpresent : 1 ; - UINT32 powercontrollerpresent : 1 ; - UINT32 mrlsensorpresent : 1 ; - UINT32 attentionindicatorpresent : 1 ; - UINT32 powerindicatorpresent : 1 ; - UINT32 hot_plugsurprise : 1 ; - UINT32 hot_plugcapable : 1 ; - UINT32 slotpowerlimitvalue : 8 ; - UINT32 slotpowerlimitscale : 2 ; - UINT32 electromechanicalinterlockpresen : 1 ; - UINT32 no_cmd_complete_support : 1 ; - UINT32 phy_slot_number : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP5_U; - - - - -typedef union tagMeepPcieCap6 -{ - - struct - { - UINT32 attentionbuttonpressedenable : 1 ; - UINT32 powerfaultdetectedenable : 1 ; - UINT32 mrlsensorchangedenable : 1 ; - UINT32 presencedetectchangedenable : 1 ; - UINT32 commandcompletedinterruptenable : 1 ; - UINT32 hot_pluginterruptenable : 1 ; - UINT32 attentionindicatorcontrol : 2 ; - UINT32 powerindicatorcontrol : 2 ; - UINT32 powercontrollercontrol : 1 ; - UINT32 electromechanicalinterlockcontrol : 1 ; - UINT32 datalinklayerstatechangedenable : 1 ; - UINT32 Reserved_31 : 3 ; - UINT32 attentionbuttonpressed : 1 ; - UINT32 powerfaultdetected : 1 ; - UINT32 mrlsensorchanged : 1 ; - UINT32 presencedetectchanged : 1 ; - UINT32 commandcompleted : 1 ; - UINT32 mrlsensorstate : 1 ; - UINT32 presencedetectstate : 1 ; - UINT32 electromechanicalinterlockstatus : 1 ; - UINT32 datalinklayerstatechanged : 1 ; - UINT32 slot_ctrl_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP6_U; - - - - -typedef union tagMeepPcieCap7 -{ - - struct - { - UINT32 systemerroroncorrectableerrorenable : 1 ; - UINT32 systemerroronnon_fatalerrorenable : 1 ; - UINT32 systemerroronfatalerrorenable : 1 ; - UINT32 pmeinterruptenable : 1 ; - UINT32 crssoftwarevisibilityenable : 1 ; - UINT32 Reserved_32 : 11 ; - UINT32 crssoftwarevisibility : 1 ; - UINT32 root_cap : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP7_U; - - - - -typedef union tagMeepPcieCap8 -{ - - struct - { - UINT32 pmerequesterid : 16 ; - UINT32 pmestatus : 1 ; - UINT32 pmepending : 1 ; - UINT32 root_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP8_U; - - - - -typedef union tagMeepPcieCap9 -{ - - struct - { - UINT32 completiontimeoutrangessupported : 4 ; - UINT32 completiontimeoutdisablesupported : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoproutingsupported : 1 ; - UINT32 _2_bitatomicopcompletersupported : 1 ; - UINT32 _4_bitatomicopcompletersupported : 1 ; - UINT32 _28_bitcascompletersupported : 1 ; - UINT32 noro_enabledpr_prpassing : 1 ; - UINT32 Reserved_33 : 1 ; - UINT32 tphcompletersupported : 2 ; - UINT32 dev_cap2 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP9_U; - - - - -typedef union tagMeepPcieCap10 -{ - - struct - { - UINT32 completiontimeoutvalue : 4 ; - UINT32 completiontimeoutdisable : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoprequesterenable : 1 ; - UINT32 atomicopegressblocking : 1 ; - UINT32 idorequestenable : 1 ; - UINT32 idocompletionenable : 1 ; - UINT32 dev_ctrl2 : 22 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP10_U; - - - - -typedef union tagMeepPcieCap11 -{ - - struct - { - UINT32 Reserved_35 : 1 ; - UINT32 gen1_suport : 1 ; - UINT32 gen2_suport : 1 ; - UINT32 gen3_suport : 1 ; - UINT32 Reserved_34 : 4 ; - UINT32 crosslink_supported : 1 ; - UINT32 link_cap2 : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP11_U; - - - - -typedef union tagMeepPcieCap12 -{ - - struct - { - UINT32 targetlinkspeed : 4 ; - UINT32 entercompliance : 1 ; - UINT32 hardwareautonomousspeeddisa : 1 ; - UINT32 selectablede_empha : 1 ; - UINT32 transmitmargin : 3 ; - UINT32 _entermodifiedcompliance : 1 ; - UINT32 compliancesos : 1 ; - UINT32 de_emphasislevel : 4 ; - UINT32 currentde_emphasislevel : 1 ; - UINT32 equalizationcomplete : 1 ; - UINT32 equalizationphase1successful : 1 ; - UINT32 equalizationphase2successful : 1 ; - UINT32 equalizationphase3successful : 1 ; - UINT32 linkequalizationrequest : 1 ; - UINT32 link_ctrl2_status2 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_CAP12_U; - - - - -typedef union tagMeepSlotCap -{ - - struct - { - UINT32 slotnumberingcapabilitiesid : 8 ; - UINT32 nextcapabilitypointer : 8 ; - UINT32 add_incardslotsprovided : 5 ; - UINT32 firstinchassis : 1 ; - UINT32 Reserved_36 : 2 ; - UINT32 slot_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SLOT_CAP_U; - - - - -typedef union tagMeepAerCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 aer_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP0_U; - - - - -typedef union tagMeepAerCap1 -{ - - struct - { - UINT32 Reserved_42 : 1 ; - UINT32 Reserved_41 : 3 ; - UINT32 datalinkprotocolerrorsta : 1 ; - UINT32 surprisedownerrorstatus : 1 ; - UINT32 Reserved_40 : 6 ; - UINT32 poisonedtlpstatu : 1 ; - UINT32 flowcontrolprotocolerrorst : 1 ; - UINT32 completiontimeouts : 1 ; - UINT32 completerabortstatus : 1 ; - UINT32 receiveroverflowstatus : 1 ; - UINT32 malformedtlpstatus : 1 ; - UINT32 ecrcerrorstatus : 1 ; - UINT32 ecrcerrorstat : 1 ; - UINT32 unsupportedrequesterrorstatus : 1 ; - UINT32 Reserved_39 : 3 ; - UINT32 atomicopegressblockedstatus : 1 ; - UINT32 uncorr_err_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP1_U; - - - - -typedef union tagMeepAerCap2 -{ - - struct - { - UINT32 Reserved_46 : 1 ; - UINT32 Reserved_45 : 3 ; - UINT32 datalinkprotocolerrormask : 1 ; - UINT32 surprisedownerrormask : 1 ; - UINT32 Reserved_44 : 6 ; - UINT32 poisonedtlpmask : 1 ; - UINT32 flowcontrolprotocolerrormask : 1 ; - UINT32 completiontimeoutmask : 1 ; - UINT32 completerabortmask : 1 ; - UINT32 unexpectedcompletionmask : 1 ; - UINT32 receiveroverflowmask : 1 ; - UINT32 malformedtlpmask : 1 ; - UINT32 ecrcerrormask : 1 ; - UINT32 unsupportedrequesterrormask : 1 ; - UINT32 Reserved_43 : 3 ; - UINT32 atomicopegressblockedmask : 1 ; - UINT32 uncorr_err_mask : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP2_U; - - - - -typedef union tagMeepAerCap3 -{ - - struct - { - UINT32 Reserved_50 : 1 ; - UINT32 Reserved_49 : 3 ; - UINT32 datalinkprotocolerrorsever : 1 ; - UINT32 surprisedownerrorseverity : 1 ; - UINT32 Reserved_48 : 6 ; - UINT32 poisonedtlpseverity : 1 ; - UINT32 flowcontrolprotocolerrorseveri : 1 ; - UINT32 completiontimeoutseverity : 1 ; - UINT32 completerabortseverity : 1 ; - UINT32 unexpectedcompletionseverity : 1 ; - UINT32 receiveroverflowseverity : 1 ; - UINT32 malformedtlpseverity : 1 ; - UINT32 ecrcerrorseverity : 1 ; - UINT32 unsupportedrequesterrorseverity : 1 ; - UINT32 Reserved_47 : 3 ; - UINT32 atomicopegressblockedseverity : 1 ; - UINT32 uncorr_err_ser : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP3_U; - - - - -typedef union tagMeepAerCap4 -{ - - struct - { - UINT32 receivererrorstatus : 1 ; - UINT32 Reserved_52 : 5 ; - UINT32 badtlpstatus : 1 ; - UINT32 baddllpstatus : 1 ; - UINT32 replay_numrolloverstatus : 1 ; - UINT32 Reserved_51 : 3 ; - UINT32 replytimertimeoutstatus : 1 ; - UINT32 advisorynon_fatalerrorstatus : 1 ; - UINT32 corr_err_status : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP4_U; - - - - -typedef union tagMeepAerCap5 -{ - - struct - { - UINT32 receivererrormask : 1 ; - UINT32 Reserved_54 : 5 ; - UINT32 badtlpmask : 1 ; - UINT32 baddllpmask : 1 ; - UINT32 replay_numrollovermask : 1 ; - UINT32 Reserved_53 : 3 ; - UINT32 replytimertimeoutmask : 1 ; - UINT32 advisorynon_fatalerrormask : 1 ; - UINT32 corr_err_mask : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP5_U; - - - - -typedef union tagMeepAerCap6 -{ - - struct - { - UINT32 firsterrorpointer : 5 ; - UINT32 ecrcgenerationcapability : 1 ; - UINT32 ecrcgenerationenable : 1 ; - UINT32 ecrccheckcapable : 1 ; - UINT32 ecrccheckenable : 1 ; - UINT32 adv_cap_ctrl : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP6_U; - - - - -typedef union tagMeepAerCap11 -{ - - struct - { - UINT32 correctableerrorreportingenable : 1 ; - UINT32 non_fatalerrorreportingenable : 1 ; - UINT32 fatalerrorreportingenable : 1 ; - UINT32 root_err_cmd : 29 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP11_U; - - - - -typedef union tagMeepAerCap12 -{ - - struct - { - UINT32 err_correceived : 1 ; - UINT32 multipleerr_correceived : 1 ; - UINT32 err_fatal_nonfatalreceived : 1 ; - UINT32 multipleerr_fatal_nonfatalreceived : 1 ; - UINT32 firstuncorrectablefatal : 1 ; - UINT32 non_fatalerrormessagesreceived : 1 ; - UINT32 fatalerrormessagesreceived : 1 ; - UINT32 Reserved_57 : 20 ; - UINT32 root_err_status : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP12_U; - - - - -typedef union tagMeepAerCap13 -{ - - struct - { - UINT32 err_corsourceidentification : 16 ; - UINT32 err_src_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_CAP13_U; - - - - -typedef union tagMeepVcCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 vc_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP0_U; - - - - -typedef union tagMeepVcCap1 -{ - - struct - { - UINT32 extendedvccount : 3 ; - UINT32 Reserved_60 : 1 ; - UINT32 lowpriorityextendedvccount : 3 ; - UINT32 Reserved_59 : 1 ; - UINT32 referenceclock : 2 ; - UINT32 portarbitrationtableentrysize : 2 ; - UINT32 vc_cap1 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP1_U; - - - - -typedef union tagMeepVcCap2 -{ - - struct - { - UINT32 vcarbitrationcapability : 8 ; - UINT32 Reserved_61 : 16 ; - UINT32 vc_cap2 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP2_U; - - - - -typedef union tagMeepVcCap3 -{ - - struct - { - UINT32 loadvcarbitrationtable : 1 ; - UINT32 vcarbitrationselect : 3 ; - UINT32 Reserved_63 : 12 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 Reserved_62 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP3_U; - - - - -typedef union tagMeepVcCap4 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_66 : 6 ; - UINT32 Reserved_65 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_64 : 1 ; - UINT32 vc_res_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP4_U; - - - - -typedef union tagMeepVcCap5 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_69 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselec : 3 ; - UINT32 Reserved_68 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_67 : 4 ; - UINT32 vc_res_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP5_U; - - - - -typedef union tagMeepVcCap6 -{ - - struct - { - UINT32 Reserved_70 : 16 ; - UINT32 portarbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP6_U; - - - - -typedef union tagMeepVcCap7 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_73 : 6 ; - UINT32 Reserved_72 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_71 : 1 ; - UINT32 vc_res_cap0 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP7_U; - - - - -typedef union tagMeepVcCap8 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_76 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselect : 3 ; - UINT32 Reserved_75 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_74 : 4 ; - UINT32 vc_res_ctrl0 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP8_U; - - - - -typedef union tagMeepVcCap9 -{ - - struct - { - UINT32 Reserved_77 : 16 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status0 : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_VC_CAP9_U; - - - - -typedef union tagMeepPortLogic0 -{ - - struct - { - UINT32 ack_lat_timer : 16 ; - UINT32 replay_timer : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC0_U; - - - - -typedef union tagMeepPortLogic2 -{ - - struct - { - UINT32 linknumber : 8 ; - UINT32 Reserved_80 : 7 ; - UINT32 forcelink : 1 ; - UINT32 linkstate : 6 ; - UINT32 Reserved_79 : 2 ; - UINT32 port_force_link : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC2_U; - - - - -typedef union tagMeepPortLogic3 -{ - - struct - { - UINT32 ackfrequency : 8 ; - UINT32 n_fts : 8 ; - UINT32 commonclockn_fts : 8 ; - UINT32 l0sentrancelatency : 3 ; - UINT32 l1entrancelatency : 3 ; - UINT32 enteraspml1withoutreceiveinl0s : 1 ; - UINT32 ack_aspm : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC3_U; - - - - -typedef union tagMeepPortLogic4 -{ - - struct - { - UINT32 vendorspecificdllprequest : 1 ; - UINT32 scrambledisable : 1 ; - UINT32 loopbackenable : 1 ; - UINT32 resetassert : 1 ; - UINT32 Reserved_83 : 1 ; - UINT32 dlllinkenable : 1 ; - UINT32 Reserved_82 : 1 ; - UINT32 fastlinkmode : 1 ; - UINT32 Reserved_81 : 8 ; - UINT32 linkmodeenable : 6 ; - UINT32 crosslinkenable : 1 ; - UINT32 crosslinkactive : 1 ; - UINT32 port_link_ctrl : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC4_U; - - - - -typedef union tagMeepPortLogic5 -{ - - struct - { - UINT32 insertlaneskewfortransmit : 24 ; - UINT32 flowcontroldisable : 1 ; - UINT32 ack_nakdisable : 1 ; - UINT32 Reserved_84 : 5 ; - UINT32 lane_skew : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC5_U; - - - - -typedef union tagMeepPortLogic6 -{ - - struct - { - UINT32 numberoftssymbols : 4 ; - UINT32 Reserved_86 : 4 ; - UINT32 numberofskpsymbols : 3 ; - UINT32 Reserved_85 : 3 ; - UINT32 timermodifierforreplaytimer : 5 ; - UINT32 timermodifierforack_naklatencytimer : 5 ; - UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; - UINT32 sym_num : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC6_U; - - - - -typedef union tagMeepPortLogic7 -{ - - struct - { - UINT32 vc0posteddataqueuedepth : 11 ; - UINT32 Reserved_87 : 4 ; - UINT32 sym_timer : 1 ; - UINT32 maskfunctionmismatchfilteringfo : 1 ; - UINT32 maskpoisonedtlpfiltering : 1 ; - UINT32 maskbarmatchfiltering : 1 ; - UINT32 masktype1configurationrequestfiltering : 1 ; - UINT32 masklockedrequestfiltering : 1 ; - UINT32 masktagerrorrulesforreceivedcompletions : 1 ; - UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; - UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; - UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; - UINT32 maske_crcerror_filtering : 1 ; - UINT32 maske_crcerror_filtering_forcompletions : 1 ; - UINT32 message_control : 1 ; - UINT32 maskfilteringofreceived : 1 ; - UINT32 flt_mask1 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC7_U; - - - - -typedef union tagMeepPortLogic8 -{ - - struct - { - UINT32 cx_flt_mask_venmsg0_drop : 1 ; - UINT32 cx_flt_mask_venmsg1_drop : 1 ; - UINT32 cx_flt_mask_dabort_4ucpl : 1 ; - UINT32 cx_flt_mask_handle_flush : 1 ; - UINT32 flt_mask2 : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC8_U; - - - - -typedef union tagMeepPortLogic9 -{ - - struct - { - UINT32 amba_multi_outbound_decomp_np : 1 ; - UINT32 amba_obnp_ctrl : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC9_U; - - - - -typedef union tagMeepPortLogic12 -{ - - struct - { - UINT32 transmitposteddatafccredits : 12 ; - UINT32 transmitpostedheaderfccredits : 8 ; - UINT32 tx_pfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC12_U; - - - - -typedef union tagMeepPortLogic13 -{ - - struct - { - UINT32 transmitnon_posteddatafccredits : 12 ; - UINT32 transmitnon_postedheaderfccredits : 8 ; - UINT32 tx_npfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC13_U; - - - - -typedef union tagMeepPortLogic14 -{ - - struct - { - UINT32 transmitcompletiondatafccredits : 12 ; - UINT32 transmitcompletionheaderfccredits : 8 ; - UINT32 tx_cplfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC14_U; - - - - -typedef union tagMeepPortLogic15 -{ - - struct - { - UINT32 rx_tlp_fc_credit_not_retured : 1 ; - UINT32 tx_retry_buf_not_empty : 1 ; - UINT32 rx_queue_not_empty : 1 ; - UINT32 Reserved_89 : 13 ; - UINT32 fc_latency_timer_override_value : 13 ; - UINT32 Reserved_88 : 2 ; - UINT32 fc_latency_timer_override_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC15_U; - - - - -typedef union tagMeepPortLogic16 -{ - - struct - { - UINT32 vc0posteddatacredits : 12 ; - UINT32 vc0postedheadercredits : 8 ; - UINT32 Reserved_91 : 1 ; - UINT32 vc0_postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemo : 1 ; - UINT32 Reserved_90 : 6 ; - UINT32 tlptypeorderingforvc0 : 1 ; - UINT32 rx_pque_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC16_U; - - - - -typedef union tagMeepPortLogic17 -{ - - struct - { - UINT32 vc0non_posteddatarcredits : 12 ; - UINT32 vc0non_postedheadercredits : 8 ; - UINT32 Reserved_93 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC17_U; - - - - -typedef union tagMeepPortLogic18 -{ - - struct - { - UINT32 vco_comp_data_credits : 12 ; - UINT32 vc0_cpl_header_credt : 8 ; - UINT32 Reserved_94 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC18_U; - - - - -typedef union tagMeepPortLogic19 -{ - - struct - { - UINT32 vco_posted_data_que_path : 14 ; - UINT32 Reserved_95 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 vc_pbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC19_U; - - - - -typedef union tagMeepPortLogic20 -{ - - struct - { - UINT32 vco_np_data_que_depth : 14 ; - UINT32 Reserved_97 : 2 ; - UINT32 vco_np_header_que_depth : 10 ; - UINT32 vc_npbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC20_U; - - - - -typedef union tagMeepPortLogic21 -{ - - struct - { - UINT32 vco_comp_data_queue_depth : 14 ; - UINT32 Reserved_99 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 Reserved_98 : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC21_U; - - - - -typedef union tagMeepPortLogic22 -{ - - struct - { - UINT32 n_fts : 8 ; - UINT32 pre_determ_num_of_lane : 9 ; - UINT32 det_sp_change : 1 ; - UINT32 config_phy_tx_sw : 1 ; - UINT32 config_tx_comp_rcv_bit : 1 ; - UINT32 set_emp_level : 1 ; - UINT32 Reserved_100 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORT_LOGIC22_U; - - - - -typedef union tagMeepPortlogic25 -{ - - struct - { - UINT32 remote_rd_req_size : 3 ; - UINT32 Reserved_103 : 5 ; - UINT32 remote_max_brd_tag : 8 ; - UINT32 Reserved_102 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC25_U; - - - - -typedef union tagMeepPortlogic26 -{ - - struct - { - UINT32 resize_master_resp_compser : 1 ; - UINT32 axi_ctrl1 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC26_U; - - - - -typedef union tagMeepPortlogic55 -{ - - struct - { - UINT32 iatu1_type : 5 ; - UINT32 iatu1_tc : 3 ; - UINT32 iatu1_td : 1 ; - UINT32 iatu1_attr : 2 ; - UINT32 Reserved_107 : 5 ; - UINT32 iatu1_at : 2 ; - UINT32 Reserved_106 : 2 ; - UINT32 iatu1_id : 3 ; - UINT32 Reserved_105 : 9 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC55_U; - - - - -typedef union tagMeepPortlogic56 -{ - - struct - { - UINT32 iatu2_type : 8 ; - UINT32 iatu2_bar_num : 3 ; - UINT32 Reserved_111 : 3 ; - UINT32 iatu2_tc_match_en : 1 ; - UINT32 iatu2_td_match_en : 1 ; - UINT32 iatu2_attr_match_en : 1 ; - UINT32 Reserved_110 : 1 ; - UINT32 iatu2_at_match_en : 1 ; - UINT32 iatu2_func_num_match_en : 1 ; - UINT32 iatu2_virtual_func_num_match_en : 1 ; - UINT32 message_code_match_en : 1 ; - UINT32 Reserved_109 : 2 ; - UINT32 iatu2_response_code : 2 ; - UINT32 Reserved_108 : 1 ; - UINT32 iatu2_fuzzy_type_match_mode : 1 ; - UINT32 iatu2_cfg_shift_mode : 1 ; - UINT32 iatu2_ivert_mode : 1 ; - UINT32 iatu2_match_mode : 1 ; - UINT32 iatu2_region_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC56_U; - - - - -typedef union tagMeepPortlogic57 -{ - - struct - { - UINT32 iatu_start_low : 12 ; - UINT32 iatu_start_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC57_U; - - - - -typedef union tagMeepPortlogic59 -{ - - struct - { - UINT32 iatu_limit_low : 12 ; - UINT32 iatu_limit_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC59_U; - - - - -typedef union tagMeepPortlogic60 -{ - - struct - { - UINT32 xlated_addr_high : 12 ; - UINT32 xlated_addr_low : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC60_U; - - - - -typedef union tagMeepPortlogic62 -{ - - struct - { - UINT32 dma_wr_eng_en : 1 ; - UINT32 dma_wr_ena : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC62_U; - - - - -typedef union tagMeepPortlogic63 -{ - - struct - { - UINT32 wr_doorbell_num : 3 ; - UINT32 Reserved_115 : 28 ; - UINT32 dma_wr_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC63_U; - - - - -typedef union tagMeepPortlogic64 -{ - - struct - { - UINT32 dma_read_eng_en : 1 ; - UINT32 dma_rd_ena : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC64_U; - - - - -typedef union tagMeepPortlogic65 -{ - - struct - { - UINT32 rd_doorbell_num : 3 ; - UINT32 Reserved_117 : 28 ; - UINT32 dma_rd_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC65_U; - - - - -typedef union tagMeepPortlogic66 -{ - - struct - { - UINT32 done_int_status : 1 ; - UINT32 Reserved_119 : 15 ; - UINT32 abort_int_status : 1 ; - UINT32 Reserved_118 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC66_U; - - - - -typedef union tagMeepPortlogic67 -{ - - struct - { - UINT32 done_int_mask : 1 ; - UINT32 Reserved_122 : 15 ; - UINT32 abort_int_mask : 1 ; - UINT32 Reserved_121 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC67_U; - - - - -typedef union tagMeepPortlogic68 -{ - - struct - { - UINT32 done_int_clr : 1 ; - UINT32 Reserved_125 : 15 ; - UINT32 abort_int_clr : 1 ; - UINT32 Reserved_124 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC68_U; - - - - -typedef union tagMeepPortlogic69 -{ - - struct - { - UINT32 app_rd_err_det : 1 ; - UINT32 Reserved_127 : 15 ; - UINT32 ll_element_fetch_err_det : 1 ; - UINT32 Reserved_126 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC69_U; - - - - -typedef union tagMeepPortlogic74 -{ - - struct - { - UINT32 dma_wr_c0_imwr_data : 16 ; - UINT32 dma_wr_c1_imwr_data : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC74_U; - - - - -typedef union tagMeepPortlogic75 -{ - - struct - { - UINT32 wr_ch_ll_remote_abort_int_en : 1 ; - UINT32 Reserved_129 : 15 ; - UINT32 wr_ch_ll_local_abort_int_en : 1 ; - UINT32 Reserved_128 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC75_U; - - - - -typedef union tagMeepPortlogic76 -{ - - struct - { - UINT32 done_int_status : 1 ; - UINT32 Reserved_132 : 15 ; - UINT32 abort_int_status : 1 ; - UINT32 Reserved_131 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC76_U; - - - - -typedef union tagMeepPortlogic77 -{ - - struct - { - UINT32 done_int_mask : 1 ; - UINT32 Reserved_134 : 15 ; - UINT32 abort_int_mask : 1 ; - UINT32 dma_rd_int_mask : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC77_U; - - - - -typedef union tagMeepPortlogic78 -{ - - struct - { - UINT32 done_int_clr : 1 ; - UINT32 Reserved_136 : 15 ; - UINT32 abort_int_clr : 1 ; - UINT32 dma_rd_int_clr : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC78_U; - - - - -typedef union tagMeepPortlogic79 -{ - - struct - { - UINT32 app_wr_err_det : 1 ; - UINT32 Reserved_137 : 15 ; - UINT32 link_list_fetch_err_det : 1 ; - UINT32 dma_rd_err_low : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC79_U; - - - - -typedef union tagMeepPortlogic80 -{ - - struct - { - UINT32 unspt_request : 8 ; - UINT32 completer_abort : 8 ; - UINT32 cpl_time_out : 8 ; - UINT32 data_poison : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC80_U; - - - - -typedef union tagMeepPortlogic81 -{ - - struct - { - UINT32 remote_abort_int_en : 1 ; - UINT32 Reserved_139 : 15 ; - UINT32 local_abort_int_en : 1 ; - UINT32 dma_rd_ll_err_ena : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC81_U; - - - - -typedef union tagMeepPortlogic86 -{ - - struct - { - UINT32 channel_dir : 3 ; - UINT32 Reserved_143 : 28 ; - UINT32 dma_ch_con_idx : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC86_U; - - - - -typedef union tagMeepPortlogic87 -{ - - struct - { - UINT32 cycle_bit : 1 ; - UINT32 toggle_cycle_bit : 1 ; - UINT32 load_link_pointer : 1 ; - UINT32 local_int_en : 1 ; - UINT32 remote_int_en : 1 ; - UINT32 channel_status : 2 ; - UINT32 Reserved_147 : 1 ; - UINT32 consumer_cycle_state : 1 ; - UINT32 linked_list_en : 1 ; - UINT32 Reserved_146 : 2 ; - UINT32 func_num_dma : 5 ; - UINT32 Reserved_145 : 7 ; - UINT32 no_snoop : 1 ; - UINT32 ro : 1 ; - UINT32 td : 1 ; - UINT32 tc : 3 ; - UINT32 dma_ch_ctrl : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC87_U; - - - - -typedef union tagMeepPortlogic93 -{ - - struct - { - UINT32 Reserved_150 : 2 ; - UINT32 dma_ll_ptr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PORTLOGIC93_U; - - - - -typedef union tagMeepPbar23xlatLower -{ - - struct - { - UINT32 Reserved_151 : 12 ; - UINT32 PBAR23_Xlat_Lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR23XLAT_LOWER_U; - - - - -typedef union tagMeepPbar45xlatLower -{ - - struct - { - UINT32 Reserved_153 : 12 ; - UINT32 PBAR45_Xlat_Lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR45XLAT_LOWER_U; - - - - -typedef union tagMeepPbar23lmtLower -{ - - struct - { - UINT32 Reserved_154 : 12 ; - UINT32 PBAR23_Limit_Lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR23LMT_LOWER_U; - - - - -typedef union tagMeepPbar45lmtLower -{ - - struct - { - UINT32 Reserved_155 : 12 ; - UINT32 PBAR45_Limit_Lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR45LMT_LOWER_U; - - - - -typedef union tagMeepPbar45lmtUpper -{ - - struct - { - UINT32 Reserved_156 : 12 ; - UINT32 PBAR45_Limit_Upper : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR45LMT_UPPER_U; - - - - -typedef union tagMeepB2bBar01xlatLower -{ - - struct - { - UINT32 Reserved_157 : 17 ; - UINT32 B2B_PBAR01_Xlat_Lower : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_B2B_BAR01XLAT_Lower_U; - - - - -typedef union tagMeepPpd -{ - - struct - { - UINT32 port_def : 1 ; - UINT32 Reserved_159 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PPD_U; - - - - -typedef union tagMeepDeviceVendorId -{ - - struct - { - UINT32 Vendor_ID : 16 ; - UINT32 Device_ID : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Device_Vendor_ID_U; - - - - -typedef union tagMeepPcistsPcicmd -{ - - struct - { - UINT32 io_space_enable : 1 ; - UINT32 memory_space_enable : 1 ; - UINT32 bus_master_enable : 1 ; - UINT32 specialcycleenable : 1 ; - UINT32 memory_write_and_invalidate : 1 ; - UINT32 vga_palette_snoop_enable : 1 ; - UINT32 parity_error_response : 1 ; - UINT32 idsel_stepping_waitcycle_control : 1 ; - UINT32 serr_enable : 1 ; - UINT32 fastback_to_backenable : 1 ; - UINT32 Interrupt_Disable : 1 ; - UINT32 Reserved_164 : 5 ; - UINT32 Reserved_163 : 3 ; - UINT32 intx_status : 1 ; - UINT32 capabilitieslist : 1 ; - UINT32 pcibus66mhzcapable : 1 ; - UINT32 Reserved_162 : 1 ; - UINT32 fastback_to_back : 1 ; - UINT32 masterdataparityerror : 1 ; - UINT32 devsel_timing : 2 ; - UINT32 Signaled_Target_Abort : 1 ; - UINT32 Received_Target_Abort : 1 ; - UINT32 Received_Master_Abort : 1 ; - UINT32 Signaled_System_Error : 1 ; - UINT32 Detected_Parity_Error : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCISTS_PCICMD_U; - - - - -typedef union tagMeepCcrRid -{ - - struct - { - UINT32 revision_identification : 8 ; - UINT32 Reserved_165 : 8 ; - UINT32 sub_class : 8 ; - UINT32 baseclass : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_CCR_RID_U; - - - - -typedef union tagMeepPbar01BaseLower -{ - - struct - { - UINT32 BAR01_Space_Inicator : 1 ; - UINT32 BAR01_Type : 2 ; - UINT32 BAR01_Prefetchable : 1 ; - UINT32 Reserved_166 : 13 ; - UINT32 base_address_register_01_lower : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR01_BASE_LOWER_U; - - - - -typedef union tagMeepPbar23BaseLower -{ - - struct - { - UINT32 BAR23_Space_Inicator : 1 ; - UINT32 BAR23_Type : 2 ; - UINT32 BAR23_Prefetchable : 1 ; - UINT32 Reserved_168 : 8 ; - UINT32 Base_Address_Register_23_Lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR23_BASE_LOWER_U; - - - - -typedef union tagMeepPbar45BaseLower -{ - - struct - { - UINT32 BAR45_Space_Inicator : 1 ; - UINT32 BAR45_Type : 2 ; - UINT32 BAR45_Prefetchable : 1 ; - UINT32 Reserved_169 : 8 ; - UINT32 Base_Address_Register_45_Lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PBAR45_BASE_LOWER_U; - - - - -typedef union tagMeepSubsystemid -{ - - struct - { - UINT32 SubsystemID : 16 ; - UINT32 SubsystemVendorID : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_SubSystemId_U; - - - - -typedef union tagMeepCapptr -{ - - struct - { - UINT32 CapPtr : 8 ; - UINT32 Reserved_172 : 24 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_CapPtr_U; - - - - -typedef union tagMeepInterrupt -{ - - struct - { - UINT32 Interrupt_Line : 8 ; - UINT32 interrupt_pin : 8 ; - UINT32 min_grant : 8 ; - UINT32 Max_Latency : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Interrupt_U; - - - - -typedef union tagMeepMsiCapabilityRegister -{ - - struct - { - UINT32 CapabilityID : 8 ; - UINT32 Next_Capability_Pointer : 8 ; - UINT32 MSI_Enabled : 1 ; - UINT32 Multiple_Message_Capable : 3 ; - UINT32 Multiple_Message_Enabled : 3 ; - UINT32 MSI_64_EN : 1 ; - UINT32 PVM_EN : 1 ; - UINT32 Message_Control_Register : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_Capability_Register_U; - - - - -typedef union tagMeepMsiLower32Bitaddress -{ - - struct - { - UINT32 Reserved_175 : 2 ; - UINT32 Lower32_bitAddress : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_Lower32_bitAddress_U; - - - - -typedef union tagMeepMsiData -{ - - struct - { - UINT32 MSI_Data : 16 ; - UINT32 Reserved_176 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_Data_U; - - - - -typedef union tagMeepMsiMask -{ - - struct - { - UINT32 MsiMask : 1 ; - UINT32 Reserved_177 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_MASK_U; - - - - -typedef union tagMeepMsiPending -{ - - struct - { - UINT32 MsiPending : 1 ; - UINT32 Reserved_178 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_Pending_U; - - - - -typedef union tagMeepPcieCapabilityRegister -{ - - struct - { - UINT32 Capability_ID : 8 ; - UINT32 Next_Capability_Pointer : 8 ; - UINT32 PCIE_Capability_Version : 4 ; - UINT32 Device_Port_Type : 4 ; - UINT32 Slot_Implemented : 1 ; - UINT32 Interrupt_Message_Number : 5 ; - UINT32 Reserved_179 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_PCIE_Capability_Register_U; - - - - -typedef union tagMeepDeviceCapabilitiesRegister -{ - - struct - { - UINT32 Max_Payload_Size_Supported : 3 ; - UINT32 Phantom_Function_Supported : 2 ; - UINT32 Extended_TagField_Supported : 1 ; - UINT32 Endpoint_L0sAcceptable_Latency : 3 ; - UINT32 Endpoint_L1Acceptable_Latency : 3 ; - UINT32 Undefined : 3 ; - UINT32 Reserved_182 : 3 ; - UINT32 Captured_Slot_Power_Limit_Value : 8 ; - UINT32 Captured_Slot_Power_Limit_Scale : 2 ; - UINT32 Function_Level_Reset : 1 ; - UINT32 Reserved_181 : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Device_Capabilities_Register_U; - - - - -typedef union tagMeepDeviceStatusRegister -{ - - struct - { - UINT32 Correctable_Error_Reporting_Enable : 1 ; - UINT32 Non_Fatal_Error_Reporting_Enable : 1 ; - UINT32 Fatal_Error_Reporting_Enable : 1 ; - UINT32 UREnable : 1 ; - UINT32 Enable_Relaxed_Ordering : 1 ; - UINT32 Max_Payload_Size : 3 ; - UINT32 Extended_TagFieldEnable : 1 ; - UINT32 Phantom_Function_Enable : 1 ; - UINT32 AUXPowerPMEnable : 1 ; - UINT32 EnableNoSnoop : 1 ; - UINT32 Max_Read_Request_Size : 3 ; - UINT32 Reserved_184 : 1 ; - UINT32 CorrectableErrorDetected : 1 ; - UINT32 Non_FatalErrordetected : 1 ; - UINT32 FatalErrorDetected : 1 ; - UINT32 UnsupportedRequestDetected : 1 ; - UINT32 AuxPowerDetected : 1 ; - UINT32 TransactionPending : 1 ; - UINT32 Reserved_183 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Device_Status_Register_U; - - - - -typedef union tagMeepLinkCapability -{ - - struct - { - UINT32 Max_Link_Speed : 4 ; - UINT32 Max_Link_Width : 6 ; - UINT32 Active_State_Power_Management : 2 ; - UINT32 L0s_ExitLatency : 3 ; - UINT32 L1_Exit_Latency : 3 ; - UINT32 Clock_Power_Management : 1 ; - UINT32 Surprise_Down_Error_Report_Cap : 1 ; - UINT32 Data_Link_Layer_Active_Report_Cap : 1 ; - UINT32 Link_Bandwidth_Noti_Cap : 1 ; - UINT32 ASPM_Option_Compliance : 1 ; - UINT32 Reserved_185 : 1 ; - UINT32 Port_Number : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Link_Capability_U; - - - - -typedef union tagMeepLinkControlStatus -{ - - struct - { - UINT32 active_state_power_management : 2 ; - UINT32 Reserved_188 : 1 ; - UINT32 rcb : 1 ; - UINT32 link_disable : 1 ; - UINT32 retrain_link : 1 ; - UINT32 common_clock_config : 1 ; - UINT32 extended_sync : 1 ; - UINT32 enable_clock_pwr_management : 1 ; - UINT32 hw_auto_width_disable : 1 ; - UINT32 link_bandwidth_management_int_en : 1 ; - UINT32 link_auto_bandwidth_int_en : 1 ; - UINT32 Reserved_187 : 4 ; - UINT32 current_link_speed : 4 ; - UINT32 negotiated_link_width : 6 ; - UINT32 Reserved_186 : 1 ; - UINT32 link_training : 1 ; - UINT32 slot_clock_configration : 1 ; - UINT32 data_link_layer_active : 1 ; - UINT32 link_bandwidth_management_status : 1 ; - UINT32 link_auto_bandwidth_status : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Link_Control_Status_U; - - - - -typedef union tagMeepAerCapHeader -{ - - struct - { - UINT32 PCIE_Extended_Capability_ID : 16 ; - UINT32 Capability_Version : 4 ; - UINT32 Next_Capability_Offset : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AER_Cap_header_U; - - - - -typedef union tagMeepUcErrorStatus -{ - - struct - { - UINT32 Reserved_193 : 1 ; - UINT32 Reserved_192 : 3 ; - UINT32 DataLinkProtocolErrorStatus : 1 ; - UINT32 SurpriseDownErrorStatus : 1 ; - UINT32 Reserved_191 : 6 ; - UINT32 PoisonedTLPStatus : 1 ; - UINT32 FlowControlProtocolErrorStatus : 1 ; - UINT32 CompletionTimeoutStatus : 1 ; - UINT32 CompleterAbortStatus : 1 ; - UINT32 UnexpectedCompletionStatus : 1 ; - UINT32 ReceiverOverflowStatus : 1 ; - UINT32 MalformedTLPStatus : 1 ; - UINT32 ECRCErrorStatus : 1 ; - UINT32 UnsupportedRequestErrorStatus : 1 ; - UINT32 Reserved_190 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_UC_Error_Status_U; - - - - -typedef union tagMeepUcErrorMask -{ - - struct - { - UINT32 Reserved_197 : 1 ; - UINT32 Reserved_196 : 3 ; - UINT32 DataLinkProtocolErrorMask : 1 ; - UINT32 SurpriseDownErrorMask : 1 ; - UINT32 Reserved_195 : 6 ; - UINT32 PoisonedTLPMask : 1 ; - UINT32 FlowControlProtocolErrorMask : 1 ; - UINT32 CompletionTimeoutMask : 1 ; - UINT32 CompleterAbortMask : 1 ; - UINT32 UnexpectedCompletionMask : 1 ; - UINT32 ReceiverOverflowMask : 1 ; - UINT32 MalformedTLPMask : 1 ; - UINT32 ECRCErrorMask : 1 ; - UINT32 UnsupportedRequestErrorMask : 1 ; - UINT32 Reserved_194 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_UC_Error_Mask_U; - - - - -typedef union tagMeepUcErrorSeverity -{ - - struct - { - UINT32 Reserved_201 : 1 ; - UINT32 Reserved_200 : 3 ; - UINT32 DataLinkProtocolErrorSeverity : 1 ; - UINT32 SurpriseDownErrorSeverity : 1 ; - UINT32 Reserved_199 : 6 ; - UINT32 PoisonedTLPSeverity : 1 ; - UINT32 FlowControlProtocolErrorSeverity : 1 ; - UINT32 CompletionTimeoutSeverity : 1 ; - UINT32 CompleterAbortSeverity : 1 ; - UINT32 UnexpectedCompletionSeverity : 1 ; - UINT32 ReceiverOverflowSeverity : 1 ; - UINT32 MalformedTLPSeverity : 1 ; - UINT32 ECRCErrorSeverity : 1 ; - UINT32 UnsupportedRequestErrorSeverity : 1 ; - UINT32 Reserved_198 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_UC_Error_Severity_U; - - - - -typedef union tagMeepCErrorStatus -{ - - struct - { - UINT32 Receiver_Error_Status : 1 ; - UINT32 Reserved_204 : 5 ; - UINT32 Bad_TLP_Status : 1 ; - UINT32 Bad_DLLP_Status : 1 ; - UINT32 REPLAY_NUM_Rollover_Status : 1 ; - UINT32 Reserved_203 : 3 ; - UINT32 Replay_Timer_Timeout_Status : 1 ; - UINT32 Advisory_Non_Fatal_Error_Status : 1 ; - UINT32 Reserved_202 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_C_Error_Status_U; - - - - -typedef union tagMeepCErrorMask -{ - - struct - { - UINT32 Receiver_Error_Mask : 1 ; - UINT32 Reserved_207 : 5 ; - UINT32 Bad_TLP_Mask : 1 ; - UINT32 Bad_DLLP_Mask : 1 ; - UINT32 REPLAY_NUMRollover_Mask : 1 ; - UINT32 Reserved_206 : 3 ; - UINT32 Replay_Timer_Timeout_Mask : 1 ; - UINT32 Advisory_Non_Fatal_Error_Mask : 1 ; - UINT32 Reserved_205 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_C_Error_Mask_U; - - - - -typedef union tagMeepAdvancedErrorCapabilitiesAndControl -{ - - struct - { - UINT32 First_Error_Pointer : 5 ; - UINT32 ECRC_Generation_Capability : 1 ; - UINT32 ECRC_Generation_Enable : 1 ; - UINT32 ECRC_Check_Capable : 1 ; - UINT32 ECRC_Check_Enable : 1 ; - UINT32 Reserved_209 : 2 ; - UINT32 TLP_Prefix_Log_Present : 1 ; - UINT32 Reserved_208 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_Advanced_Error_Capabilities_and_Control_U; - - - - -typedef union tagMeepNtbIepBar01Ctrl -{ - - struct - { - UINT32 bar01_type : 5 ; - UINT32 bar01_tc : 3 ; - UINT32 bar01_td : 1 ; - UINT32 bar01_attr : 2 ; - UINT32 Reserved_213 : 5 ; - UINT32 bar01_at : 2 ; - UINT32 bar01_match_en : 1 ; - UINT32 Reserved_212 : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_NTB_IEP_BAR01_CTRL_U; - - - - -typedef union tagMeepNtbIepBar23Ctrl -{ - - struct - { - UINT32 bar23_type : 5 ; - UINT32 bar23_tc : 3 ; - UINT32 bar23_td : 1 ; - UINT32 bar23_attr : 2 ; - UINT32 Reserved_215 : 5 ; - UINT32 bar23_at : 2 ; - UINT32 bar23_match_en : 1 ; - UINT32 Reserved_214 : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_NTB_IEP_BAR23_CTRL_U; - - - - -typedef union tagMeepNtbIepBar45Ctrl -{ - - struct - { - UINT32 bar45_type : 5 ; - UINT32 bar45_tc : 3 ; - UINT32 bar45_td : 1 ; - UINT32 bar45_attr : 2 ; - UINT32 Reserved_217 : 5 ; - UINT32 bar45_at : 2 ; - UINT32 bar45_match_en : 1 ; - UINT32 Reserved_216 : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_NTB_IEP_BAR45_CTRL_U; - - - - -typedef union tagMeepMsiCtrlIntEn -{ - - struct - { - UINT32 msi_int_en : 1 ; - UINT32 Reserved_218 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_CTRL_INT_EN_U; - - - - -typedef union tagMeepMsiCtrlInt0Mask -{ - - struct - { - UINT32 msi_int_mask : 1 ; - UINT32 Reserved_219 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_CTRL_INT0_MASK_U; - - - - -typedef union tagMeepMsiCtrlIntStatus -{ - - struct - { - UINT32 msi_int : 1 ; - UINT32 Reserved_220 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_MSI_CTRL_INT_STATUS_U; - - - - -typedef union tagMeepDbiRoWrEn -{ - - struct - { - UINT32 dbi_ro_wr_en : 1 ; - UINT32 Reserved_221 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_DBI_RO_WR_EN_U; - - - - -typedef union tagAxiErrResponse -{ - - struct - { - UINT32 err_resp_mode : 4 ; - UINT32 Reserved_222 : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MEEP_AXI_ERR_RESPONSE_U; - - - - - - - -#define PCIE_MIEP_PBAR23XLAT_LOWER_REG (0x0) -#define PCIE_MIEP_PBAR23XLAT_UPPER_REG (0x4) -#define PCIE_MIEP_PBAR45XLAT_LOWER_REG (0x8) -#define PCIE_MIEP_PBAR45XLAT_UPPER_REG (0xC) -#define PCIE_MIEP_PBAR23LMT_LOWER_REG (0x10) -#define PCIE_MIEP_PBAR23LMT_UPPER_REG (0x14) -#define PCIE_MIEP_PBAR45LMT_LOWER_REG (0x18) -#define PCIE_MIEP_PBAR45LMT_UPPER_REG (0x1C) -#define PCIE_MIEP_PDOORBELL_REG (0x20) -#define PCIE_MIEP_PDOORBELL_MASK_REG (0x24) -#define PCIE_MIEP_B2B_BAR01XLAT_LOWER_REG (0x28) -#define PCIE_MIEP_B2B_BAR01XLAT_UPPER_REG (0x2C) -#define PCIE_MIEP_B2BDOORBELL_REG (0x30) -#define PCIE_MIEP_SPAD0_REG (0x38) -#define PCIE_MIEP_SPAD1_REG (0x3C) -#define PCIE_MIEP_SPAD2_REG (0x40) -#define PCIE_MIEP_SPAD3_REG (0x44) -#define PCIE_MIEP_SPAD4_REG (0x48) -#define PCIE_MIEP_SPAD5_REG (0x4C) -#define PCIE_MIEP_SPAD6_REG (0x50) -#define PCIE_MIEP_SPAD7_REG (0x54) -#define PCIE_MIEP_SPAD8_REG (0x58) -#define PCIE_MIEP_SPAD9_REG (0x5C) -#define PCIE_MIEP_SPAD10_REG (0x60) -#define PCIE_MIEP_SPAD11_REG (0x64) -#define PCIE_MIEP_SPAD12_REG (0x68) -#define PCIE_MIEP_SPAD13_REG (0x6C) -#define PCIE_MIEP_SPAD14_REG (0x70) -#define PCIE_MIEP_SPAD15_REG (0x74) -#define PCIE_MIEP_SPAD16_REG (0x78) -#define PCIE_MIEP_SPAD17_REG (0x7C) -#define PCIE_MIEP_SPAD18_REG (0x80) -#define PCIE_MIEP_SPAD19_REG (0x84) -#define PCIE_MIEP_SPAD20_REG (0x88) -#define PCIE_MIEP_SPAD21_REG (0x8C) -#define PCIE_MIEP_SPAD22_REG (0x90) -#define PCIE_MIEP_SPAD23_REG (0x94) -#define PCIE_MIEP_SPAD24_REG (0x98) -#define PCIE_MIEP_SPAD25_REG (0x9C) -#define PCIE_MIEP_SPAD26_REG (0xA0) -#define PCIE_MIEP_SPAD27_REG (0xA4) -#define PCIE_MIEP_SPAD28_REG (0xA8) -#define PCIE_MIEP_SPAD29_REG (0xAC) -#define PCIE_MIEP_SPAD30_REG (0xB0) -#define PCIE_MIEP_SPAD31_REG (0xB4) -#define PCIE_MIEP_B2BSPAD0_REG (0xB8) -#define PCIE_MIEP_B2BSPAD1_REG (0xBC) -#define PCIE_MIEP_B2BSPAD2_REG (0xC0) -#define PCIE_MIEP_B2BSPAD3_REG (0xC4) -#define PCIE_MIEP_B2BSPAD4_REG (0xC8) -#define PCIE_MIEP_B2BSPAD5_REG (0xCC) -#define PCIE_MIEP_B2BSPAD6_REG (0xD0) -#define PCIE_MIEP_B2BSPAD7_REG (0xD4) -#define PCIE_MIEP_B2BSPAD8_REG (0xD8) -#define PCIE_MIEP_B2BSPAD9_REG (0xDC) -#define PCIE_MIEP_B2BSPAD10_REG (0xE0) -#define PCIE_MIEP_B2BSPAD11_REG (0xE4) -#define PCIE_MIEP_B2BSPAD12_REG (0xE8) -#define PCIE_MIEP_B2BSPAD13_REG (0xEC) -#define PCIE_MIEP_B2BSPAD14_REG (0xF0) -#define PCIE_MIEP_B2BSPAD15_REG (0xF4) -#define PCIE_MIEP_B2BSPAD16_REG (0xF8) -#define PCIE_MIEP_B2BSPAD17_REG (0xFC) -#define PCIE_MIEP_B2BSPAD18_REG (0x100) -#define PCIE_MIEP_B2BSPAD19_REG (0x104) -#define PCIE_MIEP_B2BSPAD20_REG (0x108) -#define PCIE_MIEP_B2BSPAD21_REG (0x10C) -#define PCIE_MIEP_B2BSPAD22_REG (0x110) -#define PCIE_MIEP_B2BSPAD23_REG (0x114) -#define PCIE_MIEP_B2BSPAD24_REG (0x118) -#define PCIE_MIEP_B2BSPAD25_REG (0x11C) -#define PCIE_MIEP_B2BSPAD26_REG (0x120) -#define PCIE_MIEP_B2BSPAD27_REG (0x124) -#define PCIE_MIEP_B2BSPAD28_REG (0x128) -#define PCIE_MIEP_B2BSPAD29_REG (0x12C) -#define PCIE_MIEP_B2BSPAD30_REG (0x130) -#define PCIE_MIEP_B2BSPAD31_REG (0x134) -#define PCIE_MIEP_PPD_REG (0x138) -#define PCIE_MIEP_P_DEVICE_VENDOR_ID_REG (0x1000) -#define PCIE_MIEP_P_PCISTS_PCICMD_REG (0x1004) -#define PCIE_MIEP_P_CCR_RID_REG (0x1008) -#define PCIE_MIEP_P_BIST_TYPE_REG (0x100C) -#define PCIE_MIEP_PBAR01_BASE_LOWER_REG (0x1010) -#define PCIE_MIEP_PBAR01_BASE_UPPER_REG (0x1014) -#define PCIE_MIEP_PBAR23_BASE_LOWER_REG (0x1018) -#define PCIE_MIEP_PBAR23_BASE_UPPER_REG (0x101C) -#define PCIE_MIEP_PBAR45_BASE_LOWER_REG (0x1020) -#define PCIE_MIEP_PBAR45_BASE_UPPER_REG (0x1024) -#define PCIE_MIEP_P_SUBSYSTEMID_REG (0x102C) -#define PCIE_MIEP_P_INTERRUPT_REG (0x103C) -#define PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_REG (0x1054) -#define PCIE_MIEP_P_MSI_UPPER32_BIT_ADDRESS_REG (0x1058) -#define PCIE_MIEP_P_LINK_CAPABILITY_REG (0x107C) -#define PCIE_MIEP_P_AER_CAP_HEADER_REG (0x1100) -#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_1_REG (0x111C) -#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_2_REG (0x1120) -#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_3_REG (0x1124) -#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_4_REG (0x1128) -#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_1_REG (0x1130) -#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_2_REG (0x1134) -#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_3_REG (0x1138) -#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_4_REG (0x113C) -#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x1700) -#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x1704) -#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_LOWER_REG (0x1714) -#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_UPPER_REG (0x1718) -#define PCIE_MIEP_SBAR23XLAT_LOWER_REG (0x8000) -#define PCIE_MIEP_SBAR23XLAT_UPPER_REG (0x8004) -#define PCIE_MIEP_SBAR45XLAT_LOWER_REG (0x8008) -#define PCIE_MIEP_SBAR45XLAT_UPPER_REG (0x800C) -#define PCIE_MIEP_SBAR23LMT_LOWER_REG (0x8010) -#define PCIE_MIEP_SBAR23LMT_UPPER_REG (0x8014) -#define PCIE_MIEP_SBAR45LMT_LOWER_REG (0x8018) -#define PCIE_MIEP_SBAR45LMT_UPPER_REG (0x801C) -#define PCIE_MIEP_SDOORBELL_REG (0x8020) -#define PCIE_MIEP_SDOORBELL_MASK_REG (0x8024) -#define PCIE_MIEP_CBDF_SBDF_REG (0x8028) -#define PCIE_MIEP_PCI_CFG_HDR0_REG (0x9000) -#define PCIE_MIEP_PCI_CFG_HDR1_REG (0x9004) -#define PCIE_MIEP_PCI_CFG_HDR9_REG (0x9024) -#define PCIE_MIEP_PCI_CFG_HDR10_REG (0x9028) -#define PCIE_MIEP_PCI_CFG_HDR11_REG (0x902C) -#define PCIE_MIEP_PCI_CFG_HDR12_REG (0x9030) -#define PCIE_MIEP_PCI_CFG_HDR13_REG (0x9034) -#define PCIE_MIEP_PCI_CFG_HDR14_REG (0x9038) -#define PCIE_MIEP_PCI_CFG_HDR15_REG (0x903C) -#define PCIE_MIEP_PCI_PM_CAP0_REG (0x9040) -#define PCIE_MIEP_PCI_PM_CAP1_REG (0x9044) -#define PCIE_MIEP_PCI_MSI_CAP0_REG (0x9050) -#define PCIE_MIEP_PCI_MSI_CAP1_REG (0x9054) -#define PCIE_MIEP_PCI_MSI_CAP2_REG (0x9058) -#define PCIE_MIEP_PCI_MSI_CAP3_REG (0x905C) -#define PCIE_MIEP_PCIE_CAP0_REG (0x9070) -#define PCIE_MIEP_PCIE_CAP1_REG (0x9074) -#define PCIE_MIEP_PCIE_CAP2_REG (0x9078) -#define PCIE_MIEP_PCIE_CAP3_REG (0x907C) -#define PCIE_MIEP_PCIE_CAP4_REG (0x9080) -#define PCIE_MIEP_PCIE_CAP5_REG (0x9084) -#define PCIE_MIEP_PCIE_CAP6_REG (0x9088) -#define PCIE_MIEP_PCIE_CAP7_REG (0x908C) -#define PCIE_MIEP_PCIE_CAP8_REG (0x9090) -#define PCIE_MIEP_PCIE_CAP9_REG (0x9094) -#define PCIE_MIEP_PCIE_CAP10_REG (0x9098) -#define PCIE_MIEP_PCIE_CAP11_REG (0x909C) -#define PCIE_MIEP_PCIE_CAP12_REG (0x90A0) -#define PCIE_MIEP_SLOT_CAP_REG (0x90C0) -#define PCIE_MIEP_AER_CAP0_REG (0x9100) -#define PCIE_MIEP_AER_CAP1_REG (0x9104) -#define PCIE_MIEP_AER_CAP2_REG (0x9108) -#define PCIE_MIEP_AER_CAP3_REG (0x910C) -#define PCIE_MIEP_AER_CAP4_REG (0x9110) -#define PCIE_MIEP_AER_CAP5_REG (0x9114) -#define PCIE_MIEP_AER_CAP6_REG (0x9118) -#define PCIE_MIEP_AER_CAP7_REG (0x911C) -#define PCIE_MIEP_AER_CAP8_REG (0x9120) -#define PCIE_MIEP_AER_CAP9_REG (0x9124) -#define PCIE_MIEP_AER_CAP10_REG (0x9128) -#define PCIE_MIEP_AER_CAP11_REG (0x912C) -#define PCIE_MIEP_AER_CAP12_REG (0x9130) -#define PCIE_MIEP_AER_CAP13_REG (0x9134) -#define PCIE_MIEP_VC_CAP0_REG (0x9140) -#define PCIE_MIEP_VC_CAP1_REG (0x9144) -#define PCIE_MIEP_VC_CAP2_REG (0x9148) -#define PCIE_MIEP_VC_CAP3_REG (0x914C) -#define PCIE_MIEP_VC_CAP4_REG (0x9150) -#define PCIE_MIEP_VC_CAP5_REG (0x9154) -#define PCIE_MIEP_VC_CAP6_REG (0x9158) -#define PCIE_MIEP_VC_CAP7_REG (0x915C) -#define PCIE_MIEP_VC_CAP8_REG (0x9160) -#define PCIE_MIEP_VC_CAP9_REG (0x9164) -#define PCIE_MIEP_PORT_LOGIC0_REG (0x9700) -#define PCIE_MIEP_PORT_LOGIC1_REG (0x9704) -#define PCIE_MIEP_PORT_LOGIC2_REG (0x9708) -#define PCIE_MIEP_PORT_LOGIC3_REG (0x970C) -#define PCIE_MIEP_PORT_LOGIC4_REG (0x9710) -#define PCIE_MIEP_PORT_LOGIC5_REG (0x9714) -#define PCIE_MIEP_PORT_LOGIC6_REG (0x9718) -#define PCIE_MIEP_PORT_LOGIC7_REG (0x971C) -#define PCIE_MIEP_PORT_LOGIC8_REG (0x9720) -#define PCIE_MIEP_PORT_LOGIC9_REG (0x9724) -#define PCIE_MIEP_PORT_LOGIC10_REG (0x9728) -#define PCIE_MIEP_PORT_LOGIC11_REG (0x972C) -#define PCIE_MIEP_PORT_LOGIC12_REG (0x9730) -#define PCIE_MIEP_PORT_LOGIC13_REG (0x9734) -#define PCIE_MIEP_PORT_LOGIC14_REG (0x9738) -#define PCIE_MIEP_PORT_LOGIC15_REG (0x973C) -#define PCIE_MIEP_PORT_LOGIC16_REG (0x9748) -#define PCIE_MIEP_PORT_LOGIC17_REG (0x974C) -#define PCIE_MIEP_PORT_LOGIC18_REG (0x9750) -#define PCIE_MIEP_PORT_LOGIC19_REG (0x97A8) -#define PCIE_MIEP_PORT_LOGIC20_REG (0x97AC) -#define PCIE_MIEP_PORT_LOGIC21_REG (0x97B0) -#define PCIE_MIEP_PORT_LOGIC22_REG (0x980C) -#define PCIE_MIEP_PORTLOGIC23_REG (0x9810) -#define PCIE_MIEP_PORTLOGIC24_REG (0x9814) -#define PCIE_MIEP_PORTLOGIC25_REG (0x9818) -#define PCIE_MIEP_PORTLOGIC26_REG (0x981C) -#define PCIE_MIEP_PORTLOGIC27_REG (0x9820) -#define PCIE_MIEP_PORTLOGIC28_REG (0x9824) -#define PCIE_MIEP_PORTLOGIC29_REG (0x9828) -#define PCIE_MIEP_PORTLOGIC30_REG (0x982C) -#define PCIE_MIEP_PORTLOGIC31_REG (0x9830) -#define PCIE_MIEP_PORTLOGIC32_REG (0x9834) -#define PCIE_MIEP_PORTLOGIC33_REG (0x9838) -#define PCIE_MIEP_PORTLOGIC34_REG (0x983C) -#define PCIE_MIEP_PORTLOGIC35_REG (0x9840) -#define PCIE_MIEP_PORTLOGIC36_REG (0x9844) -#define PCIE_MIEP_PORTLOGIC37_REG (0x9848) -#define PCIE_MIEP_PORTLOGIC38_REG (0x984C) -#define PCIE_MIEP_PORTLOGIC39_REG (0x9850) -#define PCIE_MIEP_PORTLOGIC40_REG (0x9854) -#define PCIE_MIEP_PORTLOGIC41_REG (0x9858) -#define PCIE_MIEP_PORTLOGIC42_REG (0x985C) -#define PCIE_MIEP_PORTLOGIC43_REG (0x9860) -#define PCIE_MIEP_PORTLOGIC44_REG (0x9864) -#define PCIE_MIEP_PORTLOGIC45_REG (0x9868) -#define PCIE_MIEP_PORTLOGIC46_REG (0x986C) -#define PCIE_MIEP_PORTLOGIC47_REG (0x9870) -#define PCIE_MIEP_PORTLOGIC48_REG (0x9874) -#define PCIE_MIEP_PORTLOGIC49_REG (0x9878) -#define PCIE_MIEP_PORTLOGIC50_REG (0x987C) -#define PCIE_MIEP_PORTLOGIC51_REG (0x9880) -#define PCIE_MIEP_PORTLOGIC52_REG (0x9884) -#define PCIE_MIEP_PORTLOGIC53_REG (0x9888) -#define PCIE_MIEP_PORTLOGIC54_REG (0x9900) -#define PCIE_MIEP_PORTLOGIC55_REG (0x9904) -#define PCIE_MIEP_PORTLOGIC56_REG (0x9908) -#define PCIE_MIEP_PORTLOGIC57_REG (0x990C) -#define PCIE_MIEP_PORTLOGIC58_REG (0x9910) -#define PCIE_MIEP_PORTLOGIC59_REG (0x9914) -#define PCIE_MIEP_PORTLOGIC60_REG (0x9918) -#define PCIE_MIEP_PORTLOGIC61_REG (0x991C) -#define PCIE_MIEP_PORTLOGIC62_REG (0x997C) -#define PCIE_MIEP_PORTLOGIC63_REG (0x9980) -#define PCIE_MIEP_PORTLOGIC64_REG (0x999C) -#define PCIE_MIEP_PORTLOGIC65_REG (0x99A0) -#define PCIE_MIEP_PORTLOGIC66_REG (0x99BC) -#define PCIE_MIEP_PORTLOGIC67_REG (0x99C4) -#define PCIE_MIEP_PORTLOGIC68_REG (0x99C8) -#define PCIE_MIEP_PORTLOGIC69_REG (0x99CC) -#define PCIE_MIEP_PORTLOGIC70_REG (0x99D0) -#define PCIE_MIEP_PORTLOGIC71_REG (0x99D4) -#define PCIE_MIEP_PORTLOGIC72_REG (0x99D8) -#define PCIE_MIEP_PORTLOGIC73_REG (0x99DC) -#define PCIE_MIEP_PORTLOGIC74_REG (0x99E0) -#define PCIE_MIEP_PORTLOGIC75_REG (0x9A00) -#define PCIE_MIEP_PORTLOGIC76_REG (0x9A10) -#define PCIE_MIEP_PORTLOGIC77_REG (0x9A18) -#define PCIE_MIEP_PORTLOGIC78_REG (0x9A1C) -#define PCIE_MIEP_PORTLOGIC79_REG (0x9A24) -#define PCIE_MIEP_PORTLOGIC80_REG (0x9A28) -#define PCIE_MIEP_PORTLOGIC81_REG (0x9A34) -#define PCIE_MIEP_PORTLOGIC82_REG (0x9A3C) -#define PCIE_MIEP_PORTLOGIC83_REG (0x9A40) -#define PCIE_MIEP_PORTLOGIC84_REG (0x9A44) -#define PCIE_MIEP_PORTLOGIC85_REG (0x9A48) -#define PCIE_MIEP_PORTLOGIC86_REG (0x9A6C) -#define PCIE_MIEP_PORTLOGIC87_REG (0x9A70) -#define PCIE_MIEP_PORTLOGIC88_REG (0x9A78) -#define PCIE_MIEP_PORTLOGIC89_REG (0x9A7C) -#define PCIE_MIEP_PORTLOGIC90_REG (0x9A80) -#define PCIE_MIEP_PORTLOGIC91_REG (0x9A84) -#define PCIE_MIEP_PORTLOGIC92_REG (0x9A88) -#define PCIE_MIEP_PORTLOGIC93_REG (0x9A8C) -#define PCIE_MIEP_PORTLOGIC94_REG (0x9A90) - - - - -typedef union tagMiepPbar23xlatLower -{ - - struct - { - UINT32 Reserved_0 : 12 ; - UINT32 pbar23_xlat_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR23XLAT_LOWER_U; - - - - -typedef union tagMiepPbar45xlatLower -{ - - struct - { - UINT32 Reserved_1 : 12 ; - UINT32 pbar45_xlat_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR45XLAT_LOWER_U; - - - - -typedef union tagMiepPbar23lmtLower -{ - - struct - { - UINT32 Reserved_2 : 12 ; - UINT32 pbar23_limit_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR23LMT_LOWER_U; - - - - -typedef union tagMiepPbar45lmtLower -{ - - struct - { - UINT32 Reserved_3 : 12 ; - UINT32 pbar45_limit_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR45LMT_LOWER_U; - - - - -typedef union tagMiepB2bBar01xlatLower -{ - - struct - { - UINT32 Reserved_4 : 17 ; - UINT32 b2b_pbar01_xlat_lower : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_B2B_BAR01XLAT_LOWER_U; - - - - -typedef union tagMiepPpd -{ - - struct - { - UINT32 port_def : 1 ; - UINT32 Reserved_6 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PPD_U; - - - - -typedef union tagMiepPDeviceVendorId -{ - - struct - { - UINT32 vendor_id : 16 ; - UINT32 device_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_DEVICE_VENDOR_ID_U; - - - - -typedef union tagMiepPPcistsPcicmd -{ - - struct - { - UINT32 io_space_enable : 1 ; - UINT32 memory_space_enable : 1 ; - UINT32 bus_master_enable : 1 ; - UINT32 specialcycleenable : 1 ; - UINT32 memory_write_and_invalidate : 1 ; - UINT32 vga_palette_snoop_enable : 1 ; - UINT32 parity_error_response : 1 ; - UINT32 idsel_stepping_waitcycle_control : 1 ; - UINT32 serr_enable : 1 ; - UINT32 fastback_to_backenable : 1 ; - UINT32 interrupt_disable : 1 ; - UINT32 Reserved_10 : 5 ; - UINT32 Reserved_9 : 3 ; - UINT32 intx_status : 1 ; - UINT32 capabilitieslist : 1 ; - UINT32 pcibus66mhzcapable : 1 ; - UINT32 Reserved_8 : 1 ; - UINT32 fastback_to_back : 1 ; - UINT32 masterdataparityerror : 1 ; - UINT32 devsel_timing : 2 ; - UINT32 signaled_target_abort : 1 ; - UINT32 received_target_abort : 1 ; - UINT32 received_master_abort : 1 ; - UINT32 signaled_system_error : 1 ; - UINT32 detected_parity_error : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_PCISTS_PCICMD_U; - - - - -typedef union tagMiepPCcrRid -{ - - struct - { - UINT32 revision_id : 8 ; - UINT32 Reserved_11 : 8 ; - UINT32 cfg_sub_class : 8 ; - UINT32 cfg_base_class : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_CCR_RID_U; - - - - -typedef union tagMiepPBistType -{ - - struct - { - UINT32 cache_line_size : 8 ; - UINT32 primary_latency_timer : 8 ; - UINT32 cfg_hdr_type : 8 ; - UINT32 bist : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_BIST_TYPE_U; - - - - -typedef union tagMiepPbar01BaseLower -{ - - struct - { - UINT32 cfg_iep_bar0_io : 1 ; - UINT32 cfg_iep_bar0_type : 2 ; - UINT32 cfg_iep_bar0_pref : 1 ; - UINT32 Reserved_12 : 13 ; - UINT32 bar0_low : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR01_BASE_LOWER_U; - - - - -typedef union tagMiepPbar23BaseLower -{ - - struct - { - UINT32 cfg_iep_bar2_io : 1 ; - UINT32 cfg_iep_bar2_type : 2 ; - UINT32 cfg_iep_bar2_pref : 1 ; - UINT32 Reserved_13 : 8 ; - UINT32 bar2_low : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR23_BASE_LOWER_U; - - - - -typedef union tagMiepPbar45BaseLower -{ - - struct - { - UINT32 cfg_iep_bar4_io : 1 ; - UINT32 cfg_iep_bar4_type : 2 ; - UINT32 cfg_iep_bar4_pref : 1 ; - UINT32 Reserved_14 : 8 ; - UINT32 bar4_low : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PBAR45_BASE_LOWER_U; - - - - -typedef union tagMiepPSubsystemid -{ - - struct - { - UINT32 subsystem_device_id : 16 ; - UINT32 subsystem_vendor_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_SUBSYSTEMID_U; - - - - -typedef union tagMiepPInterrupt -{ - - struct - { - UINT32 int_line_reg : 8 ; - UINT32 cfg_int_pin : 8 ; - UINT32 min_gnt : 8 ; - UINT32 max_lat : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_INTERRUPT_U; - - - - -typedef union tagMiepPMsiLower32Bitaddress -{ - - struct - { - UINT32 Reserved_17 : 2 ; - UINT32 iep_msi_addr_low32 : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_U; - - - - -typedef union tagMiepPLinkCapability -{ - - struct - { - UINT32 cfg_pcie_max_link_speed : 4 ; - UINT32 cfg_pcie_max_link_width : 6 ; - UINT32 active_state_power_management : 2 ; - UINT32 l0s_exit_latency : 3 ; - UINT32 l1_exit_latency : 3 ; - UINT32 clock_power_management : 1 ; - UINT32 surprise_down_error_report_cap : 1 ; - UINT32 data_link_layer_active_report_cap : 1 ; - UINT32 link_bandwidth_noti_cap : 1 ; - UINT32 aspm_option_compliance : 1 ; - UINT32 Reserved_19 : 1 ; - UINT32 cfg_pcie_port_num : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_LINK_CAPABILITY_U; - - - - -typedef union tagMiepPAerCapHeader -{ - - struct - { - UINT32 PCIE_Extended_Capability_ID : 16 ; - UINT32 Capability_Version : 4 ; - UINT32 Next_Capability_Offset : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_P_AER_CAP_HEADER_U; - - - - -typedef union tagMiepSbar23xlatLower -{ - - struct - { - UINT32 Reserved_26 : 12 ; - UINT32 sbar23_xlat_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_SBAR23XLAT_LOWER_U; - - - - -typedef union tagMiepSbar45xlatLower -{ - - struct - { - UINT32 Reserved_28 : 12 ; - UINT32 sbar45_xlat_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_SBAR45XLAT_LOWER_U; - - - - -typedef union tagMiepSbar23lmtLower -{ - - struct - { - UINT32 Reserved_29 : 12 ; - UINT32 sbar23_limit_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_SBAR23LMT_LOWER_U; - - - - -typedef union tagMiepSbar45lmtLower -{ - - struct - { - UINT32 Reserved_30 : 12 ; - UINT32 sbar45_limit_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_SBAR45LMT_LOWER_U; - - - - -typedef union tagMiepSbar45lmtUpper -{ - - struct - { - UINT32 Reserved_31 : 12 ; - UINT32 sbar45_limit_upper : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_SBAR45LMT_UPPER_U; - - - - -typedef union tagMiepCbdfSbdf -{ - - struct - { - UINT32 sfunc : 3 ; - UINT32 sdev : 5 ; - UINT32 sbus : 8 ; - UINT32 cap_sfunc_num : 3 ; - UINT32 cap_sdev_num : 5 ; - UINT32 cap_sbus_num : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_CBDF_SBDF_U; - - - - -typedef union tagMiepPciCfgHdr0 -{ - - struct - { - UINT32 vendor_id : 16 ; - UINT32 device_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_CFG_HDR0_U; - - - - -typedef union tagMiepPciCfgHdr1 -{ - - struct - { - UINT32 io_space_enable : 1 ; - UINT32 memory_space_enable : 1 ; - UINT32 bus_master_enable : 1 ; - UINT32 specialcycleenable : 1 ; - UINT32 memory_write_and_invalidate : 1 ; - UINT32 vga_palette_snoop_enable : 1 ; - UINT32 parity_error_response : 1 ; - UINT32 idsel_stepping_waitcycle_control : 1 ; - UINT32 serr_enable : 1 ; - UINT32 fastback_to_backenable : 1 ; - UINT32 interrupt_disable : 1 ; - UINT32 Reserved_35 : 5 ; - UINT32 Reserved_34 : 3 ; - UINT32 intx_status : 1 ; - UINT32 capabilitieslist : 1 ; - UINT32 pcibus66mhzcapable : 1 ; - UINT32 Reserved_33 : 1 ; - UINT32 fastback_to_back : 1 ; - UINT32 masterdataparityerror : 1 ; - UINT32 devsel_timing : 2 ; - UINT32 signaled_target_abort : 1 ; - UINT32 received_target_abort : 1 ; - UINT32 received_master_abort : 1 ; - UINT32 signaled_system_error : 1 ; - UINT32 detected_perr : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_CFG_HDR1_U; - - - - -typedef union tagMiepPciCfgHdr11 -{ - - struct - { - UINT32 subsystem_vendor_id : 16 ; - UINT32 subsystemid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_CFG_HDR11_U; - - - - -typedef union tagMiepPciCfgHdr13 -{ - - struct - { - UINT32 capptr : 8 ; - UINT32 Reserved_37 : 24 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_CFG_HDR13_U; - - - - -typedef union tagMiepPciCfgHdr15 -{ - - struct - { - UINT32 int_line : 8 ; - UINT32 int_pin : 8 ; - UINT32 min_grant : 8 ; - UINT32 max_latency : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_CFG_HDR15_U; - - - - -typedef union tagMiepPciMsiCap0 -{ - - struct - { - UINT32 msi_cap_id : 8 ; - UINT32 next_capability_pointer : 8 ; - UINT32 msi_enabled : 1 ; - UINT32 multiple_message_capable : 3 ; - UINT32 multiple_message_enabled : 3 ; - UINT32 msi_64_en : 1 ; - UINT32 pvm_en : 1 ; - UINT32 message_control_register : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_MSI_CAP0_U; - - - - -typedef union tagMiepPciMsiCap1 -{ - - struct - { - UINT32 Reserved_42 : 2 ; - UINT32 msi_addr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_MSI_CAP1_U; - - - - -typedef union tagMiepPciMsiCap3 -{ - - struct - { - UINT32 msi_data : 16 ; - UINT32 Reserved_43 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCI_MSI_CAP3_U; - - - - -typedef union tagMiepPcieCap0 -{ - - struct - { - UINT32 pcie_cap_id : 8 ; - UINT32 pcie_next_ptr : 8 ; - UINT32 pcie_capability_version : 4 ; - UINT32 device_port_type : 4 ; - UINT32 slot_implemented : 1 ; - UINT32 interrupt_message_number : 5 ; - UINT32 Reserved_44 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP0_U; - - - - -typedef union tagMiepPcieCap1 -{ - - struct - { - UINT32 max_payload_size_supported : 3 ; - UINT32 phantom_function_supported : 2 ; - UINT32 extended_tagfield_supported : 1 ; - UINT32 endpoint_l0sacceptable_latency : 3 ; - UINT32 endpoint_l1acceptable_latency : 3 ; - UINT32 undefined : 3 ; - UINT32 Reserved_47 : 3 ; - UINT32 captured_slot_power_limit_value : 8 ; - UINT32 captured_slot_power_limit_scale : 2 ; - UINT32 function_level_reset : 1 ; - UINT32 Reserved_46 : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP1_U; - - - - -typedef union tagMiepPcieCap2 -{ - - struct - { - UINT32 correctable_error_reporting_enable : 1 ; - UINT32 non_fatal_error_reporting_enable : 1 ; - UINT32 fatal_error_reporting_enable : 1 ; - UINT32 urenable : 1 ; - UINT32 enable_relaxed_ordering : 1 ; - UINT32 max_payload_size : 3 ; - UINT32 extended_tagfieldenable : 1 ; - UINT32 phantom_function_enable : 1 ; - UINT32 auxpowerpmenable : 1 ; - UINT32 enablenosnoop : 1 ; - UINT32 max_read_request_size : 3 ; - UINT32 Reserved_49 : 1 ; - UINT32 correctableerrordetected : 1 ; - UINT32 non_fatalerrordetected : 1 ; - UINT32 fatalerrordetected : 1 ; - UINT32 unsupportedrequestdetected : 1 ; - UINT32 auxpowerdetected : 1 ; - UINT32 transactionpending : 1 ; - UINT32 Reserved_48 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP2_U; - - - - -typedef union tagMiepPcieCap3 -{ - - struct - { - UINT32 max_link_speed : 4 ; - UINT32 max_link_width : 6 ; - UINT32 active_state_power_management : 2 ; - UINT32 l0s_exitlatency : 3 ; - UINT32 l1_exit_latency : 3 ; - UINT32 clock_power_management : 1 ; - UINT32 surprise_down_error_report_cap : 1 ; - UINT32 data_link_layer_active_report_cap : 1 ; - UINT32 link_bandwidth_noti_cap : 1 ; - UINT32 aspm_option_compliance : 1 ; - UINT32 Reserved_50 : 1 ; - UINT32 port_number : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP3_U; - - - - -typedef union tagMiepPcieCap4 -{ - - struct - { - UINT32 active_state_power_management : 2 ; - UINT32 Reserved_53 : 1 ; - UINT32 rcb : 1 ; - UINT32 link_disable : 1 ; - UINT32 retrain_link : 1 ; - UINT32 common_clock_config : 1 ; - UINT32 extended_sync : 1 ; - UINT32 enable_clock_pwr_management : 1 ; - UINT32 hw_auto_width_disable : 1 ; - UINT32 link_bandwidth_management_int_en : 1 ; - UINT32 link_auto_bandwidth_int_en : 1 ; - UINT32 Reserved_52 : 4 ; - UINT32 current_link_speed : 4 ; - UINT32 negotiated_link_width : 6 ; - UINT32 Reserved_51 : 1 ; - UINT32 link_training : 1 ; - UINT32 slot_clock_configration : 1 ; - UINT32 data_link_layer_active : 1 ; - UINT32 link_bandwidth_management_status : 1 ; - UINT32 link_auto_bandwidth_status : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP4_U; - - - - -typedef union tagMiepPcieCap5 -{ - - struct - { - UINT32 attentioonbuttonpresent : 1 ; - UINT32 powercontrollerpresent : 1 ; - UINT32 mrlsensorpresent : 1 ; - UINT32 attentionindicatorpresent : 1 ; - UINT32 powerindicatorpresent : 1 ; - UINT32 hot_plugsurprise : 1 ; - UINT32 hot_plugcapable : 1 ; - UINT32 slotpowerlimitvalue : 8 ; - UINT32 slotpowerlimitscale : 2 ; - UINT32 electromechanicalinterlockpresen : 1 ; - UINT32 no_cmd_complete_support : 1 ; - UINT32 phy_slot_number : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP5_U; - - - - -typedef union tagMiepPcieCap6 -{ - - struct - { - UINT32 attentionbuttonpressedenable : 1 ; - UINT32 powerfaultdetectedenable : 1 ; - UINT32 mrlsensorchangedenable : 1 ; - UINT32 presencedetectchangedenable : 1 ; - UINT32 commandcompletedinterruptenable : 1 ; - UINT32 hot_pluginterruptenable : 1 ; - UINT32 attentionindicatorcontrol : 2 ; - UINT32 powerindicatorcontrol : 2 ; - UINT32 powercontrollercontrol : 1 ; - UINT32 electromechanicalinterlockcontrol : 1 ; - UINT32 datalinklayerstatechangedenable : 1 ; - UINT32 Reserved_54 : 3 ; - UINT32 attentionbuttonpressed : 1 ; - UINT32 powerfaultdetected : 1 ; - UINT32 mrlsensorchanged : 1 ; - UINT32 presencedetectchanged : 1 ; - UINT32 commandcompleted : 1 ; - UINT32 mrlsensorstate : 1 ; - UINT32 presencedetectstate : 1 ; - UINT32 electromechanicalinterlockstatus : 1 ; - UINT32 datalinklayerstatechanged : 1 ; - UINT32 slot_ctrl_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP6_U; - - - - -typedef union tagMiepPcieCap7 -{ - - struct - { - UINT32 systemerroroncorrectableerrorenable : 1 ; - UINT32 systemerroronnon_fatalerrorenable : 1 ; - UINT32 systemerroronfatalerrorenable : 1 ; - UINT32 pmeinterruptenable : 1 ; - UINT32 crssoftwarevisibilityenable : 1 ; - UINT32 Reserved_55 : 11 ; - UINT32 crssoftwarevisibility : 1 ; - UINT32 root_cap : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP7_U; - - - - -typedef union tagMiepPcieCap8 -{ - - struct - { - UINT32 pmerequesterid : 16 ; - UINT32 pmestatus : 1 ; - UINT32 pmepending : 1 ; - UINT32 root_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP8_U; - - - - -typedef union tagMiepPcieCap9 -{ - - struct - { - UINT32 completiontimeoutrangessupported : 4 ; - UINT32 completiontimeoutdisablesupported : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoproutingsupported : 1 ; - UINT32 _2_bitatomicopcompletersupported : 1 ; - UINT32 _4_bitatomicopcompletersupported : 1 ; - UINT32 _28_bitcascompletersupported : 1 ; - UINT32 noro_enabledpr_prpassing : 1 ; - UINT32 Reserved_56 : 1 ; - UINT32 tphcompletersupported : 2 ; - UINT32 dev_cap2 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP9_U; - - - - -typedef union tagMiepPcieCap10 -{ - - struct - { - UINT32 completiontimeoutvalue : 4 ; - UINT32 completiontimeoutdisable : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoprequesterenable : 1 ; - UINT32 atomicopegressblocking : 1 ; - UINT32 idorequestenable : 1 ; - UINT32 idocompletionenable : 1 ; - UINT32 dev_ctrl2 : 22 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP10_U; - - - - -typedef union tagMiepPcieCap11 -{ - - struct - { - UINT32 Reserved_58 : 1 ; - UINT32 gen1_suport : 1 ; - UINT32 gen2_suport : 1 ; - UINT32 gen3_suport : 1 ; - UINT32 Reserved_57 : 4 ; - UINT32 crosslink_supported : 1 ; - UINT32 link_cap2 : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP11_U; - - - - -typedef union tagMiepPcieCap12 -{ - - struct - { - UINT32 targetlinkspeed : 4 ; - UINT32 entercompliance : 1 ; - UINT32 hardwareautonomousspeeddisa : 1 ; - UINT32 selectablede_empha : 1 ; - UINT32 transmitmargin : 3 ; - UINT32 _entermodifiedcompliance : 1 ; - UINT32 compliancesos : 1 ; - UINT32 de_emphasislevel : 4 ; - UINT32 currentde_emphasislevel : 1 ; - UINT32 equalizationcomplete : 1 ; - UINT32 equalizationphase1successful : 1 ; - UINT32 equalizationphase2successful : 1 ; - UINT32 equalizationphase3successful : 1 ; - UINT32 linkequalizationrequest : 1 ; - UINT32 link_ctrl2_status2 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PCIE_CAP12_U; - - - - -typedef union tagMiepSlotCap -{ - - struct - { - UINT32 slotnumberingcapabilitiesid : 8 ; - UINT32 nextcapabilitypointer : 8 ; - UINT32 add_incardslotsprovided : 5 ; - UINT32 firstinchassis : 1 ; - UINT32 Reserved_59 : 2 ; - UINT32 slot_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_SLOT_CAP_U; - - - - -typedef union tagMiepAerCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 aer_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP0_U; - - - - -typedef union tagMiepAerCap1 -{ - - struct - { - UINT32 Reserved_65 : 1 ; - UINT32 Reserved_64 : 3 ; - UINT32 datalinkprotocolerrorsta : 1 ; - UINT32 surprisedownerrorstatus : 1 ; - UINT32 Reserved_63 : 6 ; - UINT32 poisonedtlpstatu : 1 ; - UINT32 flowcontrolprotocolerrorst : 1 ; - UINT32 completiontimeouts : 1 ; - UINT32 completerabortstatus : 1 ; - UINT32 receiveroverflowstatus : 1 ; - UINT32 malformedtlpstatus : 1 ; - UINT32 ecrcerrorstatus : 1 ; - UINT32 ecrcerrorstat : 1 ; - UINT32 unsupportedrequesterrorstatus : 1 ; - UINT32 Reserved_62 : 3 ; - UINT32 atomicopegressblockedstatus : 1 ; - UINT32 uncorr_err_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP1_U; - - - - -typedef union tagMiepAerCap2 -{ - - struct - { - UINT32 Reserved_69 : 1 ; - UINT32 Reserved_68 : 3 ; - UINT32 datalinkprotocolerrormask : 1 ; - UINT32 surprisedownerrormask : 1 ; - UINT32 Reserved_67 : 6 ; - UINT32 poisonedtlpmask : 1 ; - UINT32 flowcontrolprotocolerrormask : 1 ; - UINT32 completiontimeoutmask : 1 ; - UINT32 completerabortmask : 1 ; - UINT32 unexpectedcompletionmask : 1 ; - UINT32 receiveroverflowmask : 1 ; - UINT32 malformedtlpmask : 1 ; - UINT32 ecrcerrormask : 1 ; - UINT32 unsupportedrequesterrormask : 1 ; - UINT32 Reserved_66 : 3 ; - UINT32 atomicopegressblockedmask : 1 ; - UINT32 uncorr_err_mask : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP2_U; - - - - -typedef union tagMiepAerCap3 -{ - - struct - { - UINT32 Reserved_73 : 1 ; - UINT32 Reserved_72 : 3 ; - UINT32 datalinkprotocolerrorsever : 1 ; - UINT32 surprisedownerrorseverity : 1 ; - UINT32 Reserved_71 : 6 ; - UINT32 poisonedtlpseverity : 1 ; - UINT32 flowcontrolprotocolerrorseveri : 1 ; - UINT32 completiontimeoutseverity : 1 ; - UINT32 completerabortseverity : 1 ; - UINT32 unexpectedcompletionseverity : 1 ; - UINT32 receiveroverflowseverity : 1 ; - UINT32 malformedtlpseverity : 1 ; - UINT32 ecrcerrorseverity : 1 ; - UINT32 unsupportedrequesterrorseverity : 1 ; - UINT32 Reserved_70 : 3 ; - UINT32 atomicopegressblockedseverity : 1 ; - UINT32 uncorr_err_ser : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP3_U; - - - - -typedef union tagMiepAerCap4 -{ - - struct - { - UINT32 receivererrorstatus : 1 ; - UINT32 Reserved_75 : 5 ; - UINT32 badtlpstatus : 1 ; - UINT32 baddllpstatus : 1 ; - UINT32 replay_numrolloverstatus : 1 ; - UINT32 Reserved_74 : 3 ; - UINT32 replytimertimeoutstatus : 1 ; - UINT32 advisorynon_fatalerrorstatus : 1 ; - UINT32 corr_err_status : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP4_U; - - - - -typedef union tagMiepAerCap5 -{ - - struct - { - UINT32 receivererrormask : 1 ; - UINT32 Reserved_77 : 5 ; - UINT32 badtlpmask : 1 ; - UINT32 baddllpmask : 1 ; - UINT32 replay_numrollovermask : 1 ; - UINT32 Reserved_76 : 3 ; - UINT32 replytimertimeoutmask : 1 ; - UINT32 advisorynon_fatalerrormask : 1 ; - UINT32 corr_err_mask : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP5_U; - - - - -typedef union tagMiepAerCap6 -{ - - struct - { - UINT32 firsterrorpointer : 5 ; - UINT32 ecrcgenerationcapability : 1 ; - UINT32 ecrcgenerationenable : 1 ; - UINT32 ecrccheckcapable : 1 ; - UINT32 ecrccheckenable : 1 ; - UINT32 adv_cap_ctrl : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP6_U; - - - - -typedef union tagMiepAerCap11 -{ - - struct - { - UINT32 correctableerrorreportingenable : 1 ; - UINT32 non_fatalerrorreportingenable : 1 ; - UINT32 fatalerrorreportingenable : 1 ; - UINT32 root_err_cmd : 29 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP11_U; - - - - -typedef union tagMiepAerCap12 -{ - - struct - { - UINT32 err_correceived : 1 ; - UINT32 multipleerr_correceived : 1 ; - UINT32 err_fatal_nonfatalreceived : 1 ; - UINT32 multipleerr_fatal_nonfatalreceived : 1 ; - UINT32 firstuncorrectablefatal : 1 ; - UINT32 non_fatalerrormessagesreceived : 1 ; - UINT32 fatalerrormessagesreceived : 1 ; - UINT32 Reserved_78 : 20 ; - UINT32 root_err_status : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP12_U; - - - - -typedef union tagMiepAerCap13 -{ - - struct - { - UINT32 err_corsourceidentification : 16 ; - UINT32 err_src_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_AER_CAP13_U; - - - - -typedef union tagMiepVcCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 vc_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP0_U; - - - - -typedef union tagMiepVcCap1 -{ - - struct - { - UINT32 extendedvccount : 3 ; - UINT32 Reserved_81 : 1 ; - UINT32 lowpriorityextendedvccount : 3 ; - UINT32 Reserved_80 : 1 ; - UINT32 referenceclock : 2 ; - UINT32 portarbitrationtableentrysize : 2 ; - UINT32 vc_cap1 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP1_U; - - - - -typedef union tagMiepVcCap2 -{ - - struct - { - UINT32 vcarbitrationcapability : 8 ; - UINT32 Reserved_82 : 16 ; - UINT32 vc_cap2 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP2_U; - - - - -typedef union tagMiepVcCap3 -{ - - struct - { - UINT32 loadvcarbitrationtable : 1 ; - UINT32 vcarbitrationselect : 3 ; - UINT32 Reserved_84 : 12 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 Reserved_83 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP3_U; - - - - -typedef union tagMiepVcCap4 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_87 : 6 ; - UINT32 Reserved_86 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_85 : 1 ; - UINT32 vc_res_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP4_U; - - - - -typedef union tagMiepVcCap5 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_90 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselec : 3 ; - UINT32 Reserved_89 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_88 : 4 ; - UINT32 vc_res_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP5_U; - - - - -typedef union tagMiepVcCap6 -{ - - struct - { - UINT32 Reserved_91 : 16 ; - UINT32 portarbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP6_U; - - - - -typedef union tagMiepVcCap7 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_94 : 6 ; - UINT32 Reserved_93 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_92 : 1 ; - UINT32 vc_res_cap0 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP7_U; - - - - -typedef union tagMiepVcCap8 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_97 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselect : 3 ; - UINT32 Reserved_96 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_95 : 4 ; - UINT32 vc_res_ctrl0 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP8_U; - - - - -typedef union tagMiepVcCap9 -{ - - struct - { - UINT32 Reserved_98 : 16 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status0 : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_VC_CAP9_U; - - - - -typedef union tagMiepPortLogic0 -{ - - struct - { - UINT32 ack_lat_timer : 16 ; - UINT32 replay_timer : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC0_U; - - - - -typedef union tagMiepPortLogic2 -{ - - struct - { - UINT32 linknumber : 8 ; - UINT32 Reserved_101 : 7 ; - UINT32 forcelink : 1 ; - UINT32 linkstate : 6 ; - UINT32 Reserved_100 : 2 ; - UINT32 port_force_link : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC2_U; - - - - -typedef union tagMiepPortLogic3 -{ - - struct - { - UINT32 ackfrequency : 8 ; - UINT32 n_fts : 8 ; - UINT32 commonclockn_fts : 8 ; - UINT32 l0sentrancelatency : 3 ; - UINT32 l1entrancelatency : 3 ; - UINT32 enteraspml1withoutreceiveinl0s : 1 ; - UINT32 ack_aspm : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC3_U; - - - - -typedef union tagMiepPortLogic4 -{ - - struct - { - UINT32 vendorspecificdllprequest : 1 ; - UINT32 scrambledisable : 1 ; - UINT32 loopbackenable : 1 ; - UINT32 resetassert : 1 ; - UINT32 Reserved_104 : 1 ; - UINT32 dlllinkenable : 1 ; - UINT32 Reserved_103 : 1 ; - UINT32 fastlinkmode : 1 ; - UINT32 Reserved_102 : 8 ; - UINT32 linkmodeenable : 6 ; - UINT32 crosslinkenable : 1 ; - UINT32 crosslinkactive : 1 ; - UINT32 port_link_ctrl : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC4_U; - - - - -typedef union tagMiepPortLogic5 -{ - - struct - { - UINT32 insertlaneskewfortransmit : 24 ; - UINT32 flowcontroldisable : 1 ; - UINT32 ack_nakdisable : 1 ; - UINT32 Reserved_105 : 5 ; - UINT32 lane_skew : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC5_U; - - - - -typedef union tagMiepPortLogic6 -{ - - struct - { - UINT32 numberoftssymbols : 4 ; - UINT32 Reserved_107 : 4 ; - UINT32 numberofskpsymbols : 3 ; - UINT32 Reserved_106 : 3 ; - UINT32 timermodifierforreplaytimer : 5 ; - UINT32 timermodifierforack_naklatencytimer : 5 ; - UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; - UINT32 sym_num : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC6_U; - - - - -typedef union tagMiepPortLogic7 -{ - - struct - { - UINT32 vc0posteddataqueuedepth : 11 ; - UINT32 Reserved_108 : 4 ; - UINT32 sym_timer : 1 ; - UINT32 maskfunctionmismatchfilteringfo : 1 ; - UINT32 maskpoisonedtlpfiltering : 1 ; - UINT32 maskbarmatchfiltering : 1 ; - UINT32 masktype1configurationrequestfiltering : 1 ; - UINT32 masklockedrequestfiltering : 1 ; - UINT32 masktagerrorrulesforreceivedcompletions : 1 ; - UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; - UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; - UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; - UINT32 maske_crcerror_filtering : 1 ; - UINT32 maske_crcerror_filtering_forcompletions : 1 ; - UINT32 message_control : 1 ; - UINT32 maskfilteringofreceived : 1 ; - UINT32 flt_mask1 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC7_U; - - - - -typedef union tagMiepPortLogic8 -{ - - struct - { - UINT32 cx_flt_mask_venmsg0_drop : 1 ; - UINT32 cx_flt_mask_venmsg1_drop : 1 ; - UINT32 cx_flt_mask_dabort_4ucpl : 1 ; - UINT32 cx_flt_mask_handle_flush : 1 ; - UINT32 flt_mask2 : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC8_U; - - - - -typedef union tagMiepPortLogic9 -{ - - struct - { - UINT32 amba_multi_outbound_decomp_np : 1 ; - UINT32 amba_obnp_ctrl : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC9_U; - - - - -typedef union tagMiepPortLogic12 -{ - - struct - { - UINT32 transmitposteddatafccredits : 12 ; - UINT32 transmitpostedheaderfccredits : 8 ; - UINT32 tx_pfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC12_U; - - - - -typedef union tagMiepPortLogic13 -{ - - struct - { - UINT32 transmitnon_posteddatafccredits : 12 ; - UINT32 transmitnon_postedheaderfccredits : 8 ; - UINT32 tx_npfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC13_U; - - - - -typedef union tagMiepPortLogic14 -{ - - struct - { - UINT32 transmitcompletiondatafccredits : 12 ; - UINT32 transmitcompletionheaderfccredits : 8 ; - UINT32 tx_cplfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC14_U; - - - - -typedef union tagMiepPortLogic15 -{ - - struct - { - UINT32 rx_tlp_fc_credit_not_retured : 1 ; - UINT32 tx_retry_buf_not_empty : 1 ; - UINT32 rx_queue_not_empty : 1 ; - UINT32 Reserved_110 : 13 ; - UINT32 fc_latency_timer_override_value : 13 ; - UINT32 Reserved_109 : 2 ; - UINT32 fc_latency_timer_override_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC15_U; - - - - -typedef union tagMiepPortLogic16 -{ - - struct - { - UINT32 vc0posteddatacredits : 12 ; - UINT32 vc0postedheadercredits : 8 ; - UINT32 Reserved_112 : 1 ; - UINT32 vc0_postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemo : 1 ; - UINT32 Reserved_111 : 6 ; - UINT32 tlptypeorderingforvc0 : 1 ; - UINT32 rx_pque_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC16_U; - - - - -typedef union tagMiepPortLogic17 -{ - - struct - { - UINT32 vc0non_posteddatacredits : 12 ; - UINT32 vc0non_postedheadercredits : 8 ; - UINT32 rx_npque_ctrl : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC17_U; - - - - -typedef union tagMiepPortLogic18 -{ - - struct - { - UINT32 vco_comp_data_credits : 12 ; - UINT32 vc0_cpl_header_credt : 8 ; - UINT32 Reserved_114 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC18_U; - - - - -typedef union tagMiepPortLogic19 -{ - - struct - { - UINT32 vco_posted_data_que_path : 14 ; - UINT32 Reserved_115 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 vc_pbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC19_U; - - - - -typedef union tagMiepPortLogic20 -{ - - struct - { - UINT32 vco_np_data_que_depth : 14 ; - UINT32 Reserved_117 : 2 ; - UINT32 vco_np_header_que_depth : 10 ; - UINT32 vc_npbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC20_U; - - - - -typedef union tagMiepPortLogic21 -{ - - struct - { - UINT32 vco_comp_data_queue_depth : 14 ; - UINT32 Reserved_119 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 Reserved_118 : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC21_U; - - - - -typedef union tagMiepPortLogic22 -{ - - struct - { - UINT32 n_fts : 8 ; - UINT32 pre_determ_num_of_lane : 9 ; - UINT32 det_sp_change : 1 ; - UINT32 config_phy_tx_sw : 1 ; - UINT32 config_tx_comp_rcv_bit : 1 ; - UINT32 set_emp_level : 1 ; - UINT32 Reserved_120 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORT_LOGIC22_U; - - - - -typedef union tagMiepPortlogic25 -{ - - struct - { - UINT32 remote_rd_req_size : 3 ; - UINT32 Reserved_123 : 5 ; - UINT32 remote_max_brd_tag : 8 ; - UINT32 Reserved_122 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC25_U; - - - - -typedef union tagMiepPortlogic26 -{ - - struct - { - UINT32 resize_master_resp_compser : 1 ; - UINT32 axi_ctrl1 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC26_U; - - - - -typedef union tagMiepPortlogic54 -{ - - struct - { - UINT32 region_index : 4 ; - UINT32 Reserved_124 : 27 ; - UINT32 iatu_view : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC54_U; - - - - -typedef union tagMiepPortlogic55 -{ - - struct - { - UINT32 iatu1_type : 5 ; - UINT32 iatu1_tc : 3 ; - UINT32 iatu1_td : 1 ; - UINT32 iatu1_attr : 2 ; - UINT32 Reserved_128 : 5 ; - UINT32 iatu1_at : 2 ; - UINT32 Reserved_127 : 2 ; - UINT32 iatu1_id : 3 ; - UINT32 Reserved_126 : 9 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC55_U; - - - - -typedef union tagMiepPortlogic56 -{ - - struct - { - UINT32 iatu2_type : 8 ; - UINT32 iatu2_bar_num : 3 ; - UINT32 Reserved_132 : 3 ; - UINT32 iatu2_tc_match_en : 1 ; - UINT32 iatu2_td_match_en : 1 ; - UINT32 iatu2_attr_match_en : 1 ; - UINT32 Reserved_131 : 1 ; - UINT32 iatu2_at_match_en : 1 ; - UINT32 iatu2_func_num_match_en : 1 ; - UINT32 iatu2_virtual_func_num_match_en : 1 ; - UINT32 message_code_match_en : 1 ; - UINT32 Reserved_130 : 2 ; - UINT32 iatu2_response_code : 2 ; - UINT32 Reserved_129 : 1 ; - UINT32 iatu2_fuzzy_type_match_mode : 1 ; - UINT32 iatu2_cfg_shift_mode : 1 ; - UINT32 iatu2_ivert_mode : 1 ; - UINT32 iatu2_match_mode : 1 ; - UINT32 iatu2_region_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC56_U; - - - - -typedef union tagMiepPortlogic57 -{ - - struct - { - UINT32 iatu_start_low : 12 ; - UINT32 iatu_start_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC57_U; - - - - -typedef union tagMiepPortlogic59 -{ - - struct - { - UINT32 iatu_limit_low : 12 ; - UINT32 iatu_limit_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC59_U; - - - - -typedef union tagMiepPortlogic60 -{ - - struct - { - UINT32 xlated_addr_high : 12 ; - UINT32 xlated_addr_low : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC60_U; - - - - -typedef union tagMiepPortlogic62 -{ - - struct - { - UINT32 dma_wr_eng_en : 1 ; - UINT32 dma_wr_ena : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC62_U; - - - - -typedef union tagMiepPortlogic63 -{ - - struct - { - UINT32 wr_doorbell_num : 3 ; - UINT32 Reserved_134 : 28 ; - UINT32 dma_wr_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC63_U; - - - - -typedef union tagMiepPortlogic64 -{ - - struct - { - UINT32 dma_read_eng_en : 1 ; - UINT32 Reserved_135 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC64_U; - - - - -typedef union tagMiepPortlogic65 -{ - - struct - { - UINT32 rd_doorbell_num : 3 ; - UINT32 Reserved_137 : 28 ; - UINT32 dma_rd_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC65_U; - - - - -typedef union tagMiepPortlogic66 -{ - - struct - { - UINT32 done_int_status : 8 ; - UINT32 Reserved_139 : 8 ; - UINT32 abort_int_status : 8 ; - UINT32 Reserved_138 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC66_U; - - - - -typedef union tagMiepPortlogic67 -{ - - struct - { - UINT32 done_int_mask : 8 ; - UINT32 Reserved_142 : 8 ; - UINT32 abort_int_mask : 8 ; - UINT32 Reserved_141 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC67_U; - - - - -typedef union tagMiepPortlogic68 -{ - - struct - { - UINT32 done_int_clr : 8 ; - UINT32 Reserved_145 : 8 ; - UINT32 abort_int_clr : 8 ; - UINT32 Reserved_144 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC68_U; - - - - -typedef union tagMiepPortlogic69 -{ - - struct - { - UINT32 app_rd_err_det : 8 ; - UINT32 Reserved_147 : 8 ; - UINT32 ll_element_fetch_err_det : 8 ; - UINT32 Reserved_146 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC69_U; - - - - -typedef union tagMiepPortlogic74 -{ - - struct - { - UINT32 dma_wr_c0_imwr_data : 16 ; - UINT32 dma_wr_c1_imwr_data : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC74_U; - - - - -typedef union tagMiepPortlogic75 -{ - - struct - { - UINT32 wr_ch_ll_remote_abort_int_en : 8 ; - UINT32 Reserved_149 : 8 ; - UINT32 wr_ch_ll_local_abort_int_en : 8 ; - UINT32 Reserved_148 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC75_U; - - - - -typedef union tagMiepPortlogic76 -{ - - struct - { - UINT32 done_int_status : 8 ; - UINT32 Reserved_152 : 8 ; - UINT32 abort_int_status : 8 ; - UINT32 Reserved_151 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC76_U; - - - - -typedef union tagMiepPortlogic77 -{ - - struct - { - UINT32 done_int_mask : 8 ; - UINT32 Reserved_154 : 8 ; - UINT32 abort_int_mask : 8 ; - UINT32 dma_rd_int_mask : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC77_U; - - - - -typedef union tagMiepPortlogic78 -{ - - struct - { - UINT32 done_int_clr : 8 ; - UINT32 Reserved_156 : 8 ; - UINT32 abort_int_clr : 8 ; - UINT32 dma_rd_int_clr : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC78_U; - - - - -typedef union tagMiepPortlogic79 -{ - - struct - { - UINT32 app_wr_err_det : 8 ; - UINT32 Reserved_157 : 8 ; - UINT32 link_list_fetch_err_det : 8 ; - UINT32 dma_rd_err_low : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC79_U; - - - - -typedef union tagMiepPortlogic80 -{ - - struct - { - UINT32 unspt_request : 8 ; - UINT32 completer_abort : 8 ; - UINT32 cpl_time_out : 8 ; - UINT32 dma_rd_err_high : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC80_U; - - - - -typedef union tagMiepPortlogic81 -{ - - struct - { - UINT32 remote_abort_int_en : 8 ; - UINT32 Reserved_159 : 8 ; - UINT32 local_abort_int_en : 8 ; - UINT32 dma_rd_ll_err_ena : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC81_U; - - - - -typedef union tagMiepPortlogic86 -{ - - struct - { - UINT32 channel_dir : 3 ; - UINT32 Reserved_162 : 28 ; - UINT32 dma_ch_con_idx : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC86_U; - - - - -typedef union tagMiepPortlogic87 -{ - - struct - { - UINT32 cycle_bit : 1 ; - UINT32 toggle_cycle_bit : 1 ; - UINT32 load_link_pointer : 1 ; - UINT32 local_int_en : 1 ; - UINT32 remote_int_en : 1 ; - UINT32 channel_status : 2 ; - UINT32 Reserved_166 : 1 ; - UINT32 consumer_cycle_state : 1 ; - UINT32 linked_list_en : 1 ; - UINT32 Reserved_165 : 2 ; - UINT32 func_num_dma : 5 ; - UINT32 Reserved_164 : 7 ; - UINT32 no_snoop : 1 ; - UINT32 ro : 1 ; - UINT32 td : 1 ; - UINT32 tc : 3 ; - UINT32 dma_ch_ctrl : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC87_U; - - - - -typedef union tagMiepPortlogic93 -{ - - struct - { - UINT32 Reserved_168 : 2 ; - UINT32 dma_ll_ptr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_MIEP_PORTLOGIC93_U; - - - -#define PCIE_IEP_BASE (0x00000000) - - - - -#define PCIE_IEP_DEVICE_VENDOR_ID_REG (PCIE_IEP_BASE + 0x0) -#define PCIE_IEP_PCISTS_PCICMD_REG (PCIE_IEP_BASE + 0x4) -#define PCIE_IEP_CCR_RID_REG (PCIE_IEP_BASE + 0x8) -#define PCIE_IEP_PBAR01_BASE_LOWER_REG (PCIE_IEP_BASE + 0x10) -#define PCIE_IEP_PBAR01_BASE_UPPER_REG (PCIE_IEP_BASE + 0x14) -#define PCIE_IEP_PBAR23_BASE_LOWER_REG (PCIE_IEP_BASE + 0x18) -#define PCIE_IEP_PBAR23_BASE_UPPER_REG (PCIE_IEP_BASE + 0x1C) -#define PCIE_IEP_PBAR45_BASE_LOWER_REG (PCIE_IEP_BASE + 0x20) -#define PCIE_IEP_PBAR45_BASE_UPPER_REG (PCIE_IEP_BASE + 0x24) -#define PCIE_IEP_CARDBUSCISPTR_REG (PCIE_IEP_BASE + 0x28) -#define PCIE_IEP_SUBSYSTEMID_REG (PCIE_IEP_BASE + 0x2C) -#define PCIE_IEP_EXPANSIONROM_BASE_ADDR_REG (PCIE_IEP_BASE + 0x30) -#define PCIE_IEP_CAPPTR_REG (PCIE_IEP_BASE + 0x34) -#define PCIE_IEP_INTERRUPT_REG (PCIE_IEP_BASE + 0x3C) -#define PCIE_IEP_MSI_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x50) -#define PCIE_IEP_MSI_LOWER32_BITADDRESS_REG (PCIE_IEP_BASE + 0x54) -#define PCIE_IEP_MSI_UPPER32_BIT_ADDRESS_REG (PCIE_IEP_BASE + 0x58) -#define PCIE_IEP_MSI_DATA_REG (PCIE_IEP_BASE + 0x5C) -#define PCIE_IEP_MSI_MASK_REG (PCIE_IEP_BASE + 0x60) -#define PCIE_IEP_MSI_PENDING_REG (PCIE_IEP_BASE + 0x64) -#define PCIE_IEP_PCIE_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x70) -#define PCIE_IEP_DEVICE_CAPABILITIES_REGISTER_REG (PCIE_IEP_BASE + 0x74) -#define PCIE_IEP_DEVICE_STATUS_REGISTER_REG (PCIE_IEP_BASE + 0x78) -#define PCIE_IEP_LINK_CAPABILITY_REG (PCIE_IEP_BASE + 0x7C) -#define PCIE_IEP_LINK_CONTROL_STATUS_REG (PCIE_IEP_BASE + 0x80) -#define PCIE_IEP_AER_CAP_HEADER_REG (PCIE_IEP_BASE + 0x100) -#define PCIE_IEP_UC_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x104) -#define PCIE_IEP_UC_ERROR_MASK_REG (PCIE_IEP_BASE + 0x108) -#define PCIE_IEP_UC_ERROR_SEVERITY_REG (PCIE_IEP_BASE + 0x10C) -#define PCIE_IEP_C_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x110) -#define PCIE_IEP_C_ERROR_MASK_REG (PCIE_IEP_BASE + 0x114) -#define PCIE_IEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (PCIE_IEP_BASE + 0x118) -#define PCIE_IEP_HEADER_LOG_REGISTERS_1_REG (PCIE_IEP_BASE + 0x11C) -#define PCIE_IEP_HEADER_LOG_REGISTERS_2_REG (PCIE_IEP_BASE + 0x120) -#define PCIE_IEP_HEADER_LOG_REGISTERS_3_REG (PCIE_IEP_BASE + 0x124) -#define PCIE_IEP_HEADER_LOG_REGISTERS_4_REG (PCIE_IEP_BASE + 0x128) -#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_1_REG (PCIE_IEP_BASE + 0x130) -#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_2_REG (PCIE_IEP_BASE + 0x134) -#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_3_REG (PCIE_IEP_BASE + 0x138) -#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_4_REG (PCIE_IEP_BASE + 0x13C) -#define PCIE_IEP_NTB_IEP_CFG_SPACE_LOWER_REG (PCIE_IEP_BASE + 0x700) -#define PCIE_IEP_NTB_IEP_CFG_SPACE_UPPER_REG (PCIE_IEP_BASE + 0x704) -#define PCIE_IEP_NTB_IEP_BAR01_CTRL_REG (PCIE_IEP_BASE + 0x708) -#define PCIE_IEP_NTB_IEP_BAR23_CTRL_REG (PCIE_IEP_BASE + 0x70C) -#define PCIE_IEP_NTB_IEP_BAR45_CTRL_REG (PCIE_IEP_BASE + 0x710) -#define PCIE_IEP_MSI_CTRL_ADDRESS_LOWER_REG (PCIE_IEP_BASE + 0x714) -#define PCIE_IEP_MSI_CTRL_ADDRESS_UPPER_REG (PCIE_IEP_BASE + 0x718) -#define PCIE_IEP_MSI_CTRL_INT_EN_REG (PCIE_IEP_BASE + 0x71C) -#define PCIE_IEP_MSI_CTRL_INT0_MASK_REG (PCIE_IEP_BASE + 0x720) -#define PCIE_IEP_MSI_CTRL_INT_STATUS_REG (PCIE_IEP_BASE + 0x724) - - - -typedef union tagIepDeviceVendorId -{ - - struct - { - UINT32 Vendor_ID : 16 ; - UINT32 Device_ID : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_DEVICE_VENDOR_ID_U; - - - - -typedef union tagIepPcistsPcicmd -{ - - struct - { - UINT32 IO_Space_Enable : 1 ; - UINT32 Memory_Space_Enable : 1 ; - UINT32 Bus_Master_Enable : 1 ; - UINT32 SpecialCycleEnable : 1 ; - UINT32 Memory_Write_and_Invalidate : 1 ; - UINT32 VGA_palette_snoop_Enable : 1 ; - UINT32 Parity_Error_Response : 1 ; - UINT32 IDSEL_Stepping_WaitCycle_Control : 1 ; - UINT32 SERR_Enable : 1 ; - UINT32 FastBack_to_BackEnable : 1 ; - UINT32 Interrupt_Disable : 1 ; - UINT32 Reserved_2 : 5 ; - UINT32 Reserved_1 : 3 ; - UINT32 INTx_Status : 1 ; - UINT32 CapabilitiesList : 1 ; - UINT32 pcibus66MHzcapable : 1 ; - UINT32 Reserved_0 : 1 ; - UINT32 FastBack_to_Back : 1 ; - UINT32 MasterDataParityError : 1 ; - UINT32 DEVSEL_Timing : 2 ; - UINT32 Signaled_Target_Abort : 1 ; - UINT32 Received_Target_Abort : 1 ; - UINT32 Received_Master_Abort : 1 ; - UINT32 Signaled_System_Error : 1 ; - UINT32 Detected_Parity_Error : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_PCISTS_PCICMD_U; - - - - -typedef union tagIepCcrRid -{ - - struct - { - UINT32 Revision_Identification : 8 ; - UINT32 Reserved_3 : 8 ; - UINT32 Sub_Class : 8 ; - UINT32 BaseClass : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_CCR_RID_U; - - - - -typedef union tagIepPbar01BaseLower -{ - - struct - { - UINT32 BAR01_Space_Inicator : 1 ; - UINT32 BAR01_Type : 2 ; - UINT32 BAR01_Prefetchable : 1 ; - UINT32 Reserved_4 : 12 ; - UINT32 pbar01_lower : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_PBAR01_BASE_LOWER_U; - - - - -typedef union tagIepPbar23BaseLower -{ - - struct - { - UINT32 pbar23_space_inicator : 1 ; - UINT32 pbar23_type : 2 ; - UINT32 pbar23_prefetchable : 1 ; - UINT32 Reserved_6 : 8 ; - UINT32 pbar23_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_PBAR23_BASE_LOWER_U; - - - - -typedef union tagIepPbar45BaseLower -{ - - struct - { - UINT32 pbar45_space_inicator : 1 ; - UINT32 pbar45_type : 2 ; - UINT32 pbar45_prefetchable : 1 ; - UINT32 Reserved_7 : 8 ; - UINT32 pbar45_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_PBAR45_BASE_LOWER_U; - - - - -typedef union tagIepSubsystemid -{ - - struct - { - UINT32 SubsystemID : 16 ; - UINT32 SubsystemVendorID : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_SubSystemId_U; - - - - -typedef union tagIepCapptr -{ - - struct - { - UINT32 CapPtr : 8 ; - UINT32 Reserved_10 : 24 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_CapPtr_U; - - - - -typedef union tagIepInterrupt -{ - - struct - { - UINT32 Interrupt_Line : 8 ; - UINT32 Interrupt_Pin : 8 ; - UINT32 Min_Grant : 8 ; - UINT32 Max_Latency : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_Interrupt_U; - - - - -typedef union tagIepMsiCapabilityRegister -{ - - struct - { - UINT32 CapabilityID : 8 ; - UINT32 Next_Capability_Pointer : 8 ; - UINT32 MSI_Enabled : 1 ; - UINT32 Multiple_Message_Capable : 3 ; - UINT32 Multiple_Message_Enabled : 3 ; - UINT32 MSI_64_EN : 1 ; - UINT32 PVM_EN : 1 ; - UINT32 Message_Control_Register : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_Capability_Register_U; - - - - -typedef union tagIepMsiLower32Bitaddress -{ - - struct - { - UINT32 Reserved_13 : 2 ; - UINT32 Lower32_bitAddress : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_Lower32_bitAddress_U; - - - - -typedef union tagIepMsiData -{ - - struct - { - UINT32 MSI_Data : 16 ; - UINT32 Reserved_14 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_Data_U; - - - - -typedef union tagIepMsiMask -{ - - struct - { - UINT32 MsiMask : 1 ; - UINT32 Reserved_15 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_MASK_U; - - - - -typedef union tagIepMsiPending -{ - - struct - { - UINT32 MsiPending : 1 ; - UINT32 Reserved_16 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_Pending_U; - - - - -typedef union tagIepPcieCapabilityRegister -{ - - struct - { - UINT32 Capability_ID : 8 ; - UINT32 Next_Capability_Pointer : 8 ; - UINT32 PCIE_Capability_Version : 4 ; - UINT32 Device_Port_Type : 4 ; - UINT32 Slot_Implemented : 1 ; - UINT32 Interrupt_Message_Number : 5 ; - UINT32 Reserved_17 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_PCIE_Capability_Register_U; - - - - -typedef union tagIepDeviceCapabilitiesRegister -{ - - struct - { - UINT32 Max_Payload_Size_Supported : 3 ; - UINT32 Phantom_Function_Supported : 2 ; - UINT32 Extended_TagField_Supported : 1 ; - UINT32 Endpoint_L0sAcceptable_Latency : 3 ; - UINT32 Endpoint_L1Acceptable_Latency : 3 ; - UINT32 Undefined : 3 ; - UINT32 Reserved_20 : 3 ; - UINT32 Captured_Slot_Power_Limit_Value : 8 ; - UINT32 Captured_Slot_Power_Limit_Scale : 2 ; - UINT32 Function_Level_Reset : 1 ; - UINT32 Reserved_19 : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_Device_Capabilities_Register_U; - - - - -typedef union tagIepDeviceStatusRegister -{ - - struct - { - UINT32 Correctable_Error_Reporting_Enable : 1 ; - UINT32 Non_Fatal_Error_Reporting_Enable : 1 ; - UINT32 Fatal_Error_Reporting_Enable : 1 ; - UINT32 UREnable : 1 ; - UINT32 Enable_Relaxed_Ordering : 1 ; - UINT32 Max_Payload_Size : 3 ; - UINT32 Extended_TagFieldEnable : 1 ; - UINT32 Phantom_Function_Enable : 1 ; - UINT32 AUXPowerPMEnable : 1 ; - UINT32 EnableNoSnoop : 1 ; - UINT32 Max_Read_Request_Size : 3 ; - UINT32 Reserved_22 : 1 ; - UINT32 CorrectableErrorDetected : 1 ; - UINT32 Non_FatalErrordetected : 1 ; - UINT32 FatalErrorDetected : 1 ; - UINT32 UnsupportedRequestDetected : 1 ; - UINT32 AuxPowerDetected : 1 ; - UINT32 TransactionPending : 1 ; - UINT32 Reserved_21 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_Device_Status_Register_U; - - - - -typedef union tagIepLinkCapability -{ - - struct - { - UINT32 Max_Link_Speed : 4 ; - UINT32 Max_Link_Width : 6 ; - UINT32 Active_State_Power_Management : 2 ; - UINT32 L0s_ExitLatency : 3 ; - UINT32 L1_Exit_Latency : 3 ; - UINT32 Clock_Power_Management : 1 ; - UINT32 Surprise_Down_Error_Report_Cap : 1 ; - UINT32 Data_Link_Layer_Active_Report_Cap : 1 ; - UINT32 Link_Bandwidth_Noti_Cap : 1 ; - UINT32 ASPM_Option_Compliance : 1 ; - UINT32 Reserved_23 : 1 ; - UINT32 Port_Number : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_Link_Capability_U; - - - - -typedef union tagIepLinkControlStatus -{ - - struct - { - UINT32 Active_State_Power_Management : 2 ; - UINT32 Reserved_26 : 1 ; - UINT32 RCB : 1 ; - UINT32 Link_Disable : 1 ; - UINT32 Retrain_Link : 1 ; - UINT32 Common_Clock_Config : 1 ; - UINT32 Extended_Sync : 1 ; - UINT32 Enable_Clock_Pwr_Management : 1 ; - UINT32 Hw_Auto_Width_Disable : 1 ; - UINT32 Link_Bandwidth_Management_Int_En : 1 ; - UINT32 Link_Auto_Bandwidth_Int_En : 1 ; - UINT32 Reserved_25 : 4 ; - UINT32 current_link_speed : 4 ; - UINT32 negotiated_link_width : 6 ; - UINT32 Reserved_24 : 1 ; - UINT32 link_training : 1 ; - UINT32 slot_clock_config : 1 ; - UINT32 data_link_layer_active : 1 ; - UINT32 link_bandwidth_management_status : 1 ; - UINT32 link_auto_bandwidth_status : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_Link_Control_Status_U; - - - - -typedef union tagIepAerCapHeader -{ - - struct - { - UINT32 PCIE_Extended_Capability_ID : 16 ; - UINT32 Capability_Version : 4 ; - UINT32 Next_Capability_Offset : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_AER_Cap_header_U; - - - - -typedef union tagIepUcErrorStatus -{ - - struct - { - UINT32 Reserved_31 : 1 ; - UINT32 Reserved_30 : 3 ; - UINT32 DataLinkProtocolErrorStatus : 1 ; - UINT32 SurpriseDownErrorStatus : 1 ; - UINT32 Reserved_29 : 6 ; - UINT32 PoisonedTLPStatus : 1 ; - UINT32 FlowControlProtocolErrorStatus : 1 ; - UINT32 CompletionTimeoutStatus : 1 ; - UINT32 CompleterAbortStatus : 1 ; - UINT32 UnexpectedCompletionStatus : 1 ; - UINT32 ReceiverOverflowStatus : 1 ; - UINT32 MalformedTLPStatus : 1 ; - UINT32 ECRCErrorStatus : 1 ; - UINT32 UnsupportedRequestErrorStatus : 1 ; - UINT32 Reserved_28 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_UC_Error_Status_U; - - - - -typedef union tagIepUcErrorMask -{ - - struct - { - UINT32 Reserved_35 : 1 ; - UINT32 Reserved_34 : 3 ; - UINT32 DataLinkProtocolErrorMask : 1 ; - UINT32 SurpriseDownErrorMask : 1 ; - UINT32 Reserved_33 : 6 ; - UINT32 PoisonedTLPMask : 1 ; - UINT32 FlowControlProtocolErrorMask : 1 ; - UINT32 CompletionTimeoutMask : 1 ; - UINT32 CompleterAbortMask : 1 ; - UINT32 UnexpectedCompletionMask : 1 ; - UINT32 ReceiverOverflowMask : 1 ; - UINT32 MalformedTLPMask : 1 ; - UINT32 ECRCErrorMask : 1 ; - UINT32 UnsupportedRequestErrorMask : 1 ; - UINT32 Reserved_32 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_UC_Error_Mask_U; - - - - -typedef union tagIepUcErrorSeverity -{ - - struct - { - UINT32 Reserved_39 : 1 ; - UINT32 Reserved_38 : 3 ; - UINT32 DataLinkProtocolErrorSeverity : 1 ; - UINT32 SurpriseDownErrorSeverity : 1 ; - UINT32 Reserved_37 : 6 ; - UINT32 PoisonedTLPSeverity : 1 ; - UINT32 FlowControlProtocolErrorSeverity : 1 ; - UINT32 CompletionTimeoutSeverity : 1 ; - UINT32 CompleterAbortSeverity : 1 ; - UINT32 UnexpectedCompletionSeverity : 1 ; - UINT32 ReceiverOverflowSeverity : 1 ; - UINT32 MalformedTLPSeverity : 1 ; - UINT32 ECRCErrorSeverity : 1 ; - UINT32 UnsupportedRequestErrorSeverity : 1 ; - UINT32 Reserved_36 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_UC_Error_Severity_U; - - - - -typedef union tagIepCErrorStatus -{ - - struct - { - UINT32 Receiver_Error_Status : 1 ; - UINT32 Reserved_42 : 5 ; - UINT32 Bad_TLP_Status : 1 ; - UINT32 Bad_DLLP_Status : 1 ; - UINT32 REPLAY_NUM_Rollover_Status : 1 ; - UINT32 Reserved_41 : 3 ; - UINT32 Replay_Timer_Timeout_Status : 1 ; - UINT32 Advisory_Non_Fatal_Error_Status : 1 ; - UINT32 Reserved_40 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_C_Error_Status_U; - - - - -typedef union tagIepCErrorMask -{ - - struct - { - UINT32 Receiver_Error_Mask : 1 ; - UINT32 Reserved_45 : 5 ; - UINT32 Bad_TLP_Mask : 1 ; - UINT32 Bad_DLLP_Mask : 1 ; - UINT32 REPLAY_NUMRollover_Mask : 1 ; - UINT32 Reserved_44 : 3 ; - UINT32 Replay_Timer_Timeout_Mask : 1 ; - UINT32 Advisory_Non_Fatal_Error_Mask : 1 ; - UINT32 Reserved_43 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_C_Error_Mask_U; - - - - -typedef union tagIepAdvancedErrorCapabilitiesAndControl -{ - - struct - { - UINT32 First_Error_Pointer : 5 ; - UINT32 ECRC_Generation_Capability : 1 ; - UINT32 ECRC_Generation_Enable : 1 ; - UINT32 ECRC_Check_Capable : 1 ; - UINT32 ECRC_Check_Enable : 1 ; - UINT32 Reserved_47 : 2 ; - UINT32 TLP_Prefix_Log_Present : 1 ; - UINT32 Reserved_46 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_Advanced_Error_Capabilities_and_Control_U; - - - - -typedef union tagIepNtbIepBar01Ctrl -{ - - struct - { - UINT32 bar01_type : 5 ; - UINT32 bar01_tc : 3 ; - UINT32 bar01_td : 1 ; - UINT32 bar01_attr : 2 ; - UINT32 Reserved_51 : 5 ; - UINT32 bar01_at : 2 ; - UINT32 bar01_match_en : 1 ; - UINT32 Reserved_50 : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_NTB_IEP_BAR01_CTRL_U; - - - - -typedef union tagIepNtbIepBar23Ctrl -{ - - struct - { - UINT32 bar23_type : 5 ; - UINT32 bar23_tc : 3 ; - UINT32 bar23_td : 1 ; - UINT32 bar23_attr : 2 ; - UINT32 Reserved_53 : 5 ; - UINT32 bar23_at : 2 ; - UINT32 bar23_match_en : 1 ; - UINT32 Reserved_52 : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_NTB_IEP_BAR23_CTRL_U; - - - - -typedef union tagIepNtbIepBar45Ctrl -{ - - struct - { - UINT32 bar45_type : 5 ; - UINT32 bar45_tc : 3 ; - UINT32 bar45_td : 1 ; - UINT32 bar45_attr : 2 ; - UINT32 Reserved_55 : 5 ; - UINT32 bar45_at : 2 ; - UINT32 bar45_match_en : 1 ; - UINT32 Reserved_54 : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_NTB_IEP_BAR45_CTRL_U; - - - - -typedef union tagIepMsiCtrlIntEn -{ - - struct - { - UINT32 msi_int_en : 1 ; - UINT32 Reserved_56 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_CTRL_INT_EN_U; - - - - -typedef union tagIepMsiCtrlInt0Mask -{ - - struct - { - UINT32 msi_int_mask : 1 ; - UINT32 Reserved_57 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_CTRL_INT0_MASK_U; - - - - -typedef union tagIepMsiCtrlIntStatus -{ - - struct - { - UINT32 msi_int : 1 ; - UINT32 Reserved_58 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_IEP_MSI_CTRL_INT_STATUS_U; - - -#define PCI_SYS_BASE (0x00000000) - - - - -#define PCIE_CTRL_0_REG (PCI_SYS_BASE + 0xF8) -#define PCIE_CTRL_1_REG (PCI_SYS_BASE + 0xFC) -#define PCIE_CTRL_2_REG (PCI_SYS_BASE + 0x100) -#define PCIE_CTRL_3_REG (PCI_SYS_BASE + 0x104) -#define PCIE_CTRL_4_REG (PCI_SYS_BASE + 0x108) -#define PCIE_CTRL_5_REG (PCI_SYS_BASE + 0x10C) -#define PCIE_CTRL_6_REG (PCI_SYS_BASE + 0x110) -#define PCIE_CTRL_7_REG (PCI_SYS_BASE + 0x114) -#define PCIE_CTRL_9_REG (PCI_SYS_BASE + 0x11C) -#define PCIE_CTRL_10_REG (PCI_SYS_BASE + 0x120) -#define PCIE_CTRL_11_REG (PCI_SYS_BASE + 0x124) -#define PCIE_SYS_CTRL12_REG (PCI_SYS_BASE + 0x0) -#define PCIE_SYS_CTRL13_REG (PCI_SYS_BASE + 0x4) -#define PCIE_SYS_CTRL14_REG (PCI_SYS_BASE + 0x8) -#define PCIE_SYS_CTRL15_REG (PCI_SYS_BASE + 0xC) -#define PCIE_SYS_CTRL16_REG (PCI_SYS_BASE + 0x10) -#define PCIE_SYS_CTRL17_REG (PCI_SYS_BASE + 0x14) -#define PCIE_SYS_CTRL18_REG (PCI_SYS_BASE + 0x18) -#define PCIE_SYS_CTRL19_REG (PCI_SYS_BASE + 0x1C) -#define PCIE_SYS_CTRL20_REG (PCI_SYS_BASE + 0x20) -#define PCIE_RD_TAB_SEL BIT31 -#define PCIE_RD_TAB_EN BIT30 -#define PCIE_SYS_CTRL21_REG (PCI_SYS_BASE + 0x24) -#define PCIE_SYS_CTRL22_REG (PCI_SYS_BASE + 0x28) -#define PCIE_SYS_CTRL23_REG (PCI_SYS_BASE + 0x2C) -#define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4) -#define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) -#define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) -#define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) -#define PCIE_SYS_STATE4_REG (PCI_SYS_BASE + 0x31C) -#define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) -#define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) -#define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) -#define PCIE_SYS_STATE8_REG (PCI_SYS_BASE + 0x3C) -#define PCIE_SYS_STATE9_REG (PCI_SYS_BASE + 0x40) -#define PCIE_SYS_STATE10_REG (PCI_SYS_BASE + 0x44) -#define PCIE_SYS_STATE11_REG (PCI_SYS_BASE + 0x48) -#define PCIE_SYS_STATE12_REG (PCI_SYS_BASE + 0x4C) -#define PCIE_SYS_STATE13_REG (PCI_SYS_BASE + 0x50) -#define PCIE_SYS_STATE14_REG (PCI_SYS_BASE + 0x54) -#define PCIE_SYS_STATE15_REG (PCI_SYS_BASE + 0x58) -#define PCIE_SYS_STATE16_REG (PCI_SYS_BASE + 0x5C) -#define PCIE_SYS_STATE17_REG (PCI_SYS_BASE + 0x60) -#define PCIE_SYS_STATE18_REG (PCI_SYS_BASE + 0x64) -#define PCIE_SYS_STATE19_REG (PCI_SYS_BASE + 0x68) -#define PCIE_SYS_STATE20_REG (PCI_SYS_BASE + 0x6C) -#define PCIE_SYS_STATE21_REG (PCI_SYS_BASE + 0x70) -#define PCIE_SYS_STATE22_REG (PCI_SYS_BASE + 0x74) -#define PCIE_SYS_STATE23_REG (PCI_SYS_BASE + 0x78) -#define PCIE_SYS_STATE24_REG (PCI_SYS_BASE + 0x7C) -#define PCIE_SYS_STATE25_REG (PCI_SYS_BASE + 0x80) -#define PCIE_SYS_STATE26_REG (PCI_SYS_BASE + 0x84) -#define PCIE_SYS_STATE27_REG (PCI_SYS_BASE + 0x88) -#define PCIE_SYS_STATE28_REG (PCI_SYS_BASE + 0x8C) -#define PCIE_SYS_STATE29_REG (PCI_SYS_BASE + 0x90) -#define PCIE_SYS_STATE30_REG (PCI_SYS_BASE + 0x94) -#define PCIE_SYS_STATE31_REG (PCI_SYS_BASE + 0x98) -#define PCIE_SYS_STATE32_REG (PCI_SYS_BASE + 0x9C) -#define PCIE_SYS_STATE33_REG (PCI_SYS_BASE + 0xA0) -#define PCIE_SYS_STATE34_REG (PCI_SYS_BASE + 0xA4) -#define PCIE_SYS_STATE35_REG (PCI_SYS_BASE + 0xA8) -#define PCIE_SYS_STATE36_REG (PCI_SYS_BASE + 0xAC) -#define PCIE_SYS_STATE37_REG (PCI_SYS_BASE + 0xB0) -#define PCIE_SYS_STATE38_REG (PCI_SYS_BASE + 0xB4) -#define PCIE_SYS_STATE39_REG (PCI_SYS_BASE + 0xB8) -#define PCIE_SYS_STATE40_REG (PCI_SYS_BASE + 0xBC) -#define PCIE_SYS_STATE41_REG (PCI_SYS_BASE + 0xC0) -#define PCIE_SYS_STATE42_REG (PCI_SYS_BASE + 0xC4) -#define PCIE_SYS_STATE43_REG (PCI_SYS_BASE + 0xC8) -#define PCIE_SYS_STATE44_REG (PCI_SYS_BASE + 0xCC) -#define PCIE_SYS_STATE45_REG (PCI_SYS_BASE + 0xD0) -#define PCIE_SYS_STATE46_REG (PCI_SYS_BASE + 0xD4) -#define PCIE_SYS_STATE47_REG (PCI_SYS_BASE + 0xD8) -#define PCIE_SYS_STATE48_REG (PCI_SYS_BASE + 0xDC) -#define PCIE_SYS_STATE49_REG (PCI_SYS_BASE + 0xE0) -#define PCIE_SYS_STATE50_REG (PCI_SYS_BASE + 0xE4) -#define PCIE_SYS_STATE51_REG (PCI_SYS_BASE + 0xE8) -#define PCIE_SYS_STATE52_REG (PCI_SYS_BASE + 0xEC) -#define PCIE_SYS_STATE53_REG (PCI_SYS_BASE + 0xF0) -#define PCIE_SYS_STATE54_REG (PCI_SYS_BASE + 0xF4) -#define PCIE_STAT_0_REG (PCI_SYS_BASE + 0x0) -#define PCIE_STAT_1_REG (PCI_SYS_BASE + 0x0) -#define PCIE_STAT_2_REG (PCI_SYS_BASE + 0x0) -#define PCIE_STAT_3_REG (PCI_SYS_BASE + 0x0) -#define PCIE_STAT_4_REG (PCI_SYS_BASE + 0x0) - - - -typedef union tagPcieCtrl0 -{ - - struct - { - UINT32 pcie2_slv_awmisc_info : 22 ; - UINT32 pcie2_slv_resp_err_map : 6 ; - UINT32 pcie2_slv_device_type : 4 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_0_U; - - - - -typedef union tagPcieCtrl1 -{ - - struct - { - UINT32 pcie2_slv_armisc_info : 22 ; - UINT32 pcie2_common_clocks : 1 ; - UINT32 pcie2_app_clk_req_n : 1 ; - UINT32 pcie2_ven_msg_code : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_1_U; - - - - -typedef union tagPcieCtrl2 -{ - - struct - { - UINT32 pcie2_mstr_bmisc_info : 14 ; - UINT32 pcie2_mstr_rmisc_info : 12 ; - UINT32 pcie2_ven_msi_req : 1 ; - UINT32 pcie2_ven_msi_vector : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_2_U; - - - - -typedef union tagPcieCtrl3 -{ - - struct - { - UINT32 pcie2_ven_msg_req : 1 ; - UINT32 pcie2_ven_msg_fmt : 2 ; - UINT32 pcie2_ven_msg_type : 5 ; - UINT32 pcie2_ven_msg_td : 1 ; - UINT32 pcie2_ven_msg_ep : 1 ; - UINT32 pcie2_ven_msg_attr : 2 ; - UINT32 pcie2_ven_msg_len : 10 ; - UINT32 pcie2_ven_msg_tag : 8 ; - UINT32 pcie_mstr_rresp_int_enable : 1 ; - UINT32 pcie_mstr_bresp_int_enable : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_3_U; - - - - -typedef union tagPcieCtrl7 -{ - - struct - { - UINT32 pcie2_app_init_rst : 1 ; - UINT32 pcie2_app_req_entr_l1 : 1 ; - UINT32 pcie2_app_ready_entr_l23 : 1 ; - UINT32 pcie2_app_req_exit_l1 : 1 ; - UINT32 pcie2_app_req_retry_en : 1 ; - UINT32 pcie2_sys_int : 1 ; - UINT32 pcie2_outband_pwrup_cmd : 1 ; - UINT32 pcie2_app_unlock_msg : 1 ; - UINT32 pcie2_apps_pm_xmt_turnoff : 1 ; - UINT32 pcie2_apps_pm_xmt_pme : 1 ; - UINT32 pcie2_sys_aux_pwr_det : 1 ; - UINT32 pcie2_app_ltssm_enable : 1 ; - UINT32 pcie2_cfg_pwr_ctrler_ctrl_pol : 1 ; - UINT32 Reserved_7 : 1 ; - UINT32 pcie2_sys_mrl_sensor_state : 1 ; - UINT32 pcie2_sys_pwr_fault_det : 1 ; - UINT32 pcie2_sys_mrl_sensor_chged : 1 ; - UINT32 Reserved_6 : 1 ; - UINT32 pcie2_sys_cmd_cpled_int : 1 ; - UINT32 pcie2_sys_eml_interlock_engaged : 1 ; - UINT32 pcie2_cfg_l1_clk_removal_en : 1 ; - UINT32 pcie0_int_ctrl : 8 ; - UINT32 pcie_linkdown_auto_rstn_enable : 1 ; - UINT32 pcie_err_bresp_enable : 1 ; - UINT32 pcie_err_rresp_enable : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_7_U; - - - - -typedef union tagPcieCtrl9 -{ - - struct - { - UINT32 cfg_l1_aux_clk_switch_core_clk_gate_en : 1 ; - UINT32 cfg_l1_mac_powerdown_override_to_p2_en : 1 ; - UINT32 Reserved_9 : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_9_U; - - - - -typedef union tagPcieCtrl10 -{ - - struct - { - UINT32 cfg_aer_rc_err_msi_mask : 1 ; - UINT32 cfg_sys_err_rc_mask : 1 ; - UINT32 radm_correctable_err_mask : 1 ; - UINT32 radm_nonfatal_err_mask : 1 ; - UINT32 radm_fatal_err_mask : 1 ; - UINT32 radm_pm_pme_mask : 1 ; - UINT32 radm_pm_to_ack_mask : 1 ; - UINT32 ven_msi_int_mask : 1 ; - UINT32 radm_cpl_timeout_mask : 1 ; - UINT32 radm_msg_unlock_mask : 1 ; - UINT32 cfg_pme_msi_mask : 1 ; - UINT32 bridge_flush_not_mask : 1 ; - UINT32 link_req_rst_not_mask : 1 ; - UINT32 pcie_p2_exit_int_mask : 1 ; - UINT32 pcie_rx_lane_flip_en_tmp : 1 ; - UINT32 pcie_tx_lane_flip_en_tmp : 1 ; - UINT32 radm_pm_turnoff_mask : 1 ; - UINT32 Reserved_11 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_10_U; - - - - -typedef union tagPcieCtrl11 -{ - - struct - { - UINT32 cfg_aer_rc_err_msi_clr : 1 ; - UINT32 cfg_sys_err_rc_clr : 1 ; - UINT32 radm_correctable_err_clr : 1 ; - UINT32 radm_nonfatal_err_clr : 1 ; - UINT32 radm_fatal_err_clr : 1 ; - UINT32 radm_pm_pme_clr : 1 ; - UINT32 radm_pm_to_ack_clr : 1 ; - UINT32 ven_msi_int_clr : 1 ; - UINT32 radm_cpl_timeout_clr : 1 ; - UINT32 radm_msg_unlock_clr : 1 ; - UINT32 cfg_pme_msi_clr : 1 ; - UINT32 bridge_flush_not_clr : 1 ; - UINT32 link_req_rst_not_clr : 1 ; - UINT32 pcie_p2_exit_int_clr : 1 ; - UINT32 pcie_slv_err_int_clr : 1 ; - UINT32 pcie_mstr_err_int_clr : 1 ; - UINT32 radm_pm_turnoff_clr : 1 ; - UINT32 cfg_ntb_mode : 1 ; - UINT32 Reserved_13 : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_CTRL_11_U; - - - - -typedef union tagPcieSysCtrl12 -{ - - struct - { - UINT32 slv_awmisc_info_func_num : 1 ; - UINT32 slv_awmisc_info_vfunc_active : 1 ; - UINT32 slv_awmisc_info_vfunc_num : 1 ; - UINT32 Reserved_17 : 1 ; - UINT32 slv_armisc_info_func_num : 1 ; - UINT32 slv_armisc_info_vfunc_active : 1 ; - UINT32 slv_armisc_info_vfunc_num : 1 ; - UINT32 Reserved_16 : 1 ; - UINT32 slv_awmisc_info_nw : 1 ; - UINT32 slv_awmisc_info_ats : 2 ; - UINT32 slv_armisc_info_nw : 1 ; - UINT32 slv_armisc_info_ats : 2 ; - UINT32 mstr_bmisc_info_ats : 2 ; - UINT32 mstr_rmisc_info_ats : 2 ; - UINT32 pcie_rfs_ctrl : 6 ; - UINT32 pcie_rft_ctrl : 7 ; - UINT32 Reserved_15 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_CTRL12_U; - - - - -typedef union tagPcieSysCtrl16 -{ - - struct - { - UINT32 app_flr_pf_done : 1 ; - UINT32 app_flr_vf_done : 2 ; - UINT32 Reserved_23 : 5 ; - UINT32 ven_msi_vfunc_active : 1 ; - UINT32 ven_msi_vfunc_num : 1 ; - UINT32 ven_msg_vfunc_active : 1 ; - UINT32 ven_msg_vfunc_num : 1 ; - UINT32 Reserved_22 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_CTRL16_U; - - - - -typedef union tagPcieSysCtrl20 -{ - - struct - { - UINT32 ro_sel : 1 ; - UINT32 dbi_func_num : 1 ; - UINT32 dbi_vfunc_num : 1 ; - UINT32 dbi_vfunc_active : 1 ; - UINT32 dbi_addr_h20 : 20 ; - UINT32 dbi_bar_num : 3 ; - UINT32 dbi_rom_access : 1 ; - UINT32 dbi_io_access : 1 ; - UINT32 memicg_bypass : 1 ; - UINT32 Reserved_28 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_CTRL20_U; - - - - -typedef union tagPcieSysCtrl21 -{ - - struct - { - UINT32 pcie_sys_pre_det_state : 1 ; - UINT32 pcie_sys_atten_button_pressed : 1 ; - UINT32 Reserved_30 : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_CTRL21_U; - - - - -typedef union tagPcieSysCtrl23 -{ - - struct - { - UINT32 Reserved_35 : 2 ; - UINT32 Reserved_34 : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_CTRL23_U; - - - - -typedef union tagPcieSysState5 -{ - - struct - { - UINT32 mstr_awmisc_info_func_num : 1 ; - UINT32 mstr_awmisc_info_vfunc_active : 1 ; - UINT32 mstr_awmisc_info_vfunc_num : 1 ; - UINT32 Reserved_39 : 1 ; - UINT32 mstr_armisc_info_func_num : 1 ; - UINT32 mstr_armisc_info_vfunc_active : 1 ; - UINT32 mstr_armisc_info_vfunc_num : 1 ; - UINT32 Reserved_38 : 1 ; - UINT32 mstr_awmisc_info_nw : 1 ; - UINT32 mstr_awmisc_info_ats : 2 ; - UINT32 mstr_armisc_info_nw : 1 ; - UINT32 mstr_armisc_info_ats : 2 ; - UINT32 slv_bmisc_info_ats : 2 ; - UINT32 slv_rmisc_info_ats : 2 ; - UINT32 Reserved_37 : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE5_U; - - - - -typedef union tagPcieSysState6 -{ - - struct - { - UINT32 cfg_flr_pf_active : 1 ; - UINT32 cfg_flr_vf_active : 2 ; - UINT32 Reserved_41 : 29 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE6_U; - - - - -typedef union tagPcieSysState7 -{ - - struct - { - UINT32 radm_timeout_vfunc_active : 1 ; - UINT32 radm_timeout_vfunc_num : 1 ; - UINT32 trgt_timeout_cpl_vfunc_active : 1 ; - UINT32 trgt_timeout_cpl_vfunc_num : 1 ; - UINT32 Reserved_43 : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE7_U; - - - - -typedef union tagPcieSysState11 -{ - - struct - { - UINT32 cfg_msi_64 : 1 ; - UINT32 cfg_vf_msi_en : 2 ; - UINT32 cfg_vf_msi_64 : 2 ; - UINT32 cfg_multi_msi_en : 3 ; - UINT32 cfg_vf_multi_msi_en : 6 ; - UINT32 Reserved_48 : 2 ; - UINT32 cfg_msi_data : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE11_U; - - - - -typedef union tagPcieSysState12 -{ - - struct - { - UINT32 cfg_vf_en : 1 ; - UINT32 cfg_ari_fwd_en : 1 ; - UINT32 cfg_vf_bme : 2 ; - UINT32 Reserved_51 : 4 ; - UINT32 cfg_num_vf : 16 ; - UINT32 Reserved_50 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE12_U; - - - - -typedef union tagPcieSysState20 -{ - - struct - { - UINT32 slv_bmisc_info : 11 ; - UINT32 slv_rmisc_info : 11 ; - UINT32 rtlh_rfc_upd : 1 ; - UINT32 Reserved_60 : 9 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE20_U; - - - - -typedef union tagPcieSysState21 -{ - - struct - { - UINT32 cfg_msix_en : 1 ; - UINT32 cfg_msix_func_mask : 1 ; - UINT32 cfg_vf_msix_func_mask : 2 ; - UINT32 cfg_vf_msix_en : 2 ; - UINT32 Reserved_62 : 26 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE21_U; - - - - -typedef union tagPcieSysState22 -{ - - struct - { - UINT32 lbc_ext_vfunc_active : 1 ; - UINT32 lbc_ext_vfunc_num : 1 ; - UINT32 lbc_dbi_ack : 1 ; - UINT32 pcie_mstr_awmisc_info : 24 ; - UINT32 Reserved_64 : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE22_U; - - - - -typedef union tagPcieSysState27 -{ - - struct - { - UINT32 trgt_cpl_timeout : 1 ; - UINT32 trgt_timeout_cpl_func_num : 1 ; - UINT32 trgt_timeout_cpl_tc : 3 ; - UINT32 trgt_timeout_cpl_attr : 2 ; - UINT32 trgt_timeout_cpl_len : 12 ; - UINT32 trgt_lookup_empty : 1 ; - UINT32 Reserved_70 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE27_U; - - - - -typedef union tagPcieSysState28 -{ - - struct - { - UINT32 trgt_timeout_lookup_id : 8 ; - UINT32 trgt_lookup_id : 8 ; - UINT32 radm_timeout_cpl_tag : 8 ; - UINT32 Reserved_72 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE28_U; - - - - -typedef union tagPcieSysState29 -{ - - struct - { - UINT32 trgt_cpl_timeout : 1 ; - UINT32 radm_timeout_func_num : 1 ; - UINT32 radm_timeout_cpl_tc : 3 ; - UINT32 radm_timeout_cpl_attr : 2 ; - UINT32 radm_timeout_cpl_len : 12 ; - UINT32 radm_pm_turnoff : 1 ; - UINT32 Reserved_74 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE29_U; - - - - -typedef union tagPcieSysState30 -{ - - struct - { - UINT32 cfg_pbus_num : 8 ; - UINT32 cfg_pbus_dev_num : 5 ; - UINT32 cfg_link_auto_bw_int : 1 ; - UINT32 cfg_bw_mgt_int : 1 ; - UINT32 Reserved_76 : 17 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE30_U; - - - - -typedef union tagPcieSysState32 -{ - - struct - { - UINT32 mstr_awmisc_info_dma : 6 ; - UINT32 mstr_armisc_info_dma : 6 ; - UINT32 cfg_hw_auto_sp_dis : 1 ; - UINT32 link_timeout_flush_not : 1 ; - UINT32 mac_phy_clk_req_n : 1 ; - UINT32 wake_ref_rst_n : 1 ; - UINT32 pcie_wake : 1 ; - UINT32 Reserved_79 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE32_U; - - - - -typedef union tagPcieSysState39 -{ - - struct - { - UINT32 radm_msg_unlock_reqid : 16 ; - UINT32 radm_nonfatal_err_reqid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE39_U; - - - - -typedef union tagPcieSysState44 -{ - - struct - { - UINT32 radm_unlock_reqid : 16 ; - UINT32 radm_nonfatal_err_reqid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE44_U; - - - - -typedef union tagPcieSysState49 -{ - - struct - { - UINT32 radm_pm_pme_reqid : 16 ; - UINT32 radm_pm_ack_to_reqid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_SYS_STATE49_U; - - - - -typedef union tagPcieStat0 -{ - - struct - { - UINT32 pcie2_gm_cmposer_lookup_err : 1 ; - UINT32 pcie2_radmx_cmposer_lookup_err : 1 ; - UINT32 pcie2_cfg_pwr_ind : 2 ; - UINT32 pcie2_cfg_atten_ind : 2 ; - UINT32 pcie2_cfg_pwr_ctrler_ctrl : 1 ; - UINT32 pcie2_pm_xtlh_block_tlp : 1 ; - UINT32 pcie2_cfg_mem_space_en : 1 ; - UINT32 pcie2_cfg_rcb : 1 ; - UINT32 pcie2_rdlh_link_up : 1 ; - UINT32 pcie2_pm_curnt_state : 3 ; - UINT32 pcie2_cfg_aer_rc_err_int : 1 ; - UINT32 Reserved_106 : 1 ; - UINT32 pcie2_cfg_aer_int_msg_num : 5 ; - UINT32 Reserved_105 : 1 ; - UINT32 pcie2_xmlh_link_up : 1 ; - UINT32 pcie2_wake : 1 ; - UINT32 pcie2_cfg_eml_control : 1 ; - UINT32 pcie2_hp_pme : 1 ; - UINT32 pcie2_hp_int : 1 ; - UINT32 pcie2_hp_msi : 1 ; - UINT32 pcie2_pm_status : 1 ; - UINT32 pcie2_ref_clk_req_n : 1 ; - UINT32 Reserved_104 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_STAT_0_U; - - - - -typedef union tagPcieStat1 -{ - - struct - { - UINT32 axi_parity_errs_reg : 4 ; - UINT32 app_parity_errs_reg : 3 ; - UINT32 pm_linkst_in_l1 : 1 ; - UINT32 pm_linkst_in_l2 : 1 ; - UINT32 pm_linkst_l2_exit : 1 ; - UINT32 mac_phy_power_down : 2 ; - UINT32 radm_correctabl_err_reg : 1 ; - UINT32 radm_nonfatal_err_reg : 1 ; - UINT32 radm_fatal_err_reg : 1 ; - UINT32 radm_pm_to_pme_reg : 1 ; - UINT32 radm_pm_to_ack_reg : 1 ; - UINT32 radm_cpl_timeout_reg : 1 ; - UINT32 radm_msg_unlock_reg : 1 ; - UINT32 cfg_pme_msi_reg : 1 ; - UINT32 bridge_flush_not_reg : 1 ; - UINT32 link_req_rst_not_reg : 1 ; - UINT32 pcie2_cfg_aer_rc_err_msi : 1 ; - UINT32 pcie2_cfg_sys_err_rc : 1 ; - UINT32 Reserved_107 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_STAT_1_U; - - - - -typedef union tagPcieStat3 -{ - - struct - { - UINT32 radm_msg_req_id : 16 ; - UINT32 Reserved_108 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_STAT_3_U; - - - - -typedef union tagPcieStat4 -{ - - struct - { - UINT32 ltssm_state : 6 ; - UINT32 mac_phy_rate : 2 ; - UINT32 pcie_slv_err_int_state : 1 ; - UINT32 retry_sram_addr : 10 ; - UINT32 pcie_mstr_rresp_int_state : 1 ; - UINT32 pcie_mstr_bresp_int_state : 1 ; - UINT32 pcie_radm_inta_int_state : 1 ; - UINT32 pcie_radm_intb_int_state : 1 ; - UINT32 pcie_radm_intc_int_state : 1 ; - UINT32 pcie_radm_intd_int_state : 1 ; - UINT32 pme_int_state : 1 ; - UINT32 radm_vendr_msg_int_state : 1 ; - UINT32 Reserved_109 : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_STAT_4_U; - - -#define PCIE_MUL_BASE (0x1000) - - - - -#define PCIE_MUL_MC_CTRL_REG (PCIE_MUL_BASE + 0x0) -#define PCIE_MUL_CFG_WIN0_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4) -#define PCIE_MUL_CFG_WIN0_BAR_UPPER_REG (PCIE_MUL_BASE + 0x8) -#define PCIE_MUL_CFG_WIN1_BAR_LOWER_REG (PCIE_MUL_BASE + 0xC) -#define PCIE_MUL_CFG_WIN1_BAR_UPPER_REG (PCIE_MUL_BASE + 0x10) -#define PCIE_MUL_CFG_WIN2_BAR_LOWER_REG (PCIE_MUL_BASE + 0x14) -#define PCIE_MUL_CFG_WIN2_BAR_UPPER_REG (PCIE_MUL_BASE + 0x18) -#define PCIE_MUL_CFG_WIN3_BAR_LOWER_REG (PCIE_MUL_BASE + 0x1C) -#define PCIE_MUL_CFG_WIN3_BAR_UPPER_REG (PCIE_MUL_BASE + 0x20) -#define PCIE_MUL_CFG_WIN4_BAR_LOWER_REG (PCIE_MUL_BASE + 0x24) -#define PCIE_MUL_CFG_WIN4_BAR_UPPER_REG (PCIE_MUL_BASE + 0x28) -#define PCIE_MUL_CFG_WIN5_BAR_LOWER_REG (PCIE_MUL_BASE + 0x2C) -#define PCIE_MUL_CFG_WIN5_BAR_UPPER_REG (PCIE_MUL_BASE + 0x30) -#define PCIE_MUL_CFG_WIN6_BAR_LOWER_REG (PCIE_MUL_BASE + 0x34) -#define PCIE_MUL_CFG_WIN6_BAR_UPPER_REG (PCIE_MUL_BASE + 0x38) -#define PCIE_MUL_CFG_WIN7_BAR_LOWER_REG (PCIE_MUL_BASE + 0x3C) -#define PCIE_MUL_CFG_WIN7_BAR_UPPER_REG (PCIE_MUL_BASE + 0x40) -#define PCIE_MUL_CFG_WIN8_BAR_LOWER_REG (PCIE_MUL_BASE + 0x44) -#define PCIE_MUL_CFG_WIN8_BAR_UPPER_REG (PCIE_MUL_BASE + 0x48) -#define PCIE_MUL_CFG_WIN9_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4C) -#define PCIE_MUL_CFG_WIN9_BAR_UPPER_REG (PCIE_MUL_BASE + 0x50) -#define PCIE_MUL_CFG_WIN10_BAR_LOWER_REG (PCIE_MUL_BASE + 0x54) -#define PCIE_MUL_CFG_WIN10_BAR_UPPER_REG (PCIE_MUL_BASE + 0x58) -#define PCIE_MUL_CFG_WIN11_BAR_LOWER_REG (PCIE_MUL_BASE + 0x5C) -#define PCIE_MUL_CFG_WIN11_BAR_UPPER_REG (PCIE_MUL_BASE + 0x60) -#define PCIE_MUL_CFG_WIN12_BAR_LOWER_REG (PCIE_MUL_BASE + 0x64) -#define PCIE_MUL_CFG_WIN12_BAR_UPPER_REG (PCIE_MUL_BASE + 0x68) -#define PCIE_MUL_CFG_WIN13_BAR_LOWER_REG (PCIE_MUL_BASE + 0x6C) -#define PCIE_MUL_CFG_WIN13_BAR_UPPER_REG (PCIE_MUL_BASE + 0x70) -#define PCIE_MUL_CFG_WIN14_BAR_LOWER_REG (PCIE_MUL_BASE + 0x74) -#define PCIE_MUL_CFG_WIN14_BAR_UPPER_REG (PCIE_MUL_BASE + 0x78) -#define PCIE_MUL_CFG_WIN15_BAR_LOWER_REG (PCIE_MUL_BASE + 0x7C) -#define PCIE_MUL_CFG_WIN15_BAR_UPPER_REG (PCIE_MUL_BASE + 0x80) -#define PCIE_MUL_CFG_WIN0_SIZE_REG (PCIE_MUL_BASE + 0x84) -#define PCIE_MUL_CFG_WIN1_SIZE_REG (PCIE_MUL_BASE + 0x88) -#define PCIE_MUL_CFG_WIN2_SIZE_REG (PCIE_MUL_BASE + 0x8C) -#define PCIE_MUL_CFG_WIN3_SIZE_REG (PCIE_MUL_BASE + 0x90) -#define PCIE_MUL_CFG_WIN4_SIZE_REG (PCIE_MUL_BASE + 0x94) -#define PCIE_MUL_CFG_WIN5_SIZE_REG (PCIE_MUL_BASE + 0x98) -#define PCIE_MUL_CFG_WIN6_SIZE_REG (PCIE_MUL_BASE + 0x9C) -#define PCIE_MUL_CFG_WIN7_SIZE_REG (PCIE_MUL_BASE + 0xA0) -#define PCIE_MUL_CFG_WIN8_SIZE_REG (PCIE_MUL_BASE + 0xA4) -#define PCIE_MUL_CFG_WIN9_SIZE_REG (PCIE_MUL_BASE + 0xA8) -#define PCIE_MUL_CFG_WIN10_SIZE_REG (PCIE_MUL_BASE + 0xAC) -#define PCIE_MUL_CFG_WIN11_SIZE_REG (PCIE_MUL_BASE + 0xB0) -#define PCIE_MUL_CFG_WIN12_SIZE_REG (PCIE_MUL_BASE + 0xB4) -#define PCIE_MUL_CFG_WIN13_SIZE_REG (PCIE_MUL_BASE + 0xB8) -#define PCIE_MUL_CFG_WIN14_SIZE_REG (PCIE_MUL_BASE + 0xBC) -#define PCIE_MUL_CFG_WIN15_SIZE_REG (PCIE_MUL_BASE + 0xC0) -#define PCIE_MUL_CFG_WIN0_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xC4) -#define PCIE_MUL_CFG_WIN0_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xC8) -#define PCIE_MUL_CFG_WIN1_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xCC) -#define PCIE_MUL_CFG_WIN1_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD0) -#define PCIE_MUL_CFG_WIN2_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xD4) -#define PCIE_MUL_CFG_WIN2_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD8) -#define PCIE_MUL_CFG_WIN3_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xDC) -#define PCIE_MUL_CFG_WIN3_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE0) -#define PCIE_MUL_CFG_WIN4_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xE4) -#define PCIE_MUL_CFG_WIN4_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE8) -#define PCIE_MUL_CFG_WIN5_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xEC) -#define PCIE_MUL_CFG_WIN5_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF0) -#define PCIE_MUL_CFG_WIN6_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xF4) -#define PCIE_MUL_CFG_WIN6_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF8) -#define PCIE_MUL_CFG_WIN7_XLAT_LOWER_REG (PCIE_MUL_BASE + 0xFC) -#define PCIE_MUL_CFG_WIN7_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x100) -#define PCIE_MUL_CFG_WIN8_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x104) -#define PCIE_MUL_CFG_WIN8_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x108) -#define PCIE_MUL_CFG_WIN9_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x10C) -#define PCIE_MUL_CFG_WIN9_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x110) -#define PCIE_MUL_CFG_WIN10_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x114) -#define PCIE_MUL_CFG_WIN10_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x118) -#define PCIE_MUL_CFG_WIN11_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x11C) -#define PCIE_MUL_CFG_WIN11_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x120) -#define PCIE_MUL_CFG_WIN12_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x124) -#define PCIE_MUL_CFG_WIN12_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x128) -#define PCIE_MUL_CFG_WIN13_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x12C) -#define PCIE_MUL_CFG_WIN13_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x130) -#define PCIE_MUL_CFG_WIN14_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x134) -#define PCIE_MUL_CFG_WIN14_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x138) -#define PCIE_MUL_CFG_WIN15_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x13C) -#define PCIE_MUL_CFG_WIN15_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x140) -#define PCIE_MUL_CFG_WIN_XLAT_EN_REG (PCIE_MUL_BASE + 0x144) -#define PCIE_MUL_CFG_MCAST_CMD_TIMEOUT_REG (PCIE_MUL_BASE + 0x148) -#define PCIE_MUL_CFG_INT_STATUS_REG (PCIE_MUL_BASE + 0x14C) -#define PCIE_MUL_CFG_INJECT_ECC_ERR_REG (PCIE_MUL_BASE + 0x150) - - - - -typedef union tagMcCtrl -{ - - struct - { - UINT32 cfg_mcast_en : 1 ; - UINT32 cfg_win0_mcast_en : 1 ; - UINT32 cfg_win1_mcast_en : 1 ; - UINT32 cfg_win2_mcast_en : 1 ; - UINT32 cfg_win3_mcast_en : 1 ; - UINT32 cfg_win4_mcast_en : 1 ; - UINT32 cfg_win5_mcast_en : 1 ; - UINT32 cfg_win6_mcast_en : 1 ; - UINT32 cfg_win7_mcast_en : 1 ; - UINT32 cfg_win8_mcast_en : 1 ; - UINT32 cfg_win9_mcast_en : 1 ; - UINT32 cfg_win10_mcast_en : 1 ; - UINT32 cfg_win11_mcast_en : 1 ; - UINT32 cfg_win12_mcast_en : 1 ; - UINT32 cfg_win13_mcast_en : 1 ; - UINT32 cfg_win14_mcast_en : 1 ; - UINT32 cfg_win15_mcast_en : 1 ; - UINT32 Reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_mc_ctrl_u; - - - - -typedef union tagCfgWin0Size -{ - - struct - { - UINT32 cfg_win0_size : 6 ; - UINT32 Reserved_1 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win0_size_u; - - - - -typedef union tagCfgWin1Size -{ - - struct - { - UINT32 cfg_win1_size : 6 ; - UINT32 Reserved_2 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win1_size_u; - - - - -typedef union tagCfgWin2Size -{ - - struct - { - UINT32 cfg_win2_size : 6 ; - UINT32 Reserved_3 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win2_size_u; - - - - -typedef union tagCfgWin3Size -{ - - struct - { - UINT32 cfg_win3_size : 6 ; - UINT32 Reserved_4 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win3_size_u; - - - - -typedef union tagCfgWin4Size -{ - - struct - { - UINT32 cfg_win4_size : 6 ; - UINT32 Reserved_5 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win4_size_u; - - - - -typedef union tagCfgWin5Size -{ - - struct - { - UINT32 cfg_win5_size : 6 ; - UINT32 Reserved_6 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win5_size_u; - - - - -typedef union tagCfgWin6Size -{ - - struct - { - UINT32 cfg_win6_size : 6 ; - UINT32 Reserved_7 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win6_size_u; - - - - -typedef union tagCfgWin7Size -{ - - struct - { - UINT32 cfg_win7_size : 6 ; - UINT32 Reserved_8 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win7_size_u; - - - - -typedef union tagCfgWin8Size -{ - - struct - { - UINT32 cfg_win8_size : 6 ; - UINT32 Reserved_9 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win8_size_u; - - - - -typedef union tagCfgWin9Size -{ - - struct - { - UINT32 cfg_win9_size : 6 ; - UINT32 Reserved_10 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win9_size_u; - - - - -typedef union tagCfgWin10Size -{ - - struct - { - UINT32 cfg_win10_size : 6 ; - UINT32 Reserved_11 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win10_size_u; - - - - -typedef union tagCfgWin11Size -{ - - struct - { - UINT32 cfg_win11_size : 6 ; - UINT32 Reserved_12 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win11_size_u; - - - - -typedef union tagCfgWin12Size -{ - - struct - { - UINT32 cfg_win12_size : 6 ; - UINT32 Reserved_13 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win12_size_u; - - - - -typedef union tagCfgWin13Size -{ - - struct - { - UINT32 cfg_win13_size : 6 ; - UINT32 Reserved_14 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win13_size_u; - - - - -typedef union tagCfgWin14Size -{ - - struct - { - UINT32 cfg_win14_size : 6 ; - UINT32 Reserved_15 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win14_size_u; - - - - -typedef union tagCfgWin15Size -{ - - struct - { - UINT32 cfg_win15_size : 6 ; - UINT32 Reserved_16 : 26 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win15_size_u; - - - - -typedef union tagCfgWinXlatEn -{ - - struct - { - UINT32 cfg_win0_xlat_en : 1 ; - UINT32 cfg_win1_xlat_en : 1 ; - UINT32 cfg_win2_xlat_en : 1 ; - UINT32 cfg_win3_xlat_en : 1 ; - UINT32 cfg_win4_xlat_en : 1 ; - UINT32 cfg_win5_xlat_en : 1 ; - UINT32 cfg_win6_xlat_en : 1 ; - UINT32 cfg_win7_xlat_en : 1 ; - UINT32 cfg_win8_xlat_en : 1 ; - UINT32 cfg_win9_xlat_en : 1 ; - UINT32 cfg_win10_xlat_en : 1 ; - UINT32 cfg_win11_xlat_en : 1 ; - UINT32 cfg_win12_xlat_en : 1 ; - UINT32 cfg_win13_xlat_en : 1 ; - UINT32 cfg_win14_xlat_en : 1 ; - UINT32 cfg_win15_xlat_en : 1 ; - UINT32 Reserved_17 : 16 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_win_xlat_en_u; - - - - -typedef union tagCfgMcastCmdTimeout -{ - - struct - { - UINT32 cfg_mcast_cmd_timeout : 10 ; - UINT32 Reserved_18 : 22 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_mcast_cmd_timeout_u; - - - - -typedef union tagCfgIntStatus -{ - - struct - { - UINT32 timeout_int : 1 ; - UINT32 ecc_err1_int : 1 ; - UINT32 ecc_err2_int : 1 ; - UINT32 Reserved_19 : 29 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_int_status_u; - - - - -typedef union tagCfgInjectEccErr -{ - - struct - { - UINT32 ecc_err_inject_en : 1 ; - UINT32 Reserved_20 : 31 ; - } Bits; - - - UINT32 UInt32; - -} pcie_mul_cfg_inject_ecc_err_u; - - -#define PCIE_EP_BASE (0x00000000) - - - - -#define PCIE_EP_PCI_CFG_HDR0_REG (PCIE_EP_BASE + 0x0) -#define PCIE_EP_PCI_CFG_HDR1_REG (PCIE_EP_BASE + 0x4) -#define PCIE_EP_PCI_CFG_HDR2_REG (PCIE_EP_BASE + 0x8) -#define PCIE_EP_PCI_CFG_HDR3_REG (PCIE_EP_BASE + 0xC) -#define PCIE_EP_PCI_CFG_HDR4_REG (PCIE_EP_BASE + 0x10) -#define PCIE_EP_PCI_CFG_HDR5_REG (PCIE_EP_BASE + 0x14) -#define PCIE_EP_PCI_CFG_HDR6_REG (PCIE_EP_BASE + 0x18) -#define PCIE_EP_PCI_CFG_HDR7_REG (PCIE_EP_BASE + 0x1C) -#define PCIE_EP_PCI_CFG_HDR8_REG (PCIE_EP_BASE + 0x20) -#define PCIE_EP_PCI_CFG_HDR9_REG (PCIE_EP_BASE + 0x24) -#define PCIE_EP_PCI_CFG_HDR10_REG (PCIE_EP_BASE + 0x28) -#define PCIE_EP_PCI_CFG_HDR11_REG (PCIE_EP_BASE + 0x2C) -#define PCIE_EP_PCI_CFG_HDR12_REG (PCIE_EP_BASE + 0x30) -#define PCIE_EP_PCI_CFG_HDR13_REG (PCIE_EP_BASE + 0x34) -#define PCIE_EP_PCI_CFG_HDR14_REG (PCIE_EP_BASE + 0x38) -#define PCIE_EP_PCI_CFG_HDR15_REG (PCIE_EP_BASE + 0x3C) -#define PCIE_EP_PCI_PM_CAP0_REG (PCIE_EP_BASE + 0x40) -#define PCIE_EP_PCI_PM_CAP1_REG (PCIE_EP_BASE + 0x44) -#define PCIE_EP_PCI_MSI_CAP0_REG (PCIE_EP_BASE + 0x50) -#define PCIE_EP_PCI_MSI_CAP1_REG (PCIE_EP_BASE + 0x54) -#define PCIE_EP_PCI_MSI_CAP2_REG (PCIE_EP_BASE + 0x58) -#define PCIE_EP_PCI_MSI_CAP3_REG (PCIE_EP_BASE + 0x5C) -#define PCIE_EP_PCIE_CAP0_REG (PCIE_EP_BASE + 0x70) -#define PCIE_EP_PCIE_CAP1_REG (PCIE_EP_BASE + 0x74) -#define PCIE_EP_PCIE_CAP2_REG (PCIE_EP_BASE + 0x78) -#define PCIE_EP_PCIE_CAP3_REG (PCIE_EP_BASE + 0x7C) -#define PCIE_EP_PCIE_CAP4_REG (PCIE_EP_BASE + 0x80) -#define PCIE_EP_PCIE_CAP5_REG (PCIE_EP_BASE + 0x84) -#define PCIE_EP_PCIE_CAP6_REG (PCIE_EP_BASE + 0x88) -#define PCIE_EP_PCIE_CAP7_REG (PCIE_EP_BASE + 0x8C) -#define PCIE_EP_PCIE_CAP8_REG (PCIE_EP_BASE + 0x90) -#define PCIE_EP_PCIE_CAP9_REG (PCIE_EP_BASE + 0x94) -#define PCIE_EP_PCIE_CAP10_REG (PCIE_EP_BASE + 0x98) -#define PCIE_EP_PCIE_CAP11_REG (PCIE_EP_BASE + 0x9C) -#define PCIE_EP_PCIE_CAP12_REG (PCIE_EP_BASE + 0xA0) -#define PCIE_EP_SLOT_CAP_REG (PCIE_EP_BASE + 0xC0) -#define PCIE_EP_AER_CAP0_REG (PCIE_EP_BASE + 0x100) -#define PCIE_EP_AER_CAP1_REG (PCIE_EP_BASE + 0x104) -#define PCIE_EP_AER_CAP2_REG (PCIE_EP_BASE + 0x108) -#define PCIE_EP_AER_CAP3_REG (PCIE_EP_BASE + 0x10C) -#define PCIE_EP_AER_CAP4_REG (PCIE_EP_BASE + 0x110) -#define PCIE_EP_AER_CAP5_REG (PCIE_EP_BASE + 0x114) -#define PCIE_EP_AER_CAP6_REG (PCIE_EP_BASE + 0x118) -#define PCIE_EP_AER_CAP7_REG (PCIE_EP_BASE + 0x11C) -#define PCIE_EP_AER_CAP8_REG (PCIE_EP_BASE + 0x120) -#define PCIE_EP_AER_CAP9_REG (PCIE_EP_BASE + 0x124) -#define PCIE_EP_AER_CAP10_REG (PCIE_EP_BASE + 0x128) -#define PCIE_EP_AER_CAP11_REG (PCIE_EP_BASE + 0x12C) -#define PCIE_EP_AER_CAP12_REG (PCIE_EP_BASE + 0x130) -#define PCIE_EP_AER_CAP13_REG (PCIE_EP_BASE + 0x134) -#define PCIE_EP_VC_CAP0_REG (PCIE_EP_BASE + 0x140) -#define PCIE_EP_VC_CAP1_REG (PCIE_EP_BASE + 0x144) -#define PCIE_EP_VC_CAP2_REG (PCIE_EP_BASE + 0x148) -#define PCIE_EP_VC_CAP3_REG (PCIE_EP_BASE + 0x14C) -#define PCIE_EP_VC_CAP4_REG (PCIE_EP_BASE + 0x150) -#define PCIE_EP_VC_CAP5_REG (PCIE_EP_BASE + 0x154) -#define PCIE_EP_VC_CAP6_REG (PCIE_EP_BASE + 0x158) -#define PCIE_EP_VC_CAP7_REG (PCIE_EP_BASE + 0x15C) -#define PCIE_EP_VC_CAP8_REG (PCIE_EP_BASE + 0x160) -#define PCIE_EP_VC_CAP9_REG (PCIE_EP_BASE + 0x164) -#define PCIE_EP_PORT_LOGIC0_REG (PCIE_EP_BASE + 0x700) -#define PCIE_EP_PORT_LOGIC1_REG (PCIE_EP_BASE + 0x704) -#define PCIE_EP_PORT_LOGIC2_REG (PCIE_EP_BASE + 0x708) -#define PCIE_EP_PORT_LOGIC3_REG (PCIE_EP_BASE + 0x0) -#define PCIE_EP_PORT_LOGIC4_REG (PCIE_EP_BASE + 0x710) -#define PCIE_EP_PORT_LOGIC5_REG (PCIE_EP_BASE + 0x714) -#define PCIE_EP_PORT_LOGIC6_REG (PCIE_EP_BASE + 0x718) -#define PCIE_EP_PORT_LOGIC7_REG (PCIE_EP_BASE + 0x71C) -#define PCIE_EP_PORT_LOGIC8_REG (PCIE_EP_BASE + 0x720) -#define PCIE_EP_PORT_LOGIC9_REG (PCIE_EP_BASE + 0x724) -#define PCIE_EP_PORT_LOGIC10_REG (PCIE_EP_BASE + 0x728) -#define PCIE_EP_PORT_LOGIC11_REG (PCIE_EP_BASE + 0x72C) -#define PCIE_EP_PORT_LOGIC12_REG (PCIE_EP_BASE + 0x730) -#define PCIE_EP_PORT_LOGIC13_REG (PCIE_EP_BASE + 0x734) -#define PCIE_EP_PORT_LOGIC14_REG (PCIE_EP_BASE + 0x738) -#define PCIE_EP_PORT_LOGIC15_REG (PCIE_EP_BASE + 0x73C) -#define PCIE_EP_PORT_LOGIC16_REG (PCIE_EP_BASE + 0x748) -#define PCIE_EP_PORT_LOGIC17_REG (PCIE_EP_BASE + 0x74C) -#define PCIE_EP_PORT_LOGIC18_REG (PCIE_EP_BASE + 0x750) -#define PCIE_EP_PORT_LOGIC19_REG (PCIE_EP_BASE + 0x7A8) -#define PCIE_EP_PORT_LOGIC20_REG (PCIE_EP_BASE + 0x7AC) -#define PCIE_EP_PORT_LOGIC21_REG (PCIE_EP_BASE + 0x7B0) -#define PCIE_EP_PORT_LOGIC22_REG (PCIE_EP_BASE + 0x80C) -#define PCIE_EP_PORTLOGIC23_REG (PCIE_EP_BASE + 0x810) -#define PCIE_EP_PORTLOGIC24_REG (PCIE_EP_BASE + 0x814) -#define PCIE_EP_PORTLOGIC25_REG (PCIE_EP_BASE + 0x818) -#define PCIE_EP_PORTLOGIC26_REG (PCIE_EP_BASE + 0x81C) -#define PCIE_EP_PORTLOGIC27_REG (PCIE_EP_BASE + 0x820) -#define PCIE_EP_PORTLOGIC28_REG (PCIE_EP_BASE + 0x824) -#define PCIE_EP_PORTLOGIC29_REG (PCIE_EP_BASE + 0x828) -#define PCIE_EP_PORTLOGIC30_REG (PCIE_EP_BASE + 0x82C) -#define PCIE_EP_PORTLOGIC31_REG (PCIE_EP_BASE + 0x830) -#define PCIE_EP_PORTLOGIC32_REG (PCIE_EP_BASE + 0x834) -#define PCIE_EP_PORTLOGIC33_REG (PCIE_EP_BASE + 0x838) -#define PCIE_EP_PORTLOGIC34_REG (PCIE_EP_BASE + 0x83C) -#define PCIE_EP_PORTLOGIC35_REG (PCIE_EP_BASE + 0x840) -#define PCIE_EP_PORTLOGIC36_REG (PCIE_EP_BASE + 0x844) -#define PCIE_EP_PORTLOGIC37_REG (PCIE_EP_BASE + 0x848) -#define PCIE_EP_PORTLOGIC38_REG (PCIE_EP_BASE + 0x84C) -#define PCIE_EP_PORTLOGIC39_REG (PCIE_EP_BASE + 0x850) -#define PCIE_EP_PORTLOGIC40_REG (PCIE_EP_BASE + 0x854) -#define PCIE_EP_PORTLOGIC41_REG (PCIE_EP_BASE + 0x858) -#define PCIE_EP_PORTLOGIC42_REG (PCIE_EP_BASE + 0x85C) -#define PCIE_EP_PORTLOGIC43_REG (PCIE_EP_BASE + 0x860) -#define PCIE_EP_PORTLOGIC44_REG (PCIE_EP_BASE + 0x864) -#define PCIE_EP_PORTLOGIC45_REG (PCIE_EP_BASE + 0x868) -#define PCIE_EP_PORTLOGIC46_REG (PCIE_EP_BASE + 0x86C) -#define PCIE_EP_PORTLOGIC47_REG (PCIE_EP_BASE + 0x870) -#define PCIE_EP_PORTLOGIC48_REG (PCIE_EP_BASE + 0x874) -#define PCIE_EP_PORTLOGIC49_REG (PCIE_EP_BASE + 0x878) -#define PCIE_EP_PORTLOGIC50_REG (PCIE_EP_BASE + 0x87C) -#define PCIE_EP_PORTLOGIC51_REG (PCIE_EP_BASE + 0x880) -#define PCIE_EP_PORTLOGIC52_REG (PCIE_EP_BASE + 0x884) -#define PCIE_EP_PORTLOGIC53_REG (PCIE_EP_BASE + 0x888) -#define PCIE_EP_LINK_TIMEOUT_OFF_REG (PCIE_EP_BASE + 0x8d4) -#define PCIE_EP_PORTLOGIC54_REG (PCIE_EP_BASE + 0x900) -#define PCIE_EP_PORTLOGIC55_REG (PCIE_EP_BASE + 0x904) -#define PCIE_EP_PORTLOGIC56_REG (PCIE_EP_BASE + 0x908) -#define PCIE_EP_PORTLOGIC57_REG (PCIE_EP_BASE + 0x90C) -#define PCIE_EP_PORTLOGIC58_REG (PCIE_EP_BASE + 0x910) -#define PCIE_EP_PORTLOGIC59_REG (PCIE_EP_BASE + 0x914) -#define PCIE_EP_PORTLOGIC60_REG (PCIE_EP_BASE + 0x918) -#define PCIE_EP_PORTLOGIC61_REG (PCIE_EP_BASE + 0x91C) -#define PCIE_EP_PORTLOGIC62_REG (PCIE_EP_BASE + 0x97C) -#define PCIE_EP_PORTLOGIC63_REG (PCIE_EP_BASE + 0x980) -#define PCIE_EP_PORTLOGIC64_REG (PCIE_EP_BASE + 0x99C) -#define PCIE_EP_PORTLOGIC65_REG (PCIE_EP_BASE + 0x9A0) -#define PCIE_EP_PORTLOGIC66_REG (PCIE_EP_BASE + 0x9BC) -#define PCIE_EP_PORTLOGIC67_REG (PCIE_EP_BASE + 0x9C4) -#define PCIE_EP_PORTLOGIC68_REG (PCIE_EP_BASE + 0x9C8) -#define PCIE_EP_PORTLOGIC69_REG (PCIE_EP_BASE + 0x9CC) -#define PCIE_EP_PORTLOGIC70_REG (PCIE_EP_BASE + 0x9D0) -#define PCIE_EP_PORTLOGIC71_REG (PCIE_EP_BASE + 0x9D4) -#define PCIE_EP_PORTLOGIC72_REG (PCIE_EP_BASE + 0x9D8) -#define PCIE_EP_PORTLOGIC73_REG (PCIE_EP_BASE + 0x9DC) -#define PCIE_EP_PORTLOGIC74_REG (PCIE_EP_BASE + 0x9E0) -#define PCIE_EP_PORTLOGIC75_REG (PCIE_EP_BASE + 0xA00) -#define PCIE_EP_PORTLOGIC76_REG (PCIE_EP_BASE + 0xA10) -#define PCIE_EP_PORTLOGIC77_REG (PCIE_EP_BASE + 0xA18) -#define PCIE_EP_PORTLOGIC78_REG (PCIE_EP_BASE + 0xA1C) -#define PCIE_EP_PORTLOGIC79_REG (PCIE_EP_BASE + 0xA24) -#define PCIE_EP_PORTLOGIC80_REG (PCIE_EP_BASE + 0xA28) -#define PCIE_EP_PORTLOGIC81_REG (PCIE_EP_BASE + 0xA34) -#define PCIE_EP_PORTLOGIC82_REG (PCIE_EP_BASE + 0xA3C) -#define PCIE_EP_PORTLOGIC83_REG (PCIE_EP_BASE + 0xA40) -#define PCIE_EP_PORTLOGIC84_REG (PCIE_EP_BASE + 0xA44) -#define PCIE_EP_PORTLOGIC85_REG (PCIE_EP_BASE + 0xA48) -#define PCIE_EP_PORTLOGIC86_REG (PCIE_EP_BASE + 0xA6C) -#define PCIE_EP_PORTLOGIC87_REG (PCIE_EP_BASE + 0xA70) -#define PCIE_EP_PORTLOGIC88_REG (PCIE_EP_BASE + 0xA78) -#define PCIE_EP_PORTLOGIC89_REG (PCIE_EP_BASE + 0xA7C) -#define PCIE_EP_PORTLOGIC90_REG (PCIE_EP_BASE + 0xA80) -#define PCIE_EP_PORTLOGIC91_REG (PCIE_EP_BASE + 0xA84) -#define PCIE_EP_PORTLOGIC92_REG (PCIE_EP_BASE + 0xA88) -#define PCIE_EP_PORTLOGIC93_REG (PCIE_EP_BASE + 0xA8C) -#define PCIE_EP_PORTLOGIC94_REG (PCIE_EP_BASE + 0xA90) - - - -typedef union tagPciCfgHdr0 -{ - - struct - { - UINT32 vendor_id : 16 ; - UINT32 device_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR0_U; - - - - -typedef union tagPciCfgHdr1 -{ - - struct - { - UINT32 io_space_enable : 1 ; - UINT32 memory_space_enable : 1 ; - UINT32 bus_master_enable : 1 ; - UINT32 specialcycleenable : 1 ; - UINT32 memory_write_and_invalidate : 1 ; - UINT32 vga_palette_snoop_enable : 1 ; - UINT32 parity_error_response : 1 ; - UINT32 idsel_stepping_waitcycle_control : 1 ; - UINT32 serr_enable : 1 ; - UINT32 fastback_to_backenable : 1 ; - UINT32 interrupt_disable : 1 ; - UINT32 Reserved_2 : 5 ; - UINT32 Reserved_1 : 3 ; - UINT32 intx_status : 1 ; - UINT32 capabilitieslist : 1 ; - UINT32 pcibus66mhzcapable : 1 ; - UINT32 Reserved_0 : 1 ; - UINT32 fastback_to_back : 1 ; - UINT32 masterdataparityerror : 1 ; - UINT32 devsel_timing : 2 ; - UINT32 signaled_target_abort : 1 ; - UINT32 received_target_abort : 1 ; - UINT32 received_master_abort : 1 ; - UINT32 signaled_system_error : 1 ; - UINT32 detected_parity_error : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR1_U; - - - - -typedef union tagPciCfgHdr2 -{ - - struct - { - UINT32 revision_identification : 8 ; - UINT32 Reserved_3 : 8 ; - UINT32 sub_class : 8 ; - UINT32 baseclass : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR2_U; - - - - -typedef union tagPciCfgHdr3 -{ - - struct - { - UINT32 cache_line_size : 8 ; - UINT32 mstr_lat_tmr : 8 ; - UINT32 multi_function_device : 7 ; - UINT32 hdr_type : 1 ; - UINT32 bist : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR3_U; - - - - -typedef union tagPciCfgHdr4 -{ - - struct - { - UINT32 sbar01_space_inicator : 1 ; - UINT32 sbar01_type : 2 ; - UINT32 sbar01_prefetchable : 1 ; - UINT32 sbar01_lower : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR4_U; - - - - -typedef union tagPciCfgHdr6 -{ - - struct - { - UINT32 sbar23_space_inicator : 1 ; - UINT32 sbar23_type : 2 ; - UINT32 sbar23_prefetchable : 1 ; - UINT32 Reserved_4 : 8 ; - UINT32 sbar23_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR6_U; - -typedef union tagPciLinkTimeOut -{ - - struct - { - UINT32 link_timeout_prepriod_default : 8 ; - UINT32 link_timeout_enable_default : 1 ; - UINT32 Reserved_4 : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_LINK_TIMEOUT_OFF_U; - - - - - -typedef union tagPciCfgHdr8 -{ - - struct - { - UINT32 sbar45_space_inicator : 1 ; - UINT32 sbar45_type : 2 ; - UINT32 sbar45_prefetchable : 1 ; - UINT32 Reserved_5 : 8 ; - UINT32 sbar45_lower : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR8_U; - - - - -typedef union tagPciCfgHdr11 -{ - - struct - { - UINT32 subsystem_vendor_id : 16 ; - UINT32 subsystemid : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR11_U; - - - - -typedef union tagPciCfgHdr13 -{ - - struct - { - UINT32 capptr : 8 ; - UINT32 Reserved_6 : 24 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR13_U; - - - - -typedef union tagPciCfgHdr15 -{ - - struct - { - UINT32 int_line : 8 ; - UINT32 int_pin : 8 ; - UINT32 Min_Grant : 8 ; - UINT32 Max_Latency : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_CFG_HDR15_U; - - - - -typedef union tagPciMsiCap0 -{ - - struct - { - UINT32 msi_cap_id : 8 ; - UINT32 next_capability_pointer : 8 ; - UINT32 msi_enabled : 1 ; - UINT32 multiple_message_capable : 3 ; - UINT32 multiple_message_enabled : 3 ; - UINT32 msi_64_en : 1 ; - UINT32 pvm_en : 1 ; - UINT32 message_control_register : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_MSI_CAP0_U; - - - - -typedef union tagPciMsiCap1 -{ - - struct - { - UINT32 Reserved_11 : 2 ; - UINT32 msi_addr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_MSI_CAP1_U; - - - - -typedef union tagPciMsiCap3 -{ - - struct - { - UINT32 msi_data : 16 ; - UINT32 Reserved_12 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCI_MSI_CAP3_U; - - - - -typedef union tagPcieCap0 -{ - - struct - { - UINT32 pcie_cap_id : 8 ; - UINT32 pcie_next_ptr : 8 ; - UINT32 pcie_capability_version : 4 ; - UINT32 device_port_type : 4 ; - UINT32 slot_implemented : 1 ; - UINT32 interrupt_message_number : 5 ; - UINT32 Reserved_13 : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP0_U; - - - - -typedef union tagPcieCap1 -{ - - struct - { - UINT32 max_payload_size_supported : 3 ; - UINT32 phantom_function_supported : 2 ; - UINT32 extended_tagfield_supported : 1 ; - UINT32 endpoint_l0sacceptable_latency : 3 ; - UINT32 endpoint_l1acceptable_latency : 3 ; - UINT32 undefined : 3 ; - UINT32 Reserved_16 : 3 ; - UINT32 captured_slot_power_limit_value : 8 ; - UINT32 captured_slot_power_limit_scale : 2 ; - UINT32 function_level_reset : 1 ; - UINT32 Reserved_15 : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP1_U; - - - - -typedef union tagPcieCap2 -{ - - struct - { - UINT32 correctable_error_reporting_enable : 1 ; - UINT32 non_fatal_error_reporting_enable : 1 ; - UINT32 fatal_error_reporting_enable : 1 ; - UINT32 urenable : 1 ; - UINT32 enable_relaxed_ordering : 1 ; - UINT32 max_payload_size : 3 ; - UINT32 extended_tagfieldenable : 1 ; - UINT32 phantom_function_enable : 1 ; - UINT32 auxpowerpmenable : 1 ; - UINT32 enablenosnoop : 1 ; - UINT32 max_read_request_size : 3 ; - UINT32 Reserved_18 : 1 ; - UINT32 correctableerrordetected : 1 ; - UINT32 non_fatalerrordetected : 1 ; - UINT32 fatalerrordetected : 1 ; - UINT32 unsupportedrequestdetected : 1 ; - UINT32 auxpowerdetected : 1 ; - UINT32 transactionpending : 1 ; - UINT32 Reserved_17 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP2_U; - - - - -typedef union tagPcieCap3 -{ - - struct - { - UINT32 max_link_speed : 4 ; - UINT32 max_link_width : 6 ; - UINT32 active_state_power_management : 2 ; - UINT32 l0s_exitlatency : 3 ; - UINT32 l1_exit_latency : 3 ; - UINT32 clock_power_management : 1 ; - UINT32 surprise_down_error_report_cap : 1 ; - UINT32 data_link_layer_active_report_cap : 1 ; - UINT32 link_bandwidth_noti_cap : 1 ; - UINT32 aspm_option_compliance : 1 ; - UINT32 Reserved_19 : 1 ; - UINT32 port_number : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP3_U; - - - - -typedef union tagPcieCap4 -{ - - struct - { - UINT32 active_state_power_management : 2 ; - UINT32 Reserved_22 : 1 ; - UINT32 rcb : 1 ; - UINT32 link_disable : 1 ; - UINT32 retrain_link : 1 ; - UINT32 common_clock_config : 1 ; - UINT32 extended_sync : 1 ; - UINT32 enable_clock_pwr_management : 1 ; - UINT32 hw_auto_width_disable : 1 ; - UINT32 link_bandwidth_management_int_en : 1 ; - UINT32 link_auto_bandwidth_int_en : 1 ; - UINT32 Reserved_21 : 4 ; - UINT32 current_link_speed : 4 ; - UINT32 negotiated_link_width : 6 ; - UINT32 Reserved_20 : 1 ; - UINT32 link_training : 1 ; - UINT32 slot_clock_configration : 1 ; - UINT32 data_link_layer_active : 1 ; - UINT32 link_bandwidth_management_status : 1 ; - UINT32 link_auto_bandwidth_status : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP4_U; - - - - -typedef union tagPcieCap5 -{ - - struct - { - UINT32 attentioonbuttonpresent : 1 ; - UINT32 powercontrollerpresent : 1 ; - UINT32 mrlsensorpresent : 1 ; - UINT32 attentionindicatorpresent : 1 ; - UINT32 powerindicatorpresent : 1 ; - UINT32 hot_plugsurprise : 1 ; - UINT32 hot_plugcapable : 1 ; - UINT32 slotpowerlimitvalue : 8 ; - UINT32 slotpowerlimitscale : 2 ; - UINT32 electromechanicalinterlockpresen : 1 ; - UINT32 no_cmd_complete_support : 1 ; - UINT32 phy_slot_number : 13 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP5_U; - - - - - -typedef union tagPcieCap6 -{ - - struct - { - UINT32 attentionbuttonpressedenable : 1 ; - UINT32 powerfaultdetectedenable : 1 ; - UINT32 mrlsensorchangedenable : 1 ; - UINT32 presencedetectchangedenable : 1 ; - UINT32 commandcompletedinterruptenable : 1 ; - UINT32 hot_pluginterruptenable : 1 ; - UINT32 attentionindicatorcontrol : 2 ; - UINT32 powerindicatorcontrol : 2 ; - UINT32 powercontrollercontrol : 1 ; - UINT32 electromechanicalinterlockcontrol : 1 ; - UINT32 datalinklayerstatechangedenable : 1 ; - UINT32 Reserved_23 : 3 ; - UINT32 attentionbuttonpressed : 1 ; - UINT32 powerfaultdetected : 1 ; - UINT32 mrlsensorchanged : 1 ; - UINT32 presencedetectchanged : 1 ; - UINT32 commandcompleted : 1 ; - UINT32 mrlsensorstate : 1 ; - UINT32 presencedetectstate : 1 ; - UINT32 electromechanicalinterlockstatus : 1 ; - UINT32 datalinklayerstatechanged : 1 ; - UINT32 slot_ctrl_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP6_U; - - - - -typedef union tagPcieCap7 -{ - - struct - { - UINT32 systemerroroncorrectableerrorenable : 1 ; - UINT32 systemerroronnon_fatalerrorenable : 1 ; - UINT32 systemerroronfatalerrorenable : 1 ; - UINT32 pmeinterruptenable : 1 ; - UINT32 crssoftwarevisibilityenable : 1 ; - UINT32 Reserved_24 : 11 ; - UINT32 crssoftwarevisibility : 1 ; - UINT32 root_cap : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP7_U; - - - - -typedef union tagPcieCap8 -{ - - struct - { - UINT32 pmerequesterid : 16 ; - UINT32 pmestatus : 1 ; - UINT32 pmepending : 1 ; - UINT32 root_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP8_U; - - - - -typedef union tagPcieCap9 -{ - - struct - { - UINT32 completiontimeoutrangessupported : 4 ; - UINT32 completiontimeoutdisablesupported : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoproutingsupported : 1 ; - UINT32 _2_bitatomicopcompletersupported : 1 ; - UINT32 _4_bitatomicopcompletersupported : 1 ; - UINT32 _28_bitcascompletersupported : 1 ; - UINT32 noro_enabledpr_prpassing : 1 ; - UINT32 Reserved_25 : 1 ; - UINT32 tphcompletersupported : 2 ; - UINT32 dev_cap2 : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP9_U; - - - - -typedef union tagPcieCap10 -{ - - struct - { - UINT32 completiontimeoutvalue : 4 ; - UINT32 completiontimeoutdisable : 1 ; - UINT32 ariforwardingsupported : 1 ; - UINT32 atomicoprequesterenable : 1 ; - UINT32 atomicopegressblocking : 1 ; - UINT32 idorequestenable : 1 ; - UINT32 idocompletionenable : 1 ; - UINT32 dev_ctrl2 : 22 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP10_U; - - - - -typedef union tagPcieCap11 -{ - - struct - { - UINT32 Reserved_27 : 1 ; - UINT32 gen1_suport : 1 ; - UINT32 gen2_suport : 1 ; - UINT32 gen3_suport : 1 ; - UINT32 Reserved_26 : 4 ; - UINT32 crosslink_supported : 1 ; - UINT32 link_cap2 : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP11_U; - - - - -typedef union tagPcieCap12 -{ - - struct - { - UINT32 targetlinkspeed : 4 ; - UINT32 entercompliance : 1 ; - UINT32 hardwareautonomousspeeddisa : 1 ; - UINT32 selectablede_empha : 1 ; - UINT32 transmitmargin : 3 ; - UINT32 _entermodifiedcompliance : 1 ; - UINT32 compliancesos : 1 ; - UINT32 de_emphasislevel : 4 ; - UINT32 currentde_emphasislevel : 1 ; - UINT32 equalizationcomplete : 1 ; - UINT32 equalizationphase1successful : 1 ; - UINT32 equalizationphase2successful : 1 ; - UINT32 equalizationphase3successful : 1 ; - UINT32 linkequalizationrequest : 1 ; - UINT32 link_ctrl2_status2 : 10 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PCIE_CAP12_U; - - - - -typedef union tagSlotCap -{ - - struct - { - UINT32 slotnumberingcapabilitiesid : 8 ; - UINT32 nextcapabilitypointer : 8 ; - UINT32 add_incardslotsprovided : 5 ; - UINT32 firstinchassis : 1 ; - UINT32 Reserved_28 : 2 ; - UINT32 slot_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_SLOT_CAP_U; - - - - -typedef union tagAerCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 aer_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP0_U; - - - - -typedef union tagAerCap1 -{ - - struct - { - UINT32 Reserved_34 : 1 ; - UINT32 Reserved_33 : 3 ; - UINT32 datalinkprotocolerrorsta : 1 ; - UINT32 surprisedownerrorstatus : 1 ; - UINT32 Reserved_32 : 6 ; - UINT32 poisonedtlpstatu : 1 ; - UINT32 flowcontrolprotocolerrorst : 1 ; - UINT32 completiontimeouts : 1 ; - UINT32 completerabortstatus : 1 ; - UINT32 receiveroverflowstatus : 1 ; - UINT32 malformedtlpstatus : 1 ; - UINT32 ecrcerrorstatus : 1 ; - UINT32 ecrcerrorstat : 1 ; - UINT32 unsupportedrequesterrorstatus : 1 ; - UINT32 Reserved_31 : 3 ; - UINT32 atomicopegressblockedstatus : 1 ; - UINT32 uncorr_err_status : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP1_U; - - - - -typedef union tagAerCap2 -{ - - struct - { - UINT32 Reserved_38 : 1 ; - UINT32 Reserved_37 : 3 ; - UINT32 datalinkprotocolerrormask : 1 ; - UINT32 surprisedownerrormask : 1 ; - UINT32 Reserved_36 : 6 ; - UINT32 poisonedtlpmask : 1 ; - UINT32 flowcontrolprotocolerrormask : 1 ; - UINT32 completiontimeoutmask : 1 ; - UINT32 completerabortmask : 1 ; - UINT32 unexpectedcompletionmask : 1 ; - UINT32 receiveroverflowmask : 1 ; - UINT32 malformedtlpmask : 1 ; - UINT32 ecrcerrormask : 1 ; - UINT32 unsupportedrequesterrormask : 1 ; - UINT32 Reserved_35 : 3 ; - UINT32 atomicopegressblockedmask : 1 ; - UINT32 uncorr_err_mask : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP2_U; - - - - -typedef union tagAerCap3 -{ - - struct - { - UINT32 Reserved_42 : 1 ; - UINT32 Reserved_41 : 3 ; - UINT32 datalinkprotocolerrorsever : 1 ; - UINT32 surprisedownerrorseverity : 1 ; - UINT32 Reserved_40 : 6 ; - UINT32 poisonedtlpseverity : 1 ; - UINT32 flowcontrolprotocolerrorseveri : 1 ; - UINT32 completiontimeoutseverity : 1 ; - UINT32 completerabortseverity : 1 ; - UINT32 unexpectedcompletionseverity : 1 ; - UINT32 receiveroverflowseverity : 1 ; - UINT32 malformedtlpseverity : 1 ; - UINT32 ecrcerrorseverity : 1 ; - UINT32 unsupportedrequesterrorseverity : 1 ; - UINT32 Reserved_39 : 3 ; - UINT32 atomicopegressblockedseverity : 1 ; - UINT32 uncorr_err_ser : 7 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP3_U; - - - - -typedef union tagAerCap4 -{ - - struct - { - UINT32 receivererrorstatus : 1 ; - UINT32 Reserved_44 : 5 ; - UINT32 badtlpstatus : 1 ; - UINT32 baddllpstatus : 1 ; - UINT32 replay_numrolloverstatus : 1 ; - UINT32 Reserved_43 : 3 ; - UINT32 replytimertimeoutstatus : 1 ; - UINT32 advisorynon_fatalerrorstatus : 1 ; - UINT32 corr_err_status : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP4_U; - - - - -typedef union tagAerCap5 -{ - - struct - { - UINT32 receivererrormask : 1 ; - UINT32 Reserved_46 : 5 ; - UINT32 badtlpmask : 1 ; - UINT32 baddllpmask : 1 ; - UINT32 replay_numrollovermask : 1 ; - UINT32 Reserved_45 : 3 ; - UINT32 replytimertimeoutmask : 1 ; - UINT32 advisorynon_fatalerrormask : 1 ; - UINT32 corr_err_mask : 18 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP5_U; - - - - -typedef union tagAerCap6 -{ - - struct - { - UINT32 firsterrorpointer : 5 ; - UINT32 ecrcgenerationcapability : 1 ; - UINT32 ecrcgenerationenable : 1 ; - UINT32 ecrccheckcapable : 1 ; - UINT32 ecrccheckenable : 1 ; - UINT32 adv_cap_ctrl : 23 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP6_U; - - - - -typedef union tagAerCap11 -{ - - struct - { - UINT32 correctableerrorreportingenable : 1 ; - UINT32 non_fatalerrorreportingenable : 1 ; - UINT32 fatalerrorreportingenable : 1 ; - UINT32 root_err_cmd : 29 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP11_U; - - - - -typedef union tagAerCap12 -{ - - struct - { - UINT32 err_correceived : 1 ; - UINT32 multipleerr_correceived : 1 ; - UINT32 err_fatal_nonfatalreceived : 1 ; - UINT32 multipleerr_fatal_nonfatalreceived : 1 ; - UINT32 firstuncorrectablefatal : 1 ; - UINT32 non_fatalerrormessagesreceived : 1 ; - UINT32 fatalerrormessagesreceived : 1 ; - UINT32 Reserved_47 : 20 ; - UINT32 root_err_status : 5 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP12_U; - - - - -typedef union tagAerCap13 -{ - - struct - { - UINT32 err_corsourceidentification : 16 ; - UINT32 err_src_id : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_AER_CAP13_U; - - - - -typedef union tagVcCap0 -{ - - struct - { - UINT32 pciexpressextendedcapabilityid : 16 ; - UINT32 capabilityversion : 4 ; - UINT32 vc_cap_hdr : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP0_U; - - - - -typedef union tagVcCap1 -{ - - struct - { - UINT32 extendedvccount : 3 ; - UINT32 Reserved_50 : 1 ; - UINT32 lowpriorityextendedvccount : 3 ; - UINT32 Reserved_49 : 1 ; - UINT32 referenceclock : 2 ; - UINT32 portarbitrationtableentrysize : 2 ; - UINT32 vc_cap1 : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP1_U; - - - - -typedef union tagVcCap2 -{ - - struct - { - UINT32 vcarbitrationcapability : 8 ; - UINT32 Reserved_51 : 16 ; - UINT32 vc_cap2 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP2_U; - - - - -typedef union tagVcCap3 -{ - - struct - { - UINT32 loadvcarbitrationtable : 1 ; - UINT32 vcarbitrationselect : 3 ; - UINT32 Reserved_53 : 12 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 Reserved_52 : 15 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP3_U; - - - - -typedef union tagVcCap4 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_56 : 6 ; - UINT32 Reserved_55 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_54 : 1 ; - UINT32 vc_res_cap : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP4_U; - - - - -typedef union tagVcCap5 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_59 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselec : 3 ; - UINT32 Reserved_58 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_57 : 4 ; - UINT32 vc_res_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP5_U; - - - - -typedef union tagVcCap6 -{ - - struct - { - UINT32 Reserved_60 : 16 ; - UINT32 portarbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP6_U; - - - - -typedef union tagVcCap7 -{ - - struct - { - UINT32 portarbitrationcapability : 8 ; - UINT32 Reserved_63 : 6 ; - UINT32 Reserved_62 : 1 ; - UINT32 rejectsnooptransactions : 1 ; - UINT32 maximumtimeslots : 7 ; - UINT32 Reserved_61 : 1 ; - UINT32 vc_res_cap0 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP7_U; - - - - -typedef union tagVcCap8 -{ - - struct - { - UINT32 tc_vcmap : 8 ; - UINT32 Reserved_66 : 8 ; - UINT32 loadportarbitrationtable : 1 ; - UINT32 portarbitrationselect : 3 ; - UINT32 Reserved_65 : 4 ; - UINT32 vcid : 3 ; - UINT32 Reserved_64 : 4 ; - UINT32 vc_res_ctrl0 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP8_U; - - - - -typedef union tagVcCap9 -{ - - struct - { - UINT32 Reserved_67 : 16 ; - UINT32 arbitrationtablestatus : 1 ; - UINT32 vcnegotiationpending : 1 ; - UINT32 vc_res_status0 : 14 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_VC_CAP9_U; - - - - -typedef union tagPortLogic0 -{ - - struct - { - UINT32 ack_lat_timer : 16 ; - UINT32 replay_timer : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC0_U; - - - - -typedef union tagPortLogic2 -{ - - struct - { - UINT32 linknumber : 8 ; - UINT32 Reserved_70 : 7 ; - UINT32 forcelink : 1 ; - UINT32 linkstate : 6 ; - UINT32 Reserved_69 : 2 ; - UINT32 port_force_link : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC2_U; - - - - -typedef union tagPortLogic3 -{ - - struct - { - UINT32 ackfrequency : 8 ; - UINT32 n_fts : 8 ; - UINT32 commonclockn_fts : 8 ; - UINT32 l0sentrancelatency : 3 ; - UINT32 l1entrancelatency : 3 ; - UINT32 enteraspml1withoutreceiveinl0s : 1 ; - UINT32 ack_aspm : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC3_U; - - - - -typedef union tagPortLogic4 -{ - - struct - { - UINT32 vendorspecificdllprequest : 1 ; - UINT32 scrambledisable : 1 ; - UINT32 loopbackenable : 1 ; - UINT32 resetassert : 1 ; - UINT32 Reserved_73 : 1 ; - UINT32 dlllinkenable : 1 ; - UINT32 Reserved_72 : 1 ; - UINT32 fastlinkmode : 1 ; - UINT32 Reserved_71 : 8 ; - UINT32 linkmodeenable : 6 ; - UINT32 crosslinkenable : 1 ; - UINT32 crosslinkactive : 1 ; - UINT32 port_link_ctrl : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC4_U; - - - - -typedef union tagPortLogic5 -{ - - struct - { - UINT32 insertlaneskewfortransmit : 24 ; - UINT32 flowcontroldisable : 1 ; - UINT32 ack_nakdisable : 1 ; - UINT32 Reserved_75 : 5 ; - UINT32 lane_skew : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC5_U; - - - - -typedef union tagPortLogic6 -{ - - struct - { - UINT32 numberoftssymbols : 4 ; - UINT32 Reserved_77 : 4 ; - UINT32 numberofskpsymbols : 3 ; - UINT32 Reserved_76 : 3 ; - UINT32 timermodifierforreplaytimer : 5 ; - UINT32 timermodifierforack_naklatencytimer : 5 ; - UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; - UINT32 sym_num : 3 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC6_U; - - - - -typedef union tagPortLogic7 -{ - - struct - { - UINT32 vc0posteddataqueuedepth : 11 ; - UINT32 Reserved_78 : 4 ; - UINT32 sym_timer : 1 ; - UINT32 maskfunctionmismatchfilteringfo : 1 ; - UINT32 maskpoisonedtlpfiltering : 1 ; - UINT32 maskbarmatchfiltering : 1 ; - UINT32 masktype1configurationrequestfiltering : 1 ; - UINT32 masklockedrequestfiltering : 1 ; - UINT32 masktagerrorrulesforreceivedcompletions : 1 ; - UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; - UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; - UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; - UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; - UINT32 maske_crcerror_filtering : 1 ; - UINT32 maske_crcerror_filtering_forcompletions : 1 ; - UINT32 message_control : 1 ; - UINT32 maskfilteringofreceived : 1 ; - UINT32 flt_mask1 : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC7_U; - - - - -typedef union tagPortLogic8 -{ - - struct - { - UINT32 cx_flt_mask_venmsg0_drop : 1 ; - UINT32 cx_flt_mask_venmsg1_drop : 1 ; - UINT32 cx_flt_mask_dabort_4ucpl : 1 ; - UINT32 cx_flt_mask_handle_flush : 1 ; - UINT32 flt_mask2 : 28 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC8_U; - - - - -typedef union tagPortLogic9 -{ - - struct - { - UINT32 amba_multi_outbound_decomp_np : 1 ; - UINT32 amba_obnp_ctrl : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC9_U; - - - - -typedef union tagPortLogic12 -{ - - struct - { - UINT32 transmitposteddatafccredits : 12 ; - UINT32 transmitpostedheaderfccredits : 8 ; - UINT32 tx_pfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC12_U; - - - - -typedef union tagPortLogic13 -{ - - struct - { - UINT32 transmitnon_posteddatafccredits : 12 ; - UINT32 transmitnon_postedheaderfccredits : 8 ; - UINT32 tx_npfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC13_U; - - - - -typedef union tagPortLogic14 -{ - - struct - { - UINT32 transmitcompletiondatafccredits : 12 ; - UINT32 transmitcompletionheaderfccredits : 8 ; - UINT32 tx_cplfc_status : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC14_U; - - - - -typedef union tagPortLogic15 -{ - - struct - { - UINT32 rx_tlp_fc_credit_not_retured : 1 ; - UINT32 tx_retry_buf_not_empty : 1 ; - UINT32 rx_queue_not_empty : 1 ; - UINT32 Reserved_80 : 13 ; - UINT32 fc_latency_timer_override_value : 13 ; - UINT32 Reserved_79 : 2 ; - UINT32 fc_latency_timer_override_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC15_U; - - - - -typedef union tagPortLogic16 -{ - - struct - { - UINT32 vc0posteddatacredits : 12 ; - UINT32 vc0postedheadercredits : 8 ; - UINT32 Reserved_82 : 1 ; - UINT32 vc0_postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemode : 1 ; - UINT32 vc0postedtlpqueuemo : 1 ; - UINT32 Reserved_81 : 6 ; - UINT32 tlptypeorderingforvc0 : 1 ; - UINT32 rx_pque_ctrl : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC16_U; - - - - -typedef union tagPortLogic17 -{ - - struct - { - UINT32 vc0non_posteddatacredits : 12 ; - UINT32 vc0non_postedheadercredits : 8 ; - UINT32 rx_npque_ctrl : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC17_U; - - - - -typedef union tagPortLogic18 -{ - - struct - { - UINT32 vco_comp_data_credits : 12 ; - UINT32 vc0_cpl_header_credt : 8 ; - UINT32 Reserved_84 : 12 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC18_U; - - - - -typedef union tagPortLogic19 -{ - - struct - { - UINT32 vco_posted_data_que_path : 14 ; - UINT32 Reserved_85 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 vc_pbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC19_U; - - - - -typedef union tagPortLogic20 -{ - - struct - { - UINT32 vco_np_data_que_depth : 14 ; - UINT32 Reserved_87 : 2 ; - UINT32 vco_np_header_que_depth : 10 ; - UINT32 vc_npbuf_ctrl : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC20_U; - - - - -typedef union tagPortLogic21 -{ - - struct - { - UINT32 vco_comp_data_queue_depth : 14 ; - UINT32 Reserved_89 : 2 ; - UINT32 vco_posted_head_queue_depth : 10 ; - UINT32 Reserved_88 : 6 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC21_U; - - - - -typedef union tagPortLogic22 -{ - - struct - { - UINT32 n_fts : 8 ; - UINT32 pre_determ_num_of_lane : 9 ; - UINT32 det_sp_change : 1 ; - UINT32 config_phy_tx_sw : 1 ; - UINT32 config_tx_comp_rcv_bit : 1 ; - UINT32 set_emp_level : 1 ; - UINT32 Reserved_90 : 11 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORT_LOGIC22_U; - - - - -typedef union tagPortlogic25 -{ - - struct - { - UINT32 remote_rd_req_size : 3 ; - UINT32 Reserved_93 : 5 ; - UINT32 remote_max_brd_tag : 8 ; - UINT32 Reserved_92 : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC25_U; - - - - -typedef union tagPortlogic26 -{ - - struct - { - UINT32 resize_master_resp_compser : 1 ; - UINT32 axi_ctrl1 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC26_U; - - - - -typedef union tagPortlogic54 -{ - - struct - { - UINT32 region_index : 4 ; - UINT32 Reserved_94 : 27 ; - UINT32 iatu_view : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC54_U; - - - - -typedef union tagPortlogic55 -{ - - struct - { - UINT32 iatu1_type : 5 ; - UINT32 iatu1_tc : 3 ; - UINT32 iatu1_td : 1 ; - UINT32 iatu1_attr : 2 ; - UINT32 Reserved_98 : 5 ; - UINT32 iatu1_at : 2 ; - UINT32 Reserved_97 : 2 ; - UINT32 iatu1_id : 3 ; - UINT32 Reserved_96 : 9 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC55_U; - - - - -typedef union tagPortlogic56 -{ - - struct - { - UINT32 iatu2_type : 8 ; - UINT32 iatu2_bar_num : 3 ; - UINT32 Reserved_102 : 3 ; - UINT32 iatu2_tc_match_en : 1 ; - UINT32 iatu2_td_match_en : 1 ; - UINT32 iatu2_attr_match_en : 1 ; - UINT32 Reserved_101 : 1 ; - UINT32 iatu2_at_match_en : 1 ; - UINT32 iatu2_func_num_match_en : 1 ; - UINT32 iatu2_virtual_func_num_match_en : 1 ; - UINT32 message_code_match_en : 1 ; - UINT32 Reserved_100 : 2 ; - UINT32 iatu2_response_code : 2 ; - UINT32 Reserved_99 : 1 ; - UINT32 iatu2_fuzzy_type_match_mode : 1 ; - UINT32 iatu2_cfg_shift_mode : 1 ; - UINT32 iatu2_ivert_mode : 1 ; - UINT32 iatu2_match_mode : 1 ; - UINT32 iatu2_region_en : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC56_U; - - - - -typedef union tagPortlogic57 -{ - - struct - { - UINT32 iatu_start_low : 12 ; - UINT32 iatu_start_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC57_U; - - - - -typedef union tagPortlogic59 -{ - - struct - { - UINT32 iatu_limit_low : 12 ; - UINT32 iatu_limit_high : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC59_U; - - - - -typedef union tagPortlogic60 -{ - - struct - { - UINT32 xlated_addr_high : 12 ; - UINT32 xlated_addr_low : 20 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC60_U; - - - - -typedef union tagPortlogic62 -{ - - struct - { - UINT32 dma_wr_eng_en : 1 ; - UINT32 dma_wr_ena : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC62_U; - - - - -typedef union tagPortlogic63 -{ - - struct - { - UINT32 wr_doorbell_num : 3 ; - UINT32 Reserved_104 : 28 ; - UINT32 dma_wr_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC63_U; - - - - -typedef union tagPortlogic64 -{ - - struct - { - UINT32 dma_read_eng_en : 1 ; - UINT32 Reserved_105 : 31 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC64_U; - - - - -typedef union tagPortlogic65 -{ - - struct - { - UINT32 rd_doorbell_num : 3 ; - UINT32 Reserved_107 : 28 ; - UINT32 dma_rd_dbell_stop : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC65_U; - - - - -typedef union tagPortlogic66 -{ - - struct - { - UINT32 done_int_status : 8 ; - UINT32 Reserved_109 : 8 ; - UINT32 abort_int_status : 8 ; - UINT32 Reserved_108 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC66_U; - - - - -typedef union tagPortlogic67 -{ - - struct - { - UINT32 done_int_mask : 8 ; - UINT32 Reserved_112 : 8 ; - UINT32 abort_int_mask : 8 ; - UINT32 Reserved_111 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC67_U; - - - - -typedef union tagPortlogic68 -{ - - struct - { - UINT32 done_int_clr : 8 ; - UINT32 Reserved_115 : 8 ; - UINT32 abort_int_clr : 8 ; - UINT32 Reserved_114 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC68_U; - - - - -typedef union tagPortlogic69 -{ - - struct - { - UINT32 app_rd_err_det : 8 ; - UINT32 Reserved_117 : 8 ; - UINT32 ll_element_fetch_err_det : 8 ; - UINT32 Reserved_116 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC69_U; - - - - -typedef union tagPortlogic74 -{ - - struct - { - UINT32 dma_wr_c0_imwr_data : 16 ; - UINT32 dma_wr_c1_imwr_data : 16 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC74_U; - - - - -typedef union tagPortlogic75 -{ - - struct - { - UINT32 wr_ch_ll_remote_abort_int_en : 8 ; - UINT32 Reserved_119 : 8 ; - UINT32 wr_ch_ll_local_abort_int_en : 8 ; - UINT32 Reserved_118 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC75_U; - - - - -typedef union tagPortlogic76 -{ - - struct - { - UINT32 done_int_status : 8 ; - UINT32 Reserved_122 : 8 ; - UINT32 abort_int_status : 8 ; - UINT32 Reserved_121 : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC76_U; - - - - -typedef union tagPortlogic77 -{ - - struct - { - UINT32 done_int_mask : 8 ; - UINT32 Reserved_124 : 8 ; - UINT32 abort_int_mask : 8 ; - UINT32 dma_rd_int_mask : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC77_U; - - - - -typedef union tagPortlogic78 -{ - - struct - { - UINT32 done_int_clr : 8 ; - UINT32 Reserved_126 : 8 ; - UINT32 abort_int_clr : 8 ; - UINT32 dma_rd_int_clr : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC78_U; - - - - -typedef union tagPortlogic79 -{ - - struct - { - UINT32 app_wr_err_det : 8 ; - UINT32 Reserved_127 : 8 ; - UINT32 link_list_fetch_err_det : 8 ; - UINT32 dma_rd_err_low : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC79_U; - - - - -typedef union tagPortlogic80 -{ - - struct - { - UINT32 unspt_request : 8 ; - UINT32 completer_abort : 8 ; - UINT32 cpl_time_out : 8 ; - UINT32 data_poison : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC80_U; - - - - -typedef union tagPortlogic81 -{ - - struct - { - UINT32 remote_abort_int_en : 8 ; - UINT32 Reserved_129 : 8 ; - UINT32 local_abort_int_en : 8 ; - UINT32 dma_rd_ll_err_ena : 8 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC81_U; - - - - -typedef union tagPortlogic86 -{ - - struct - { - UINT32 channel_dir : 3 ; - UINT32 Reserved_132 : 28 ; - UINT32 dma_ch_con_idx : 1 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC86_U; - - - - -typedef union tagPortlogic87 -{ - - struct - { - UINT32 cycle_bit : 1 ; - UINT32 toggle_cycle_bit : 1 ; - UINT32 load_link_pointer : 1 ; - UINT32 local_int_en : 1 ; - UINT32 remote_int_en : 1 ; - UINT32 channel_status : 2 ; - UINT32 Reserved_136 : 1 ; - UINT32 consumer_cycle_state : 1 ; - UINT32 linked_list_en : 1 ; - UINT32 Reserved_135 : 2 ; - UINT32 func_num_dma : 5 ; - UINT32 Reserved_134 : 7 ; - UINT32 no_snoop : 1 ; - UINT32 ro : 1 ; - UINT32 td : 1 ; - UINT32 tc : 3 ; - UINT32 dma_ch_ctrl : 2 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC87_U; - - - - -typedef union tagPortlogic93 -{ - - struct - { - UINT32 Reserved_138 : 2 ; - UINT32 dma_ll_ptr_low : 30 ; - } Bits; - - - UINT32 UInt32; - -} PCIE_EP_PORTLOGIC93_U; - - -#define PCIE_SUBCTRL_BASE (0x0) - - - - - -#define PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x300) -#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(port_id) \ - (PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG + (port_id << 3)) -#define PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x304) -#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(port_id) \ - (PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG + (port_id << 3)) -#define PCIE_SUBCTRL_SC_PCIE1_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x308) -#define PCIE_SUBCTRL_SC_PCIE1_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x30C) -#define PCIE_SUBCTRL_SC_PCIE2_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x310) -#define PCIE_SUBCTRL_SC_PCIE2_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x314) -#define PCIE_SUBCTRL_SC_SAS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x318) -#define PCIE_SUBCTRL_SC_SAS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x31C) -#define PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x320) -#define PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x324) -#define PCIE_SUBCTRL_SC_ITS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x328) -#define PCIE_SUBCTRL_SC_ITS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x32C) -#define PCIE_SUBCTRL_SC_SLLC_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x360) -#define PCIE_SUBCTRL_SC_SLLC_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x364) -#define PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA00) -#define PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA04) -#define PCIE_SUBCTRL_SC_PCIE1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA08) -#define PCIE_SUBCTRL_SC_PCIE1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA0C) -#define PCIE_SUBCTRL_SC_PCIE2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA10) -#define PCIE_SUBCTRL_SC_PCIE2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA14) -#define PCIE_SUBCTRL_SC_SAS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA18) -#define PCIE_SUBCTRL_SC_SAS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA1C) -#define PCIE_SUBCTRL_SC_MCTP0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA20) -#define PCIE_SUBCTRL_SC_MCTP0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA24) -#define PCIE_SUBCTRL_SC_MCTP1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA28) -#define PCIE_SUBCTRL_SC_MCTP1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA2C) -#define PCIE_SUBCTRL_SC_MCTP2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA30) -#define PCIE_SUBCTRL_SC_MCTP2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA34) -#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA58) -#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA5C) -#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA60) -#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA64) -#define PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA68) -#define PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA6C) -#define PCIE_SUBCTRL_SC_MCTP3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA70) -#define PCIE_SUBCTRL_SC_MCTP3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA74) -#define PCIE_SUBCTRL_SC_ITS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA80) -#define PCIE_SUBCTRL_SC_ITS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA84) -#define PCIE_SUBCTRL_SC_SLLC_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAA0) -#define PCIE_SUBCTRL_SC_SLLC_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAA4) -#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC0) -#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAC4) -#define PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC8) -#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (PCIE_SUBCTRL_BASE + 0x1000) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY0_REG (PCIE_SUBCTRL_BASE + 0x1004) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY1_REG (PCIE_SUBCTRL_BASE + 0x1008) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY2_REG (PCIE_SUBCTRL_BASE + 0x100C) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (PCIE_SUBCTRL_BASE + 0x1010) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (PCIE_SUBCTRL_BASE + 0x1014) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C) -#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020) -#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_BASE + 0x1024) -#define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030) -#define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100) -#define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104) -#define PCIE_SUBCTRL_SC_DISPATCH_INTSTAT_REG (PCIE_SUBCTRL_BASE + 0x1108) -#define PCIE_SUBCTRL_SC_DISPATCH_INTCLR_REG (PCIE_SUBCTRL_BASE + 0x110C) -#define PCIE_SUBCTRL_SC_DISPATCH_ERRSTAT_REG (PCIE_SUBCTRL_BASE + 0x1110) -#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (PCIE_SUBCTRL_BASE + 0x1200) -#define PCIE_SUBCTRL_SC_FTE_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2200) -#define PCIE_SUBCTRL_SC_HILINK0_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2300) -#define PCIE_SUBCTRL_SC_HILINK1_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2304) -#define PCIE_SUBCTRL_SC_HILINK2_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2308) -#define PCIE_SUBCTRL_SC_HILINK5_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2314) -#define PCIE_SUBCTRL_SC_HILINK1_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2324) -#define PCIE_SUBCTRL_SC_HILINK2_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2328) -#define PCIE_SUBCTRL_SC_HILINK5_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2334) -#define PCIE_SUBCTRL_SC_HILINK5_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2340) -#define PCIE_SUBCTRL_SC_HILINK6_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2344) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2400) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2404) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2408) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x240C) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2410) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2414) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2418) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x241C) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2420) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2424) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2500) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2504) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2508) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x250C) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2510) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2514) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2518) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x251C) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2520) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2524) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2600) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2604) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2608) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x260C) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2610) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2614) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2618) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x261C) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2620) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2624) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2700) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2704) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2708) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x270C) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2710) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2714) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2718) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x271C) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2720) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2724) -#define PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2800) -#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2880) -#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2890) -#define PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2900) -#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2980) -#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2990) -#define PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2A00) -#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A80) -#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A90) -#define PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2B00) -#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3000) -#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3004) -#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3008) -#define PCIE_SUBCTRL_SC_SLLC0_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3010) -#define PCIE_SUBCTRL_SC_SAS_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3030) -#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3040) -#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3044) -#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3048) -#define PCIE_SUBCTRL_SC_SKEW_COMMON_0_REG (PCIE_SUBCTRL_BASE + 0x3400) -#define PCIE_SUBCTRL_SC_SKEW_COMMON_1_REG (PCIE_SUBCTRL_BASE + 0x3404) -#define PCIE_SUBCTRL_SC_SKEW_COMMON_2_REG (PCIE_SUBCTRL_BASE + 0x3408) -#define PCIE_SUBCTRL_SC_SKEW_A_0_REG (PCIE_SUBCTRL_BASE + 0x3500) -#define PCIE_SUBCTRL_SC_SKEW_A_1_REG (PCIE_SUBCTRL_BASE + 0x3504) -#define PCIE_SUBCTRL_SC_SKEW_A_2_REG (PCIE_SUBCTRL_BASE + 0x3508) -#define PCIE_SUBCTRL_SC_SKEW_A_3_REG (PCIE_SUBCTRL_BASE + 0x350C) -#define PCIE_SUBCTRL_SC_SKEW_A_4_REG (PCIE_SUBCTRL_BASE + 0x3510) -#define PCIE_SUBCTRL_SC_SKEW_A_5_REG (PCIE_SUBCTRL_BASE + 0x3514) -#define PCIE_SUBCTRL_SC_SKEW_A_6_REG (PCIE_SUBCTRL_BASE + 0x3518) -#define PCIE_SUBCTRL_SC_SKEW_A_7_REG (PCIE_SUBCTRL_BASE + 0x351C) -#define PCIE_SUBCTRL_SC_SKEW_A_8_REG (PCIE_SUBCTRL_BASE + 0x3520) -#define PCIE_SUBCTRL_SC_SKEW_B_0_REG (PCIE_SUBCTRL_BASE + 0x3600) -#define PCIE_SUBCTRL_SC_SKEW_B_1_REG (PCIE_SUBCTRL_BASE + 0x3604) -#define PCIE_SUBCTRL_SC_SKEW_B_2_REG (PCIE_SUBCTRL_BASE + 0x3608) -#define PCIE_SUBCTRL_SC_SKEW_B_3_REG (PCIE_SUBCTRL_BASE + 0x360C) -#define PCIE_SUBCTRL_SC_SKEW_B_4_REG (PCIE_SUBCTRL_BASE + 0x3610) -#define PCIE_SUBCTRL_SC_SKEW_B_5_REG (PCIE_SUBCTRL_BASE + 0x3614) -#define PCIE_SUBCTRL_SC_SKEW_B_6_REG (PCIE_SUBCTRL_BASE + 0x3618) -#define PCIE_SUBCTRL_SC_SKEW_B_7_REG (PCIE_SUBCTRL_BASE + 0x361C) -#define PCIE_SUBCTRL_SC_SKEW_B_8_REG (PCIE_SUBCTRL_BASE + 0x3620) -#define PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5300) -#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(port_id) \ - (PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG + (port_id << 2)) -#define PCIE_SUBCTRL_SC_PCIE1_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5304) -#define PCIE_SUBCTRL_SC_PCIE2_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5308) -#define PCIE_SUBCTRL_SC_SAS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x530C) -#define PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5310) -#define PCIE_SUBCTRL_SC_ITS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5314) -#define PCIE_SUBCTRL_SC_SLLC_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5330) -#define PCIE_SUBCTRL_SC_PCIE0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A00) -#define PCIE_SUBCTRL_SC_PCIE1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A04) -#define PCIE_SUBCTRL_SC_PCIE2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A08) -#define PCIE_SUBCTRL_SC_SAS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A0C) -#define PCIE_SUBCTRL_SC_MCTP0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A10) -#define PCIE_SUBCTRL_SC_MCTP1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A14) -#define PCIE_SUBCTRL_SC_MCTP2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A18) -#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A2C) -#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A30) -#define PCIE_SUBCTRL_SC_PCIE3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A34) -#define PCIE_SUBCTRL_SC_MCTP3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A38) -#define PCIE_SUBCTRL_SC_ITS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A40) -#define PCIE_SUBCTRL_SC_SLLC_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A50) -#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A60) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6400) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6404) -#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6408) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6500) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6504) -#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6508) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6600) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6604) -#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6608) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6700) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6704) -#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6708) -#define PCIE_SUBCTRL_SC_PCIE0_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6800) -#define PCIE_SUBCTRL_SC_PCIE0_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6804) -#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6808) -#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x680C) -#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6810) -#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814) -#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818) -#define PCIE_LTSSM_STATE_MASK (0x3f) -#define PCIE_LTSSM_CFG_LANENUM_ACPT 0x0a -#define PCIE_LTSSM_CFG_COMPLETE 0x0b -#define PCIE_LTSSM_LINKUP_STATE (0x11) -#define LTSSM_ENABLE BIT11 -#define MAX_TRY_LINK_NUM 5 -#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880) -#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884) -#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890) -#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6894) -#define PCIE_SUBCTRL_SC_PCIE0_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x68A0) -#define PCIE_SUBCTRL_SC_PCIE0_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x68C0) -#define PCIE_SUBCTRL_SC_PCIE1_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6900) -#define PCIE_SUBCTRL_SC_PCIE1_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6904) -#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6908) -#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x690C) -#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6910) -#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6914) -#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6918) -#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6980) -#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6984) -#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6990) -#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6994) -#define PCIE_SUBCTRL_SC_PCIE1_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x69A0) -#define PCIE_SUBCTRL_SC_PCIE1_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x69C0) -#define PCIE_SUBCTRL_SC_PCIE2_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A00) -#define PCIE_SUBCTRL_SC_PCIE2_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A04) -#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6A08) -#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6A0C) -#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6A10) -#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6A14) -#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6A18) -#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A80) -#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A84) -#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A90) -#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A94) -#define PCIE_SUBCTRL_SC_PCIE2_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x6AA0) -#define PCIE_SUBCTRL_SC_PCIE2_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6AC0) -#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6B08) -#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6B0C) -#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6B10) -#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6B14) -#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6B18) -#define PCIE_SUBCTRL_SC_PCIE3_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6BC0) -#define PCIE_SUBCTRL_SC_SKEW_ST_0_REG (PCIE_SUBCTRL_BASE + 0x7400) -#define PCIE_SUBCTRL_SC_SKEW_ST_A_0_REG (PCIE_SUBCTRL_BASE + 0x7500) -#define PCIE_SUBCTRL_SC_SKEW_ST_A_1_REG (PCIE_SUBCTRL_BASE + 0x7504) -#define PCIE_SUBCTRL_SC_SKEW_ST_A_2_REG (PCIE_SUBCTRL_BASE + 0x7508) -#define PCIE_SUBCTRL_SC_SKEW_ST_A_3_REG (PCIE_SUBCTRL_BASE + 0x750C) -#define PCIE_SUBCTRL_SC_SKEW_ST_B_0_REG (PCIE_SUBCTRL_BASE + 0x7600) -#define PCIE_SUBCTRL_SC_SKEW_ST_B_1_REG (PCIE_SUBCTRL_BASE + 0x7604) -#define PCIE_SUBCTRL_SC_SKEW_ST_B_2_REG (PCIE_SUBCTRL_BASE + 0x7608) -#define PCIE_SUBCTRL_SC_SKEW_ST_B_3_REG (PCIE_SUBCTRL_BASE + 0x760C) -#define PCIE_SUBCTRL_SC_ECO_RSV0_REG (PCIE_SUBCTRL_BASE + 0x8000) -#define PCIE_SUBCTRL_SC_ECO_RSV1_REG (PCIE_SUBCTRL_BASE + 0x8004) -#define PCIE_SUBCTRL_SC_ECO_RSV2_REG (PCIE_SUBCTRL_BASE + 0x8008) - - -typedef union -{ - - struct - { - UINT32 clk_pcie0_enb : 1 ; - UINT32 clk_pcie0_pipe_enb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_pcie0_dsb : 1 ; - UINT32 clk_pcie0_pipe_dsb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_clk_dis; - - -typedef union -{ - - struct - { - UINT32 clk_pcie1_enb : 1 ; - UINT32 clk_pcie1_pipe_enb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_pcie1_dsb : 1 ; - UINT32 clk_pcie1_pipe_dsb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_clk_dis; - - -typedef union -{ - - struct - { - UINT32 clk_pcie2_enb : 1 ; - UINT32 clk_pcie2_pipe_enb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_pcie2_dsb : 1 ; - UINT32 clk_pcie2_pipe_dsb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_clk_dis; - - -typedef union -{ - - struct - { - UINT32 clk_sas_enb : 1 ; - UINT32 clk_sas_mem_enb : 1 ; - UINT32 clk_sas_ahb_enb : 1 ; - UINT32 clk_sas_oob_enb : 1 ; - UINT32 clk_sas_ch0_rx_enb : 1 ; - UINT32 clk_sas_ch1_rx_enb : 1 ; - UINT32 clk_sas_ch2_rx_enb : 1 ; - UINT32 clk_sas_ch3_rx_enb : 1 ; - UINT32 clk_sas_ch4_rx_enb : 1 ; - UINT32 clk_sas_ch5_rx_enb : 1 ; - UINT32 clk_sas_ch6_rx_enb : 1 ; - UINT32 clk_sas_ch7_rx_enb : 1 ; - UINT32 clk_sas_ch0_tx_enb : 1 ; - UINT32 clk_sas_ch1_tx_enb : 1 ; - UINT32 clk_sas_ch2_tx_enb : 1 ; - UINT32 clk_sas_ch3_tx_enb : 1 ; - UINT32 clk_sas_ch4_tx_enb : 1 ; - UINT32 clk_sas_ch5_tx_enb : 1 ; - UINT32 clk_sas_ch6_tx_enb : 1 ; - UINT32 clk_sas_ch7_tx_enb : 1 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_sas_dsb : 1 ; - UINT32 clk_sas_mem_dsb : 1 ; - UINT32 clk_sas_ahb_dsb : 1 ; - UINT32 clk_sas_oob_dsb : 1 ; - UINT32 clk_sas_ch0_rx_dsb : 1 ; - UINT32 clk_sas_ch1_rx_dsb : 1 ; - UINT32 clk_sas_ch2_rx_dsb : 1 ; - UINT32 clk_sas_ch3_rx_dsb : 1 ; - UINT32 clk_sas_ch4_rx_dsb : 1 ; - UINT32 clk_sas_ch5_rx_dsb : 1 ; - UINT32 clk_sas_ch6_rx_dsb : 1 ; - UINT32 clk_sas_ch7_rx_dsb : 1 ; - UINT32 clk_sas_ch0_tx_dsb : 1 ; - UINT32 clk_sas_ch1_tx_dsb : 1 ; - UINT32 clk_sas_ch2_tx_dsb : 1 ; - UINT32 clk_sas_ch3_tx_dsb : 1 ; - UINT32 clk_sas_ch4_tx_dsb : 1 ; - UINT32 clk_sas_ch5_tx_dsb : 1 ; - UINT32 clk_sas_ch6_tx_dsb : 1 ; - UINT32 clk_sas_ch7_tx_dsb : 1 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_clk_dis; - - -typedef union -{ - - struct - { - UINT32 clk_pcie3_enb : 1 ; - UINT32 clk_pcie3_pipe_enb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_pcie3_dsb : 1 ; - UINT32 clk_pcie3_pipe_dsb : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_clk_dis; - - -typedef union -{ - - struct - { - UINT32 clk_its_enb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_its_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_its_dsb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_its_clk_dis; - - -typedef union -{ - - struct - { - UINT32 clk_sllc_enb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_clk_en; - - -typedef union -{ - - struct - { - UINT32 clk_sllc_dsb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_clk_dis; - - -typedef union -{ - - struct - { - UINT32 pcie0_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_reset_req; - - -typedef union -{ - - struct - { - UINT32 pcie0_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 pcie1_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_reset_req; - - -typedef union -{ - - struct - { - UINT32 pcie1_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 pcie2_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_reset_req; - - -typedef union -{ - - struct - { - UINT32 pcie2_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 sas_srst_req : 1 ; - UINT32 sas_oob_srst_req : 1 ; - UINT32 sas_ahb_srst_req : 1 ; - UINT32 sas_ch0_rx_srst_req : 1 ; - UINT32 sas_ch1_rx_srst_req : 1 ; - UINT32 sas_ch2_rx_srst_req : 1 ; - UINT32 sas_ch3_rx_srst_req : 1 ; - UINT32 sas_ch4_rx_srst_req : 1 ; - UINT32 sas_ch5_rx_srst_req : 1 ; - UINT32 sas_ch6_rx_srst_req : 1 ; - UINT32 sas_ch7_rx_srst_req : 1 ; - UINT32 sas_ch0_tx_srst_req : 1 ; - UINT32 sas_ch1_tx_srst_req : 1 ; - UINT32 sas_ch2_tx_srst_req : 1 ; - UINT32 sas_ch3_tx_srst_req : 1 ; - UINT32 sas_ch4_tx_srst_req : 1 ; - UINT32 sas_ch5_tx_srst_req : 1 ; - UINT32 sas_ch6_tx_srst_req : 1 ; - UINT32 sas_ch7_tx_srst_req : 1 ; - UINT32 reserved_0 : 13 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_reset_req; - - -typedef union -{ - - struct - { - UINT32 sas_srst_dreq : 1 ; - UINT32 sas_oob_srst_dreq : 1 ; - UINT32 sas_ahb_srst_dreq : 1 ; - UINT32 sas_ch0_rx_srst_dreq : 1 ; - UINT32 sas_ch1_rx_srst_dreq : 1 ; - UINT32 sas_ch2_rx_srst_dreq : 1 ; - UINT32 sas_ch3_rx_srst_dreq : 1 ; - UINT32 sas_ch4_rx_srst_dreq : 1 ; - UINT32 sas_ch5_rx_srst_dreq : 1 ; - UINT32 sas_ch6_rx_srst_dreq : 1 ; - UINT32 sas_ch7_rx_srst_dreq : 1 ; - UINT32 sas_ch0_tx_srst_dreq : 1 ; - UINT32 sas_ch1_tx_srst_dreq : 1 ; - UINT32 sas_ch2_tx_srst_dreq : 1 ; - UINT32 sas_ch3_tx_srst_dreq : 1 ; - UINT32 sas_ch4_tx_srst_dreq : 1 ; - UINT32 sas_ch5_tx_srst_dreq : 1 ; - UINT32 sas_ch6_tx_srst_dreq : 1 ; - UINT32 sas_ch7_tx_srst_dreq : 1 ; - UINT32 reserved_0 : 13 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 mctp0_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp0_reset_req; - - -typedef union -{ - - struct - { - UINT32 mctp0_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp0_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 mctp1_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp1_reset_req; - - -typedef union -{ - - struct - { - UINT32 mctp1_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp1_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 mctp2_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp2_reset_req; - - -typedef union -{ - - struct - { - UINT32 mctp2_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp2_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 sllc_tsvrx0_srst_req : 1 ; - UINT32 sllc_tsvrx1_srst_req : 1 ; - UINT32 sllc_tsvrx2_srst_req : 1 ; - UINT32 sllc_tsvrx3_srst_req : 1 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_tsvrx_reset_req; - - -typedef union -{ - - struct - { - UINT32 sllc_tsvrx0_srst_dreq : 1 ; - UINT32 sllc_tsvrx1_srst_dreq : 1 ; - UINT32 sllc_tsvrx2_srst_dreq : 1 ; - UINT32 sllc_tsvrx3_srst_dreq : 1 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_tsvrx_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 pcie0_hilink_pcs_lane0_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane1_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane2_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane3_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane4_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane5_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane6_srst_req : 1 ; - UINT32 pcie0_hilink_pcs_lane7_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane0_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane1_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane2_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane3_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane4_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane5_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane6_srst_req : 1 ; - UINT32 pcie1_hilink_pcs_lane7_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane0_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane1_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane2_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane3_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane4_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane5_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane6_srst_req : 1 ; - UINT32 pcie2_hilink_pcs_lane7_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane0_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane1_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane2_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane3_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane4_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane5_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane6_srst_req : 1 ; - UINT32 pcie3_hilink_pcs_lane7_srst_req : 1 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie_hilink_pcs_reset_req; - - -typedef union -{ - - struct - { - UINT32 pcie0_hilink_pcs_lane0_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane1_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane2_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane3_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane4_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane5_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane6_srst_dreq : 1 ; - UINT32 pcie0_hilink_pcs_lane7_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane0_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane1_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane2_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane3_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane4_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane5_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane6_srst_dreq : 1 ; - UINT32 pcie1_hilink_pcs_lane7_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane0_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane1_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane2_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane3_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane4_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane5_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane6_srst_dreq : 1 ; - UINT32 pcie2_hilink_pcs_lane7_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane0_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane1_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane2_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane3_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane4_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane5_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane6_srst_dreq : 1 ; - UINT32 pcie3_hilink_pcs_lane7_srst_dreq : 1 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie_hilink_pcs_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 pcie3_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_reset_req; - - -typedef union -{ - - struct - { - UINT32 pcie3_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 mctp3_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp3_reset_req; - - -typedef union -{ - - struct - { - UINT32 mctp3_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp3_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 its_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_its_reset_req; - - -typedef union -{ - - struct - { - UINT32 its_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_its_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 sllc_srst_req : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_reset_req; - - -typedef union -{ - - struct - { - UINT32 sllc_srst_dreq : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 pcie0_pcs_local_srst_req : 1 ; - UINT32 pcie1_pcs_local_srst_req : 1 ; - UINT32 pcie2_pcs_local_srst_req : 1 ; - UINT32 pcie3_pcs_local_srst_req : 1 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcs_local_reset_req; - - -typedef union -{ - - struct - { - UINT32 pcie0_pcs_local_srst_dreq : 1 ; - UINT32 pcie1_pcs_local_srst_dreq : 1 ; - UINT32 pcie2_pcs_local_srst_dreq : 1 ; - UINT32 pcie3_pcs_local_srst_dreq : 1 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcs_local_reset_dreq; - - -typedef union -{ - - struct - { - UINT32 dispatch_daw_en : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_disp_daw_en; - - -typedef union -{ - - struct - { - UINT32 daw_array0_did : 3 ; - UINT32 daw_array0_size : 5 ; - UINT32 daw_array0_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array0_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array0; - - -typedef union -{ - - struct - { - UINT32 daw_array1_did : 3 ; - UINT32 daw_array1_size : 5 ; - UINT32 daw_array1_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array1_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array1; - - -typedef union -{ - - struct - { - UINT32 daw_array2_did : 3 ; - UINT32 daw_array2_size : 5 ; - UINT32 daw_array2_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array2_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array2; - - -typedef union -{ - - struct - { - UINT32 daw_array3_did : 3 ; - UINT32 daw_array3_size : 5 ; - UINT32 daw_array3_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array3_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array3; - - -typedef union -{ - - struct - { - UINT32 daw_array4_did : 3 ; - UINT32 daw_array4_size : 5 ; - UINT32 daw_array4_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array4_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array4; - - -typedef union -{ - - struct - { - UINT32 daw_array5_did : 3 ; - UINT32 daw_array5_size : 5 ; - UINT32 daw_array5_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array5_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array5; - - -typedef union -{ - - struct - { - UINT32 daw_array6_did : 3 ; - UINT32 daw_array6_size : 5 ; - UINT32 daw_array6_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array6_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array6; - - -typedef union -{ - - struct - { - UINT32 daw_array7_did : 3 ; - UINT32 daw_array7_size : 5 ; - UINT32 daw_array7_sync : 1 ; - UINT32 reserved_0 : 4 ; - UINT32 daw_array7_addr : 19 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_daw_array7; - - -typedef union -{ - - struct - { - UINT32 retry_num_limit : 16 ; - UINT32 retry_en : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_retry_control; - - -typedef union -{ - - struct - { - UINT32 intmask : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_intmask; - - -typedef union -{ - - struct - { - UINT32 rawint : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_rawint; - - -typedef union -{ - - struct - { - UINT32 intsts : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_intstat; - - -typedef union -{ - - struct - { - UINT32 intclr : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_intclr; - - -typedef union -{ - - struct - { - UINT32 err_opcode : 5 ; - UINT32 err_addr : 17 ; - UINT32 reserved_0 : 10 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_dispatch_errstat; - - -typedef union -{ - - struct - { - UINT32 sys_remap_vld : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_remap_ctrl; - - -typedef union -{ - - struct - { - UINT32 mux_sel_fte : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_fte_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink0_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink1_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink2_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink2_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink5_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink1_ahb_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_ahb_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink2_ahb_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink2_ahb_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink5_ahb_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_ahb_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink5_lrstb_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_lrstb_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink6_lrstb_mux_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_lrstb_mux_ctrl; - - -typedef union -{ - - struct - { - UINT32 hilink0_ss_refclk0_x2s : 2 ; - UINT32 hilink0_ss_refclk0_x2n : 2 ; - UINT32 hilink0_ss_refclk0_x2e : 2 ; - UINT32 hilink0_ss_refclk0_x2w : 2 ; - UINT32 hilink0_ss_refclk1_x2s : 2 ; - UINT32 hilink0_ss_refclk1_x2n : 2 ; - UINT32 hilink0_ss_refclk1_x2e : 2 ; - UINT32 hilink0_ss_refclk1_x2w : 2 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_ss_refclk; - - -typedef union -{ - - struct - { - UINT32 hilink0_cs_refclk0_dirsel0 : 2 ; - UINT32 hilink0_cs_refclk0_dirsel1 : 2 ; - UINT32 hilink0_cs_refclk0_dirsel2 : 2 ; - UINT32 hilink0_cs_refclk0_dirsel3 : 2 ; - UINT32 hilink0_cs_refclk0_dirsel4 : 2 ; - UINT32 hilink0_cs_refclk1_dirsel0 : 2 ; - UINT32 hilink0_cs_refclk1_dirsel1 : 2 ; - UINT32 hilink0_cs_refclk1_dirsel2 : 2 ; - UINT32 hilink0_cs_refclk1_dirsel3 : 2 ; - UINT32 hilink0_cs_refclk1_dirsel4 : 2 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_cs_refclk_dirsel; - - -typedef union -{ - - struct - { - UINT32 hilink0_lifeclk2dig_sel : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_lifeclk2dig_sel; - - -typedef union -{ - - struct - { - UINT32 hilink0_core_clk_selext : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_core_clk_selext; - - -typedef union -{ - - struct - { - UINT32 hilink0_core_clk_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_core_clk_sel; - - -typedef union -{ - - struct - { - UINT32 hilink0_ctrl_bus_mode : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_ctrl_bus_mode; - - -typedef union -{ - - struct - { - UINT32 hilink0_macropwrdb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_macropwrdb; - - -typedef union -{ - - struct - { - UINT32 hilink0_grstb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_grstb; - - -typedef union -{ - - struct - { - UINT32 hilink0_bit_slip : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_bit_slip; - - -typedef union -{ - - struct - { - UINT32 hilink0_lrstb : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_lrstb; - - -typedef union -{ - - struct - { - UINT32 hilink1_ss_refclk0_x2s : 2 ; - UINT32 hilink1_ss_refclk0_x2n : 2 ; - UINT32 hilink1_ss_refclk0_x2e : 2 ; - UINT32 hilink1_ss_refclk0_x2w : 2 ; - UINT32 hilink1_ss_refclk1_x2s : 2 ; - UINT32 hilink1_ss_refclk1_x2n : 2 ; - UINT32 hilink1_ss_refclk1_x2e : 2 ; - UINT32 hilink1_ss_refclk1_x2w : 2 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_ss_refclk; - - -typedef union -{ - - struct - { - UINT32 hilink1_cs_refclk0_dirsel0 : 2 ; - UINT32 hilink1_cs_refclk0_dirsel1 : 2 ; - UINT32 hilink1_cs_refclk0_dirsel2 : 2 ; - UINT32 hilink1_cs_refclk0_dirsel3 : 2 ; - UINT32 hilink1_cs_refclk0_dirsel4 : 2 ; - UINT32 hilink1_cs_refclk1_dirsel0 : 2 ; - UINT32 hilink1_cs_refclk1_dirsel1 : 2 ; - UINT32 hilink1_cs_refclk1_dirsel2 : 2 ; - UINT32 hilink1_cs_refclk1_dirsel3 : 2 ; - UINT32 hilink1_cs_refclk1_dirsel4 : 2 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_cs_refclk_dirsel; - - -typedef union -{ - - struct - { - UINT32 hilink1_lifeclk2dig_sel : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_lifeclk2dig_sel; - - -typedef union -{ - - struct - { - UINT32 hilink1_core_clk_selext : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_core_clk_selext; - - -typedef union -{ - - struct - { - UINT32 hilink1_core_clk_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_core_clk_sel; - - -typedef union -{ - - struct - { - UINT32 hilink1_ctrl_bus_mode : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_ctrl_bus_mode; - - -typedef union -{ - - struct - { - UINT32 hilink1_macropwrdb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_macropwrdb; - - -typedef union -{ - - struct - { - UINT32 hilink1_grstb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_grstb; - - -typedef union -{ - - struct - { - UINT32 hilink1_bit_slip : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_bit_slip; - - -typedef union -{ - - struct - { - UINT32 hilink1_lrstb : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_lrstb; - - -typedef union -{ - - struct - { - UINT32 hilink5_ss_refclk0_x2s : 2 ; - UINT32 hilink5_ss_refclk0_x2n : 2 ; - UINT32 hilink5_ss_refclk0_x2e : 2 ; - UINT32 hilink5_ss_refclk0_x2w : 2 ; - UINT32 hilink5_ss_refclk1_x2s : 2 ; - UINT32 hilink5_ss_refclk1_x2n : 2 ; - UINT32 hilink5_ss_refclk1_x2e : 2 ; - UINT32 hilink5_ss_refclk1_x2w : 2 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_ss_refclk; - - -typedef union -{ - - struct - { - UINT32 hilink5_cs_refclk0_dirsel0 : 2 ; - UINT32 hilink5_cs_refclk0_dirsel1 : 2 ; - UINT32 hilink5_cs_refclk0_dirsel2 : 2 ; - UINT32 hilink5_cs_refclk0_dirsel3 : 2 ; - UINT32 hilink5_cs_refclk0_dirsel4 : 2 ; - UINT32 hilink5_cs_refclk1_dirsel0 : 2 ; - UINT32 hilink5_cs_refclk1_dirsel1 : 2 ; - UINT32 hilink5_cs_refclk1_dirsel2 : 2 ; - UINT32 hilink5_cs_refclk1_dirsel3 : 2 ; - UINT32 hilink5_cs_refclk1_dirsel4 : 2 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_cs_refclk_dirsel; - - -typedef union -{ - - struct - { - UINT32 hilink5_lifeclk2dig_sel : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_lifeclk2dig_sel; - - -typedef union -{ - - struct - { - UINT32 hilink5_core_clk_selext : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_core_clk_selext; - - -typedef union -{ - - struct - { - UINT32 hilink5_core_clk_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_core_clk_sel; - - -typedef union -{ - - struct - { - UINT32 hilink5_ctrl_bus_mode : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_ctrl_bus_mode; - - -typedef union -{ - - struct - { - UINT32 hilink5_macropwrdb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_macropwrdb; - - -typedef union -{ - - struct - { - UINT32 hilink5_grstb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_grstb; - - -typedef union -{ - - struct - { - UINT32 hilink5_bit_slip : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_bit_slip; - - -typedef union -{ - - struct - { - UINT32 hilink5_lrstb : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_lrstb; - - -typedef union -{ - - struct - { - UINT32 hilink6_ss_refclk0_x2s : 2 ; - UINT32 hilink6_ss_refclk0_x2n : 2 ; - UINT32 hilink6_ss_refclk0_x2e : 2 ; - UINT32 hilink6_ss_refclk0_x2w : 2 ; - UINT32 hilink6_ss_refclk1_x2s : 2 ; - UINT32 hilink6_ss_refclk1_x2n : 2 ; - UINT32 hilink6_ss_refclk1_x2e : 2 ; - UINT32 hilink6_ss_refclk1_x2w : 2 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_ss_refclk; - - -typedef union -{ - - struct - { - UINT32 hilink6_cs_refclk0_dirsel0 : 2 ; - UINT32 hilink6_cs_refclk0_dirsel1 : 2 ; - UINT32 hilink6_cs_refclk0_dirsel2 : 2 ; - UINT32 hilink6_cs_refclk0_dirsel3 : 2 ; - UINT32 hilink6_cs_refclk0_dirsel4 : 2 ; - UINT32 hilink6_cs_refclk1_dirsel0 : 2 ; - UINT32 hilink6_cs_refclk1_dirsel1 : 2 ; - UINT32 hilink6_cs_refclk1_dirsel2 : 2 ; - UINT32 hilink6_cs_refclk1_dirsel3 : 2 ; - UINT32 hilink6_cs_refclk1_dirsel4 : 2 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_cs_refclk_dirsel; - - -typedef union -{ - - struct - { - UINT32 hilink6_lifeclk2dig_sel : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_lifeclk2dig_sel; - - -typedef union -{ - - struct - { - UINT32 hilink6_core_clk_selext : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_core_clk_selext; - - -typedef union -{ - - struct - { - UINT32 hilink6_core_clk_sel : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_core_clk_sel; - - -typedef union -{ - - struct - { - UINT32 hilink6_ctrl_bus_mode : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_ctrl_bus_mode; - - -typedef union -{ - - struct - { - UINT32 hilink6_macropwrdb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_macropwrdb; - - -typedef union -{ - - struct - { - UINT32 hilink6_grstb : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_grstb; - - -typedef union -{ - - struct - { - UINT32 hilink6_bit_slip : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_bit_slip; - - -typedef union -{ - - struct - { - UINT32 hilink6_lrstb : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_lrstb; - - -typedef union -{ - - struct - { - UINT32 pcie0_phy_clk_req_n : 1 ; - UINT32 pcie0_apb_cfg_sel : 2 ; - UINT32 reserved_0 : 29 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_clkreq; - - -typedef union -{ - - struct - { - UINT32 pcie0_cfg_max_wr_trans : 6 ; - UINT32 reserved_0 : 2 ; - UINT32 pcie0_wr_rate_limit : 4 ; - UINT32 pcie0_ctrl_lat_stat_wr_en : 1 ; - UINT32 reserved_1 : 3 ; - UINT32 pcie0_en_device_wr_ooo : 1 ; - UINT32 reserved_2 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_axi_mstr_ooo_wr_cfg; - - -typedef union -{ - - struct - { - UINT32 pcie0_cfg_max_rd_trans : 6 ; - UINT32 reserved_0 : 2 ; - UINT32 pcie0_rd_rate_limit : 4 ; - UINT32 pcie0_ctrl_lat_stat_rd_en : 1 ; - UINT32 reserved_1 : 3 ; - UINT32 pcie0_en_device_rd_ooo : 1 ; - UINT32 reserved_2 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_axi_mstr_ooo_rd_cfg; - - -typedef union -{ - - struct - { - UINT32 pcie1hilink_phy_clk_req_n : 1 ; - UINT32 pcie1vsemi_phy_clk_req_n : 1 ; - UINT32 pcie1_apb_cfg_sel : 2 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_clkreq; - - -typedef union -{ - - struct - { - UINT32 pcie1_cfg_max_wr_trans : 6 ; - UINT32 reserved_0 : 2 ; - UINT32 pcie1_wr_rate_limit : 4 ; - UINT32 pcie1_ctrl_lat_stat_wr_en : 1 ; - UINT32 reserved_1 : 3 ; - UINT32 pcie1_en_device_wr_ooo : 1 ; - UINT32 reserved_2 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_axi_mstr_ooo_wr_cfg; - - -typedef union -{ - - struct - { - UINT32 pcie1_cfg_max_rd_trans : 6 ; - UINT32 reserved_0 : 2 ; - UINT32 pcie1_rd_rate_limit : 4 ; - UINT32 pcie1_ctrl_lat_stat_rd_en : 1 ; - UINT32 reserved_1 : 3 ; - UINT32 pcie1_en_device_rd_ooo : 1 ; - UINT32 reserved_2 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_axi_mstr_ooo_rd_cfg; - - -typedef union -{ - - struct - { - UINT32 pcie2hilink_phy_clk_req_n : 1 ; - UINT32 pcie2vsemi_phy_clk_req_n : 1 ; - UINT32 pcie2_apb_cfg_sel : 2 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_clkreq; - - -typedef union -{ - - struct - { - UINT32 pcie2_cfg_max_wr_trans : 6 ; - UINT32 reserved_0 : 2 ; - UINT32 pcie2_wr_rate_limit : 4 ; - UINT32 pcie2_ctrl_lat_stat_wr_en : 1 ; - UINT32 reserved_1 : 3 ; - UINT32 pcie2_en_device_wr_ooo : 1 ; - UINT32 reserved_2 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_axi_mstr_ooo_wr_cfg; - - -typedef union -{ - - struct - { - UINT32 pcie2_cfg_max_rd_trans : 6 ; - UINT32 reserved_0 : 2 ; - UINT32 pcie2_rd_rate_limit : 4 ; - UINT32 pcie2_ctrl_lat_stat_rd_en : 1 ; - UINT32 reserved_1 : 3 ; - UINT32 pcie2_en_device_rd_ooo : 1 ; - UINT32 reserved_2 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_axi_mstr_ooo_rd_cfg; - - -typedef union -{ - - struct - { - UINT32 pcie3_phy_clk_req_n : 1 ; - UINT32 pcie3_apb_cfg_sel : 2 ; - UINT32 reserved_0 : 29 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_clkreq; - - -typedef union -{ - - struct - { - UINT32 ctrl_rfs_smmu : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_smmu_mem_ctrl0; - - -typedef union -{ - - struct - { - UINT32 tsel_hc_smmu : 3 ; - UINT32 reserved_0 : 29 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_smmu_mem_ctrl1; - - -typedef union -{ - - struct - { - UINT32 test_hc_smmu : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_smmu_mem_ctrl2; - - -typedef union -{ - - struct - { - UINT32 ctrl_rft_sllc0 : 10 ; - UINT32 reserved_0 : 22 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc0_mem_ctrl; - - -typedef union -{ - - struct - { - UINT32 ctrl_rfs_sas : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_mem_ctrl; - - -typedef union -{ - - struct - { - UINT32 ctrl_rft_pcie : 10 ; - UINT32 reserved_0 : 22 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie_mem_ctrl0; - - -typedef union -{ - - struct - { - UINT32 ctrl_rashsd_pcie : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie_mem_ctrl1; - - -typedef union -{ - - struct - { - UINT32 ctrl_rfs_pcie : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie_mem_ctrl2; - - -typedef union -{ - - struct - { - UINT32 skew_en : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_common_0; - - -typedef union -{ - - struct - { - UINT32 skew_addr_offset : 5 ; - UINT32 reserved_0 : 27 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_common_1; - - -typedef union -{ - - struct - { - UINT32 skew_config_in : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_common_2; - - -typedef union -{ - - struct - { - UINT32 skew_bypass_a : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_0; - - -typedef union -{ - - struct - { - UINT32 skew_config_in_a : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_1; - - -typedef union -{ - - struct - { - UINT32 skew_out_delay_sel_a : 2 ; - UINT32 skew_in_delay_sel_a : 2 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_2; - - -typedef union -{ - - struct - { - UINT32 skew_sel_a_1 : 1 ; - UINT32 skew_sel_a_0 : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_3; - - -typedef union -{ - - struct - { - UINT32 skew_update_en_a : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_4; - - -typedef union -{ - - struct - { - UINT32 skew_varible_set_a : 16 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_5; - - -typedef union -{ - - struct - { - UINT32 skew_dcell_set_a_h : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_7; - - -typedef union -{ - - struct - { - UINT32 skew_sel_osc_a : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_a_8; - - -typedef union -{ - - struct - { - UINT32 skew_bypass_b : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_0; - - -typedef union -{ - - struct - { - UINT32 skew_config_in_b : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_1; - - -typedef union -{ - - struct - { - UINT32 skew_out_delay_sel_b : 2 ; - UINT32 skew_in_delay_sel_b : 2 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_2; - - -typedef union -{ - - struct - { - UINT32 skew_sel_b_1 : 1 ; - UINT32 skew_sel_b_0 : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_3; - - -typedef union -{ - - struct - { - UINT32 skew_update_en_b : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_4; - - -typedef union -{ - - struct - { - UINT32 skew_varible_set_b : 16 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_5; - - -typedef union -{ - - struct - { - UINT32 skew_dcell_set_b_h : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_7; - - -typedef union -{ - - struct - { - UINT32 skew_sel_osc_b : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_b_8; - - -typedef union -{ - - struct - { - UINT32 clk_pcie0_st : 1 ; - UINT32 clk_pcie0_pipe_st : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_clk_st; - - -typedef union -{ - - struct - { - UINT32 clk_pcie1_st : 1 ; - UINT32 clk_pcie1_pipe_st : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_clk_st; - - -typedef union -{ - - struct - { - UINT32 clk_pcie2_st : 1 ; - UINT32 clk_pcie2_pipe_st : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_clk_st; - - -typedef union -{ - - struct - { - UINT32 clk_sas_st : 1 ; - UINT32 clk_sas_mem_st : 1 ; - UINT32 clk_sas_ahb_st : 1 ; - UINT32 clk_sas_oob_st : 1 ; - UINT32 clk_sas_ch0_rx_st : 1 ; - UINT32 clk_sas_ch1_rx_st : 1 ; - UINT32 clk_sas_ch2_rx_st : 1 ; - UINT32 clk_sas_ch3_rx_st : 1 ; - UINT32 clk_sas_ch4_rx_st : 1 ; - UINT32 clk_sas_ch5_rx_st : 1 ; - UINT32 clk_sas_ch6_rx_st : 1 ; - UINT32 clk_sas_ch7_rx_st : 1 ; - UINT32 clk_sas_ch0_tx_st : 1 ; - UINT32 clk_sas_ch1_tx_st : 1 ; - UINT32 clk_sas_ch2_tx_st : 1 ; - UINT32 clk_sas_ch3_tx_st : 1 ; - UINT32 clk_sas_ch4_tx_st : 1 ; - UINT32 clk_sas_ch5_tx_st : 1 ; - UINT32 clk_sas_ch6_tx_st : 1 ; - UINT32 clk_sas_ch7_tx_st : 1 ; - UINT32 reserved_0 : 12 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_clk_st; - - -typedef union -{ - - struct - { - UINT32 clk_pcie3_st : 1 ; - UINT32 clk_pcie3_pipe_st : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_clk_st; - - -typedef union -{ - - struct - { - UINT32 clk_its_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_its_clk_st; - - -typedef union -{ - - struct - { - UINT32 clk_sllc_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_clk_st; - - -typedef union -{ - - struct - { - UINT32 pcie0_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_reset_st; - - -typedef union -{ - - struct - { - UINT32 pcie1_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_reset_st; - - -typedef union -{ - - struct - { - UINT32 pcie2_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_reset_st; - - -typedef union -{ - - struct - { - UINT32 sas_srst_st : 1 ; - UINT32 sas_oob_srst_st : 1 ; - UINT32 sas_ahb_srst_st : 1 ; - UINT32 sas_ch0_rx_srst_st : 1 ; - UINT32 sas_ch1_rx_srst_st : 1 ; - UINT32 sas_ch2_rx_srst_st : 1 ; - UINT32 sas_ch3_rx_srst_st : 1 ; - UINT32 sas_ch4_rx_srst_st : 1 ; - UINT32 sas_ch5_rx_srst_st : 1 ; - UINT32 sas_ch6_rx_srst_st : 1 ; - UINT32 sas_ch7_rx_srst_st : 1 ; - UINT32 sas_ch0_tx_srst_st : 1 ; - UINT32 sas_ch1_tx_srst_st : 1 ; - UINT32 sas_ch2_tx_srst_st : 1 ; - UINT32 sas_ch3_tx_srst_st : 1 ; - UINT32 sas_ch4_tx_srst_st : 1 ; - UINT32 sas_ch5_tx_srst_st : 1 ; - UINT32 sas_ch6_tx_srst_st : 1 ; - UINT32 sas_ch7_tx_srst_st : 1 ; - UINT32 reserved_0 : 13 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sas_reset_st; - - -typedef union -{ - - struct - { - UINT32 mctp0_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp0_reset_st; - - -typedef union -{ - - struct - { - UINT32 mctp1_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp1_reset_st; - - -typedef union -{ - - struct - { - UINT32 mctp2_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp2_reset_st; - - -typedef union -{ - - struct - { - UINT32 sllc_tsvrx0_srst_st : 1 ; - UINT32 sllc_tsvrx1_srst_st : 1 ; - UINT32 sllc_tsvrx2_srst_st : 1 ; - UINT32 sllc_tsvrx3_srst_st : 1 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_tsvrx_reset_st; - - -typedef union -{ - - struct - { - UINT32 pcie0_hilink_pcs_lane0_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane1_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane2_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane3_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane4_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane5_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane6_srst_st : 1 ; - UINT32 pcie0_hilink_pcs_lane7_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane0_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane1_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane2_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane3_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane4_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane5_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane6_srst_st : 1 ; - UINT32 pcie1_hilink_pcs_lane7_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane0_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane1_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane2_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane3_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane4_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane5_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane6_srst_st : 1 ; - UINT32 pcie2_hilink_pcs_lane7_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane0_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane1_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane2_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane3_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane4_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane5_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane6_srst_st : 1 ; - UINT32 pcie3_hilink_pcs_lane7_srst_st : 1 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie_hilink_pcs_reset_st; - - -typedef union -{ - - struct - { - UINT32 pcie3_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_reset_st; - - -typedef union -{ - - struct - { - UINT32 mctp3_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_mctp3_reset_st; - - -typedef union -{ - - struct - { - UINT32 its_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_its_reset_st; - - -typedef union -{ - - struct - { - UINT32 sllc_srst_st : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_sllc_reset_st; - - -typedef union -{ - - struct - { - UINT32 pcie0_pcs_local_srst_st : 1 ; - UINT32 pcie1_pcs_local_srst_st : 1 ; - UINT32 pcie2_pcs_local_srst_st : 1 ; - UINT32 pcie3_pcs_local_srst_st : 1 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcs_local_reset_st; - - -typedef union -{ - - struct - { - UINT32 hilink0_plloutoflock : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_plloutoflock; - - -typedef union -{ - - struct - { - UINT32 hilink0_prbs_err : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_prbs_err; - - -typedef union -{ - - struct - { - UINT32 hilink0_los : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink0_macro_los; - - -typedef union -{ - - struct - { - UINT32 hilink1_plloutoflock : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_plloutoflock; - - -typedef union -{ - - struct - { - UINT32 hilink1_prbs_err : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_prbs_err; - - -typedef union -{ - - struct - { - UINT32 hilink1_los : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink1_macro_los; - - -typedef union -{ - - struct - { - UINT32 hilink5_plloutoflock : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_plloutoflock; - - -typedef union -{ - - struct - { - UINT32 hilink5_prbs_err : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_prbs_err; - - -typedef union -{ - - struct - { - UINT32 hilink5_los : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink5_macro_los; - - -typedef union -{ - - struct - { - UINT32 hilink6_plloutoflock : 2 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_plloutoflock; - - -typedef union -{ - - struct - { - UINT32 hilink6_prbs_err : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_prbs_err; - - -typedef union -{ - - struct - { - UINT32 hilink6_los : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_hilink6_macro_los; - - -typedef union -{ - - struct - { - UINT32 pcie0_mac_phy_rxeqinprogress : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_rxeqinpro_stat; - - -typedef union -{ - - struct - { - UINT32 pcie0_cfg_link_eq_req_int : 1 ; - UINT32 pcie0_xmlh_ltssm_state_rcvry_eq : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_linkint_rcvry_stat; - - -typedef union -{ - - struct - { - UINT32 pcie0_gm_cmposer_lookup_err : 1 ; - UINT32 pcie0_radmx_cmposer_lookup_err : 1 ; - UINT32 pcie0_pm_xtlh_block_tlp : 1 ; - UINT32 pcie0_cfg_mem_space_en : 1 ; - UINT32 pcie0_cfg_rcb : 1 ; - UINT32 pcie0_rdlh_link_up : 1 ; - UINT32 pcie0_pm_curnt_state : 3 ; - UINT32 pcie0_cfg_aer_rc_err_int : 1 ; - UINT32 pcie0_cfg_aer_int_msg_num : 5 ; - UINT32 pcie0_xmlh_link_up : 1 ; - UINT32 pcie0_wake : 1 ; - UINT32 pcie0_cfg_eml_control : 1 ; - UINT32 pcie0_hp_pme : 1 ; - UINT32 pcie0_hp_int : 1 ; - UINT32 pcie0_hp_msi : 1 ; - UINT32 pcie0_pm_status : 1 ; - UINT32 pcie0_ref_clk_req_n : 1 ; - UINT32 pcie0_p2_exit_reg : 1 ; - UINT32 pcie0_radm_msg_req_id_low : 8 ; - } Bits; - - - UINT32 UInt32; - -}U_SC_PCIE0_SYS_STATE0; - - -typedef union -{ - - struct - { - UINT32 pcie0_axi_parity_errs_reg : 4 ; - UINT32 pcie0_app_parity_errs_reg : 3 ; - UINT32 pcie0_pm_linkst_in_l1 : 1 ; - UINT32 pcie0_pm_linkst_in_l2 : 1 ; - UINT32 pcie0_pm_linkst_l2_exit : 1 ; - UINT32 pcie0_mac_phy_power_down : 2 ; - UINT32 pcie0_radm_correctabl_err_reg : 1 ; - UINT32 pcie0_radm_nonfatal_err_reg : 1 ; - UINT32 pcie0_radm_fatal_err_reg : 1 ; - UINT32 pcie0_radm_pm_to_pme_reg : 1 ; - UINT32 pcie0_radm_pm_to_ack_reg : 1 ; - UINT32 pcie0_radm_cpl_timeout_reg : 1 ; - UINT32 pcie0_radm_msg_unlock_reg : 1 ; - UINT32 pcie0_cfg_pme_msi_reg : 1 ; - UINT32 pcie0_bridge_flush_not_reg : 1 ; - UINT32 pcie0_link_req_rst_not_reg : 1 ; - UINT32 pcie0_cfg_aer_rc_err_msi : 1 ; - UINT32 pcie0_cfg_sys_err_rc : 1 ; - UINT32 pcie0_radm_msg_req_id_high : 8 ; - } Bits; - - - UINT32 UInt32; - -} U_SC_PCIE0_SYS_STATE1; - - -typedef union -{ - - struct - { - UINT32 pcie0_ltssm_state : 6 ; - UINT32 pcie0_mac_phy_rate : 2 ; - UINT32 pcie0_slv_err_int : 1 ; - UINT32 pcie0_retry_sram_addr : 10 ; - UINT32 pcie0_mstr_rresp_int : 1 ; - UINT32 pcie0_mstr_bresp_int : 1 ; - UINT32 pcie0_radm_inta_reg : 1 ; - UINT32 pcie0_radm_intb_reg : 1 ; - UINT32 pcie0_radm_intc_reg : 1 ; - UINT32 pcie0_radm_intd_reg : 1 ; - UINT32 pcie0_cfg_pme_int_reg : 1 ; - UINT32 pcie0_radm_vendor_msg_reg : 1 ; - UINT32 pcie0_bridge_flush_not : 1 ; - UINT32 pcie0_link_req_rst_not : 1 ; - UINT32 reserved_0 : 3 ; - } Bits; - - - UINT32 UInt32; - -} U_SC_PCIE0_SYS_STATE4; - - -typedef union -{ - - struct - { - UINT32 pcie0_curr_wr_latency : 16 ; - UINT32 pcie0_curr_wr_port_sts : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_axi_mstr_ooo_wr_sts1; - - -typedef union -{ - - struct - { - UINT32 pcie0_curr_rd_latency : 16 ; - UINT32 pcie0_curr_rd_port_sts : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_axi_mstr_ooo_rd_sts1; - - -typedef union -{ - - struct - { - UINT32 pcie0_rob_ecc_err_detect : 1 ; - UINT32 pcie0_rob_ecc_err_multpl : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_dsize_brg_ecc_err; - - -typedef union -{ - - struct - { - UINT32 pcie0_pciephy_ctrl_error : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie0_pciephy_ctrl_error; - - -typedef union -{ - - struct - { - UINT32 pcie1_mac_phy_rxeqinprogress : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_rxeqinpro_stat; - - -typedef union -{ - - struct - { - UINT32 pcie1_cfg_link_eq_req_int : 1 ; - UINT32 pcie1_xmlh_ltssm_state_rcvry_eq : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_linkint_rcvry_stat; - - -typedef union -{ - - struct - { - UINT32 pcie1_gm_cmposer_lookup_err : 1 ; - UINT32 pcie1_radmx_cmposer_lookup_err : 1 ; - UINT32 pcie1_pm_xtlh_block_tlp : 1 ; - UINT32 pcie1_cfg_mem_space_en : 1 ; - UINT32 pcie1_cfg_rcb : 1 ; - UINT32 pcie1_rdlh_link_up : 1 ; - UINT32 pcie1_pm_curnt_state : 3 ; - UINT32 pcie1_cfg_aer_rc_err_int : 1 ; - UINT32 pcie1_cfg_aer_int_msg_num : 5 ; - UINT32 pcie1_xmlh_link_up : 1 ; - UINT32 pcie1_wake : 1 ; - UINT32 pcie1_cfg_eml_control : 1 ; - UINT32 pcie1_hp_pme : 1 ; - UINT32 pcie1_hp_int : 1 ; - UINT32 pcie1_hp_msi : 1 ; - UINT32 pcie1_pm_status : 1 ; - UINT32 pcie1_ref_clk_req_n : 1 ; - UINT32 pcie1_p2_exit_reg : 1 ; - UINT32 pcie1_radm_msg_req_id_low : 8 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_sys_state0; - - -typedef union -{ - - struct - { - UINT32 pcie1_axi_parity_errs_reg : 4 ; - UINT32 pcie1_app_parity_errs_reg : 3 ; - UINT32 pcie1_pm_linkst_in_l1 : 1 ; - UINT32 pcie1_pm_linkst_in_l2 : 1 ; - UINT32 pcie1_pm_linkst_l2_exit : 1 ; - UINT32 pcie1_mac_phy_power_down : 2 ; - UINT32 pcie1_radm_correctabl_err_reg : 1 ; - UINT32 pcie1_radm_nonfatal_err_reg : 1 ; - UINT32 pcie1_radm_fatal_err_reg : 1 ; - UINT32 pcie1_radm_pm_to_pme_reg : 1 ; - UINT32 pcie1_radm_pm_to_ack_reg : 1 ; - UINT32 pcie1_radm_cpl_timeout_reg : 1 ; - UINT32 pcie1_radm_msg_unlock_reg : 1 ; - UINT32 pcie1_cfg_pme_msi_reg : 1 ; - UINT32 pcie1_bridge_flush_not_reg : 1 ; - UINT32 pcie1_link_req_rst_not_reg : 1 ; - UINT32 pcie1_cfg_aer_rc_err_msi : 1 ; - UINT32 pcie1_cfg_sys_err_rc : 1 ; - UINT32 pcie1_radm_msg_req_id_high : 8 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_sys_state1; - - -typedef union -{ - - struct - { - UINT32 pcie1_ltssm_state : 6 ; - UINT32 pcie1_mac_phy_rate : 2 ; - UINT32 pcie1_slv_err_int : 1 ; - UINT32 pcie1_retry_sram_addr : 10 ; - UINT32 pcie1_mstr_rresp_int : 1 ; - UINT32 pcie1_mstr_bresp_int : 1 ; - UINT32 pcie1_radm_inta_reg : 1 ; - UINT32 pcie1_radm_intb_reg : 1 ; - UINT32 pcie1_radm_intc_reg : 1 ; - UINT32 pcie1_radm_intd_reg : 1 ; - UINT32 pcie1_cfg_pme_int_reg : 1 ; - UINT32 pcie1_radm_vendor_msg_reg : 1 ; - UINT32 pcie1_bridge_flush_not : 1 ; - UINT32 pcie1_link_req_rst_not : 1 ; - UINT32 reserved_0 : 3 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_sys_state4; - - -typedef union -{ - - struct - { - UINT32 pcie1_curr_wr_latency : 16 ; - UINT32 pcie1_curr_wr_port_sts : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_axi_mstr_ooo_wr_sts1; - - -typedef union -{ - - struct - { - UINT32 pcie1_curr_rd_latency : 16 ; - UINT32 pcie1_curr_rd_port_sts : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_axi_mstr_ooo_rd_sts1; - - -typedef union -{ - - struct - { - UINT32 pcie1_rob_ecc_err_detect : 1 ; - UINT32 pcie1_rob_ecc_err_multpl : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_dsize_brg_ecc_err; - - -typedef union -{ - - struct - { - UINT32 pcie1_pciephy_ctrl_error : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie1_pciephy_ctrl_error; - - -typedef union -{ - - struct - { - UINT32 pcie2_mac_phy_rxeqinprogress : 8 ; - UINT32 reserved_0 : 24 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_rxeqinpro_stat; - - -typedef union -{ - - struct - { - UINT32 pcie2_cfg_link_eq_req_int : 1 ; - UINT32 pcie2_xmlh_ltssm_state_rcvry_eq : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_linkint_rcvry_stat; - - -typedef union -{ - - struct - { - UINT32 pcie2_gm_cmposer_lookup_err : 1 ; - UINT32 pcie2_radmx_cmposer_lookup_err : 1 ; - UINT32 pcie2_pm_xtlh_block_tlp : 1 ; - UINT32 pcie2_cfg_mem_space_en : 1 ; - UINT32 pcie2_cfg_rcb : 1 ; - UINT32 pcie2_rdlh_link_up : 1 ; - UINT32 pcie2_pm_curnt_state : 3 ; - UINT32 pcie2_cfg_aer_rc_err_int : 1 ; - UINT32 pcie2_cfg_aer_int_msg_num : 5 ; - UINT32 pcie2_xmlh_link_up : 1 ; - UINT32 pcie2_wake : 1 ; - UINT32 pcie2_cfg_eml_control : 1 ; - UINT32 pcie2_hp_pme : 1 ; - UINT32 pcie2_hp_int : 1 ; - UINT32 pcie2_hp_msi : 1 ; - UINT32 pcie2_pm_status : 1 ; - UINT32 pcie2_ref_clk_req_n : 1 ; - UINT32 pcie2_p2_exit_reg : 1 ; - UINT32 pcie2_radm_msg_req_id_low : 8 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_sys_state0; - - -typedef union -{ - - struct - { - UINT32 pcie2_axi_parity_errs_reg : 4 ; - UINT32 pcie2_app_parity_errs_reg : 3 ; - UINT32 pcie2_pm_linkst_in_l1 : 1 ; - UINT32 pcie2_pm_linkst_in_l2 : 1 ; - UINT32 pcie2_pm_linkst_l2_exit : 1 ; - UINT32 pcie2_mac_phy_power_down : 2 ; - UINT32 pcie2_radm_correctabl_err_reg : 1 ; - UINT32 pcie2_radm_nonfatal_err_reg : 1 ; - UINT32 pcie2_radm_fatal_err_reg : 1 ; - UINT32 pcie2_radm_pm_to_pme_reg : 1 ; - UINT32 pcie2_radm_pm_to_ack_reg : 1 ; - UINT32 pcie2_radm_cpl_timeout_reg : 1 ; - UINT32 pcie2_radm_msg_unlock_reg : 1 ; - UINT32 pcie2_cfg_pme_msi_reg : 1 ; - UINT32 pcie2_bridge_flush_not_reg : 1 ; - UINT32 pcie2_link_req_rst_not_reg : 1 ; - UINT32 pcie2_cfg_aer_rc_err_msi : 1 ; - UINT32 pcie2_cfg_sys_err_rc : 1 ; - UINT32 pcie2_radm_msg_req_id_high : 8 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_sys_state1; - - -typedef union -{ - - struct - { - UINT32 pcie2_ltssm_state : 6 ; - UINT32 pcie2_mac_phy_rate : 2 ; - UINT32 pcie2_slv_err_int : 1 ; - UINT32 pcie2_retry_sram_addr : 10 ; - UINT32 pcie2_mstr_rresp_int : 1 ; - UINT32 pcie2_mstr_bresp_int : 1 ; - UINT32 pcie2_radm_inta_reg : 1 ; - UINT32 pcie2_radm_intb_reg : 1 ; - UINT32 pcie2_radm_intc_reg : 1 ; - UINT32 pcie2_radm_intd_reg : 1 ; - UINT32 pcie2_cfg_pme_int_reg : 1 ; - UINT32 pcie2_radm_vendor_msg_reg : 1 ; - UINT32 pcie2_bridge_flush_not : 1 ; - UINT32 pcie2_link_req_rst_not : 1 ; - UINT32 reserved_0 : 3 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_sys_state4; - - -typedef union -{ - - struct - { - UINT32 pcie2_curr_wr_latency : 16 ; - UINT32 pcie2_curr_wr_port_sts : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_axi_mstr_ooo_wr_sts1; - - -typedef union -{ - - struct - { - UINT32 pcie2_curr_rd_latency : 16 ; - UINT32 pcie2_curr_rd_port_sts : 1 ; - UINT32 reserved_0 : 15 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_axi_mstr_ooo_rd_sts1; - - -typedef union -{ - - struct - { - UINT32 pcie2_rob_ecc_err_detect : 1 ; - UINT32 pcie2_rob_ecc_err_multpl : 1 ; - UINT32 reserved_0 : 30 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_dsize_brg_ecc_err; - - -typedef union -{ - - struct - { - UINT32 pcie2_pciephy_ctrl_error : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie2_pciephy_ctrl_error; - - -typedef union -{ - - struct - { - UINT32 pcie3_gm_cmposer_lookup_err : 1 ; - UINT32 pcie3_radmx_cmposer_lookup_err : 1 ; - UINT32 pcie3_pm_xtlh_block_tlp : 1 ; - UINT32 pcie3_cfg_mem_space_en : 1 ; - UINT32 pcie3_cfg_rcb : 1 ; - UINT32 pcie3_rdlh_link_up : 1 ; - UINT32 pcie3_pm_curnt_state : 3 ; - UINT32 pcie3_cfg_aer_rc_err_int : 1 ; - UINT32 pcie3_cfg_aer_int_msg_num : 5 ; - UINT32 pcie3_xmlh_link_up : 1 ; - UINT32 pcie3_wake : 1 ; - UINT32 pcie3_cfg_eml_control : 1 ; - UINT32 pcie3_hp_pme : 1 ; - UINT32 pcie3_hp_int : 1 ; - UINT32 pcie3_hp_msi : 1 ; - UINT32 pcie3_pm_status : 1 ; - UINT32 pcie3_ref_clk_req_n : 1 ; - UINT32 pcie3_p2_exit_reg : 1 ; - UINT32 pcie3_radm_msg_req_id_low : 8 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_sys_state0; - - -typedef union -{ - - struct - { - UINT32 pcie3_axi_parity_errs_reg : 4 ; - UINT32 pcie3_app_parity_errs_reg : 3 ; - UINT32 pcie3_pm_linkst_in_l1 : 1 ; - UINT32 pcie3_pm_linkst_in_l2 : 1 ; - UINT32 pcie3_pm_linkst_l2_exit : 1 ; - UINT32 pcie3_mac_phy_power_down : 2 ; - UINT32 pcie3_radm_correctabl_err_reg : 1 ; - UINT32 pcie3_radm_nonfatal_err_reg : 1 ; - UINT32 pcie3_radm_fatal_err_reg : 1 ; - UINT32 pcie3_radm_pm_to_pme_reg : 1 ; - UINT32 pcie3_radm_pm_to_ack_reg : 1 ; - UINT32 pcie3_radm_cpl_timeout_reg : 1 ; - UINT32 pcie3_radm_msg_unlock_reg : 1 ; - UINT32 pcie3_cfg_pme_msi_reg : 1 ; - UINT32 pcie3_bridge_flush_not_reg : 1 ; - UINT32 pcie3_link_req_rst_not_reg : 1 ; - UINT32 pcie3_cfg_aer_rc_err_msi : 1 ; - UINT32 pcie3_cfg_sys_err_rc : 1 ; - UINT32 pcie3_radm_msg_req_id_high : 8 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_sys_state1; - - -typedef union -{ - - struct - { - UINT32 pcie3_ltssm_state : 6 ; - UINT32 pcie3_mac_phy_rate : 2 ; - UINT32 pcie3_slv_err_int : 1 ; - UINT32 pcie3_retry_sram_addr : 10 ; - UINT32 pcie3_mstr_rresp_int : 1 ; - UINT32 pcie3_mstr_bresp_int : 1 ; - UINT32 pcie3_radm_inta_reg : 1 ; - UINT32 pcie3_radm_intb_reg : 1 ; - UINT32 pcie3_radm_intc_reg : 1 ; - UINT32 pcie3_radm_intd_reg : 1 ; - UINT32 pcie3_cfg_pme_int_reg : 1 ; - UINT32 pcie3_radm_vendor_msg_reg : 1 ; - UINT32 pcie3_bridge_flush_not : 1 ; - UINT32 pcie3_link_req_rst_not : 1 ; - UINT32 reserved_0 : 3 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_sys_state4; - - -typedef union -{ - - struct - { - UINT32 pcie3_pciephy_ctrl_error : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_pcie3_pciephy_ctrl_error; - - -typedef union -{ - - struct - { - UINT32 skew_lock_a : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_st_a_0; - - -typedef union -{ - - struct - { - UINT32 skew_varible_out_a : 16 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_st_a_1; - - -typedef union -{ - - struct - { - UINT32 skew_dcell_out_a_h : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_st_a_3; - - -typedef union -{ - - struct - { - UINT32 skew_lock_b : 1 ; - UINT32 reserved_0 : 31 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_st_b_0; - - -typedef union -{ - - struct - { - UINT32 skew_varible_out_b : 16 ; - UINT32 reserved_0 : 16 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_st_b_1; - - -typedef union -{ - - struct - { - UINT32 skew_dcell_out_b_h : 4 ; - UINT32 reserved_0 : 28 ; - } Bits; - - - UINT32 UInt32; - -} u_sc_skew_st_b_3; - -#endif - - diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S deleted file mode 100644 index 64c1a57550008699a662081e088b2120e4a82661..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// Copyright (c) 2015, Hisilicon Limited. All rights reserved. -// Copyright (c) 2015, Linaro Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -// Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -// -// - -#include -#include - -ASM_FUNC(ArmPlatformPeiBootAction) - ret - -ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c deleted file mode 100644 index 070bd0a7f5dcf84f8c926912a42dde771af138a0..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c +++ /dev/null @@ -1,80 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -* -**/ - -#include -#include -#include -#include - -#include - -extern EFI_STATUS MemInitEntry (VOID); - -/** - Return the current Boot Mode - - This function returns the boot reason on the platform - - @return Return the current Boot Mode of the platform - -**/ -EFI_BOOT_MODE -ArmPlatformGetBootMode ( - VOID - ) -{ - return BOOT_WITH_FULL_CONFIGURATION; -} - -/** - Initialize controllers that must setup in the normal world - - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim - in the PEI phase. - -**/ -RETURN_STATUS -ArmPlatformInitialize ( - IN UINTN MpId - ) -{ - return RETURN_SUCCESS; -} - -EFI_STATUS -PrePeiCoreGetMpCoreInfo ( - OUT UINTN *CoreCount, - OUT ARM_CORE_INFO **ArmCoreTable - ) -{ - return EFI_UNSUPPORTED; -} - -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; - -EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi - } -}; - -VOID -ArmPlatformGetPlatformPpiList ( - OUT UINTN *PpiListSize, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiList - ) -{ - *PpiListSize = sizeof(gPlatformPpiTable); - *PpiList = gPlatformPpiTable; -} diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf deleted file mode 100644 index 2ab649019aa05e9ba204696ef47902cad4edf9e2..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf +++ /dev/null @@ -1,61 +0,0 @@ -#/* @file -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ArmPlatformLib - FILE_GUID = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - IoLib - ArmLib - MemoryAllocationLib - SerialPortLib - -[Sources.common] - ArmPlatformLib.c - ArmPlatformLibMem.c - -[Sources.AARCH64] - AArch64/Helper.S - -[Ppis] - gArmMpCoreInfoPpiGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdFvBaseAddress - - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdArmPrimaryCore - - gArmPlatformTokenSpaceGuid.PcdCoreCount - - gHisiTokenSpaceGuid.PcdNORFlashBase - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - gHisiTokenSpaceGuid.PcdSysControlBaseAddress - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c deleted file mode 100644 index fbcf87e45e053684c43e3203a5b698a59cf7de6a..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c +++ /dev/null @@ -1,87 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -* -**/ - -#include -#include -#include -#include -#include -#include - -#include - -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32 - -// DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED - -/** - Return the Virtual Memory Map of your platform - - This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. - - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- - Virtual Memory mapping. This array must be ended by a zero-filled - entry - -**/ -VOID -ArmPlatformGetVirtualMemoryMap ( - IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap - ) -{ - ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; - UINTN Index; - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - EFI_PEI_HOB_POINTERS NextHob; - - ASSERT (VirtualMemoryMap != NULL); - - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); - if (VirtualMemoryTable == NULL) { - return; - } - - CacheAttributes = DDR_ATTRIBUTES_CACHED; - - Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes); - - // Search for System Memory Hob that contains the EFI resource system memory - NextHob.Raw = GetHobList (); - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) - { - if (NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) - { - if (NextHob.ResourceDescriptor->PhysicalStart > BASE_4GB) - { - VirtualMemoryTable[++Index].PhysicalBase = NextHob.ResourceDescriptor->PhysicalStart; - VirtualMemoryTable[Index].VirtualBase = NextHob.ResourceDescriptor->PhysicalStart; - VirtualMemoryTable[Index].Length =NextHob.ResourceDescriptor->ResourceLength; - VirtualMemoryTable[Index].Attributes = CacheAttributes; - } - } - - NextHob.Raw = GET_NEXT_HOB (NextHob); - } - - // End of Table - VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; - - ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - DEBUG((DEBUG_INFO, "[%a]:[%dL] discriptor count=%d\n", __func__, __LINE__, Index+1)); - - *VirtualMemoryMap = VirtualMemoryTable; -} diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf deleted file mode 100644 index ac587deedfd80cb09588973bfdcd9c51472714b9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/* @file -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ArmPlatformLibSec - FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - IoLib - ArmLib - SerialPortLib - -[Sources.common] - ArmPlatformLib.c - -[Sources.AARCH64] - AArch64/Helper.S - -[FixedPcd] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdFvBaseAddress - - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdArmPrimaryCore - - gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c deleted file mode 100644 index 431806a6239d3e0ce93a23471ab00ee9c30471d6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c +++ /dev/null @@ -1,460 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -STATIC -UINT16 -EFIAPI -GetBBSTypeFromFileSysPath ( - IN CHAR16 *UsbPathTxt, - IN CHAR16 *FileSysPathTxt, - IN EFI_DEVICE_PATH_PROTOCOL *FileSysPath - ) -{ - EFI_DEVICE_PATH_PROTOCOL *Node; - - if (StrnCmp (UsbPathTxt, FileSysPathTxt, StrLen (UsbPathTxt)) == 0) { - Node = FileSysPath; - while (!IsDevicePathEnd (Node)) { - if ((DevicePathType (Node) == MEDIA_DEVICE_PATH) && - (DevicePathSubType (Node) == MEDIA_CDROM_DP)) { - return BBS_TYPE_CDROM; - } - Node = NextDevicePathNode (Node); - } - } - - return BBS_TYPE_UNKNOWN; -} - -STATIC -UINT16 -EFIAPI -GetBBSTypeFromUsbPath ( - IN CONST EFI_DEVICE_PATH_PROTOCOL *UsbPath - ) -{ - EFI_STATUS Status; - EFI_HANDLE *FileSystemHandles; - UINTN NumberFileSystemHandles; - UINTN Index; - EFI_DEVICE_PATH_PROTOCOL *FileSysPath; - EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *DevPathToText; - CHAR16 *UsbPathTxt; - CHAR16 *FileSysPathTxt; - UINT16 Result; - - Status = gBS->LocateProtocol ( - &gEfiDevicePathToTextProtocolGuid, - NULL, - (VOID **) &DevPathToText); - ASSERT_EFI_ERROR(Status); - - Result = BBS_TYPE_UNKNOWN; - UsbPathTxt = DevPathToText->ConvertDevicePathToText (UsbPath, TRUE, TRUE); - if (UsbPathTxt == NULL) { - return Result; - } - - Status = gBS->LocateHandleBuffer ( - ByProtocol, - &gEfiSimpleFileSystemProtocolGuid, - NULL, - &NumberFileSystemHandles, - &FileSystemHandles - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Locate SimpleFileSystemProtocol error(%r)\n", Status)); - FreePool (UsbPathTxt); - return BBS_TYPE_UNKNOWN; - } - - for (Index = 0; Index < NumberFileSystemHandles; Index++) { - FileSysPath = DevicePathFromHandle (FileSystemHandles[Index]); - FileSysPathTxt = DevPathToText->ConvertDevicePathToText (FileSysPath, TRUE, TRUE); - - if (FileSysPathTxt == NULL) { - continue; - } - - Result = GetBBSTypeFromFileSysPath (UsbPathTxt, FileSysPathTxt, FileSysPath); - FreePool (FileSysPathTxt); - - if (Result != BBS_TYPE_UNKNOWN) { - break; - } - } - - if (NumberFileSystemHandles != 0) { - FreePool (FileSystemHandles); - } - - FreePool (UsbPathTxt); - - return Result; -} - -STATIC -UINT16 -EFIAPI -GetBBSTypeFromMessagingDevicePath ( - IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, - IN EFI_DEVICE_PATH_PROTOCOL *Node - ) -{ - VENDOR_DEVICE_PATH *Vendor; - UINT16 Result; - - Result = BBS_TYPE_UNKNOWN; - - switch (DevicePathSubType (Node)) { - case MSG_MAC_ADDR_DP: - Result = BBS_TYPE_EMBEDDED_NETWORK; - break; - - case MSG_USB_DP: - Result = GetBBSTypeFromUsbPath (DevicePath); - if (Result == BBS_TYPE_UNKNOWN) { - Result = BBS_TYPE_USB; - } - break; - - case MSG_SATA_DP: - Result = BBS_TYPE_HARDDRIVE; - break; - - case MSG_VENDOR_DP: - Vendor = (VENDOR_DEVICE_PATH *) (Node); - if (&Vendor->Guid != NULL) { - if (CompareGuid (&Vendor->Guid, &((EFI_GUID) DEVICE_PATH_MESSAGING_SAS))) { - Result = BBS_TYPE_HARDDRIVE; - } - } - break; - - default: - Result = BBS_TYPE_UNKNOWN; - break; - } - - return Result; -} - -STATIC -UINT16 -EFIAPI -GetBBSTypeByDevicePath ( - IN EFI_DEVICE_PATH_PROTOCOL *DevicePath - ) -{ - EFI_DEVICE_PATH_PROTOCOL *Node; - UINT16 Result; - - Result = BBS_TYPE_UNKNOWN; - if (DevicePath == NULL) { - return Result; - } - - Node = DevicePath; - while (!IsDevicePathEnd (Node)) { - switch (DevicePathType (Node)) { - case MEDIA_DEVICE_PATH: - if (DevicePathSubType (Node) == MEDIA_CDROM_DP) { - Result = BBS_TYPE_CDROM; - } - break; - - case MESSAGING_DEVICE_PATH: - Result = GetBBSTypeFromMessagingDevicePath (DevicePath, Node); - break; - - default: - Result = BBS_TYPE_UNKNOWN; - break; - } - - if (Result != BBS_TYPE_UNKNOWN) { - break; - } - - Node = NextDevicePathNode (Node); - } - - return Result; -} - -STATIC -EFI_STATUS -EFIAPI -GetBmcBootOptionsSetting ( - OUT IPMI_GET_BOOT_OPTION *BmcBootOpt - ) -{ - EFI_STATUS Status; - - Status = IpmiCmdGetSysBootOptions (BmcBootOpt); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get iBMC BootOpts %r!\n", Status)); - return Status; - } - - if (BmcBootOpt->BootFlagsValid != BOOT_OPTION_BOOT_FLAG_VALID) { - return EFI_NOT_FOUND; - } - - if (BmcBootOpt->Persistent) { - BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_VALID; - } else { - BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_INVALID; - } - - Status = IpmiCmdSetSysBootOptions (BmcBootOpt); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Set iBMC BootOpts %r!\n", Status)); - } - - return Status; -} - -VOID -EFIAPI -RestoreBootOrder ( - VOID - ) -{ - EFI_STATUS Status; - UINT16 *BootOrder; - UINTN BootOrderSize; - - GetVariable2 ( - L"BootOrderBackup", - &gOemBootVariableGuid, - (VOID **) &BootOrder, - &BootOrderSize - ); - if (BootOrder == NULL) { - return ; - } - - Print (L"\nRestore BootOrder(%d).\n", BootOrderSize / sizeof (UINT16)); - - Status = gRT->SetVariable ( - L"BootOrder", - &gEfiGlobalVariableGuid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS - | EFI_VARIABLE_NON_VOLATILE, - BootOrderSize, - BootOrder - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "SetVariable BootOrder %r!\n", Status)); - } - - Status = gRT->SetVariable ( - L"BootOrderBackup", - &gOemBootVariableGuid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, - 0, - NULL - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "SetVariable BootOrderBackup %r!\n", Status)); - } - - FreePool (BootOrder); -} - - -STATIC -VOID -EFIAPI -RestoreBootOrderOnReadyToBoot ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - // restore BootOrder variable in normal condition. - RestoreBootOrder (); -} - -STATIC -VOID -EFIAPI -UpdateBootOrder ( - IN UINT16 *NewOrder, - IN UINT16 *BootOrder, - IN UINTN BootOrderSize - ) -{ - EFI_STATUS Status; - EFI_EVENT Event; - - Status = gRT->SetVariable ( - L"BootOrderBackup", - &gOemBootVariableGuid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, - BootOrderSize, - BootOrder - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Set BootOrderBackup Variable:%r!\n", Status)); - return; - } - - Status = gRT->SetVariable ( - L"BootOrder", - &gEfiGlobalVariableGuid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS - | EFI_VARIABLE_NON_VOLATILE, - BootOrderSize, - NewOrder - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Set BootOrder Variable:%r!\n", Status)); - return; - } - - // Register notify function to restore BootOrder variable on ReadyToBoot Event. - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - RestoreBootOrderOnReadyToBoot, - NULL, - &gEfiEventReadyToBootGuid, - &Event - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Create ready to boot event %r!\n", Status)); - } -} - -STATIC -VOID -EFIAPI -SetBootOrder ( - IN UINT16 BootType - ) -{ - EFI_STATUS Status; - UINT16 *NewOrder; - UINT16 *RemainBoots; - UINT16 *BootOrder; - UINTN BootOrderSize; - EFI_BOOT_MANAGER_LOAD_OPTION Option; - CHAR16 OptionName[sizeof ("Boot####")]; - UINTN Index; - UINTN SelectCnt; - UINTN RemainCnt; - - GetEfiGlobalVariable2 (L"BootOrder", (VOID **) &BootOrder, &BootOrderSize); - if (BootOrder == NULL) { - return ; - } - - NewOrder = AllocatePool (BootOrderSize); - RemainBoots = AllocatePool (BootOrderSize); - if ((NewOrder == NULL) || (RemainBoots == NULL)) { - DEBUG ((DEBUG_ERROR, "Out of resources.")); - goto Exit; - } - - SelectCnt = 0; - RemainCnt = 0; - - for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) { - UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", BootOrder[Index]); - Status = EfiBootManagerVariableToLoadOption (OptionName, &Option); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Boot%04x is invalid option!\n", BootOrder[Index])); - continue; - } - - if (GetBBSTypeByDevicePath (Option.FilePath) == BootType) { - NewOrder[SelectCnt++] = BootOrder[Index]; - } else { - RemainBoots[RemainCnt++] = BootOrder[Index]; - } - } - - if (SelectCnt != 0) { - // append RemainBoots to NewOrder - for (Index = 0; Index < RemainCnt; Index++) { - NewOrder[SelectCnt + Index] = RemainBoots[Index]; - } - - if (CompareMem (NewOrder, BootOrder, BootOrderSize) != 0) { - UpdateBootOrder (NewOrder, BootOrder, BootOrderSize); - } - } - -Exit: - FreePool (BootOrder); - if (NewOrder != NULL) { - FreePool (NewOrder); - } - if (RemainBoots != NULL) { - FreePool (RemainBoots); - } -} - -VOID -EFIAPI -HandleBmcBootType ( - VOID - ) -{ - EFI_STATUS Status; - IPMI_GET_BOOT_OPTION BmcBootOpt; - UINT16 BootType; - - Status = GetBmcBootOptionsSetting (&BmcBootOpt); - if (EFI_ERROR (Status)) { - return; - } - - Print (L"Boot Type from BMC is %x\n", BmcBootOpt.BootDeviceSelector); - - switch (BmcBootOpt.BootDeviceSelector) { - case ForcePxe: - BootType = BBS_TYPE_EMBEDDED_NETWORK; - break; - - case ForcePrimaryRemovableMedia: - BootType = BBS_TYPE_USB; - break; - - case ForceDefaultHardDisk: - BootType = BBS_TYPE_HARDDRIVE; - break; - - case ForceDefaultCD: - BootType = BBS_TYPE_CDROM; - break; - - default: - return; - } - - SetBootOrder (BootType); -} - diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf deleted file mode 100644 index c5776791a1707198a028f42c6e6818908e6a4651..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = BmcConfigBootLib - FILE_GUID = f174d192-7208-46c1-b9d1-65b2db06ad3b - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = BmcConfigBootLib - -[Sources.common] - BmcConfigBootLib.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - DevicePathLib - IpmiCmdLib - PcdLib - PrintLib - UefiBootManagerLib - -[Guids] - gEfiEventReadyToBootGuid - gOemBootVariableGuid - -[Protocols] - gEfiDevicePathToTextProtocolGuid ## CONSUMES - gEfiSimpleFileSystemProtocolGuid ## CONSUMES - -[Depex] - gEfiDevicePathToTextProtocolGuid diff --git a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.c b/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.c deleted file mode 100644 index adb712b9e5525c943f23eb4646e3d29fe8b556be..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.c +++ /dev/null @@ -1,47 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include - - -VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue) -{ - MmioWrite8 (ulRegAddr + PcdGet64(PcdCpldBaseAddress), ulValue); -} - - -UINT8 ReadCpldReg(UINTN ulRegAddr) -{ - return MmioRead8 (ulRegAddr + PcdGet64(PcdCpldBaseAddress)); -} - - -VOID ReadCpldBytes(UINT16 Addr, UINT8 *Data, UINT8 Bytes) -{ - UINT8 i; - - for(i = 0;i < Bytes; i++) - { - *(Data + i) = ReadCpldReg(Addr + i); - } -} - -VOID WriteCpldBytes(UINT16 Addr, UINT8 *Data, UINT8 Bytes) -{ - UINT8 i; - - for(i = 0; i < Bytes; i++) - { - WriteCpldReg(Addr + i, *(Data + i)); - } -} diff --git a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf b/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf deleted file mode 100644 index ef84a9fe3a485e10ea110831c233c07e88922a4e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf +++ /dev/null @@ -1,41 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = CpldIoLib - FILE_GUID = 4633665C-0029-464E-9788-58B8D49FF57E - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = CpldIoLib - -[Sources.common] - CpldIoLib.c - -[Packages] - MdePkg/MdePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Hisilicon/HisiPkg.dec - - -[LibraryClasses] - DebugLib - IoLib - BaseLib - ArmLib - TimerLib - -[BuildOptions] - -[Pcd] - gHisiTokenSpaceGuid.PcdCpldBaseAddress diff --git a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.c b/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.c deleted file mode 100644 index 1b3543175483602f38d6c466f53157828de80b9b..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.c +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -UINTN mCpldRegAddr; -EFI_EVENT mCpldVirtualAddressChangeEvent; - - -VOID -EFIAPI -CpldVirtualAddressChange ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EfiConvertPointer (0, (VOID **) &mCpldRegAddr); - - return; -} - -RETURN_STATUS -EFIAPI -CpldRuntimeLibConstructor ( - VOID -) -{ - EFI_STATUS Status; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0}; - - mCpldRegAddr = PcdGet64(PcdCpldBaseAddress); - Status = gDS->GetMemorySpaceDescriptor(mCpldRegAddr,&desp); - if(EFI_ERROR(Status)){ - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] GetMemorySpaceDescriptor failed: %r\n", __func__, __LINE__, Status)); - return Status; - } - desp.Attributes |= EFI_MEMORY_RUNTIME; - Status = gDS->SetMemorySpaceAttributes(mCpldRegAddr,0x10000, desp.Attributes); - if(EFI_ERROR(Status)){ - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] SetMemorySpaceAttributes failed: %r\n", __func__, __LINE__, Status)); - return Status; - } - // - // Register notify function for EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_NOTIFY, - CpldVirtualAddressChange, - NULL, - &gEfiEventVirtualAddressChangeGuid, - &mCpldVirtualAddressChangeEvent - ); - ASSERT_EFI_ERROR (Status); - return Status; -} - -EFI_STATUS -EFIAPI -CpldRuntimeLibDestructor ( - VOID - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - - if(!mCpldVirtualAddressChangeEvent ){ - return Status; - } - - Status = gBS->CloseEvent(mCpldVirtualAddressChangeEvent); - return Status; -} - -VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue) -{ - MmioWrite8 (ulRegAddr + mCpldRegAddr, ulValue); -} - -UINT8 ReadCpldReg(UINTN ulRegAddr) -{ - return MmioRead8 (ulRegAddr + mCpldRegAddr); -} - - diff --git a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf b/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf deleted file mode 100644 index b57b6e286692fca64b2dbfe5fb972c7decd519ba..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf +++ /dev/null @@ -1,45 +0,0 @@ -#/** @file -# -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = CpldIoLibRuntime - FILE_GUID = C0939398-4AF5-43d0-B6FF-37996D642C04 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = CpldIoLib - CONSTRUCTOR = CpldRuntimeLibConstructor - DESTRUCTOR = CpldRuntimeLibDestructor - -[Sources.common] - CpldIoLibRuntime.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/Hisilicon/HisiPkg.dec - - -[LibraryClasses] - UefiRuntimeLib - UefiBootServicesTableLib - DxeServicesTableLib - DebugLib - IoLib - BaseLib - TimerLib - PcdLib - -[BuildOptions] - -[Guids] - gEfiEventVirtualAddressChangeGuid -[Pcd] - gHisiTokenSpaceGuid.PcdCpldBaseAddress diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c deleted file mode 100644 index d98970ff7555893be740bafbabc381838befa407..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c +++ /dev/null @@ -1,296 +0,0 @@ -/** @file - UART Serial Port library functions - - Copyright (c) 2006 - 2009, Intel Corporation - Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. - Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. - SPDX-License-Identifier: BSD-2-Clause-Patent - - Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ -**/ -#include -#include -#include -#include -#include - -#include "Dw8250SerialPortLib.h" - - -/** - Initialize the serial device hardware. - - If no initialization is required, then return RETURN_SUCCESS. - If the serial device was successfuly initialized, then return RETURN_SUCCESS. - If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. - - @retval RETURN_SUCCESS The serial device was initialized. - @retval RETURN_DEVICE_ERROR The serail device could not be initialized. - -**/ -RETURN_STATUS -EFIAPI -SerialPortInitialize ( - VOID - ) -{ - UINT32 ulUartClkFreq; - - MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8); - MmioWrite8 (UART_FCR_REG, UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR); - MmioWrite8 (UART_LCR_REG, UART_LCR_DLAB | UART_LCR_DLS8); - - ulUartClkFreq = PcdGet32(PcdUartClkInHz); - - MmioWrite8 (UART_DLL_REG, (ulUartClkFreq / (16 * (UINT32)BAUDRATE) ) & 0xff); - MmioWrite8 (UART_DLH_REG, ((ulUartClkFreq/ (16 * (UINT32)BAUDRATE) ) >> 8 ) & 0xff); - MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8); - MmioWrite8 (UART_IEL_REG, 0x00); - - return RETURN_SUCCESS; -} - - -/** - Write data from buffer to serial device. - - Writes NumberOfBytes data bytes from Buffer to the serial device. - The number of bytes actually written to the serial device is returned. - If the return value is less than NumberOfBytes, then the write operation failed. - - If Buffer is NULL, then ASSERT(). - - If NumberOfBytes is zero, then return 0. - - @param Buffer Pointer to the data buffer to be written. - @param NumberOfBytes Number of bytes to written to the serial device. - - @retval 0 NumberOfBytes is 0. - @retval >0 The number of bytes written to the serial device. - If this value is less than NumberOfBytes, then the read operation failed. - -**/ -UINTN -EFIAPI -SerialPortWrite ( - IN UINT8 *Buffer, - IN UINTN NumberOfBytes -) -{ - UINTN Result; - - if (NULL == Buffer) { - return 0; - } - - Result = NumberOfBytes; - - while (NumberOfBytes--) { - - SerialPortWriteChar(*Buffer); - Buffer++; - } - - return Result; -} - - -/** - Reads data from a serial device into a buffer. - - @param Buffer Pointer to the data buffer to store the data read from the serial device. - @param NumberOfBytes Number of bytes to read from the serial device. - - @retval 0 NumberOfBytes is 0. - @retval >0 The number of bytes read from the serial device. - If this value is less than NumberOfBytes, then the read operation failed. - -**/ -UINTN -EFIAPI -SerialPortRead ( - OUT UINT8 *Buffer, - IN UINTN NumberOfBytes -) -{ - UINTN Result; - - if (NULL == Buffer) { - return 0; - } - - Result = 0; - - while (NumberOfBytes--) { - // - // Wait for the serail port to be ready. - // - *Buffer=SerialPortReadChar(); - Buffer++ ; - Result++; - } - - return Result; -} - -/** - Polls a serial device to see if there is any data waiting to be read. - - Polls aserial device to see if there is any data waiting to be read. - If there is data waiting to be read from the serial device, then TRUE is returned. - If there is no data waiting to be read from the serial device, then FALSE is returned. - - @retval TRUE Data is waiting to be read from the serial device. - @retval FALSE There is no data waiting to be read from the serial device. - -**/ -BOOLEAN -EFIAPI -SerialPortPoll ( - VOID - ) -{ - - return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR); - -} - - -VOID SerialPortWriteChar(UINT8 scShowChar) -{ - UINT32 ulLoop = 0; - - while(ulLoop < (UINT32)UART_SEND_DELAY) - { - - if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02) - { - break; - } - - ulLoop++; - } - MmioWrite8 (UART_THR_REG, (UINT8)scShowChar); - - ulLoop = 0; - while(ulLoop < (UINT32)UART_SEND_DELAY) - { - if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04) - { - break; - } - ulLoop++; - } - - return; -} - - -UINT8 SerialPortReadChar(VOID) -{ - UINT8 recvchar = 0; - - while(1) - { - if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR) - { - break; - } - } - - recvchar = MmioRead8 (UART_RBR_REG); - - return recvchar; -} - -/** - Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, - data bits, and stop bits on a serial device. - - @param BaudRate The requested baud rate. A BaudRate value of 0 will use the - device's default interface speed. - On output, the value actually set. - @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the - serial interface. A ReceiveFifoDepth value of 0 will use - the device's default FIFO depth. - On output, the value actually set. - @param Timeout The requested time out for a single character in microseconds. - This timeout applies to both the transmit and receive side of the - interface. A Timeout value of 0 will use the device's default time - out value. - On output, the value actually set. - @param Parity The type of parity to use on this serial device. A Parity value of - DefaultParity will use the device's default parity value. - On output, the value actually set. - @param DataBits The number of data bits to use on the serial device. A DataBits - vaule of 0 will use the device's default data bit setting. - On output, the value actually set. - @param StopBits The number of stop bits to use on this serial device. A StopBits - value of DefaultStopBits will use the device's default number of - stop bits. - On output, the value actually set. - - @retval RETURN_SUCCESS The new attributes were set on the serial device. - @retval RETURN_UNSUPPORTED The serial device does not support this operation. - @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. - @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortSetAttributes ( - IN OUT UINT64 *BaudRate, - IN OUT UINT32 *ReceiveFifoDepth, - IN OUT UINT32 *Timeout, - IN OUT EFI_PARITY_TYPE *Parity, - IN OUT UINT8 *DataBits, - IN OUT EFI_STOP_BITS_TYPE *StopBits - ) -{ - return RETURN_UNSUPPORTED; -} - -/** - Set the serial device control bits. - - @param Control Control bits which are to be set on the serial device. - - @retval EFI_SUCCESS The new control bits were set on the serial device. - @retval EFI_UNSUPPORTED The serial device does not support this operation. - @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortSetControl ( - IN UINT32 Control - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Get the serial device control bits. - - @param Control Control signals read from the serial device. - - @retval EFI_SUCCESS The control bits were read from the serial device. - @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortGetControl ( - OUT UINT32 *Control - ) -{ - - if (SerialPortPoll ()) { - // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY - *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY; - } else { - *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY; - } - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h deleted file mode 100644 index 0eecb21f5d1e814da957d9edc8214369a834b247..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ -**/ - -#ifndef __DW8250_SERIALPORTLIB_H__ -#define __DW8250_SERIALPORTLIB_H__ - - -#define SERIAL_0_BASE_ADR (PcdGet64(PcdSerialRegisterBase)) - - -#define UART_SEND_DELAY (PcdGet32(PcdSerialPortSendDelay)) -#define BAUDRATE (PcdGet64(PcdUartDefaultBaudRate)) - - -#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_THR) -#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_RBR) -#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL) -#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH) -#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL) -#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR) -#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR) -#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR) -#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR) -#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR) - - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_DLL 0x00 -#define UART_DLH 0x04 -#define UART_IEL 0x04 -#define UART_IIR 0x08 -#define UART_FCR 0x08 -#define UART_LCR 0x0C -#define UART_MCR 0x10 -#define UART_LSR 0x14 -#define UART_USR 0x7C - -/* register definitions */ - -#define UART_FCR_EN 0x01 -#define UART_FCR_RXCLR 0x02 -#define UART_FCR_TXCLR 0x04 -#define UART_FCR_CLEARFIFO 0x00 -#define UART_FCR_RXL1 0x00 -#define UART_FCR_RXL4 0x40 -#define UART_FCR_RXL8 0x80 -#define UART_FCR_RXL14 0xc0 -#define UART_FCR_TXL0 0x00 -#define UART_FCR_TXL4 0x20 -#define UART_FCR_TXL8 0x30 -#define UART_FCR_TXL14 0x10 - -/*LCR Name: Line Control Register fields*/ -#define UART_LCR_DLAB 0x80 -#define UART_LCR_EPS 0x10 -#define UART_LCR_PEN 0x08 -#define UART_LCR_STOP 0x04 -#define UART_LCR_DLS8 0x03 -#define UART_LCR_DLS7 0x02 -#define UART_LCR_DLS6 0x01 -#define UART_LCR_DLS5 0x00 - - -#define UART_DLH_AND_DLL_WIDTH 0xFF - - -#define UART_IER_PTIME 0x80 -#define UART_IER_ELSI 0x04 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ERBFI 0x01 - - -#define UART_IIR_FIFOSE 0xC0 - - -#define UART_IIR_InterruptID 0x01 -#define UART_IIR_INTIDTE 0x02 -#define UART_IIR_INTIDRA 0x04 -#define UART_IIR_INTIDRLS 0x06 -#define UART_IIR_INTMASK 0x0f -#define UART_IIR_RDA 0x04 -#define UART_IIR_TE 0x02 - -#define UART_LSR_TEMT 0x40 -#define UART_LSR_THRE 0x20 -#define UART_LSR_BI 0x10 -#define UART_LSR_FE 0x08 -#define UART_LSR_PE 0x04 -#define UART_LSR_R 0x02 -#define UART_LSR_DR 0x01 - - -#define UART_USR_BUSY 0x01 - -#define FIFO_MAXSIZE 32 - -extern UINT8 SerialPortReadChar(VOID); -extern VOID SerialPortWriteChar(UINT8 scShowChar); - -#endif - diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf deleted file mode 100644 index d5eb7b3d298c1dd3684fc4d9b6f61df5cd1c4c08..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf +++ /dev/null @@ -1,39 +0,0 @@ -#/** @file -# -# Copyright (c) 2011, ARM Ltd. All rights reserved.
-# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Dw8250SerialPortLib - FILE_GUID = 78337705-D2A8-4EA7-9C18-27FC4A8A2C6E - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = SerialPortLib - - -[Sources.common] - Dw8250SerialPortLib.c - - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - IoLib - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gHisiTokenSpaceGuid.PcdSerialPortSendDelay - gHisiTokenSpaceGuid.PcdUartClkInHz diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c b/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c deleted file mode 100644 index 8c68eb21c8951db8de54a874d24bce6c2c9de7af..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c +++ /dev/null @@ -1,350 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ -**/ -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include "Dw8250SerialPortRuntimeLib.h" - -UINT64 mSerialRegBaseAddr = 0; - -EFI_EVENT mSerialVirtualAddressChangeEvent = NULL; - -VOID -EFIAPI -SerialVirtualAddressChangeCallBack ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EfiConvertPointer (0, (VOID **) &mSerialRegBaseAddr); - - return; -} - - -EFI_STATUS -EFIAPI -SerialPortLibDestructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - - if(!mSerialVirtualAddressChangeEvent ){ - return Status; - } - - Status = gBS->CloseEvent(mSerialVirtualAddressChangeEvent); - return Status; -} - -/** - Initialize the serial device hardware. - - If no initialization is required, then return RETURN_SUCCESS. - If the serial device was successfuly initialized, then return RETURN_SUCCESS. - If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. - - @retval RETURN_SUCCESS The serial device was initialized. - @retval RETURN_DEVICE_ERROR The serail device could not be initialized. - -**/ -RETURN_STATUS -EFIAPI -SerialPortInitialize ( - VOID - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0}; - - mSerialRegBaseAddr = PcdGet64(PcdSerialRegisterBase); - - Status = gDS->GetMemorySpaceDescriptor(PcdGet64(PcdSerialRegisterBase),&desp); - if(EFI_ERROR(Status)){ - return Status; - } - desp.Attributes |= EFI_MEMORY_RUNTIME; - Status = gDS->SetMemorySpaceAttributes(PcdGet64(PcdSerialRegisterBase),PcdGet64(PcdSerialRegisterSpaceSize), desp.Attributes); - if(EFI_ERROR(Status)){ - return Status; - } - - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_NOTIFY, - SerialVirtualAddressChangeCallBack, - NULL, - &gEfiEventVirtualAddressChangeGuid, - &mSerialVirtualAddressChangeEvent - ); - - if(EFI_ERROR(Status)){ - mSerialVirtualAddressChangeEvent = NULL; - } - - return Status; -} - - -/** - Write data from buffer to serial device. - - Writes NumberOfBytes data bytes from Buffer to the serial device. - The number of bytes actually written to the serial device is returned. - If the return value is less than NumberOfBytes, then the write operation failed. - - If Buffer is NULL, then ASSERT(). - - If NumberOfBytes is zero, then return 0. - - @param Buffer Pointer to the data buffer to be written. - @param NumberOfBytes Number of bytes to written to the serial device. - - @retval 0 NumberOfBytes is 0. - @retval >0 The number of bytes written to the serial device. - If this value is less than NumberOfBytes, then the read operation failed. - -**/ -UINTN -EFIAPI -SerialPortWrite ( - IN UINT8 *Buffer, - IN UINTN NumberOfBytes -) -{ - UINTN Result; - - if (NULL == Buffer) { - return 0; - } - - Result = NumberOfBytes; - - while (NumberOfBytes--) { - - SerialPortWriteChar(*Buffer); - Buffer++; - } - - return Result; -} - - -/** - Reads data from a serial device into a buffer. - - @param Buffer Pointer to the data buffer to store the data read from the serial device. - @param NumberOfBytes Number of bytes to read from the serial device. - - @retval 0 NumberOfBytes is 0. - @retval >0 The number of bytes read from the serial device. - If this value is less than NumberOfBytes, then the read operation failed. - -**/ -UINTN -EFIAPI -SerialPortRead ( - OUT UINT8 *Buffer, - IN UINTN NumberOfBytes -) -{ - UINTN Result; - - if (NULL == Buffer) { - return 0; - } - - Result = 0; - - while (NumberOfBytes--) { - // - // Wait for the serail port to be ready. - // - *Buffer=SerialPortReadChar(); - Buffer++ ; - Result++; - } - - return Result; -} - -/** - Polls a serial device to see if there is any data waiting to be read. - - Polls aserial device to see if there is any data waiting to be read. - If there is data waiting to be read from the serial device, then TRUE is returned. - If there is no data waiting to be read from the serial device, then FALSE is returned. - - @retval TRUE Data is waiting to be read from the serial device. - @retval FALSE There is no data waiting to be read from the serial device. - -**/ -BOOLEAN -EFIAPI -SerialPortPoll ( - VOID - ) -{ - - return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR); - -} - - -VOID SerialPortWriteChar(UINT8 scShowChar) -{ - UINT32 ulLoop = 0; - - while(ulLoop < (UINT32)UART_SEND_DELAY) - { - - if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02) - { - break; - } - - ulLoop++; - } - MmioWrite8 (UART_THR_REG, (UINT8)scShowChar); - - ulLoop = 0; - while(ulLoop < (UINT32)UART_SEND_DELAY) - { - if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04) - { - break; - } - ulLoop++; - } - - return; -} - - -UINT8 SerialPortReadChar(VOID) -{ - UINT8 recvchar = 0; - - do - { - if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR) { - break; - } - - }while(MmioRead8 (UART_USR_REG) & UART_USR_BUSY); - - recvchar = MmioRead8 (UART_RBR_REG); - - return recvchar; -} - -/** - Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, - data bits, and stop bits on a serial device. - - @param BaudRate The requested baud rate. A BaudRate value of 0 will use the - device's default interface speed. - On output, the value actually set. - @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the - serial interface. A ReceiveFifoDepth value of 0 will use - the device's default FIFO depth. - On output, the value actually set. - @param Timeout The requested time out for a single character in microseconds. - This timeout applies to both the transmit and receive side of the - interface. A Timeout value of 0 will use the device's default time - out value. - On output, the value actually set. - @param Parity The type of parity to use on this serial device. A Parity value of - DefaultParity will use the device's default parity value. - On output, the value actually set. - @param DataBits The number of data bits to use on the serial device. A DataBits - vaule of 0 will use the device's default data bit setting. - On output, the value actually set. - @param StopBits The number of stop bits to use on this serial device. A StopBits - value of DefaultStopBits will use the device's default number of - stop bits. - On output, the value actually set. - - @retval RETURN_SUCCESS The new attributes were set on the serial device. - @retval RETURN_UNSUPPORTED The serial device does not support this operation. - @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. - @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortSetAttributes ( - IN OUT UINT64 *BaudRate, - IN OUT UINT32 *ReceiveFifoDepth, - IN OUT UINT32 *Timeout, - IN OUT EFI_PARITY_TYPE *Parity, - IN OUT UINT8 *DataBits, - IN OUT EFI_STOP_BITS_TYPE *StopBits - ) -{ - return RETURN_UNSUPPORTED; -} - -/** - Set the serial device control bits. - - @param Control Control bits which are to be set on the serial device. - - @retval EFI_SUCCESS The new control bits were set on the serial device. - @retval EFI_UNSUPPORTED The serial device does not support this operation. - @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortSetControl ( - IN UINT32 Control - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Get the serial device control bits. - - @param Control Control signals read from the serial device. - - @retval EFI_SUCCESS The control bits were read from the serial device. - @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortGetControl ( - OUT UINT32 *Control - ) -{ - - if (SerialPortPoll ()) { - // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY - *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY; - } else { - *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY; - } - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h b/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h deleted file mode 100644 index e86282b10eeebcb561d2d09f913ec2acd3e97f34..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ -**/ - -#ifndef __DW8250_SERIALPORTLIB_H__ -#define __DW8250_SERIALPORTLIB_H__ - - -#define SERIAL_0_BASE_ADR (mSerialRegBaseAddr) - - -#define UART_SEND_DELAY (PcdGet32(PcdSerialPortSendDelay)) -#define BAUDRATE (PcdGet64(PcdUartDefaultBaudRate)) - - -#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_THR) -#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_RBR) -#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL) -#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH) -#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL) -#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR) -#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR) -#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR) -#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR) -#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR) - - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_DLL 0x00 -#define UART_DLH 0x04 -#define UART_IEL 0x04 -#define UART_IIR 0x08 -#define UART_FCR 0x08 -#define UART_LCR 0x0C -#define UART_MCR 0x10 -#define UART_LSR 0x14 -#define UART_USR 0x7C - -/* register definitions */ - -#define UART_FCR_EN 0x01 -#define UART_FCR_RXCLR 0x02 -#define UART_FCR_TXCLR 0x04 -#define UART_FCR_CLEARFIFO 0x00 -#define UART_FCR_RXL1 0x00 -#define UART_FCR_RXL4 0x40 -#define UART_FCR_RXL8 0x80 -#define UART_FCR_RXL14 0xc0 -#define UART_FCR_TXL0 0x00 -#define UART_FCR_TXL4 0x20 -#define UART_FCR_TXL8 0x30 -#define UART_FCR_TXL14 0x10 - -/*LCR Name: Line Control Register fields*/ -#define UART_LCR_DLAB 0x80 -#define UART_LCR_EPS 0x10 -#define UART_LCR_PEN 0x08 -#define UART_LCR_STOP 0x04 -#define UART_LCR_DLS8 0x03 -#define UART_LCR_DLS7 0x02 -#define UART_LCR_DLS6 0x01 -#define UART_LCR_DLS5 0x00 - - -#define UART_DLH_AND_DLL_WIDTH 0xFF - - -#define UART_IER_PTIME 0x80 -#define UART_IER_ELSI 0x04 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ERBFI 0x01 - - -#define UART_IIR_FIFOSE 0xC0 - - -#define UART_IIR_InterruptID 0x01 -#define UART_IIR_INTIDTE 0x02 -#define UART_IIR_INTIDRA 0x04 -#define UART_IIR_INTIDRLS 0x06 -#define UART_IIR_INTMASK 0x0f -#define UART_IIR_RDA 0x04 -#define UART_IIR_TE 0x02 - -#define UART_LSR_TEMT 0x40 -#define UART_LSR_THRE 0x20 -#define UART_LSR_BI 0x10 -#define UART_LSR_FE 0x08 -#define UART_LSR_PE 0x04 -#define UART_LSR_R 0x02 -#define UART_LSR_DR 0x01 - - -#define UART_USR_BUSY 0x01 - -#define FIFO_MAXSIZE 32 - -extern UINT8 SerialPortReadChar(VOID); -extern VOID SerialPortWriteChar(UINT8 scShowChar); - -#endif - diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf b/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf deleted file mode 100644 index 3c4e528f7b9889093db573cd455560c496de14c2..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/** @file -# -# Copyright (c) 2011, ARM Ltd. All rights reserved.
-# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Dw8250SerialPortLib - FILE_GUID = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0 - MODULE_TYPE = DXE_RUNTIME_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = SerialPortLib - DESTRUCTOR = SerialPortLibDestructor - -[Sources.common] - Dw8250SerialPortRuntimeLib.c - - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - IoLib - UefiRuntimeLib - UefiBootServicesTableLib - DxeServicesTableLib - -[Guids] - gEfiEventVirtualAddressChangeGuid ## CONSUMES ## Event - -[Pcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gHisiTokenSpaceGuid.PcdSerialPortSendDelay - gHisiTokenSpaceGuid.PcdUartClkInHz diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h deleted file mode 100644 index 1fa824f768e2d6f23d335d8242e03bdef507a942..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h +++ /dev/null @@ -1,270 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _I2C_HW_H_ -#define _I2C_HW_H_ - -#include -#include - -// The HNS I2C port 5 is under I2C extender -#define I2C_EXTENDER_PORT_HNS 5 - -#define I2C_READ_TIMEOUT 500 -#define I2C_DRV_ONCE_WRITE_BYTES_NUM 8 -#define I2C_DRV_ONCE_READ_BYTES_NUM 8 -#define I2C_READ_SIGNAL 0x0100 -#define I2C_TXRX_THRESHOLD 0x7 -#define I2C_SS_SCLHCNT 0x493 -#define I2C_SS_SCLLCNT 0x4fe -#define I2C_CMD_STOP_BIT BIT9 - -#define I2C_REG_WRITE(reg,data) \ - MmioWrite32 ((reg), (data)) - -#define I2C_REG_READ(reg,result) \ - (result) = MmioRead32 ((reg)) - - #define I2C_CON_OFFSET 0x0 - #define I2C_TAR_OFFSET 0x4 - #define I2C_SAR_OFFSET 0x8 - #define I2C_DATA_CMD_OFFSET 0x10 - #define I2C_SS_SCL_HCNT_OFFSET 0x14 - #define I2C_SS_SCL_LCNT_OFFSET 0x18 - #define I2C_FS_SCL_HCNT_OFFSET 0x1c - #define I2C_FS_SCL_LCNT_OFFSET 0x20 - #define I2C_INTR_STAT_OFFSET 0x2c - #define I2C_INTR_MASK_OFFSET 0x30 - #define I2C_RAW_INTR_STAT_OFFSET 0x34 - #define I2C_RX_TL_OFFSET 0x38 - #define I2C_TX_TL_OFFSET 0x3c - #define I2C_CLR_INTR_OFFSET 0x40 - #define I2C_CLR_RX_UNDER_OFFSET 0x44 - #define I2C_CLR_RX_OVER_OFFSET 0x48 - #define I2C_CLR_TX_OVER_OFFSET 0x4c - #define I2C_CLR_RD_REQ_OFFSET 0x50 - #define I2C_CLR_TX_ABRT_OFFSET 0x54 - #define I2C_CLR_RX_DONE_OFFSET 0x58 - #define I2C_CLR_ACTIVITY_OFFSET 0x5c - #define I2C_CLR_STOP_DET_OFFSET 0x60 - #define I2C_CLR_START_DET_OFFSET 0x64 - #define I2C_CLR_GEN_CALL_OFFSET 0x68 - #define I2C_ENABLE_OFFSET 0x6c - #define I2C_STATUS_OFFSET 0x70 - #define I2C_TXFLR_OFFSET 0x74 - #define I2C_RXFLR_OFFSET 0x78 - #define I2C_SDA_HOLD 0x7c - #define I2C_TX_ABRT_SOURCE_OFFSET 0x80 - #define I2C_SLV_DATA_ONLY_OFFSET 0x84 - #define I2C_DMA_CR_OFFSET 0x88 - #define I2C_DMA_TDLR_OFFSET 0x8c - #define I2C_DMA_RDLR_OFFSET 0x90 - #define I2C_SDA_SETUP_OFFSET 0x94 - #define I2C_ACK_GENERAL_CALL_OFFSET 0x98 - #define I2C_ENABLE_STATUS_OFFSET 0x9c - - - typedef union tagI2c0Con - { - struct - { - UINT32 master : 1 ; - UINT32 Speed : 2 ; - UINT32 slave_10bit : 1 ; - UINT32 master_10bit : 1 ; - UINT32 restart_en : 1 ; - UINT32 slave_disable : 1 ; - UINT32 Reserved_0 : 25 ; - } bits; - UINT32 Val32; - } I2C0_CON_U; - - - typedef union tagI2c0Tar - { - struct - { - UINT32 ic_tar : 10 ; - UINT32 gc_or_start : 1 ; - UINT32 special : 1 ; - UINT32 ic_10bitaddr_master : 1 ; - UINT32 Reserved_1 : 19 ; - } bits; - UINT32 Val32; - } I2C0_TAR_U; - - - typedef union tagI2c0DataCmd - { - struct - { - UINT32 dat : 8 ; - UINT32 cmd : 1 ; - UINT32 Reserved_5 : 23 ; - } bits; - UINT32 Val32; - } I2C0_DATA_CMD_U; - - - typedef union tagI2c0SsSclHcnt - { - struct - { - UINT32 ic_ss_scl_hcnt : 16 ; - UINT32 Reserved_7 : 16 ; - } bits; - UINT32 Val32; - } I2C0_SS_SCL_HCNT_U; - - - typedef union tagI2c0SsSclLcnt - { - struct - { - UINT32 ic_ss_scl_lcnt : 16 ; - UINT32 Reserved_9 : 16 ; - } bits; - UINT32 Val32; - } I2C0_SS_SCL_LCNT_U; - - - typedef union tagI2c0FsSclHcnt - { - struct - { - UINT32 ic_fs_scl_hcnt : 16 ; - UINT32 Reserved_11 : 16 ; - } bits; - UINT32 Val32; - } I2C0_FS_SCL_HCNT_U; - - - typedef union tagI2c0FsSclLcnt - { - struct - { - UINT32 ic_fs_scl_lcnt : 16 ; - UINT32 Reserved_13 : 16 ; - } bits; - UINT32 Val32; - } I2C0_FS_SCL_LCNT_U; - - - typedef union tagI2c0IntrMask - { - struct - { - UINT32 m_rx_under : 1 ; - UINT32 m_rx_over : 1 ; - UINT32 m_rx_full : 1 ; - UINT32 m_tx_over : 1 ; - UINT32 m_tx_empty : 1 ; - UINT32 m_rd_req : 1 ; - UINT32 m_tx_abrt : 1 ; - UINT32 m_rx_done : 1 ; - UINT32 m_activity : 1 ; - UINT32 m_stop_det : 1 ; - UINT32 m_start_det : 1 ; - UINT32 m_gen_call : 1 ; - UINT32 Reserved_17 : 20 ; - } bits; - UINT32 Val32; - } I2C0_INTR_MASK_U; - - - typedef union tagI2c0RxTl - { - struct - { - UINT32 rx_tl : 8 ; - UINT32 Reserved_21 : 24 ; - } bits; - UINT32 Val32; - } I2C0_RX_TL_U; - - - typedef union tagI2c0TxTl - { - struct - { - UINT32 tx_tl : 8 ; - UINT32 Reserved_23 : 24 ; - } bits; - UINT32 Val32; - } I2C0_TX_TL_U; - - - typedef union tagI2c0Enable - { - struct - { - UINT32 enable : 1 ; - UINT32 Reserved_47 : 31 ; - } bits; - UINT32 Val32; - } I2C0_ENABLE_U; - - - typedef union tagI2c0Status - { - struct - { - UINT32 activity : 1 ; - UINT32 tfnf : 1 ; - UINT32 tfe : 1 ; - UINT32 rfne : 1 ; - UINT32 rff : 1 ; - UINT32 mst_activity : 1 ; - UINT32 slv_activity : 1 ; - UINT32 Reserved_49 : 25 ; - } bits; - UINT32 Val32; - } I2C0_STATUS_U; - - - typedef union tagI2c0Txflr - { - struct - { - UINT32 txflr : 4 ; - UINT32 Reserved_51 : 28 ; - } bits; - UINT32 Val32; - } I2C0_TXFLR_U; - - - typedef union tagI2c0Rxflr - { - struct - { - UINT32 rxflr : 4 ; - UINT32 Reserved_53 : 28 ; - } bits; - UINT32 Val32; - } I2C0_RXFLR_U; - - - typedef union tagI2c0EnableStatus - { - struct - { - UINT32 ic_en : 1 ; - UINT32 slv_disable_while_busy: 1 ; - UINT32 slv_rx_data_lost : 1 ; - UINT32 Reserved_69 : 29 ; - } bits; - UINT32 Val32; - } I2C0_ENABLE_STATUS_U; - -typedef enum { - I2CTx, - I2CRx -} I2CTransfer; - -#endif diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c deleted file mode 100644 index 20595120245a08a49503e60058c1ce2061d197f4..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c +++ /dev/null @@ -1,600 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "I2CLibInternal.h" -#include "I2CHw.h" - -#define I2C_100KB_SPEED 0x1 -#define I2C_400KB_SPEED 0x2 - -VOID -I2C_Delay ( - UINT32 Count - ) -{ - MicroSecondDelay (Count); - return; -} - - -EFI_STATUS -EFIAPI -I2C_Disable ( - UINT32 Socket, - UINT8 Port - ) -{ - UINT32 TimeCnt = I2C_READ_TIMEOUT; - I2C0_STATUS_U I2cStatusReg; - I2C0_ENABLE_U I2cEnableReg; - I2C0_ENABLE_STATUS_U I2cEnableStatusReg; - - UINTN Base = GetI2cBase (Socket, Port); - - I2C_REG_READ ((Base + I2C_STATUS_OFFSET), I2cStatusReg.Val32); - - while (I2cStatusReg.bits.activity) { - I2C_Delay (10000); - - TimeCnt--; - I2C_REG_READ (Base + I2C_STATUS_OFFSET, I2cStatusReg.Val32); - if (TimeCnt == 0) { - return EFI_DEVICE_ERROR; - } - } - - I2C_REG_READ (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32); - I2cEnableReg.bits.enable = 0; - I2C_REG_WRITE (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32); - - I2C_REG_READ (Base + I2C_ENABLE_OFFSET, I2cEnableStatusReg.Val32); - if (I2cEnableStatusReg.bits.ic_en == 0) { - return EFI_SUCCESS; - } else { - return EFI_DEVICE_ERROR; - } -} - - -EFI_STATUS -EFIAPI -I2C_Enable ( - UINT32 Socket, - UINT8 Port - ) -{ - I2C0_ENABLE_U I2cEnableReg; - I2C0_ENABLE_STATUS_U I2cEnableStatusReg; - UINT32 TimeCnt = I2C_READ_TIMEOUT; - - UINTN Base = GetI2cBase (Socket, Port); - - I2C_REG_READ (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32); - I2cEnableReg.bits.enable = 1; - I2C_REG_WRITE (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32); - - do { - // This is a empirical value for I2C delay. MemoryFence is no need here. - I2C_Delay (10000); - - TimeCnt--; - I2C_REG_READ (Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32); - if (TimeCnt == 0) { - return EFI_DEVICE_ERROR; - } - } while (I2cEnableStatusReg.bits.ic_en == 0); - - return EFI_SUCCESS; -} - -VOID -I2C_SetTarget ( - UINT32 Socket, - UINT8 Port, - UINT32 I2cDeviceAddr - ) -{ - I2C0_TAR_U I2cTargetReg; - - UINTN Base = GetI2cBase (Socket, Port); - - I2C_REG_READ (Base + I2C_TAR_OFFSET, I2cTargetReg.Val32); - I2cTargetReg.bits.ic_tar = I2cDeviceAddr; - I2C_REG_WRITE (Base + I2C_TAR_OFFSET, I2cTargetReg.Val32); - - return; -} - - -EFI_STATUS -EFIAPI -I2CInit ( - UINT32 Socket, - UINT32 Port, - SPEED_MODE SpeedMode - ) -{ - I2C0_CON_U I2cControlReg; - I2C0_SS_SCL_HCNT_U I2cStandardSpeedSclHighCount; - I2C0_SS_SCL_LCNT_U I2cStandardSpeedSclLowCount; - I2C0_RX_TL_U I2cRxFifoReg; - I2C0_TX_TL_U I2cTxFifoReg; - I2C0_INTR_MASK_U I2cIntrMask; - EFI_STATUS Status; - - UINTN Base = GetI2cBase (Socket, Port); - - if ((Socket >= MAX_SOCKET) || - (Port >= I2C_PORT_MAX) || - (SpeedMode >= SPEED_MODE_MAX)) { - return EFI_INVALID_PARAMETER; - } - - Status = I2C_Disable (Socket,Port); - if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; - } - - I2C_REG_READ (Base + I2C_CON_OFFSET, I2cControlReg.Val32); - I2cControlReg.bits.master = 1; - if(SpeedMode == Normal) { - I2cControlReg.bits.Speed = I2C_100KB_SPEED; - } else { - I2cControlReg.bits.Speed = I2C_400KB_SPEED; - } - I2cControlReg.bits.restart_en = 1; - I2cControlReg.bits.slave_disable = 1; - I2C_REG_WRITE (Base + I2C_CON_OFFSET, I2cControlReg.Val32); - - if (SpeedMode == Normal) { - I2C_REG_READ (Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32); - I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT; - I2C_REG_WRITE (Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32); - I2C_REG_READ (Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32); - I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT; - I2C_REG_WRITE (Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32); - } else { - I2C_REG_READ (Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32); - I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT; - I2C_REG_WRITE (Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32); - I2C_REG_READ (Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32); - I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT; - I2C_REG_WRITE (Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32); - } - - I2C_REG_READ (Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32); - I2cRxFifoReg.bits.rx_tl = I2C_TXRX_THRESHOLD; - I2C_REG_WRITE (Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32); - I2C_REG_READ (Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32); - I2cTxFifoReg.bits.tx_tl = I2C_TXRX_THRESHOLD; - I2C_REG_WRITE (Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32); - - I2C_REG_READ (Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32); - I2cIntrMask.Val32 = 0x0; - I2C_REG_WRITE (Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32); - - Status = I2C_Enable (Socket, Port); - if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; - } - - return I2cLibRuntimeSetup (Socket, Port); -} - -EFI_STATUS -EFIAPI -I2CSdaConfig ( - UINT32 Socket, - UINT32 Port - ) -{ - UINTN Base = GetI2cBase (Socket, Port); - - if ((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX)) { - return EFI_INVALID_PARAMETER; - } - - I2C_REG_WRITE (Base + I2C_SDA_HOLD, 0x14); - - return EFI_SUCCESS; -} - - - -UINT32 -I2C_GetTxStatus ( - UINT32 Socket, - UINT8 Port - ) -{ - I2C0_TXFLR_U Fifo; - UINTN Base = GetI2cBase (Socket, Port); - - I2C_REG_READ (Base + I2C_TXFLR_OFFSET, Fifo.Val32); - return Fifo.bits.txflr; -} - -UINT32 -I2C_GetRxStatus ( - UINT32 Socket, - UINT8 Port - ) -{ - I2C0_RXFLR_U Fifo; - UINTN Base = GetI2cBase (Socket, Port); - - I2C_REG_READ (Base + I2C_RXFLR_OFFSET, Fifo.Val32); - return Fifo.bits.rxflr; -} - -EFI_STATUS -EFIAPI -CheckI2CTimeOut ( - UINT32 Socket, - UINT8 Port, - I2CTransfer Transfer - ) -{ - UINT32 Times = 0; - UINT32 Fifo; - - if (Transfer == I2CTx) { - Fifo = I2C_GetTxStatus (Socket, Port); - while (Fifo != 0) { - if (Port == I2C_EXTENDER_PORT_HNS) { - // This is a empirical value for I2C delay. MemoryFence is no need here. - I2C_Delay (1000); - } else { - // This is a empirical value for I2C delay. MemoryFence is no need here. - I2C_Delay (2); - } - if (++Times > I2C_READ_TIMEOUT) { - (VOID)I2C_Disable (Socket, Port); - return EFI_TIMEOUT; - } - Fifo = I2C_GetTxStatus (Socket, Port); - } - } else { - Fifo = I2C_GetRxStatus (Socket, Port); - while (Fifo == 0) { - if (Port == I2C_EXTENDER_PORT_HNS) { - // This is a empirical value for I2C delay. MemoryFence is no need here. - I2C_Delay (1000); - } else { - // This is a empirical value for I2C delay. MemoryFence is no need here. - I2C_Delay (2); - } - if (++Times > I2C_READ_TIMEOUT) { - (VOID)I2C_Disable (Socket, Port); - return EFI_TIMEOUT; - } - Fifo = I2C_GetRxStatus (Socket, Port); - } - } - - return EFI_SUCCESS; -} - - -EFI_STATUS -EFIAPI -WriteBeforeRead ( - I2C_DEVICE *I2cInfo, - UINT32 Length, - UINT8 *pBuf - ) -{ - UINT32 Fifo; - UINT32 Count; - UINT32 Times = 0; - - UINTN Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port); - - I2C_SetTarget (I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress); - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - Fifo = 0; - for (Count = 0; Count < Length; Count++) { - Times = 0; - while (Fifo > I2C_TXRX_THRESHOLD) { - I2C_Delay (2); - if (++Times > I2C_READ_TIMEOUT) { - return EFI_TIMEOUT; - } - Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port); - } - - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, *pBuf++); - Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port); - } - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - return EFI_SUCCESS; -} - - -EFI_STATUS -EFIAPI -I2CWrite( - I2C_DEVICE *I2cInfo, - UINT16 InfoOffset, - UINT32 Length, - UINT8 *pBuf - ) -{ - UINT32 Fifo; - UINT32 Times = 0; - UINT32 Idx; - UINTN Base; - - if (I2cInfo->Port >= I2C_PORT_MAX) { - return EFI_INVALID_PARAMETER; - } - - Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port); - - (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port); - - I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress); - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - if (I2cInfo->DeviceType) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff); - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff); - } else { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff); - } - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - for (Idx = 0; Idx < Length; Idx++) { - Times = 0; - Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port); - while (Fifo > I2C_TXRX_THRESHOLD) { - // This is a empirical value for I2C delay. MemoryFence is no need here. - I2C_Delay (1000); - if (++Times > I2C_READ_TIMEOUT) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_TIMEOUT; - } - Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port); - } - - if (Idx < Length - 1) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (*pBuf++)); - } else { - //Send command stop bit for the last transfer - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT); - } - } - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -I2CRead( - I2C_DEVICE *I2cInfo, - UINT16 InfoOffset, - UINT32 RxLen, - UINT8 *pBuf - ) -{ - UINT8 I2CWAddr[2]; - EFI_STATUS Status; - UINT32 Idx = 0; - UINTN Base; - - if (I2cInfo->Port >= I2C_PORT_MAX) { - return EFI_INVALID_PARAMETER; - } - - (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port); - Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port); - if (I2cInfo->DeviceType) { - I2CWAddr[0] = (InfoOffset >> 8) & 0xff; - I2CWAddr[1] = (InfoOffset & 0xff); - Status = WriteBeforeRead (I2cInfo, 2,I2CWAddr); - if (EFI_ERROR (Status)) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_ABORTED; - } - } else { - I2CWAddr[0] = (InfoOffset & 0xff); - Status = WriteBeforeRead (I2cInfo, 1, I2CWAddr); - if (EFI_ERROR (Status)) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_ABORTED; - } - } - - I2C_SetTarget (I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress); - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - while (RxLen > 0) { - if (RxLen > 1) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL); - } else { - //Send command stop bit for the last transfer - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT); - } - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CRx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - I2C_REG_READ (Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]); - - RxLen --; - } - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -I2CReadMultiByte ( - I2C_DEVICE *I2cInfo, - UINT32 InfoOffset, - UINT32 RxLen, - UINT8 *pBuf - ) -{ - UINT32 Count; - UINT16 TotalLen = 0; - UINT8 I2CWAddr[4]; - EFI_STATUS Status; - UINT32 BytesLeft; - UINT32 Idx = 0; - UINTN Base; - - if (I2cInfo->Port >= I2C_PORT_MAX) { - return EFI_INVALID_PARAMETER; - } - - (VOID)I2C_Enable (I2cInfo->Socket, I2cInfo->Port); - Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port); - if (I2cInfo->DeviceType == DEVICE_TYPE_E2PROM) { - I2CWAddr[0] = (InfoOffset >> 8) & 0xff; - I2CWAddr[1] = (InfoOffset & 0xff); - Status = WriteBeforeRead (I2cInfo, 2,I2CWAddr); - if (EFI_ERROR (Status)) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_ABORTED; - } - } else if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS) { - I2CWAddr[0] = (InfoOffset >> 16) & 0xff; - I2CWAddr[1] = (InfoOffset >> 8) & 0xff; - I2CWAddr[2] = (InfoOffset & 0xff); - Status = WriteBeforeRead (I2cInfo, 3, I2CWAddr); - if (EFI_ERROR (Status)) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_ABORTED; - } - } else if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS) { - I2CWAddr[0] = (InfoOffset >> 24) & 0xff; - I2CWAddr[1] = (InfoOffset >> 16) & 0xff; - I2CWAddr[2] = (InfoOffset >> 8) & 0xff; - I2CWAddr[3] = (InfoOffset & 0xff); - Status = WriteBeforeRead (I2cInfo, 4,I2CWAddr); - if (EFI_ERROR (Status)) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_ABORTED; - } - } else { - I2CWAddr[0] = (InfoOffset & 0xff); - Status = WriteBeforeRead (I2cInfo, 1,I2CWAddr); - if (EFI_ERROR (Status)) { - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - return EFI_ABORTED; - } - } - - I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress); - TotalLen = RxLen; - BytesLeft = TotalLen; - - for (Count = 0; Count < BytesLeft; Count++) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL); - } - - for (Count = 0; Count < BytesLeft; Count++) { - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CRx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - I2C_REG_READ (Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]); - } - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -I2CWriteMultiByte( - I2C_DEVICE *I2cInfo, - UINT32 InfoOffset, - UINT32 Length, - UINT8 *pBuf - ) -{ - UINT32 Idx; - UINTN Base; - - if (I2cInfo->Port >= I2C_PORT_MAX) { - return EFI_INVALID_PARAMETER; - } - - Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port); - - (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port); - - I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress); - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - - if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff); - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff); - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff); - } else if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 24) & 0xff); - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff); - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff); - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff); - } else { - } - - for (Idx = 0; Idx < Length; Idx++) { - I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, *pBuf++); - } - - if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) { - return EFI_TIMEOUT; - } - (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port); - - return EFI_SUCCESS; -} - diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf deleted file mode 100644 index d2edbb28a3c558a667865c404c28f055932e9490..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf +++ /dev/null @@ -1,44 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = I2CLib - FILE_GUID = 162F2DF1-DBF8-41E6-9792-92A96ADEAB40 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = I2CLib - -[Sources.common] - I2CLib.c - I2CLibCommon.c - -[Packages] - MdePkg/MdePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - - -[LibraryClasses] - DebugLib - IoLib - BaseLib - ArmLib - TimerLib - - PlatformSysCtrlLib - -[BuildOptions] - -[Pcd] - diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c b/Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c deleted file mode 100644 index fbe3a4e0a54b69cf651834f486011b9ab246a4b6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibCommon.c +++ /dev/null @@ -1,29 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include - -#include -#include "I2CLibInternal.h" - -UINTN GetI2cBase (UINT32 Socket, UINT8 Port) -{ - return PlatformGetI2cBase(Socket, Port); -} - -EFI_STATUS -I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port) -{ - return EFI_SUCCESS; -} - - diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h b/Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h deleted file mode 100644 index 32e923a50894feb9f1083625a51cc5353fa80e2e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibInternal.h +++ /dev/null @@ -1,23 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef _I2C_LIB_INTERNAL_H_ -#define _I2C_LIB_INTERNAL_H_ - -#include -#include - -UINTN GetI2cBase (UINT32 Socket, UINT8 Port); - -EFI_STATUS -I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port); - - -#endif - diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c deleted file mode 100644 index 890258aed1272116eece033255756e81a28e88cf..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.c +++ /dev/null @@ -1,103 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - - -#include -#include -#include -#include -#include -#include -#include - -#include -#include "I2CLibInternal.h" - -STATIC EFI_EVENT mI2cLibVirtualAddrChangeEvent; - -STATIC UINTN gI2cBase[MAX_SOCKET][I2C_PORT_MAX]; - -UINTN GetI2cBase (UINT32 Socket, UINT8 Port) -{ - if (gI2cBase[Socket][Port] == 0) { - gI2cBase[Socket][Port] = PlatformGetI2cBase(Socket, Port); - } - - return gI2cBase[Socket][Port]; -} - -VOID -EFIAPI -I2cLibVirtualNotifyEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - UINT32 Socket; - UINT8 Port; - - // We assume that all I2C ports used in one runtime driver need to be - // converted into virtual address. - for (Socket = 0; Socket < MAX_SOCKET; Socket++) { - for (Port = 0; Port < I2C_PORT_MAX; Port++) { - if (gI2cBase[Socket][Port] != 0) { - EfiConvertPointer (0x0, (VOID **)&gI2cBase[Socket][Port]); - } - } - } - - return; -} - -EFI_STATUS -I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port) -{ - EFI_STATUS Status; - - UINTN Base = GetI2cBase (Socket, Port); - - // Declare the controller as EFI_MEMORY_RUNTIME - Status = gDS->AddMemorySpace ( - EfiGcdMemoryTypeMemoryMappedIo, - Base, SIZE_64KB, - EFI_MEMORY_UC | EFI_MEMORY_RUNTIME - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "[%a:%d] AddMemorySpace failed: %r\n", __func__, __LINE__, Status)); - } - - Status = gDS->SetMemorySpaceAttributes (Base, SIZE_64KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a:%d] SetMemorySpaceAttributes failed: %r\n", __func__, __LINE__, Status)); - return Status; - } - - // - // Register for the virtual address change event - // - // Only create event once - if (mI2cLibVirtualAddrChangeEvent == NULL) { - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_NOTIFY, - I2cLibVirtualNotifyEvent, - NULL, - &gEfiEventVirtualAddressChangeGuid, - &mI2cLibVirtualAddrChangeEvent - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a:%d] Create event failed: %r\n", __func__, __LINE__, Status)); - return Status; - } - } - - return EFI_SUCCESS; -} - - diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf deleted file mode 100644 index d53de09ea4298743a6b41e697d5a2402432b18a3..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = I2CLibRuntime - FILE_GUID = 2E602B32-9203-44A4-BF28-1FF98BD89523 - MODULE_TYPE = DXE_RUNTIME_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = I2CLib - -[Sources.common] - I2CLib.c - I2CLibRuntime.c - -[Packages] - MdePkg/MdePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - - -[LibraryClasses] - DebugLib - IoLib - BaseLib - ArmLib - TimerLib - DxeServicesTableLib - UefiRuntimeLib - - PlatformSysCtrlLib - -[BuildOptions] - -[Pcd] - diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h deleted file mode 100644 index 09329c49a12470a0ee02a3008f678c4cec2e1655..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h +++ /dev/null @@ -1,145 +0,0 @@ -/** @file - - Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2018, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __M41T83_REAL_TIME_CLOCK_H__ -#define __M41T83_REAL_TIME_CLOCK_H__ - -#define M41T83_REGADDR_DOTSECONDS 0x00 -#define M41T83_REGADDR_SECONDS 0x01 -#define M41T83_REGADDR_MINUTES 0x02 -#define M41T83_REGADDR_HOURS 0x03 -#define M41T83_REGADDR_WEEK_DAY 0x04 -#define M41T83_REGADDR_DAY 0x05 -#define M41T83_REGADDR_MONTH 0x06 -#define M41T83_REGADDR_YEAR 0x07 -#define M41T83_REGADDR_ALARM1SEC 0x0E -#define M41T83_REGADDR_ALARM1MIN 0x0D -#define M41T83_REGADDR_ALARM1HOUR 0x0C -#define M41T83_REGADDR_ALARM1DATE 0x0B -#define M41T83_REGADDR_ALARM1MONTH 0x0A - -#define M41T83_REGADDR_TIMERCONTROL 0x11 - -#define M41T83_REGADDR_ALARM2SEC 0x18 -#define M41T83_REGADDR_ALARM2MIN 0x17 -#define M41T83_REGADDR_ALARM2HOUR 0x16 -#define M41T83_REGADDR_ALARM2DATE 0x15 -#define M41T83_REGADDR_ALARM2MONTH 0x14 - -typedef union { - struct { - UINT8 TD0:1; - UINT8 TD1:1; - UINT8 RSV:3; - UINT8 TIE:1; - UINT8 TITP:1; - UINT8 TE:1; - } Bits; - UINT8 Uint8; -} RTC_M41T83_TIMERCONTROL; - -typedef union { - struct { - UINT8 MicroSeconds; - } Bits; - UINT8 Uint8; -} RTC_M41T83_DOTSECOND; - -typedef union { - struct{ - UINT8 Seconds:7; - UINT8 ST:1; - } Bits; - UINT8 Uint8; -} RTC_M41T83_SECOND; - -typedef union { - struct { - UINT8 Minutes:7; - UINT8 Rsv:1; - } Bits; - UINT8 Uint8; -} RTC_M41T83_MINUTE; - -typedef union { - struct { - UINT8 Hours:6; - UINT8 CB:2; - } Bits; - UINT8 Uint8; -} RTC_M41T83_HOUR; - -typedef union { - struct{ - UINT8 Days:3; - UINT8 Rsv:5; - } Bits; - UINT8 Uint8; -} RTC_M41T83_WEEK_DAY; - -typedef union { - struct{ - UINT8 Days:6; - UINT8 Rsv:2; - } Bits; - UINT8 Uint8; -} RTC_M41T83_MONTH_DAY; - -typedef union { - struct { - UINT8 Months:5; - UINT8 Rsv:3; - } Bits; - UINT8 Uint8; -} RTC_M41T83_MONTH; - -typedef union { - struct { - UINT8 Years:8; - } Bits; - UINT8 Uint8; -} RTC_M41T83_YEAR; - -typedef union { - struct { - UINT8 Second:7; - UINT8 RPT11:1; - } Bits; - UINT8 Uint8; -} RTC_M41T83_ALARM1SEC; - -typedef union { - struct { - UINT8 Minute:7; - UINT8 RPT12:1; - } Bits; - UINT8 Uint8; -} RTC_M41T83_ALARM1MIN; - -typedef union { - struct { - UINT8 Hour:6; - UINT8 HT:1; - UINT8 RPT13:1; - } Bits; - UINT8 Uint8; -} RTC_M41T83_ALARM1HOUR; - -typedef struct { - RTC_M41T83_DOTSECOND DotSecond; - RTC_M41T83_SECOND Second; - RTC_M41T83_MINUTE Minute; - RTC_M41T83_HOUR Hour; - RTC_M41T83_WEEK_DAY WeekDay; - RTC_M41T83_MONTH_DAY Day; - RTC_M41T83_MONTH Month; - RTC_M41T83_YEAR Year; -} RTC_M41T83_TIME; - -#endif diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c deleted file mode 100644 index 1971c33eeffbb58ab817c48f1420574ad82b9ab6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c +++ /dev/null @@ -1,468 +0,0 @@ -/** @file - - Copyright (c) 2018, Hisilicon Limited. All rights reserved.
- Copyright (c) 2018, Linaro Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "M41T83RealTimeClock.h" - -extern I2C_DEVICE gRtcDevice; - -STATIC EFI_LOCK mRtcLock; - -/** - Read RTC content through its registers. - - @param Address Address offset of RTC data. - @param Size Size of RTC data to read. - @param Data The data of UINT8 type read from RTC. - - @return EFI_STATUS -**/ -EFI_STATUS -RtcRead ( - IN UINT8 Address, - IN UINT8 Size, - OUT UINT8 *Data - ) -{ - EFI_STATUS Status; - - Status = I2CRead (&gRtcDevice, Address, Size, Data); - MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - return Status; -} - -/** - Write RTC through its registers. - - @param Address Address offset of RTC data. - @param Size Size of RTC data to write. - @param Data The data of UINT8 type write from RTC. - - @return EFI_STATUS -**/ -EFI_STATUS -RtcWrite ( - IN UINT8 Address, - IN UINT8 Size, - UINT8 *Data - ) -{ - EFI_STATUS Status; - - Status = I2CWrite (&gRtcDevice, Address, Size, Data); - MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - return Status; -} - -EFI_STATUS -InitializeM41T83 ( - VOID - ) -{ - EFI_STATUS Status; - RTC_M41T83_ALARM1HOUR Alarm1Hour; - RTC_M41T83_SECOND Second; - - // Acquire RTC Lock to make access to RTC atomic - if (!EfiAtRuntime ()) { - EfiAcquireLock (&mRtcLock); - } - - Status = I2CInit (gRtcDevice.Socket, gRtcDevice.Port, Normal); - MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - if (EFI_ERROR (Status)) { - if (!EfiAtRuntime ()) { - EfiReleaseLock (&mRtcLock); - } - return Status; - } - - Status = SwitchRtcI2cChannelAndLock (); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get i2c preemption failed: %r\n", Status)); - if (!EfiAtRuntime ()) { - EfiReleaseLock (&mRtcLock); - } - return Status; - } - - MicroSecondDelay(RTC_DELAY_1000_MICROSECOND); - - // Set ST at Power up to clear Oscillator fail detection(OF) - Status = RtcRead (M41T83_REGADDR_SECONDS, 1, &Second.Uint8); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - } - Second.Bits.ST= 1; - Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &Second.Uint8); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - goto Exit; - } - Status = RtcRead (M41T83_REGADDR_SECONDS, 1, &Second.Uint8); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - } - Second.Bits.ST= 0; - Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &Second.Uint8); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - goto Exit; - } - - // Clear HT bit to enanle write to the RTC registers (addresses 0-7) - Status = RtcRead (M41T83_REGADDR_ALARM1HOUR, 1, &Alarm1Hour.Uint8); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - } - Alarm1Hour.Bits.HT = 0; - Status = RtcWrite (M41T83_REGADDR_ALARM1HOUR, 1, &Alarm1Hour.Uint8); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - goto Exit; - } - -Exit: - // Release RTC Lock. - ReleaseOwnershipOfRtc (); - if (!EfiAtRuntime ()) { - EfiReleaseLock (&mRtcLock); - } - return Status; -} - -/** - Sets the current local time and date information. - - @param Time A pointer to the current time. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_INVALID_PARAMETER A time field is out of range. - @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. - -**/ -EFI_STATUS -EFIAPI -LibSetTime ( - IN EFI_TIME *Time - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - RTC_M41T83_TIME BcdTime; - UINT16 CenturyBase = 2000; - UINTN LineNum = 0; - - if (NULL == Time) { - return EFI_INVALID_PARAMETER; - } - - if (!IsTimeValid (Time)) { - if (!EfiAtRuntime ()) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, __LINE__, Status)); - DEBUG ((DEBUG_ERROR, "Now RTC Time is : %04d-%02d-%02d %02d:%02d:%02d\n", - Time->Year, Time->Month, Time->Day, Time->Hour, Time->Minute, Time->Second - )); - } - return EFI_INVALID_PARAMETER; - } - - Status = SwitchRtcI2cChannelAndLock (); - if (EFI_ERROR (Status)) { - return Status; - } - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - - SetMem (&BcdTime, sizeof (RTC_M41T83_TIME), 0); - - // Acquire RTC Lock to make access to RTC atomic - if (!EfiAtRuntime ()) { - EfiAcquireLock (&mRtcLock); - } - - BcdTime.Second.Bits.Seconds = DecimalToBcd8 (Time->Second); - BcdTime.Minute.Bits.Minutes = DecimalToBcd8 (Time->Minute); - BcdTime.Hour.Bits.Hours = DecimalToBcd8 (Time->Hour); - BcdTime.Day.Bits.Days = DecimalToBcd8 (Time->Day); - BcdTime.Month.Bits.Months = DecimalToBcd8 (Time->Month); - BcdTime.Year.Bits.Years = DecimalToBcd8 (Time->Year % 100); - BcdTime.Hour.Bits.CB = (Time->Year - CenturyBase) / 100 % 10; - - Status = RtcWrite (M41T83_REGADDR_DOTSECONDS, 1, &BcdTime.DotSecond.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &BcdTime.Second.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - Status = RtcWrite (M41T83_REGADDR_MINUTES, 1, &BcdTime.Minute.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - Status = RtcWrite (M41T83_REGADDR_HOURS, 1, &BcdTime.Hour.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - Status = RtcWrite (M41T83_REGADDR_DAY, 1, &BcdTime.Day.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - Status = RtcWrite (M41T83_REGADDR_MONTH, 1, &BcdTime.Month.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - Status = RtcWrite (M41T83_REGADDR_YEAR, 1, &BcdTime.Year.Uint8); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - -Exit: - ReleaseOwnershipOfRtc (); - // Release RTC Lock. - if (!EfiAtRuntime ()) { - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, LineNum, Status)); - } - EfiReleaseLock (&mRtcLock); - } - return Status; -} - - -/** - Returns the current time and date information, and the time-keeping capabilities - of the hardware platform. - - @param Time A pointer to storage to receive a snapshot of the current time. - @param Capabilities An optional pointer to a buffer to receive the real time clock - device's capabilities. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_INVALID_PARAMETER Time is NULL. - @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. - @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure. -**/ -EFI_STATUS -EFIAPI -LibGetTime ( - OUT EFI_TIME *Time, - OUT EFI_TIME_CAPABILITIES *Capabilities - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - RTC_M41T83_TIME BcdTime; - UINT16 CenturyBase = 2000; - UINTN LineNum = 0; - BOOLEAN IsTimeInvalid = FALSE; - UINT8 TimeTemp[7] = {0}; - - // Ensure Time is a valid pointer - if (Time == NULL) { - return EFI_INVALID_PARAMETER; - } - - Status = SwitchRtcI2cChannelAndLock (); - if (EFI_ERROR (Status)) { - return Status; - } - - MicroSecondDelay(RTC_DELAY_1000_MICROSECOND); - - SetMem (&BcdTime, sizeof (RTC_M41T83_TIME), 0); - SetMem (Time , sizeof (EFI_TIME), 0); - - // Acquire RTC Lock to make access to RTC atomic - if (!EfiAtRuntime ()) { - EfiAcquireLock (&mRtcLock); - } - - Status = RtcRead (M41T83_REGADDR_SECONDS, 7, TimeTemp); - if (EFI_ERROR (Status)) { - LineNum = __LINE__; - goto Exit; - } - - BcdTime.Second.Uint8 = TimeTemp[0]; //SECONDS - BcdTime.Minute.Uint8 = TimeTemp[1]; //MINUTES - BcdTime.Hour.Uint8 = TimeTemp[2]; //HOURS - BcdTime.Day.Uint8 = TimeTemp[4]; //DAY - BcdTime.Month.Uint8 = TimeTemp[5]; //MONTH - BcdTime.Year.Uint8 = TimeTemp[6]; //Year - - Time->Year = BcdToDecimal8 (BcdTime.Year.Bits.Years); - Time->Year += CenturyBase + BcdTime.Hour.Bits.CB * 100; - Time->Month = BcdToDecimal8 (BcdTime.Month.Bits.Months); - Time->Day = BcdToDecimal8 (BcdTime.Day.Bits.Days); - Time->Hour = BcdToDecimal8 (BcdTime.Hour.Bits.Hours); - Time->Minute = BcdToDecimal8 (BcdTime.Minute.Bits.Minutes); - Time->Second = BcdToDecimal8 (BcdTime.Second.Bits.Seconds); - Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; - - if (!IsTimeValid (Time)) { - Status = EFI_DEVICE_ERROR; - LineNum = __LINE__; - IsTimeInvalid = TRUE; - goto Exit; - } - -Exit: - ReleaseOwnershipOfRtc (); - // Release RTC Lock. - if (!EfiAtRuntime ()) { - if (EFI_ERROR (Status)) { - if (IsTimeInvalid == TRUE) { - DEBUG((DEBUG_ERROR, "%a(%d) Time invalid.\r\n",__func__, LineNum)); - } else { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", - __func__, LineNum, Status)); - } - } - EfiReleaseLock (&mRtcLock); - } - return Status; -} - - -/** - Returns the current wakeup alarm clock setting. - - @param Enabled Indicates if the alarm is currently enabled or disabled. - @param Pending Indicates if the alarm signal is pending and requires acknowledgement. - @param Time The current alarm setting. - - @retval EFI_SUCCESS The alarm settings were returned. - @retval EFI_INVALID_PARAMETER Any parameter is NULL. - @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. - -**/ -EFI_STATUS -EFIAPI -LibGetWakeupTime ( - OUT BOOLEAN *Enabled, - OUT BOOLEAN *Pending, - OUT EFI_TIME *Time - ) -{ - // Not a required feature - return EFI_UNSUPPORTED; -} - - -/** - Sets the system wakeup alarm clock time. - - @param Enabled Enable or disable the wakeup alarm. - @param Time If Enable is TRUE, the time to set the wakeup alarm for. - - @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If - Enable is FALSE, then the wakeup alarm was disabled. - @retval EFI_INVALID_PARAMETER A time field is out of range. - @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. - @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. - -**/ -EFI_STATUS -EFIAPI -LibSetWakeupTime ( - IN BOOLEAN Enabled, - OUT EFI_TIME *Time - ) -{ - // Not a required feature - return EFI_UNSUPPORTED; -} - - -/** - This is the declaration of an EFI image entry point. This can be the entry point to an application - written to this specification, an EFI boot service driver, or an EFI runtime driver. - - @param ImageHandle Handle that identifies the loaded image. - @param SystemTable System Table for this image. - - @retval EFI_SUCCESS The operation completed successfully. - -**/ -EFI_STATUS -EFIAPI -LibRtcInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - EFI_TIME EfiTime; - - EfiInitializeLock (&mRtcLock, TPL_CALLBACK); - - Status = InitializeM41T83 (); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\nRTC M41T83 Init Failed !!!\n", - __func__, __LINE__, Status)); - /* - * Returning ERROR on failure of RTC initilization will cause the system to hang up. - * So we add some debug message to indecate the RTC initilization failed, - * and continue without returning with error to avoid system hanging up. - * - *return Status; - */ - } - - LibGetTime (&EfiTime, NULL); - if (!IsTimeValid (&EfiTime)) { - EfiTime.Year = 2015; - EfiTime.Month = 1; - EfiTime.Day = 1; - EfiTime.Hour = 0; - EfiTime.Minute = 0; - EfiTime.Second = 0; - Status = LibSetTime (&EfiTime); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] RTC settime Status : %r\n", - __func__, __LINE__, Status)); - } - } - - DEBUG (( - DEBUG_ERROR, "Now RTC Time is : %04d-%02d-%02d %02d:%02d:%02d\n", - EfiTime.Year, EfiTime.Month, EfiTime.Day, EfiTime.Hour, EfiTime.Minute, - EfiTime.Second - )); - /* - * Returning ERROR on failure of RTC initilization will cause the system to hang up. - * So we add some debug message to indecate the RTC initilization failed, - * and return success to avoid system hanging up. - */ - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf deleted file mode 100644 index 5970c0ef729f0ea2fc2e878a03424f1fbebc53d6..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf +++ /dev/null @@ -1,41 +0,0 @@ -#/** @file -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
-# Copyright (c) 2018, Linaro Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = M41T83RealTimeClockLib - FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = RealTimeClockLib - -[Sources.common] - M41T83RealTimeClockLib.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - Platform/Hisilicon/D06/D06.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseMemoryLib - CpldIoLib - DebugLib - I2CLib - IoLib - PcdLib - RtcHelperLib - TimeBaseLib - TimerLib - UefiLib - UefiRuntimeLib # Use EFiAtRuntime to check stage - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c deleted file mode 100644 index acca25820c3f529292f7129578ba207e8ba5bbca..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c +++ /dev/null @@ -1,712 +0,0 @@ -/** @file - Implementation for PlatformBootManagerLib library class interfaces. - - Copyright (c) 2018, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Ltd. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "PlatformBm.h" - -#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) } - - -#pragma pack (1) -typedef struct { - VENDOR_DEVICE_PATH SerialDxe; - UART_DEVICE_PATH Uart; - VENDOR_DEFINED_DEVICE_PATH TermType; - EFI_DEVICE_PATH_PROTOCOL End; -} PLATFORM_SERIAL_CONSOLE; -#pragma pack () - -#define SERIAL_DXE_FILE_GUID { \ - 0xD3987D4B, 0x971A, 0x435F, \ - { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \ - } - -EFI_GUID EblAppGuid2 = {0x3CEF354A,0x3B7A,0x4519,{0xAD,0x70,0x72,0xA1,0x34,0x69,0x83,0x11}}; - -STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { - // - // VENDOR_DEVICE_PATH SerialDxe - // - { - { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) }, - SERIAL_DXE_FILE_GUID - }, - - // - // UART_DEVICE_PATH Uart - // - { - { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) }, - 0, // Reserved - FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate - FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits - FixedPcdGet8 (PcdUartDefaultParity), // Parity - FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits - }, - - // - // VENDOR_DEFINED_DEVICE_PATH TermType - // - { - { - MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, - DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) - } - // - // Guid to be filled in dynamically - // - }, - - // - // EFI_DEVICE_PATH_PROTOCOL End - // - { - END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, - DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) - } -}; - - -#pragma pack (1) -typedef struct { - USB_CLASS_DEVICE_PATH Keyboard; - EFI_DEVICE_PATH_PROTOCOL End; -} PLATFORM_USB_KEYBOARD; -#pragma pack () - -STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = { - // - // USB_CLASS_DEVICE_PATH Keyboard - // - { - { - MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, - DP_NODE_LEN (USB_CLASS_DEVICE_PATH) - }, - 0xFFFF, // VendorId: any - 0xFFFF, // ProductId: any - 3, // DeviceClass: HID - 1, // DeviceSubClass: boot - 1 // DeviceProtocol: keyboard - }, - - // - // EFI_DEVICE_PATH_PROTOCOL End - // - { - END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, - DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) - } -}; - - -/** - Check if the handle satisfies a particular condition. - - @param[in] Handle The handle to check. - @param[in] ReportText A caller-allocated string passed in for reporting - purposes. It must never be NULL. - - @retval TRUE The condition is satisfied. - @retval FALSE Otherwise. This includes the case when the condition could not - be fully evaluated due to an error. -**/ -typedef -BOOLEAN -(EFIAPI *FILTER_FUNCTION) ( - IN EFI_HANDLE Handle, - IN CONST CHAR16 *ReportText - ); - - -/** - Process a handle. - - @param[in] Handle The handle to process. - @param[in] ReportText A caller-allocated string passed in for reporting - purposes. It must never be NULL. -**/ -typedef -VOID -(EFIAPI *CALLBACK_FUNCTION) ( - IN EFI_HANDLE Handle, - IN CONST CHAR16 *ReportText - ); - -/** - Locate all handles that carry the specified protocol, filter them with a - callback function, and pass each handle that passes the filter to another - callback. - - @param[in] ProtocolGuid The protocol to look for. - - @param[in] Filter The filter function to pass each handle to. If this - parameter is NULL, then all handles are processed. - - @param[in] Process The callback function to pass each handle to that - clears the filter. -**/ -STATIC -VOID -FilterAndProcess ( - IN EFI_GUID *ProtocolGuid, - IN FILTER_FUNCTION Filter OPTIONAL, - IN CALLBACK_FUNCTION Process - ) -{ - EFI_STATUS Status; - EFI_HANDLE *Handles; - UINTN NoHandles; - UINTN Idx; - - Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid, - NULL /* SearchKey */, &NoHandles, &Handles); - if (EFI_ERROR (Status)) { - // - // This is not an error, just an informative condition. - // - DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __func__, ProtocolGuid, - Status)); - return; - } - - ASSERT (NoHandles > 0); - for (Idx = 0; Idx < NoHandles; ++Idx) { - CHAR16 *DevicePathText; - STATIC CHAR16 Fallback[] = L""; - - // - // The ConvertDevicePathToText() function handles NULL input transparently. - // - DevicePathText = ConvertDevicePathToText ( - DevicePathFromHandle (Handles[Idx]), - FALSE, // DisplayOnly - FALSE // AllowShortcuts - ); - if (DevicePathText == NULL) { - DevicePathText = Fallback; - } - - if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) { - Process (Handles[Idx], DevicePathText); - } - - if (DevicePathText != Fallback) { - FreePool (DevicePathText); - } - } - gBS->FreePool (Handles); -} - - -/** - This FILTER_FUNCTION checks if a handle corresponds to a PCI display device. -**/ -STATIC -BOOLEAN -EFIAPI -IsPciDisplay ( - IN EFI_HANDLE Handle, - IN CONST CHAR16 *ReportText - ) -{ - EFI_STATUS Status; - EFI_PCI_IO_PROTOCOL *PciIo; - PCI_TYPE00 Pci; - - Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid, - (VOID**)&PciIo); - if (EFI_ERROR (Status)) { - // - // This is not an error worth reporting. - // - return FALSE; - } - - Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */, - sizeof Pci / sizeof (UINT32), &Pci); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __func__, ReportText, Status)); - return FALSE; - } - - return IS_PCI_DISPLAY (&Pci); -} - - -/** - This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking - the matching driver to produce all first-level child handles. -**/ -STATIC -VOID -EFIAPI -Connect ( - IN EFI_HANDLE Handle, - IN CONST CHAR16 *ReportText - ) -{ - EFI_STATUS Status; - - Status = gBS->ConnectController ( - Handle, // ControllerHandle - NULL, // DriverImageHandle - NULL, // RemainingDevicePath -- produce all children - FALSE // Recursive - ); - DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, "%a: %s: %r\n", - __func__, ReportText, Status)); -} - - -/** - This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the - handle, and adds it to ConOut and ErrOut. -**/ -STATIC -VOID -EFIAPI -AddOutput ( - IN EFI_HANDLE Handle, - IN CONST CHAR16 *ReportText - ) -{ - EFI_STATUS Status; - EFI_DEVICE_PATH_PROTOCOL *DevicePath; - - DevicePath = DevicePathFromHandle (Handle); - if (DevicePath == NULL) { - DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n", - __func__, ReportText, Handle)); - return; - } - - Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __func__, - ReportText, Status)); - return; - } - - Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __func__, - ReportText, Status)); - return; - } - - DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __func__, - ReportText)); -} - -STATIC -VOID -PlatformRegisterFvBootOption ( - EFI_GUID *FileGuid, - CHAR16 *Description, - UINT32 Attributes - ) -{ - EFI_STATUS Status; - INTN OptionIndex; - EFI_BOOT_MANAGER_LOAD_OPTION NewOption; - EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; - UINTN BootOptionCount; - MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; - EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; - EFI_DEVICE_PATH_PROTOCOL *DevicePath; - - Status = gBS->HandleProtocol ( - gImageHandle, - &gEfiLoadedImageProtocolGuid, - (VOID **) &LoadedImage - ); - ASSERT_EFI_ERROR (Status); - - EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); - DevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle); - ASSERT (DevicePath != NULL); - DevicePath = AppendDevicePathNode ( - DevicePath, - (EFI_DEVICE_PATH_PROTOCOL *) &FileNode - ); - ASSERT (DevicePath != NULL); - - Status = EfiBootManagerInitializeLoadOption ( - &NewOption, - LoadOptionNumberUnassigned, - LoadOptionTypeBoot, - Attributes, - Description, - DevicePath, - NULL, - 0 - ); - ASSERT_EFI_ERROR (Status); - FreePool (DevicePath); - - BootOptions = EfiBootManagerGetLoadOptions ( - &BootOptionCount, LoadOptionTypeBoot - ); - - OptionIndex = EfiBootManagerFindLoadOption ( - &NewOption, BootOptions, BootOptionCount - ); - - if (OptionIndex == -1) { - Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN); - ASSERT_EFI_ERROR (Status); - } - EfiBootManagerFreeLoadOption (&NewOption); - EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); -} - - -STATIC -VOID -PlatformRegisterOptionsAndKeys ( - VOID - ) -{ - EFI_STATUS Status; - EFI_INPUT_KEY Enter; - EFI_INPUT_KEY F2; - EFI_INPUT_KEY Esc; - EFI_BOOT_MANAGER_LOAD_OPTION BootOption; - - // - // Register ENTER as CONTINUE key - // - Enter.ScanCode = SCAN_NULL; - Enter.UnicodeChar = CHAR_CARRIAGE_RETURN; - Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); - ASSERT_EFI_ERROR (Status); - - // - // Map F2 and ESC to Boot Manager Menu - // - F2.ScanCode = SCAN_F2; - F2.UnicodeChar = CHAR_NULL; - Esc.ScanCode = SCAN_ESC; - Esc.UnicodeChar = CHAR_NULL; - - Status = EfiBootManagerGetBootManagerMenu (&BootOption); - ASSERT_EFI_ERROR (Status); - Status = EfiBootManagerAddKeyOptionVariable ( - NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL - ); - ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED); - Status = EfiBootManagerAddKeyOptionVariable ( - NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL - ); - ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED); -} - -STATIC -VOID -UpdateMemory ( - ) -{ - EFI_STATUS Status; - EFI_GENERIC_MEMORY_TEST_PROTOCOL* MemoryTest; - BOOLEAN RequireSoftECCInit; - - RequireSoftECCInit = FALSE; - - // Add MemoryTest for memmap add above 4G memory. - Status = gBS->LocateProtocol ( - &gEfiGenericMemTestProtocolGuid, - NULL, - (VOID **)&MemoryTest); - if (!EFI_ERROR (Status)) { - Status = MemoryTest->MemoryTestInit ( - MemoryTest, - IGNORE, - &RequireSoftECCInit); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "MemoryTestInit fail(%r)\n", Status)); - } - } else { - DEBUG ((DEBUG_ERROR, "Get GenericMemTestProtocol fail(%r)\n", Status)); - } - - return; -} - -// -// BDS Platform Functions -// -/** - Do the platform init, can be customized by OEM/IBV - Possible things that can be done in PlatformBootManagerBeforeConsole: - Update console variable: 1. include hot-plug devices; - 2. Clear ConIn and add SOL for AMT - Register new Driver#### or Boot#### - Register new Key####: e.g.: F12 - Signal ReadyToLock event - Authentication action: 1. connect Auth devices; - 2. Identify auto logon user. -**/ -VOID -EFIAPI -PlatformBootManagerBeforeConsole ( - VOID - ) -{ - EFI_STATUS Status; - ESRT_MANAGEMENT_PROTOCOL *EsrtManagement; - - // - // Signal EndOfDxe PI Event - // - EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid); - - // - //Sync Esrt Table - // - EsrtManagement = NULL; - Status = gBS->LocateProtocol ( - &gEsrtManagementProtocolGuid, - NULL, - (VOID **)&EsrtManagement); - if (!EFI_ERROR (Status)) { - Status = EsrtManagement->SyncEsrtFmp (); - } - - // restore BootOrder variable if previous BMC boot override attempt - // left it in a modified state - RestoreBootOrder (); - - UpdateMemory (); - - // - // Locate the PCI root bridges and make the PCI bus driver connect each, - // non-recursively. This will produce a number of child handles with PciIo on - // them. - // - FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect); - - // - // Find all display class PCI devices (using the handles from the previous - // step), and connect them non-recursively. This should produce a number of - // child handles with GOPs on them. - // - FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect); - - // - // Now add the device path of all handles with GOP on them to ConOut and - // ErrOut. - // - FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput); - - // - // Add the hardcoded short-form USB keyboard device path to ConIn. - // - EfiBootManagerUpdateConsoleVariable (ConIn, - (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL); - - // - // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. - // - ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4); - CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid); - - EfiBootManagerUpdateConsoleVariable (ConIn, - (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); - EfiBootManagerUpdateConsoleVariable (ConOut, - (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); - EfiBootManagerUpdateConsoleVariable (ErrOut, - (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); - - // - // Register platform-specific boot options and keyboard shortcuts. - // - PlatformRegisterOptionsAndKeys (); -} - -STATIC -VOID -WaitForDiskReady ( - VOID - ) -{ - EFI_STATUS Status; - UINT32 Index; - PLATFORM_SAS_NOTIFY *SasNotify; - - Status = gBS->LocateProtocol ( - &gPlatformSasNotifyProtocolGuid, - NULL, - (VOID **)&SasNotify); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "Locate SasPlatformNotify:%r\n", Status)); - return; - } - - // Wait for 30 seconds at most. - for (Index = 0; Index < 30; Index++) { - Status = gBS->CheckEvent (SasNotify->WaitDiskEvent); - if (!EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "WaitDiskEvent is signaled.\n")); - EfiBootManagerConnectAll (); - break; - } - DEBUG ((DEBUG_ERROR, "%a", Index == 0 ? "Wait for disk." : ".")); - MicroSecondDelay (1000 * 1000); - } - - return; -} - -/** - Do the platform specific action after the console is ready - Possible things that can be done in PlatformBootManagerAfterConsole: - Console post action: - Dynamically switch output mode from 100x31 to 80x25 for certain senarino - Signal console ready platform customized event - Run diagnostics like memory testing - Connect certain devices - Dispatch aditional option roms - Special boot: e.g.: USB boot, enter UI -**/ -VOID -EFIAPI -PlatformBootManagerAfterConsole ( - VOID - ) -{ - EFI_STATUS Status; - ESRT_MANAGEMENT_PROTOCOL *EsrtManagement = NULL; - OEM_CONFIG_DATA SetupData; - UINTN DataSize = sizeof (OEM_CONFIG_DATA); - - // - // Show the splash screen. - // - BootLogoEnableLogo (); - - // - // Connect the rest of the devices. - // - EfiBootManagerConnectAll (); - WaitForDiskReady (); - - // - // Enumerate all possible boot options. - // - EfiBootManagerRefreshAllBootOption (); - - // - // Sync Esrt Table - // - Status = gBS->LocateProtocol ( - &gEsrtManagementProtocolGuid, - NULL, - (VOID **)&EsrtManagement); - if (!EFI_ERROR (Status)) { - Status = EsrtManagement->SyncEsrtFmp (); - } - - // - // Register UEFI Shell - // - PlatformRegisterFvBootOption ( - PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE - ); - - HandleBmcBootType (); - - //Disable POST Watch Dog before attempting boot - Status = gRT->GetVariable ( - OEM_CONFIG_NAME, - &gOemConfigGuid, - NULL, - &DataSize, - &SetupData - ); - - if (!EFI_ERROR (Status)) { - if (SetupData.BmcWdtEnable) { - Status = IpmiCmdStopWatchdogTimer (EfiBiosPost); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a:%r\n", __func__, Status)); - } - } - } -} - -/** - This function is called each second during the boot manager waits the - timeout. - - @param TimeoutRemain The remaining timeout. -**/ -VOID -EFIAPI -PlatformBootManagerWaitCallback ( - UINT16 TimeoutRemain - ) -{ - EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black; - EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White; - UINT16 Timeout; - - Print(L"\r%-2d seconds left, Press Esc or F2 to enter Setup.", TimeoutRemain); - Timeout = PcdGet16 (PcdPlatformBootTimeOut); - - Black.Raw = 0x00000000; - White.Raw = 0x00FFFFFF; - - BootLogoUpdateProgress ( - White.Pixel, - Black.Pixel, - L"Start boot option", - White.Pixel, - (Timeout - TimeoutRemain) * 100 / Timeout, - 0 - ); -} - -/** - The function is called when no boot option could be launched, - including platform recovery options and options pointing to applications - built into firmware volumes. - - If this function returns, BDS attempts to enter an infinite loop. -**/ -VOID -EFIAPI -PlatformBootManagerUnableToBoot ( - VOID - ) -{ - return; -} diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h deleted file mode 100644 index 139978719cb5c140f4869bdd49eefab57e01d982..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h +++ /dev/null @@ -1,25 +0,0 @@ -/** @file - Head file for BDS Platform specific code - - Copyright (c) 2018, ARM Ltd. All rights reserved.
- Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Ltd. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _PLATFORM_BM_H_ -#define _PLATFORM_BM_H_ - -#include -#include -#include -#include -#include -#include -#include -#include - - -#endif // _PLATFORM_BM_H_ diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf deleted file mode 100644 index 1c4b52dde0c7741ada38df367ad7e20e10e9c51f..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf +++ /dev/null @@ -1,72 +0,0 @@ -## @file -# Implementation for PlatformBootManagerLib library class interfaces. -# -# Copyright (c) 2018, ARM Ltd. All rights reserved.
-# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Ltd. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = PlatformBootManagerLib - FILE_GUID = f2a6b1de-479e-4212-859e-f014ddd27b66 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = ARM AARCH64 -# - -[Sources] - PlatformBm.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiliconNonOsi.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - BootLogoLib - BmcConfigBootLib - DebugLib - DevicePathLib - DxeServicesLib - IpmiCmdLib - MemoryAllocationLib - PcdLib - PrintLib - TimerLib - UefiBootManagerLib - UefiBootServicesTableLib - UefiLib - -[FixedPcd] - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType - gHisiTokenSpaceGuid.PcdShellFile - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut - -[Guids] - gEfiEndOfDxeEventGroupGuid - gEfiTtyTermGuid - gOemConfigGuid - -[Protocols] - gEfiGenericMemTestProtocolGuid - gEfiLoadedImageProtocolGuid - gEsrtManagementProtocolGuid - gPlatformSasNotifyProtocolGuid diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c deleted file mode 100644 index 91dc13b6d0a717ade0e44c8bf3df461feed1f741..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c +++ /dev/null @@ -1,172 +0,0 @@ -/** @file - Platform Flash Access library. - - Copyright (c) 2018, Hisilicon Limited. All rights reserved. - Copyright (c) 2018, Linaro Limited. All rights reserved. - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - -STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress; -STATIC EFI_PHYSICAL_ADDRESS mSFCMEM0BaseAddress; - -STATIC HISI_SPI_FLASH_PROTOCOL *mSpiProtocol; - -/** - Perform flash write operation with progress indicator. The start and end - completion percentage values are passed into this function. If the requested - flash write operation is broken up, then completion percentage between the - start and end values may be passed to the provided Progress function. The - caller of this function is required to call the Progress function for the - start and end completion percentage values. This allows the Progress, - StartPercentage, and EndPercentage parameters to be ignored if the requested - flash write operation can not be broken up - - @param[in] FirmwareType The type of firmware. - @param[in] FlashAddress The address of flash device to be accessed. - @param[in] FlashAddressType The type of flash device address. - @param[in] Buffer The pointer to the data buffer. - @param[in] Length The length of data buffer in bytes. - @param[in] Progress A function used report the progress of the - firmware update. This is an optional parameter - that may be NULL. - @param[in] StartPercentage The start completion percentage value that may - be used to report progress during the flash - write operation. - @param[in] EndPercentage The end completion percentage value that may - be used to report progress during the flash - write operation. - - @retval EFI_SUCCESS The operation returns successfully. - @retval EFI_WRITE_PROTECTED The flash device is read only. - @retval EFI_UNSUPPORTED The flash device access is unsupported. - @retval EFI_INVALID_PARAMETER The input parameter is not valid. -**/ -EFI_STATUS -EFIAPI -PerformFlashWriteWithProgress ( - IN PLATFORM_FIRMWARE_TYPE FirmwareType, - IN EFI_PHYSICAL_ADDRESS FlashAddress, - IN FLASH_ADDRESS_TYPE FlashAddressType, - IN VOID *Buffer, - IN UINTN Length, - IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIONAL - IN UINTN StartPercentage, - IN UINTN EndPercentage - ) -{ - UINT32 RomAddress; - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, - "PerformFlashWrite - 0x%x(%x) - 0x%x\n", - (UINTN)FlashAddress, - (UINTN)FlashAddressType, - Length)); - - if (FlashAddressType == FlashAddressTypeAbsoluteAddress) { - FlashAddress = FlashAddress - mInternalFdAddress; - } - - RomAddress = (UINT32)FlashAddress + (mInternalFdAddress - mSFCMEM0BaseAddress); - - DEBUG ((DEBUG_INFO, "Erase and Write Flash Start\n")); - - Status = mSpiProtocol->EraseWrite ( - mSpiProtocol, - (UINT32) RomAddress, - (UINT8 *)Buffer, - (UINT32) Length - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Erase and Write Status = %r \n", Status)); - } - - return Status; -} - -/** - Perform flash write operation. - - @param[in] FirmwareType The type of firmware. - @param[in] FlashAddress The address of flash device to be accessed. - @param[in] FlashAddressType The type of flash device address. - @param[in] Buffer The pointer to the data buffer. - @param[in] Length The length of data buffer in bytes. - - @retval EFI_SUCCESS The operation returns successfully. - @retval EFI_WRITE_PROTECTED The flash device is read only. - @retval EFI_UNSUPPORTED The flash device access is unsupported. - @retval EFI_INVALID_PARAMETER The input parameter is not valid. -**/ -EFI_STATUS -EFIAPI -PerformFlashWrite ( - IN PLATFORM_FIRMWARE_TYPE FirmwareType, - IN EFI_PHYSICAL_ADDRESS FlashAddress, - IN FLASH_ADDRESS_TYPE FlashAddressType, - IN VOID *Buffer, - IN UINTN Length - ) -{ - return PerformFlashWriteWithProgress ( - FirmwareType, - FlashAddress, - FlashAddressType, - Buffer, - Length, - NULL, - 0, - 0 - ); -} - -/** - Platform Flash Access Lib Constructor. - - @param[in] ImageHandle The firmware allocated handle for the EFI image. - @param[in] SystemTable A pointer to the EFI System Table. - - @retval EFI_SUCCESS Constructor returns successfully. -**/ -EFI_STATUS -EFIAPI -PerformFlashAccessLibConstructor ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - mInternalFdAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdFdBaseAddress); - - mSFCMEM0BaseAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdSFCMEM0BaseAddress); - - DEBUG ((DEBUG_INFO, - "PcdFlashAreaBaseAddress - 0x%x, PcdSFCMEM0BaseAddress - 0x%x \n", - mInternalFdAddress, - mSFCMEM0BaseAddress)); - - Status = gBS->LocateProtocol ( - &gHisiSpiFlashProtocolGuid, - NULL, - (VOID **)&mSpiProtocol); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, - "LocateProtocol gHisiSpiFlashProtocolGuid Status = %r \n", - Status)); - } - - return Status; -} diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf deleted file mode 100644 index 52811be5607d0002e4484ee524b1c4dff56b40ff..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf +++ /dev/null @@ -1,45 +0,0 @@ -## @file -# Platform Flash Access library. -# -# Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# Copyright (c) 2016, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = PlatformFlashAccessLibDxe - FILE_GUID = c230e06c-c0d8-4935-8c23-9b8f7d33d1c4 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER - CONSTRUCTOR = PerformFlashAccessLibConstructor - -[Sources] - PlatformFlashAccessLibDxe.c - -[Packages] - ArmPkg/ArmPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - SignedCapsulePkg/SignedCapsulePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - BaseMemoryLib - DebugLib - PcdLib - UefiBootServicesTableLib - -[Protocols] - gHisiSpiFlashProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdFdBaseAddress - gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress - -[Depex] - gHisiSpiFlashProtocolGuid diff --git a/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClock.h b/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClock.h deleted file mode 100644 index ac2be7ea4e9353cfb1088f38aa270863c286eab9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClock.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @file - - Copyright (c) 2020, Hisilicon Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef RX8900_REAL_TIME_CLOCK_H__ -#define RX8900_REAL_TIME_CLOCK_H__ - -#define RX8900_REGADDR_SECONDS 0x00 -#define RX8900_REGADDR_MIUTES 0x01 -#define RX8900_REGADDR_HOURS 0x02 -#define RX8900_REGADDR_DAY 0x03 -#define RX8900_REGADDR_DATE 0x04 -#define RX8900_REGADDR_MONTH 0x05 -#define RX8900_REGADDR_YEAR 0x06 -#define RX8900_REGADDR_RAM 0x07 -#define RX8900_REGADDR_ALARMMIN 0x08 -#define RX8900_REGADDR_ALARMHOUR 0x09 -#define RX8900_REGADDR_ALARMDAY 0x0A -#define RX8900_REGADDR_ALARMWEEK 0x0A -#define RX8900_REGADDR_TIMECOUNTER_0 0x0B -#define RX8900_REGADDR_TIMECOUNTER_1 0x0C -#define RX8900_REGADDR_EXTENSIONREG 0x0D -#define RX8900_REGADDR_FLAGREG 0x0E -#define RX8900_REGADDR_CONTRLREG 0xF -#define RX8900_REGADDR_BACKUP_FUN 0x18 - -#define RX8900_VDETOFF_SWOFF 0x0C -#define TEMPERATURE_COMPENSATION_2S 0x40 -#define OUTPUT_FREQUENCY_32768 0x0C -#define FLAG_REG_DEFAULT 0x00 -#define RX8900_RAM_REG_DEFAULT 0x5A - -#define EFI_TIMEOFFSET_TIMEZONE 0x5A0 - -#endif diff --git a/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClockLib.c b/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClockLib.c deleted file mode 100644 index eaaf95a1979dbf25bcb15bdc0b3b20483750d3a7..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClockLib.c +++ /dev/null @@ -1,439 +0,0 @@ -/** @file - - Copyright (c) 2020, Hisilicon Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "RX8900RealTimeClock.h" - -extern I2C_DEVICE gRtcDevice; - -STATIC BOOLEAN mRX8900Initialized = FALSE; -STATIC CONST CHAR16 mTimeZoneVariableName[] = L"RX8900RtcTimeZone"; -STATIC CONST CHAR16 mDaylightVariableName[] = L"RX8900RtcDaylight"; - -EFI_STATUS -InitializeRX8900 ( - VOID - ) -{ - EFI_STATUS Status; - unsigned char writeTemp; - - Status = SwitchRtcI2cChannelAndLock (); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - Status = I2CInit (gRtcDevice.Socket, gRtcDevice.Port, Normal); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - writeTemp = RX8900_VDETOFF_SWOFF; - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_BACKUP_FUN, 1, &writeTemp); - if (EFI_ERROR (Status)) { - goto EXIT; - } - writeTemp = TEMPERATURE_COMPENSATION_2S; - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_CONTRLREG, 1, &writeTemp); - if (EFI_ERROR (Status)) { - goto EXIT; - } - writeTemp = OUTPUT_FREQUENCY_32768; - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_EXTENSIONREG, 1, &writeTemp); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - writeTemp = FLAG_REG_DEFAULT; - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_FLAGREG, 1, &writeTemp); - if (EFI_ERROR (Status)) { - goto EXIT; - } - writeTemp = RX8900_RAM_REG_DEFAULT; - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_RAM, 1, &writeTemp); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - mRX8900Initialized = TRUE; - - EXIT: - - ReleaseOwnershipOfRtc (); - return Status; -} - -STATIC -INT16 -GetTimeZone ( - VOID - ) -{ - EFI_STATUS Status; - INT16 TimeZone; - UINTN Size; - - TimeZone = EFI_UNSPECIFIED_TIMEZONE; - Size = sizeof (TimeZone); - Status = EfiGetVariable ( - (CHAR16 *)mTimeZoneVariableName, - &gEfiCallerIdGuid, - NULL, - &Size, - (VOID *)&TimeZone - ); - - if (EFI_ERROR (Status)) { - TimeZone = EFI_UNSPECIFIED_TIMEZONE; - // The time zone variable does not exist in non-volatile storage, so create it. - Status = EfiSetVariable ( - (CHAR16 *)mTimeZoneVariableName, - &gEfiCallerIdGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, - Size, - (VOID *)&TimeZone - ); - - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "Failed to save %s variable, Status = %r\n", - mTimeZoneVariableName, Status)); - } - } else { - // Check TimeZone bounds: -1440 to 1440 or 2047 - if ((TimeZone < -EFI_TIMEOFFSET_TIMEZONE) || (TimeZone > EFI_TIMEOFFSET_TIMEZONE)) { - TimeZone = EFI_UNSPECIFIED_TIMEZONE; - } - } - - return TimeZone; -} - -STATIC -UINT8 -GetDayLight ( - VOID - ) -{ - EFI_STATUS Status; - UINT8 DayLight; - UINTN Size; - - DayLight = 0; - // Get the current daylight information from non-volatile storage - Size = sizeof (DayLight); - Status = EfiGetVariable ( - (CHAR16 *)mDaylightVariableName, - &gEfiCallerIdGuid, - NULL, - &Size, - (VOID *)&DayLight - ); - - if (EFI_ERROR (Status)) { - DayLight = 0; - // The daylight variable does not exist in non-volatile storage, so create it. - Status = EfiSetVariable ( - (CHAR16 *)mDaylightVariableName, - &gEfiCallerIdGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, - Size, - (VOID *)&DayLight - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "Failed to save %s variable, Status = %r\n", - mDaylightVariableName, Status)); - } - } - - return DayLight; -} - -EFI_STATUS -EFIAPI -LibGetTime ( - OUT EFI_TIME *Time, - OUT EFI_TIME_CAPABILITIES *Capabilities - ) -{ - EFI_STATUS Status; - UINT8 Temp[7] = {0}; - UINT16 BaseYear = 2000; - UINTN EpochSeconds; - UINT8 TryCount = 0; - - // Ensure Time is a valid pointer - if (Time == NULL) { - return EFI_INVALID_PARAMETER; - } - - // Initialize the hardware if not already done - if (!mRX8900Initialized) { - Status = InitializeRX8900 (); - if (EFI_ERROR (Status)) { - return EFI_NOT_READY; - } - } - - Status = SwitchRtcI2cChannelAndLock (); - if (EFI_ERROR (Status)) { - ReleaseOwnershipOfRtc (); - return Status; - } - - do { - Status = I2CRead (&gRtcDevice, RX8900_REGADDR_SECONDS, 7, Temp); - if (EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - goto Err; - } - - Time->Second = BcdToDecimal8 (Temp[0]); - Time->Minute = BcdToDecimal8 (Temp[1]); - Time->Hour = BcdToDecimal8 (Temp[2]); - Time->Day = BcdToDecimal8 (Temp[4]); - Time->Month = BcdToDecimal8 (Temp[5]); - Time->Year = BaseYear + BcdToDecimal8 (Temp[6]); - Time->Nanosecond = 0; - - EpochSeconds = EfiTimeToEpoch (Time); - - Time->TimeZone = GetTimeZone (); - // Adjust for the correct time zone - if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) { - EpochSeconds += Time->TimeZone * SEC_PER_MIN; - } - - Time->Daylight = GetDayLight (); - // Adjust for the correct period - if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) { - // Convert to adjusted time, i.e. spring forwards one hour - EpochSeconds += SEC_PER_HOUR; - } - - // Convert from internal 32-bit time to UEFI time - EpochToEfiTime (EpochSeconds, Time); - if ((!IsTimeValid (Time)) || ((Time->Year - BaseYear) > 99) || (Time->Year < 2000)) { - DEBUG ((DEBUG_INFO, "LibGetTime: %d-%d-%d %d-%d-%d EpochSeconds:%llx is invalid time!\n", - Time->Second, Time->Minute, Time->Hour, Time->Day, Time->Month, - Time->Year, EpochSeconds)); - Status = EFI_DEVICE_ERROR; - } - -Err: - TryCount++; - } while ((TryCount < 3) && (EFI_ERROR (Status))); - - ReleaseOwnershipOfRtc (); - return Status; -} - -STATIC -EFI_STATUS -SetTimeToRX8900 ( - IN EFI_TIME *Time - ) -{ - EFI_STATUS Status; - UINT8 Temp; - - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - Temp = DecimalToBcd8 (Time->Second); - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_SECONDS, 1, &Temp); - if(EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - return Status; - } - - Temp = DecimalToBcd8 (Time->Minute); - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_MIUTES, 1, &Temp); - if(EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - return Status; - } - - Temp = DecimalToBcd8 (Time->Hour); - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_HOURS, 1, &Temp); - if(EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - return Status; - } - - Temp = DecimalToBcd8 (Time->Day); - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_DATE, 1, &Temp); - if(EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - return Status; - } - - Temp = DecimalToBcd8 (Time->Month); - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_MONTH, 1, &Temp); - if(EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - return Status; - } - - Time->Year= Time->Year % 100; - Temp = Time->Year; - Temp = DecimalToBcd8 (Temp); - (VOID)MicroSecondDelay (RTC_DELAY_1000_MICROSECOND); - Status = I2CWrite (&gRtcDevice, RX8900_REGADDR_YEAR, 1, &Temp); - if(EFI_ERROR (Status)) { - Status = EFI_DEVICE_ERROR; - return Status; - } - - return Status; -} - -EFI_STATUS -EFIAPI -LibSetTime ( - IN EFI_TIME *Time - ) -{ - EFI_STATUS Status; - UINTN EpochSeconds; - - // Initialize the hardware if not already done - if (!mRX8900Initialized) { - Status = InitializeRX8900 (); - if (EFI_ERROR (Status)) { - goto EXIT; - } - } - - Status = SwitchRtcI2cChannelAndLock (); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - if(!IsTimeValid(Time)){ - return EFI_INVALID_PARAMETER; - } - - EpochSeconds = EfiTimeToEpoch (Time); - - // Adjust for the correct time zone, i.e. convert to UTC time zone - if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) { - EpochSeconds -= Time->TimeZone * SEC_PER_MIN; - } - - // Adjust for the correct period - if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) { - // Convert to un-adjusted time, i.e. fall back one hour - EpochSeconds -= SEC_PER_HOUR; - } - - EpochToEfiTime (EpochSeconds, Time); - Status = SetTimeToRX8900 (Time); - if (EFI_ERROR (Status)) { - goto EXIT; - } - - // Save the current time zone information into non-volatile storage - Status = EfiSetVariable ( - (CHAR16 *)mTimeZoneVariableName, - &gEfiCallerIdGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, - sizeof (Time->TimeZone), - (VOID *)&(Time->TimeZone) - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "LibSetTime: Failed to save %s variable, Status = %r\n", - mTimeZoneVariableName, Status)); - goto EXIT; - } - - // Save the current daylight information into non-volatile storage - Status = EfiSetVariable ( - (CHAR16 *)mDaylightVariableName, - &gEfiCallerIdGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, - sizeof(Time->Daylight), - (VOID *)&(Time->Daylight) - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "LibSetTime: Failed to save %s variable, Status = %r\n", - mDaylightVariableName, Status)); - goto EXIT; - } - - EXIT: - ReleaseOwnershipOfRtc (); - return Status; -} - -EFI_STATUS -EFIAPI -LibGetWakeupTime ( - OUT BOOLEAN *Enabled, - OUT BOOLEAN *Pending, - OUT EFI_TIME *Time - ) -{ - // Not a required feature - return EFI_UNSUPPORTED; -} - -EFI_STATUS -EFIAPI -LibSetWakeupTime ( - IN BOOLEAN Enabled, - OUT EFI_TIME *Time - ) -{ - // Not a required feature - return EFI_UNSUPPORTED; -} - - -EFI_STATUS -EFIAPI -LibRtcInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_TIME EfiTime; - - Status = LibGetTime (&EfiTime, NULL); - if (EFI_ERROR (Status) || (EfiTime.Year < 2000) || (EfiTime.Year > 2099) || - (!IsTimeValid (&EfiTime))) { - EfiTime.Year = 2000; - EfiTime.Month = 1; - EfiTime.Day = 1; - EfiTime.Hour = 0; - EfiTime.Minute = 0; - EfiTime.Second = 0; - EfiTime.Nanosecond = 0; - EfiTime.Daylight = 0; - EfiTime.TimeZone = EFI_UNSPECIFIED_TIMEZONE; - - Status = LibSetTime (&EfiTime); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "SetTime Status : %r\n", Status)); - } - } - - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClockLib.inf b/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClockLib.inf deleted file mode 100644 index aa07a064fd5091eebd9a299ff288ccbc786d50a9..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/RX8900RealTimeClockLib/RX8900RealTimeClockLib.inf +++ /dev/null @@ -1,33 +0,0 @@ -/** @file - - Copyright (c) 2020, Hisilicon Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = RX8900RealTimeClockLib - FILE_GUID = 55BBD010-EA76-4836-8FEA-99CBAA6664F4 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = RealTimeClockLib - -[Sources.common] - RX8900RealTimeClockLib.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - DebugLib - I2CLib - IoLib - RtcHelperLib - TimeBaseLib - TimerLib - UefiLib - UefiRuntimeLib diff --git a/Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.c b/Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.c deleted file mode 100644 index bfcbfb2bbd5e2315a272a91dbc0285da6ba8282e..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.c +++ /dev/null @@ -1,94 +0,0 @@ -/** @file - - Copyright (c) 2020, Hisilicon Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -EFI_STATUS -SwitchRtcI2cChannelAndLock ( - VOID - ) -{ - UINT8 Temp; - UINT8 Count; - - for (Count = 0; Count < 100; Count++) { - // To get the other side's state is idle first - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - if ((Temp & BIT3) != 0) { - (VOID) MicroSecondDelay (RTC_DELAY_30_MS); - // Try 100 times, if BMC has not released the bus, return preemption failed - if (Count == 99) { - if (!EfiAtRuntime ()) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Clear cpu_i2c_rtc_state 100 times fail!\n", - __func__, __LINE__)); - } - return EFI_DEVICE_ERROR; - } - continue; - } - - // if BMC free the bus, can be set 1 preemption - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp | CPU_GET_I2C_CONTROL; - // CPU occupied RTC I2C State - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - (VOID)MicroSecondDelay (RTC_DELAY_2_MICROSECOND); - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - // Is preempt success - if (CPU_GET_I2C_CONTROL == (Temp & CPU_GET_I2C_CONTROL)) { - break; - } - if (Count == 99) { - if (!EfiAtRuntime ()) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Clear cpu_i2c_rtc_state fail !!! \n", - __func__, __LINE__)); - } - return EFI_DEVICE_ERROR; - } - (VOID)MicroSecondDelay (RTC_DELAY_30_MS); - } - - //Polling BMC RTC I2C status - for (Count = 0; Count < 100; Count++) { - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - if ((Temp & BIT3) == 0) { - return EFI_SUCCESS; - } - (VOID)MicroSecondDelay (RTC_DELAY_30_MS); - } - - //If the BMC occupies the RTC I2C Channel, write back the CPU side is idle - // or the subsequent BMC will not preempt - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp & (~CPU_GET_I2C_CONTROL); - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - - return EFI_NOT_READY; -} - -VOID -ReleaseOwnershipOfRtc ( - VOID - ) -{ - UINT8 Temp; - - Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); - Temp = Temp & ~CPU_GET_I2C_CONTROL; - WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); - return ; -} diff --git a/Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.inf b/Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.inf deleted file mode 100644 index 1a36e642dfc402e571992f0a89541f901774e6b7..0000000000000000000000000000000000000000 --- a/Silicon/Hisilicon/Library/RtcHelperLib/RtcHelperLib.inf +++ /dev/null @@ -1,32 +0,0 @@ -#/** @file -# -# Copyright (c) 2020, Hisilicon Limited. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = RtcHelperLib - FILE_GUID = 5cb1a98f-2408-4fef-b68f-d5d04ff6a91f - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = RtcHelperLib - -[Sources.common] - RtcHelperLib.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - Platform/Hisilicon/D06/D06.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - CpldIoLib - DebugLib - IoLib - -[Depex] - TRUE